diff --git a/.DS_Store b/.DS_Store index f42755c..b68c1b1 100755 Binary files a/.DS_Store and b/.DS_Store differ diff --git a/.mxproject b/.mxproject old mode 100755 new mode 100644 index 1f3aad3..45d3b71 --- a/.mxproject +++ b/.mxproject @@ -1,34 +1,38 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/can.c;Core/Src/rtc.c;Core/Src/usart.c;Core/Src/stm32f1xx_it.c;Core/Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;;; +SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/can.c;Core/Src/crc.c;Core/Src/rtc.c;Core/Src/tim.c;Core/Src/usart.c;Core/Src/stm32f1xx_it.c;Core/Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Core/Src/system_stm32f1xx.c;;; HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_HAL_DRIVER;STM32F107xC;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=8 +HeaderFileListSize=10 HeaderFiles#0=../Core/Inc/gpio.h HeaderFiles#1=../Core/Inc/adc.h HeaderFiles#2=../Core/Inc/can.h -HeaderFiles#3=../Core/Inc/rtc.h -HeaderFiles#4=../Core/Inc/usart.h -HeaderFiles#5=../Core/Inc/stm32f1xx_it.h -HeaderFiles#6=../Core/Inc/stm32f1xx_hal_conf.h -HeaderFiles#7=../Core/Inc/main.h +HeaderFiles#3=../Core/Inc/crc.h +HeaderFiles#4=../Core/Inc/rtc.h +HeaderFiles#5=../Core/Inc/tim.h +HeaderFiles#6=../Core/Inc/usart.h +HeaderFiles#7=../Core/Inc/stm32f1xx_it.h +HeaderFiles#8=../Core/Inc/stm32f1xx_hal_conf.h +HeaderFiles#9=../Core/Inc/main.h HeaderFolderListSize=1 HeaderPath#0=../Core/Inc HeaderFiles=; -SourceFileListSize=8 +SourceFileListSize=10 SourceFiles#0=../Core/Src/gpio.c SourceFiles#1=../Core/Src/adc.c SourceFiles#2=../Core/Src/can.c -SourceFiles#3=../Core/Src/rtc.c -SourceFiles#4=../Core/Src/usart.c -SourceFiles#5=../Core/Src/stm32f1xx_it.c -SourceFiles#6=../Core/Src/stm32f1xx_hal_msp.c -SourceFiles#7=../Core/Src/main.c +SourceFiles#3=../Core/Src/crc.c +SourceFiles#4=../Core/Src/rtc.c +SourceFiles#5=../Core/Src/tim.c +SourceFiles#6=../Core/Src/usart.c +SourceFiles#7=../Core/Src/stm32f1xx_it.c +SourceFiles#8=../Core/Src/stm32f1xx_hal_msp.c +SourceFiles#9=../Core/Src/main.c SourceFolderListSize=1 SourcePath#0=../Core/Src SourceFiles=; diff --git a/.project b/.project old mode 100755 new mode 100644 index d1dece3..343746a --- a/.project +++ b/.project @@ -1,6 +1,6 @@ - GbTModuleSW + GbTModuleSW30Web diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..7952aa3 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,6 @@ +{ + "files.associations": { + "charger_config.h": "c", + "charger_gbt.h": "c" + } +} \ No newline at end of file diff --git a/Core/.DS_Store b/Core/.DS_Store index 27e9fde..605af8f 100755 Binary files a/Core/.DS_Store and b/Core/.DS_Store differ diff --git a/Core/Inc/.DS_Store b/Core/Inc/.DS_Store index 84d66a1..e23fe3c 100755 Binary files a/Core/Inc/.DS_Store and b/Core/Inc/.DS_Store differ diff --git a/Core/Inc/board.h b/Core/Inc/board.h index ed4562f..9884ba1 100755 --- a/Core/Inc/board.h +++ b/Core/Inc/board.h @@ -11,10 +11,16 @@ void GBT_Lock(uint8_t state); typedef enum{ - RELAY_AUX, + RELAY_AUX0 = 0, + RELAY_AUX1, + RELAY3, + RELAY_DC, + RELAY_AC, RELAY_CC, - -}relay_t; + RELAY_DC1, + // + RELAY_COUNT +} relay_t; void RELAY_Write(relay_t num, uint8_t state); void Init_Peripheral(); @@ -24,5 +30,30 @@ uint8_t SW_GetAddr(); void ADC_Select_Channel(uint32_t ch); int16_t GBT_ReadTemp(uint8_t ch); +typedef enum{ + IN_SW0 = 0, + IN_SW1, + IN0, + IN_ESTOP, + IN_FB1, + IN_CONT_FB_DC, + ISO_IN, +} inputNum_t; + +uint8_t IN_ReadInput(inputNum_t input_n); + +// Версия устройства +#define VERSION_OFFSET (0x1E4) + +typedef struct __attribute__((packed)) { + uint32_t serialNumber; // Байты 0-3: серийный номер станции (little-endian) + uint8_t stationType; // Байт 4: тип станции + uint8_t boardVersion; // Байт 5: версия платы + uint8_t addrEdcan; // Байт 6: адрес EDCAN + uint8_t reserved[57]; // Байты 7-63: зарезервированы +} InfoBlock_t; + +extern InfoBlock_t *InfoBlock; + #endif /* SRC_BOARD_H_ */ diff --git a/Core/Inc/charger_config.h b/Core/Inc/charger_config.h new file mode 100755 index 0000000..5b549a4 --- /dev/null +++ b/Core/Inc/charger_config.h @@ -0,0 +1,13 @@ +#pragma once +#include "main.h" + +#define PSU_MAX_VOLTAGE 1000 //1V/bit +#define PSU_MIN_VOLTAGE 150 //1V/bit +#define PSU_MAX_CURRENT 100 //1A/bit +#define PSU_MIN_CURRENT 1 //1A/bit +#define PSU_MAX_POWER 30000 //1W/bit + +#define PSU_NUM 1 + +#define GBT_CH_VER_MAJOR 1 +#define GBT_CH_VER_MINOR 0 \ No newline at end of file diff --git a/Core/Inc/charger_control.h b/Core/Inc/charger_control.h new file mode 100755 index 0000000..47d9a3f --- /dev/null +++ b/Core/Inc/charger_control.h @@ -0,0 +1,98 @@ +/* + * charger_control.h + * + * Created on: Jul 29, 2024 + * Author: colorbass + */ + +#ifndef INC_CHARGER_CONTROL_H_ +#define INC_CHARGER_CONTROL_H_ + +#include "main.h" + +#pragma pack(push, 1) + +// Статус +// статус подключения к автомобилю + +typedef enum __attribute__((packed)) { + Unknown, + Unplugged, + Disabled, + Preparing, + AuthRequired, + WaitingForEnergy, + ChargingPausedEV, + ChargingPausedEVSE, + Charging, + AuthTimeout, + Finished, + FinishedEVSE, + FinishedEV, + Replugging +} CONN_State_t; + +// Управление +// Разрешение на зарядку + +typedef enum __attribute__((packed)){ + CMD_NONE = 0, + CMD_STOP = 1, + CMD_START = 2, + CMD_FORCE_UNLOCK = 3, + CMD_REPLUG = 4, +} CONN_Control_t; + +typedef enum __attribute__((packed)){ + CONN_NO_ERROR = 0, + CONN_ERR_INSULATION = 1, // Утечка тока + CONN_ERR_EMERGENCY = 2, // Нажата кнопка аварийной остановки + CONN_ERR_DOOR_OPEN = 3, // Открыта дверь + CONN_ERR_LOCK = 4, // Ошибка замка + CONN_ERR_CONN_TEMP = 5, // Перегрев коннектора + CONN_ERR_AC_FAULT = 6, // Нет напряжения сети + CONN_ERR_CONTACTOR = 7, // Контактор неисправен + CONN_ERR_HOTPLUG = 8, // Коннектор неожиданно отключился + CONN_ERR_EV_COMM = 9, // Ошибка протокола связи с электромобилем + CONN_ERR_PSU_FAULT = 10, // Ошибка PSU + +}CONN_Error_t; + +typedef struct{ + CONN_Control_t connControl; //0 + CONN_State_t connState; //1 + uint8_t SOC; // State of charge [%] //2 + uint32_t Power; // Power [W] //3..6 + uint32_t Energy; // Energy [Wh] //7..10 + uint32_t RequestedPower; //1W/bit + uint16_t RequestedVoltage; //1V/bit + uint16_t RequestedCurrent; //0.1A/bit + uint16_t MeasuredVoltage; //1V/bit + uint16_t MeasuredCurrent; //0.1A/bit + uint8_t EnableOutput; + uint8_t outputEnabled; + int16_t UnmetDemand; + uint16_t WantedCurrent; //0.1A/bit + CONN_Error_t chargingError; // 0 if okay + uint8_t EvConnected; + +} ChargingConnector_t; + + +#pragma pack(pop) + +extern ChargingConnector_t CONN; + +//информация о зарядке + +//база данных с хранением инфы +//главный блок хранит в себе инфу о конфиге возможно во флеше +//либо в charger_config.h +//OCPP - универсальный блок типа + +void CONN_Init(); +void CONN_Loop(); + +void CONN_PrintChargingTotal(); + +#endif /* INC_CHARGER_CONTROL_H_ */ diff --git a/Core/Inc/charger_gbt.h b/Core/Inc/charger_gbt.h index a4e52f1..fec8399 100755 --- a/Core/Inc/charger_gbt.h +++ b/Core/Inc/charger_gbt.h @@ -7,8 +7,11 @@ #ifndef INC_CHARGER_GBT_H_ #define INC_CHARGER_GBT_H_ + #include "main.h" #include "connector.h" +#include "charger_control.h" + #define GBT_CST_NO_REASON 0x0000F0F0 // Без причины #define GBT_CST_CONDITION_REACHED 0x0100F0F0 // Заряд завершен @@ -23,6 +26,13 @@ #define GBT_CST_CURRENT_MISMATCH 0x0000F0F1 // Неправильный ток #define GBT_CST_ABNORMALVOLTAGEERROR 0x0000F0F4 // Ненормальное напряжение +typedef enum { + GBT_STOP_EVSE = 0, + GBT_STOP_EV = 1, + GBT_STOP_OCPP = 2, + +}GBT_StopSource_t; + typedef enum{ GBT_CC_UNKNOWN, @@ -40,26 +50,23 @@ typedef enum{ // GBT_S2_LOCKED = 0x12, // GBT_S3_STARTED = 0x13, // 12V AUX GBT_S31_WAIT_BHM = 0x14, // testing isolation, send CHM receive BHM - GBT_S4_ISOTEST = 0x15, // testing isolation, send CHM receive BHM - GBT_S5_BAT_INFO = 0x16, // identifying BMS, send CRM receive BRM (long) - GBT_S6_BAT_STAT = 0x17, // send CRM(AA), receive BCP (long) - GBT_S7_BMS_WAIT = 0x18, // wait for BMS, send CTS+CML receive BRO(00), next BRO(AA) - GBT_S8_INIT_CHARGER = 0x19,// starting power modules, send CRO(00) - GBT_S9_WAIT_BCL = 0x20, // waiting for BCL (requested voltage), send CRO(00) - GBT_S10_CHARGING = 0x21, // charging, contactor ON, send CCS, receiving BCL+BCS+BSM - GBT_STOP = 0x22, // normal stop - GBT_STOP_CSD = 0x23, // normal stop - GBT_ERROR = 0x24, // Error - GBT_COMPLETE = 0x25, + GBT_S4_WAIT_PSU_READY = 0x15, // wait for PSU to be ready + GBT_S4_WAIT_PSU_ON = 0x16, // PSU is on, wait for isolation test + GBT_S4_ISOTEST = 0x17, // testing isolation, send CHM receive BHM + GBT_S4_WAIT_PSU_OFF = 0x18, // PSU is off, wait for battery info + GBT_S5_BAT_INFO = 0x19, // identifying BMS, send CRM receive BRM (long) + GBT_S6_BAT_STAT = 0x1A, // send CRM(AA), receive BCP (long) + GBT_S7_BMS_WAIT = 0x1B, // wait for BMS, send CTS+CML receive BRO(00), next BRO(AA) + GBT_S8_INIT_CHARGER = 0x1C,// starting power modules, send CRO(00) + GBT_S9_WAIT_BCL = 0x1D, // waiting for BCL (requested voltage), send CRO(00) + GBT_S10_CHARGING = 0x1E, // charging, contactor ON, send CCS, receiving BCL+BCS+BSM + GBT_STOP = 0x1F, // normal stop + GBT_STOP_CSD = 0x20, // normal stop + GBT_ERROR = 0x21, // Error + GBT_COMPLETE = 0x22, }gbtState_t; -typedef enum __attribute__((packed)){ - GBT_ERR_OKAY = 0, - GBT_ERR_INSULATION = 1, - -}GBT_Error_t; - #pragma pack(push, 1) typedef struct { @@ -154,32 +161,6 @@ typedef struct { }GBT_CSD_t; -typedef struct { - uint8_t enablePSU; - uint16_t requestedVoltage; // 0.1V/bit - uint16_t requestedCurrent; // 0.1A/bit - uint8_t chargingMode; // 0x01 - CV, 0x02 - CC - uint8_t chargingPercentage; // - uint16_t chargingRemainingTimeMin; // - uint16_t chargingElapsedTimeMin; // - uint8_t chargingElapsedTimeSec; // - - CONN_State_t connectorState; - - -}GBT_EDCAN_Output_t; - -typedef struct { - uint8_t PSU_Status; - uint16_t measuredVoltage; // 0.1V/bit - uint16_t measuredCurrent; // 0.1A/bit - - CONN_Control_t chargeControl; - GBT_Error_t chargingError; // 0 if okay - -}GBT_EDCAN_Input_t; - - /* 500 - Power Supply TX * PSU_ENABLE @@ -223,10 +204,15 @@ extern uint8_t GBT_BRO; extern uint8_t GBT_Charger_Enable; +extern GBT_StopSource_t GBT_StopSource; + void GBT_Init(); void GBT_Start(); void GBT_Reset(); -void GBT_Stop(uint32_t causecode); +//void GBT_Stop(uint32_t causecode); +void GBT_StopEV(uint32_t causecode); +void GBT_StopEVSE(uint32_t causecode); +void GBT_StopOCPP(uint32_t causecode); void GBT_ForceStop(); void GBT_ChargerTask(); void GBT_Error(uint32_t errorcode); @@ -249,6 +235,4 @@ void GBT_SendCHM(); void GBT_SendCRM(uint8_t state); void GBT_SendCSD(); void GBT_SendCEM(uint32_t ErrorCode); - - #endif /* INC_CHARGER_GBT_H_ */ diff --git a/Core/Inc/connector.h b/Core/Inc/connector.h index 5d48786..716ef8c 100755 --- a/Core/Inc/connector.h +++ b/Core/Inc/connector.h @@ -10,33 +10,8 @@ #include "main.h" - - -// Статус -// статус подключения к автомобилю - -typedef enum __attribute__((packed)) { - CONN_Initializing = 1, - CONN_Faulted = 2, - CONN_Available = 3, - CONN_Preparing = 4,// to charge - CONN_Charging = 5, - CONN_Finishing = 6,//, waiting to disconnect - CONN_Suspended_EV = 7, - CONN_Suspended_EVSE = 8, - //Reserved -} CONN_State_t; - -// Управление -// Разрешение на зарядку - -typedef enum __attribute__((packed)) { - CHARGING_NOT_ALLOWED = 1, - CHARGING_ALLOWED = 2, - FORCE_UNLOCK = 3, - -} CONN_Control_t; #include "charger_gbt.h" +#include "charger_control.h" extern CONN_State_t connectorState; diff --git a/Core/Inc/crc.h b/Core/Inc/crc.h new file mode 100644 index 0000000..fd3b26e --- /dev/null +++ b/Core/Inc/crc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.h + * @brief This file contains all the function prototypes for + * the crc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern CRC_HandleTypeDef hcrc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_CRC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ + diff --git a/Core/Inc/debug.h b/Core/Inc/debug.h index 1543b68..e4aa92a 100755 --- a/Core/Inc/debug.h +++ b/Core/Inc/debug.h @@ -8,9 +8,27 @@ #ifndef SRC_DEBUG_H_ #define SRC_DEBUG_H_ -void debug_task(); -void debug_init(); -void debug_rx_interrupt(UART_HandleTypeDef *huart, uint16_t Size); +#include +#include +typedef enum { + LOG_EMERG = 1, + LOG_ALERT = 2, + LOG_CRIT = 3, + LOG_ERR = 4, + LOG_WARN = 5, + LOG_NOTICE = 6, + LOG_INFO = 7, + LOG_DEBUG = 8, +} LogLevel_t; + + +// Функции для работы с кольцевым буфером отладочных сообщений +void debug_buffer_add(const uint8_t* data, uint16_t len); +uint16_t debug_buffer_available(void); +void debug_buffer_send(void); + +// Кастомный printf с приоритетом лога +int log_printf(LogLevel_t level, const char *format, ...); #endif /* SRC_DEBUG_H_ */ diff --git a/Core/Inc/edcan_config.h b/Core/Inc/edcan_config.h deleted file mode 100755 index ebfd108..0000000 --- a/Core/Inc/edcan_config.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef EDCAN_CONFIG_H -#define EDCAN_CONFIG_H - -#define DEVICE_ID 0x20 -#define FWVER 1 - -//если используется STM32 с одним каном -//#define ED_CANx -//extern CAN_HandleTypeDef hcan; -//#define ED_CAN_INSTANCE hcan - -//если используется CAN1 на STM32 с двумя канами -//#define ED_CAN1 -//extern CAN_HandleTypeDef hcan1; -//#define ED_CAN_INSTANCE hcan1 - -//если используется CAN2 на STM32 с двумя канами -#define ED_CAN2 -extern CAN_HandleTypeDef hcan2; -#define ED_CAN_INSTANCE hcan2 - -//можно уменьшать для уменьшения объема потребляемой памяти -#define BUFFER_SIZE 256 - -#endif //EDCAN_CONFIG_H diff --git a/Core/Inc/lock.h b/Core/Inc/lock.h index 969065a..83e1be2 100755 --- a/Core/Inc/lock.h +++ b/Core/Inc/lock.h @@ -13,14 +13,21 @@ void GBT_Lock(uint8_t state); -void GBT_ManageLock(); +void GBT_ManageLockSolenoid(); +void GBT_ManageLockMotor(); uint8_t GBT_LockGetState(); void GBT_ForceLock(uint8_t state); +void GBT_ResetErrorTimeout(); typedef struct { // uint8_t state; uint8_t demand; uint8_t error; + uint8_t action_requested; // 0 = unlock, 1 = lock, 255 = no action + uint8_t motor_state; // 0 = idle, 1 = motor_on, 2 = waiting_off + uint32_t last_action_time; // время последнего изменения состояния мотора + uint8_t retry_count; // счетчик попыток + uint32_t error_tick; // время установки ошибки (для таймаута сброса) } GBT_LockState_t; extern GBT_LockState_t GBT_LockState; diff --git a/Core/Inc/main.h b/Core/Inc/main.h old mode 100755 new mode 100644 index 233c14b..5a279de --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -41,7 +41,9 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ - +#define FW_VERSION_MAJOR 0x01 +#define FW_VERSION_MINOR 0x00 +#define FW_VERSION_PATCH 0x01 /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ @@ -57,8 +59,10 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ -#define ADC_CC1_Pin GPIO_PIN_6 -#define ADC_CC1_GPIO_Port GPIOA +#define IN_SW0_Pin GPIO_PIN_1 +#define IN_SW0_GPIO_Port GPIOA +#define IN_SW1_Pin GPIO_PIN_2 +#define IN_SW1_GPIO_Port GPIOA #define LOCK_A_Pin GPIO_PIN_4 #define LOCK_A_GPIO_Port GPIOC #define LOCK_B_Pin GPIO_PIN_5 @@ -67,18 +71,36 @@ void Error_Handler(void); #define ADC_NTC1_GPIO_Port GPIOB #define ADC_NTC2_Pin GPIO_PIN_1 #define ADC_NTC2_GPIO_Port GPIOB -#define LOCK_FB_Pin GPIO_PIN_9 -#define LOCK_FB_GPIO_Port GPIOE -#define ADDR_0_Pin GPIO_PIN_10 -#define ADDR_0_GPIO_Port GPIOE -#define ADDR_1_Pin GPIO_PIN_11 -#define ADDR_1_GPIO_Port GPIOE +#define IN0_Pin GPIO_PIN_7 +#define IN0_GPIO_Port GPIOE +#define RELAY1_Pin GPIO_PIN_8 +#define RELAY1_GPIO_Port GPIOE +#define RELAY2_Pin GPIO_PIN_9 +#define RELAY2_GPIO_Port GPIOE +#define RELAY3_Pin GPIO_PIN_10 +#define RELAY3_GPIO_Port GPIOE +#define RELAY4_Pin GPIO_PIN_11 +#define RELAY4_GPIO_Port GPIOE +#define RELAY5_Pin GPIO_PIN_12 +#define RELAY5_GPIO_Port GPIOE +#define AC_OK_Pin GPIO_PIN_14 +#define AC_OK_GPIO_Port GPIOE #define RELAY_CC_Pin GPIO_PIN_15 -#define RELAY_CC_GPIO_Port GPIOE +#define RELAY_CC_GPIO_Port GPIOA +#define RELAY_DC_Pin GPIO_PIN_3 +#define RELAY_DC_GPIO_Port GPIOD #define USART2_DIR_Pin GPIO_PIN_4 #define USART2_DIR_GPIO_Port GPIOD -#define RELAY_AUX_Pin GPIO_PIN_4 -#define RELAY_AUX_GPIO_Port GPIOB +#define IN_ESTOP_Pin GPIO_PIN_7 +#define IN_ESTOP_GPIO_Port GPIOD +#define IN_FB2_Pin GPIO_PIN_3 +#define IN_FB2_GPIO_Port GPIOB +#define IN_FB1_Pin GPIO_PIN_4 +#define IN_FB1_GPIO_Port GPIOB +#define EE_WP_Pin GPIO_PIN_7 +#define EE_WP_GPIO_Port GPIOB +#define ISO_IN_Pin GPIO_PIN_1 +#define ISO_IN_GPIO_Port GPIOE /* USER CODE BEGIN Private defines */ diff --git a/Core/Inc/meter.h b/Core/Inc/meter.h new file mode 100755 index 0000000..ab283f3 --- /dev/null +++ b/Core/Inc/meter.h @@ -0,0 +1,31 @@ +/* + * psu_struct.h + * + * Created on: Jul 24, 2024 + * Author: colorbass + */ + +#ifndef INC_METER_H_ +#define INC_METER_H_ + +#include "main.h" +#include "charger_config.h" + + +typedef struct { + uint32_t meterLastTick; // Время последнего пакета Alive + uint8_t online; + uint32_t lastTick; // Время последнего вызова для каждого коннектора + uint64_t EnergyPSU_Ws; // Энергия для каждого коннектора (расчет по силовым модулям) + uint32_t AbsoluteEnergy; // Абсолютная энергия каждого счетчика (ватт*час) + uint32_t EnergyOffset; // смещение энергии по счетчикам (если 0, значит не успели захватить Offset) (ватт*час) + uint32_t EnergyOffset1; // смещение энергии по счетчикам относительно PSU + + uint8_t enable; //если 0, то счетчик обнуляется +}METER_t; + +extern METER_t METER; + +void METER_CalculateEnergy(); + +#endif /* INC_METER_H_ */ diff --git a/Core/Inc/psu_control.h b/Core/Inc/psu_control.h new file mode 100755 index 0000000..d5e28b5 --- /dev/null +++ b/Core/Inc/psu_control.h @@ -0,0 +1,196 @@ +/* + * ccs_control.h + * + * Created on: 19 авг. 2024 г. + * Author: colorbass + */ + +#ifndef INC_PSU_CONTROL_H_ +#define INC_PSU_CONTROL_H_ + +#include "main.h" +#include "charger_config.h" + +void PSU_Init(); +void PSU_Enable(uint8_t addr, uint8_t enable); +void PSU_Loop(); +void CONT_Loop(); + +// --- Состояние силового модуля (DC30, один PSU) --- + +typedef enum{ + PSU_UNREADY, // отключен, не готов к использованию + PSU_INITIALIZING, // инициализация модуля + PSU_READY, // отключен, готов к использованию + PSU_WAIT_ACK_ON, // ждём подтверждение включения модуля (напряжение выше порога) + PSU_CONT_WAIT_ACK_ON, // включаем DC-контактор и ждём подтверждение + PSU_CONNECTED, // модуль включён, DC-контактор замкнут + PSU_CURRENT_DROP, // снижение тока перед отключением + PSU_WAIT_ACK_OFF, // ждём подтверждение выключения модуля (напряжение ниже порога) + PSU_CONT_WAIT_ACK_OFF, // выключаем DC-контактор и ждём подтверждение + PSU_OFF_PAUSE, // пауза после выключения модуля +} PSU_State_t; + +/* Status0 (состояние модуля N, таблица 0 — modularForm0) */ +typedef struct{ + /* Bit0 */ uint8_t shortCircuitFault:1; /* 1: короткое замыкание на выходе */ + /* Bit1 */ uint8_t unevenFlowAlarm:1; /* 1: перекос/неравномерность распределения тока между модулями */ + /* Bit2 */ uint8_t internalCommunicationFault:1; /* 1: внутренняя ошибка связи модуля */ + /* Bit3 */ uint8_t inputBusLineFault:1; /* 1: авария по входу или по шине постоянного тока */ + /* Bit4 */ uint8_t lockProtection:1; /* 1: защита с защёлкой (латч, блокировка до сброса) */ + /* Bit5 */ uint8_t dischargeFault:1; /* 1: неисправность цепи разряда (bleeder/разрядный резистор) */ + /* Bit6 */ uint8_t eepromFault:1; /* 1: ошибка/неисправность EEPROM */ + /* Bit7 */ uint8_t rsvd_s0:1; /* зарезервировано */ +} PSU_Status0_t; + +/* Status1 (состояние модуля N, таблица 1 — modularForm1) */ +typedef struct{ + /* Bit0 */ uint8_t dcSideOffStatus:1; /* 1: отключена сторона постоянного тока (DC-выход) */ + /* Bit1 */ uint8_t moduleFaultAlarm:1; /* 1: общая авария модуля */ + /* Bit2 */ uint8_t moduleProtectionAlarm:1; /* 1: сработала защита модуля */ + /* Bit3 */ uint8_t fanFaultAlarm:1; /* 1: авария вентилятора */ + /* Bit4 */ uint8_t overTempAlarm:1; /* 1: перегрев модуля */ + /* Bit5 */ uint8_t outputOverVoltageAlarm:1; /* 1: перенапряжение на выходе */ + /* Bit6 */ uint8_t outputOverCurrentAlarm:1; /* 1: сверхток на выходе */ + /* Bit7 */ uint8_t canCommunicationInterruptAlarm:1; /* 1: нарушение связи по CAN */ +} PSU_Status1_t; + +/* Status2 (состояние модуля N, таблица 2 — modularForm2) */ +typedef struct{ + /* Bit0 */ uint8_t powerLimitStatus:1; /* 1: активен режим ограничения мощности */ + /* Bit1 */ uint8_t moduleAddressDuplicate:1; /* 1: дублирование адреса модуля */ + /* Bit2 */ uint8_t severeUnevenFlowFault:1; /* 1: сильный перекос токораспределения между модулями */ + /* Bit3 */ uint8_t threePhaseInputPhaseLossAlarm:1; /* 1: авария по пропаданию фазы трёхфазного входа */ + /* Bit4 */ uint8_t threePhaseInputUnbalanceAlarm:1; /* 1: авария по разбалансу трёхфазного входа */ + /* Bit5 */ uint8_t inputUnderVoltageAlarm:1; /* 1: пониженное напряжение на входе */ + /* Bit6 */ uint8_t inputOverVoltageAlarm:1; /* 1: повышенное напряжение на входе */ + /* Bit7 */ uint8_t pfcSideOffStatus:1; /* 1: отключена сторона PFC */ +} PSU_Status2_t; + +typedef struct { + uint8_t enableAC; // состояние AC-контактора (желание) + uint8_t enableOutput; // разрешение выхода модуля (желание) + uint16_t outputVoltage; // измеренное выходное напряжение [В] + int16_t outputCurrent; // измеренный выходной ток [0.1 А] + uint8_t temperature; // температура модуля + + PSU_State_t state; // состояние силового модуля и контакторов + + uint8_t online; // модуль в сети (есть телеметрия) + uint8_t ready; // модуль готов к работе (online && нет ошибок) + uint8_t PSU_enabled; // на выходе есть напряжение (> порога) + uint8_t CONT_enabled; // DC-контактор замкнут (по обратной связи) + uint8_t cont_fault; // внутренняя ошибка контакторов + uint8_t psu_fault; // внутренняя ошибка силового модуля + + uint32_t statetick; // время входа в состояние + + // Дополнительные параметры для одного модуля DC30 + uint32_t power_limit; // лимит мощности [кВт] + uint8_t hv_mode; // HV-режим (ограничение напряжения) + + uint32_t tempAmbient; // температура окружающего воздуха (из PSU_04) + union { uint8_t raw; PSU_Status0_t bits; } status0; // modularForm0 + union { uint8_t raw; PSU_Status1_t bits; } status1; // modularForm1 + union { uint8_t raw; PSU_Status2_t bits; } status2; // modularForm2 +} PSU_t; + +extern PSU_t PSU0; + +void PSU_Task(void); + +#pragma pack(push, 1) + +typedef struct{ + uint8_t source:8; + uint8_t destination:8; + uint8_t command:6; + uint8_t device:4; + uint8_t error:3; + +}CanId_t; + +typedef struct{ + uint8_t rsvd0[2]; + uint16_t moduleNumber; + uint8_t rsvd1[5]; +}PSU_02_t; + +typedef struct{ + uint8_t rsvd0[2]; + uint16_t moduleGroupNumber; + uint8_t moduleTemperature; + uint8_t rsvd1; + uint8_t modularForm2; + uint8_t modularForm1; + uint8_t modularForm0; +}PSU_04_t; + +typedef struct{ + uint8_t VABHi; + uint8_t VABLo; + uint8_t VBCHi; + uint8_t VBCLo; + uint8_t VCAHi; + uint8_t VCALo; + uint8_t rsvd1[2]; + + uint32_t VAB; + uint32_t VBC; + uint32_t VCA; +}PSU_06_t; + +typedef struct{ + uint32_t totalSystemVoltage; + uint32_t totalSystemCurrent; +}PSU_08_t; + +typedef struct{ + uint8_t moduleNVoltage_[4]; + uint8_t moduleNCurrent_[4]; + uint32_t moduleNVoltage; + uint32_t moduleNCurrent; +}PSU_09_t; + +// setup + +typedef struct{ + uint8_t enable; + uint8_t rsvd1[7]; +}PSU_1A_t; + +typedef struct{ + uint8_t moduleVoltage[4]; + uint8_t moduleCurrentTotal[4]; +}PSU_1B_t; + +//typedef struct{ +// uint32_t moduleVoltage; +// uint32_t moduleCurrentTotal; +//}PSU_1B_t; + +typedef struct{ + uint8_t moduleVoltage[4]; + uint8_t moduleCurrentTotal[4]; +}PSU_1C_t; + +typedef struct{ + uint8_t enable; + uint8_t rsvd1[7]; +}PSU_1D_t; + +extern PSU_02_t PSU_02; +extern PSU_04_t PSU_04; +extern PSU_06_t PSU_06; +extern PSU_08_t PSU_08; +extern PSU_09_t PSU_09; + +extern PSU_1A_t PSU_1A; +extern PSU_1B_t PSU_1B; +extern PSU_1C_t PSU_1C; + +#pragma pack(pop) + + + +#endif /* INC_PSU_CONTROL_H_ */ diff --git a/Core/Inc/rgb_controller.h b/Core/Inc/rgb_controller.h new file mode 100755 index 0000000..3bb8c9d --- /dev/null +++ b/Core/Inc/rgb_controller.h @@ -0,0 +1,53 @@ +/* + * rgb_handler.h + * + * Created on: Jul 25, 2024 + * Author: colorbass + */ + +#ifndef INC_RGB_CONTROLLER_H_ +#define INC_RGB_CONTROLLER_H_ + +#include "main.h" + +#pragma pack(push, 1) + +typedef struct{ + uint8_t R; + uint8_t G; + uint8_t B; + +}RGB_t; + +typedef struct{ + RGB_t Color1; + uint8_t Tr; //20ms/step, 5.1s max + uint8_t Th; //20ms/step, 5.1s max + uint8_t Tf; //20ms/step, 5.1s max + uint8_t Tl; //20ms/step, 5.1s max + RGB_t Color2; + //uint8_t rsvd[6]; // 6 bytes reserved +}RGB_Cycle_t; + +#pragma pack(pop) + +typedef enum{ + LED_RISING, + LED_HIGH, + LED_FALLING, + LED_LOW, +}RGB_Phase_t; + +typedef struct{ + uint8_t state; // 0 1 2 3 + uint16_t tick; + RGB_t color; + uint8_t phasesync; +}RGB_State_t; + +void LED_Task(); +void LED_Write(); +void LED_Init(); + + +#endif /* INC_RGB_CONTROLLER_H_ */ diff --git a/Core/Inc/serial_control.h b/Core/Inc/serial_control.h new file mode 100644 index 0000000..e311c15 --- /dev/null +++ b/Core/Inc/serial_control.h @@ -0,0 +1,164 @@ +#ifndef SERIALCONTROL_H +#define SERIALCONTROL_H + +#include "main.h" +#include +#include "charger_control.h" + +#define USE_WEB_INTERFACE + +// Команды от ПК к устройству +#define CMD_GET_STATUS 0x40 + +#define CMD_GET_LOG 0x50 +#define CMD_GET_LOG_CONTINUE 0x51 +#define CMD_GET_INFO 0x60 + +// Команды с аргументами +#define CMD_SET_POWER_LIMIT 0xC0 +#define CMD_TEST_PSU 0xC1 +#define CMD_CHARGE_PERMIT 0xC2 + +// Сервисные команды +#define CMD_SET_CONFIG 0xB0 + +// Перезагрузка для входа в бутлоадер +#define CMD_DEVICE_RESET 0xB5 + +// Коды ответов +#define RESP_SUCCESS 0x12 +#define RESP_FAILED 0x13 +#define RESP_INVALID 0x14 + +// Максимальный размер буфера полезной нагрузки (включая 4 байта CRC) +#define MAX_TX_BUFFER_SIZE 256 +// Максимальный размер буфера для принятого экранированного пакета без START/END +#define MAX_RX_BUFFER_SIZE 256 + +// Макросы для CRC +#define SERIAL_PROTOCOL_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define SERIAL_PROTOCOL_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) + +#define CRC32_POLYNOMIAL ((uint32_t)0xEDB88320) + +void ReadVersion(); + +// Структура для хранения принятой команды с аргументом +typedef struct { + uint8_t command; + uint8_t argument_length; + void* argument; +} ReceivedCommand_t; + +typedef struct __attribute__((packed)) { + + CONN_State_t connState; + CONN_Error_t chargingError; // Причина остановки зарядки + uint8_t SOC; // State of charge [%] + uint32_t Energy; // Energy [Wh] + uint16_t RequestedVoltage; //1V/bit + uint16_t RequestedCurrent; //0.1A/bit + uint16_t MeasuredVoltage; //1V/bit + uint16_t MeasuredCurrent; //0.1A/bit + uint8_t outputEnabled; + uint16_t chargingElapsedTimeMin; + uint8_t chargingElapsedTimeSec; + uint16_t estimatedRemainingChargingTime; + + // Flags (32 bit) + uint8_t relayAC:1; + uint8_t relayDC:1; + uint8_t relayAUX:1; + uint8_t lockState:1; + uint8_t stopButton:1; + uint8_t logAvailable:1; + uint8_t evInfoAvailable:1; + uint8_t psuOnline:1; + uint8_t rsvd1[3]; + + int8_t tempConnector0; + int8_t tempConnector1; + int8_t tempAmbient; + int8_t tempBatteryMax; + int8_t tempBatteryMin; + + uint16_t highestVoltageOfBatteryCell; + uint8_t batteryStatus; + + uint16_t phaseVoltageAB; + uint16_t phaseVoltageBC; + uint16_t phaseVoltageCA; + + char VIN[17]; + + uint8_t batteryType; //battery type + uint16_t batteryCapacity; // 0.1Ah/bit + uint16_t batteryVoltage; // 0.1V/bit + uint8_t batteryVendor[4]; // Battery vendor (ASCII string) + uint32_t batterySN; // int + uint8_t batteryManuY; // year (offset 1985) + uint8_t batteryManuM; // month + uint8_t batteryManuD; // day + uint16_t batteryCycleCount; + uint8_t ownAuto; // 0 = lizing, 1 = own auto + uint8_t EV_SW_VER[8]; + + uint8_t testMode; + uint16_t testVoltage; + uint16_t testCurrent; + +} StatusPacket_t; + +typedef struct __attribute__((packed)) { + uint16_t serialNumber; + uint8_t boardVersion; + uint8_t stationType; + uint16_t fw_version_major; + uint16_t fw_version_minor; + uint16_t fw_version_patch; +} InfoPacket_t; + +typedef struct __attribute__((packed)) { + char location[3]; + uint32_t chargerNumber; + uint32_t unixTime; + +} ConfigBlock_t; + +// Предварительное объявление структуры протокола +typedef struct SerialControl_t SerialControl_t; + +// Структура протокола +struct SerialControl_t { + // Буферы для UART + uint8_t tx_buffer[MAX_TX_BUFFER_SIZE]; + uint8_t rx_buffer[MAX_RX_BUFFER_SIZE]; + + // Переменные для передачи команды + volatile ReceivedCommand_t received_command; + volatile uint8_t command_ready; + + // Время отправки последнего пакета + volatile uint32_t tx_tick; + +}; + +// Публичные методы +void SC_Init(); +void SC_Task(); +void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code); + +// Внешняя функция обработки команд (определена в serial_handler.c) +extern void SC_CommandHandler(ReceivedCommand_t* cmd); + +extern SerialControl_t serial_control; +extern StatusPacket_t statusPacket; +extern InfoPacket_t infoPacket; + +#endif // SERIALCONTROL_H diff --git a/Core/Inc/stm32f1xx_hal_conf.h b/Core/Inc/stm32f1xx_hal_conf.h old mode 100755 new mode 100644 index b98b46d..5b1f422 --- a/Core/Inc/stm32f1xx_hal_conf.h +++ b/Core/Inc/stm32f1xx_hal_conf.h @@ -40,7 +40,7 @@ /*#define HAL_CAN_LEGACY_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */ /*#define HAL_CORTEX_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED /*#define HAL_DAC_MODULE_ENABLED */ /*#define HAL_DMA_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */ @@ -64,7 +64,7 @@ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/Core/Inc/stm32f1xx_it.h b/Core/Inc/stm32f1xx_it.h old mode 100755 new mode 100644 index afbaefe..f645893 --- a/Core/Inc/stm32f1xx_it.h +++ b/Core/Inc/stm32f1xx_it.h @@ -22,7 +22,7 @@ #define __STM32F1xx_IT_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Private includes ----------------------------------------------------------*/ @@ -56,7 +56,9 @@ void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void CAN1_RX0_IRQHandler(void); +void USART1_IRQHandler(void); void USART2_IRQHandler(void); +void USART3_IRQHandler(void); void CAN2_TX_IRQHandler(void); void CAN2_RX1_IRQHandler(void); /* USER CODE BEGIN EFP */ diff --git a/Core/Inc/tim.h b/Core/Inc/tim.h new file mode 100644 index 0000000..efce052 --- /dev/null +++ b/Core/Inc/tim.h @@ -0,0 +1,54 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim4; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM4_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h old mode 100755 new mode 100644 index 731e3b0..67e16d8 --- a/Core/Inc/usart.h +++ b/Core/Inc/usart.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -32,13 +32,22 @@ extern "C" { /* USER CODE END Includes */ +extern UART_HandleTypeDef huart5; + +extern UART_HandleTypeDef huart1; + extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart3; + /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ +void MX_UART5_Init(void); +void MX_USART1_UART_Init(void); void MX_USART2_UART_Init(void); +void MX_USART3_UART_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/Core/Src/.DS_Store b/Core/Src/.DS_Store index 6a5c29b..c5fbc9a 100755 Binary files a/Core/Src/.DS_Store and b/Core/Src/.DS_Store differ diff --git a/Core/Src/adc.c b/Core/Src/adc.c old mode 100755 new mode 100644 index 69db07a..6f6f72d --- a/Core/Src/adc.c +++ b/Core/Src/adc.c @@ -84,13 +84,13 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /**ADC1 GPIO Configuration - PA6 ------> ADC1_IN6 + PA3 ------> ADC1_IN3 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ - GPIO_InitStruct.Pin = ADC_CC1_Pin; + GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - HAL_GPIO_Init(ADC_CC1_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; @@ -114,11 +114,11 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) __HAL_RCC_ADC1_CLK_DISABLE(); /**ADC1 GPIO Configuration - PA6 ------> ADC1_IN6 + PA3 ------> ADC1_IN3 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ - HAL_GPIO_DeInit(ADC_CC1_GPIO_Port, ADC_CC1_Pin); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3); HAL_GPIO_DeInit(GPIOB, ADC_NTC1_Pin|ADC_NTC2_Pin); diff --git a/Core/Src/board.c b/Core/Src/board.c index 46fb7de..fcc75b1 100755 --- a/Core/Src/board.c +++ b/Core/Src/board.c @@ -1,11 +1,7 @@ -/* - * board.c - * - * Created on: Apr 15, 2024 - * Author: colorbass - */ + #include "main.h" #include "board.h" +#include "tim.h" extern ADC_HandleTypeDef hadc1; @@ -13,10 +9,64 @@ extern ADC_HandleTypeDef hadc1; //TEMP READ //GBT_TEMP_SENSORS -void RELAY_Write(relay_t num, uint8_t state){ - if(num==RELAY_AUX)HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, state); - if(num==RELAY_CC)HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); +InfoBlock_t *InfoBlock = (InfoBlock_t *)(VERSION_OFFSET); +uint8_t RELAY_State[RELAY_COUNT]; + +void RELAY_Write(relay_t num, uint8_t state){ + switch (num) { + case RELAY_AUX0: + HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); + break; + case RELAY_AUX1: + HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); + break; + case RELAY3: + HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); + break; + case RELAY_DC: + HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); + break; + case RELAY_AC: + HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); + break; + case RELAY_CC: + HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); + break; + case RELAY_DC1: + HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); + break; + default: + break; + } + + RELAY_State[num] = state; +} + +uint8_t RELAY_Read(relay_t num){ + return RELAY_State[num]; +} + + +uint8_t IN_ReadInput(inputNum_t input_n){ + switch(input_n){ + case IN_SW0: + return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); + case IN_SW1: + return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); + case IN0: + return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); + case IN_ESTOP: + return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); + case IN_FB1: + return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); + case IN_CONT_FB_DC: + return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); + case ISO_IN: + return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); + default: + return 0; + } } uint8_t GetBoardTemp(){ @@ -33,21 +83,21 @@ uint8_t GetBoardTemp(){ void Init_Peripheral(){ HAL_ADCEx_Calibration_Start(&hadc1); - RELAY_Write(RELAY_AUX, 0); - RELAY_Write(RELAY_CC, 1); + RELAY_Write(RELAY_AUX0, 0); + RELAY_Write(RELAY_AUX1, 0); + RELAY_Write(RELAY3, 0); + RELAY_Write(RELAY_DC, 0); + RELAY_Write(RELAY_AC, 0); + RELAY_Write(RELAY_CC, 1); + RELAY_Write(RELAY_DC1, 0); } float pt1000_to_temperature(float resistance) { // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C const float C_A = 3.9083E-3f; -// const float A = 3.9083e-03; // Коэффициент температурного изменения (°C^-1) -// const float B = -5.775e-07; // Второй коэффициент (°C^-2) -// -// // Расчет температуры по формуле -// float temperature = -A / (B - (R0 / resistance - 1) * A); - + float temperature = (resistance-R0) / ( R0 * C_A); return temperature; @@ -95,15 +145,10 @@ int16_t GBT_ReadTemp(uint8_t ch){ float temp = pt1000_to_temperature(calculate_NTC_resistance(adcValue, Vref, Vin, R)); - - return (int16_t)temp; } - - - void ADC_Select_Channel(uint32_t ch) { ADC_ChannelConfTypeDef conf = { .Channel = ch, @@ -114,21 +159,3 @@ void ADC_Select_Channel(uint32_t ch) { Error_Handler(); } } - -uint8_t SW_GetAddr(){ - if(!HAL_GPIO_ReadPin(ADDR_0_GPIO_Port, ADDR_0_Pin)){ - if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ - return 0x23; - }else{ - return 0x21; - } - - }else{ - if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ - return 0x22; - }else{ - return 0x20; - } - - } -} diff --git a/Core/Src/can.c b/Core/Src/can.c old mode 100755 new mode 100644 index cc976c9..93803fd --- a/Core/Src/can.c +++ b/Core/Src/can.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -47,7 +47,7 @@ void MX_CAN1_Init(void) hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = ENABLE; hcan1.Init.AutoWakeUp = ENABLE; - hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.AutoRetransmission = ENABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = ENABLE; if (HAL_CAN_Init(&hcan1) != HAL_OK) diff --git a/Core/Src/charger_control.c b/Core/Src/charger_control.c new file mode 100644 index 0000000..94e51f2 --- /dev/null +++ b/Core/Src/charger_control.c @@ -0,0 +1,46 @@ + +#include "charger_control.h" +#include "charger_config.h" +#include "lock.h" +#include "psu_control.h" + +ChargingConnector_t CONN; + +void CONN_Init(){ + + CONN.connControl = CMD_NONE; + CONN.connState = Unknown; + CONN.RequestedVoltage = PSU_MIN_VOLTAGE; + +} + +void CONN_Loop(){ + static CONN_State_t last_connState = Unknown; + if(last_connState != CONN.connState){ + last_connState = CONN.connState; + CONN.connControl = CMD_NONE; + } + + if(GBT_LockState.error){ + CONN.chargingError = CONN_ERR_LOCK; + } else if(PSU0.cont_fault){ + CONN.chargingError = CONN_ERR_CONTACTOR; + } else if(PSU0.psu_fault){ + CONN.chargingError = CONN_ERR_PSU_FAULT; + // } else if(!CTRL.ac_ok) { + // CONN.chargingError = CONN_ERR_AC_FAULT; + // } else + }else if (CONN.EvConnected == 0){ + CONN.chargingError = CONN_NO_ERROR; + } + + if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); + +} + +void CONN_PrintChargingTotal(){ + printf("CONN%d Charging Finished:\n", 0); +// printf("Charging Time: %d\n", CONN.chargingTime); + printf("Charging Energy: %d\n", CONN.Energy); +// printf("Charging Power: %d\n", CONN.chargingPower); +} diff --git a/Core/Src/charger_gbt.c b/Core/Src/charger_gbt.c index 4710fac..777efbf 100755 --- a/Core/Src/charger_gbt.c +++ b/Core/Src/charger_gbt.c @@ -12,10 +12,14 @@ #include "stdio.h" #include "j1939.h" #include "string.h" -#include "edcan.h" #include "lock.h" #include "connector.h" #include "soft_rtc.h" +#include "debug.h" +#include "charger_config.h" +#include "serial_control.h" +#include "lock.h" +#include "psu_control.h" uint8_t GBT_CC_GetStateRaw(); @@ -52,21 +56,36 @@ GBT_CSD_t GBT_ChargerStop; uint8_t GBT_BRO; uint32_t GBT_TimeChargingStarted; +/** Время последнего приёма любого из PGN BCL/BCS/BSM; общий таймаут в GBT_S10_CHARGING */ +uint32_t GBT_last_BCL_BCS_BSM_tick; + +#define GBT_BCL_BCS_BSM_TIMEOUT_MS 2000 uint32_t GBT_StopCauseCode; uint32_t GBT_ErrorCode; -extern GBT_EDCAN_Output_t GBT_EDCAN_Output; -extern GBT_EDCAN_Input_t GBT_EDCAN_Input; +GBT_StopSource_t GBT_StopSource; +extern ConfigBlock_t config; void GBT_Init(){ GBT_State = GBT_DISABLED; - GBT_EDCAN_Input.chargeControl = CHARGING_NOT_ALLOWED; GBT_Reset(); + + GBT_MaxLoad.maxOutputVoltage = PSU_MAX_VOLTAGE*10; // 1000V + GBT_MaxLoad.minOutputVoltage = PSU_MIN_VOLTAGE*10; //150V + GBT_MaxLoad.maxOutputCurrent = 4000 - (PSU_MAX_CURRENT*10); //100A + GBT_MaxLoad.minOutputCurrent = 4000 - (PSU_MIN_CURRENT*10); //1A + } - +void GBT_SetConfig(){ + set_Time(config.unixTime); + GBT_ChargerInfo.chargerLocation[0] = config.location[0]; + GBT_ChargerInfo.chargerLocation[1] = config.location[1]; + GBT_ChargerInfo.chargerLocation[2] = config.location[2]; + GBT_ChargerInfo.chargerNumber = config.chargerNumber; +} void GBT_ChargerTask(){ @@ -99,22 +118,26 @@ void GBT_ChargerTask(){ break; case 0x1000: //PGN BCL + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); //TODO: power block memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); - uint16_t volt=GBT_ReqPower.requestedVoltage; - GBT_EDCAN_Output.requestedVoltage = volt; - uint16_t curr=4000-GBT_ReqPower.requestedCurrent; - GBT_EDCAN_Output.requestedCurrent = curr; + + uint16_t volt = GBT_ReqPower.requestedVoltage; // 0.1V/bit + uint16_t curr = 4000 - GBT_ReqPower.requestedCurrent; // 0.1A/bit + CONN.RequestedVoltage = volt / 10; // В + CONN.WantedCurrent = curr; // 0.1A + break; case 0x1100: //PGN BCS + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); //TODO memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); - GBT_EDCAN_Output.chargingRemainingTimeMin = GBT_ChargingStatus.estimatedRemainingChargingTime; - GBT_EDCAN_Output.chargingPercentage = GBT_ChargingStatus.currentChargeState; + CONN.SOC = GBT_ChargingStatus.currentChargeState; break; case 0x1300: //PGN BSM + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); //TODO memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); break; @@ -154,48 +177,13 @@ void GBT_ChargerTask(){ //waiting }else switch (GBT_State){ case GBT_DISABLED: - RELAY_Write(RELAY_AUX, 0); - if(connectorState == CONN_Charging){ + RELAY_Write(RELAY_AUX0, 0); + RELAY_Write(RELAY_AUX1, 0); + if(connectorState == Preparing){ GBT_Reset(); GBT_Start();//TODO IF protections (maybe not needed) } break; -// case GBT_S0_UNCONNECTED: -// if(!GBT_Charger_Enable){ -// GBT_Stop(); -// break; -// } -// if(GBT_CC_GetState()==GBT_CC_4V){ -// -// GBT_SwitchState(GBT_S1_CONNECTED); -// GBT_Delay(500); -// } -// break; -// case GBT_S1_CONNECTED: -// if(!GBT_Charger_Enable){ -// GBT_Stop(); -// break; -// } -// if(GBT_CC_GetState()==GBT_CC_4V){ -// -// GBT_Lock(1); -// GBT_SwitchState(GBT_S2_LOCKED); -// GBT_Delay(500); -// }else{ -// GBT_SwitchState(GBT_S0_UNCONNECTED); -// } -// break; -// case GBT_S2_LOCKED: -// if(!GBT_Charger_Enable){ -// GBT_Stop(); -// break; -// } -// if(1){ //TODO: charge permission -// RELAY_Write(RELAY_AUX, 1); // 13.8V AUX ON -// GBT_SwitchState(GBT_S3_STARTED); -// GBT_Delay(500); -// } -// break; case GBT_S3_STARTED: GBT_SwitchState(GBT_S31_WAIT_BHM); @@ -207,36 +195,72 @@ void GBT_ChargerTask(){ GBT_Delay(250); if(GBT_BHM_recv) { - GBT_SwitchState(GBT_S4_ISOTEST); + GBT_SwitchState(GBT_S4_WAIT_PSU_READY); } //Timeout 10S if((GBT_BHM_recv == 0) && (GBT_StateTick()>10000)) { //BHM Timeout GBT_Error(0xFCF0C0FC); - EDCAN_printf(LOG_WARN, "BHM Timeout\n"); + CONN.chargingError = CONN_ERR_EV_COMM; + log_printf(LOG_ERR, "BHM Timeout\n"); + } + break; + case GBT_S4_WAIT_PSU_READY: + if(j_rx.state == 0) GBT_SendCHM(); + GBT_Delay(250); + if(PSU0.ready){ + GBT_SwitchState(GBT_S4_WAIT_PSU_ON); + } + if(GBT_StateTick()>10000){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_PSU_FAULT; + log_printf(LOG_ERR, "PSU ready timeout, stopping...\n"); + break; + } + break; + + case GBT_S4_WAIT_PSU_ON: + if(j_rx.state == 0) GBT_SendCHM(); + GBT_Delay(250); + CONN.RequestedVoltage = GBT_MaxVoltage.maxOutputVoltage / 10; // 0.1V -> V + CONN.WantedCurrent = 10; // 1A max (0.1A units) + CONN.EnableOutput = 1; + if(PSU0.state == PSU_CONNECTED){ + GBT_SwitchState(GBT_S4_ISOTEST); + } + if(GBT_StateTick()>10000){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_PSU_FAULT; + log_printf(LOG_ERR, "PSU on timeout, stopping...\n"); + break; } break; case GBT_S4_ISOTEST: if(j_rx.state == 0) GBT_SendCHM(); GBT_Delay(250); - - GBT_EDCAN_Output.requestedVoltage = GBT_MaxVoltage.maxOutputVoltage; - GBT_EDCAN_Output.requestedCurrent = 10; // 1A max - GBT_EDCAN_Output.enablePSU = 1; - //TODO: Isolation test trigger - if(GBT_EDCAN_Input.chargingError == GBT_ERR_INSULATION){ - GBT_Stop(GBT_CST_OTHERFALUT); + if(CONN.chargingError != CONN_NO_ERROR){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); } - if(GBT_StateTick()>5000){ - GBT_SwitchState(GBT_S5_BAT_INFO); - GBT_EDCAN_Output.requestedVoltage = 50; - GBT_EDCAN_Output.requestedCurrent = 10; // 1A max - GBT_EDCAN_Output.enablePSU = 0; + GBT_SwitchState(GBT_S4_WAIT_PSU_OFF); } + break; + case GBT_S4_WAIT_PSU_OFF: + CONN.RequestedVoltage = 0; + CONN.WantedCurrent = 0; + CONN.EnableOutput = 0; + if(GBT_StateTick()>5000){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_PSU_FAULT; + log_printf(LOG_ERR, "PSU off timeout, stopping...\n"); + break; + } + if(PSU0.PSU_enabled == 0){ + GBT_SwitchState(GBT_S5_BAT_INFO); + } break; case GBT_S5_BAT_INFO: @@ -245,24 +269,25 @@ void GBT_ChargerTask(){ if(GBT_BAT_INFO_recv){ //BRM //Got battery info GBT_SwitchState(GBT_S6_BAT_STAT); - EDCAN_printf(LOG_INFO, "EV info:\n"); - EDCAN_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); - EDCAN_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); - EDCAN_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit - EDCAN_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit - EDCAN_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) - EDCAN_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int - EDCAN_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) - EDCAN_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t - EDCAN_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto - EDCAN_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN - EDCAN_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); + log_printf(LOG_INFO, "EV info:\n"); + log_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); + log_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); + log_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit + log_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit + log_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) + log_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int + log_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) + log_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t + log_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto + log_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN + log_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); } //Timeout if((GBT_StateTick()>5000) && (GBT_BAT_INFO_recv == 0)){ + CONN.chargingError = CONN_ERR_EV_COMM; GBT_Error(0xFDF0C0FC); //BRM Timeout - EDCAN_printf(LOG_WARN, "BRM Timeout\n"); + log_printf(LOG_ERR, "BRM Timeout\n"); } break; @@ -272,19 +297,20 @@ void GBT_ChargerTask(){ if(GBT_BAT_STAT_recv){ //Got battery status GBT_SwitchState(GBT_S7_BMS_WAIT); - EDCAN_printf(LOG_INFO, "Battery info:\n"); - EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit - EDCAN_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit - EDCAN_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh - EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit - EDCAN_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset - EDCAN_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% - EDCAN_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit + log_printf(LOG_INFO, "Battery info:\n"); + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit + log_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit + log_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit + log_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset + log_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% + log_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit } if((GBT_StateTick()>5000) && (GBT_BAT_STAT_recv == 0)){ + CONN.chargingError = CONN_ERR_EV_COMM; GBT_Error(0xFCF1C0FC); //BCP Timeout - EDCAN_printf(LOG_WARN, "BCP Timeout\n"); + log_printf(LOG_ERR, "BCP Timeout\n"); } break; @@ -294,16 +320,18 @@ void GBT_ChargerTask(){ if(j_rx.state == 0) GBT_SendCML(); GBT_Delay(250); if((GBT_StateTick()>5000) && (GBT_BRO_recv == 0)){ + CONN.chargingError = CONN_ERR_EV_COMM; GBT_Error(0xFCF4C0FC); //BRO Timeout - EDCAN_printf(LOG_WARN, "BRO Timeout\n"); + log_printf(LOG_ERR, "BRO Timeout\n"); } if(EV_ready){ //EV ready (AA) GBT_SwitchState(GBT_S8_INIT_CHARGER); }else{ if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ + CONN.chargingError = CONN_ERR_EV_COMM; GBT_Error(0xFCF4C0FC); //BRO Timeout - EDCAN_printf(LOG_WARN, "BRO Timeout\n"); + log_printf(LOG_ERR, "EV not ready for a 60s\n"); } } break; @@ -312,10 +340,16 @@ void GBT_ChargerTask(){ if(j_rx.state == 0) GBT_SendCRO(0x00); //TODO GBT_Delay(250); - if(GBT_StateTick()>1500){ + // if(GBT_StateTick()>1500){ + if(PSU0.ready){ //Power Modules initiated GBT_SwitchState(GBT_S9_WAIT_BCL); } + if((GBT_StateTick()>6000) && (PSU0.ready == 0)){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_PSU_FAULT; + log_printf(LOG_ERR, "PSU not ready, stopping...\n"); + } break; case GBT_S9_WAIT_BCL: @@ -325,14 +359,15 @@ void GBT_ChargerTask(){ //BCL power requirements received GBT_SwitchState(GBT_S10_CHARGING); - CONN_SetState(CONN_Charging); - uint16_t curr=4000-GBT_ReqPower.requestedCurrent; - uint16_t volt=GBT_ReqPower.requestedVoltage; - //TODO Limits + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + CONN_SetState(Charging); - GBT_EDCAN_Output.requestedVoltage = volt; - GBT_EDCAN_Output.requestedCurrent = curr; - GBT_EDCAN_Output.enablePSU = 1; + uint16_t curr = 4000 - GBT_ReqPower.requestedCurrent; + uint16_t volt = GBT_ReqPower.requestedVoltage; + //TODO Limits + CONN.RequestedVoltage = volt / 10; // В + CONN.WantedCurrent = curr; // 0.1A + CONN.EnableOutput = 1; GBT_TimeChargingStarted = get_Current_Time(); } @@ -340,46 +375,65 @@ void GBT_ChargerTask(){ case GBT_S10_CHARGING: //CHARGING - //TODO BCL BCS BSM missing ERRORS - if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); - if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY);//GBT_ForceStop(); - if(GBT_LockState.error) GBT_Stop(GBT_CST_OTHERFALUT); - if((GBT_ReadTemp(0) > 90) || (GBT_ReadTemp(1) > 90)) { - GBT_Stop(GBT_CST_CONNECTOR_OVER_TEMP); - EDCAN_printf(LOG_WARN, "Connector overheat %d %d\n", GBT_ReadTemp(0), GBT_ReadTemp(1)); + if((HAL_GetTick() - GBT_last_BCL_BCS_BSM_tick) > GBT_BCL_BCS_BSM_TIMEOUT_MS){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_EV_COMM; + log_printf(LOG_WARN, "BCL/BCS/BSM timeout, stopping...\n"); + break; } - if(GBT_EDCAN_Input.chargingError == GBT_ERR_INSULATION) { - GBT_Stop(GBT_CST_OTHERFALUT); - EDCAN_printf(LOG_WARN, "Isolation error\n"); + if(CONN.connControl == CMD_STOP) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); // --> Finished + if(GBT_LockState.error) { + GBT_StopEVSE(GBT_CST_OTHERFALUT); // --> Suspend EVSE + CONN.chargingError = CONN_ERR_LOCK; + log_printf(LOG_WARN, "Lock error, stopping...\n"); + break; + } + if(CONN_CC_GetState()!=GBT_CC_4V){ + GBT_StopEVSE(GBT_CST_OTHERFALUT); + CONN.chargingError = CONN_ERR_HOTPLUG; + log_printf(LOG_WARN, "Hotplug detected, stopping...\n"); + break; + } + if((GBT_ReadTemp(0) > 90) || (GBT_ReadTemp(1) > 90)) { + GBT_StopEVSE(GBT_CST_CONNECTOR_OVER_TEMP); + CONN.chargingError = CONN_ERR_CONN_TEMP; + log_printf(LOG_WARN, "Connector overheat %d %d, stopping...\n", GBT_ReadTemp(0), GBT_ReadTemp(1)); + break; + } + if(CONN.chargingError != CONN_NO_ERROR){ // --> Suspend EVSE + GBT_StopEVSE(GBT_CST_OTHERFALUT); +// log_printf(LOG_WARN, "Isolation error\n"); } //GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111100;//NOT PERMITTED GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111101; GBT_ChargerCurrentStatus.chargingTime = (get_Current_Time() - GBT_TimeChargingStarted)/60; -// GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Output.requestedCurrent; -// GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Output.requestedVoltage; - GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Input.measuredCurrent; - GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Input.measuredVoltage; - GBT_EDCAN_Output.chargingElapsedTimeMin = (get_Current_Time() - GBT_TimeChargingStarted)/60; - GBT_EDCAN_Output.chargingElapsedTimeSec = (get_Current_Time() - GBT_TimeChargingStarted)%60; + GBT_ChargerCurrentStatus.outputCurrent = 4000 - CONN.MeasuredCurrent; // 0.1A + GBT_ChargerCurrentStatus.outputVoltage = CONN.MeasuredVoltage * 10; // V -> 0.1V - if(j_rx.state == 0) GBT_SendCCS(); + if(j_rx.state == 0) { + GBT_SendCCS(); + GBT_Delay(49); + }else{ + GBT_Delay(10); // Resend packet if not sent - GBT_Delay(50); + } + + //TODO: снижение тока если перегрев контактов break; case GBT_STOP: GBT_Delay(10); - GBT_EDCAN_Output.enablePSU = 0; + CONN.EnableOutput = 0; GBT_SendCST(GBT_StopCauseCode); //RELAY_Write(RELAY_OUTPUT, 0); //GBT_SwitchState(GBT_DISABLED); if(GBT_StateTick()>10000){ - EDCAN_printf(LOG_WARN, "BSD Timeout\n"); + log_printf(LOG_ERR, "BSD Timeout\n"); GBT_Error(0xFCF0C0FD); //BSD Timeout - } if(GBT_BSD_recv != 0){ @@ -392,10 +446,7 @@ void GBT_ChargerTask(){ GBT_SendCSD(); if(GBT_StateTick()>2500){ //2.5S GBT_SwitchState(GBT_COMPLETE); -// GBT_Reset(); - //CONN_SetState(CONN_Occupied_complete); - //if(connectorState == CONN_Occupied_charging) - //PSU_Mode(0x0100); + } break; @@ -403,59 +454,44 @@ void GBT_ChargerTask(){ case GBT_ERROR: GBT_SendCEM(GBT_ErrorCode); //2.5S GBT_SwitchState(GBT_COMPLETE); -// GBT_Reset(); - // + break; case GBT_COMPLETE: - if(connectorState != CONN_Finishing) GBT_SwitchState(GBT_DISABLED); + if(connectorState != Finished) { + GBT_SwitchState(GBT_DISABLED); + GBT_Reset();//CHECK + } break; default: GBT_SwitchState(GBT_DISABLED); } + if (CONN_CC_GetState()==GBT_CC_4V) CONN.EvConnected = 1; + else CONN.EvConnected = 0; } void GBT_SwitchState(gbtState_t state){ GBT_State = state; - ED_status = state; GBT_state_tick = HAL_GetTick(); - if(GBT_State == GBT_DISABLED) printf ("GBT_DISABLED\n"); -// if(GBT_State == GBT_S0_UNCONNECTED) printf ("GBT_S0_UNCONNECTED\n"); -// if(GBT_State == GBT_S1_CONNECTED) printf ("GBT_S1_CONNECTED\n"); -// if(GBT_State == GBT_S2_LOCKED) printf ("GBT_S2_LOCKED\n"); - if(GBT_State == GBT_S3_STARTED) printf ("GBT_S3_STARTED\n"); - if(GBT_State == GBT_S31_WAIT_BHM) printf ("GBT_S31_WAIT_BHM\n"); - if(GBT_State == GBT_S4_ISOTEST) printf ("GBT_S4_ISOTEST\n"); - if(GBT_State == GBT_S5_BAT_INFO) printf ("GBT_S5_BAT_INFO\n"); - if(GBT_State == GBT_S6_BAT_STAT) printf ("GBT_S6_BAT_STAT\n"); - if(GBT_State == GBT_S7_BMS_WAIT) printf ("GBT_S7_BMS_WAIT\n"); - if(GBT_State == GBT_S8_INIT_CHARGER)printf ("GBT_S8_INIT_CHARGER\n"); - if(GBT_State == GBT_S9_WAIT_BCL) printf ("GBT_S9_WAIT_BCL\n"); - if(GBT_State == GBT_S10_CHARGING) printf ("GBT_S10_CHARGING\n"); - if(GBT_State == GBT_STOP) printf ("GBT_STOP\n"); - if(GBT_State == GBT_STOP_CSD) printf ("GBT_STOP_CSD\n"); - if(GBT_State == GBT_ERROR) printf ("GBT_ERROR\n"); - if(GBT_State == GBT_COMPLETE) printf ("GBT_COMPLETE\n"); - - if(GBT_State == GBT_DISABLED) EDCAN_printf(LOG_INFO, "GBT_DISABLED\n"); - if(GBT_State == GBT_S3_STARTED) EDCAN_printf(LOG_INFO, "GBT_S3_STARTED\n"); - if(GBT_State == GBT_S31_WAIT_BHM) EDCAN_printf(LOG_INFO, "GBT_S31_WAIT_BHM\n"); - if(GBT_State == GBT_S4_ISOTEST) EDCAN_printf(LOG_INFO, "GBT_S4_ISOTEST\n"); - if(GBT_State == GBT_S5_BAT_INFO) EDCAN_printf(LOG_INFO, "GBT_S5_BAT_INFO\n"); - if(GBT_State == GBT_S6_BAT_STAT) EDCAN_printf(LOG_INFO, "GBT_S6_BAT_STAT\n"); - if(GBT_State == GBT_S7_BMS_WAIT) EDCAN_printf(LOG_INFO, "GBT_S7_BMS_WAIT\n"); - if(GBT_State == GBT_S8_INIT_CHARGER)EDCAN_printf(LOG_INFO, "GBT_S8_INIT_CHARGER\n"); - if(GBT_State == GBT_S9_WAIT_BCL) EDCAN_printf(LOG_INFO, "GBT_S9_WAIT_BCL\n"); - if(GBT_State == GBT_S10_CHARGING) EDCAN_printf(LOG_INFO, "GBT_S10_CHARGING\n"); - if(GBT_State == GBT_STOP) EDCAN_printf(LOG_INFO, "GBT_STOP\n"); - if(GBT_State == GBT_STOP_CSD) EDCAN_printf(LOG_INFO, "GBT_STOP_CSD\n"); - if(GBT_State == GBT_ERROR) EDCAN_printf(LOG_WARN, "GBT_ERROR\n"); - if(GBT_State == GBT_COMPLETE) EDCAN_printf(LOG_INFO, "GBT_COMPLETE\n"); - + if(GBT_State == GBT_DISABLED) log_printf(LOG_INFO, "Disabled\n"); + if(GBT_State == GBT_S3_STARTED) log_printf(LOG_INFO, "Charging started\n"); + if(GBT_State == GBT_S31_WAIT_BHM) log_printf(LOG_INFO, "Waiting for BHM\n"); + if(GBT_State == GBT_S4_WAIT_PSU_READY) log_printf(LOG_INFO, "Waiting for PSU ready\n"); + if(GBT_State == GBT_S4_ISOTEST) log_printf(LOG_INFO, "Isolation test\n"); + if(GBT_State == GBT_S5_BAT_INFO) log_printf(LOG_INFO, "Waiting for battery info\n"); + if(GBT_State == GBT_S6_BAT_STAT) log_printf(LOG_INFO, "Waiting for battery status\n"); + if(GBT_State == GBT_S7_BMS_WAIT) log_printf(LOG_INFO, "Waiting for BMS\n"); + if(GBT_State == GBT_S8_INIT_CHARGER)log_printf(LOG_INFO, "Initializing charger\n"); + if(GBT_State == GBT_S9_WAIT_BCL) log_printf(LOG_INFO, "Waiting for BCL\n"); + if(GBT_State == GBT_S10_CHARGING) log_printf(LOG_INFO, "Charging in progress\n"); + if(GBT_State == GBT_STOP) log_printf(LOG_INFO, "Charging Stopped\n"); + if(GBT_State == GBT_STOP_CSD) log_printf(LOG_INFO, "Charging Stopped with CSD\n"); + if(GBT_State == GBT_ERROR) log_printf(LOG_INFO, "Charging Error\n"); + if(GBT_State == GBT_COMPLETE) log_printf(LOG_INFO, "Charging Finished\n"); } uint32_t GBT_StateTick(){ @@ -467,31 +503,57 @@ void GBT_Delay(uint32_t delay){ GBT_delay = delay; } -void GBT_Stop(uint32_t causecode){ +void GBT_StopEV(uint32_t causecode){ // --> Suspend EV + if (CONN.chargingError){ + GBT_StopSource = GBT_STOP_EVSE; + }else{ + GBT_StopSource = GBT_STOP_EV; + } GBT_StopCauseCode = causecode; if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); } -void GBT_Error(uint32_t errorcode){ - EDCAN_printf(LOG_WARN, "GBT Error code: 0x%X\n", errorcode); +void GBT_StopEVSE(uint32_t causecode){ // --> Suspend EVSE + GBT_StopSource = GBT_STOP_EVSE; + GBT_StopCauseCode = causecode; + if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); +} + +void GBT_StopOCPP(uint32_t causecode){ // --> Finished + GBT_StopSource = GBT_STOP_OCPP; + GBT_StopCauseCode = causecode; + if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); +} + +void GBT_ForceStop(){ // --> Suspend EV + GBT_StopSource = GBT_STOP_EV; + CONN.EnableOutput = 0; + GBT_SwitchState(GBT_COMPLETE); + GBT_Lock(0); + RELAY_Write(RELAY_AUX0, 0); + RELAY_Write(RELAY_AUX1, 0); +} + +void GBT_Error(uint32_t errorcode){ // --> Suspend EV + GBT_StopSource = GBT_STOP_EV; + log_printf(LOG_ERR, "GBT Error code: 0x%X\n", errorcode); GBT_ErrorCode = errorcode; GBT_SwitchState(GBT_ERROR); } -void GBT_ForceStop(){ - GBT_EDCAN_Output.enablePSU = 0; - GBT_SwitchState(GBT_COMPLETE); - GBT_Lock(0); - RELAY_Write(RELAY_AUX, 0); -} void GBT_Reset(){ + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); GBT_BAT_INFO_recv = 0; GBT_BAT_STAT_recv = 0; GBT_BRO_recv = 0; GBT_BHM_recv = 0; GBT_BSD_recv = 0; EV_ready = 0; + CONN.SOC = 0; + CONN.EnableOutput = 0; + CONN.WantedCurrent = 0; + CONN.RequestedVoltage = 0; memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); @@ -505,8 +567,11 @@ void GBT_Reset(){ GBT_CurrPower.requestedVoltage = 500; //50V GBT_TimeChargingStarted = 0; GBT_BRO = 0x00; + GBT_LockResetError(); } void GBT_Start(){ - RELAY_Write(RELAY_AUX, 1); + RELAY_Write(RELAY_AUX0, 1); + RELAY_Write(RELAY_AUX1, 1); + GBT_SwitchState(GBT_S3_STARTED); } diff --git a/Core/Src/connector.c b/Core/Src/connector.c index 51e8736..681a933 100755 --- a/Core/Src/connector.c +++ b/Core/Src/connector.c @@ -7,107 +7,148 @@ #include "connector.h" #include "lock.h" #include "board.h" +#include "debug.h" CONN_State_t connectorState; -extern GBT_EDCAN_Output_t GBT_EDCAN_Output; -extern GBT_EDCAN_Input_t GBT_EDCAN_Input; -uint8_t CC_STATE_FILTERED; +extern uint8_t config_initialized; -void CONN_Init(){ - CONN_SetState(CONN_Initializing); -} +gbtCcState_t CC_STATE_FILTERED; void CONN_Task(){ switch (connectorState){ - case CONN_Initializing: // unlocked + case Unknown: // unlocked, waiting for config GBT_Lock(0); - CONN_SetState(CONN_Available); - GBT_LockState.error = 0; - break; - case CONN_Faulted: //unlocked - GBT_Lock(0); - - break; - case CONN_Available: //unlocked, waiting to connect - GBT_Lock(0); - GBT_LockState.error = 0; - if((CONN_CC_GetState()==GBT_CC_4V) && (GBT_EDCAN_Input.chargeControl != FORCE_UNLOCK)){ // Исправить - CONN_SetState(CONN_Preparing); - GBT_Lock(1); - + if (config_initialized) { + CONN_SetState(Unplugged); } break; - // Выйти из двух состояний в Finished если force unlock - case CONN_Preparing: //locked, waiting to charge - GBT_Lock(1); + case Disabled: // faulted, unlocked + GBT_Lock(0); + if(CONN.chargingError == 0) CONN_SetState(Unplugged); + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + break; + + case Unplugged: // unlocked, waiting to connect + GBT_Lock(0); + if(CONN.chargingError != 0) CONN_SetState(Disabled); + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + + if((CONN_CC_GetState()==GBT_CC_4V) && (CONN.connControl != CMD_FORCE_UNLOCK)){ + CONN_SetState(AuthRequired); + GBT_Lock(0); + } + break; + + case AuthRequired: // plugged, waiting to start charge + GBT_Lock(0); + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); if(CONN_CC_GetState()==GBT_CC_4V){ - if(GBT_EDCAN_Input.chargeControl == CHARGING_ALLOWED){ -// RELAY_Write(RELAY_AUX, 1); -// GBT_Start(); - CONN_SetState(CONN_Charging); + if(CONN.connControl == CMD_START){ + CONN_SetState(Preparing); } - if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK){ - CONN_SetState(CONN_Available);//TODO: CONN_Occupied_complete + if(CONN.connControl == CMD_FORCE_UNLOCK){ + CONN_SetState(Unplugged); } - //if (CHARGING_NOT_ALLOWED) stay here + // if CHARGING_NOT_ALLOWED — stay here }else{ - CONN_SetState(CONN_Available); + CONN_SetState(Unplugged); } break; - case CONN_Charging://charging, locked + + case Preparing: // charging, locked GBT_Lock(1); if(GBT_State == GBT_COMPLETE){ - CONN_SetState(CONN_Finishing); + if(GBT_StopSource == GBT_STOP_EVSE){ + CONN_SetState(FinishedEVSE); + }else if(GBT_StopSource == GBT_STOP_EV){ + CONN_SetState(FinishedEV); + }else if(GBT_StopSource == GBT_STOP_OCPP){ + CONN_SetState(Finished); + }else{ + CONN_SetState(FinishedEVSE); + } + } + if(GBT_State == GBT_S10_CHARGING){ + CONN_SetState(Charging); } - // - break; - case CONN_Finishing://charging completed, waiting to disconnect, unlocked + case Charging: // charging, locked + GBT_Lock(1); + + if(GBT_State == GBT_COMPLETE){ + if(GBT_StopSource == GBT_STOP_EVSE){ + CONN_SetState(FinishedEVSE); + }else if(GBT_StopSource == GBT_STOP_EV){ + CONN_SetState(FinishedEV); + }else if(GBT_StopSource == GBT_STOP_OCPP){ + CONN_SetState(Finished); + }else{ + CONN_SetState(FinishedEVSE); + } + } + break; + + case FinishedEV: // charging completed by EV, waiting to transaction stop GBT_Lock(0); -// RELAY_Write(RELAY_AUX, 0); - //TODO: Reconnection -// if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED){ -// CONN_SetState(CONN_Initializing); -// } - if(CONN_CC_GetState()==GBT_CC_6V){ - CONN_SetState(CONN_Initializing); - } - //Проблема, если нажать кнопку и не вынуть пистолет, то он снова блочится + CONN_SetState(Finished); break; + + case FinishedEVSE: // charging completed by EVSE, waiting to transaction stop + GBT_Lock(0); + CONN_SetState(Finished); + break; + + case Finished: // charging completed, waiting to disconnect, unlocked + GBT_Lock(0); + + //TODO Force unlock time limit + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + + if(CONN_CC_GetState()==GBT_CC_6V){ + GBT_Lock(0); + CONN_SetState(Unplugged); + } + break; + default: - CONN_SetState(CONN_Initializing); - + CONN_SetState(Unknown); } - } //external -//CONN_SetState(CONN_Error); -//CONN_SetState(CONN_Occupied_charging); -//CONN_SetState(CONN_Occupied_Complete); +//CONN_SetState(Disabled); void CONN_SetState(CONN_State_t state){ connectorState = state; - if(connectorState == CONN_Initializing) printf ("CONN_Initializing\n"); - if(connectorState == CONN_Faulted) printf ("CONN_Error\n"); - if(connectorState == CONN_Available) printf ("CONN_Available\n"); - if(connectorState == CONN_Preparing) printf ("CONN_Occupied_waiting\n"); - if(connectorState == CONN_Charging) printf ("CONN_Occupied_charging\n"); - if(connectorState == CONN_Finishing) printf ("CONN_Occupied_complete\n"); - GBT_EDCAN_Output.connectorState = state; + + if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); + if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); + if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); + if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); + if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); + if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); + if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); + if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); + if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); + if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); + if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); + if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); + if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); + if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); + + CONN.connState = state; } void CONN_CC_ReadStateFiltered() { - static uint32_t last_change_time; - static uint32_t last_check_time; - static uint8_t prev_state; + static uint32_t last_change_time = 0; + static uint32_t last_check_time = 0; + static uint8_t prev_state = 0; -// if((last_check_time+100)>HAL_GetTick()) return; if((HAL_GetTick()-last_check_time)<100) return; last_check_time = HAL_GetTick(); @@ -120,64 +161,13 @@ void CONN_CC_ReadStateFiltered() { } else if ((HAL_GetTick() - last_change_time) >= 300) { CC_STATE_FILTERED = prev_state; } - -// switch(new_state){ -// case GBT_CC_UNKNOWN: -// printf("GBT_CC_UNKNOWN\n"); -// break; -// case GBT_CC_12V: -// printf("GBT_CC_12V\n"); -// break; -// case GBT_CC_6V: -// printf("GBT_CC_6V\n"); -// break; -// case GBT_CC_4V: -// printf("GBT_CC_4V\n"); -// break; -// case GBT_CC_2V: -// printf("GBT_CC_2V\n"); -// break; -// -// } -// switch(CONN_CC_GetState()){ -// case GBT_CC_UNKNOWN: -// printf("FGBT_CC_UNKNOWN\n"); -// break; -// case GBT_CC_12V: -// printf("FGBT_CC_12V\n"); -// break; -// case GBT_CC_6V: -// printf("FGBT_CC_6V\n"); -// break; -// case GBT_CC_4V: -// printf("FGBT_CC_4V\n"); -// break; -// case GBT_CC_2V: -// printf("FGBT_CC_2V\n"); -// break; -// -// } } uint8_t CONN_CC_GetState(){ return CC_STATE_FILTERED; } uint8_t CONN_CC_GetStateRaw(){ - //Vref=3.3v = 4095 - //k=1/11 - //Vin = 12v - //Vin*k= 1.09v - //12vin = 1353 ADC -//TODO: Filter 100ms - uint32_t adc; - float volt; - ADC_Select_Channel(ADC_CHANNEL_6); - HAL_ADC_Start(&hadc1); - HAL_ADC_PollForConversion(&hadc1, 100); - adc = HAL_ADC_GetValue(&hadc1); - HAL_ADC_Stop(&hadc1); - - volt = (float)adc/113.4f; + float volt = CONN_CC_GetAdc(); // if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; // if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; // if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; @@ -199,7 +189,7 @@ float CONN_CC_GetAdc(){ uint32_t adc; float volt; - ADC_Select_Channel(ADC_CHANNEL_6); + ADC_Select_Channel(ADC_CHANNEL_3); HAL_ADC_Start(&hadc1); HAL_ADC_PollForConversion(&hadc1, 100); adc = HAL_ADC_GetValue(&hadc1); diff --git a/Core/Src/crc.c b/Core/Src/crc.c new file mode 100644 index 0000000..6001d12 --- /dev/null +++ b/Core/Src/crc.c @@ -0,0 +1,85 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.c + * @brief This file provides code for the configuration + * of the CRC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "crc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +CRC_HandleTypeDef hcrc; + +/* CRC init function */ +void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + if (HAL_CRC_Init(&hcrc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + +void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) +{ + + if(crcHandle->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* CRC clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } +} + +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* crcHandle) +{ + + if(crcHandle->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspDeInit 0 */ + + /* USER CODE END CRC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC_CLK_DISABLE(); + /* USER CODE BEGIN CRC_MspDeInit 1 */ + + /* USER CODE END CRC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/debug.c b/Core/Src/debug.c index 60bcc3b..bd47071 100755 --- a/Core/Src/debug.c +++ b/Core/Src/debug.c @@ -8,29 +8,156 @@ #include "main.h" #include #include +#include +#include #include "debug.h" #include "board.h" #include "charger_gbt.h" #include "usart.h" #include #include +#include "serial_control.h" + +// Кольцевой буфер для отладочных сообщений +#define DEBUG_BUFFER_SIZE 1024 +#define DEBUG_BUFFER_MAX_COUNT 128 + +typedef struct { + uint8_t buffer[DEBUG_BUFFER_SIZE]; + volatile uint16_t write_index; + volatile uint16_t read_index; + volatile uint16_t count; +} DebugBuffer_t; + +static DebugBuffer_t debug_buffer = { + .buffer = {0}, + .write_index = 0, + .read_index = 0, + .count = 0 +}; + + + + +#if defined(__GNUC__) +int _write(int fd, char * ptr, int len) +{ + debug_buffer_add((const uint8_t*)ptr, len); + return len; +} +#endif + +// Добавляет данные в кольцевой буфер +void debug_buffer_add(const uint8_t* data, uint16_t len) +{ + __disable_irq(); + + for (uint16_t i = 0; i < len; i++) { + // Если буфер полон, перезаписываем старые данные + if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { + debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; + debug_buffer.count--; + } + + debug_buffer.buffer[debug_buffer.write_index] = data[i]; + debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; + debug_buffer.count++; + } + + __enable_irq(); +} + +// Возвращает количество доступных данных в буфере +uint16_t debug_buffer_available(void) +{ + __disable_irq(); + uint16_t count = debug_buffer.count; + __enable_irq(); + return count; +} + +// Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) +void debug_buffer_send(void) +{ + __disable_irq(); + + // Если буфер пуст, ничего не делаем + if (debug_buffer.count == 0) { + __enable_irq(); + return; + } + + // Определяем сколько байт можно отправить (не более 250) + uint16_t bytes_to_send = debug_buffer.count; + if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { + bytes_to_send = DEBUG_BUFFER_MAX_COUNT; + } + + // Вычисляем сколько байт до конца буфера + uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; + + // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) + if (bytes_to_send > bytes_to_end) { + bytes_to_send = bytes_to_end; + } + + // Отправляем данные напрямую из буфера + if(bytes_to_send == debug_buffer.count){ + SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); + }else{ + SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); + } + debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; + debug_buffer.count -= bytes_to_send; + + __enable_irq(); +} + +#define LOG_BUFFER_SIZE 128 +uint8_t log_buffer[LOG_BUFFER_SIZE]; + +// Кастомный printf с приоритетом лога +int log_printf(LogLevel_t level, const char *format, ...) +{ + va_list args; + int result; + + // Добавляем приоритет первым байтом + log_buffer[0] = (uint8_t)level; + + // Форматируем строку начиная со второго байта + va_start(args, format); + result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); + va_end(args); + + // Проверяем, не переполнился ли буфер + if (result < 0) { + return result; + } + + // Ограничиваем размер, чтобы оставить место для нуль-терминатора + if (result >= (LOG_BUFFER_SIZE - 2)) { + result = LOG_BUFFER_SIZE - 2; + } + + // Добавляем нуль-терминатор в конец + log_buffer[result + 1] = '\0'; + + // Отправляем в буфер (приоритет + строка + нуль-терминатор) + debug_buffer_add(log_buffer, result + 2); + + return result; +} + +#ifndef USE_WEB_INTERFACE + +extern UART_HandleTypeDef huart2; uint8_t debug_rx_buffer[256]; uint8_t debug_cmd_received; uint8_t debug_rx_buffer_size = 0; -extern UART_HandleTypeDef huart2; - -#if defined(__GNUC__) -int _write(int fd, char * ptr, int len) -{ - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 1); - HAL_UART_Transmit(&huart2, (uint8_t *) ptr, len, HAL_MAX_DELAY); - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 0); - return len; -} -#endif void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size){ @@ -50,12 +177,6 @@ void debug_rx_interrupt(UART_HandleTypeDef *huart, uint16_t Size){ void debug_init(){ HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); - //mm_schedule_write(0x01, 0x0000, 0x0800); - // mm_schedule_write(0x02, 0x00FF, 0xFFFF); - //for (int i=0;i<60;i++) - // mm_schedule_write(0x02, 0x0000, 0xFF00); - // mm_schedule_write(0x01, 0x0000, 0x0100); - // mm_schedule_write(0x01, 0x0000, 0x0100); } void parse_command(uint8_t* buffer, size_t length) { @@ -70,56 +191,61 @@ void parse_command(uint8_t* buffer, size_t length) { } if (buffer[0] == 0) return; if (strncmp((const char*)buffer, "reset", length) == 0) { - printf("Resetting...\n"); + log_printf(LOG_INFO, "Resetting...\n"); NVIC_SystemReset(); } else if (strncmp((const char*)buffer, "relayaux", length) == 0) { - printf("Relaying...\n"); + log_printf(LOG_INFO, "Relaying...\n"); RELAY_Write(RELAY_AUX, 1); - HAL_Delay(200); + HAL_Delay(2000); RELAY_Write(RELAY_AUX, 0); } else if (strncmp((const char*)buffer, "relaycc", length) == 0) { - printf("Relaying...\n"); + log_printf(LOG_INFO, "Relaying...\n"); RELAY_Write(RELAY_CC, 1); HAL_Delay(200); RELAY_Write(RELAY_CC, 0); - - -// } else if (strncmp((const char*)buffer, "voltage", length) == 0) { -// printf("Voltaging...\n"); -// mm_schedule_read(0x02, 0x0001); + } else if (strncmp((const char*)buffer, "relaydc", length) == 0) { + log_printf(LOG_INFO, "Relaying...\n"); + RELAY_Write(RELAY_DC, 1); + HAL_Delay(200); + RELAY_Write(RELAY_DC, 0); + } else if (strncmp((const char*)buffer, "relayac", length) == 0) { + log_printf(LOG_INFO, "Relaying...\n"); + RELAY_Write(RELAY_AC, 1); + HAL_Delay(200); + RELAY_Write(RELAY_AC, 0); } else if (strncmp((const char*)buffer, "adc", length) == 0) { - printf("CC1=%.2f\n", CONN_CC_GetAdc()); + log_printf(LOG_INFO, "CC1=%.2f\n", CONN_CC_GetAdc()); } else if (strncmp((const char*)buffer, "lock_state", length) == 0) { - printf("Lock state=%d\n", GBT_LockGetState()); + log_printf(LOG_INFO, "Lock state=%d\n", GBT_LockGetState()); } else if (strncmp((const char*)buffer, "lock_lock", length) == 0) { - printf("Locked\n"); + log_printf(LOG_INFO, "Locked\n"); GBT_Lock(1); } else if (strncmp((const char*)buffer, "lock_unlock", length) == 0) { - printf("Unlocked\n"); + log_printf(LOG_INFO, "Unlocked\n"); GBT_Lock(0); } else if (strncmp((const char*)buffer, "complete", length) == 0) { - CONN_SetState(CONN_Finishing); + CONN_SetState(Finished); } else if (strncmp((const char*)buffer, "start", length) == 0) { - printf("Started\n"); + log_printf(LOG_INFO, "Started\n"); GBT_Start(); } else if (strncmp((const char*)buffer, "stop", length) == 0) { - printf("Stopped\n"); - GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); + log_printf(LOG_INFO, "Stopped\n"); + GBT_StopEVSE(GBT_CST_SUSPENDS_ARTIFICIALLY); } else if (strncmp((const char*)buffer, "stop1", length) == 0) { - printf("Stopped\n"); + log_printf(LOG_INFO, "Stopped\n"); GBT_ForceStop(); // } else if (strncmp((const char*)buffer, "force", length) == 0) { -// printf("Stopped\n"); +// log_printf(LOG_INFO, "Stopped\n"); // GBT_Lock(1); // GBT_SwitchState(GBT_S2_LOCKED); // GBT_Delay(500); @@ -127,81 +253,81 @@ void parse_command(uint8_t* buffer, size_t length) { } else if (strncmp((const char*)buffer, "cc_state", length) == 0) { switch(CONN_CC_GetState()){ case GBT_CC_UNKNOWN: - printf("GBT_CC_UNKNOWN\n"); + log_printf(LOG_INFO, "GBT_CC_UNKNOWN\n"); break; case GBT_CC_12V: - printf("GBT_CC_12V\n"); + log_printf(LOG_INFO, "GBT_CC_12V\n"); break; case GBT_CC_6V: - printf("GBT_CC_6V\n"); + log_printf(LOG_INFO, "GBT_CC_6V\n"); break; case GBT_CC_4V: - printf("GBT_CC_4V\n"); + log_printf(LOG_INFO, "GBT_CC_4V\n"); break; case GBT_CC_2V: - printf("GBT_CC_2V\n"); + log_printf(LOG_INFO, "GBT_CC_2V\n"); break; } } else if (strncmp((const char*)buffer, "temp", length) == 0) { - printf("temp1 %d\n",GBT_ReadTemp(0)); - printf("temp2 %d\n",GBT_ReadTemp(1)); + log_printf(LOG_INFO, "temp1 %d\n",GBT_ReadTemp(0)); + log_printf(LOG_INFO, "temp2 %d\n",GBT_ReadTemp(1)); } else if (strncmp((const char*)buffer, "info1", length) == 0) { - printf("Battery info:\n"); - printf("maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit - printf("maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit - printf("totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh - printf("maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit - printf("maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset - printf("SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% - printf("Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit + log_printf(LOG_INFO, "Battery info:\n"); + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit + log_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit + log_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit + log_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset + log_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% + log_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit } else if (strncmp((const char*)buffer, "info2", length) == 0) { - printf("EV info:\n"); - printf("GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); - printf("Battery type: %d\n",GBT_EVInfo.batteryType); - printf("Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit - printf("Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit - printf("Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) - printf("Battery SN: %lu\n", GBT_EVInfo.batterySN); // int - printf("Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) - printf("Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t - printf("Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto - printf("EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN - printf("EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); + log_printf(LOG_INFO, "EV info:\n"); + log_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); + log_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); + log_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit + log_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit + log_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) + log_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int + log_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) + log_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t + log_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto + log_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN + log_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); } else if (strncmp((const char*)buffer, "info3", length) == 0) { - printf("GBT_MaxLoad info:\n"); - printf("Output max current: %d\n",GBT_MaxLoad.maxOutputCurrent); - printf("Output min current: %d\n",GBT_MaxLoad.minOutputCurrent); - printf("Output max voltage: %d\n",GBT_MaxLoad.maxOutputVoltage); - printf("Output min voltage: %d\n",GBT_MaxLoad.minOutputVoltage); - printf("\nGBT_ChargerInfo info:\n"); - printf("BMS Recognized: %d\n",GBT_ChargerInfo.bmsIdentified); - printf("Charger location: %.3s\n",GBT_ChargerInfo.chargerLocation); - printf("Charger number: %lu\n",GBT_ChargerInfo.chargerNumber); + log_printf(LOG_INFO, "GBT_MaxLoad info:\n"); + log_printf(LOG_INFO, "Output max current: %d\n",GBT_MaxLoad.maxOutputCurrent); + log_printf(LOG_INFO, "Output min current: %d\n",GBT_MaxLoad.minOutputCurrent); + log_printf(LOG_INFO, "Output max voltage: %d\n",GBT_MaxLoad.maxOutputVoltage); + log_printf(LOG_INFO, "Output min voltage: %d\n",GBT_MaxLoad.minOutputVoltage); + log_printf(LOG_INFO, "\nGBT_ChargerInfo info:\n"); + log_printf(LOG_INFO, "BMS Recognized: %d\n",GBT_ChargerInfo.bmsIdentified); + log_printf(LOG_INFO, "Charger location: %.3s\n",GBT_ChargerInfo.chargerLocation); + log_printf(LOG_INFO, "Charger number: %lu\n",GBT_ChargerInfo.chargerNumber); } else if (strncmp((const char*)buffer, "help", length) == 0) { - printf("Command list:\n"); - printf("reset\n"); - printf("help\n"); - printf("cc_state\n"); - printf("lock_lock\n"); - printf("lock_unlock\n"); - printf("lock_state\n"); - printf("adc\n"); - printf("relay(cc,aux)\n"); - printf("start\n"); - printf("stop\n"); - printf("stop1\n"); -// printf("force\n"); - printf("temp\n"); - printf("info1\n"); - printf("info2\n"); - printf("info3\n"); - printf("time\n"); - printf("cantest\n"); + log_printf(LOG_INFO, "Command list:\n"); + log_printf(LOG_INFO, "reset\n"); + log_printf(LOG_INFO, "help\n"); + log_printf(LOG_INFO, "cc_state\n"); + log_printf(LOG_INFO, "lock_lock\n"); + log_printf(LOG_INFO, "lock_unlock\n"); + log_printf(LOG_INFO, "lock_state\n"); + log_printf(LOG_INFO, "adc\n"); + log_printf(LOG_INFO, "relay(cc,aux,ac,dc)\n"); + log_printf(LOG_INFO, "start\n"); + log_printf(LOG_INFO, "stop\n"); + log_printf(LOG_INFO, "stop1\n"); +// log_printf(LOG_INFO, "force\n"); + log_printf(LOG_INFO, "temp\n"); + log_printf(LOG_INFO, "info1\n"); + log_printf(LOG_INFO, "info2\n"); + log_printf(LOG_INFO, "info3\n"); + log_printf(LOG_INFO, "time\n"); + log_printf(LOG_INFO, "cantest\n"); //TODO: info commands @@ -210,20 +336,20 @@ void parse_command(uint8_t* buffer, size_t length) { time_t unix_time = (time_t)get_Current_Time(); struct tm *parts = localtime(&unix_time); - printf("Year: %d\n", parts->tm_year + 1900); - printf("Month: %d\n", parts->tm_mon + 1); - printf("Day: %d\n", parts->tm_mday); - printf("Hour: %d\n", parts->tm_hour); - printf("Minute: %d\n", parts->tm_min); - printf("Second: %d\n", parts->tm_sec); + log_printf(LOG_INFO, "Year: %d\n", parts->tm_year + 1900); + log_printf(LOG_INFO, "Month: %d\n", parts->tm_mon + 1); + log_printf(LOG_INFO, "Day: %d\n", parts->tm_mday); + log_printf(LOG_INFO, "Hour: %d\n", parts->tm_hour); + log_printf(LOG_INFO, "Minute: %d\n", parts->tm_min); + log_printf(LOG_INFO, "Second: %d\n", parts->tm_sec); } else if (strncmp((const char*)buffer, "cantest", length) == 0) { //GBT_SendCHM(); GBT_Error(0xFDF0C0FC); //BRM Timeout - printf("can test\n"); + log_printf(LOG_INFO, "can test\n"); } else { - printf("Unknown command\n"); + log_printf(LOG_INFO, "Unknown command\n"); } } @@ -234,3 +360,7 @@ void debug_task(){ debug_cmd_received = 0; } } + +#else + +#endif // USE_WEB_INTERFACE diff --git a/Core/Src/edcan_handler_user.c b/Core/Src/edcan_handler_user.c deleted file mode 100755 index 1e56609..0000000 --- a/Core/Src/edcan_handler_user.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * edcan_handler.c - * - * В этом файле расположены обработчики приходящих пакетов для пользовательских регистров - * - * Created on: Jul 5, 2024 - * Author: colorbass - */ - - -#include -#include "stdio.h" -#include "soft_rtc.h" -#include "charger_gbt.h" - -// * здесь объявлять внешние устройства и их регистры * -//uint8_t edcan_register_BMS[256];//300...3FF - - -////meter registers -//#define EDCAN_ID_METER 0x10 -//#define EDCAN_REG_METER_VOLTAGE 0x03 -//#define EDCAN_REG_METER_CURRENT 0x04 - - -//own registers -#define EDCAN_REG_CHARGER_ENABLE 0x100 - - -/* Charger info registers */ -#define EDCAN_REG_CHARGER_INFO 0x200 -//UNIX TIME -#define EDCAN_REG_TIME_0 0x210 -#define EDCAN_REG_TIME_1 0x211 -#define EDCAN_REG_TIME_2 0x212 -#define EDCAN_REG_TIME_3 0x213 - -#define EDCAN_REG_MAX_LOAD 0x220 - - - -#define EDCAN_REG_BRM 0x310 - -#define EDCAN_REG_BCP 0x350 - -#define EDCAN_REG_BRO 0x35F - -#define EDCAN_REG_BCL 0x360 - -#define EDCAN_REG_BCS 0x370 - -#define EDCAN_REG_BSM 0x380 - - -#define EDCAN_REG_OUTPUT 0x500 - -GBT_EDCAN_Output_t GBT_EDCAN_Output; - - -#define EDCAN_REG_INPUT 0x580 - -GBT_EDCAN_Input_t GBT_EDCAN_Input; - - - -/** - * @brief Handler for incoming Read packet - * Another device reply value of its registers - * - * @param SourceID: Packet Source ID - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_ReadHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ - //Получили пакет Read (запрошенное значение регистров) -// printf("Received packet: Read\n"); -// printf("Source ID = %d\n", SourceID); -// printf("Destination ID = %d\n", DestinationID); -// printf("Address = %d\n", Addr); -// printf("Len = %d\n", len); -// printf("\n"); - - for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler - - // * добавить сюда новые устройства * - -// if(SourceID == EDCAN_ID_METER){ -// printf ("register[%d] = %d\n", Addr+AddrOffset, data[AddrOffset]); -// switch(Addr+AddrOffset){ -// -// // * добавить сюда внешние регистры этого устройства * -// case EDCAN_REG_METER_VOLTAGE: -// printf ("Voltage = %d\n", data[AddrOffset]); -// break; -// -// case EDCAN_REG_METER_CURRENT: -// printf ("Current = %d\n", data[AddrOffset]); -// break; -// default: -// printf ("Unknown register\n"); -// } -// } - - } -// printf("\n"); -} - -/** - * @brief Handler for incoming Read packet - * Another device reply value of its registers - * - * @param SourceID: Packet Source ID - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_WriteUserRegister(uint16_t addr, uint8_t value){ - switch(addr){ - //edcan_register[addr] = value; -// case EDCAN_REG_K0: -// printf ("K0 = %d\n", value); -// HAL_GPIO_WritePin (K0_GPIO_Port, K0_Pin, (value == 0)); -// break; -// case EDCAN_REG_CHARGER_ENABLE: -// if(value)GBT_Charger_Enable = 1; -// else GBT_Charger_Enable = 0; -// break; - - case EDCAN_REG_TIME_0: - writeTimeReg(0, value); - break; - case EDCAN_REG_TIME_1: - writeTimeReg(1, value); - break; - case EDCAN_REG_TIME_2: - writeTimeReg(2, value); - break; - case EDCAN_REG_TIME_3: - writeTimeReg(3, value); - break; - - - - //0x220 - case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): - ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD] = value; - break; - - //0x200 - case EDCAN_REG_CHARGER_INFO ... (EDCAN_REG_CHARGER_INFO+sizeof(GBT_CRM_t)): - ((uint8_t*)&GBT_ChargerInfo)[addr - EDCAN_REG_CHARGER_INFO] = value; - break; - - //0x580 - case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): - ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT] = value; - - //TODO - //GBT_EDCAN_Input.measuredCurrent; - break; - - - - default: - printf ("Unknown register\n"); - } - -} - - -uint8_t EDCAN_GetUserRegisterValue(uint16_t addr){ - switch (addr){ - -// /* регистры 256..2047 используются пользовательских нужд */ - -// 0x400 - case EDCAN_REG_TIME_0: - return getTimeReg(0); - break; - - case EDCAN_REG_TIME_1: - return getTimeReg(1); - break; - - case EDCAN_REG_TIME_2: - return getTimeReg(2); - break; - - case EDCAN_REG_TIME_3: - return getTimeReg(3); - break; - - - //0x220 - case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): - return ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD]; - - //0x310 - case EDCAN_REG_BRM ... (EDCAN_REG_BRM+sizeof(GBT_BRM_t)-1): - return ((uint8_t*)&GBT_EVInfo)[addr - EDCAN_REG_BRM]; - - //0x340 - case EDCAN_REG_BCP ... (EDCAN_REG_BCP+sizeof(GBT_BCP_t)): - return ((uint8_t*)&GBT_BATStat)[addr - EDCAN_REG_BCP]; - - //0x34F - case EDCAN_REG_BRO: - return GBT_BRO; - - //0x350 - case EDCAN_REG_BCL ... (EDCAN_REG_BCL+sizeof(GBT_BCL_t)): - return ((uint8_t*)&GBT_ReqPower)[addr - EDCAN_REG_BCL]; - - //0x360 - case EDCAN_REG_BCS ... (EDCAN_REG_BCS+sizeof(GBT_BCS_t)): - return ((uint8_t*)&GBT_ChargingStatus)[addr - EDCAN_REG_BCS]; - - //0x370 - case EDCAN_REG_BSM ... (EDCAN_REG_BSM+sizeof(GBT_BSM_t)): - return ((uint8_t*)&GBT_BatteryStatus)[addr - EDCAN_REG_BSM]; - - - //0x500 - case EDCAN_REG_OUTPUT ... (EDCAN_REG_OUTPUT+sizeof(GBT_EDCAN_Output_t)): - return ((uint8_t*)&GBT_EDCAN_Output)[addr - EDCAN_REG_OUTPUT]; - - //0x580 - case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): - return ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT]; - - - default: - return 0x00; - } -} - - - - diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c old mode 100755 new mode 100644 index 7dc0857..de2e6b8 --- a/Core/Src/gpio.c +++ b/Core/Src/gpio.c @@ -38,6 +38,8 @@ * Output * EVENT_OUT * EXTI + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { @@ -54,54 +56,94 @@ void MX_GPIO_Init(void) /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin + |RELAY5_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); - /*Configure GPIO pins : PCPin PCPin */ + /*Configure GPIO pin : IN_SW0_Pin */ + GPIO_InitStruct.Pin = IN_SW0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : IN_SW1_Pin */ + GPIO_InitStruct.Pin = IN_SW1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = LOCK_FB_Pin; + /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ + GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(LOCK_FB_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : PEPin PEPin */ - GPIO_InitStruct.Pin = ADDR_0_Pin|ADDR_1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ + /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin + RELAY5_Pin */ + GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin + |RELAY5_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USART2_DIR_Pin; + /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ + GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(USART2_DIR_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = RELAY_AUX_Pin; + /*Configure GPIO pin : IN_ESTOP_Pin */ + GPIO_InitStruct.Pin = IN_ESTOP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ + GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : EE_WP_Pin */ + GPIO_InitStruct.Pin = EE_WP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(RELAY_AUX_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure peripheral I/O remapping */ + __HAL_AFIO_REMAP_I2C1_ENABLE(); } diff --git a/Core/Src/j1939.c b/Core/Src/j1939.c index 1b7f70c..4b92f73 100755 --- a/Core/Src/j1939.c +++ b/Core/Src/j1939.c @@ -10,7 +10,7 @@ #include "charger_gbt.h" #include "string.h" #include "can.h" -#include "edcan.h" +#include "debug.h" extern GBT_BCL_t GBT_ReqPower; extern GBT_BCL_t GBT_CurrPower; @@ -79,18 +79,21 @@ void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) case 0x1E00: //PGN BEM (ERROR) //Error force stop - EDCAN_printf(LOG_WARN, "BEM Received, force stopping...\n"); - EDCAN_printf(LOG_WARN, "BEM: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); - EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); + // --> Suspend EV + log_printf(LOG_ERR, "BEM Received, force stopping...\n"); + log_printf(LOG_ERR, "BEM: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); + log_printf(LOG_ERR, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); GBT_ForceStop(); break; case 0x1900: //PGN BST (STOP) //Normal stop - EDCAN_printf(LOG_WARN, "BST Received, stopping...\n"); - EDCAN_printf(LOG_WARN, "BST: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); - EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); - GBT_Stop(GBT_CST_BMS_ACTIVELY_SUSPENDS); + + // --> Suspend EV + log_printf(LOG_INFO, "BST Received, stopping...\n"); + log_printf(LOG_INFO, "BST: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); + log_printf(LOG_INFO, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); + GBT_StopEV(GBT_CST_BMS_ACTIVELY_SUSPENDS); break; @@ -114,9 +117,9 @@ void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) void GBT_CAN_ReInit(){ HAL_CAN_Stop(&hcan1); MX_CAN1_Init(); + GBT_CAN_FilterInit(); HAL_CAN_Start(&hcan1); HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); - GBT_CAN_FilterInit(); } void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ diff --git a/Core/Src/lock.c b/Core/Src/lock.c index 7e3e738..d85a895 100755 --- a/Core/Src/lock.c +++ b/Core/Src/lock.c @@ -5,45 +5,37 @@ * Author: colorbass */ #include "lock.h" +#include "debug.h" -uint8_t LOCK_POLARITY = 1; + +uint8_t LOCK_POLARITY = 1; // 1 for v1 uint8_t LOCK_MOTOR_POLARITY = 1; -uint8_t LOCK_DELAY = 50; +uint16_t LOCK_DELAY = 100; -GBT_LockState_t GBT_LockState; +GBT_LockState_t GBT_LockState = { + .demand = 0, + .error = 0, + .action_requested = 255, // нет запрошенного действия + .motor_state = 0, // idle + .last_action_time = 0, + .retry_count = 0, + .error_tick = 0 +}; void GBT_ForceLock(uint8_t state){ - if(LOCK_MOTOR_POLARITY){ - if(state){//LOCK - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); - HAL_Delay(LOCK_DELAY); - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); - }else{ //UNLOCK - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); - HAL_Delay(LOCK_DELAY); - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); - } - }else{ - if(state){//LOCK - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); - HAL_Delay(LOCK_DELAY); - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); - }else{ //UNLOCK - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); - HAL_Delay(LOCK_DELAY); - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); - } - } + // Устанавливаем флаг для выполнения действия + GBT_LockState.action_requested = state ? 1 : 0; + GBT_LockState.retry_count = 0; } uint8_t GBT_LockGetState(){ //1 = locked //0 = unlocked if(LOCK_POLARITY){ - return HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); + return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); }else{ - return !HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); + return !HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); } } @@ -52,37 +44,126 @@ void GBT_Lock(uint8_t state){ GBT_LockState.demand = state; } -void GBT_ManageLock(){ - uint8_t MAX_RETRIES = 5; - if (GBT_LockState.error) { - return; - } +void GBT_ManageLockSolenoid(){ + static uint32_t tick; + if(HAL_GetTick() - tick < 50) return; + tick = HAL_GetTick(); + + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, GBT_LockState.demand ? 1 : 0); +} + +void GBT_ManageLockMotor(){ + static const uint8_t MAX_RETRIES = 5; + uint32_t current_tick = HAL_GetTick(); + + // Проверяем таймаут сброса ошибки (до проверки error, чтобы можно было сбросить) + GBT_ResetErrorTimeout(); + + if (GBT_LockState.error) { + return; + } + + // Проверяем, нужно ли выполнить действие bool lock_is_open = GBT_LockGetState() == 0; bool lock_should_be_open = GBT_LockState.demand == 0; - uint8_t retry_count = 0; - - if (lock_is_open != lock_should_be_open) { - while (retry_count < MAX_RETRIES) { - if (lock_should_be_open) { - GBT_ForceLock(0); - } else { - GBT_ForceLock(1); - } - - lock_is_open = GBT_LockGetState() == 0; - - if (lock_is_open == lock_should_be_open) { - break; - } - - retry_count++; + + // Если есть запрошенное действие или состояние не соответствует требуемому + if (GBT_LockState.action_requested != 255 || (lock_is_open != lock_should_be_open)) { + // Если действие еще не запрошено, запрашиваем его + if (GBT_LockState.action_requested == 255) { + GBT_LockState.action_requested = lock_should_be_open ? 0 : 1; + GBT_LockState.retry_count = 0; } + + // Управление мотором через машину состояний + switch (GBT_LockState.motor_state) { + case 0: // idle - мотор выключен + // Определяем, какой пин нужно включить + if (LOCK_MOTOR_POLARITY) { + if (GBT_LockState.action_requested == 1) { // LOCK + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); + } else { // UNLOCK + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); + } + } else { + if (GBT_LockState.action_requested == 1) { // LOCK + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); + } else { // UNLOCK + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); + } + } + GBT_LockState.motor_state = 1; // motor_on + GBT_LockState.last_action_time = current_tick; + break; + + case 1: // motor_on - мотор включен, ждем LOCK_DELAY + if (current_tick - GBT_LockState.last_action_time >= LOCK_DELAY) { + // Выключаем оба пина + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); + GBT_LockState.motor_state = 2; // waiting_off + GBT_LockState.last_action_time = current_tick; + } + break; + + case 2: // waiting_off - ждем немного перед проверкой состояния + // Небольшая задержка перед проверкой состояния (например, 50мс) + if (current_tick - GBT_LockState.last_action_time >= 50) { + // Проверяем, достигнуто ли требуемое состояние + lock_is_open = GBT_LockGetState() == 0; + bool action_success = (lock_is_open == (GBT_LockState.action_requested == 0)); + + if (action_success) { + // Действие выполнено успешно + GBT_LockState.action_requested = 255; // сбрасываем флаг + GBT_LockState.motor_state = 0; // idle + GBT_LockState.retry_count = 0; + } else { + // Действие не выполнено, повторяем попытку + GBT_LockState.retry_count++; + if (GBT_LockState.retry_count >= MAX_RETRIES) { + // Превышено количество попыток + GBT_LockState.error = 1; + GBT_LockState.error_tick = current_tick; // сохраняем время установки ошибки + GBT_LockState.action_requested = 0; // пытаемся разблокировать + GBT_LockState.motor_state = 0; + GBT_LockState.retry_count = 0; + log_printf(LOG_ERR, "Lock error\n"); + } else { + // Повторяем попытку + GBT_LockState.motor_state = 0; // возвращаемся к началу + } + } + } + break; + } + } else { + // Состояние соответствует требуемому, сбрасываем флаги + if (GBT_LockState.motor_state != 0) { + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); + GBT_LockState.motor_state = 0; + } + GBT_LockState.action_requested = 255; + GBT_LockState.retry_count = 0; + } +} - if (retry_count >= MAX_RETRIES) { - GBT_LockState.error = 1; - GBT_ForceLock(0); - printf ("Lock error\n"); +void GBT_LockResetError(){ + GBT_LockState.error = 0; + GBT_LockState.error_tick = 0; + log_printf(LOG_INFO, "Lock error reset\n"); +} + +void GBT_ResetErrorTimeout(){ + static const uint32_t ERROR_TIMEOUT_MS = 300000; // 5 минут + + if (GBT_LockState.error && GBT_LockState.error_tick != 0) { + + if ((HAL_GetTick()-GBT_LockState.error_tick) >= ERROR_TIMEOUT_MS) { + // Прошло 5 минут, сбрасываем ошибку + GBT_LockResetError(); } } } diff --git a/Core/Src/main.c b/Core/Src/main.c old mode 100755 new mode 100644 index 634e9f0..ba38126 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -1,26 +1,12 @@ /* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "adc.h" #include "can.h" +#include "crc.h" #include "rtc.h" +#include "tim.h" #include "usart.h" #include "gpio.h" @@ -35,6 +21,8 @@ #include "j1939.h" #include "lock.h" #include "connector.h" +#include "serial_control.h" +#include "charger_config.h" /* USER CODE END Includes */ @@ -46,8 +34,6 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ -#include "edcan_config.h" -#include "edcan_defines.h" /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -70,6 +56,70 @@ void SystemClock_Config(void); /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ +/** + * @brief Vector base address configuration. It should no longer be at the start of + * flash memory but moved forward because the first part of flash is + * reserved for the bootloader. Note that this is already done by the + * bootloader before starting this program. Unfortunately, function + * SystemInit() overwrites this change again. + * @return none. + */ +static void VectorBase_Config(void) +{ + /* The constant array with vectors of the vector table is declared externally in the + * c-startup code. + */ + extern const unsigned long g_pfnVectors[]; + + /* Remap the vector table to where the vector table is located for this program. */ + SCB->VTOR = (unsigned long)&g_pfnVectors[0]; +} + +uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ + static uint8_t memory[32]; + if(id > 31) return 0; + uint8_t result = 0; + if(memory[id] != flag){ + result = 1; + } + memory[id] = flag; + return result; +} + + +void ED_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait){ + CONN_CC_ReadStateFiltered(); + GBT_ManageLockMotor(); + CONN_Task(); + GBT_ChargerTask(); + LED_Task(); + SC_Task(); + // if(huart2.gState != HAL_UART_STATE_BUSY_TX) debug_buffer_send(); // TEST + } +} + +void StopButtonControl(){ + + //Charging do nothing + if(!IN_ReadInput(IN_ESTOP)){ + CONN.connControl = CMD_STOP; + } + +} + +uint8_t temp0, temp1; + /* USER CODE END 0 */ /** @@ -78,8 +128,9 @@ void SystemClock_Config(void); */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ + VectorBase_Config(); /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ @@ -88,7 +139,7 @@ int main(void) HAL_Init(); /* USER CODE BEGIN Init */ - + HAL_RCC_DeInit(); /* USER CODE END Init */ /* Configure the system clock */ @@ -103,24 +154,30 @@ int main(void) MX_ADC1_Init(); MX_CAN1_Init(); MX_CAN2_Init(); - MX_USART2_UART_Init(); MX_RTC_Init(); + MX_TIM4_Init(); + MX_USART2_UART_Init(); + MX_CRC_Init(); + MX_UART5_Init(); + MX_USART1_UART_Init(); + MX_USART3_UART_Init(); /* USER CODE BEGIN 2 */ - CAN_ReInit(); Init_Peripheral(); + LED_Init(); HAL_Delay(300); GBT_Init(); - set_Time(1721651966); - printf("Startup (type \'help\' for command list)\n"); - debug_init(); - EDCAN_Init(SW_GetAddr()); //0x20..0x23 - EDCAN_printf(LOG_INFO, "Startup\n"); - //EDCAN_Init(0x20); //Адрес EDCAN + SC_Init(); + log_printf(LOG_INFO, "GBT Charger v%d.%d\n", GBT_CH_VER_MAJOR, GBT_CH_VER_MINOR); + ReadVersion(); + log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); + log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); + log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); + GBT_SetConfig(); GBT_CAN_ReInit(); - CAN_ReInit(); - + PSU_Init(); CONN_Init(); + /* USER CODE END 2 */ /* Infinite loop */ @@ -130,14 +187,17 @@ int main(void) /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ -// HAL_Delay(1); - EDCAN_Loop(); - //can_task(); - debug_task(); - CONN_CC_ReadStateFiltered(); - GBT_ManageLock(); - CONN_Task(); - GBT_ChargerTask(); + + + PSU_ReadWrite(); + PSU_Task(); + ED_Delay(10); + METER_CalculateEnergy(); + CONN_Loop(); + LED_Write(); + ED_Delay(10); + StopButtonControl(); + ED_Delay(50); } /* USER CODE END 3 */ @@ -217,8 +277,7 @@ void Error_Handler(void) } /* USER CODE END Error_Handler_Debug */ } - -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. diff --git a/Core/Src/meter.c b/Core/Src/meter.c new file mode 100755 index 0000000..d02446f --- /dev/null +++ b/Core/Src/meter.c @@ -0,0 +1,54 @@ +/* + * meter.c + * + * Created on: 27 сент. 2024 г. + * Author: root + */ + + +#include "meter.h" +#include "charger_config.h" +#include "charger_control.h" + + +METER_t METER; + +// Функция для расчета и накопления энергии c дробной частью без счетчиков +void METER_CalculateEnergy() { + // Проверяем, что индекс находится в пределах массива + + METER.online = 0; + + if(CONN.connState == Charging){ + METER.enable = 1; + }else{ + METER.enable = 0; + } + + uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах + uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах + METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора + uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени + + //Расчет энергии теперь идет всегда, смещение берем суммарное + METER.EnergyPSU_Ws += energyWs; + + // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков + METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час + + if(METER.enable) { + //enabled state + CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час + + }else{ + // Reset statе + CONN.Energy = 0; + + METER.EnergyOffset = METER.AbsoluteEnergy; + + } + + +} + + diff --git a/Core/Src/psu_control.c b/Core/Src/psu_control.c new file mode 100755 index 0000000..ff8657c --- /dev/null +++ b/Core/Src/psu_control.c @@ -0,0 +1,448 @@ + +#include + +#include "can.h" +#include "string.h" +#include "stdio.h" +#include "charger_config.h" +#include "charger_control.h" +#include "charger_gbt.h" +#include "board.h" +#include "debug.h" + +PSU_02_t PSU_02; +PSU_04_t PSU_04; +PSU_06_t PSU_06; +PSU_08_t PSU_08; +PSU_09_t PSU_09; + +PSU_1A_t PSU_1A; +PSU_1B_t PSU_1B; +PSU_1C_t PSU_1C; + +PSU_t PSU0; + +#define CAN_DELAY 20 +#define PSU_VOLTAGE_THRESHOLD 20 // Порог напряжения для определения состояния (В) +#define PSU_ONLINE_TIMEOUT 500 // Таймаут для определения состояния (мс) +#define PSU_STARTUP_DELAY 4000 // Задержка 2 секунды перед включением + +uint32_t can_lastpacket; + +extern CAN_HandleTypeDef hcan2; + +static void PSU_SwitchState(PSU_State_t state){ + PSU0.state = state; + PSU0.statetick = HAL_GetTick(); +} + +static uint32_t PSU_StateTime(void){ + return HAL_GetTick() - PSU0.statetick; +} + +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ + + static CAN_RxHeaderTypeDef RxHeader; + static uint8_t RxData[8] = {0,}; + CanId_t CanId; + + if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) + { + memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); + + /* Для DC30 поддерживается только один силовой модуль (source == 0) */ + if(CanId.source != 0) return; + can_lastpacket = HAL_GetTick(); + + if(CanId.command==0x02){ + memcpy(&PSU_02, RxData, 8); + } + if(CanId.command==0x04){ + memcpy(&PSU_04, RxData, 8); + + PSU0.tempAmbient = PSU_04.moduleTemperature; + PSU0.status0.raw = PSU_04.modularForm0; + PSU0.status1.raw = PSU_04.modularForm1; + PSU0.status2.raw = PSU_04.modularForm2; + } + if(CanId.command==0x06){ + memcpy(&PSU_06, RxData, 8); + + PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); + PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); + PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); + + } + if(CanId.command==0x08){ + memcpy(&PSU_08, RxData, 8); + } + if(CanId.command==0x09){ + + memcpy(&PSU_09, RxData, 8); + PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; + + PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; + + // PSU_09 -> PSU -> CONN (один модуль) + { + uint16_t v = PSU_09.moduleNVoltage / 1000; + int16_t i = PSU_09.moduleNCurrent / 100; + + // Обновляем модель PSU0 по телеметрии + PSU0.outputVoltage = v; + PSU0.outputCurrent = i; + PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); + PSU0.online = 1; + PSU0.temperature = PSU_04.moduleTemperature; + + // Экспортируем значения из PSU0 в CONN только, + // когда модуль хотя бы в состоянии READY и выше + if(PSU0.state >= PSU_READY){ + CONN.MeasuredVoltage = PSU0.outputVoltage; + CONN.MeasuredCurrent = PSU0.outputCurrent; + CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; + CONN.outputEnabled = PSU0.PSU_enabled; + } + } + } + } +} + +void PSU_CAN_FilterInit(){ + CAN_FilterTypeDef sFilterConfig; + + sFilterConfig.FilterBank = 14; + sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; + sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; + sFilterConfig.FilterIdHigh = 0x0000; + sFilterConfig.FilterIdLow = 0x0000; + sFilterConfig.FilterMaskIdHigh = 0x0000; + sFilterConfig.FilterMaskIdLow = 0x0000; + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; + sFilterConfig.FilterActivation = ENABLE; + + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; + sFilterConfig.SlaveStartFilterBank = 14; + + + if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) + { + Error_Handler(); + } +} + +void PSU_Init(){ + + HAL_CAN_Stop(&hcan2); + MX_CAN2_Init(); + PSU_CAN_FilterInit(); + HAL_CAN_Start(&hcan2); + HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); + memset(&PSU0, 0, sizeof(PSU0)); + PSU0.state = PSU_UNREADY; + PSU0.statetick = HAL_GetTick(); + + PSU0.power_limit = PSU_MAX_POWER; // kW + PSU0.hv_mode = 0; + + PSU_Enable(0, 0); +} + +void PSU_Enable(uint8_t addr, uint8_t enable){ + PSU_1A_t data; + memset(&data, 0, sizeof(data)); + /* Для DC30 поддерживается только один модуль с адресом 0 */ + if(addr != 0) return; + if(PSU0.online == 0) return; + + data.enable = !enable; + PSU_SendCmd(0xF0, addr, 0x1A, &data); + ED_Delay(CAN_DELAY); +} + +void PSU_SetHVMode(uint8_t addr, uint8_t enable){ + PSU_1D_t data; + memset(&data, 0, sizeof(data)); + data.enable = !enable; + if(addr != 0) return; + PSU_SendCmd(0xF0, addr, 0x1D, &data); +} +void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ + PSU_1C_t data; + memset(&data, 0, sizeof(data)); + + if(addr != 0) return; + + if(voltage499) voltage = 499; + + uint32_t current_ma = current * 100; + uint32_t voltage_mv = voltage * 1000; + + data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; + data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; + data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; + data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; + + data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; + data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; + data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; + data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; + + PSU_SendCmd(0xF0, addr, 0x1C, &data); + +} + +void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ + CanId_t CanId; + CanId.source = source; + CanId.destination = destination; + CanId.command = cmd; + CanId.device = 0x0A; + + int8_t retry_counter = 10; + CAN_TxHeaderTypeDef tx_header; + uint32_t tx_mailbox; + HAL_StatusTypeDef CAN_result; + + memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); + + tx_header.RTR = CAN_RTR_DATA; + tx_header.IDE = CAN_ID_EXT; + tx_header.DLC = 8; + + while(retry_counter>0){ //если буфер полон, ждем пока он освободится + if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ + /* отправка сообщения */ + CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); + + /* если отправка удалась, выход */ + if(CAN_result == HAL_OK) { + return; + retry_counter = 0; + } + } + ED_Delay(1); + + retry_counter--; + } + +} + +uint32_t max(uint32_t a, uint32_t b){ + if(a>b) return a; + else return b; +} + +void PSU_ReadWrite(){ + + uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; + + PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); + PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); + // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); + PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); + + // Power Limit + if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ + CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; + }else{ + CONN.RequestedCurrent = CONN.WantedCurrent; + } + + if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ + CONN.RequestedCurrent = PSU_MAX_CURRENT*10; + } + CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; + + + if(PSU0.ready){ + PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode + ED_Delay(CAN_DELAY); + if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; + } + + // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need + // ED_Delay(CAN_DELAY); + +} + +void PSU_Task(void){ + static uint32_t psu_on_tick = 0; + static uint32_t dc_on_tick = 0; + static uint32_t cont_ok_tick = 0; + + // Обновляем ONLINE/READY по таймауту + if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ + PSU0.online = 0; + PSU0.PSU_enabled = 0; + PSU_04.moduleTemperature = 0; + PSU_04.modularForm0 = 0; + PSU_04.modularForm1 = 0; + PSU_04.modularForm2 = 0; + PSU_06.VAB = 0; + PSU_06.VBC = 0; + PSU_06.VCA = 0; + PSU_09.moduleNCurrent = 0; + PSU_09.moduleNVoltage = 0; + } + if(!PSU0.online || !PSU0.enableAC){ + CONN.MeasuredVoltage = 0; + CONN.MeasuredCurrent = 0; + CONN.outputEnabled = 0; + } + + // Управление AC-контактором с задержкой отключения 1 минута + if(CONN.EvConnected){ + RELAY_Write(RELAY_AC, 1); + psu_on_tick = HAL_GetTick(); + PSU0.enableAC = 1; + }else{ + if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ + RELAY_Write(RELAY_AC, 0); + PSU0.enableAC = 0; + } + } + + // Текущее состояние DC-контактора по обратной связи + PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); + + // Обновляем ready с учётом ошибок + if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ + // PSU0.ready = 1; + }else{ + PSU0.ready = 0; + } + + switch(PSU0.state){ + case PSU_UNREADY: + PSU0.enableOutput = 0; + RELAY_Write(RELAY_DC, 0); + if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ + PSU_SwitchState(PSU_INITIALIZING); + } + break; + + case PSU_INITIALIZING: + if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize + PSU0.ready = 1; + PSU_SwitchState(PSU_READY); + } + break; + + case PSU_READY: + // модуль готов, но выключен + PSU0.hv_mode = 0; + + RELAY_Write(RELAY_DC, 0); + if(!PSU0.ready){ + PSU_SwitchState(PSU_UNREADY); + break; + } + if(CONN.EnableOutput){ + PSU_Enable(0, 1); + PSU_SwitchState(PSU_WAIT_ACK_ON); + } + break; + + case PSU_WAIT_ACK_ON: + + if(PSU0.PSU_enabled && PSU0.ready){ + dc_on_tick = HAL_GetTick(); + PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); + }else if(PSU_StateTime() > 10000){ + PSU0.psu_fault = 1; + CONN.chargingError = CONN_ERR_PSU_FAULT; + PSU_SwitchState(PSU_UNREADY); + log_printf(LOG_ERR, "PSU on timeout\n"); + } + break; + + case PSU_CONT_WAIT_ACK_ON: + // замыкаем DC-контактор и ждём подтверждение + RELAY_Write(RELAY_DC, 1); + if(PSU0.CONT_enabled){ + PSU_SwitchState(PSU_CONNECTED); + }else if(PSU_StateTime() > 1000){ + PSU0.cont_fault = 1; + CONN.chargingError = CONN_ERR_CONTACTOR; + PSU_SwitchState(PSU_CURRENT_DROP); + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + } + break; + + case PSU_CONNECTED: + // Основное рабочее состояние + if(!CONN.EnableOutput || !PSU0.ready){ + PSU_SwitchState(PSU_CURRENT_DROP); + break; + } + // контроль контактора: 1 c таймаут + if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ + if((HAL_GetTick() - cont_ok_tick) > 1000){ + CONN.chargingError = CONN_ERR_CONTACTOR; + PSU0.cont_fault = 1; + PSU_SwitchState(PSU_CURRENT_DROP); + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + } + }else{ + cont_ok_tick = HAL_GetTick(); + } + break; + + case PSU_CURRENT_DROP: + // снижаем ток до нуля перед отключением DC + CONN.RequestedCurrent = 0; + + // если ток действительно упал или вышло время, отключаем DC + if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ + PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); + } + break; + + case PSU_CONT_WAIT_ACK_OFF: + RELAY_Write(RELAY_DC, 0); + if(!PSU0.CONT_enabled){ + PSU_Enable(0, 0); + PSU_SwitchState(PSU_WAIT_ACK_OFF); + }else if(PSU_StateTime() > 1000){ + PSU0.cont_fault = 1; + CONN.chargingError = CONN_ERR_CONTACTOR; + PSU_Enable(0, 0); + PSU_SwitchState(PSU_WAIT_ACK_OFF); + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + } + break; + + case PSU_WAIT_ACK_OFF: + if(!PSU0.PSU_enabled){ + PSU_SwitchState(PSU_OFF_PAUSE); + }else if(PSU_StateTime() > 10000){ + PSU0.psu_fault = 1; + CONN.chargingError = CONN_ERR_PSU_FAULT; + PSU_SwitchState(PSU_UNREADY); + log_printf(LOG_ERR, "PSU off timeout\n"); + } + break; + case PSU_OFF_PAUSE: + if(PSU_StateTime() > 4000){ + PSU_SwitchState(PSU_READY); + } + break; + + + + default: + PSU_SwitchState(PSU_UNREADY); + break; + } +} + + diff --git a/Core/Src/rgb_controller.c b/Core/Src/rgb_controller.c new file mode 100644 index 0000000..9722cf9 --- /dev/null +++ b/Core/Src/rgb_controller.c @@ -0,0 +1,251 @@ +#include "rgb_controller.h" +#include "main.h" +#include "string.h" +#include "charger_control.h" + +#include "tim.h" + +RGB_State_t LED_State; +RGB_Cycle_t LED_Cycle; + +RGB_Cycle_t color_estop = { + .Color1 = { .R = 250, .G = 0, .B = 0 }, + .Color2 = { .R = 250, .G = 0, .B = 0 }, + .Tr = 50, + .Th = 50, + .Tf = 50, + .Tl = 50, + }; + +RGB_Cycle_t color_unknown = { + .Color1 = { .R = 64, .G = 0, .B = 0 }, + .Color2 = { .R = 64, .G = 0, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_light = { + .Color1 = { .R = 0, .G = 255, .B = 0 }, + .Color2 = { .R = 0, .G = 255, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_disabled = { + .Color1 = { .R = 250, .G = 0, .B = 0 }, + .Color2 = { .R = 32, .G = 0, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_unplugged = { + .Color1 = { .R = 0, .G = 128, .B = 0 }, + .Color2 = { .R = 0, .G = 128, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_preparing = { + .Color1 = { .R = 0, .G = 0, .B = 250 }, + .Color2 = { .R = 0, .G = 0, .B = 250 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_charging = { + .Color1 = { .R = 0, .G = 255, .B = 0 }, + .Color2 = { .R = 0, .G = 32, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_finished = { + .Color1 = { .R = 255, .G = 255, .B = 255 }, + .Color2 = { .R = 255, .G = 255, .B = 255 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +RGB_Cycle_t color_error = { + .Color1 = { .R = 255, .G = 0, .B = 0 }, + .Color2 = { .R = 32, .G = 0, .B = 0 }, + .Tr = 50, + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +void LED_Write(){ + if(CONN.chargingError != CONN_NO_ERROR){ + LED_SetColor(&color_error); + return; + } + switch(CONN.connState){ + case Unknown: + LED_SetColor(&color_unknown); + break; + case Unplugged: + LED_SetColor(&color_unplugged); + break; + case Disabled: + LED_SetColor(&color_error); + break; + case Preparing: + LED_SetColor(&color_preparing); + break; + case AuthRequired: + LED_SetColor(&color_preparing); + break; + case WaitingForEnergy: + LED_SetColor(&color_charging); + break; + case ChargingPausedEV: + LED_SetColor(&color_charging); + break; + case ChargingPausedEVSE: + LED_SetColor(&color_charging); + break; + case Charging: + LED_SetColor(&color_charging); + break; + case AuthTimeout: + LED_SetColor(&color_finished); + break; + case Finished: + LED_SetColor(&color_finished); + break; + case FinishedEVSE: + LED_SetColor(&color_finished); + break; + case FinishedEV: + LED_SetColor(&color_finished); + break; + case Replugging: + LED_SetColor(&color_preparing); + break; + default: + LED_SetColor(&color_unknown); + break; + } + } + +void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { + + // Проверяем, чтобы a не выходила за пределы диапазона + if (a > b) a = b; + + if(b==0) b = 1; + + // Вычисляем коэффициент смешивания в виде целого числа + uint16_t t = (a * 255) / b; // t будет от 0 до 255 + + // Линейная интерполяция с использованием целых чисел + result->R = (color1->R * (255 - t) + color2->R * t) / 255; + result->G = (color1->G * (255 - t) + color2->G * t) / 255; + result->B = (color1->B * (255 - t) + color2->B * t) / 255; + +} + + +void RGB_SetColor(RGB_t *color){ + htim4.Instance->CCR2 = color->R * 100 / 255; + htim4.Instance->CCR3 = color->G * 100 / 255; + htim4.Instance->CCR4 = color->B * 100 / 255; +} + +void LED_SetColor(RGB_Cycle_t *color){ + memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); +} + + +void LED_Init(){ + RGB_t color = {.R=0, .G=0, .B=0}; + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); + RGB_SetColor(&color); +} + +// void LED_PhaseSync(uint8_t led_n){ +// if(LED_State[led_n].phasesync){ +// LED_State[led_n].phasesync = 0; +// //default settings +// LED_State[led_n].state = LED_HIGH; +// LED_State[led_n].tick = 0; +// //ищем среди всех светодиодов такую же последовательность +// for (uint8_t led_n1 = 0; led_n1 < 5; led_n1++){ +// if ((LED_Cycle[led_n].Tf == LED_Cycle[led_n1].Tf) && +// (LED_Cycle[led_n].Tr == LED_Cycle[led_n1].Tr) && +// (LED_Cycle[led_n].Th == LED_Cycle[led_n1].Th) && +// (LED_Cycle[led_n].Tl == LED_Cycle[led_n1].Tl) && +// (led_n != led_n1)){ +// //если нашли, то копируем фазу оттуда +// LED_State[led_n].state = LED_State[led_n1].state; +// LED_State[led_n].tick = LED_State[led_n1].tick; +// return; + + +// } +// } +// } +// } + +void LED_Task(){ + static uint32_t led_tick; + if((HAL_GetTick() - led_tick) > 20){ + led_tick = HAL_GetTick(); + LED_State.tick++; + // LED_PhaseSync(led_n); + switch(LED_State.state){ + case LED_RISING: + interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); + + if(LED_State.tick>LED_Cycle.Tr){ + LED_State.state = LED_HIGH; + LED_State.tick = 0; + } + break; + case LED_HIGH: + memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); + + if(LED_State.tick>LED_Cycle.Th){ + LED_State.state = LED_FALLING; + LED_State.tick = 0; + } + break; + case LED_FALLING: + interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); + + if(LED_State.tick>LED_Cycle.Tf){ + LED_State.state = LED_LOW; + LED_State.tick = 0; + } + break; + case LED_LOW: + memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); + + if(LED_State.tick>LED_Cycle.Tl){ + LED_State.state = LED_RISING; + LED_State.tick = 0; + } + break; + default: + LED_State.state = LED_RISING; + } + RGB_SetColor(&LED_State.color); + } +} diff --git a/Core/Src/rtc.c b/Core/Src/rtc.c index dd1f3bb..c955786 100755 --- a/Core/Src/rtc.c +++ b/Core/Src/rtc.c @@ -1,21 +1,5 @@ /* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file rtc.c - * @brief This file provides code for the configuration - * of the RTC instances. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "rtc.h" diff --git a/Core/Src/serial_control.c b/Core/Src/serial_control.c new file mode 100644 index 0000000..3b216e2 --- /dev/null +++ b/Core/Src/serial_control.c @@ -0,0 +1,243 @@ +#include "serial_control.h" +#include "crc.h" +#include "usart.h" +#include "board.h" + +// Приватные функции +uint32_t revbit(uint32_t uData); +uint32_t CRC32_ForBytes(uint8_t *pData, uint32_t uLen); +uint32_t calculate_crc32(const uint8_t* data, uint16_t length); +uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code); +uint8_t process_received_packet(const uint8_t* packet_data, uint16_t packet_len); + +uint8_t test_crc_invalid = 0; + +SerialControl_t serial_control; + +StatusPacket_t statusPacket = { + .SOC = 0, + .Energy = 0, + .RequestedVoltage = 0, + .RequestedCurrent = 0, + .MeasuredVoltage = 0, + .MeasuredCurrent = 0, + .outputEnabled = 0, + .chargingError = 0, + .connState = 0, + .chargingElapsedTimeMin = 0, + .chargingElapsedTimeSec = 0, + .estimatedRemainingChargingTime = 0, + .relayAC = 0, + .relayDC = 0, + .relayAUX = 0, + .lockState = 0, + .evInfoAvailable = 0, + .psuOnline = 0, + .tempConnector0 = 0, + .tempConnector1 = 0, + .tempAmbient = 0, + .tempBatteryMax = 0, + .tempBatteryMin = 0, + .highestVoltageOfBatteryCell = 0, + .batteryStatus = 0, + .phaseVoltageAB = 0, + .phaseVoltageBC = 0, + .phaseVoltageCA = 0, +}; + +InfoPacket_t infoPacket = { + .serialNumber = 0, + .boardVersion = 0, + .stationType = 0, + .fw_version_major = 0, + .fw_version_minor = 0, + .fw_version_patch = 0, +}; + +void ReadVersion(){ + infoPacket.serialNumber = InfoBlock->serialNumber; + infoPacket.boardVersion = InfoBlock->boardVersion; + infoPacket.stationType = InfoBlock->stationType; + infoPacket.fw_version_major = FW_VERSION_MAJOR; + infoPacket.fw_version_minor = FW_VERSION_MINOR; + infoPacket.fw_version_patch = FW_VERSION_PATCH; +} + +// Внешняя функция обработки команд (определена в serial_handler.c) +extern void SC_CommandHandler(ReceivedCommand_t* cmd); + +void SC_Init() { + // Обнуляем структуру + memset(&serial_control, 0, sizeof(SerialControl_t)); +} + +void SC_Task() { + // Запуск приема в режиме прерывания с ожиданием idle + if((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); + + // Проверка таймаута отправки пакета (больше 100 мс) + if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { + if ((HAL_GetTick() - serial_control.tx_tick) > 100) { + // Таймаут: принудительно сбрасываем передачу + HAL_UART_Abort_IT(&huart2); + // Выключаем DIR при сбросе передачи + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + serial_control.tx_tick = 0; // Сбрасываем tick + } + } + + // Проверка наличия принятой команды для обработки + if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { +// HAL_Delay(2); + SC_CommandHandler(&serial_control.received_command); + HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); + serial_control.command_ready = 0; // Сбрасываем флаг + } +} + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { + if (huart->Instance == huart2.Instance) { + if(!process_received_packet(serial_control.rx_buffer, Size)){ + SC_SendPacket(NULL, 0, RESP_INVALID); + } + } +} + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { + if (huart->Instance == huart2.Instance) { + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + serial_control.tx_tick = 0; + } +} + +// Приватные функции реализации +uint32_t revbit(uint32_t uData) { + uint32_t uRevData = 0, uIndex = 0; + uRevData |= ((uData >> uIndex) & 0x01); + for(uIndex = 1; uIndex < 32; uIndex++) { + uRevData <<= 1; + uRevData |= ((uData >> uIndex) & 0x01); + } + return uRevData; +} + +uint32_t CRC32_ForBytes(uint8_t *pData, uint32_t uLen) { + uint32_t uIndex = 0, uData = 0, i; + uIndex = uLen >> 2; + + SERIAL_PROTOCOL_CRC_CLK_ENABLE(); + + __HAL_CRC_DR_RESET(&hcrc); + + while(uIndex--) { + ((uint8_t *) & uData)[0] = pData[0]; + ((uint8_t *) & uData)[1] = pData[1]; + ((uint8_t *) & uData)[2] = pData[2]; + ((uint8_t *) & uData)[3] = pData[3]; + pData += 4; + uData = revbit(uData); + hcrc.Instance->DR = uData; + } + uData = revbit(hcrc.Instance->DR); + uIndex = uLen & 0x03; + while(uIndex--) { + uData ^= (uint32_t) * pData++; + for(i = 0; i < 8; i++) + if (uData & 0x1) + uData = (uData >> 1) ^ CRC32_POLYNOMIAL; + else + uData >>= 1; + } + + SERIAL_PROTOCOL_CRC_CLK_DISABLE(); + + return uData ^ 0xFFFFFFFF; +} + +uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { + return CRC32_ForBytes((uint8_t*)data, (uint32_t)length); +} + +uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { + uint16_t out_index = 0; + + output[out_index++] = response_code; + + if (payload != NULL) { + // Просто копируем полезную нагрузку без какого‑либо экранирования + for (uint16_t i = 0; i < payload_len; i++) { + output[out_index++] = payload[i]; + + // Проверка переполнения + if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE + return 0; + } + } + } + + // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) + uint32_t crc = calculate_crc32(output, out_index); + uint8_t* crc_bytes = (uint8_t*)&crc; + + // Добавляем CRC без экранирования + for (int i = 0; i < 4; i++) { + output[out_index++] = crc_bytes[i]; + + if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE + return 0; + } + } + + return out_index; +} + +void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { + uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); + + if (packet_len > 0) { + if (huart2.gState == HAL_UART_STATE_BUSY_TX) { + HAL_UART_Abort_IT(&huart2); + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + } + + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); + + HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); + + serial_control.tx_tick = HAL_GetTick(); + } +} + +uint8_t process_received_packet(const uint8_t* packet_data, uint16_t packet_len) { + // if (test_crc_invalid && (packet_data[1] != CMD_GET_STATUS)) { + // test_crc_invalid--; + // return 0; + // }else{ + // test_crc_invalid = 5; + // } + + // Минимальный размер: 1 байт команды + 4 байта CRC + if (packet_len < 5) return 0; + if (packet_len > MAX_RX_BUFFER_SIZE) return 0; + + uint16_t payload_length = packet_len - 4; + + // Извлекаем принятую CRC (последние 4 байта, little-endian) + uint32_t received_checksum = + ((uint32_t)packet_data[payload_length] << 0) | + ((uint32_t)packet_data[payload_length + 1] << 8) | + ((uint32_t)packet_data[payload_length + 2] << 16) | + ((uint32_t)packet_data[payload_length + 3] << 24); + + // Вычисляем CRC для полезной нагрузки + uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); + + if (received_checksum != calculated_checksum) return 0; // CRC не совпадает + + serial_control.received_command.argument = &packet_data[1]; + serial_control.received_command.command = packet_data[0]; + serial_control.received_command.argument_length = payload_length - 1; + serial_control.command_ready = 1; + return 1; +} + diff --git a/Core/Src/serial_handler.c b/Core/Src/serial_handler.c new file mode 100644 index 0000000..70d0430 --- /dev/null +++ b/Core/Src/serial_handler.c @@ -0,0 +1,188 @@ +#include "serial_control.h" +#include "charger_gbt.h" +#include "crc.h" +#include "usart.h" +#include "charger_control.h" +#include "charger_gbt.h" +#include "board.h" +#include "psu_control.h" +#include "debug.h" + +#ifdef USE_WEB_INTERFACE + +extern uint8_t GBT_BAT_STAT_recv; + +uint8_t config_initialized = 0; +ConfigBlock_t config = { + .location = "RUS", + .chargerNumber = 00001, + .unixTime = 1721651966, +}; + +// Единая функция-обработчик всех команд со switch-case +void SC_CommandHandler(ReceivedCommand_t* cmd) { + + uint8_t response_code = RESP_FAILED; + + switch (cmd->command) { + // Команды БЕЗ аргументов + case CMD_GET_STATUS: + // Логика получения информации + monitoring_data_callback(); + + // Отправляем с нормальным приоритетом + SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); + return; // Специальный ответ уже отправлен + + case CMD_GET_INFO: + SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); + return; + + case CMD_GET_LOG: + debug_buffer_send(); + return; // Ответ формируется внутри debug_buffer_send + + // Команды С аргументами + + case CMD_SET_CONFIG: + if (cmd->argument_length == sizeof(ConfigBlock_t)) { + memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); + GBT_SetConfig(); + config_initialized = 1; + GBT_SetConfig(); +// CONN.connState = CONN_Available; // + log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); + response_code = RESP_SUCCESS; + break; + } + response_code = RESP_FAILED; + break; + case CMD_SET_POWER_LIMIT: + if (cmd->argument_length == 1) { + PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; + log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); + //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; + response_code = RESP_SUCCESS; + break; + } + response_code = RESP_FAILED; + break; + case CMD_CHARGE_PERMIT: + if (cmd->argument_length == 1) { + CONN.connControl = ((uint8_t*)cmd->argument)[0]; + log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); + response_code = RESP_SUCCESS; + break; + } + response_code = RESP_FAILED; + break; + + case CMD_TEST_PSU: + // if (cmd->argument_length == sizeof(PSU_TestMode_t)) { + // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); + // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); + // response_code = RESP_SUCCESS; + // break; + // } + response_code = RESP_FAILED; + break; + case CMD_DEVICE_RESET: + // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) + SC_SendPacket(NULL, 0, RESP_SUCCESS); + + while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи + // 3. Выполняем программный сброс + NVIC_SystemReset(); + return; // Сюда код уже не дойдет, но для компилятора нужно + + default: + // Неизвестная команда + response_code = RESP_FAILED; + break; + } + + // Отправляем финальный ответ (для команд без собственного ответа) + SC_SendPacket(NULL, 0, response_code); +} + + +// Колбэк для заполнения данных мониторинга +void monitoring_data_callback() { + + // Информация о зарядной сессии + statusPacket.SOC = CONN.SOC; + statusPacket.Energy = CONN.Energy; + statusPacket.RequestedVoltage = CONN.RequestedVoltage; + statusPacket.RequestedCurrent = CONN.WantedCurrent; + statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; + statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; + statusPacket.outputEnabled = CONN.outputEnabled; + statusPacket.chargingError = CONN.chargingError; + statusPacket.connState = CONN.connState; + statusPacket.chargingElapsedTimeMin = 0; + statusPacket.chargingElapsedTimeSec = 0; + statusPacket.estimatedRemainingChargingTime = 0; + + // состояние зарядной станции + statusPacket.relayAC = RELAY_Read(RELAY_AC); + statusPacket.relayDC = RELAY_Read(RELAY_DC); + statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); + statusPacket.lockState = GBT_LockGetState(); + statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); + statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; + statusPacket.evInfoAvailable = GBT_BAT_STAT_recv; + statusPacket.psuOnline = PSU0.online; + + statusPacket.tempConnector0 = GBT_ReadTemp(0); // температура коннектора + statusPacket.tempConnector1 = GBT_ReadTemp(1); + statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха + statusPacket.tempBatteryMax = GBT_BatteryStatus.batteryHighestTemp; // максимальная температура батареи + statusPacket.tempBatteryMin = GBT_BatteryStatus.batteryLowestTemp; // минимальная температура батареи + + statusPacket.highestVoltageOfBatteryCell = GBT_ChargingStatus.highestVoltageOfBatteryCell; + statusPacket.batteryStatus = GBT_BatteryStatus.batteryStatus; + + statusPacket.phaseVoltageAB = PSU_06.VAB; + statusPacket.phaseVoltageBC = PSU_06.VBC; + statusPacket.phaseVoltageCA = PSU_06.VCA; + + memcpy(statusPacket.VIN, GBT_EVInfo.EVIN, sizeof(GBT_EVInfo.EVIN)); + + statusPacket.batteryType = GBT_EVInfo.batteryType; + statusPacket.batteryCapacity = GBT_EVInfo.batteryCapacity; + statusPacket.batteryVoltage = GBT_EVInfo.batteryVoltage; + memcpy(statusPacket.batteryVendor, GBT_EVInfo.batteryVendor, sizeof(statusPacket.batteryVendor)); + statusPacket.batterySN = GBT_EVInfo.batterySN; + statusPacket.batteryManuD = GBT_EVInfo.batteryManuD; + statusPacket.batteryManuM = GBT_EVInfo.batteryManuM; + statusPacket.batteryManuY = GBT_EVInfo.batteryManuY; + statusPacket.batteryCycleCount = GBT_EVInfo.batteryCycleCount; + statusPacket.ownAuto = GBT_EVInfo.ownAuto; + memcpy(statusPacket.EV_SW_VER, GBT_EVInfo.EV_SW_VER, sizeof(statusPacket.EV_SW_VER)); + + statusPacket.testMode = 0; + statusPacket.testVoltage = 0; + statusPacket.testCurrent = 0; + + // Информация о тачке + + // --- Информация об EV (из команды info2) --- + // memcpy(statusPacket.version, GBT_EVInfo.version, sizeof(statusPacket.version)); + + + // --- Состояние Hardware и GBT (различные команды) --- + //statusPacket.lockState = GBT_LockGetState(); // Из команды lock_state + //statusPacket.ccState = CONN_CC_GetState(); // Из команды cc_state + //statusPacket.ccAdc = CONN_CC_GetAdc(); // Из команды adc + + // --- Поля, требующие внимания (неявные геттеры) --- + + // 1. Состояние соединения (ConnState) + // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() + // Если такой функции нет, закомментируйте следующую строку: + // statusPacket.connState = CONN_GetState(); + + +} + +#endif diff --git a/Core/Src/soft_rtc.c b/Core/Src/soft_rtc.c index 96ba55e..78260dc 100755 --- a/Core/Src/soft_rtc.c +++ b/Core/Src/soft_rtc.c @@ -72,7 +72,7 @@ uint8_t getTimeReg(uint8_t reg_number){ // // // Print the BCD values for verification // for (int i = 0; i < 8; i++) { -// printf("time[%d]: %02X\n", i, time[i]); +// log_printf(LOG_INFO, "time[%d]: %02X\n", i, time[i]); // } // // return 0; diff --git a/Core/Src/stm32f1xx_hal_msp.c b/Core/Src/stm32f1xx_hal_msp.c old mode 100755 new mode 100644 index a51f0d4..9dd9806 --- a/Core/Src/stm32f1xx_hal_msp.c +++ b/Core/Src/stm32f1xx_hal_msp.c @@ -62,6 +62,7 @@ */ void HAL_MspInit(void) { + /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ diff --git a/Core/Src/stm32f1xx_it.c b/Core/Src/stm32f1xx_it.c old mode 100755 new mode 100644 index 16853bf..3bc5f9a --- a/Core/Src/stm32f1xx_it.c +++ b/Core/Src/stm32f1xx_it.c @@ -57,7 +57,9 @@ /* External variables --------------------------------------------------------*/ extern CAN_HandleTypeDef hcan1; extern CAN_HandleTypeDef hcan2; +extern UART_HandleTypeDef huart1; extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -214,6 +216,20 @@ void CAN1_RX0_IRQHandler(void) /* USER CODE END CAN1_RX0_IRQn 1 */ } +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + /** * @brief This function handles USART2 global interrupt. */ @@ -228,6 +244,20 @@ void USART2_IRQHandler(void) /* USER CODE END USART2_IRQn 1 */ } +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + /* USER CODE BEGIN USART3_IRQn 0 */ + + /* USER CODE END USART3_IRQn 0 */ + HAL_UART_IRQHandler(&huart3); + /* USER CODE BEGIN USART3_IRQn 1 */ + + /* USER CODE END USART3_IRQn 1 */ +} + /** * @brief This function handles CAN2 TX interrupt. */ diff --git a/Core/Src/tim.c b/Core/Src/tim.c new file mode 100644 index 0000000..3cd40ba --- /dev/null +++ b/Core/Src/tim.c @@ -0,0 +1,155 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim4; + +/* TIM4 init function */ +void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 720; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 100; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* TIM4 clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM4_ENABLE(); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c old mode 100755 new mode 100644 index d97daeb..4571c1e --- a/Core/Src/usart.c +++ b/Core/Src/usart.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -24,8 +24,68 @@ /* USER CODE END 0 */ +UART_HandleTypeDef huart5; +UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; +/* UART5 init function */ +void MX_UART5_Init(void) +{ + + /* USER CODE BEGIN UART5_Init 0 */ + + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + huart5.Init.BaudRate = 115200; + huart5.Init.WordLength = UART_WORDLENGTH_8B; + huart5.Init.StopBits = UART_STOPBITS_1; + huart5.Init.Parity = UART_PARITY_NONE; + huart5.Init.Mode = UART_MODE_TX_RX; + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} /* USART2 init function */ void MX_USART2_UART_Init(void) @@ -54,13 +114,100 @@ void MX_USART2_UART_Init(void) /* USER CODE END USART2_Init 2 */ +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + } void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(uartHandle->Instance==USART2) + if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspInit 0 */ + + /* USER CODE END UART5_MspInit 0 */ + /* UART5 clock enable */ + __HAL_RCC_UART5_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN UART5_MspInit 1 */ + + /* USER CODE END UART5_MspInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) { /* USER CODE BEGIN USART2_MspInit 0 */ @@ -92,12 +239,84 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) /* USER CODE END USART2_MspInit 1 */ } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART3 GPIO Configuration + PC10 ------> USART3_TX + PC11 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_USART3_PARTIAL(); + + /* USART3 interrupt Init */ + HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } } void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { - if(uartHandle->Instance==USART2) + if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspDeInit 0 */ + + /* USER CODE END UART5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART5_CLK_DISABLE(); + + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN UART5_MspDeInit 1 */ + + /* USER CODE END UART5_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) { /* USER CODE BEGIN USART2_MspDeInit 0 */ @@ -117,6 +336,26 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) /* USER CODE END USART2_MspDeInit 1 */ } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PC10 ------> USART3_TX + PC11 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); + + /* USART3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ diff --git a/Core/Startup/startup_stm32f107vctx.s b/Core/Startup/startup_stm32f107vctx.s index 2d1b748..7bf47ac 100755 --- a/Core/Startup/startup_stm32f107vctx.s +++ b/Core/Startup/startup_stm32f107vctx.s @@ -59,6 +59,7 @@ defined in linker script */ .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: + ldr sp, =_estack /* set stack pointer */ /* Call the clock system initialization function.*/ bl SystemInit @@ -252,6 +253,7 @@ g_pfnVectors: .word 0 .word BootRAM /* @0x1E0. This is for boot in RAM mode for STM32F10x Connectivity line Devices. */ + .word 0x66666666 /* Reserved for OpenBLT checksum*/ /******************************************************************************* * diff --git a/Debug/.DS_Store b/Debug/.DS_Store new file mode 100644 index 0000000..2a920ff Binary files /dev/null and b/Debug/.DS_Store differ diff --git a/Debug/Core/.DS_Store b/Debug/Core/.DS_Store new file mode 100644 index 0000000..ca9e589 Binary files /dev/null and b/Debug/Core/.DS_Store differ diff --git a/Debug/Core/Src/adc.cyclo b/Debug/Core/Src/adc.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/board.cyclo b/Debug/Core/Src/board.cyclo index 4c69929..b497a98 100644 --- a/Debug/Core/Src/board.cyclo +++ b/Debug/Core/Src/board.cyclo @@ -1,8 +1,9 @@ -../Core/Src/board.c:16:6:RELAY_Write 3 -../Core/Src/board.c:22:9:GetBoardTemp 1 -../Core/Src/board.c:34:6:Init_Peripheral 1 -../Core/Src/board.c:41:7:pt1000_to_temperature 1 -../Core/Src/board.c:57:7:calculate_NTC_resistance 2 -../Core/Src/board.c:72:9:GBT_ReadTemp 3 -../Core/Src/board.c:107:6:ADC_Select_Channel 2 -../Core/Src/board.c:118:9:SW_GetAddr 4 +../Core/Src/board.c:16:6:RELAY_Write 8 +../Core/Src/board.c:46:9:RELAY_Read 1 +../Core/Src/board.c:51:9:IN_ReadInput 8 +../Core/Src/board.c:72:9:GetBoardTemp 1 +../Core/Src/board.c:84:6:Init_Peripheral 1 +../Core/Src/board.c:96:7:pt1000_to_temperature 1 +../Core/Src/board.c:107:7:calculate_NTC_resistance 2 +../Core/Src/board.c:122:9:GBT_ReadTemp 3 +../Core/Src/board.c:152:6:ADC_Select_Channel 2 diff --git a/Debug/Core/Src/can.cyclo b/Debug/Core/Src/can.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/charger_control.cyclo b/Debug/Core/Src/charger_control.cyclo new file mode 100644 index 0000000..79ce2a0 --- /dev/null +++ b/Debug/Core/Src/charger_control.cyclo @@ -0,0 +1,3 @@ +../Core/Src/charger_control.c:9:6:CONN_Init 1 +../Core/Src/charger_control.c:17:6:CONN_Loop 7 +../Core/Src/charger_control.c:41:6:CONN_PrintChargingTotal 1 diff --git a/Debug/Core/Src/charger_gbt.cyclo b/Debug/Core/Src/charger_gbt.cyclo index b3cb5d9..17c6033 100644 --- a/Debug/Core/Src/charger_gbt.cyclo +++ b/Debug/Core/Src/charger_gbt.cyclo @@ -1,10 +1,13 @@ -../Core/Src/charger_gbt.c:63:6:GBT_Init 1 -../Core/Src/charger_gbt.c:72:6:GBT_ChargerTask 76 -../Core/Src/charger_gbt.c:421:6:GBT_SwitchState 29 -../Core/Src/charger_gbt.c:461:10:GBT_StateTick 1 -../Core/Src/charger_gbt.c:465:6:GBT_Delay 1 -../Core/Src/charger_gbt.c:470:6:GBT_Stop 2 -../Core/Src/charger_gbt.c:475:6:GBT_Error 1 -../Core/Src/charger_gbt.c:481:6:GBT_ForceStop 1 -../Core/Src/charger_gbt.c:488:6:GBT_Reset 1 -../Core/Src/charger_gbt.c:509:6:GBT_Start 1 +../Core/Src/charger_gbt.c:71:6:GBT_Init 1 +../Core/Src/charger_gbt.c:82:6:GBT_SetConfig 1 +../Core/Src/charger_gbt.c:91:6:GBT_ChargerTask 92 +../Core/Src/charger_gbt.c:476:6:GBT_SwitchState 16 +../Core/Src/charger_gbt.c:497:10:GBT_StateTick 1 +../Core/Src/charger_gbt.c:501:6:GBT_Delay 1 +../Core/Src/charger_gbt.c:506:6:GBT_StopEV 3 +../Core/Src/charger_gbt.c:516:6:GBT_StopEVSE 2 +../Core/Src/charger_gbt.c:522:6:GBT_StopOCPP 2 +../Core/Src/charger_gbt.c:528:6:GBT_ForceStop 1 +../Core/Src/charger_gbt.c:537:6:GBT_Error 1 +../Core/Src/charger_gbt.c:545:6:GBT_Reset 1 +../Core/Src/charger_gbt.c:572:6:GBT_Start 1 diff --git a/Debug/Core/Src/connector.cyclo b/Debug/Core/Src/connector.cyclo index 9e7353a..4a179d6 100644 --- a/Debug/Core/Src/connector.cyclo +++ b/Debug/Core/Src/connector.cyclo @@ -1,7 +1,6 @@ -../Core/Src/connector.c:18:6:CONN_Init 1 -../Core/Src/connector.c:22:6:CONN_Task 14 -../Core/Src/connector.c:94:6:CONN_SetState 7 -../Core/Src/connector.c:105:6:CONN_CC_ReadStateFiltered 4 -../Core/Src/connector.c:162:9:CONN_CC_GetState 1 -../Core/Src/connector.c:165:9:CONN_CC_GetStateRaw 9 -../Core/Src/connector.c:192:7:CONN_CC_GetAdc 1 +../Core/Src/connector.c:19:6:CONN_Task 32 +../Core/Src/connector.c:126:6:CONN_SetState 15 +../Core/Src/connector.c:147:6:CONN_CC_ReadStateFiltered 4 +../Core/Src/connector.c:166:9:CONN_CC_GetState 1 +../Core/Src/connector.c:169:9:CONN_CC_GetStateRaw 9 +../Core/Src/connector.c:182:7:CONN_CC_GetAdc 1 diff --git a/Debug/Core/Src/crc.cyclo b/Debug/Core/Src/crc.cyclo new file mode 100644 index 0000000..dd81665 --- /dev/null +++ b/Debug/Core/Src/crc.cyclo @@ -0,0 +1,3 @@ +../Core/Src/crc.c:30:6:MX_CRC_Init 2 +../Core/Src/crc.c:51:6:HAL_CRC_MspInit 2 +../Core/Src/crc.c:67:6:HAL_CRC_MspDeInit 2 diff --git a/Debug/Core/Src/debug.cyclo b/Debug/Core/Src/debug.cyclo index e2719a8..8eb6a57 100644 --- a/Debug/Core/Src/debug.cyclo +++ b/Debug/Core/Src/debug.cyclo @@ -1,7 +1,5 @@ -../Drivers/CMSIS/Include/core_cm3.h:1762:34:__NVIC_SystemReset 1 -../Core/Src/debug.c:26:5:_write 1 -../Core/Src/debug.c:35:6:HAL_UARTEx_RxEventCallback 2 -../Core/Src/debug.c:45:6:debug_rx_interrupt 1 -../Core/Src/debug.c:51:6:debug_init 1 -../Core/Src/debug.c:61:6:parse_command 28 -../Core/Src/debug.c:230:6:debug_task 2 +../Core/Src/debug.c:43:5:_write 1 +../Core/Src/debug.c:51:6:debug_buffer_add 3 +../Core/Src/debug.c:71:10:debug_buffer_available 1 +../Core/Src/debug.c:80:6:debug_buffer_send 5 +../Core/Src/debug.c:120:5:log_printf 3 diff --git a/Debug/Core/Src/edcan_handler_user.cyclo b/Debug/Core/Src/edcan_handler_user.cyclo index 515f558..e69de29 100644 --- a/Debug/Core/Src/edcan_handler_user.cyclo +++ b/Debug/Core/Src/edcan_handler_user.cyclo @@ -1,3 +0,0 @@ -../Core/Src/edcan_handler_user.c:76:6:EDCAN_ReadHandler 2 -../Core/Src/edcan_handler_user.c:120:6:EDCAN_WriteUserRegister 10 -../Core/Src/edcan_handler_user.c:174:9:EDCAN_GetUserRegisterValue 20 diff --git a/Debug/Core/Src/gbt_control.cyclo b/Debug/Core/Src/gbt_control.cyclo new file mode 100644 index 0000000..3919d5f --- /dev/null +++ b/Debug/Core/Src/gbt_control.cyclo @@ -0,0 +1,3 @@ +../Core/Src/gbt_control.c:10:6:GBT_SetConfig 1 +../Core/Src/gbt_control.c:24:6:GBT_ControlRead 1 +../Core/Src/gbt_control.c:33:6:GBT_ControlWrite 2 diff --git a/Debug/Core/Src/gpio.cyclo b/Debug/Core/Src/gpio.cyclo old mode 100755 new mode 100644 index 56b6958..f931fa1 --- a/Debug/Core/Src/gpio.cyclo +++ b/Debug/Core/Src/gpio.cyclo @@ -1 +1 @@ -../Core/Src/gpio.c:42:6:MX_GPIO_Init 1 +../Core/Src/gpio.c:44:6:MX_GPIO_Init 1 diff --git a/Debug/Core/Src/j1939.cyclo b/Debug/Core/Src/j1939.cyclo index 47157fb..65cbe3a 100644 --- a/Debug/Core/Src/j1939.cyclo +++ b/Debug/Core/Src/j1939.cyclo @@ -1,6 +1,6 @@ ../Core/Src/j1939.c:20:6:HAL_CAN_RxFifo0MsgPendingCallback 20 -../Core/Src/j1939.c:114:6:GBT_CAN_ReInit 1 -../Core/Src/j1939.c:122:6:J_SendPacket 1 -../Core/Src/j1939.c:143:6:J_SendCTS 2 -../Core/Src/j1939.c:161:6:J_SendACK 1 -../Core/Src/j1939.c:176:6:GBT_CAN_FilterInit 2 +../Core/Src/j1939.c:117:6:GBT_CAN_ReInit 1 +../Core/Src/j1939.c:125:6:J_SendPacket 1 +../Core/Src/j1939.c:146:6:J_SendCTS 2 +../Core/Src/j1939.c:164:6:J_SendACK 1 +../Core/Src/j1939.c:179:6:GBT_CAN_FilterInit 2 diff --git a/Debug/Core/Src/lock.cyclo b/Debug/Core/Src/lock.cyclo old mode 100755 new mode 100644 index 16d0a54..23b64a9 --- a/Debug/Core/Src/lock.cyclo +++ b/Debug/Core/Src/lock.cyclo @@ -1,4 +1,7 @@ -../Core/Src/lock.c:16:6:GBT_ForceLock 4 -../Core/Src/lock.c:40:9:GBT_LockGetState 2 -../Core/Src/lock.c:51:6:GBT_Lock 1 -../Core/Src/lock.c:55:6:GBT_ManageLock 7 +../Core/Src/lock.c:26:6:GBT_ForceLock 1 +../Core/Src/lock.c:32:9:GBT_LockGetState 2 +../Core/Src/lock.c:43:6:GBT_Lock 1 +../Core/Src/lock.c:47:6:GBT_ManageLockSolenoid 2 +../Core/Src/lock.c:56:6:GBT_ManageLockMotor 17 +../Core/Src/lock.c:153:6:GBT_LockResetError 1 +../Core/Src/lock.c:159:6:GBT_ResetErrorTimeout 4 diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo index ef53855..29bffda 100644 --- a/Debug/Core/Src/main.cyclo +++ b/Debug/Core/Src/main.cyclo @@ -1,37 +1,7 @@ -../Drivers/CMSIS/Include/core_cm3.h:1762:34:__NVIC_SystemReset 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:110:6:HAL_CAN_RxFifo1MsgPendingCallback 7 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:137:6:HAL_CAN_TxMailbox0CompleteCallback 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:144:6:HAL_CAN_TxMailbox1CompleteCallback 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:151:6:HAL_CAN_TxMailbox2CompleteCallback 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:163:6:EDCAN_Init 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:172:6:EDCAN_SetSecondID 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:182:6:CAN_ReInit 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:222:6:EDCAN_FilterInit 5 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:312:6:EDCAN_SendPacketWrite 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:351:6:EDCAN_SendPacketWriteLong 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:444:6:EDCAN_SendPacketRead 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:482:6:EDCAN_SendPacketReadRequest 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:516:6:EDCAN_Loop 7 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:551:6:EDCAN_SendAlivePacket 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:562:6:EDCAN_EnterSilentMode 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan.c:576:6:EDCAN_SetSilentMode 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:42:6:EDCAN_TxBufferAdd 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:58:10:EDCAN_getTxBufferElementCount 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:63:6:EDCAN_TxBufferPeekFirst 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:76:6:EDCAN_TxBufferRemoveFirst 3 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:94:6:EDCAN_ExchangeTxBuffer 7 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:150:6:EDCAN_RxBufferAdd 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:165:6:EDCAN_RxBufferGet 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:183:10:EDCAN_getRxBufferElementCount 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_buffer.c:188:6:EDCAN_ExchangeRxBuffer 5 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_handler.c:43:6:EDCAN_WriteHandler 3 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_handler.c:63:6:EDCAN_WriteSystemRegister 5 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_handler.c:90:9:EDCAN_GetSystemRegisterValue 8 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_handler.c:132:9:EDCAN_GetOwnRegisterValue 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_handler.c:151:6:EDCAN_ReadRequestHandler 5 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_log.c:28:6:EDCAN_printf 1 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_log.c:49:6:EDCAN_Log 2 -/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN/edcan_log.c:74:6:EDCAN_SendPacketLog 1 -../Core/Src/main.c:79:5:main 1 -../Core/Src/main.c:150:6:SystemClock_Config 4 -../Core/Src/main.c:210:6:Error_Handler 1 +../Core/Src/main.c:67:13:VectorBase_Config 1 +../Core/Src/main.c:78:9:ED_TraceWarning 3 +../Core/Src/main.c:90:6:ED_Delay 3 +../Core/Src/main.c:112:6:StopButtonControl 2 +../Core/Src/main.c:129:5:main 1 +../Core/Src/main.c:210:6:SystemClock_Config 4 +../Core/Src/main.c:270:6:Error_Handler 1 diff --git a/Debug/Core/Src/meter.cyclo b/Debug/Core/Src/meter.cyclo new file mode 100644 index 0000000..14212aa --- /dev/null +++ b/Debug/Core/Src/meter.cyclo @@ -0,0 +1 @@ +../Core/Src/meter.c:17:6:METER_CalculateEnergy 3 diff --git a/Debug/Core/Src/psu_control.cyclo b/Debug/Core/Src/psu_control.cyclo new file mode 100644 index 0000000..703fe8c --- /dev/null +++ b/Debug/Core/Src/psu_control.cyclo @@ -0,0 +1,12 @@ +../Core/Src/psu_control.c:34:13:PSU_SwitchState 1 +../Core/Src/psu_control.c:39:17:PSU_StateTime 1 +../Core/Src/psu_control.c:43:6:HAL_CAN_RxFifo1MsgPendingCallback 9 +../Core/Src/psu_control.c:117:6:PSU_CAN_FilterInit 2 +../Core/Src/psu_control.c:140:6:PSU_Init 1 +../Core/Src/psu_control.c:157:6:PSU_Enable 3 +../Core/Src/psu_control.c:169:6:PSU_SetHVMode 2 +../Core/Src/psu_control.c:176:6:PSU_SetVoltageCurrent 5 +../Core/Src/psu_control.c:203:6:PSU_SendCmd 4 +../Core/Src/psu_control.c:239:10:max 2 +../Core/Src/psu_control.c:244:6:PSU_ReadWrite 5 +../Core/Src/psu_control.c:277:6:PSU_Task 41 diff --git a/Debug/Core/Src/rgb_controller.cyclo b/Debug/Core/Src/rgb_controller.cyclo new file mode 100644 index 0000000..f1caecd --- /dev/null +++ b/Debug/Core/Src/rgb_controller.cyclo @@ -0,0 +1,6 @@ +../Core/Src/rgb_controller.c:92:6:LED_Write 16 +../Core/Src/rgb_controller.c:146:6:interpolateColors 3 +../Core/Src/rgb_controller.c:164:6:RGB_SetColor 1 +../Core/Src/rgb_controller.c:170:6:LED_SetColor 1 +../Core/Src/rgb_controller.c:175:6:LED_Init 1 +../Core/Src/rgb_controller.c:207:6:LED_Task 10 diff --git a/Debug/Core/Src/rtc.cyclo b/Debug/Core/Src/rtc.cyclo old mode 100755 new mode 100644 index 2fcc49b..7ec31a2 --- a/Debug/Core/Src/rtc.cyclo +++ b/Debug/Core/Src/rtc.cyclo @@ -1,3 +1,3 @@ -../Core/Src/rtc.c:30:6:MX_RTC_Init 2 -../Core/Src/rtc.c:56:6:HAL_RTC_MspInit 2 -../Core/Src/rtc.c:75:6:HAL_RTC_MspDeInit 2 +../Core/Src/rtc.c:14:6:MX_RTC_Init 2 +../Core/Src/rtc.c:40:6:HAL_RTC_MspInit 2 +../Core/Src/rtc.c:59:6:HAL_RTC_MspDeInit 2 diff --git a/Debug/Core/Src/serial_control.cyclo b/Debug/Core/Src/serial_control.cyclo new file mode 100644 index 0000000..3a253dc --- /dev/null +++ b/Debug/Core/Src/serial_control.cyclo @@ -0,0 +1,11 @@ +../Core/Src/serial_control.c:57:6:ReadVersion 1 +../Core/Src/serial_control.c:69:6:SC_Init 1 +../Core/Src/serial_control.c:74:6:SC_Task 8 +../Core/Src/serial_control.c:98:6:HAL_UARTEx_RxEventCallback 3 +../Core/Src/serial_control.c:106:6:HAL_UART_TxCpltCallback 2 +../Core/Src/serial_control.c:114:10:revbit 2 +../Core/Src/serial_control.c:124:10:CRC32_ForBytes 5 +../Core/Src/serial_control.c:157:10:calculate_crc32 1 +../Core/Src/serial_control.c:161:10:encode_packet 6 +../Core/Src/serial_control.c:194:6:SC_SendPacket 3 +../Core/Src/serial_control.c:211:9:process_received_packet 4 diff --git a/Debug/Core/Src/serial_handler.cyclo b/Debug/Core/Src/serial_handler.cyclo new file mode 100644 index 0000000..91fb07a --- /dev/null +++ b/Debug/Core/Src/serial_handler.cyclo @@ -0,0 +1,3 @@ +../Drivers/CMSIS/Include/core_cm3.h:1762:34:__NVIC_SystemReset 1 +../Core/Src/serial_handler.c:23:6:SC_CommandHandler 15 +../Core/Src/serial_handler.c:110:6:monitoring_data_callback 1 diff --git a/Debug/Core/Src/soft_rtc.cyclo b/Debug/Core/Src/soft_rtc.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/stm32f1xx_hal_msp.cyclo b/Debug/Core/Src/stm32f1xx_hal_msp.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/stm32f1xx_it.cyclo b/Debug/Core/Src/stm32f1xx_it.cyclo old mode 100755 new mode 100644 index aca5fab..69aba20 --- a/Debug/Core/Src/stm32f1xx_it.cyclo +++ b/Debug/Core/Src/stm32f1xx_it.cyclo @@ -1,13 +1,15 @@ -../Core/Src/stm32f1xx_it.c:71:6:NMI_Handler 1 -../Core/Src/stm32f1xx_it.c:86:6:HardFault_Handler 1 -../Core/Src/stm32f1xx_it.c:101:6:MemManage_Handler 1 -../Core/Src/stm32f1xx_it.c:116:6:BusFault_Handler 1 -../Core/Src/stm32f1xx_it.c:131:6:UsageFault_Handler 1 -../Core/Src/stm32f1xx_it.c:146:6:SVC_Handler 1 -../Core/Src/stm32f1xx_it.c:159:6:DebugMon_Handler 1 -../Core/Src/stm32f1xx_it.c:172:6:PendSV_Handler 1 -../Core/Src/stm32f1xx_it.c:185:6:SysTick_Handler 1 -../Core/Src/stm32f1xx_it.c:206:6:CAN1_RX0_IRQHandler 1 -../Core/Src/stm32f1xx_it.c:220:6:USART2_IRQHandler 1 -../Core/Src/stm32f1xx_it.c:234:6:CAN2_TX_IRQHandler 1 -../Core/Src/stm32f1xx_it.c:248:6:CAN2_RX1_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:73:6:NMI_Handler 1 +../Core/Src/stm32f1xx_it.c:88:6:HardFault_Handler 1 +../Core/Src/stm32f1xx_it.c:103:6:MemManage_Handler 1 +../Core/Src/stm32f1xx_it.c:118:6:BusFault_Handler 1 +../Core/Src/stm32f1xx_it.c:133:6:UsageFault_Handler 1 +../Core/Src/stm32f1xx_it.c:148:6:SVC_Handler 1 +../Core/Src/stm32f1xx_it.c:161:6:DebugMon_Handler 1 +../Core/Src/stm32f1xx_it.c:174:6:PendSV_Handler 1 +../Core/Src/stm32f1xx_it.c:187:6:SysTick_Handler 1 +../Core/Src/stm32f1xx_it.c:208:6:CAN1_RX0_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:222:6:USART1_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:236:6:USART2_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:250:6:USART3_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:264:6:CAN2_TX_IRQHandler 1 +../Core/Src/stm32f1xx_it.c:278:6:CAN2_RX1_IRQHandler 1 diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk index e4f8428..dcb5c58 100755 --- a/Debug/Core/Src/subdir.mk +++ b/Debug/Core/Src/subdir.mk @@ -1,6 +1,6 @@ ################################################################################ # Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (12.3.rel1) +# Toolchain: GNU Tools for STM32 (13.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables @@ -8,77 +8,98 @@ C_SRCS += \ ../Core/Src/adc.c \ ../Core/Src/board.c \ ../Core/Src/can.c \ +../Core/Src/charger_control.c \ ../Core/Src/charger_gbt.c \ ../Core/Src/connector.c \ +../Core/Src/crc.c \ ../Core/Src/debug.c \ -../Core/Src/edcan_handler_user.c \ ../Core/Src/gbt_packet.c \ ../Core/Src/gpio.c \ ../Core/Src/j1939.c \ ../Core/Src/lock.c \ ../Core/Src/main.c \ +../Core/Src/meter.c \ +../Core/Src/psu_control.c \ +../Core/Src/rgb_controller.c \ ../Core/Src/rtc.c \ +../Core/Src/serial_control.c \ +../Core/Src/serial_handler.c \ ../Core/Src/soft_rtc.c \ ../Core/Src/stm32f1xx_hal_msp.c \ ../Core/Src/stm32f1xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ ../Core/Src/system_stm32f1xx.c \ +../Core/Src/tim.c \ ../Core/Src/usart.c -OBJS += \ -./Core/Src/adc.o \ -./Core/Src/board.o \ -./Core/Src/can.o \ -./Core/Src/charger_gbt.o \ -./Core/Src/connector.o \ -./Core/Src/debug.o \ -./Core/Src/edcan_handler_user.o \ -./Core/Src/gbt_packet.o \ -./Core/Src/gpio.o \ -./Core/Src/j1939.o \ -./Core/Src/lock.o \ -./Core/Src/main.o \ -./Core/Src/rtc.o \ -./Core/Src/soft_rtc.o \ -./Core/Src/stm32f1xx_hal_msp.o \ -./Core/Src/stm32f1xx_it.o \ -./Core/Src/syscalls.o \ -./Core/Src/sysmem.o \ -./Core/Src/system_stm32f1xx.o \ -./Core/Src/usart.o - C_DEPS += \ ./Core/Src/adc.d \ ./Core/Src/board.d \ ./Core/Src/can.d \ +./Core/Src/charger_control.d \ ./Core/Src/charger_gbt.d \ ./Core/Src/connector.d \ +./Core/Src/crc.d \ ./Core/Src/debug.d \ -./Core/Src/edcan_handler_user.d \ ./Core/Src/gbt_packet.d \ ./Core/Src/gpio.d \ ./Core/Src/j1939.d \ ./Core/Src/lock.d \ ./Core/Src/main.d \ +./Core/Src/meter.d \ +./Core/Src/psu_control.d \ +./Core/Src/rgb_controller.d \ ./Core/Src/rtc.d \ +./Core/Src/serial_control.d \ +./Core/Src/serial_handler.d \ ./Core/Src/soft_rtc.d \ ./Core/Src/stm32f1xx_hal_msp.d \ ./Core/Src/stm32f1xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ ./Core/Src/system_stm32f1xx.d \ +./Core/Src/tim.d \ ./Core/Src/usart.d +OBJS += \ +./Core/Src/adc.o \ +./Core/Src/board.o \ +./Core/Src/can.o \ +./Core/Src/charger_control.o \ +./Core/Src/charger_gbt.o \ +./Core/Src/connector.o \ +./Core/Src/crc.o \ +./Core/Src/debug.o \ +./Core/Src/gbt_packet.o \ +./Core/Src/gpio.o \ +./Core/Src/j1939.o \ +./Core/Src/lock.o \ +./Core/Src/main.o \ +./Core/Src/meter.o \ +./Core/Src/psu_control.o \ +./Core/Src/rgb_controller.o \ +./Core/Src/rtc.o \ +./Core/Src/serial_control.o \ +./Core/Src/serial_handler.o \ +./Core/Src/soft_rtc.o \ +./Core/Src/stm32f1xx_hal_msp.o \ +./Core/Src/stm32f1xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f1xx.o \ +./Core/Src/tim.o \ +./Core/Src/usart.o + # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F107xC -c -I../Core/Inc -I/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F107xC -c -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: - -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/board.cyclo ./Core/Src/board.d ./Core/Src/board.o ./Core/Src/board.su ./Core/Src/can.cyclo ./Core/Src/can.d ./Core/Src/can.o ./Core/Src/can.su ./Core/Src/charger_gbt.cyclo ./Core/Src/charger_gbt.d ./Core/Src/charger_gbt.o ./Core/Src/charger_gbt.su ./Core/Src/connector.cyclo ./Core/Src/connector.d ./Core/Src/connector.o ./Core/Src/connector.su ./Core/Src/debug.cyclo ./Core/Src/debug.d ./Core/Src/debug.o ./Core/Src/debug.su ./Core/Src/edcan_handler_user.cyclo ./Core/Src/edcan_handler_user.d ./Core/Src/edcan_handler_user.o ./Core/Src/edcan_handler_user.su ./Core/Src/gbt_packet.cyclo ./Core/Src/gbt_packet.d ./Core/Src/gbt_packet.o ./Core/Src/gbt_packet.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/j1939.cyclo ./Core/Src/j1939.d ./Core/Src/j1939.o ./Core/Src/j1939.su ./Core/Src/lock.cyclo ./Core/Src/lock.d ./Core/Src/lock.o ./Core/Src/lock.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/rtc.cyclo ./Core/Src/rtc.d ./Core/Src/rtc.o ./Core/Src/rtc.su ./Core/Src/soft_rtc.cyclo ./Core/Src/soft_rtc.d ./Core/Src/soft_rtc.o ./Core/Src/soft_rtc.su ./Core/Src/stm32f1xx_hal_msp.cyclo ./Core/Src/stm32f1xx_hal_msp.d ./Core/Src/stm32f1xx_hal_msp.o ./Core/Src/stm32f1xx_hal_msp.su ./Core/Src/stm32f1xx_it.cyclo ./Core/Src/stm32f1xx_it.d ./Core/Src/stm32f1xx_it.o ./Core/Src/stm32f1xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f1xx.cyclo ./Core/Src/system_stm32f1xx.d ./Core/Src/system_stm32f1xx.o ./Core/Src/system_stm32f1xx.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su + -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/board.cyclo ./Core/Src/board.d ./Core/Src/board.o ./Core/Src/board.su ./Core/Src/can.cyclo ./Core/Src/can.d ./Core/Src/can.o ./Core/Src/can.su ./Core/Src/charger_control.cyclo ./Core/Src/charger_control.d ./Core/Src/charger_control.o ./Core/Src/charger_control.su ./Core/Src/charger_gbt.cyclo ./Core/Src/charger_gbt.d ./Core/Src/charger_gbt.o ./Core/Src/charger_gbt.su ./Core/Src/connector.cyclo ./Core/Src/connector.d ./Core/Src/connector.o ./Core/Src/connector.su ./Core/Src/crc.cyclo ./Core/Src/crc.d ./Core/Src/crc.o ./Core/Src/crc.su ./Core/Src/debug.cyclo ./Core/Src/debug.d ./Core/Src/debug.o ./Core/Src/debug.su ./Core/Src/gbt_packet.cyclo ./Core/Src/gbt_packet.d ./Core/Src/gbt_packet.o ./Core/Src/gbt_packet.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/j1939.cyclo ./Core/Src/j1939.d ./Core/Src/j1939.o ./Core/Src/j1939.su ./Core/Src/lock.cyclo ./Core/Src/lock.d ./Core/Src/lock.o ./Core/Src/lock.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/meter.cyclo ./Core/Src/meter.d ./Core/Src/meter.o ./Core/Src/meter.su ./Core/Src/psu_control.cyclo ./Core/Src/psu_control.d ./Core/Src/psu_control.o ./Core/Src/psu_control.su ./Core/Src/rgb_controller.cyclo ./Core/Src/rgb_controller.d ./Core/Src/rgb_controller.o ./Core/Src/rgb_controller.su ./Core/Src/rtc.cyclo ./Core/Src/rtc.d ./Core/Src/rtc.o ./Core/Src/rtc.su ./Core/Src/serial_control.cyclo ./Core/Src/serial_control.d ./Core/Src/serial_control.o ./Core/Src/serial_control.su ./Core/Src/serial_handler.cyclo ./Core/Src/serial_handler.d ./Core/Src/serial_handler.o ./Core/Src/serial_handler.su ./Core/Src/soft_rtc.cyclo ./Core/Src/soft_rtc.d ./Core/Src/soft_rtc.o ./Core/Src/soft_rtc.su ./Core/Src/stm32f1xx_hal_msp.cyclo ./Core/Src/stm32f1xx_hal_msp.d ./Core/Src/stm32f1xx_hal_msp.o ./Core/Src/stm32f1xx_hal_msp.su ./Core/Src/stm32f1xx_it.cyclo ./Core/Src/stm32f1xx_it.d ./Core/Src/stm32f1xx_it.o ./Core/Src/stm32f1xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f1xx.cyclo ./Core/Src/system_stm32f1xx.d ./Core/Src/system_stm32f1xx.o ./Core/Src/system_stm32f1xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su .PHONY: clean-Core-2f-Src diff --git a/Debug/Core/Src/syscalls.cyclo b/Debug/Core/Src/syscalls.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/sysmem.cyclo b/Debug/Core/Src/sysmem.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/system_stm32f1xx.cyclo b/Debug/Core/Src/system_stm32f1xx.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Core/Src/tim.cyclo b/Debug/Core/Src/tim.cyclo new file mode 100644 index 0000000..ccc1d1c --- /dev/null +++ b/Debug/Core/Src/tim.cyclo @@ -0,0 +1,4 @@ +../Core/Src/tim.c:30:6:MX_TIM4_Init 8 +../Core/Src/tim.c:92:6:HAL_TIM_Base_MspInit 2 +../Core/Src/tim.c:107:6:HAL_TIM_MspPostInit 2 +../Core/Src/tim.c:137:6:HAL_TIM_Base_MspDeInit 2 diff --git a/Debug/Core/Src/usart.cyclo b/Debug/Core/Src/usart.cyclo old mode 100755 new mode 100644 index 4e75865..62bf258 --- a/Debug/Core/Src/usart.cyclo +++ b/Debug/Core/Src/usart.cyclo @@ -1,3 +1,6 @@ -../Core/Src/usart.c:31:6:MX_USART2_UART_Init 2 -../Core/Src/usart.c:59:6:HAL_UART_MspInit 2 -../Core/Src/usart.c:97:6:HAL_UART_MspDeInit 2 +../Core/Src/usart.c:33:6:MX_UART5_Init 2 +../Core/Src/usart.c:62:6:MX_USART1_UART_Init 2 +../Core/Src/usart.c:91:6:MX_USART2_UART_Init 2 +../Core/Src/usart.c:120:6:MX_USART3_UART_Init 2 +../Core/Src/usart.c:148:6:HAL_UART_MspInit 5 +../Core/Src/usart.c:276:6:HAL_UART_MspDeInit 5 diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk index 7b9168c..8377175 100755 --- a/Debug/Core/Startup/subdir.mk +++ b/Debug/Core/Startup/subdir.mk @@ -1,18 +1,18 @@ ################################################################################ # Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (12.3.rel1) +# Toolchain: GNU Tools for STM32 (13.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables S_SRCS += \ ../Core/Startup/startup_stm32f107vctx.s -OBJS += \ -./Core/Startup/startup_stm32f107vctx.o - S_DEPS += \ ./Core/Startup/startup_stm32f107vctx.d +OBJS += \ +./Core/Startup/startup_stm32f107vctx.o + # Each subdirectory must supply rules for building sources it contributes Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk diff --git a/Debug/Drivers/.DS_Store b/Debug/Drivers/.DS_Store new file mode 100644 index 0000000..444b325 Binary files /dev/null and b/Debug/Drivers/.DS_Store differ diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo old mode 100755 new mode 100644 index 9570d3e..8ac57cf --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo @@ -7,19 +7,19 @@ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:304:17:HAL_GetTick 1 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:313:10:HAL_GetTickPrio 1 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:322:19:HAL_SetTickFreq 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:354:21:HAL_GetTickFreq 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:370:13:HAL_Delay 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:396:13:HAL_SuspendTick 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:412:13:HAL_ResumeTick 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:422:10:HAL_GetHalVersion 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:438:10:HAL_GetREVID 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:454:10:HAL_GetDEVID 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:463:10:HAL_GetUIDw0 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:472:10:HAL_GetUIDw1 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:481:10:HAL_GetUIDw2 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:490:6:HAL_DBGMCU_EnableDBGSleepMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:506:6:HAL_DBGMCU_DisableDBGSleepMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:536:6:HAL_DBGMCU_EnableDBGStopMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:552:6:HAL_DBGMCU_DisableDBGStopMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:568:6:HAL_DBGMCU_EnableDBGStandbyMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:584:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:355:21:HAL_GetTickFreq 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:371:13:HAL_Delay 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:397:13:HAL_SuspendTick 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:413:13:HAL_ResumeTick 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:423:10:HAL_GetHalVersion 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:439:10:HAL_GetREVID 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:455:10:HAL_GetDEVID 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:464:10:HAL_GetUIDw0 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:473:10:HAL_GetUIDw1 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:482:10:HAL_GetUIDw2 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:491:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:507:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:537:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:553:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:569:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c:585:6:HAL_DBGMCU_DisableDBGStandbyMode 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo old mode 100755 new mode 100644 index 889243f..2c3b962 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo @@ -1,27 +1,27 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:421:19:HAL_ADC_Init 12 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:639:19:HAL_ADC_DeInit 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:787:13:HAL_ADC_MspInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:801:13:HAL_ADC_MspDeInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1046:19:HAL_ADC_Start 13 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1159:19:HAL_ADC_Stop 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1203:19:HAL_ADC_PollForConversion 25 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1342:19:HAL_ADC_PollForEvent 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1395:19:HAL_ADC_Start_IT 13 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1506:19:HAL_ADC_Stop_IT 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1563:19:HAL_ADC_Start_DMA 14 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1704:19:HAL_ADC_Stop_DMA 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1772:10:HAL_ADC_GetValue 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1789:6:HAL_ADC_IRQHandler 17 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1916:13:HAL_ADC_ConvCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1930:13:HAL_ADC_ConvHalfCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1944:13:HAL_ADC_LevelOutOfWindowCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1959:13:HAL_ADC_ErrorCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2007:19:HAL_ADC_ConfigChannel 11 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2117:19:HAL_ADC_AnalogWDGConfig 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2204:10:HAL_ADC_GetState 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2215:10:HAL_ADC_GetError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2239:19:ADC_Enable 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2298:19:ADC_ConversionStop_Disable 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2340:6:ADC_DMAConvCplt 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2387:6:ADC_DMAHalfConvCplt 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2405:6:ADC_DMAError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:411:19:HAL_ADC_Init 12 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:629:19:HAL_ADC_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:777:13:HAL_ADC_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:791:13:HAL_ADC_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1036:19:HAL_ADC_Start 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1149:19:HAL_ADC_Stop 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1193:19:HAL_ADC_PollForConversion 25 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1332:19:HAL_ADC_PollForEvent 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1385:19:HAL_ADC_Start_IT 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1496:19:HAL_ADC_Stop_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1553:19:HAL_ADC_Start_DMA 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1694:19:HAL_ADC_Stop_DMA 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1762:10:HAL_ADC_GetValue 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1779:6:HAL_ADC_IRQHandler 17 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1909:13:HAL_ADC_ConvCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1923:13:HAL_ADC_ConvHalfCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1937:13:HAL_ADC_LevelOutOfWindowCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:1952:13:HAL_ADC_ErrorCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2000:19:HAL_ADC_ConfigChannel 11 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2110:19:HAL_ADC_AnalogWDGConfig 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2197:10:HAL_ADC_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2208:10:HAL_ADC_GetError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2232:19:ADC_Enable 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2291:19:ADC_ConversionStop_Disable 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2333:6:ADC_DMAConvCplt 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2380:6:ADC_DMAHalfConvCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c:2398:6:ADC_DMAError 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo old mode 100755 new mode 100644 index 473073d..88d1e93 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo @@ -1,13 +1,13 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:126:19:HAL_ADCEx_Calibration_Start 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:239:19:HAL_ADCEx_InjectedStart 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:338:19:HAL_ADCEx_InjectedStop 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:391:19:HAL_ADCEx_InjectedPollForConversion 25 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:517:19:HAL_ADCEx_InjectedStart_IT 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:616:19:HAL_ADCEx_InjectedStop_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:685:19:HAL_ADCEx_MultiModeStart_DMA 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:811:19:HAL_ADCEx_MultiModeStop_DMA 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:899:10:HAL_ADCEx_InjectedGetValue 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:936:10:HAL_ADCEx_MultiModeGetValue 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:968:13:HAL_ADCEx_InjectedConvCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:1010:19:HAL_ADCEx_InjectedConfigChannel 23 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:1271:19:HAL_ADCEx_MultiModeConfigChannel 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:119:19:HAL_ADCEx_Calibration_Start 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:229:19:HAL_ADCEx_InjectedStart 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:328:19:HAL_ADCEx_InjectedStop 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:381:19:HAL_ADCEx_InjectedPollForConversion 25 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:507:19:HAL_ADCEx_InjectedStart_IT 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:606:19:HAL_ADCEx_InjectedStop_IT 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:675:19:HAL_ADCEx_MultiModeStart_DMA 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:801:19:HAL_ADCEx_MultiModeStop_DMA 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:889:10:HAL_ADCEx_InjectedGetValue 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:926:10:HAL_ADCEx_MultiModeGetValue 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:958:13:HAL_ADCEx_InjectedConvCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:1000:19:HAL_ADCEx_InjectedConfigChannel 23 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c:1261:19:HAL_ADCEx_MultiModeConfigChannel 5 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo old mode 100755 new mode 100644 index 57bae32..cafa16e --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo @@ -1,36 +1,36 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:274:19:HAL_CAN_Init 13 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:459:19:HAL_CAN_DeInit 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:506:13:HAL_CAN_MspInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:522:13:HAL_CAN_MspDeInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:838:19:HAL_CAN_ConfigFilter 8 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1004:19:HAL_CAN_Start 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1056:19:HAL_CAN_Stop 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1111:19:HAL_CAN_RequestSleep 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1142:19:HAL_CAN_WakeUp 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:275:19:HAL_CAN_Init 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:460:19:HAL_CAN_DeInit 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:507:13:HAL_CAN_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:523:13:HAL_CAN_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:840:19:HAL_CAN_ConfigFilter 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1006:19:HAL_CAN_Start 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1058:19:HAL_CAN_Stop 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1113:19:HAL_CAN_RequestSleep 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1144:19:HAL_CAN_WakeUp 5 ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1191:10:HAL_CAN_IsSleepActive 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1222:19:HAL_CAN_AddTxMessage 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1330:19:HAL_CAN_AbortTxRequest 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1379:10:HAL_CAN_GetTxMailboxesFreeLevel 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1422:10:HAL_CAN_IsTxMessagePending 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1454:10:HAL_CAN_GetTxTimestamp 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1488:19:HAL_CAN_GetRxMessage 8 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1578:10:HAL_CAN_GetRxFifoFillLevel 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1631:19:HAL_CAN_ActivateNotification 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1664:19:HAL_CAN_DeactivateNotification 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1695:6:HAL_CAN_IRQHandler 51 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2106:13:HAL_CAN_TxMailbox0CompleteCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2123:13:HAL_CAN_TxMailbox1CompleteCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2140:13:HAL_CAN_TxMailbox2CompleteCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2157:13:HAL_CAN_TxMailbox0AbortCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2174:13:HAL_CAN_TxMailbox1AbortCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2191:13:HAL_CAN_TxMailbox2AbortCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2208:13:HAL_CAN_RxFifo0MsgPendingCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2225:13:HAL_CAN_RxFifo0FullCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2242:13:HAL_CAN_RxFifo1MsgPendingCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2259:13:HAL_CAN_RxFifo1FullCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2276:13:HAL_CAN_SleepCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2292:13:HAL_CAN_WakeUpFromRxMsgCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2309:13:HAL_CAN_ErrorCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2346:22:HAL_CAN_GetState 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2381:10:HAL_CAN_GetError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2393:19:HAL_CAN_ResetError 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1222:19:HAL_CAN_AddTxMessage 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1322:19:HAL_CAN_AbortTxRequest 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1371:10:HAL_CAN_GetTxMailboxesFreeLevel 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1414:10:HAL_CAN_IsTxMessagePending 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1446:10:HAL_CAN_GetTxTimestamp 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1480:19:HAL_CAN_GetRxMessage 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1580:10:HAL_CAN_GetRxFifoFillLevel 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1633:19:HAL_CAN_ActivateNotification 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1666:19:HAL_CAN_DeactivateNotification 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:1697:6:HAL_CAN_IRQHandler 51 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2108:13:HAL_CAN_TxMailbox0CompleteCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2125:13:HAL_CAN_TxMailbox1CompleteCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2142:13:HAL_CAN_TxMailbox2CompleteCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2159:13:HAL_CAN_TxMailbox0AbortCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2176:13:HAL_CAN_TxMailbox1AbortCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2193:13:HAL_CAN_TxMailbox2AbortCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2210:13:HAL_CAN_RxFifo0MsgPendingCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2227:13:HAL_CAN_RxFifo0FullCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2244:13:HAL_CAN_RxFifo1MsgPendingCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2261:13:HAL_CAN_RxFifo1FullCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2278:13:HAL_CAN_SleepCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2294:13:HAL_CAN_WakeUpFromRxMsgCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2311:13:HAL_CAN_ErrorCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2348:22:HAL_CAN_GetState 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2383:10:HAL_CAN_GetError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c:2395:19:HAL_CAN_ResetError 3 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo old mode 100755 new mode 100644 index 1957771..5f7cf8b --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo @@ -12,18 +12,18 @@ ../Drivers/CMSIS/Include/core_cm3.h:1713:22:NVIC_DecodePriority 2 ../Drivers/CMSIS/Include/core_cm3.h:1762:34:__NVIC_SystemReset 1 ../Drivers/CMSIS/Include/core_cm3.h:1834:26:SysTick_Config 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:143:6:HAL_NVIC_SetPriorityGrouping 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:165:6:HAL_NVIC_SetPriority 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:187:6:HAL_NVIC_EnableIRQ 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:203:6:HAL_NVIC_DisableIRQ 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:216:6:HAL_NVIC_SystemReset 0 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:229:10:HAL_SYSTICK_Config 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:344:10:HAL_NVIC_GetPriorityGrouping 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:371:6:HAL_NVIC_GetPriority 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:386:6:HAL_NVIC_SetPendingIRQ 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:404:10:HAL_NVIC_GetPendingIRQ 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:420:6:HAL_NVIC_ClearPendingIRQ 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:437:10:HAL_NVIC_GetActive 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:454:6:HAL_SYSTICK_CLKSourceConfig 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:472:6:HAL_SYSTICK_IRQHandler 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:481:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:228:10:HAL_SYSTICK_Config 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:369:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:396:6:HAL_NVIC_GetPriority 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:411:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:429:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:445:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:462:10:HAL_NVIC_GetActive 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:479:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:497:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c:506:13:HAL_SYSTICK_Callback 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.cyclo new file mode 100644 index 0000000..33703e3 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:95:19:HAL_CRC_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:126:19:HAL_CRC_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:170:13:HAL_CRC_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:185:13:HAL_CRC_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:227:10:HAL_CRC_Accumulate 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:257:10:HAL_CRC_Calculate 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c:306:22:HAL_CRC_GetState 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo old mode 100755 new mode 100644 index a9560f9..56a3830 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo @@ -1,13 +1,13 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:143:19:HAL_DMA_Init 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:220:19:HAL_DMA_DeInit 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:319:19:HAL_DMA_Start 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:362:19:HAL_DMA_Start_IT 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:416:19:HAL_DMA_Abort 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:457:19:HAL_DMA_Abort_IT 26 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:502:19:HAL_DMA_PollForTransfer 102 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:603:6:HAL_DMA_IRQHandler 58 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:693:19:HAL_DMA_RegisterCallback 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:744:19:HAL_DMA_UnRegisterCallback 8 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:820:22:HAL_DMA_GetState 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:832:10:HAL_DMA_GetError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:858:13:DMA_SetConfig 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:142:19:HAL_DMA_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:219:19:HAL_DMA_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:318:19:HAL_DMA_Start 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:361:19:HAL_DMA_Start_IT 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:415:19:HAL_DMA_Abort 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:456:19:HAL_DMA_Abort_IT 26 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:501:19:HAL_DMA_PollForTransfer 102 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:602:6:HAL_DMA_IRQHandler 58 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:692:19:HAL_DMA_RegisterCallback 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:743:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:819:22:HAL_DMA_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:831:10:HAL_DMA_GetError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c:857:13:DMA_SetConfig 2 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo old mode 100755 new mode 100644 index cf51798..633b181 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo @@ -1,9 +1,9 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:317:19:HAL_EXTI_ClearConfigLine 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:370:19:HAL_EXTI_RegisterCallback 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:395:19:HAL_EXTI_GetHandle 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:435:6:HAL_EXTI_IRQHandler 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:467:10:HAL_EXTI_GetPending 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:499:6:HAL_EXTI_ClearPending 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:523:6:HAL_EXTI_GenerateSWI 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:466:10:HAL_EXTI_GetPending 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo old mode 100755 new mode 100644 index b79e62a..6f8a0a9 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo @@ -1,14 +1,14 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:168:19:HAL_FLASH_Program 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:267:19:HAL_FLASH_Program_IT 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:332:6:HAL_FLASH_IRQHandler 12 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:606:13:HAL_FLASH_EndOfOperationCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:624:13:HAL_FLASH_OperationErrorCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:657:19:HAL_FLASH_Unlock 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:695:19:HAL_FLASH_Lock 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:712:19:HAL_FLASH_OB_Unlock 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:732:19:HAL_FLASH_OB_Lock 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:745:6:HAL_FLASH_OB_Launch 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:774:10:HAL_FLASH_GetError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:797:13:FLASH_Program_HalfWord 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:826:19:FLASH_WaitForLastOperation 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:914:13:FLASH_SetErrorCode 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:166:19:HAL_FLASH_Program 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:265:19:HAL_FLASH_Program_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:327:6:HAL_FLASH_IRQHandler 12 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:599:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:617:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:650:19:HAL_FLASH_Unlock 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:688:19:HAL_FLASH_Lock 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:705:19:HAL_FLASH_OB_Unlock 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:725:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:738:6:HAL_FLASH_OB_Launch 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:767:10:HAL_FLASH_GetError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:790:13:FLASH_Program_HalfWord 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:819:19:FLASH_WaitForLastOperation 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c:907:13:FLASH_SetErrorCode 5 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo old mode 100755 new mode 100644 index 07d971c..7f86e1e --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo @@ -1,16 +1,16 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:319:19:HAL_FLASHEx_Erase_IT 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:397:19:HAL_FLASHEx_OBErase 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:446:19:HAL_FLASHEx_OBProgram 11 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:527:6:HAL_FLASHEx_OBGetConfig 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:549:10:HAL_FLASHEx_OBGetUserData 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:595:13:FLASH_MassErase 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:644:26:FLASH_OB_EnableWRP 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:767:26:FLASH_OB_DisableWRP 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:886:26:FLASH_OB_RDP_LevelConfig 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:937:26:FLASH_OB_UserConfig 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:988:26:FLASH_OB_ProgramData 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1021:17:FLASH_OB_GetWRP 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1034:17:FLASH_OB_GetRDP 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1060:16:FLASH_OB_GetUser 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1089:6:FLASH_PageErase 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:157:19:HAL_FLASHEx_Erase 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:317:19:HAL_FLASHEx_Erase_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:392:19:HAL_FLASHEx_OBErase 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:441:19:HAL_FLASHEx_OBProgram 11 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:522:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:544:10:HAL_FLASHEx_OBGetUserData 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:590:13:FLASH_MassErase 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:639:26:FLASH_OB_EnableWRP 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:762:26:FLASH_OB_DisableWRP 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:881:26:FLASH_OB_RDP_LevelConfig 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:932:26:FLASH_OB_UserConfig 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:983:26:FLASH_OB_ProgramData 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1016:17:FLASH_OB_GetWRP 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1029:17:FLASH_OB_GetRDP 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1055:16:FLASH_OB_GetUser 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c:1084:6:FLASH_PageErase 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo old mode 100755 new mode 100644 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo old mode 100755 new mode 100644 index eac00c4..eb782db --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo @@ -1,18 +1,18 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:117:13:PWR_OverloadWfe 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:156:6:HAL_PWR_DeInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:169:6:HAL_PWR_EnableBkUpAccess 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:182:6:HAL_PWR_DisableBkUpAccess 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:316:6:HAL_PWR_ConfigPVD 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:359:6:HAL_PWR_EnablePVD 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:369:6:HAL_PWR_DisablePVD 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:382:6:HAL_PWR_EnableWakeUpPin 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:397:6:HAL_PWR_DisableWakeUpPin 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:417:6:HAL_PWR_EnterSLEEPMode 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:463:6:HAL_PWR_EnterSTOPMode 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:503:6:HAL_PWR_EnterSTANDBYMode 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:528:6:HAL_PWR_EnableSleepOnExit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:541:6:HAL_PWR_DisableSleepOnExit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:554:6:HAL_PWR_EnableSEVOnPend 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:567:6:HAL_PWR_DisableSEVOnPend 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:580:6:HAL_PWR_PVD_IRQHandler 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:597:13:HAL_PWR_PVDCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:116:13:PWR_OverloadWfe 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:155:6:HAL_PWR_DeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:168:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:181:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:315:6:HAL_PWR_ConfigPVD 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:358:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:368:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:381:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:396:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:416:6:HAL_PWR_EnterSLEEPMode 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:462:6:HAL_PWR_EnterSTOPMode 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:502:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:527:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:540:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:553:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:566:6:HAL_PWR_DisableSEVOnPend 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:579:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c:596:13:HAL_PWR_PVDCallback 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo old mode 100755 new mode 100644 index 1f06f55..6d7f1d6 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo @@ -1,15 +1,15 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:202:19:HAL_RCC_DeInit 14 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:347:19:HAL_RCC_OscConfig 73 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:813:19:HAL_RCC_ClockConfig 19 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1002:6:HAL_RCC_MCOConfig 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1039:6:HAL_RCC_EnableCSS 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1048:6:HAL_RCC_DisableCSS 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1082:10:HAL_RCC_GetSysClockFreq 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1176:10:HAL_RCC_GetHCLKFreq 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1187:10:HAL_RCC_GetPCLK1Freq 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1199:10:HAL_RCC_GetPCLK2Freq 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1212:6:HAL_RCC_GetOscConfig 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1312:6:HAL_RCC_GetClockConfig 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1347:6:HAL_RCC_NMI_IRQHandler 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1365:13:RCC_Delay 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1379:13:HAL_RCC_CSSCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:200:19:HAL_RCC_DeInit 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:345:19:HAL_RCC_OscConfig 73 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:811:19:HAL_RCC_ClockConfig 19 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1000:6:HAL_RCC_MCOConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1037:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1046:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1080:10:HAL_RCC_GetSysClockFreq 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1174:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1185:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1197:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1210:6:HAL_RCC_GetOscConfig 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1310:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1345:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1363:13:RCC_Delay 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c:1377:13:HAL_RCC_CSSCallback 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo old mode 100755 new mode 100644 index 6ff2f76..f8c081f --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo @@ -1,7 +1,7 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:100:19:HAL_RCCEx_PeriphCLKConfig 25 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:294:6:HAL_RCCEx_GetPeriphCLKConfig 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:387:10:HAL_RCCEx_GetPeriphCLKFreq 21 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:613:19:HAL_RCCEx_EnablePLLI2S 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:683:19:HAL_RCCEx_DisablePLLI2S 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:739:19:HAL_RCCEx_EnablePLL2 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:810:19:HAL_RCCEx_DisablePLL2 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:98:19:HAL_RCCEx_PeriphCLKConfig 25 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:292:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:385:10:HAL_RCCEx_GetPeriphCLKFreq 21 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:611:19:HAL_RCCEx_EnablePLLI2S 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:681:19:HAL_RCCEx_DisablePLLI2S 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:737:19:HAL_RCCEx_EnablePLL2 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c:808:19:HAL_RCCEx_DisablePLL2 6 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo old mode 100755 new mode 100644 index f5d4547..bc26cfd --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo @@ -1,28 +1,28 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:275:19:HAL_RTC_Init 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:411:19:HAL_RTC_DeInit 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:650:13:HAL_RTC_MspInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:665:13:HAL_RTC_MspDeInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:703:19:HAL_RTC_SetTime 9 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:802:19:HAL_RTC_GetTime 12 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:913:19:HAL_RTC_SetDate 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1027:19:HAL_RTC_GetDate 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1092:19:HAL_RTC_SetAlarm 8 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1184:19:HAL_RTC_SetAlarm_IT 8 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1289:19:HAL_RTC_GetAlarm 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1334:19:HAL_RTC_DeactivateAlarm 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1404:6:HAL_RTC_AlarmIRQHandler 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1436:13:HAL_RTC_AlarmAEventCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1452:19:HAL_RTC_PollForAlarmAEvent 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1507:21:HAL_RTC_GetState 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1540:19:HAL_RTC_WaitForSynchro 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1587:17:RTC_ReadTimeCounter 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1619:26:RTC_WriteTimeCounter 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1651:17:RTC_ReadAlarmCounter 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1668:26:RTC_WriteAlarmCounter 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1700:26:RTC_EnterInitMode 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1727:26:RTC_ExitInitMode 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1752:16:RTC_ByteToBcd2 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1770:16:RTC_Bcd2ToByte 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1784:13:RTC_DateUpdate 21 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1879:16:RTC_IsLeapYear 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1916:16:RTC_WeekDayNum 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:276:19:HAL_RTC_Init 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:412:19:HAL_RTC_DeInit 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:651:13:HAL_RTC_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:666:13:HAL_RTC_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:704:19:HAL_RTC_SetTime 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:803:19:HAL_RTC_GetTime 12 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:914:19:HAL_RTC_SetDate 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1028:19:HAL_RTC_GetDate 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1093:19:HAL_RTC_SetAlarm 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1185:19:HAL_RTC_SetAlarm_IT 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1290:19:HAL_RTC_GetAlarm 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1335:19:HAL_RTC_DeactivateAlarm 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1405:6:HAL_RTC_AlarmIRQHandler 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1437:13:HAL_RTC_AlarmAEventCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1453:19:HAL_RTC_PollForAlarmAEvent 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1508:21:HAL_RTC_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1541:19:HAL_RTC_WaitForSynchro 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1588:17:RTC_ReadTimeCounter 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1620:26:RTC_WriteTimeCounter 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1652:17:RTC_ReadAlarmCounter 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1669:26:RTC_WriteAlarmCounter 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1701:26:RTC_EnterInitMode 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1728:26:RTC_ExitInitMode 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1753:16:RTC_ByteToBcd2 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1771:16:RTC_Bcd2ToByte 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1785:13:RTC_DateUpdate 21 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1880:16:RTC_IsLeapYear 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c:1917:16:RTC_WeekDayNum 2 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo old mode 100755 new mode 100644 index 4032a87..cf9dc35 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo @@ -1,14 +1,14 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:81:19:HAL_RTCEx_SetTamper 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:127:19:HAL_RTCEx_SetTamper_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:175:19:HAL_RTCEx_DeactivateTamper 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:217:6:HAL_RTCEx_TamperIRQHandler 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:247:13:HAL_RTCEx_Tamper1EventCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:263:19:HAL_RTCEx_PollForTamper1Event 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:319:19:HAL_RTCEx_SetSecond_IT 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:349:19:HAL_RTCEx_DeactivateSecond 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:379:6:HAL_RTCEx_RTCIRQHandler 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:419:13:HAL_RTCEx_RTCEventCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:434:13:HAL_RTCEx_RTCEventErrorCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:474:6:HAL_RTCEx_BKUPWrite 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:499:10:HAL_RTCEx_BKUPRead 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:529:19:HAL_RTCEx_SetSmoothCalib 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:80:19:HAL_RTCEx_SetTamper 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:126:19:HAL_RTCEx_SetTamper_IT 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:174:19:HAL_RTCEx_DeactivateTamper 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:216:6:HAL_RTCEx_TamperIRQHandler 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:246:13:HAL_RTCEx_Tamper1EventCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:262:19:HAL_RTCEx_PollForTamper1Event 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:318:19:HAL_RTCEx_SetSecond_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:348:19:HAL_RTCEx_DeactivateSecond 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:378:6:HAL_RTCEx_RTCIRQHandler 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:418:13:HAL_RTCEx_RTCEventCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:433:13:HAL_RTCEx_RTCEventErrorCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:473:6:HAL_RTCEx_BKUPWrite 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:498:10:HAL_RTCEx_BKUPRead 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c:528:19:HAL_RTCEx_SetSmoothCalib 3 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo old mode 100755 new mode 100644 index e69de29..e7f7ebc --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo @@ -0,0 +1,119 @@ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:266:19:HAL_TIM_Base_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:400:19:HAL_TIM_Base_Start 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 12 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:650:19:HAL_TIM_OC_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:789:19:HAL_TIM_OC_Start 15 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 20 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 30 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 15 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 20 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 30 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 21 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 26 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 33 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3133:19:HAL_TIM_Encoder_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:3178:13:HAL_TIM_Encoder_MspInit 1 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+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6388:22:HAL_TIM_Encoder_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6398:23:HAL_TIM_GetActiveChannel 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6416:29:HAL_TIM_GetChannelState 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6433:30:HAL_TIM_DMABurstState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6458:6:TIM_DMAError 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6501:13:TIM_DMADelayPulseCplt 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6560:6:TIM_DMADelayPulseHalfCplt 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6599:6:TIM_DMACaptureCplt 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6662:6:TIM_DMACaptureHalfCplt 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6701:13:TIM_DMAPeriodElapsedCplt 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6722:13:TIM_DMAPeriodElapsedHalfCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6738:13:TIM_DMATriggerCplt 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6759:13:TIM_DMATriggerHalfCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6776:6:TIM_Base_SetConfig 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6831:13:TIM_OC1_SetConfig 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6907:6:TIM_OC2_SetConfig 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:6983:13:TIM_OC3_SetConfig 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7058:13:TIM_OC4_SetConfig 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7119:26:TIM_SlaveTimer_SetConfig 16 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7253:6:TIM_TI1_SetConfig 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7300:13:TIM_TI1_ConfigInputStage 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7343:13:TIM_TI2_SetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7383:13:TIM_TI2_ConfigInputStage 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7425:13:TIM_TI3_SetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7472:13:TIM_TI4_SetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo old mode 100755 new mode 100644 index e69de29..c685cd4 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 11 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 11 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 19 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 28 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 19 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 14 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 28 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 13 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2062:19:HAL_TIMEx_RemapConfig 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2096:13:HAL_TIMEx_CommutCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2110:13:HAL_TIMEx_CommutHalfCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2125:13:HAL_TIMEx_BreakCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2158:22:HAL_TIMEx_HallSensor_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2173:29:HAL_TIMEx_GetChannelNState 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2202:6:TIMEx_DMACommutationCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2221:6:TIMEx_DMACommutationHalfCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2241:13:TIM_DMADelayPulseNCplt 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2291:13:TIM_DMAErrorCCxN 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c:2336:13:TIM_CCxNChannelCmd 1 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo old mode 100755 new mode 100644 index 8afafd1..84d4131 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo @@ -1,61 +1,62 @@ -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:352:19:HAL_UART_Init 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:429:19:HAL_HalfDuplex_Init 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:504:19:HAL_LIN_Init 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:587:19:HAL_MultiProcessor_Init 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:666:19:HAL_UART_DeInit 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:711:13:HAL_UART_MspInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:726:13:HAL_UART_MspDeInit 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1136:19:HAL_UART_Transmit 11 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1224:19:HAL_UART_Receive 13 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1315:19:HAL_UART_Transmit_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1360:19:HAL_UART_Receive_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1395:19:HAL_UART_Transmit_DMA 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1463:19:HAL_UART_Receive_DMA 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1493:19:HAL_UART_DMAPause 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1530:19:HAL_UART_DMAResume 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1566:19:HAL_UART_DMAStop 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1621:19:HAL_UARTEx_ReceiveToIdle 18 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1747:19:HAL_UARTEx_ReceiveToIdle_IT 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1808:19:HAL_UARTEx_ReceiveToIdle_DMA 7 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1865:19:HAL_UART_Abort 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1954:19:HAL_UART_AbortTransmit 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2005:19:HAL_UART_AbortReceive 6 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2066:19:HAL_UART_Abort_IT 13 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2201:19:HAL_UART_AbortTransmit_IT 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2278:19:HAL_UART_AbortReceive_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2356:6:HAL_UART_IRQHandler 37 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2586:13:HAL_UART_TxCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2601:13:HAL_UART_TxHalfCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2616:13:HAL_UART_RxCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2631:13:HAL_UART_RxHalfCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2646:13:HAL_UART_ErrorCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2660:13:HAL_UART_AbortCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2675:13:HAL_UART_AbortTransmitCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2690:13:HAL_UART_AbortReceiveCpltCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2707:13:HAL_UARTEx_RxEventCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2747:19:HAL_LIN_SendBreak 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2774:19:HAL_MultiProcessor_EnterMuteMode 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2801:19:HAL_MultiProcessor_ExitMuteMode 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2828:19:HAL_HalfDuplex_EnableTransmitter 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2863:19:HAL_HalfDuplex_EnableReceiver 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2920:23:HAL_UART_GetState 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2935:10:HAL_UART_GetError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2980:13:UART_DMATransmitCplt 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3015:13:UART_DMATxHalfCplt 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3034:13:UART_DMAReceiveCplt 4 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3091:13:UART_DMARxHalfCplt 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3126:13:UART_DMAError 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3167:26:UART_WaitOnFlagUntilTimeout 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3205:19:UART_Start_Receive_IT 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3240:19:UART_Start_Receive_DMA 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3290:13:UART_EndTxTransfer 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3304:13:UART_EndRxTransfer 2 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3328:13:UART_DMAAbortOnError 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3352:13:UART_DMATxAbortCallback 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3398:13:UART_DMARxAbortCallback 3 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3444:13:UART_DMATxOnlyAbortCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3472:13:UART_DMARxOnlyAbortCallback 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3498:26:UART_Transmit_IT 5 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3538:26:UART_EndTransmit_IT 1 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3563:26:UART_Receive_IT 10 -../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3661:13:UART_SetConfig 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:354:19:HAL_UART_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:432:19:HAL_HalfDuplex_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:508:19:HAL_LIN_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:592:19:HAL_MultiProcessor_Init 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:672:19:HAL_UART_DeInit 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:718:13:HAL_UART_MspInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:733:13:HAL_UART_MspDeInit 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1138:19:HAL_UART_Transmit 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1224:19:HAL_UART_Receive 12 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1311:19:HAL_UART_Transmit_IT 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1350:19:HAL_UART_Receive_IT 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1382:19:HAL_UART_Transmit_DMA 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1444:19:HAL_UART_Receive_DMA 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1471:19:HAL_UART_DMAPause 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1502:19:HAL_UART_DMAResume 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1536:19:HAL_UART_DMAStop 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1591:19:HAL_UARTEx_ReceiveToIdle 17 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1716:19:HAL_UARTEx_ReceiveToIdle_IT 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1776:19:HAL_UARTEx_ReceiveToIdle_DMA 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1841:29:HAL_UARTEx_GetRxEventType 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1859:19:HAL_UART_Abort 15 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1948:19:HAL_UART_AbortTransmit 7 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:1999:19:HAL_UART_AbortReceive 10 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2060:19:HAL_UART_Abort_IT 18 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2195:19:HAL_UART_AbortTransmit_IT 6 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2272:19:HAL_UART_AbortReceive_IT 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2350:6:HAL_UART_IRQHandler 45 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2592:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2607:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2622:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2637:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2652:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2666:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2681:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2696:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2713:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2753:19:HAL_LIN_SendBreak 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2780:19:HAL_MultiProcessor_EnterMuteMode 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2808:19:HAL_MultiProcessor_ExitMuteMode 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2836:19:HAL_HalfDuplex_EnableTransmitter 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2871:19:HAL_HalfDuplex_EnableReceiver 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2928:23:HAL_UART_GetState 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2943:10:HAL_UART_GetError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:2988:13:UART_DMATransmitCplt 4 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3023:13:UART_DMATxHalfCplt 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3042:13:UART_DMAReceiveCplt 8 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3104:13:UART_DMARxHalfCplt 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3143:13:UART_DMAError 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3185:26:UART_WaitOnFlagUntilTimeout 9 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3236:19:UART_Start_Receive_IT 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3271:19:UART_Start_Receive_DMA 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3321:13:UART_EndTxTransfer 2 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3335:13:UART_EndRxTransfer 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3359:13:UART_DMAAbortOnError 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3383:13:UART_DMATxAbortCallback 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3429:13:UART_DMARxAbortCallback 3 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3475:13:UART_DMATxOnlyAbortCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3503:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3529:26:UART_Transmit_IT 5 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3569:26:UART_EndTransmit_IT 1 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3594:26:UART_Receive_IT 11 +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c:3695:13:UART_SetConfig 2 diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk index 9259b41..b4c635a 100755 --- a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk @@ -1,6 +1,6 @@ ################################################################################ # Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (12.3.rel1) +# Toolchain: GNU Tools for STM32 (13.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables @@ -10,6 +10,7 @@ C_SRCS += \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ @@ -25,33 +26,13 @@ C_SRCS += \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c -OBJS += \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \ -./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o - C_DEPS += \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d \ @@ -67,15 +48,37 @@ C_DEPS += \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \ ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d +OBJS += \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o + # Each subdirectory must supply rules for building sources it contributes Drivers/STM32F1xx_HAL_Driver/Src/%.o Drivers/STM32F1xx_HAL_Driver/Src/%.su Drivers/STM32F1xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F1xx_HAL_Driver/Src/%.c Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F107xC -c -I../Core/Inc -I/Users/colorbass/STM32CubeIDE/workspace_1.12.0/lib_EDCAN -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F107xC -c -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" clean: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src: - -$(RM) ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su + -$(RM) ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.cyclo ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o ./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su .PHONY: clean-Drivers-2f-STM32F1xx_HAL_Driver-2f-Src diff --git a/Debug/GbTModuleSW.list b/Debug/GbTModuleSW.list deleted file mode 100755 index 9dd31b5..0000000 --- a/Debug/GbTModuleSW.list +++ /dev/null @@ -1,29890 +0,0 @@ - -GbTModuleSW.elf: file format elf32-littlearm - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .isr_vector 000001e4 08000000 08000000 00001000 2**0 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 0000d454 080001e8 080001e8 000011e8 2**3 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000eb0 0800d640 0800d640 0000e640 2**3 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 0800e4f0 0800e4f0 0001023c 2**0 - CONTENTS - 4 .ARM 00000008 0800e4f0 0800e4f0 0000f4f0 2**2 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 0800e4f8 0800e4f8 0001023c 2**0 - CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 0800e4f8 0800e4f8 0000f4f8 2**2 - CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 0800e4fc 0800e4fc 0000f4fc 2**2 - CONTENTS, ALLOC, LOAD, DATA - 8 .data 0000023c 20000000 0800e500 00010000 2**3 - CONTENTS, ALLOC, LOAD, DATA - 9 .bss 000032d0 2000023c 0800e73c 0001023c 2**2 - ALLOC - 10 ._user_heap_stack 00000604 2000350c 0800e73c 0001050c 2**0 - ALLOC - 11 .ARM.attributes 00000029 00000000 00000000 0001023c 2**0 - CONTENTS, READONLY - 12 .debug_info 0001196b 00000000 00000000 00010265 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 00004245 00000000 00000000 00021bd0 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00001098 00000000 00000000 00025e18 2**3 - CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 00000c6c 00000000 00000000 00026eb0 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00024410 00000000 00000000 00027b1c 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 0001773a 00000000 00000000 0004bf2c 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000bfdf4 00000000 00000000 00063666 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 0012345a 2**0 - CONTENTS, READONLY - 20 .debug_frame 00005958 00000000 00000000 001234a0 2**2 - CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000069 00000000 00000000 00128df8 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - -Disassembly of section .text: - -080001e8 <__do_global_dtors_aux>: - 80001e8: b510 push {r4, lr} - 80001ea: 4c05 ldr r4, [pc, #20] @ (8000200 <__do_global_dtors_aux+0x18>) - 80001ec: 7823 ldrb r3, [r4, #0] - 80001ee: b933 cbnz r3, 80001fe <__do_global_dtors_aux+0x16> - 80001f0: 4b04 ldr r3, [pc, #16] @ (8000204 <__do_global_dtors_aux+0x1c>) - 80001f2: b113 cbz r3, 80001fa <__do_global_dtors_aux+0x12> - 80001f4: 4804 ldr r0, [pc, #16] @ (8000208 <__do_global_dtors_aux+0x20>) - 80001f6: f3af 8000 nop.w - 80001fa: 2301 movs r3, #1 - 80001fc: 7023 strb r3, [r4, #0] - 80001fe: bd10 pop {r4, pc} - 8000200: 2000023c .word 0x2000023c - 8000204: 00000000 .word 0x00000000 - 8000208: 0800d624 .word 0x0800d624 - -0800020c : - 800020c: b508 push {r3, lr} - 800020e: 4b03 ldr r3, [pc, #12] @ (800021c ) - 8000210: b11b cbz r3, 800021a - 8000212: 4903 ldr r1, [pc, #12] @ (8000220 ) - 8000214: 4803 ldr r0, [pc, #12] @ (8000224 ) - 8000216: f3af 8000 nop.w - 800021a: bd08 pop {r3, pc} - 800021c: 00000000 .word 0x00000000 - 8000220: 20000240 .word 0x20000240 - 8000224: 0800d624 .word 0x0800d624 - -08000228 : - 8000228: 4603 mov r3, r0 - 800022a: f813 2b01 ldrb.w r2, [r3], #1 - 800022e: 2a00 cmp r2, #0 - 8000230: d1fb bne.n 800022a - 8000232: 1a18 subs r0, r3, r0 - 8000234: 3801 subs r0, #1 - 8000236: 4770 bx lr - -08000238 : - 8000238: f810 2b01 ldrb.w r2, [r0], #1 - 800023c: f811 3b01 ldrb.w r3, [r1], #1 - 8000240: 2a01 cmp r2, #1 - 8000242: bf28 it cs - 8000244: 429a cmpcs r2, r3 - 8000246: d0f7 beq.n 8000238 - 8000248: 1ad0 subs r0, r2, r3 - 800024a: 4770 bx lr - -0800024c <__aeabi_drsub>: - 800024c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 - 8000250: e002 b.n 8000258 <__adddf3> - 8000252: bf00 nop - -08000254 <__aeabi_dsub>: - 8000254: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 - -08000258 <__adddf3>: - 8000258: b530 push {r4, r5, lr} - 800025a: ea4f 0441 mov.w r4, r1, lsl #1 - 800025e: ea4f 0543 mov.w r5, r3, lsl #1 - 8000262: ea94 0f05 teq r4, r5 - 8000266: bf08 it eq - 8000268: ea90 0f02 teqeq r0, r2 - 800026c: bf1f itttt ne - 800026e: ea54 0c00 orrsne.w ip, r4, r0 - 8000272: ea55 0c02 orrsne.w ip, r5, r2 - 8000276: ea7f 5c64 mvnsne.w ip, r4, asr #21 - 800027a: ea7f 5c65 mvnsne.w ip, r5, asr #21 - 800027e: f000 80e2 beq.w 8000446 <__adddf3+0x1ee> - 8000282: ea4f 5454 mov.w r4, r4, lsr #21 - 8000286: ebd4 5555 rsbs r5, r4, r5, lsr #21 - 800028a: bfb8 it lt - 800028c: 426d neglt r5, r5 - 800028e: dd0c ble.n 80002aa <__adddf3+0x52> - 8000290: 442c add r4, r5 - 8000292: ea80 0202 eor.w r2, r0, r2 - 8000296: ea81 0303 eor.w r3, r1, r3 - 800029a: ea82 0000 eor.w r0, r2, r0 - 800029e: ea83 0101 eor.w r1, r3, r1 - 80002a2: ea80 0202 eor.w r2, r0, r2 - 80002a6: ea81 0303 eor.w r3, r1, r3 - 80002aa: 2d36 cmp r5, #54 @ 0x36 - 80002ac: bf88 it hi - 80002ae: bd30 pophi {r4, r5, pc} - 80002b0: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 - 80002b4: ea4f 3101 mov.w r1, r1, lsl #12 - 80002b8: f44f 1c80 mov.w ip, #1048576 @ 0x100000 - 80002bc: ea4c 3111 orr.w r1, ip, r1, lsr #12 - 80002c0: d002 beq.n 80002c8 <__adddf3+0x70> - 80002c2: 4240 negs r0, r0 - 80002c4: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 80002c8: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 - 80002cc: ea4f 3303 mov.w r3, r3, lsl #12 - 80002d0: ea4c 3313 orr.w r3, ip, r3, lsr #12 - 80002d4: d002 beq.n 80002dc <__adddf3+0x84> - 80002d6: 4252 negs r2, r2 - 80002d8: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 80002dc: ea94 0f05 teq r4, r5 - 80002e0: f000 80a7 beq.w 8000432 <__adddf3+0x1da> - 80002e4: f1a4 0401 sub.w r4, r4, #1 - 80002e8: f1d5 0e20 rsbs lr, r5, #32 - 80002ec: db0d blt.n 800030a <__adddf3+0xb2> - 80002ee: fa02 fc0e lsl.w ip, r2, lr - 80002f2: fa22 f205 lsr.w r2, r2, r5 - 80002f6: 1880 adds r0, r0, r2 - 80002f8: f141 0100 adc.w r1, r1, #0 - 80002fc: fa03 f20e lsl.w r2, r3, lr - 8000300: 1880 adds r0, r0, r2 - 8000302: fa43 f305 asr.w r3, r3, r5 - 8000306: 4159 adcs r1, r3 - 8000308: e00e b.n 8000328 <__adddf3+0xd0> - 800030a: f1a5 0520 sub.w r5, r5, #32 - 800030e: f10e 0e20 add.w lr, lr, #32 - 8000312: 2a01 cmp r2, #1 - 8000314: fa03 fc0e lsl.w ip, r3, lr - 8000318: bf28 it cs - 800031a: f04c 0c02 orrcs.w ip, ip, #2 - 800031e: fa43 f305 asr.w r3, r3, r5 - 8000322: 18c0 adds r0, r0, r3 - 8000324: eb51 71e3 adcs.w r1, r1, r3, asr #31 - 8000328: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 - 800032c: d507 bpl.n 800033e <__adddf3+0xe6> - 800032e: f04f 0e00 mov.w lr, #0 - 8000332: f1dc 0c00 rsbs ip, ip, #0 - 8000336: eb7e 0000 sbcs.w r0, lr, r0 - 800033a: eb6e 0101 sbc.w r1, lr, r1 - 800033e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 - 8000342: d31b bcc.n 800037c <__adddf3+0x124> - 8000344: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 - 8000348: d30c bcc.n 8000364 <__adddf3+0x10c> - 800034a: 0849 lsrs r1, r1, #1 - 800034c: ea5f 0030 movs.w r0, r0, rrx - 8000350: ea4f 0c3c mov.w ip, ip, rrx - 8000354: f104 0401 add.w r4, r4, #1 - 8000358: ea4f 5244 mov.w r2, r4, lsl #21 - 800035c: f512 0f80 cmn.w r2, #4194304 @ 0x400000 - 8000360: f080 809a bcs.w 8000498 <__adddf3+0x240> - 8000364: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 - 8000368: bf08 it eq - 800036a: ea5f 0c50 movseq.w ip, r0, lsr #1 - 800036e: f150 0000 adcs.w r0, r0, #0 - 8000372: eb41 5104 adc.w r1, r1, r4, lsl #20 - 8000376: ea41 0105 orr.w r1, r1, r5 - 800037a: bd30 pop {r4, r5, pc} - 800037c: ea5f 0c4c movs.w ip, ip, lsl #1 - 8000380: 4140 adcs r0, r0 - 8000382: eb41 0101 adc.w r1, r1, r1 - 8000386: 3c01 subs r4, #1 - 8000388: bf28 it cs - 800038a: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 - 800038e: d2e9 bcs.n 8000364 <__adddf3+0x10c> - 8000390: f091 0f00 teq r1, #0 - 8000394: bf04 itt eq - 8000396: 4601 moveq r1, r0 - 8000398: 2000 moveq r0, #0 - 800039a: fab1 f381 clz r3, r1 - 800039e: bf08 it eq - 80003a0: 3320 addeq r3, #32 - 80003a2: f1a3 030b sub.w r3, r3, #11 - 80003a6: f1b3 0220 subs.w r2, r3, #32 - 80003aa: da0c bge.n 80003c6 <__adddf3+0x16e> - 80003ac: 320c adds r2, #12 - 80003ae: dd08 ble.n 80003c2 <__adddf3+0x16a> - 80003b0: f102 0c14 add.w ip, r2, #20 - 80003b4: f1c2 020c rsb r2, r2, #12 - 80003b8: fa01 f00c lsl.w r0, r1, ip - 80003bc: fa21 f102 lsr.w r1, r1, r2 - 80003c0: e00c b.n 80003dc <__adddf3+0x184> - 80003c2: f102 0214 add.w r2, r2, #20 - 80003c6: bfd8 it le - 80003c8: f1c2 0c20 rsble ip, r2, #32 - 80003cc: fa01 f102 lsl.w r1, r1, r2 - 80003d0: fa20 fc0c lsr.w ip, r0, ip - 80003d4: bfdc itt le - 80003d6: ea41 010c orrle.w r1, r1, ip - 80003da: 4090 lslle r0, r2 - 80003dc: 1ae4 subs r4, r4, r3 - 80003de: bfa2 ittt ge - 80003e0: eb01 5104 addge.w r1, r1, r4, lsl #20 - 80003e4: 4329 orrge r1, r5 - 80003e6: bd30 popge {r4, r5, pc} - 80003e8: ea6f 0404 mvn.w r4, r4 - 80003ec: 3c1f subs r4, #31 - 80003ee: da1c bge.n 800042a <__adddf3+0x1d2> - 80003f0: 340c adds r4, #12 - 80003f2: dc0e bgt.n 8000412 <__adddf3+0x1ba> - 80003f4: f104 0414 add.w r4, r4, #20 - 80003f8: f1c4 0220 rsb r2, r4, #32 - 80003fc: fa20 f004 lsr.w r0, r0, r4 - 8000400: fa01 f302 lsl.w r3, r1, r2 - 8000404: ea40 0003 orr.w r0, r0, r3 - 8000408: fa21 f304 lsr.w r3, r1, r4 - 800040c: ea45 0103 orr.w r1, r5, r3 - 8000410: bd30 pop {r4, r5, pc} - 8000412: f1c4 040c rsb r4, r4, #12 - 8000416: f1c4 0220 rsb r2, r4, #32 - 800041a: fa20 f002 lsr.w r0, r0, r2 - 800041e: fa01 f304 lsl.w r3, r1, r4 - 8000422: ea40 0003 orr.w r0, r0, r3 - 8000426: 4629 mov r1, r5 - 8000428: bd30 pop {r4, r5, pc} - 800042a: fa21 f004 lsr.w r0, r1, r4 - 800042e: 4629 mov r1, r5 - 8000430: bd30 pop {r4, r5, pc} - 8000432: f094 0f00 teq r4, #0 - 8000436: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 - 800043a: bf06 itte eq - 800043c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 - 8000440: 3401 addeq r4, #1 - 8000442: 3d01 subne r5, #1 - 8000444: e74e b.n 80002e4 <__adddf3+0x8c> - 8000446: ea7f 5c64 mvns.w ip, r4, asr #21 - 800044a: bf18 it ne - 800044c: ea7f 5c65 mvnsne.w ip, r5, asr #21 - 8000450: d029 beq.n 80004a6 <__adddf3+0x24e> - 8000452: ea94 0f05 teq r4, r5 - 8000456: bf08 it eq - 8000458: ea90 0f02 teqeq r0, r2 - 800045c: d005 beq.n 800046a <__adddf3+0x212> - 800045e: ea54 0c00 orrs.w ip, r4, r0 - 8000462: bf04 itt eq - 8000464: 4619 moveq r1, r3 - 8000466: 4610 moveq r0, r2 - 8000468: bd30 pop {r4, r5, pc} - 800046a: ea91 0f03 teq r1, r3 - 800046e: bf1e ittt ne - 8000470: 2100 movne r1, #0 - 8000472: 2000 movne r0, #0 - 8000474: bd30 popne {r4, r5, pc} - 8000476: ea5f 5c54 movs.w ip, r4, lsr #21 - 800047a: d105 bne.n 8000488 <__adddf3+0x230> - 800047c: 0040 lsls r0, r0, #1 - 800047e: 4149 adcs r1, r1 - 8000480: bf28 it cs - 8000482: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 - 8000486: bd30 pop {r4, r5, pc} - 8000488: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 - 800048c: bf3c itt cc - 800048e: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 - 8000492: bd30 popcc {r4, r5, pc} - 8000494: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 - 8000498: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 - 800049c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 - 80004a0: f04f 0000 mov.w r0, #0 - 80004a4: bd30 pop {r4, r5, pc} - 80004a6: ea7f 5c64 mvns.w ip, r4, asr #21 - 80004aa: bf1a itte ne - 80004ac: 4619 movne r1, r3 - 80004ae: 4610 movne r0, r2 - 80004b0: ea7f 5c65 mvnseq.w ip, r5, asr #21 - 80004b4: bf1c itt ne - 80004b6: 460b movne r3, r1 - 80004b8: 4602 movne r2, r0 - 80004ba: ea50 3401 orrs.w r4, r0, r1, lsl #12 - 80004be: bf06 itte eq - 80004c0: ea52 3503 orrseq.w r5, r2, r3, lsl #12 - 80004c4: ea91 0f03 teqeq r1, r3 - 80004c8: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 - 80004cc: bd30 pop {r4, r5, pc} - 80004ce: bf00 nop - -080004d0 <__aeabi_ui2d>: - 80004d0: f090 0f00 teq r0, #0 - 80004d4: bf04 itt eq - 80004d6: 2100 moveq r1, #0 - 80004d8: 4770 bxeq lr - 80004da: b530 push {r4, r5, lr} - 80004dc: f44f 6480 mov.w r4, #1024 @ 0x400 - 80004e0: f104 0432 add.w r4, r4, #50 @ 0x32 - 80004e4: f04f 0500 mov.w r5, #0 - 80004e8: f04f 0100 mov.w r1, #0 - 80004ec: e750 b.n 8000390 <__adddf3+0x138> - 80004ee: bf00 nop - -080004f0 <__aeabi_i2d>: - 80004f0: f090 0f00 teq r0, #0 - 80004f4: bf04 itt eq - 80004f6: 2100 moveq r1, #0 - 80004f8: 4770 bxeq lr - 80004fa: b530 push {r4, r5, lr} - 80004fc: f44f 6480 mov.w r4, #1024 @ 0x400 - 8000500: f104 0432 add.w r4, r4, #50 @ 0x32 - 8000504: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 - 8000508: bf48 it mi - 800050a: 4240 negmi r0, r0 - 800050c: f04f 0100 mov.w r1, #0 - 8000510: e73e b.n 8000390 <__adddf3+0x138> - 8000512: bf00 nop - -08000514 <__aeabi_f2d>: - 8000514: 0042 lsls r2, r0, #1 - 8000516: ea4f 01e2 mov.w r1, r2, asr #3 - 800051a: ea4f 0131 mov.w r1, r1, rrx - 800051e: ea4f 7002 mov.w r0, r2, lsl #28 - 8000522: bf1f itttt ne - 8000524: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 - 8000528: f093 4f7f teqne r3, #4278190080 @ 0xff000000 - 800052c: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 - 8000530: 4770 bxne lr - 8000532: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 - 8000536: bf08 it eq - 8000538: 4770 bxeq lr - 800053a: f093 4f7f teq r3, #4278190080 @ 0xff000000 - 800053e: bf04 itt eq - 8000540: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 - 8000544: 4770 bxeq lr - 8000546: b530 push {r4, r5, lr} - 8000548: f44f 7460 mov.w r4, #896 @ 0x380 - 800054c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 - 8000550: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 - 8000554: e71c b.n 8000390 <__adddf3+0x138> - 8000556: bf00 nop - -08000558 <__aeabi_ul2d>: - 8000558: ea50 0201 orrs.w r2, r0, r1 - 800055c: bf08 it eq - 800055e: 4770 bxeq lr - 8000560: b530 push {r4, r5, lr} - 8000562: f04f 0500 mov.w r5, #0 - 8000566: e00a b.n 800057e <__aeabi_l2d+0x16> - -08000568 <__aeabi_l2d>: - 8000568: ea50 0201 orrs.w r2, r0, r1 - 800056c: bf08 it eq - 800056e: 4770 bxeq lr - 8000570: b530 push {r4, r5, lr} - 8000572: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 - 8000576: d502 bpl.n 800057e <__aeabi_l2d+0x16> - 8000578: 4240 negs r0, r0 - 800057a: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 800057e: f44f 6480 mov.w r4, #1024 @ 0x400 - 8000582: f104 0432 add.w r4, r4, #50 @ 0x32 - 8000586: ea5f 5c91 movs.w ip, r1, lsr #22 - 800058a: f43f aed8 beq.w 800033e <__adddf3+0xe6> - 800058e: f04f 0203 mov.w r2, #3 - 8000592: ea5f 0cdc movs.w ip, ip, lsr #3 - 8000596: bf18 it ne - 8000598: 3203 addne r2, #3 - 800059a: ea5f 0cdc movs.w ip, ip, lsr #3 - 800059e: bf18 it ne - 80005a0: 3203 addne r2, #3 - 80005a2: eb02 02dc add.w r2, r2, ip, lsr #3 - 80005a6: f1c2 0320 rsb r3, r2, #32 - 80005aa: fa00 fc03 lsl.w ip, r0, r3 - 80005ae: fa20 f002 lsr.w r0, r0, r2 - 80005b2: fa01 fe03 lsl.w lr, r1, r3 - 80005b6: ea40 000e orr.w r0, r0, lr - 80005ba: fa21 f102 lsr.w r1, r1, r2 - 80005be: 4414 add r4, r2 - 80005c0: e6bd b.n 800033e <__adddf3+0xe6> - 80005c2: bf00 nop - -080005c4 <__aeabi_dmul>: - 80005c4: b570 push {r4, r5, r6, lr} - 80005c6: f04f 0cff mov.w ip, #255 @ 0xff - 80005ca: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 - 80005ce: ea1c 5411 ands.w r4, ip, r1, lsr #20 - 80005d2: bf1d ittte ne - 80005d4: ea1c 5513 andsne.w r5, ip, r3, lsr #20 - 80005d8: ea94 0f0c teqne r4, ip - 80005dc: ea95 0f0c teqne r5, ip - 80005e0: f000 f8de bleq 80007a0 <__aeabi_dmul+0x1dc> - 80005e4: 442c add r4, r5 - 80005e6: ea81 0603 eor.w r6, r1, r3 - 80005ea: ea21 514c bic.w r1, r1, ip, lsl #21 - 80005ee: ea23 534c bic.w r3, r3, ip, lsl #21 - 80005f2: ea50 3501 orrs.w r5, r0, r1, lsl #12 - 80005f6: bf18 it ne - 80005f8: ea52 3503 orrsne.w r5, r2, r3, lsl #12 - 80005fc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 - 8000600: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 8000604: d038 beq.n 8000678 <__aeabi_dmul+0xb4> - 8000606: fba0 ce02 umull ip, lr, r0, r2 - 800060a: f04f 0500 mov.w r5, #0 - 800060e: fbe1 e502 umlal lr, r5, r1, r2 - 8000612: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 - 8000616: fbe0 e503 umlal lr, r5, r0, r3 - 800061a: f04f 0600 mov.w r6, #0 - 800061e: fbe1 5603 umlal r5, r6, r1, r3 - 8000622: f09c 0f00 teq ip, #0 - 8000626: bf18 it ne - 8000628: f04e 0e01 orrne.w lr, lr, #1 - 800062c: f1a4 04ff sub.w r4, r4, #255 @ 0xff - 8000630: f5b6 7f00 cmp.w r6, #512 @ 0x200 - 8000634: f564 7440 sbc.w r4, r4, #768 @ 0x300 - 8000638: d204 bcs.n 8000644 <__aeabi_dmul+0x80> - 800063a: ea5f 0e4e movs.w lr, lr, lsl #1 - 800063e: 416d adcs r5, r5 - 8000640: eb46 0606 adc.w r6, r6, r6 - 8000644: ea42 21c6 orr.w r1, r2, r6, lsl #11 - 8000648: ea41 5155 orr.w r1, r1, r5, lsr #21 - 800064c: ea4f 20c5 mov.w r0, r5, lsl #11 - 8000650: ea40 505e orr.w r0, r0, lr, lsr #21 - 8000654: ea4f 2ece mov.w lr, lr, lsl #11 - 8000658: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd - 800065c: bf88 it hi - 800065e: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 - 8000662: d81e bhi.n 80006a2 <__aeabi_dmul+0xde> - 8000664: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 - 8000668: bf08 it eq - 800066a: ea5f 0e50 movseq.w lr, r0, lsr #1 - 800066e: f150 0000 adcs.w r0, r0, #0 - 8000672: eb41 5104 adc.w r1, r1, r4, lsl #20 - 8000676: bd70 pop {r4, r5, r6, pc} - 8000678: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 - 800067c: ea46 0101 orr.w r1, r6, r1 - 8000680: ea40 0002 orr.w r0, r0, r2 - 8000684: ea81 0103 eor.w r1, r1, r3 - 8000688: ebb4 045c subs.w r4, r4, ip, lsr #1 - 800068c: bfc2 ittt gt - 800068e: ebd4 050c rsbsgt r5, r4, ip - 8000692: ea41 5104 orrgt.w r1, r1, r4, lsl #20 - 8000696: bd70 popgt {r4, r5, r6, pc} - 8000698: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 - 800069c: f04f 0e00 mov.w lr, #0 - 80006a0: 3c01 subs r4, #1 - 80006a2: f300 80ab bgt.w 80007fc <__aeabi_dmul+0x238> - 80006a6: f114 0f36 cmn.w r4, #54 @ 0x36 - 80006aa: bfde ittt le - 80006ac: 2000 movle r0, #0 - 80006ae: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 - 80006b2: bd70 pople {r4, r5, r6, pc} - 80006b4: f1c4 0400 rsb r4, r4, #0 - 80006b8: 3c20 subs r4, #32 - 80006ba: da35 bge.n 8000728 <__aeabi_dmul+0x164> - 80006bc: 340c adds r4, #12 - 80006be: dc1b bgt.n 80006f8 <__aeabi_dmul+0x134> - 80006c0: f104 0414 add.w r4, r4, #20 - 80006c4: f1c4 0520 rsb r5, r4, #32 - 80006c8: fa00 f305 lsl.w r3, r0, r5 - 80006cc: fa20 f004 lsr.w r0, r0, r4 - 80006d0: fa01 f205 lsl.w r2, r1, r5 - 80006d4: ea40 0002 orr.w r0, r0, r2 - 80006d8: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 - 80006dc: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 - 80006e0: eb10 70d3 adds.w r0, r0, r3, lsr #31 - 80006e4: fa21 f604 lsr.w r6, r1, r4 - 80006e8: eb42 0106 adc.w r1, r2, r6 - 80006ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 80006f0: bf08 it eq - 80006f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 80006f6: bd70 pop {r4, r5, r6, pc} - 80006f8: f1c4 040c rsb r4, r4, #12 - 80006fc: f1c4 0520 rsb r5, r4, #32 - 8000700: fa00 f304 lsl.w r3, r0, r4 - 8000704: fa20 f005 lsr.w r0, r0, r5 - 8000708: fa01 f204 lsl.w r2, r1, r4 - 800070c: ea40 0002 orr.w r0, r0, r2 - 8000710: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 - 8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31 - 8000718: f141 0100 adc.w r1, r1, #0 - 800071c: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 8000720: bf08 it eq - 8000722: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 8000726: bd70 pop {r4, r5, r6, pc} - 8000728: f1c4 0520 rsb r5, r4, #32 - 800072c: fa00 f205 lsl.w r2, r0, r5 - 8000730: ea4e 0e02 orr.w lr, lr, r2 - 8000734: fa20 f304 lsr.w r3, r0, r4 - 8000738: fa01 f205 lsl.w r2, r1, r5 - 800073c: ea43 0302 orr.w r3, r3, r2 - 8000740: fa21 f004 lsr.w r0, r1, r4 - 8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 - 8000748: fa21 f204 lsr.w r2, r1, r4 - 800074c: ea20 0002 bic.w r0, r0, r2 - 8000750: eb00 70d3 add.w r0, r0, r3, lsr #31 - 8000754: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 8000758: bf08 it eq - 800075a: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 800075e: bd70 pop {r4, r5, r6, pc} - 8000760: f094 0f00 teq r4, #0 - 8000764: d10f bne.n 8000786 <__aeabi_dmul+0x1c2> - 8000766: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 - 800076a: 0040 lsls r0, r0, #1 - 800076c: eb41 0101 adc.w r1, r1, r1 - 8000770: f411 1f80 tst.w r1, #1048576 @ 0x100000 - 8000774: bf08 it eq - 8000776: 3c01 subeq r4, #1 - 8000778: d0f7 beq.n 800076a <__aeabi_dmul+0x1a6> - 800077a: ea41 0106 orr.w r1, r1, r6 - 800077e: f095 0f00 teq r5, #0 - 8000782: bf18 it ne - 8000784: 4770 bxne lr - 8000786: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 - 800078a: 0052 lsls r2, r2, #1 - 800078c: eb43 0303 adc.w r3, r3, r3 - 8000790: f413 1f80 tst.w r3, #1048576 @ 0x100000 - 8000794: bf08 it eq - 8000796: 3d01 subeq r5, #1 - 8000798: d0f7 beq.n 800078a <__aeabi_dmul+0x1c6> - 800079a: ea43 0306 orr.w r3, r3, r6 - 800079e: 4770 bx lr - 80007a0: ea94 0f0c teq r4, ip - 80007a4: ea0c 5513 and.w r5, ip, r3, lsr #20 - 80007a8: bf18 it ne - 80007aa: ea95 0f0c teqne r5, ip - 80007ae: d00c beq.n 80007ca <__aeabi_dmul+0x206> - 80007b0: ea50 0641 orrs.w r6, r0, r1, lsl #1 - 80007b4: bf18 it ne - 80007b6: ea52 0643 orrsne.w r6, r2, r3, lsl #1 - 80007ba: d1d1 bne.n 8000760 <__aeabi_dmul+0x19c> - 80007bc: ea81 0103 eor.w r1, r1, r3 - 80007c0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 - 80007c4: f04f 0000 mov.w r0, #0 - 80007c8: bd70 pop {r4, r5, r6, pc} - 80007ca: ea50 0641 orrs.w r6, r0, r1, lsl #1 - 80007ce: bf06 itte eq - 80007d0: 4610 moveq r0, r2 - 80007d2: 4619 moveq r1, r3 - 80007d4: ea52 0643 orrsne.w r6, r2, r3, lsl #1 - 80007d8: d019 beq.n 800080e <__aeabi_dmul+0x24a> - 80007da: ea94 0f0c teq r4, ip - 80007de: d102 bne.n 80007e6 <__aeabi_dmul+0x222> - 80007e0: ea50 3601 orrs.w r6, r0, r1, lsl #12 - 80007e4: d113 bne.n 800080e <__aeabi_dmul+0x24a> - 80007e6: ea95 0f0c teq r5, ip - 80007ea: d105 bne.n 80007f8 <__aeabi_dmul+0x234> - 80007ec: ea52 3603 orrs.w r6, r2, r3, lsl #12 - 80007f0: bf1c itt ne - 80007f2: 4610 movne r0, r2 - 80007f4: 4619 movne r1, r3 - 80007f6: d10a bne.n 800080e <__aeabi_dmul+0x24a> - 80007f8: ea81 0103 eor.w r1, r1, r3 - 80007fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 - 8000800: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 - 8000804: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 - 8000808: f04f 0000 mov.w r0, #0 - 800080c: bd70 pop {r4, r5, r6, pc} - 800080e: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 - 8000812: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 - 8000816: bd70 pop {r4, r5, r6, pc} - -08000818 <__aeabi_ddiv>: - 8000818: b570 push {r4, r5, r6, lr} - 800081a: f04f 0cff mov.w ip, #255 @ 0xff - 800081e: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 - 8000822: ea1c 5411 ands.w r4, ip, r1, lsr #20 - 8000826: bf1d ittte ne - 8000828: ea1c 5513 andsne.w r5, ip, r3, lsr #20 - 800082c: ea94 0f0c teqne r4, ip - 8000830: ea95 0f0c teqne r5, ip - 8000834: f000 f8a7 bleq 8000986 <__aeabi_ddiv+0x16e> - 8000838: eba4 0405 sub.w r4, r4, r5 - 800083c: ea81 0e03 eor.w lr, r1, r3 - 8000840: ea52 3503 orrs.w r5, r2, r3, lsl #12 - 8000844: ea4f 3101 mov.w r1, r1, lsl #12 - 8000848: f000 8088 beq.w 800095c <__aeabi_ddiv+0x144> - 800084c: ea4f 3303 mov.w r3, r3, lsl #12 - 8000850: f04f 5580 mov.w r5, #268435456 @ 0x10000000 - 8000854: ea45 1313 orr.w r3, r5, r3, lsr #4 - 8000858: ea43 6312 orr.w r3, r3, r2, lsr #24 - 800085c: ea4f 2202 mov.w r2, r2, lsl #8 - 8000860: ea45 1511 orr.w r5, r5, r1, lsr #4 - 8000864: ea45 6510 orr.w r5, r5, r0, lsr #24 - 8000868: ea4f 2600 mov.w r6, r0, lsl #8 - 800086c: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 - 8000870: 429d cmp r5, r3 - 8000872: bf08 it eq - 8000874: 4296 cmpeq r6, r2 - 8000876: f144 04fd adc.w r4, r4, #253 @ 0xfd - 800087a: f504 7440 add.w r4, r4, #768 @ 0x300 - 800087e: d202 bcs.n 8000886 <__aeabi_ddiv+0x6e> - 8000880: 085b lsrs r3, r3, #1 - 8000882: ea4f 0232 mov.w r2, r2, rrx - 8000886: 1ab6 subs r6, r6, r2 - 8000888: eb65 0503 sbc.w r5, r5, r3 - 800088c: 085b lsrs r3, r3, #1 - 800088e: ea4f 0232 mov.w r2, r2, rrx - 8000892: f44f 1080 mov.w r0, #1048576 @ 0x100000 - 8000896: f44f 2c00 mov.w ip, #524288 @ 0x80000 - 800089a: ebb6 0e02 subs.w lr, r6, r2 - 800089e: eb75 0e03 sbcs.w lr, r5, r3 - 80008a2: bf22 ittt cs - 80008a4: 1ab6 subcs r6, r6, r2 - 80008a6: 4675 movcs r5, lr - 80008a8: ea40 000c orrcs.w r0, r0, ip - 80008ac: 085b lsrs r3, r3, #1 - 80008ae: ea4f 0232 mov.w r2, r2, rrx - 80008b2: ebb6 0e02 subs.w lr, r6, r2 - 80008b6: eb75 0e03 sbcs.w lr, r5, r3 - 80008ba: bf22 ittt cs - 80008bc: 1ab6 subcs r6, r6, r2 - 80008be: 4675 movcs r5, lr - 80008c0: ea40 005c orrcs.w r0, r0, ip, lsr #1 - 80008c4: 085b lsrs r3, r3, #1 - 80008c6: ea4f 0232 mov.w r2, r2, rrx - 80008ca: ebb6 0e02 subs.w lr, r6, r2 - 80008ce: eb75 0e03 sbcs.w lr, r5, r3 - 80008d2: bf22 ittt cs - 80008d4: 1ab6 subcs r6, r6, r2 - 80008d6: 4675 movcs r5, lr - 80008d8: ea40 009c orrcs.w r0, r0, ip, lsr #2 - 80008dc: 085b lsrs r3, r3, #1 - 80008de: ea4f 0232 mov.w r2, r2, rrx - 80008e2: ebb6 0e02 subs.w lr, r6, r2 - 80008e6: eb75 0e03 sbcs.w lr, r5, r3 - 80008ea: bf22 ittt cs - 80008ec: 1ab6 subcs r6, r6, r2 - 80008ee: 4675 movcs r5, lr - 80008f0: ea40 00dc orrcs.w r0, r0, ip, lsr #3 - 80008f4: ea55 0e06 orrs.w lr, r5, r6 - 80008f8: d018 beq.n 800092c <__aeabi_ddiv+0x114> - 80008fa: ea4f 1505 mov.w r5, r5, lsl #4 - 80008fe: ea45 7516 orr.w r5, r5, r6, lsr #28 - 8000902: ea4f 1606 mov.w r6, r6, lsl #4 - 8000906: ea4f 03c3 mov.w r3, r3, lsl #3 - 800090a: ea43 7352 orr.w r3, r3, r2, lsr #29 - 800090e: ea4f 02c2 mov.w r2, r2, lsl #3 - 8000912: ea5f 1c1c movs.w ip, ip, lsr #4 - 8000916: d1c0 bne.n 800089a <__aeabi_ddiv+0x82> - 8000918: f411 1f80 tst.w r1, #1048576 @ 0x100000 - 800091c: d10b bne.n 8000936 <__aeabi_ddiv+0x11e> - 800091e: ea41 0100 orr.w r1, r1, r0 - 8000922: f04f 0000 mov.w r0, #0 - 8000926: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 - 800092a: e7b6 b.n 800089a <__aeabi_ddiv+0x82> - 800092c: f411 1f80 tst.w r1, #1048576 @ 0x100000 - 8000930: bf04 itt eq - 8000932: 4301 orreq r1, r0 - 8000934: 2000 moveq r0, #0 - 8000936: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd - 800093a: bf88 it hi - 800093c: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 - 8000940: f63f aeaf bhi.w 80006a2 <__aeabi_dmul+0xde> - 8000944: ebb5 0c03 subs.w ip, r5, r3 - 8000948: bf04 itt eq - 800094a: ebb6 0c02 subseq.w ip, r6, r2 - 800094e: ea5f 0c50 movseq.w ip, r0, lsr #1 - 8000952: f150 0000 adcs.w r0, r0, #0 - 8000956: eb41 5104 adc.w r1, r1, r4, lsl #20 - 800095a: bd70 pop {r4, r5, r6, pc} - 800095c: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 - 8000960: ea4e 3111 orr.w r1, lr, r1, lsr #12 - 8000964: eb14 045c adds.w r4, r4, ip, lsr #1 - 8000968: bfc2 ittt gt - 800096a: ebd4 050c rsbsgt r5, r4, ip - 800096e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 - 8000972: bd70 popgt {r4, r5, r6, pc} - 8000974: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 - 8000978: f04f 0e00 mov.w lr, #0 - 800097c: 3c01 subs r4, #1 - 800097e: e690 b.n 80006a2 <__aeabi_dmul+0xde> - 8000980: ea45 0e06 orr.w lr, r5, r6 - 8000984: e68d b.n 80006a2 <__aeabi_dmul+0xde> - 8000986: ea0c 5513 and.w r5, ip, r3, lsr #20 - 800098a: ea94 0f0c teq r4, ip - 800098e: bf08 it eq - 8000990: ea95 0f0c teqeq r5, ip - 8000994: f43f af3b beq.w 800080e <__aeabi_dmul+0x24a> - 8000998: ea94 0f0c teq r4, ip - 800099c: d10a bne.n 80009b4 <__aeabi_ddiv+0x19c> - 800099e: ea50 3401 orrs.w r4, r0, r1, lsl #12 - 80009a2: f47f af34 bne.w 800080e <__aeabi_dmul+0x24a> - 80009a6: ea95 0f0c teq r5, ip - 80009aa: f47f af25 bne.w 80007f8 <__aeabi_dmul+0x234> - 80009ae: 4610 mov r0, r2 - 80009b0: 4619 mov r1, r3 - 80009b2: e72c b.n 800080e <__aeabi_dmul+0x24a> - 80009b4: ea95 0f0c teq r5, ip - 80009b8: d106 bne.n 80009c8 <__aeabi_ddiv+0x1b0> - 80009ba: ea52 3503 orrs.w r5, r2, r3, lsl #12 - 80009be: f43f aefd beq.w 80007bc <__aeabi_dmul+0x1f8> - 80009c2: 4610 mov r0, r2 - 80009c4: 4619 mov r1, r3 - 80009c6: e722 b.n 800080e <__aeabi_dmul+0x24a> - 80009c8: ea50 0641 orrs.w r6, r0, r1, lsl #1 - 80009cc: bf18 it ne - 80009ce: ea52 0643 orrsne.w r6, r2, r3, lsl #1 - 80009d2: f47f aec5 bne.w 8000760 <__aeabi_dmul+0x19c> - 80009d6: ea50 0441 orrs.w r4, r0, r1, lsl #1 - 80009da: f47f af0d bne.w 80007f8 <__aeabi_dmul+0x234> - 80009de: ea52 0543 orrs.w r5, r2, r3, lsl #1 - 80009e2: f47f aeeb bne.w 80007bc <__aeabi_dmul+0x1f8> - 80009e6: e712 b.n 800080e <__aeabi_dmul+0x24a> - -080009e8 <__gedf2>: - 80009e8: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff - 80009ec: e006 b.n 80009fc <__cmpdf2+0x4> - 80009ee: bf00 nop - -080009f0 <__ledf2>: - 80009f0: f04f 0c01 mov.w ip, #1 - 80009f4: e002 b.n 80009fc <__cmpdf2+0x4> - 80009f6: bf00 nop - -080009f8 <__cmpdf2>: - 80009f8: f04f 0c01 mov.w ip, #1 - 80009fc: f84d cd04 str.w ip, [sp, #-4]! - 8000a00: ea4f 0c41 mov.w ip, r1, lsl #1 - 8000a04: ea7f 5c6c mvns.w ip, ip, asr #21 - 8000a08: ea4f 0c43 mov.w ip, r3, lsl #1 - 8000a0c: bf18 it ne - 8000a0e: ea7f 5c6c mvnsne.w ip, ip, asr #21 - 8000a12: d01b beq.n 8000a4c <__cmpdf2+0x54> - 8000a14: b001 add sp, #4 - 8000a16: ea50 0c41 orrs.w ip, r0, r1, lsl #1 - 8000a1a: bf0c ite eq - 8000a1c: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 - 8000a20: ea91 0f03 teqne r1, r3 - 8000a24: bf02 ittt eq - 8000a26: ea90 0f02 teqeq r0, r2 - 8000a2a: 2000 moveq r0, #0 - 8000a2c: 4770 bxeq lr - 8000a2e: f110 0f00 cmn.w r0, #0 - 8000a32: ea91 0f03 teq r1, r3 - 8000a36: bf58 it pl - 8000a38: 4299 cmppl r1, r3 - 8000a3a: bf08 it eq - 8000a3c: 4290 cmpeq r0, r2 - 8000a3e: bf2c ite cs - 8000a40: 17d8 asrcs r0, r3, #31 - 8000a42: ea6f 70e3 mvncc.w r0, r3, asr #31 - 8000a46: f040 0001 orr.w r0, r0, #1 - 8000a4a: 4770 bx lr - 8000a4c: ea4f 0c41 mov.w ip, r1, lsl #1 - 8000a50: ea7f 5c6c mvns.w ip, ip, asr #21 - 8000a54: d102 bne.n 8000a5c <__cmpdf2+0x64> - 8000a56: ea50 3c01 orrs.w ip, r0, r1, lsl #12 - 8000a5a: d107 bne.n 8000a6c <__cmpdf2+0x74> - 8000a5c: ea4f 0c43 mov.w ip, r3, lsl #1 - 8000a60: ea7f 5c6c mvns.w ip, ip, asr #21 - 8000a64: d1d6 bne.n 8000a14 <__cmpdf2+0x1c> - 8000a66: ea52 3c03 orrs.w ip, r2, r3, lsl #12 - 8000a6a: d0d3 beq.n 8000a14 <__cmpdf2+0x1c> - 8000a6c: f85d 0b04 ldr.w r0, [sp], #4 - 8000a70: 4770 bx lr - 8000a72: bf00 nop - -08000a74 <__aeabi_cdrcmple>: - 8000a74: 4684 mov ip, r0 - 8000a76: 4610 mov r0, r2 - 8000a78: 4662 mov r2, ip - 8000a7a: 468c mov ip, r1 - 8000a7c: 4619 mov r1, r3 - 8000a7e: 4663 mov r3, ip - 8000a80: e000 b.n 8000a84 <__aeabi_cdcmpeq> - 8000a82: bf00 nop - -08000a84 <__aeabi_cdcmpeq>: - 8000a84: b501 push {r0, lr} - 8000a86: f7ff ffb7 bl 80009f8 <__cmpdf2> - 8000a8a: 2800 cmp r0, #0 - 8000a8c: bf48 it mi - 8000a8e: f110 0f00 cmnmi.w r0, #0 - 8000a92: bd01 pop {r0, pc} - -08000a94 <__aeabi_dcmpeq>: - 8000a94: f84d ed08 str.w lr, [sp, #-8]! - 8000a98: f7ff fff4 bl 8000a84 <__aeabi_cdcmpeq> - 8000a9c: bf0c ite eq - 8000a9e: 2001 moveq r0, #1 - 8000aa0: 2000 movne r0, #0 - 8000aa2: f85d fb08 ldr.w pc, [sp], #8 - 8000aa6: bf00 nop - -08000aa8 <__aeabi_dcmplt>: - 8000aa8: f84d ed08 str.w lr, [sp, #-8]! - 8000aac: f7ff ffea bl 8000a84 <__aeabi_cdcmpeq> - 8000ab0: bf34 ite cc - 8000ab2: 2001 movcc r0, #1 - 8000ab4: 2000 movcs r0, #0 - 8000ab6: f85d fb08 ldr.w pc, [sp], #8 - 8000aba: bf00 nop - -08000abc <__aeabi_dcmple>: - 8000abc: f84d ed08 str.w lr, [sp, #-8]! - 8000ac0: f7ff ffe0 bl 8000a84 <__aeabi_cdcmpeq> - 8000ac4: bf94 ite ls - 8000ac6: 2001 movls r0, #1 - 8000ac8: 2000 movhi r0, #0 - 8000aca: f85d fb08 ldr.w pc, [sp], #8 - 8000ace: bf00 nop - -08000ad0 <__aeabi_dcmpge>: - 8000ad0: f84d ed08 str.w lr, [sp, #-8]! - 8000ad4: f7ff ffce bl 8000a74 <__aeabi_cdrcmple> - 8000ad8: bf94 ite ls - 8000ada: 2001 movls r0, #1 - 8000adc: 2000 movhi r0, #0 - 8000ade: f85d fb08 ldr.w pc, [sp], #8 - 8000ae2: bf00 nop - -08000ae4 <__aeabi_dcmpgt>: - 8000ae4: f84d ed08 str.w lr, [sp, #-8]! - 8000ae8: f7ff ffc4 bl 8000a74 <__aeabi_cdrcmple> - 8000aec: bf34 ite cc - 8000aee: 2001 movcc r0, #1 - 8000af0: 2000 movcs r0, #0 - 8000af2: f85d fb08 ldr.w pc, [sp], #8 - 8000af6: bf00 nop - -08000af8 <__aeabi_dcmpun>: - 8000af8: ea4f 0c41 mov.w ip, r1, lsl #1 - 8000afc: ea7f 5c6c mvns.w ip, ip, asr #21 - 8000b00: d102 bne.n 8000b08 <__aeabi_dcmpun+0x10> - 8000b02: ea50 3c01 orrs.w ip, r0, r1, lsl #12 - 8000b06: d10a bne.n 8000b1e <__aeabi_dcmpun+0x26> - 8000b08: ea4f 0c43 mov.w ip, r3, lsl #1 - 8000b0c: ea7f 5c6c mvns.w ip, ip, asr #21 - 8000b10: d102 bne.n 8000b18 <__aeabi_dcmpun+0x20> - 8000b12: ea52 3c03 orrs.w ip, r2, r3, lsl #12 - 8000b16: d102 bne.n 8000b1e <__aeabi_dcmpun+0x26> - 8000b18: f04f 0000 mov.w r0, #0 - 8000b1c: 4770 bx lr - 8000b1e: f04f 0001 mov.w r0, #1 - 8000b22: 4770 bx lr - -08000b24 <__aeabi_d2iz>: - 8000b24: ea4f 0241 mov.w r2, r1, lsl #1 - 8000b28: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 - 8000b2c: d215 bcs.n 8000b5a <__aeabi_d2iz+0x36> - 8000b2e: d511 bpl.n 8000b54 <__aeabi_d2iz+0x30> - 8000b30: f46f 7378 mvn.w r3, #992 @ 0x3e0 - 8000b34: ebb3 5262 subs.w r2, r3, r2, asr #21 - 8000b38: d912 bls.n 8000b60 <__aeabi_d2iz+0x3c> - 8000b3a: ea4f 23c1 mov.w r3, r1, lsl #11 - 8000b3e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 - 8000b42: ea43 5350 orr.w r3, r3, r0, lsr #21 - 8000b46: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 - 8000b4a: fa23 f002 lsr.w r0, r3, r2 - 8000b4e: bf18 it ne - 8000b50: 4240 negne r0, r0 - 8000b52: 4770 bx lr - 8000b54: f04f 0000 mov.w r0, #0 - 8000b58: 4770 bx lr - 8000b5a: ea50 3001 orrs.w r0, r0, r1, lsl #12 - 8000b5e: d105 bne.n 8000b6c <__aeabi_d2iz+0x48> - 8000b60: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 - 8000b64: bf08 it eq - 8000b66: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 - 8000b6a: 4770 bx lr - 8000b6c: f04f 0000 mov.w r0, #0 - 8000b70: 4770 bx lr - 8000b72: bf00 nop - -08000b74 <__aeabi_d2f>: - 8000b74: ea4f 0241 mov.w r2, r1, lsl #1 - 8000b78: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 - 8000b7c: bf24 itt cs - 8000b7e: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 - 8000b82: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 - 8000b86: d90d bls.n 8000ba4 <__aeabi_d2f+0x30> - 8000b88: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 - 8000b8c: ea4f 02c0 mov.w r2, r0, lsl #3 - 8000b90: ea4c 7050 orr.w r0, ip, r0, lsr #29 - 8000b94: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 - 8000b98: eb40 0083 adc.w r0, r0, r3, lsl #2 - 8000b9c: bf08 it eq - 8000b9e: f020 0001 biceq.w r0, r0, #1 - 8000ba2: 4770 bx lr - 8000ba4: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 - 8000ba8: d121 bne.n 8000bee <__aeabi_d2f+0x7a> - 8000baa: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 - 8000bae: bfbc itt lt - 8000bb0: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 - 8000bb4: 4770 bxlt lr - 8000bb6: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 - 8000bba: ea4f 5252 mov.w r2, r2, lsr #21 - 8000bbe: f1c2 0218 rsb r2, r2, #24 - 8000bc2: f1c2 0c20 rsb ip, r2, #32 - 8000bc6: fa10 f30c lsls.w r3, r0, ip - 8000bca: fa20 f002 lsr.w r0, r0, r2 - 8000bce: bf18 it ne - 8000bd0: f040 0001 orrne.w r0, r0, #1 - 8000bd4: ea4f 23c1 mov.w r3, r1, lsl #11 - 8000bd8: ea4f 23d3 mov.w r3, r3, lsr #11 - 8000bdc: fa03 fc0c lsl.w ip, r3, ip - 8000be0: ea40 000c orr.w r0, r0, ip - 8000be4: fa23 f302 lsr.w r3, r3, r2 - 8000be8: ea4f 0343 mov.w r3, r3, lsl #1 - 8000bec: e7cc b.n 8000b88 <__aeabi_d2f+0x14> - 8000bee: ea7f 5362 mvns.w r3, r2, asr #21 - 8000bf2: d107 bne.n 8000c04 <__aeabi_d2f+0x90> - 8000bf4: ea50 3301 orrs.w r3, r0, r1, lsl #12 - 8000bf8: bf1e ittt ne - 8000bfa: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 - 8000bfe: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 - 8000c02: 4770 bxne lr - 8000c04: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 - 8000c08: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 - 8000c0c: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 8000c10: 4770 bx lr - 8000c12: bf00 nop - -08000c14 <__aeabi_frsub>: - 8000c14: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 - 8000c18: e002 b.n 8000c20 <__addsf3> - 8000c1a: bf00 nop - -08000c1c <__aeabi_fsub>: - 8000c1c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 - -08000c20 <__addsf3>: - 8000c20: 0042 lsls r2, r0, #1 - 8000c22: bf1f itttt ne - 8000c24: ea5f 0341 movsne.w r3, r1, lsl #1 - 8000c28: ea92 0f03 teqne r2, r3 - 8000c2c: ea7f 6c22 mvnsne.w ip, r2, asr #24 - 8000c30: ea7f 6c23 mvnsne.w ip, r3, asr #24 - 8000c34: d06a beq.n 8000d0c <__addsf3+0xec> - 8000c36: ea4f 6212 mov.w r2, r2, lsr #24 - 8000c3a: ebd2 6313 rsbs r3, r2, r3, lsr #24 - 8000c3e: bfc1 itttt gt - 8000c40: 18d2 addgt r2, r2, r3 - 8000c42: 4041 eorgt r1, r0 - 8000c44: 4048 eorgt r0, r1 - 8000c46: 4041 eorgt r1, r0 - 8000c48: bfb8 it lt - 8000c4a: 425b neglt r3, r3 - 8000c4c: 2b19 cmp r3, #25 - 8000c4e: bf88 it hi - 8000c50: 4770 bxhi lr - 8000c52: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 - 8000c56: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 8000c5a: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 - 8000c5e: bf18 it ne - 8000c60: 4240 negne r0, r0 - 8000c62: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 - 8000c66: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 - 8000c6a: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 - 8000c6e: bf18 it ne - 8000c70: 4249 negne r1, r1 - 8000c72: ea92 0f03 teq r2, r3 - 8000c76: d03f beq.n 8000cf8 <__addsf3+0xd8> - 8000c78: f1a2 0201 sub.w r2, r2, #1 - 8000c7c: fa41 fc03 asr.w ip, r1, r3 - 8000c80: eb10 000c adds.w r0, r0, ip - 8000c84: f1c3 0320 rsb r3, r3, #32 - 8000c88: fa01 f103 lsl.w r1, r1, r3 - 8000c8c: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 - 8000c90: d502 bpl.n 8000c98 <__addsf3+0x78> - 8000c92: 4249 negs r1, r1 - 8000c94: eb60 0040 sbc.w r0, r0, r0, lsl #1 - 8000c98: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 - 8000c9c: d313 bcc.n 8000cc6 <__addsf3+0xa6> - 8000c9e: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 - 8000ca2: d306 bcc.n 8000cb2 <__addsf3+0x92> - 8000ca4: 0840 lsrs r0, r0, #1 - 8000ca6: ea4f 0131 mov.w r1, r1, rrx - 8000caa: f102 0201 add.w r2, r2, #1 - 8000cae: 2afe cmp r2, #254 @ 0xfe - 8000cb0: d251 bcs.n 8000d56 <__addsf3+0x136> - 8000cb2: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 - 8000cb6: eb40 50c2 adc.w r0, r0, r2, lsl #23 - 8000cba: bf08 it eq - 8000cbc: f020 0001 biceq.w r0, r0, #1 - 8000cc0: ea40 0003 orr.w r0, r0, r3 - 8000cc4: 4770 bx lr - 8000cc6: 0049 lsls r1, r1, #1 - 8000cc8: eb40 0000 adc.w r0, r0, r0 - 8000ccc: 3a01 subs r2, #1 - 8000cce: bf28 it cs - 8000cd0: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 - 8000cd4: d2ed bcs.n 8000cb2 <__addsf3+0x92> - 8000cd6: fab0 fc80 clz ip, r0 - 8000cda: f1ac 0c08 sub.w ip, ip, #8 - 8000cde: ebb2 020c subs.w r2, r2, ip - 8000ce2: fa00 f00c lsl.w r0, r0, ip - 8000ce6: bfaa itet ge - 8000ce8: eb00 50c2 addge.w r0, r0, r2, lsl #23 - 8000cec: 4252 neglt r2, r2 - 8000cee: 4318 orrge r0, r3 - 8000cf0: bfbc itt lt - 8000cf2: 40d0 lsrlt r0, r2 - 8000cf4: 4318 orrlt r0, r3 - 8000cf6: 4770 bx lr - 8000cf8: f092 0f00 teq r2, #0 - 8000cfc: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 - 8000d00: bf06 itte eq - 8000d02: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 - 8000d06: 3201 addeq r2, #1 - 8000d08: 3b01 subne r3, #1 - 8000d0a: e7b5 b.n 8000c78 <__addsf3+0x58> - 8000d0c: ea4f 0341 mov.w r3, r1, lsl #1 - 8000d10: ea7f 6c22 mvns.w ip, r2, asr #24 - 8000d14: bf18 it ne - 8000d16: ea7f 6c23 mvnsne.w ip, r3, asr #24 - 8000d1a: d021 beq.n 8000d60 <__addsf3+0x140> - 8000d1c: ea92 0f03 teq r2, r3 - 8000d20: d004 beq.n 8000d2c <__addsf3+0x10c> - 8000d22: f092 0f00 teq r2, #0 - 8000d26: bf08 it eq - 8000d28: 4608 moveq r0, r1 - 8000d2a: 4770 bx lr - 8000d2c: ea90 0f01 teq r0, r1 - 8000d30: bf1c itt ne - 8000d32: 2000 movne r0, #0 - 8000d34: 4770 bxne lr - 8000d36: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 - 8000d3a: d104 bne.n 8000d46 <__addsf3+0x126> - 8000d3c: 0040 lsls r0, r0, #1 - 8000d3e: bf28 it cs - 8000d40: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 - 8000d44: 4770 bx lr - 8000d46: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 - 8000d4a: bf3c itt cc - 8000d4c: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 - 8000d50: 4770 bxcc lr - 8000d52: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 - 8000d56: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 - 8000d5a: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 8000d5e: 4770 bx lr - 8000d60: ea7f 6222 mvns.w r2, r2, asr #24 - 8000d64: bf16 itet ne - 8000d66: 4608 movne r0, r1 - 8000d68: ea7f 6323 mvnseq.w r3, r3, asr #24 - 8000d6c: 4601 movne r1, r0 - 8000d6e: 0242 lsls r2, r0, #9 - 8000d70: bf06 itte eq - 8000d72: ea5f 2341 movseq.w r3, r1, lsl #9 - 8000d76: ea90 0f01 teqeq r0, r1 - 8000d7a: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 - 8000d7e: 4770 bx lr - -08000d80 <__aeabi_ui2f>: - 8000d80: f04f 0300 mov.w r3, #0 - 8000d84: e004 b.n 8000d90 <__aeabi_i2f+0x8> - 8000d86: bf00 nop - -08000d88 <__aeabi_i2f>: - 8000d88: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 - 8000d8c: bf48 it mi - 8000d8e: 4240 negmi r0, r0 - 8000d90: ea5f 0c00 movs.w ip, r0 - 8000d94: bf08 it eq - 8000d96: 4770 bxeq lr - 8000d98: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 - 8000d9c: 4601 mov r1, r0 - 8000d9e: f04f 0000 mov.w r0, #0 - 8000da2: e01c b.n 8000dde <__aeabi_l2f+0x2a> - -08000da4 <__aeabi_ul2f>: - 8000da4: ea50 0201 orrs.w r2, r0, r1 - 8000da8: bf08 it eq - 8000daa: 4770 bxeq lr - 8000dac: f04f 0300 mov.w r3, #0 - 8000db0: e00a b.n 8000dc8 <__aeabi_l2f+0x14> - 8000db2: bf00 nop - -08000db4 <__aeabi_l2f>: - 8000db4: ea50 0201 orrs.w r2, r0, r1 - 8000db8: bf08 it eq - 8000dba: 4770 bxeq lr - 8000dbc: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 - 8000dc0: d502 bpl.n 8000dc8 <__aeabi_l2f+0x14> - 8000dc2: 4240 negs r0, r0 - 8000dc4: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 8000dc8: ea5f 0c01 movs.w ip, r1 - 8000dcc: bf02 ittt eq - 8000dce: 4684 moveq ip, r0 - 8000dd0: 4601 moveq r1, r0 - 8000dd2: 2000 moveq r0, #0 - 8000dd4: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 - 8000dd8: bf08 it eq - 8000dda: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 - 8000dde: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 - 8000de2: fabc f28c clz r2, ip - 8000de6: 3a08 subs r2, #8 - 8000de8: eba3 53c2 sub.w r3, r3, r2, lsl #23 - 8000dec: db10 blt.n 8000e10 <__aeabi_l2f+0x5c> - 8000dee: fa01 fc02 lsl.w ip, r1, r2 - 8000df2: 4463 add r3, ip - 8000df4: fa00 fc02 lsl.w ip, r0, r2 - 8000df8: f1c2 0220 rsb r2, r2, #32 - 8000dfc: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 - 8000e00: fa20 f202 lsr.w r2, r0, r2 - 8000e04: eb43 0002 adc.w r0, r3, r2 - 8000e08: bf08 it eq - 8000e0a: f020 0001 biceq.w r0, r0, #1 - 8000e0e: 4770 bx lr - 8000e10: f102 0220 add.w r2, r2, #32 - 8000e14: fa01 fc02 lsl.w ip, r1, r2 - 8000e18: f1c2 0220 rsb r2, r2, #32 - 8000e1c: ea50 004c orrs.w r0, r0, ip, lsl #1 - 8000e20: fa21 f202 lsr.w r2, r1, r2 - 8000e24: eb43 0002 adc.w r0, r3, r2 - 8000e28: bf08 it eq - 8000e2a: ea20 70dc biceq.w r0, r0, ip, lsr #31 - 8000e2e: 4770 bx lr - -08000e30 <__aeabi_fmul>: - 8000e30: f04f 0cff mov.w ip, #255 @ 0xff - 8000e34: ea1c 52d0 ands.w r2, ip, r0, lsr #23 - 8000e38: bf1e ittt ne - 8000e3a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 - 8000e3e: ea92 0f0c teqne r2, ip - 8000e42: ea93 0f0c teqne r3, ip - 8000e46: d06f beq.n 8000f28 <__aeabi_fmul+0xf8> - 8000e48: 441a add r2, r3 - 8000e4a: ea80 0c01 eor.w ip, r0, r1 - 8000e4e: 0240 lsls r0, r0, #9 - 8000e50: bf18 it ne - 8000e52: ea5f 2141 movsne.w r1, r1, lsl #9 - 8000e56: d01e beq.n 8000e96 <__aeabi_fmul+0x66> - 8000e58: f04f 6300 mov.w r3, #134217728 @ 0x8000000 - 8000e5c: ea43 1050 orr.w r0, r3, r0, lsr #5 - 8000e60: ea43 1151 orr.w r1, r3, r1, lsr #5 - 8000e64: fba0 3101 umull r3, r1, r0, r1 - 8000e68: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 - 8000e6c: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 - 8000e70: bf3e ittt cc - 8000e72: 0049 lslcc r1, r1, #1 - 8000e74: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 - 8000e78: 005b lslcc r3, r3, #1 - 8000e7a: ea40 0001 orr.w r0, r0, r1 - 8000e7e: f162 027f sbc.w r2, r2, #127 @ 0x7f - 8000e82: 2afd cmp r2, #253 @ 0xfd - 8000e84: d81d bhi.n 8000ec2 <__aeabi_fmul+0x92> - 8000e86: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 - 8000e8a: eb40 50c2 adc.w r0, r0, r2, lsl #23 - 8000e8e: bf08 it eq - 8000e90: f020 0001 biceq.w r0, r0, #1 - 8000e94: 4770 bx lr - 8000e96: f090 0f00 teq r0, #0 - 8000e9a: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 - 8000e9e: bf08 it eq - 8000ea0: 0249 lsleq r1, r1, #9 - 8000ea2: ea4c 2050 orr.w r0, ip, r0, lsr #9 - 8000ea6: ea40 2051 orr.w r0, r0, r1, lsr #9 - 8000eaa: 3a7f subs r2, #127 @ 0x7f - 8000eac: bfc2 ittt gt - 8000eae: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff - 8000eb2: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 - 8000eb6: 4770 bxgt lr - 8000eb8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 8000ebc: f04f 0300 mov.w r3, #0 - 8000ec0: 3a01 subs r2, #1 - 8000ec2: dc5d bgt.n 8000f80 <__aeabi_fmul+0x150> - 8000ec4: f112 0f19 cmn.w r2, #25 - 8000ec8: bfdc itt le - 8000eca: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 - 8000ece: 4770 bxle lr - 8000ed0: f1c2 0200 rsb r2, r2, #0 - 8000ed4: 0041 lsls r1, r0, #1 - 8000ed6: fa21 f102 lsr.w r1, r1, r2 - 8000eda: f1c2 0220 rsb r2, r2, #32 - 8000ede: fa00 fc02 lsl.w ip, r0, r2 - 8000ee2: ea5f 0031 movs.w r0, r1, rrx - 8000ee6: f140 0000 adc.w r0, r0, #0 - 8000eea: ea53 034c orrs.w r3, r3, ip, lsl #1 - 8000eee: bf08 it eq - 8000ef0: ea20 70dc biceq.w r0, r0, ip, lsr #31 - 8000ef4: 4770 bx lr - 8000ef6: f092 0f00 teq r2, #0 - 8000efa: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 - 8000efe: bf02 ittt eq - 8000f00: 0040 lsleq r0, r0, #1 - 8000f02: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 - 8000f06: 3a01 subeq r2, #1 - 8000f08: d0f9 beq.n 8000efe <__aeabi_fmul+0xce> - 8000f0a: ea40 000c orr.w r0, r0, ip - 8000f0e: f093 0f00 teq r3, #0 - 8000f12: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 - 8000f16: bf02 ittt eq - 8000f18: 0049 lsleq r1, r1, #1 - 8000f1a: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 - 8000f1e: 3b01 subeq r3, #1 - 8000f20: d0f9 beq.n 8000f16 <__aeabi_fmul+0xe6> - 8000f22: ea41 010c orr.w r1, r1, ip - 8000f26: e78f b.n 8000e48 <__aeabi_fmul+0x18> - 8000f28: ea0c 53d1 and.w r3, ip, r1, lsr #23 - 8000f2c: ea92 0f0c teq r2, ip - 8000f30: bf18 it ne - 8000f32: ea93 0f0c teqne r3, ip - 8000f36: d00a beq.n 8000f4e <__aeabi_fmul+0x11e> - 8000f38: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 - 8000f3c: bf18 it ne - 8000f3e: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 - 8000f42: d1d8 bne.n 8000ef6 <__aeabi_fmul+0xc6> - 8000f44: ea80 0001 eor.w r0, r0, r1 - 8000f48: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 - 8000f4c: 4770 bx lr - 8000f4e: f090 0f00 teq r0, #0 - 8000f52: bf17 itett ne - 8000f54: f090 4f00 teqne r0, #2147483648 @ 0x80000000 - 8000f58: 4608 moveq r0, r1 - 8000f5a: f091 0f00 teqne r1, #0 - 8000f5e: f091 4f00 teqne r1, #2147483648 @ 0x80000000 - 8000f62: d014 beq.n 8000f8e <__aeabi_fmul+0x15e> - 8000f64: ea92 0f0c teq r2, ip - 8000f68: d101 bne.n 8000f6e <__aeabi_fmul+0x13e> - 8000f6a: 0242 lsls r2, r0, #9 - 8000f6c: d10f bne.n 8000f8e <__aeabi_fmul+0x15e> - 8000f6e: ea93 0f0c teq r3, ip - 8000f72: d103 bne.n 8000f7c <__aeabi_fmul+0x14c> - 8000f74: 024b lsls r3, r1, #9 - 8000f76: bf18 it ne - 8000f78: 4608 movne r0, r1 - 8000f7a: d108 bne.n 8000f8e <__aeabi_fmul+0x15e> - 8000f7c: ea80 0001 eor.w r0, r0, r1 - 8000f80: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 - 8000f84: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 - 8000f88: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 8000f8c: 4770 bx lr - 8000f8e: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 - 8000f92: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 - 8000f96: 4770 bx lr - -08000f98 <__aeabi_fdiv>: - 8000f98: f04f 0cff mov.w ip, #255 @ 0xff - 8000f9c: ea1c 52d0 ands.w r2, ip, r0, lsr #23 - 8000fa0: bf1e ittt ne - 8000fa2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 - 8000fa6: ea92 0f0c teqne r2, ip - 8000faa: ea93 0f0c teqne r3, ip - 8000fae: d069 beq.n 8001084 <__aeabi_fdiv+0xec> - 8000fb0: eba2 0203 sub.w r2, r2, r3 - 8000fb4: ea80 0c01 eor.w ip, r0, r1 - 8000fb8: 0249 lsls r1, r1, #9 - 8000fba: ea4f 2040 mov.w r0, r0, lsl #9 - 8000fbe: d037 beq.n 8001030 <__aeabi_fdiv+0x98> - 8000fc0: f04f 5380 mov.w r3, #268435456 @ 0x10000000 - 8000fc4: ea43 1111 orr.w r1, r3, r1, lsr #4 - 8000fc8: ea43 1310 orr.w r3, r3, r0, lsr #4 - 8000fcc: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 - 8000fd0: 428b cmp r3, r1 - 8000fd2: bf38 it cc - 8000fd4: 005b lslcc r3, r3, #1 - 8000fd6: f142 027d adc.w r2, r2, #125 @ 0x7d - 8000fda: f44f 0c00 mov.w ip, #8388608 @ 0x800000 - 8000fde: 428b cmp r3, r1 - 8000fe0: bf24 itt cs - 8000fe2: 1a5b subcs r3, r3, r1 - 8000fe4: ea40 000c orrcs.w r0, r0, ip - 8000fe8: ebb3 0f51 cmp.w r3, r1, lsr #1 - 8000fec: bf24 itt cs - 8000fee: eba3 0351 subcs.w r3, r3, r1, lsr #1 - 8000ff2: ea40 005c orrcs.w r0, r0, ip, lsr #1 - 8000ff6: ebb3 0f91 cmp.w r3, r1, lsr #2 - 8000ffa: bf24 itt cs - 8000ffc: eba3 0391 subcs.w r3, r3, r1, lsr #2 - 8001000: ea40 009c orrcs.w r0, r0, ip, lsr #2 - 8001004: ebb3 0fd1 cmp.w r3, r1, lsr #3 - 8001008: bf24 itt cs - 800100a: eba3 03d1 subcs.w r3, r3, r1, lsr #3 - 800100e: ea40 00dc orrcs.w r0, r0, ip, lsr #3 - 8001012: 011b lsls r3, r3, #4 - 8001014: bf18 it ne - 8001016: ea5f 1c1c movsne.w ip, ip, lsr #4 - 800101a: d1e0 bne.n 8000fde <__aeabi_fdiv+0x46> - 800101c: 2afd cmp r2, #253 @ 0xfd - 800101e: f63f af50 bhi.w 8000ec2 <__aeabi_fmul+0x92> - 8001022: 428b cmp r3, r1 - 8001024: eb40 50c2 adc.w r0, r0, r2, lsl #23 - 8001028: bf08 it eq - 800102a: f020 0001 biceq.w r0, r0, #1 - 800102e: 4770 bx lr - 8001030: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 - 8001034: ea4c 2050 orr.w r0, ip, r0, lsr #9 - 8001038: 327f adds r2, #127 @ 0x7f - 800103a: bfc2 ittt gt - 800103c: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff - 8001040: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 - 8001044: 4770 bxgt lr - 8001046: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 - 800104a: f04f 0300 mov.w r3, #0 - 800104e: 3a01 subs r2, #1 - 8001050: e737 b.n 8000ec2 <__aeabi_fmul+0x92> - 8001052: f092 0f00 teq r2, #0 - 8001056: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 - 800105a: bf02 ittt eq - 800105c: 0040 lsleq r0, r0, #1 - 800105e: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 - 8001062: 3a01 subeq r2, #1 - 8001064: d0f9 beq.n 800105a <__aeabi_fdiv+0xc2> - 8001066: ea40 000c orr.w r0, r0, ip - 800106a: f093 0f00 teq r3, #0 - 800106e: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 - 8001072: bf02 ittt eq - 8001074: 0049 lsleq r1, r1, #1 - 8001076: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 - 800107a: 3b01 subeq r3, #1 - 800107c: d0f9 beq.n 8001072 <__aeabi_fdiv+0xda> - 800107e: ea41 010c orr.w r1, r1, ip - 8001082: e795 b.n 8000fb0 <__aeabi_fdiv+0x18> - 8001084: ea0c 53d1 and.w r3, ip, r1, lsr #23 - 8001088: ea92 0f0c teq r2, ip - 800108c: d108 bne.n 80010a0 <__aeabi_fdiv+0x108> - 800108e: 0242 lsls r2, r0, #9 - 8001090: f47f af7d bne.w 8000f8e <__aeabi_fmul+0x15e> - 8001094: ea93 0f0c teq r3, ip - 8001098: f47f af70 bne.w 8000f7c <__aeabi_fmul+0x14c> - 800109c: 4608 mov r0, r1 - 800109e: e776 b.n 8000f8e <__aeabi_fmul+0x15e> - 80010a0: ea93 0f0c teq r3, ip - 80010a4: d104 bne.n 80010b0 <__aeabi_fdiv+0x118> - 80010a6: 024b lsls r3, r1, #9 - 80010a8: f43f af4c beq.w 8000f44 <__aeabi_fmul+0x114> - 80010ac: 4608 mov r0, r1 - 80010ae: e76e b.n 8000f8e <__aeabi_fmul+0x15e> - 80010b0: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 - 80010b4: bf18 it ne - 80010b6: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 - 80010ba: d1ca bne.n 8001052 <__aeabi_fdiv+0xba> - 80010bc: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 - 80010c0: f47f af5c bne.w 8000f7c <__aeabi_fmul+0x14c> - 80010c4: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 - 80010c8: f47f af3c bne.w 8000f44 <__aeabi_fmul+0x114> - 80010cc: e75f b.n 8000f8e <__aeabi_fmul+0x15e> - 80010ce: bf00 nop - -080010d0 <__gesf2>: - 80010d0: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff - 80010d4: e006 b.n 80010e4 <__cmpsf2+0x4> - 80010d6: bf00 nop - -080010d8 <__lesf2>: - 80010d8: f04f 0c01 mov.w ip, #1 - 80010dc: e002 b.n 80010e4 <__cmpsf2+0x4> - 80010de: bf00 nop - -080010e0 <__cmpsf2>: - 80010e0: f04f 0c01 mov.w ip, #1 - 80010e4: f84d cd04 str.w ip, [sp, #-4]! - 80010e8: ea4f 0240 mov.w r2, r0, lsl #1 - 80010ec: ea4f 0341 mov.w r3, r1, lsl #1 - 80010f0: ea7f 6c22 mvns.w ip, r2, asr #24 - 80010f4: bf18 it ne - 80010f6: ea7f 6c23 mvnsne.w ip, r3, asr #24 - 80010fa: d011 beq.n 8001120 <__cmpsf2+0x40> - 80010fc: b001 add sp, #4 - 80010fe: ea52 0c53 orrs.w ip, r2, r3, lsr #1 - 8001102: bf18 it ne - 8001104: ea90 0f01 teqne r0, r1 - 8001108: bf58 it pl - 800110a: ebb2 0003 subspl.w r0, r2, r3 - 800110e: bf88 it hi - 8001110: 17c8 asrhi r0, r1, #31 - 8001112: bf38 it cc - 8001114: ea6f 70e1 mvncc.w r0, r1, asr #31 - 8001118: bf18 it ne - 800111a: f040 0001 orrne.w r0, r0, #1 - 800111e: 4770 bx lr - 8001120: ea7f 6c22 mvns.w ip, r2, asr #24 - 8001124: d102 bne.n 800112c <__cmpsf2+0x4c> - 8001126: ea5f 2c40 movs.w ip, r0, lsl #9 - 800112a: d105 bne.n 8001138 <__cmpsf2+0x58> - 800112c: ea7f 6c23 mvns.w ip, r3, asr #24 - 8001130: d1e4 bne.n 80010fc <__cmpsf2+0x1c> - 8001132: ea5f 2c41 movs.w ip, r1, lsl #9 - 8001136: d0e1 beq.n 80010fc <__cmpsf2+0x1c> - 8001138: f85d 0b04 ldr.w r0, [sp], #4 - 800113c: 4770 bx lr - 800113e: bf00 nop - -08001140 <__aeabi_cfrcmple>: - 8001140: 4684 mov ip, r0 - 8001142: 4608 mov r0, r1 - 8001144: 4661 mov r1, ip - 8001146: e7ff b.n 8001148 <__aeabi_cfcmpeq> - -08001148 <__aeabi_cfcmpeq>: - 8001148: b50f push {r0, r1, r2, r3, lr} - 800114a: f7ff ffc9 bl 80010e0 <__cmpsf2> - 800114e: 2800 cmp r0, #0 - 8001150: bf48 it mi - 8001152: f110 0f00 cmnmi.w r0, #0 - 8001156: bd0f pop {r0, r1, r2, r3, pc} - -08001158 <__aeabi_fcmpeq>: - 8001158: f84d ed08 str.w lr, [sp, #-8]! - 800115c: f7ff fff4 bl 8001148 <__aeabi_cfcmpeq> - 8001160: bf0c ite eq - 8001162: 2001 moveq r0, #1 - 8001164: 2000 movne r0, #0 - 8001166: f85d fb08 ldr.w pc, [sp], #8 - 800116a: bf00 nop - -0800116c <__aeabi_fcmplt>: - 800116c: f84d ed08 str.w lr, [sp, #-8]! - 8001170: f7ff ffea bl 8001148 <__aeabi_cfcmpeq> - 8001174: bf34 ite cc - 8001176: 2001 movcc r0, #1 - 8001178: 2000 movcs r0, #0 - 800117a: f85d fb08 ldr.w pc, [sp], #8 - 800117e: bf00 nop - -08001180 <__aeabi_fcmple>: - 8001180: f84d ed08 str.w lr, [sp, #-8]! - 8001184: f7ff ffe0 bl 8001148 <__aeabi_cfcmpeq> - 8001188: bf94 ite ls - 800118a: 2001 movls r0, #1 - 800118c: 2000 movhi r0, #0 - 800118e: f85d fb08 ldr.w pc, [sp], #8 - 8001192: bf00 nop - -08001194 <__aeabi_fcmpge>: - 8001194: f84d ed08 str.w lr, [sp, #-8]! - 8001198: f7ff ffd2 bl 8001140 <__aeabi_cfrcmple> - 800119c: bf94 ite ls - 800119e: 2001 movls r0, #1 - 80011a0: 2000 movhi r0, #0 - 80011a2: f85d fb08 ldr.w pc, [sp], #8 - 80011a6: bf00 nop - -080011a8 <__aeabi_fcmpgt>: - 80011a8: f84d ed08 str.w lr, [sp, #-8]! - 80011ac: f7ff ffc8 bl 8001140 <__aeabi_cfrcmple> - 80011b0: bf34 ite cc - 80011b2: 2001 movcc r0, #1 - 80011b4: 2000 movcs r0, #0 - 80011b6: f85d fb08 ldr.w pc, [sp], #8 - 80011ba: bf00 nop - -080011bc <__aeabi_f2iz>: - 80011bc: ea4f 0240 mov.w r2, r0, lsl #1 - 80011c0: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 - 80011c4: d30f bcc.n 80011e6 <__aeabi_f2iz+0x2a> - 80011c6: f04f 039e mov.w r3, #158 @ 0x9e - 80011ca: ebb3 6212 subs.w r2, r3, r2, lsr #24 - 80011ce: d90d bls.n 80011ec <__aeabi_f2iz+0x30> - 80011d0: ea4f 2300 mov.w r3, r0, lsl #8 - 80011d4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 - 80011d8: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 - 80011dc: fa23 f002 lsr.w r0, r3, r2 - 80011e0: bf18 it ne - 80011e2: 4240 negne r0, r0 - 80011e4: 4770 bx lr - 80011e6: f04f 0000 mov.w r0, #0 - 80011ea: 4770 bx lr - 80011ec: f112 0f61 cmn.w r2, #97 @ 0x61 - 80011f0: d101 bne.n 80011f6 <__aeabi_f2iz+0x3a> - 80011f2: 0242 lsls r2, r0, #9 - 80011f4: d105 bne.n 8001202 <__aeabi_f2iz+0x46> - 80011f6: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 - 80011fa: bf08 it eq - 80011fc: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 - 8001200: 4770 bx lr - 8001202: f04f 0000 mov.w r0, #0 - 8001206: 4770 bx lr - -08001208 <__aeabi_ldivmod>: - 8001208: b97b cbnz r3, 800122a <__aeabi_ldivmod+0x22> - 800120a: b972 cbnz r2, 800122a <__aeabi_ldivmod+0x22> - 800120c: 2900 cmp r1, #0 - 800120e: bfbe ittt lt - 8001210: 2000 movlt r0, #0 - 8001212: f04f 4100 movlt.w r1, #2147483648 @ 0x80000000 - 8001216: e006 blt.n 8001226 <__aeabi_ldivmod+0x1e> - 8001218: bf08 it eq - 800121a: 2800 cmpeq r0, #0 - 800121c: bf1c itt ne - 800121e: f06f 4100 mvnne.w r1, #2147483648 @ 0x80000000 - 8001222: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff - 8001226: f000 b9b3 b.w 8001590 <__aeabi_idiv0> - 800122a: f1ad 0c08 sub.w ip, sp, #8 - 800122e: e96d ce04 strd ip, lr, [sp, #-16]! - 8001232: 2900 cmp r1, #0 - 8001234: db09 blt.n 800124a <__aeabi_ldivmod+0x42> - 8001236: 2b00 cmp r3, #0 - 8001238: db1a blt.n 8001270 <__aeabi_ldivmod+0x68> - 800123a: f000 f84d bl 80012d8 <__udivmoddi4> - 800123e: f8dd e004 ldr.w lr, [sp, #4] - 8001242: e9dd 2302 ldrd r2, r3, [sp, #8] - 8001246: b004 add sp, #16 - 8001248: 4770 bx lr - 800124a: 4240 negs r0, r0 - 800124c: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 8001250: 2b00 cmp r3, #0 - 8001252: db1b blt.n 800128c <__aeabi_ldivmod+0x84> - 8001254: f000 f840 bl 80012d8 <__udivmoddi4> - 8001258: f8dd e004 ldr.w lr, [sp, #4] - 800125c: e9dd 2302 ldrd r2, r3, [sp, #8] - 8001260: b004 add sp, #16 - 8001262: 4240 negs r0, r0 - 8001264: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 8001268: 4252 negs r2, r2 - 800126a: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 800126e: 4770 bx lr - 8001270: 4252 negs r2, r2 - 8001272: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 8001276: f000 f82f bl 80012d8 <__udivmoddi4> - 800127a: f8dd e004 ldr.w lr, [sp, #4] - 800127e: e9dd 2302 ldrd r2, r3, [sp, #8] - 8001282: b004 add sp, #16 - 8001284: 4240 negs r0, r0 - 8001286: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 800128a: 4770 bx lr - 800128c: 4252 negs r2, r2 - 800128e: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 8001292: f000 f821 bl 80012d8 <__udivmoddi4> - 8001296: f8dd e004 ldr.w lr, [sp, #4] - 800129a: e9dd 2302 ldrd r2, r3, [sp, #8] - 800129e: b004 add sp, #16 - 80012a0: 4252 negs r2, r2 - 80012a2: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 80012a6: 4770 bx lr - -080012a8 <__aeabi_uldivmod>: - 80012a8: b953 cbnz r3, 80012c0 <__aeabi_uldivmod+0x18> - 80012aa: b94a cbnz r2, 80012c0 <__aeabi_uldivmod+0x18> - 80012ac: 2900 cmp r1, #0 - 80012ae: bf08 it eq - 80012b0: 2800 cmpeq r0, #0 - 80012b2: bf1c itt ne - 80012b4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff - 80012b8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff - 80012bc: f000 b968 b.w 8001590 <__aeabi_idiv0> - 80012c0: f1ad 0c08 sub.w ip, sp, #8 - 80012c4: e96d ce04 strd ip, lr, [sp, #-16]! - 80012c8: f000 f806 bl 80012d8 <__udivmoddi4> - 80012cc: f8dd e004 ldr.w lr, [sp, #4] - 80012d0: e9dd 2302 ldrd r2, r3, [sp, #8] - 80012d4: b004 add sp, #16 - 80012d6: 4770 bx lr - -080012d8 <__udivmoddi4>: - 80012d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 80012dc: 9d08 ldr r5, [sp, #32] - 80012de: 460c mov r4, r1 - 80012e0: 2b00 cmp r3, #0 - 80012e2: d14e bne.n 8001382 <__udivmoddi4+0xaa> - 80012e4: 4694 mov ip, r2 - 80012e6: 458c cmp ip, r1 - 80012e8: 4686 mov lr, r0 - 80012ea: fab2 f282 clz r2, r2 - 80012ee: d962 bls.n 80013b6 <__udivmoddi4+0xde> - 80012f0: b14a cbz r2, 8001306 <__udivmoddi4+0x2e> - 80012f2: f1c2 0320 rsb r3, r2, #32 - 80012f6: 4091 lsls r1, r2 - 80012f8: fa20 f303 lsr.w r3, r0, r3 - 80012fc: fa0c fc02 lsl.w ip, ip, r2 - 8001300: 4319 orrs r1, r3 - 8001302: fa00 fe02 lsl.w lr, r0, r2 - 8001306: ea4f 471c mov.w r7, ip, lsr #16 - 800130a: fbb1 f4f7 udiv r4, r1, r7 - 800130e: fb07 1114 mls r1, r7, r4, r1 - 8001312: fa1f f68c uxth.w r6, ip - 8001316: ea4f 431e mov.w r3, lr, lsr #16 - 800131a: ea43 4301 orr.w r3, r3, r1, lsl #16 - 800131e: fb04 f106 mul.w r1, r4, r6 - 8001322: 4299 cmp r1, r3 - 8001324: d90a bls.n 800133c <__udivmoddi4+0x64> - 8001326: eb1c 0303 adds.w r3, ip, r3 - 800132a: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff - 800132e: f080 8110 bcs.w 8001552 <__udivmoddi4+0x27a> - 8001332: 4299 cmp r1, r3 - 8001334: f240 810d bls.w 8001552 <__udivmoddi4+0x27a> - 8001338: 3c02 subs r4, #2 - 800133a: 4463 add r3, ip - 800133c: 1a59 subs r1, r3, r1 - 800133e: fbb1 f0f7 udiv r0, r1, r7 - 8001342: fb07 1110 mls r1, r7, r0, r1 - 8001346: fb00 f606 mul.w r6, r0, r6 - 800134a: fa1f f38e uxth.w r3, lr - 800134e: ea43 4301 orr.w r3, r3, r1, lsl #16 - 8001352: 429e cmp r6, r3 - 8001354: d90a bls.n 800136c <__udivmoddi4+0x94> - 8001356: eb1c 0303 adds.w r3, ip, r3 - 800135a: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff - 800135e: f080 80fa bcs.w 8001556 <__udivmoddi4+0x27e> - 8001362: 429e cmp r6, r3 - 8001364: f240 80f7 bls.w 8001556 <__udivmoddi4+0x27e> - 8001368: 4463 add r3, ip - 800136a: 3802 subs r0, #2 - 800136c: 2100 movs r1, #0 - 800136e: 1b9b subs r3, r3, r6 - 8001370: ea40 4004 orr.w r0, r0, r4, lsl #16 - 8001374: b11d cbz r5, 800137e <__udivmoddi4+0xa6> - 8001376: 40d3 lsrs r3, r2 - 8001378: 2200 movs r2, #0 - 800137a: e9c5 3200 strd r3, r2, [r5] - 800137e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8001382: 428b cmp r3, r1 - 8001384: d905 bls.n 8001392 <__udivmoddi4+0xba> - 8001386: b10d cbz r5, 800138c <__udivmoddi4+0xb4> - 8001388: e9c5 0100 strd r0, r1, [r5] - 800138c: 2100 movs r1, #0 - 800138e: 4608 mov r0, r1 - 8001390: e7f5 b.n 800137e <__udivmoddi4+0xa6> - 8001392: fab3 f183 clz r1, r3 - 8001396: 2900 cmp r1, #0 - 8001398: d146 bne.n 8001428 <__udivmoddi4+0x150> - 800139a: 42a3 cmp r3, r4 - 800139c: d302 bcc.n 80013a4 <__udivmoddi4+0xcc> - 800139e: 4290 cmp r0, r2 - 80013a0: f0c0 80ee bcc.w 8001580 <__udivmoddi4+0x2a8> - 80013a4: 1a86 subs r6, r0, r2 - 80013a6: eb64 0303 sbc.w r3, r4, r3 - 80013aa: 2001 movs r0, #1 - 80013ac: 2d00 cmp r5, #0 - 80013ae: d0e6 beq.n 800137e <__udivmoddi4+0xa6> - 80013b0: e9c5 6300 strd r6, r3, [r5] - 80013b4: e7e3 b.n 800137e <__udivmoddi4+0xa6> - 80013b6: 2a00 cmp r2, #0 - 80013b8: f040 808f bne.w 80014da <__udivmoddi4+0x202> - 80013bc: eba1 040c sub.w r4, r1, ip - 80013c0: 2101 movs r1, #1 - 80013c2: ea4f 481c mov.w r8, ip, lsr #16 - 80013c6: fa1f f78c uxth.w r7, ip - 80013ca: fbb4 f6f8 udiv r6, r4, r8 - 80013ce: fb08 4416 mls r4, r8, r6, r4 - 80013d2: fb07 f006 mul.w r0, r7, r6 - 80013d6: ea4f 431e mov.w r3, lr, lsr #16 - 80013da: ea43 4304 orr.w r3, r3, r4, lsl #16 - 80013de: 4298 cmp r0, r3 - 80013e0: d908 bls.n 80013f4 <__udivmoddi4+0x11c> - 80013e2: eb1c 0303 adds.w r3, ip, r3 - 80013e6: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff - 80013ea: d202 bcs.n 80013f2 <__udivmoddi4+0x11a> - 80013ec: 4298 cmp r0, r3 - 80013ee: f200 80cb bhi.w 8001588 <__udivmoddi4+0x2b0> - 80013f2: 4626 mov r6, r4 - 80013f4: 1a1c subs r4, r3, r0 - 80013f6: fbb4 f0f8 udiv r0, r4, r8 - 80013fa: fb08 4410 mls r4, r8, r0, r4 - 80013fe: fb00 f707 mul.w r7, r0, r7 - 8001402: fa1f f38e uxth.w r3, lr - 8001406: ea43 4304 orr.w r3, r3, r4, lsl #16 - 800140a: 429f cmp r7, r3 - 800140c: d908 bls.n 8001420 <__udivmoddi4+0x148> - 800140e: eb1c 0303 adds.w r3, ip, r3 - 8001412: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff - 8001416: d202 bcs.n 800141e <__udivmoddi4+0x146> - 8001418: 429f cmp r7, r3 - 800141a: f200 80ae bhi.w 800157a <__udivmoddi4+0x2a2> - 800141e: 4620 mov r0, r4 - 8001420: 1bdb subs r3, r3, r7 - 8001422: ea40 4006 orr.w r0, r0, r6, lsl #16 - 8001426: e7a5 b.n 8001374 <__udivmoddi4+0x9c> - 8001428: f1c1 0720 rsb r7, r1, #32 - 800142c: 408b lsls r3, r1 - 800142e: fa22 fc07 lsr.w ip, r2, r7 - 8001432: ea4c 0c03 orr.w ip, ip, r3 - 8001436: fa24 f607 lsr.w r6, r4, r7 - 800143a: ea4f 491c mov.w r9, ip, lsr #16 - 800143e: fbb6 f8f9 udiv r8, r6, r9 - 8001442: fa1f fe8c uxth.w lr, ip - 8001446: fb09 6618 mls r6, r9, r8, r6 - 800144a: fa20 f307 lsr.w r3, r0, r7 - 800144e: 408c lsls r4, r1 - 8001450: fa00 fa01 lsl.w sl, r0, r1 - 8001454: fb08 f00e mul.w r0, r8, lr - 8001458: 431c orrs r4, r3 - 800145a: 0c23 lsrs r3, r4, #16 - 800145c: ea43 4306 orr.w r3, r3, r6, lsl #16 - 8001460: 4298 cmp r0, r3 - 8001462: fa02 f201 lsl.w r2, r2, r1 - 8001466: d90a bls.n 800147e <__udivmoddi4+0x1a6> - 8001468: eb1c 0303 adds.w r3, ip, r3 - 800146c: f108 36ff add.w r6, r8, #4294967295 @ 0xffffffff - 8001470: f080 8081 bcs.w 8001576 <__udivmoddi4+0x29e> - 8001474: 4298 cmp r0, r3 - 8001476: d97e bls.n 8001576 <__udivmoddi4+0x29e> - 8001478: f1a8 0802 sub.w r8, r8, #2 - 800147c: 4463 add r3, ip - 800147e: 1a1e subs r6, r3, r0 - 8001480: fbb6 f3f9 udiv r3, r6, r9 - 8001484: fb09 6613 mls r6, r9, r3, r6 - 8001488: fb03 fe0e mul.w lr, r3, lr - 800148c: b2a4 uxth r4, r4 - 800148e: ea44 4406 orr.w r4, r4, r6, lsl #16 - 8001492: 45a6 cmp lr, r4 - 8001494: d908 bls.n 80014a8 <__udivmoddi4+0x1d0> - 8001496: eb1c 0404 adds.w r4, ip, r4 - 800149a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff - 800149e: d266 bcs.n 800156e <__udivmoddi4+0x296> - 80014a0: 45a6 cmp lr, r4 - 80014a2: d964 bls.n 800156e <__udivmoddi4+0x296> - 80014a4: 3b02 subs r3, #2 - 80014a6: 4464 add r4, ip - 80014a8: ea43 4008 orr.w r0, r3, r8, lsl #16 - 80014ac: fba0 8302 umull r8, r3, r0, r2 - 80014b0: eba4 040e sub.w r4, r4, lr - 80014b4: 429c cmp r4, r3 - 80014b6: 46c6 mov lr, r8 - 80014b8: 461e mov r6, r3 - 80014ba: d350 bcc.n 800155e <__udivmoddi4+0x286> - 80014bc: d04d beq.n 800155a <__udivmoddi4+0x282> - 80014be: b155 cbz r5, 80014d6 <__udivmoddi4+0x1fe> - 80014c0: ebba 030e subs.w r3, sl, lr - 80014c4: eb64 0406 sbc.w r4, r4, r6 - 80014c8: fa04 f707 lsl.w r7, r4, r7 - 80014cc: 40cb lsrs r3, r1 - 80014ce: 431f orrs r7, r3 - 80014d0: 40cc lsrs r4, r1 - 80014d2: e9c5 7400 strd r7, r4, [r5] - 80014d6: 2100 movs r1, #0 - 80014d8: e751 b.n 800137e <__udivmoddi4+0xa6> - 80014da: fa0c fc02 lsl.w ip, ip, r2 - 80014de: f1c2 0320 rsb r3, r2, #32 - 80014e2: 40d9 lsrs r1, r3 - 80014e4: ea4f 481c mov.w r8, ip, lsr #16 - 80014e8: fa20 f303 lsr.w r3, r0, r3 - 80014ec: fa00 fe02 lsl.w lr, r0, r2 - 80014f0: fbb1 f0f8 udiv r0, r1, r8 - 80014f4: fb08 1110 mls r1, r8, r0, r1 - 80014f8: 4094 lsls r4, r2 - 80014fa: 431c orrs r4, r3 - 80014fc: fa1f f78c uxth.w r7, ip - 8001500: 0c23 lsrs r3, r4, #16 - 8001502: ea43 4301 orr.w r3, r3, r1, lsl #16 - 8001506: fb00 f107 mul.w r1, r0, r7 - 800150a: 4299 cmp r1, r3 - 800150c: d908 bls.n 8001520 <__udivmoddi4+0x248> - 800150e: eb1c 0303 adds.w r3, ip, r3 - 8001512: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff - 8001516: d22c bcs.n 8001572 <__udivmoddi4+0x29a> - 8001518: 4299 cmp r1, r3 - 800151a: d92a bls.n 8001572 <__udivmoddi4+0x29a> - 800151c: 3802 subs r0, #2 - 800151e: 4463 add r3, ip - 8001520: 1a5b subs r3, r3, r1 - 8001522: fbb3 f1f8 udiv r1, r3, r8 - 8001526: fb08 3311 mls r3, r8, r1, r3 - 800152a: b2a4 uxth r4, r4 - 800152c: ea44 4403 orr.w r4, r4, r3, lsl #16 - 8001530: fb01 f307 mul.w r3, r1, r7 - 8001534: 42a3 cmp r3, r4 - 8001536: d908 bls.n 800154a <__udivmoddi4+0x272> - 8001538: eb1c 0404 adds.w r4, ip, r4 - 800153c: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff - 8001540: d213 bcs.n 800156a <__udivmoddi4+0x292> - 8001542: 42a3 cmp r3, r4 - 8001544: d911 bls.n 800156a <__udivmoddi4+0x292> - 8001546: 3902 subs r1, #2 - 8001548: 4464 add r4, ip - 800154a: 1ae4 subs r4, r4, r3 - 800154c: ea41 4100 orr.w r1, r1, r0, lsl #16 - 8001550: e73b b.n 80013ca <__udivmoddi4+0xf2> - 8001552: 4604 mov r4, r0 - 8001554: e6f2 b.n 800133c <__udivmoddi4+0x64> - 8001556: 4608 mov r0, r1 - 8001558: e708 b.n 800136c <__udivmoddi4+0x94> - 800155a: 45c2 cmp sl, r8 - 800155c: d2af bcs.n 80014be <__udivmoddi4+0x1e6> - 800155e: ebb8 0e02 subs.w lr, r8, r2 - 8001562: eb63 060c sbc.w r6, r3, ip - 8001566: 3801 subs r0, #1 - 8001568: e7a9 b.n 80014be <__udivmoddi4+0x1e6> - 800156a: 4631 mov r1, r6 - 800156c: e7ed b.n 800154a <__udivmoddi4+0x272> - 800156e: 4603 mov r3, r0 - 8001570: e79a b.n 80014a8 <__udivmoddi4+0x1d0> - 8001572: 4630 mov r0, r6 - 8001574: e7d4 b.n 8001520 <__udivmoddi4+0x248> - 8001576: 46b0 mov r8, r6 - 8001578: e781 b.n 800147e <__udivmoddi4+0x1a6> - 800157a: 4463 add r3, ip - 800157c: 3802 subs r0, #2 - 800157e: e74f b.n 8001420 <__udivmoddi4+0x148> - 8001580: 4606 mov r6, r0 - 8001582: 4623 mov r3, r4 - 8001584: 4608 mov r0, r1 - 8001586: e711 b.n 80013ac <__udivmoddi4+0xd4> - 8001588: 3e02 subs r6, #2 - 800158a: 4463 add r3, ip - 800158c: e732 b.n 80013f4 <__udivmoddi4+0x11c> - 800158e: bf00 nop - -08001590 <__aeabi_idiv0>: - 8001590: 4770 bx lr - 8001592: bf00 nop - -08001594 : - -ADC_HandleTypeDef hadc1; - -/* ADC1 init function */ -void MX_ADC1_Init(void) -{ - 8001594: b580 push {r7, lr} - 8001596: b084 sub sp, #16 - 8001598: af00 add r7, sp, #0 - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - 800159a: 1d3b adds r3, r7, #4 - 800159c: 2200 movs r2, #0 - 800159e: 601a str r2, [r3, #0] - 80015a0: 605a str r2, [r3, #4] - 80015a2: 609a str r2, [r3, #8] - - /* USER CODE END ADC1_Init 1 */ - - /** Common config - */ - hadc1.Instance = ADC1; - 80015a4: 4b18 ldr r3, [pc, #96] @ (8001608 ) - 80015a6: 4a19 ldr r2, [pc, #100] @ (800160c ) - 80015a8: 601a str r2, [r3, #0] - hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; - 80015aa: 4b17 ldr r3, [pc, #92] @ (8001608 ) - 80015ac: 2200 movs r2, #0 - 80015ae: 609a str r2, [r3, #8] - hadc1.Init.ContinuousConvMode = DISABLE; - 80015b0: 4b15 ldr r3, [pc, #84] @ (8001608 ) - 80015b2: 2200 movs r2, #0 - 80015b4: 731a strb r2, [r3, #12] - hadc1.Init.DiscontinuousConvMode = DISABLE; - 80015b6: 4b14 ldr r3, [pc, #80] @ (8001608 ) - 80015b8: 2200 movs r2, #0 - 80015ba: 751a strb r2, [r3, #20] - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - 80015bc: 4b12 ldr r3, [pc, #72] @ (8001608 ) - 80015be: f44f 2260 mov.w r2, #917504 @ 0xe0000 - 80015c2: 61da str r2, [r3, #28] - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 80015c4: 4b10 ldr r3, [pc, #64] @ (8001608 ) - 80015c6: 2200 movs r2, #0 - 80015c8: 605a str r2, [r3, #4] - hadc1.Init.NbrOfConversion = 1; - 80015ca: 4b0f ldr r3, [pc, #60] @ (8001608 ) - 80015cc: 2201 movs r2, #1 - 80015ce: 611a str r2, [r3, #16] - if (HAL_ADC_Init(&hadc1) != HAL_OK) - 80015d0: 480d ldr r0, [pc, #52] @ (8001608 ) - 80015d2: f004 f95d bl 8005890 - 80015d6: 4603 mov r3, r0 - 80015d8: 2b00 cmp r3, #0 - 80015da: d001 beq.n 80015e0 - { - Error_Handler(); - 80015dc: f003 fd00 bl 8004fe0 - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_8; - 80015e0: 2308 movs r3, #8 - 80015e2: 607b str r3, [r7, #4] - sConfig.Rank = ADC_REGULAR_RANK_1; - 80015e4: 2301 movs r3, #1 - 80015e6: 60bb str r3, [r7, #8] - sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; - 80015e8: 2300 movs r3, #0 - 80015ea: 60fb str r3, [r7, #12] - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80015ec: 1d3b adds r3, r7, #4 - 80015ee: 4619 mov r1, r3 - 80015f0: 4805 ldr r0, [pc, #20] @ (8001608 ) - 80015f2: f004 fc11 bl 8005e18 - 80015f6: 4603 mov r3, r0 - 80015f8: 2b00 cmp r3, #0 - 80015fa: d001 beq.n 8001600 - { - Error_Handler(); - 80015fc: f003 fcf0 bl 8004fe0 - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - 8001600: bf00 nop - 8001602: 3710 adds r7, #16 - 8001604: 46bd mov sp, r7 - 8001606: bd80 pop {r7, pc} - 8001608: 20000258 .word 0x20000258 - 800160c: 40012400 .word 0x40012400 - -08001610 : - -void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) -{ - 8001610: b580 push {r7, lr} - 8001612: b08a sub sp, #40 @ 0x28 - 8001614: af00 add r7, sp, #0 - 8001616: 6078 str r0, [r7, #4] - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001618: f107 0318 add.w r3, r7, #24 - 800161c: 2200 movs r2, #0 - 800161e: 601a str r2, [r3, #0] - 8001620: 605a str r2, [r3, #4] - 8001622: 609a str r2, [r3, #8] - 8001624: 60da str r2, [r3, #12] - if(adcHandle->Instance==ADC1) - 8001626: 687b ldr r3, [r7, #4] - 8001628: 681b ldr r3, [r3, #0] - 800162a: 4a1f ldr r2, [pc, #124] @ (80016a8 ) - 800162c: 4293 cmp r3, r2 - 800162e: d137 bne.n 80016a0 - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* ADC1 clock enable */ - __HAL_RCC_ADC1_CLK_ENABLE(); - 8001630: 4b1e ldr r3, [pc, #120] @ (80016ac ) - 8001632: 699b ldr r3, [r3, #24] - 8001634: 4a1d ldr r2, [pc, #116] @ (80016ac ) - 8001636: f443 7300 orr.w r3, r3, #512 @ 0x200 - 800163a: 6193 str r3, [r2, #24] - 800163c: 4b1b ldr r3, [pc, #108] @ (80016ac ) - 800163e: 699b ldr r3, [r3, #24] - 8001640: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001644: 617b str r3, [r7, #20] - 8001646: 697b ldr r3, [r7, #20] - - __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001648: 4b18 ldr r3, [pc, #96] @ (80016ac ) - 800164a: 699b ldr r3, [r3, #24] - 800164c: 4a17 ldr r2, [pc, #92] @ (80016ac ) - 800164e: f043 0304 orr.w r3, r3, #4 - 8001652: 6193 str r3, [r2, #24] - 8001654: 4b15 ldr r3, [pc, #84] @ (80016ac ) - 8001656: 699b ldr r3, [r3, #24] - 8001658: f003 0304 and.w r3, r3, #4 - 800165c: 613b str r3, [r7, #16] - 800165e: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 8001660: 4b12 ldr r3, [pc, #72] @ (80016ac ) - 8001662: 699b ldr r3, [r3, #24] - 8001664: 4a11 ldr r2, [pc, #68] @ (80016ac ) - 8001666: f043 0308 orr.w r3, r3, #8 - 800166a: 6193 str r3, [r2, #24] - 800166c: 4b0f ldr r3, [pc, #60] @ (80016ac ) - 800166e: 699b ldr r3, [r3, #24] - 8001670: f003 0308 and.w r3, r3, #8 - 8001674: 60fb str r3, [r7, #12] - 8001676: 68fb ldr r3, [r7, #12] - /**ADC1 GPIO Configuration - PA6 ------> ADC1_IN6 - PB0 ------> ADC1_IN8 - PB1 ------> ADC1_IN9 - */ - GPIO_InitStruct.Pin = ADC_CC1_Pin; - 8001678: 2340 movs r3, #64 @ 0x40 - 800167a: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 800167c: 2303 movs r3, #3 - 800167e: 61fb str r3, [r7, #28] - HAL_GPIO_Init(ADC_CC1_GPIO_Port, &GPIO_InitStruct); - 8001680: f107 0318 add.w r3, r7, #24 - 8001684: 4619 mov r1, r3 - 8001686: 480a ldr r0, [pc, #40] @ (80016b0 ) - 8001688: f005 ff02 bl 8007490 - - GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; - 800168c: 2303 movs r3, #3 - 800168e: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 8001690: 2303 movs r3, #3 - 8001692: 61fb str r3, [r7, #28] - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8001694: f107 0318 add.w r3, r7, #24 - 8001698: 4619 mov r1, r3 - 800169a: 4806 ldr r0, [pc, #24] @ (80016b4 ) - 800169c: f005 fef8 bl 8007490 - - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } -} - 80016a0: bf00 nop - 80016a2: 3728 adds r7, #40 @ 0x28 - 80016a4: 46bd mov sp, r7 - 80016a6: bd80 pop {r7, pc} - 80016a8: 40012400 .word 0x40012400 - 80016ac: 40021000 .word 0x40021000 - 80016b0: 40010800 .word 0x40010800 - 80016b4: 40010c00 .word 0x40010c00 - -080016b8 : - -//TODO: -//TEMP READ -//GBT_TEMP_SENSORS - -void RELAY_Write(relay_t num, uint8_t state){ - 80016b8: b580 push {r7, lr} - 80016ba: b082 sub sp, #8 - 80016bc: af00 add r7, sp, #0 - 80016be: 4603 mov r3, r0 - 80016c0: 460a mov r2, r1 - 80016c2: 71fb strb r3, [r7, #7] - 80016c4: 4613 mov r3, r2 - 80016c6: 71bb strb r3, [r7, #6] - if(num==RELAY_AUX)HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, state); - 80016c8: 79fb ldrb r3, [r7, #7] - 80016ca: 2b00 cmp r3, #0 - 80016cc: d105 bne.n 80016da - 80016ce: 79bb ldrb r3, [r7, #6] - 80016d0: 461a mov r2, r3 - 80016d2: 2110 movs r1, #16 - 80016d4: 4808 ldr r0, [pc, #32] @ (80016f8 ) - 80016d6: f006 f876 bl 80077c6 - if(num==RELAY_CC)HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); - 80016da: 79fb ldrb r3, [r7, #7] - 80016dc: 2b01 cmp r3, #1 - 80016de: d106 bne.n 80016ee - 80016e0: 79bb ldrb r3, [r7, #6] - 80016e2: 461a mov r2, r3 - 80016e4: f44f 4100 mov.w r1, #32768 @ 0x8000 - 80016e8: 4804 ldr r0, [pc, #16] @ (80016fc ) - 80016ea: f006 f86c bl 80077c6 - -} - 80016ee: bf00 nop - 80016f0: 3708 adds r7, #8 - 80016f2: 46bd mov sp, r7 - 80016f4: bd80 pop {r7, pc} - 80016f6: bf00 nop - 80016f8: 40010c00 .word 0x40010c00 - 80016fc: 40011800 .word 0x40011800 - -08001700 : -// -// HAL_ADC_Stop(&hadc1); // stop adc - return 0; -} - -void Init_Peripheral(){ - 8001700: b580 push {r7, lr} - 8001702: af00 add r7, sp, #0 - HAL_ADCEx_Calibration_Start(&hadc1); - 8001704: 4806 ldr r0, [pc, #24] @ (8001720 ) - 8001706: f004 fd1b bl 8006140 - RELAY_Write(RELAY_AUX, 0); - 800170a: 2100 movs r1, #0 - 800170c: 2000 movs r0, #0 - 800170e: f7ff ffd3 bl 80016b8 - RELAY_Write(RELAY_CC, 1); - 8001712: 2101 movs r1, #1 - 8001714: 2001 movs r0, #1 - 8001716: f7ff ffcf bl 80016b8 - -} - 800171a: bf00 nop - 800171c: bd80 pop {r7, pc} - 800171e: bf00 nop - 8001720: 20000258 .word 0x20000258 - -08001724 : - -float pt1000_to_temperature(float resistance) { - 8001724: b590 push {r4, r7, lr} - 8001726: b087 sub sp, #28 - 8001728: af00 add r7, sp, #0 - 800172a: 6078 str r0, [r7, #4] - // Константы для PT1000 - const float R0 = 1000.0; // Сопротивление при 0 °C - 800172c: 4b0c ldr r3, [pc, #48] @ (8001760 ) - 800172e: 617b str r3, [r7, #20] - const float C_A = 3.9083E-3f; - 8001730: 4b0c ldr r3, [pc, #48] @ (8001764 ) - 8001732: 613b str r3, [r7, #16] -// const float B = -5.775e-07; // Второй коэффициент (°C^-2) -// -// // Расчет температуры по формуле -// float temperature = -A / (B - (R0 / resistance - 1) * A); - - float temperature = (resistance-R0) / ( R0 * C_A); - 8001734: 6979 ldr r1, [r7, #20] - 8001736: 6878 ldr r0, [r7, #4] - 8001738: f7ff fa70 bl 8000c1c <__aeabi_fsub> - 800173c: 4603 mov r3, r0 - 800173e: 461c mov r4, r3 - 8001740: 6939 ldr r1, [r7, #16] - 8001742: 6978 ldr r0, [r7, #20] - 8001744: f7ff fb74 bl 8000e30 <__aeabi_fmul> - 8001748: 4603 mov r3, r0 - 800174a: 4619 mov r1, r3 - 800174c: 4620 mov r0, r4 - 800174e: f7ff fc23 bl 8000f98 <__aeabi_fdiv> - 8001752: 4603 mov r3, r0 - 8001754: 60fb str r3, [r7, #12] - - return temperature; - 8001756: 68fb ldr r3, [r7, #12] -} - 8001758: 4618 mov r0, r3 - 800175a: 371c adds r7, #28 - 800175c: 46bd mov sp, r7 - 800175e: bd90 pop {r4, r7, pc} - 8001760: 447a0000 .word 0x447a0000 - 8001764: 3b801132 .word 0x3b801132 - -08001768 : - - -float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { - 8001768: b5b0 push {r4, r5, r7, lr} - 800176a: b086 sub sp, #24 - 800176c: af00 add r7, sp, #0 - 800176e: 60f8 str r0, [r7, #12] - 8001770: 60b9 str r1, [r7, #8] - 8001772: 607a str r2, [r7, #4] - 8001774: 603b str r3, [r7, #0] - // Преобразуем значение АЦП в выходное напряжение - float Vout = (adc_value / 4095.0) * Vref; - 8001776: 68f8 ldr r0, [r7, #12] - 8001778: f7fe feba bl 80004f0 <__aeabi_i2d> - 800177c: a31c add r3, pc, #112 @ (adr r3, 80017f0 ) - 800177e: e9d3 2300 ldrd r2, r3, [r3] - 8001782: f7ff f849 bl 8000818 <__aeabi_ddiv> - 8001786: 4602 mov r2, r0 - 8001788: 460b mov r3, r1 - 800178a: 4614 mov r4, r2 - 800178c: 461d mov r5, r3 - 800178e: 68b8 ldr r0, [r7, #8] - 8001790: f7fe fec0 bl 8000514 <__aeabi_f2d> - 8001794: 4602 mov r2, r0 - 8001796: 460b mov r3, r1 - 8001798: 4620 mov r0, r4 - 800179a: 4629 mov r1, r5 - 800179c: f7fe ff12 bl 80005c4 <__aeabi_dmul> - 80017a0: 4602 mov r2, r0 - 80017a2: 460b mov r3, r1 - 80017a4: 4610 mov r0, r2 - 80017a6: 4619 mov r1, r3 - 80017a8: f7ff f9e4 bl 8000b74 <__aeabi_d2f> - 80017ac: 4603 mov r3, r0 - 80017ae: 617b str r3, [r7, #20] - - // Проверяем, чтобы Vout не было равно Vin - if (Vout >= Vin) { - 80017b0: 6879 ldr r1, [r7, #4] - 80017b2: 6978 ldr r0, [r7, #20] - 80017b4: f7ff fcee bl 8001194 <__aeabi_fcmpge> - 80017b8: 4603 mov r3, r0 - 80017ba: 2b00 cmp r3, #0 - 80017bc: d001 beq.n 80017c2 - return -1; // Ошибка: Vout не может быть больше или равно Vin - 80017be: 4b0e ldr r3, [pc, #56] @ (80017f8 ) - 80017c0: e010 b.n 80017e4 - } - - // Вычисляем сопротивление термистора - float R_NTC = R * (Vout / (Vin - Vout)); - 80017c2: 6979 ldr r1, [r7, #20] - 80017c4: 6878 ldr r0, [r7, #4] - 80017c6: f7ff fa29 bl 8000c1c <__aeabi_fsub> - 80017ca: 4603 mov r3, r0 - 80017cc: 4619 mov r1, r3 - 80017ce: 6978 ldr r0, [r7, #20] - 80017d0: f7ff fbe2 bl 8000f98 <__aeabi_fdiv> - 80017d4: 4603 mov r3, r0 - 80017d6: 4619 mov r1, r3 - 80017d8: 6838 ldr r0, [r7, #0] - 80017da: f7ff fb29 bl 8000e30 <__aeabi_fmul> - 80017de: 4603 mov r3, r0 - 80017e0: 613b str r3, [r7, #16] - - return R_NTC; - 80017e2: 693b ldr r3, [r7, #16] -} - 80017e4: 4618 mov r0, r3 - 80017e6: 3718 adds r7, #24 - 80017e8: 46bd mov sp, r7 - 80017ea: bdb0 pop {r4, r5, r7, pc} - 80017ec: f3af 8000 nop.w - 80017f0: 00000000 .word 0x00000000 - 80017f4: 40affe00 .word 0x40affe00 - 80017f8: bf800000 .word 0xbf800000 - -080017fc : - -int16_t GBT_ReadTemp(uint8_t ch){ - 80017fc: b580 push {r7, lr} - 80017fe: b088 sub sp, #32 - 8001800: af00 add r7, sp, #0 - 8001802: 4603 mov r3, r0 - 8001804: 71fb strb r3, [r7, #7] - //TODO - if(ch)ADC_Select_Channel(ADC_CHANNEL_8); - 8001806: 79fb ldrb r3, [r7, #7] - 8001808: 2b00 cmp r3, #0 - 800180a: d003 beq.n 8001814 - 800180c: 2008 movs r0, #8 - 800180e: f000 f83b bl 8001888 - 8001812: e002 b.n 800181a - else ADC_Select_Channel(ADC_CHANNEL_9); - 8001814: 2009 movs r0, #9 - 8001816: f000 f837 bl 8001888 - // Начало конверсии - HAL_ADC_Start(&hadc1); - 800181a: 4817 ldr r0, [pc, #92] @ (8001878 ) - 800181c: f004 f910 bl 8005a40 - - - // Ожидание окончания конверсии - HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); - 8001820: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff - 8001824: 4814 ldr r0, [pc, #80] @ (8001878 ) - 8001826: f004 f9e5 bl 8005bf4 - - // Получение значения - uint32_t adcValue = HAL_ADC_GetValue(&hadc1); - 800182a: 4813 ldr r0, [pc, #76] @ (8001878 ) - 800182c: f004 fae8 bl 8005e00 - 8001830: 61f8 str r0, [r7, #28] - - // Остановка АЦП (по желанию) - HAL_ADC_Stop(&hadc1); - 8001832: 4811 ldr r0, [pc, #68] @ (8001878 ) - 8001834: f004 f9b2 bl 8005b9c - - if(adcValue>4000) return 20; //Термодатчик не подключен - 8001838: 69fb ldr r3, [r7, #28] - 800183a: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 - 800183e: d901 bls.n 8001844 - 8001840: 2314 movs r3, #20 - 8001842: e015 b.n 8001870 - -// int adc_value = 2048; // Пример значения АЦП - float Vref = 3.3; // Напряжение опорное - 8001844: 4b0d ldr r3, [pc, #52] @ (800187c ) - 8001846: 61bb str r3, [r7, #24] - float Vin = 5.0; // Входное напряжение - 8001848: 4b0d ldr r3, [pc, #52] @ (8001880 ) - 800184a: 617b str r3, [r7, #20] - float R = 1000; // Сопротивление резистора в Омах - 800184c: 4b0d ldr r3, [pc, #52] @ (8001884 ) - 800184e: 613b str r3, [r7, #16] - - float temp = pt1000_to_temperature(calculate_NTC_resistance(adcValue, Vref, Vin, R)); - 8001850: 69f8 ldr r0, [r7, #28] - 8001852: 693b ldr r3, [r7, #16] - 8001854: 697a ldr r2, [r7, #20] - 8001856: 69b9 ldr r1, [r7, #24] - 8001858: f7ff ff86 bl 8001768 - 800185c: 4603 mov r3, r0 - 800185e: 4618 mov r0, r3 - 8001860: f7ff ff60 bl 8001724 - 8001864: 60f8 str r0, [r7, #12] - - - - return (int16_t)temp; - 8001866: 68f8 ldr r0, [r7, #12] - 8001868: f7ff fca8 bl 80011bc <__aeabi_f2iz> - 800186c: 4603 mov r3, r0 - 800186e: b21b sxth r3, r3 - -} - 8001870: 4618 mov r0, r3 - 8001872: 3720 adds r7, #32 - 8001874: 46bd mov sp, r7 - 8001876: bd80 pop {r7, pc} - 8001878: 20000258 .word 0x20000258 - 800187c: 40533333 .word 0x40533333 - 8001880: 40a00000 .word 0x40a00000 - 8001884: 447a0000 .word 0x447a0000 - -08001888 : - - - - -void ADC_Select_Channel(uint32_t ch) { - 8001888: b580 push {r7, lr} - 800188a: b086 sub sp, #24 - 800188c: af00 add r7, sp, #0 - 800188e: 6078 str r0, [r7, #4] - ADC_ChannelConfTypeDef conf = { - 8001890: 687b ldr r3, [r7, #4] - 8001892: 60fb str r3, [r7, #12] - 8001894: 2301 movs r3, #1 - 8001896: 613b str r3, [r7, #16] - 8001898: 2303 movs r3, #3 - 800189a: 617b str r3, [r7, #20] - .Channel = ch, - .Rank = 1, - .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, - }; - if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { - 800189c: f107 030c add.w r3, r7, #12 - 80018a0: 4619 mov r1, r3 - 80018a2: 4806 ldr r0, [pc, #24] @ (80018bc ) - 80018a4: f004 fab8 bl 8005e18 - 80018a8: 4603 mov r3, r0 - 80018aa: 2b00 cmp r3, #0 - 80018ac: d001 beq.n 80018b2 - Error_Handler(); - 80018ae: f003 fb97 bl 8004fe0 - } -} - 80018b2: bf00 nop - 80018b4: 3718 adds r7, #24 - 80018b6: 46bd mov sp, r7 - 80018b8: bd80 pop {r7, pc} - 80018ba: bf00 nop - 80018bc: 20000258 .word 0x20000258 - -080018c0 : - -uint8_t SW_GetAddr(){ - 80018c0: b580 push {r7, lr} - 80018c2: af00 add r7, sp, #0 - if(!HAL_GPIO_ReadPin(ADDR_0_GPIO_Port, ADDR_0_Pin)){ - 80018c4: f44f 6180 mov.w r1, #1024 @ 0x400 - 80018c8: 480f ldr r0, [pc, #60] @ (8001908 ) - 80018ca: f005 ff65 bl 8007798 - 80018ce: 4603 mov r3, r0 - 80018d0: 2b00 cmp r3, #0 - 80018d2: d10b bne.n 80018ec - if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ - 80018d4: f44f 6100 mov.w r1, #2048 @ 0x800 - 80018d8: 480b ldr r0, [pc, #44] @ (8001908 ) - 80018da: f005 ff5d bl 8007798 - 80018de: 4603 mov r3, r0 - 80018e0: 2b00 cmp r3, #0 - 80018e2: d101 bne.n 80018e8 - return 0x23; - 80018e4: 2323 movs r3, #35 @ 0x23 - 80018e6: e00c b.n 8001902 - }else{ - return 0x21; - 80018e8: 2321 movs r3, #33 @ 0x21 - 80018ea: e00a b.n 8001902 - } - - }else{ - if(!HAL_GPIO_ReadPin(ADDR_1_GPIO_Port, ADDR_1_Pin)){ - 80018ec: f44f 6100 mov.w r1, #2048 @ 0x800 - 80018f0: 4805 ldr r0, [pc, #20] @ (8001908 ) - 80018f2: f005 ff51 bl 8007798 - 80018f6: 4603 mov r3, r0 - 80018f8: 2b00 cmp r3, #0 - 80018fa: d101 bne.n 8001900 - return 0x22; - 80018fc: 2322 movs r3, #34 @ 0x22 - 80018fe: e000 b.n 8001902 - }else{ - return 0x20; - 8001900: 2320 movs r3, #32 - } - - } -} - 8001902: 4618 mov r0, r3 - 8001904: bd80 pop {r7, pc} - 8001906: bf00 nop - 8001908: 40011800 .word 0x40011800 - -0800190c : -CAN_HandleTypeDef hcan1; -CAN_HandleTypeDef hcan2; - -/* CAN1 init function */ -void MX_CAN1_Init(void) -{ - 800190c: b580 push {r7, lr} - 800190e: af00 add r7, sp, #0 - /* USER CODE END CAN1_Init 0 */ - - /* USER CODE BEGIN CAN1_Init 1 */ - - /* USER CODE END CAN1_Init 1 */ - hcan1.Instance = CAN1; - 8001910: 4b17 ldr r3, [pc, #92] @ (8001970 ) - 8001912: 4a18 ldr r2, [pc, #96] @ (8001974 ) - 8001914: 601a str r2, [r3, #0] - hcan1.Init.Prescaler = 8; - 8001916: 4b16 ldr r3, [pc, #88] @ (8001970 ) - 8001918: 2208 movs r2, #8 - 800191a: 605a str r2, [r3, #4] - hcan1.Init.Mode = CAN_MODE_NORMAL; - 800191c: 4b14 ldr r3, [pc, #80] @ (8001970 ) - 800191e: 2200 movs r2, #0 - 8001920: 609a str r2, [r3, #8] - hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - 8001922: 4b13 ldr r3, [pc, #76] @ (8001970 ) - 8001924: 2200 movs r2, #0 - 8001926: 60da str r2, [r3, #12] - hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; - 8001928: 4b11 ldr r3, [pc, #68] @ (8001970 ) - 800192a: f44f 2260 mov.w r2, #917504 @ 0xe0000 - 800192e: 611a str r2, [r3, #16] - hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; - 8001930: 4b0f ldr r3, [pc, #60] @ (8001970 ) - 8001932: f44f 1280 mov.w r2, #1048576 @ 0x100000 - 8001936: 615a str r2, [r3, #20] - hcan1.Init.TimeTriggeredMode = DISABLE; - 8001938: 4b0d ldr r3, [pc, #52] @ (8001970 ) - 800193a: 2200 movs r2, #0 - 800193c: 761a strb r2, [r3, #24] - hcan1.Init.AutoBusOff = ENABLE; - 800193e: 4b0c ldr r3, [pc, #48] @ (8001970 ) - 8001940: 2201 movs r2, #1 - 8001942: 765a strb r2, [r3, #25] - hcan1.Init.AutoWakeUp = ENABLE; - 8001944: 4b0a ldr r3, [pc, #40] @ (8001970 ) - 8001946: 2201 movs r2, #1 - 8001948: 769a strb r2, [r3, #26] - hcan1.Init.AutoRetransmission = DISABLE; - 800194a: 4b09 ldr r3, [pc, #36] @ (8001970 ) - 800194c: 2200 movs r2, #0 - 800194e: 76da strb r2, [r3, #27] - hcan1.Init.ReceiveFifoLocked = DISABLE; - 8001950: 4b07 ldr r3, [pc, #28] @ (8001970 ) - 8001952: 2200 movs r2, #0 - 8001954: 771a strb r2, [r3, #28] - hcan1.Init.TransmitFifoPriority = ENABLE; - 8001956: 4b06 ldr r3, [pc, #24] @ (8001970 ) - 8001958: 2201 movs r2, #1 - 800195a: 775a strb r2, [r3, #29] - if (HAL_CAN_Init(&hcan1) != HAL_OK) - 800195c: 4804 ldr r0, [pc, #16] @ (8001970 ) - 800195e: f004 fc9b bl 8006298 - 8001962: 4603 mov r3, r0 - 8001964: 2b00 cmp r3, #0 - 8001966: d001 beq.n 800196c - { - Error_Handler(); - 8001968: f003 fb3a bl 8004fe0 - } - /* USER CODE BEGIN CAN1_Init 2 */ - - /* USER CODE END CAN1_Init 2 */ - -} - 800196c: bf00 nop - 800196e: bd80 pop {r7, pc} - 8001970: 20000288 .word 0x20000288 - 8001974: 40006400 .word 0x40006400 - -08001978 : -/* CAN2 init function */ -void MX_CAN2_Init(void) -{ - 8001978: b580 push {r7, lr} - 800197a: af00 add r7, sp, #0 - /* USER CODE END CAN2_Init 0 */ - - /* USER CODE BEGIN CAN2_Init 1 */ - - /* USER CODE END CAN2_Init 1 */ - hcan2.Instance = CAN2; - 800197c: 4b17 ldr r3, [pc, #92] @ (80019dc ) - 800197e: 4a18 ldr r2, [pc, #96] @ (80019e0 ) - 8001980: 601a str r2, [r3, #0] - hcan2.Init.Prescaler = 16; - 8001982: 4b16 ldr r3, [pc, #88] @ (80019dc ) - 8001984: 2210 movs r2, #16 - 8001986: 605a str r2, [r3, #4] - hcan2.Init.Mode = CAN_MODE_NORMAL; - 8001988: 4b14 ldr r3, [pc, #80] @ (80019dc ) - 800198a: 2200 movs r2, #0 - 800198c: 609a str r2, [r3, #8] - hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; - 800198e: 4b13 ldr r3, [pc, #76] @ (80019dc ) - 8001990: 2200 movs r2, #0 - 8001992: 60da str r2, [r3, #12] - hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; - 8001994: 4b11 ldr r3, [pc, #68] @ (80019dc ) - 8001996: f44f 2260 mov.w r2, #917504 @ 0xe0000 - 800199a: 611a str r2, [r3, #16] - hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; - 800199c: 4b0f ldr r3, [pc, #60] @ (80019dc ) - 800199e: f44f 1280 mov.w r2, #1048576 @ 0x100000 - 80019a2: 615a str r2, [r3, #20] - hcan2.Init.TimeTriggeredMode = DISABLE; - 80019a4: 4b0d ldr r3, [pc, #52] @ (80019dc ) - 80019a6: 2200 movs r2, #0 - 80019a8: 761a strb r2, [r3, #24] - hcan2.Init.AutoBusOff = ENABLE; - 80019aa: 4b0c ldr r3, [pc, #48] @ (80019dc ) - 80019ac: 2201 movs r2, #1 - 80019ae: 765a strb r2, [r3, #25] - hcan2.Init.AutoWakeUp = ENABLE; - 80019b0: 4b0a ldr r3, [pc, #40] @ (80019dc ) - 80019b2: 2201 movs r2, #1 - 80019b4: 769a strb r2, [r3, #26] - hcan2.Init.AutoRetransmission = ENABLE; - 80019b6: 4b09 ldr r3, [pc, #36] @ (80019dc ) - 80019b8: 2201 movs r2, #1 - 80019ba: 76da strb r2, [r3, #27] - hcan2.Init.ReceiveFifoLocked = DISABLE; - 80019bc: 4b07 ldr r3, [pc, #28] @ (80019dc ) - 80019be: 2200 movs r2, #0 - 80019c0: 771a strb r2, [r3, #28] - hcan2.Init.TransmitFifoPriority = ENABLE; - 80019c2: 4b06 ldr r3, [pc, #24] @ (80019dc ) - 80019c4: 2201 movs r2, #1 - 80019c6: 775a strb r2, [r3, #29] - if (HAL_CAN_Init(&hcan2) != HAL_OK) - 80019c8: 4804 ldr r0, [pc, #16] @ (80019dc ) - 80019ca: f004 fc65 bl 8006298 - 80019ce: 4603 mov r3, r0 - 80019d0: 2b00 cmp r3, #0 - 80019d2: d001 beq.n 80019d8 - { - Error_Handler(); - 80019d4: f003 fb04 bl 8004fe0 - } - /* USER CODE BEGIN CAN2_Init 2 */ - - /* USER CODE END CAN2_Init 2 */ - -} - 80019d8: bf00 nop - 80019da: bd80 pop {r7, pc} - 80019dc: 200002b0 .word 0x200002b0 - 80019e0: 40006800 .word 0x40006800 - -080019e4 : - -static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; - -void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) -{ - 80019e4: b580 push {r7, lr} - 80019e6: b08e sub sp, #56 @ 0x38 - 80019e8: af00 add r7, sp, #0 - 80019ea: 6078 str r0, [r7, #4] - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80019ec: f107 0320 add.w r3, r7, #32 - 80019f0: 2200 movs r2, #0 - 80019f2: 601a str r2, [r3, #0] - 80019f4: 605a str r2, [r3, #4] - 80019f6: 609a str r2, [r3, #8] - 80019f8: 60da str r2, [r3, #12] - if(canHandle->Instance==CAN1) - 80019fa: 687b ldr r3, [r7, #4] - 80019fc: 681b ldr r3, [r3, #0] - 80019fe: 4a61 ldr r2, [pc, #388] @ (8001b84 ) - 8001a00: 4293 cmp r3, r2 - 8001a02: d153 bne.n 8001aac - { - /* USER CODE BEGIN CAN1_MspInit 0 */ - - /* USER CODE END CAN1_MspInit 0 */ - /* CAN1 clock enable */ - HAL_RCC_CAN1_CLK_ENABLED++; - 8001a04: 4b60 ldr r3, [pc, #384] @ (8001b88 ) - 8001a06: 681b ldr r3, [r3, #0] - 8001a08: 3301 adds r3, #1 - 8001a0a: 4a5f ldr r2, [pc, #380] @ (8001b88 ) - 8001a0c: 6013 str r3, [r2, #0] - if(HAL_RCC_CAN1_CLK_ENABLED==1){ - 8001a0e: 4b5e ldr r3, [pc, #376] @ (8001b88 ) - 8001a10: 681b ldr r3, [r3, #0] - 8001a12: 2b01 cmp r3, #1 - 8001a14: d10b bne.n 8001a2e - __HAL_RCC_CAN1_CLK_ENABLE(); - 8001a16: 4b5d ldr r3, [pc, #372] @ (8001b8c ) - 8001a18: 69db ldr r3, [r3, #28] - 8001a1a: 4a5c ldr r2, [pc, #368] @ (8001b8c ) - 8001a1c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 8001a20: 61d3 str r3, [r2, #28] - 8001a22: 4b5a ldr r3, [pc, #360] @ (8001b8c ) - 8001a24: 69db ldr r3, [r3, #28] - 8001a26: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001a2a: 61fb str r3, [r7, #28] - 8001a2c: 69fb ldr r3, [r7, #28] - } - - __HAL_RCC_GPIOD_CLK_ENABLE(); - 8001a2e: 4b57 ldr r3, [pc, #348] @ (8001b8c ) - 8001a30: 699b ldr r3, [r3, #24] - 8001a32: 4a56 ldr r2, [pc, #344] @ (8001b8c ) - 8001a34: f043 0320 orr.w r3, r3, #32 - 8001a38: 6193 str r3, [r2, #24] - 8001a3a: 4b54 ldr r3, [pc, #336] @ (8001b8c ) - 8001a3c: 699b ldr r3, [r3, #24] - 8001a3e: f003 0320 and.w r3, r3, #32 - 8001a42: 61bb str r3, [r7, #24] - 8001a44: 69bb ldr r3, [r7, #24] - /**CAN1 GPIO Configuration - PD0 ------> CAN1_RX - PD1 ------> CAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_0; - 8001a46: 2301 movs r3, #1 - 8001a48: 623b str r3, [r7, #32] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8001a4a: 2300 movs r3, #0 - 8001a4c: 627b str r3, [r7, #36] @ 0x24 - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001a4e: 2300 movs r3, #0 - 8001a50: 62bb str r3, [r7, #40] @ 0x28 - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 8001a52: f107 0320 add.w r3, r7, #32 - 8001a56: 4619 mov r1, r3 - 8001a58: 484d ldr r0, [pc, #308] @ (8001b90 ) - 8001a5a: f005 fd19 bl 8007490 - - GPIO_InitStruct.Pin = GPIO_PIN_1; - 8001a5e: 2302 movs r3, #2 - 8001a60: 623b str r3, [r7, #32] - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8001a62: 2302 movs r3, #2 - 8001a64: 627b str r3, [r7, #36] @ 0x24 - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 8001a66: 2303 movs r3, #3 - 8001a68: 62fb str r3, [r7, #44] @ 0x2c - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 8001a6a: f107 0320 add.w r3, r7, #32 - 8001a6e: 4619 mov r1, r3 - 8001a70: 4847 ldr r0, [pc, #284] @ (8001b90 ) - 8001a72: f005 fd0d bl 8007490 - - __HAL_AFIO_REMAP_CAN1_3(); - 8001a76: 4b47 ldr r3, [pc, #284] @ (8001b94 ) - 8001a78: 685b ldr r3, [r3, #4] - 8001a7a: 633b str r3, [r7, #48] @ 0x30 - 8001a7c: 6b3b ldr r3, [r7, #48] @ 0x30 - 8001a7e: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 - 8001a82: 633b str r3, [r7, #48] @ 0x30 - 8001a84: 6b3b ldr r3, [r7, #48] @ 0x30 - 8001a86: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 - 8001a8a: 633b str r3, [r7, #48] @ 0x30 - 8001a8c: 6b3b ldr r3, [r7, #48] @ 0x30 - 8001a8e: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 - 8001a92: 633b str r3, [r7, #48] @ 0x30 - 8001a94: 4a3f ldr r2, [pc, #252] @ (8001b94 ) - 8001a96: 6b3b ldr r3, [r7, #48] @ 0x30 - 8001a98: 6053 str r3, [r2, #4] - - /* CAN1 interrupt Init */ - HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); - 8001a9a: 2200 movs r2, #0 - 8001a9c: 2100 movs r1, #0 - 8001a9e: 2014 movs r0, #20 - 8001aa0: f005 fb7d bl 800719e - HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); - 8001aa4: 2014 movs r0, #20 - 8001aa6: f005 fb96 bl 80071d6 - HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); - /* USER CODE BEGIN CAN2_MspInit 1 */ - - /* USER CODE END CAN2_MspInit 1 */ - } -} - 8001aaa: e067 b.n 8001b7c - else if(canHandle->Instance==CAN2) - 8001aac: 687b ldr r3, [r7, #4] - 8001aae: 681b ldr r3, [r3, #0] - 8001ab0: 4a39 ldr r2, [pc, #228] @ (8001b98 ) - 8001ab2: 4293 cmp r3, r2 - 8001ab4: d162 bne.n 8001b7c - __HAL_RCC_CAN2_CLK_ENABLE(); - 8001ab6: 4b35 ldr r3, [pc, #212] @ (8001b8c ) - 8001ab8: 69db ldr r3, [r3, #28] - 8001aba: 4a34 ldr r2, [pc, #208] @ (8001b8c ) - 8001abc: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 - 8001ac0: 61d3 str r3, [r2, #28] - 8001ac2: 4b32 ldr r3, [pc, #200] @ (8001b8c ) - 8001ac4: 69db ldr r3, [r3, #28] - 8001ac6: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 8001aca: 617b str r3, [r7, #20] - 8001acc: 697b ldr r3, [r7, #20] - HAL_RCC_CAN1_CLK_ENABLED++; - 8001ace: 4b2e ldr r3, [pc, #184] @ (8001b88 ) - 8001ad0: 681b ldr r3, [r3, #0] - 8001ad2: 3301 adds r3, #1 - 8001ad4: 4a2c ldr r2, [pc, #176] @ (8001b88 ) - 8001ad6: 6013 str r3, [r2, #0] - if(HAL_RCC_CAN1_CLK_ENABLED==1){ - 8001ad8: 4b2b ldr r3, [pc, #172] @ (8001b88 ) - 8001ada: 681b ldr r3, [r3, #0] - 8001adc: 2b01 cmp r3, #1 - 8001ade: d10b bne.n 8001af8 - __HAL_RCC_CAN1_CLK_ENABLE(); - 8001ae0: 4b2a ldr r3, [pc, #168] @ (8001b8c ) - 8001ae2: 69db ldr r3, [r3, #28] - 8001ae4: 4a29 ldr r2, [pc, #164] @ (8001b8c ) - 8001ae6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 8001aea: 61d3 str r3, [r2, #28] - 8001aec: 4b27 ldr r3, [pc, #156] @ (8001b8c ) - 8001aee: 69db ldr r3, [r3, #28] - 8001af0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001af4: 613b str r3, [r7, #16] - 8001af6: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 8001af8: 4b24 ldr r3, [pc, #144] @ (8001b8c ) - 8001afa: 699b ldr r3, [r3, #24] - 8001afc: 4a23 ldr r2, [pc, #140] @ (8001b8c ) - 8001afe: f043 0308 orr.w r3, r3, #8 - 8001b02: 6193 str r3, [r2, #24] - 8001b04: 4b21 ldr r3, [pc, #132] @ (8001b8c ) - 8001b06: 699b ldr r3, [r3, #24] - 8001b08: f003 0308 and.w r3, r3, #8 - 8001b0c: 60fb str r3, [r7, #12] - 8001b0e: 68fb ldr r3, [r7, #12] - GPIO_InitStruct.Pin = GPIO_PIN_5; - 8001b10: 2320 movs r3, #32 - 8001b12: 623b str r3, [r7, #32] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8001b14: 2300 movs r3, #0 - 8001b16: 627b str r3, [r7, #36] @ 0x24 - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001b18: 2300 movs r3, #0 - 8001b1a: 62bb str r3, [r7, #40] @ 0x28 - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8001b1c: f107 0320 add.w r3, r7, #32 - 8001b20: 4619 mov r1, r3 - 8001b22: 481e ldr r0, [pc, #120] @ (8001b9c ) - 8001b24: f005 fcb4 bl 8007490 - GPIO_InitStruct.Pin = GPIO_PIN_6; - 8001b28: 2340 movs r3, #64 @ 0x40 - 8001b2a: 623b str r3, [r7, #32] - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8001b2c: 2302 movs r3, #2 - 8001b2e: 627b str r3, [r7, #36] @ 0x24 - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 8001b30: 2303 movs r3, #3 - 8001b32: 62fb str r3, [r7, #44] @ 0x2c - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8001b34: f107 0320 add.w r3, r7, #32 - 8001b38: 4619 mov r1, r3 - 8001b3a: 4818 ldr r0, [pc, #96] @ (8001b9c ) - 8001b3c: f005 fca8 bl 8007490 - __HAL_AFIO_REMAP_CAN2_ENABLE(); - 8001b40: 4b14 ldr r3, [pc, #80] @ (8001b94 ) - 8001b42: 685b ldr r3, [r3, #4] - 8001b44: 637b str r3, [r7, #52] @ 0x34 - 8001b46: 6b7b ldr r3, [r7, #52] @ 0x34 - 8001b48: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 - 8001b4c: 637b str r3, [r7, #52] @ 0x34 - 8001b4e: 6b7b ldr r3, [r7, #52] @ 0x34 - 8001b50: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8001b54: 637b str r3, [r7, #52] @ 0x34 - 8001b56: 4a0f ldr r2, [pc, #60] @ (8001b94 ) - 8001b58: 6b7b ldr r3, [r7, #52] @ 0x34 - 8001b5a: 6053 str r3, [r2, #4] - HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); - 8001b5c: 2200 movs r2, #0 - 8001b5e: 2100 movs r1, #0 - 8001b60: 203f movs r0, #63 @ 0x3f - 8001b62: f005 fb1c bl 800719e - HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); - 8001b66: 203f movs r0, #63 @ 0x3f - 8001b68: f005 fb35 bl 80071d6 - HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); - 8001b6c: 2200 movs r2, #0 - 8001b6e: 2100 movs r1, #0 - 8001b70: 2041 movs r0, #65 @ 0x41 - 8001b72: f005 fb14 bl 800719e - HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); - 8001b76: 2041 movs r0, #65 @ 0x41 - 8001b78: f005 fb2d bl 80071d6 -} - 8001b7c: bf00 nop - 8001b7e: 3738 adds r7, #56 @ 0x38 - 8001b80: 46bd mov sp, r7 - 8001b82: bd80 pop {r7, pc} - 8001b84: 40006400 .word 0x40006400 - 8001b88: 200002d8 .word 0x200002d8 - 8001b8c: 40021000 .word 0x40021000 - 8001b90: 40011400 .word 0x40011400 - 8001b94: 40010000 .word 0x40010000 - 8001b98: 40006800 .word 0x40006800 - 8001b9c: 40010c00 .word 0x40010c00 - -08001ba0 : - -extern GBT_EDCAN_Output_t GBT_EDCAN_Output; -extern GBT_EDCAN_Input_t GBT_EDCAN_Input; - - -void GBT_Init(){ - 8001ba0: b580 push {r7, lr} - 8001ba2: af00 add r7, sp, #0 - GBT_State = GBT_DISABLED; - 8001ba4: 4b04 ldr r3, [pc, #16] @ (8001bb8 ) - 8001ba6: 2210 movs r2, #16 - 8001ba8: 701a strb r2, [r3, #0] - GBT_EDCAN_Input.chargeControl = CHARGING_NOT_ALLOWED; - 8001baa: 4b04 ldr r3, [pc, #16] @ (8001bbc ) - 8001bac: 2201 movs r2, #1 - 8001bae: 715a strb r2, [r3, #5] - GBT_Reset(); - 8001bb0: f000 fe2a bl 8002808 -} - 8001bb4: bf00 nop - 8001bb6: bd80 pop {r7, pc} - 8001bb8: 200002dc .word 0x200002dc - 8001bbc: 200004b4 .word 0x200004b4 - -08001bc0 : - - - - -void GBT_ChargerTask(){ - 8001bc0: b5b0 push {r4, r5, r7, lr} - 8001bc2: b084 sub sp, #16 - 8001bc4: af02 add r7, sp, #8 - - //GBT_LockTask(); - if(j_rx.state == 2){ - 8001bc6: 4ba1 ldr r3, [pc, #644] @ (8001e4c ) - 8001bc8: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8001bcc: 2b02 cmp r3, #2 - 8001bce: f040 80c1 bne.w 8001d54 - switch (j_rx.PGN){ - 8001bd2: 4b9e ldr r3, [pc, #632] @ (8001e4c ) - 8001bd4: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 - 8001bd8: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 - 8001bdc: d044 beq.n 8001c68 - 8001bde: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 - 8001be2: f200 80b3 bhi.w 8001d4c - 8001be6: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 - 8001bea: f000 80a6 beq.w 8001d3a - 8001bee: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 - 8001bf2: f200 80ab bhi.w 8001d4c - 8001bf6: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 - 8001bfa: f000 80a2 beq.w 8001d42 - 8001bfe: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 - 8001c02: f200 80a3 bhi.w 8001d4c - 8001c06: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 - 8001c0a: f000 809c beq.w 8001d46 - 8001c0e: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 - 8001c12: f200 809b bhi.w 8001d4c - 8001c16: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 - 8001c1a: f000 8096 beq.w 8001d4a - 8001c1e: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 - 8001c22: f200 8093 bhi.w 8001d4c - 8001c26: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 - 8001c2a: d07b beq.n 8001d24 - 8001c2c: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 - 8001c30: f200 808c bhi.w 8001d4c - 8001c34: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 - 8001c38: d063 beq.n 8001d02 - 8001c3a: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 - 8001c3e: f200 8085 bhi.w 8001d4c - 8001c42: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8001c46: d044 beq.n 8001cd2 - 8001c48: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8001c4c: d87e bhi.n 8001d4c - 8001c4e: f5b3 6f10 cmp.w r3, #2304 @ 0x900 - 8001c52: d02b beq.n 8001cac - 8001c54: f5b3 6f10 cmp.w r3, #2304 @ 0x900 - 8001c58: d878 bhi.n 8001d4c - 8001c5a: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 8001c5e: d00b beq.n 8001c78 - 8001c60: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 - 8001c64: d018 beq.n 8001c98 - 8001c66: e071 b.n 8001d4c - case 0x2700: //PGN BHM - GBT_BHM_recv = 1; - 8001c68: 4b79 ldr r3, [pc, #484] @ (8001e50 ) - 8001c6a: 2201 movs r2, #1 - 8001c6c: 701a strb r2, [r3, #0] - memcpy (&GBT_MaxVoltage, j_rx.data, sizeof(GBT_MaxVoltage)); - 8001c6e: 4b77 ldr r3, [pc, #476] @ (8001e4c ) - 8001c70: 881a ldrh r2, [r3, #0] - 8001c72: 4b78 ldr r3, [pc, #480] @ (8001e54 ) - 8001c74: 801a strh r2, [r3, #0] - - break; - 8001c76: e069 b.n 8001d4c - - case 0x0200: //PGN BRM LONG - GBT_BAT_INFO_recv = 1; - 8001c78: 4b77 ldr r3, [pc, #476] @ (8001e58 ) - 8001c7a: 2201 movs r2, #1 - 8001c7c: 701a strb r2, [r3, #0] - memcpy (&GBT_EVInfo, j_rx.data, sizeof(GBT_EVInfo)); - 8001c7e: 4a77 ldr r2, [pc, #476] @ (8001e5c ) - 8001c80: 4b72 ldr r3, [pc, #456] @ (8001e4c ) - 8001c82: 4614 mov r4, r2 - 8001c84: 461d mov r5, r3 - 8001c86: cd0f ldmia r5!, {r0, r1, r2, r3} - 8001c88: c40f stmia r4!, {r0, r1, r2, r3} - 8001c8a: cd0f ldmia r5!, {r0, r1, r2, r3} - 8001c8c: c40f stmia r4!, {r0, r1, r2, r3} - 8001c8e: cd0f ldmia r5!, {r0, r1, r2, r3} - 8001c90: c40f stmia r4!, {r0, r1, r2, r3} - 8001c92: 682b ldr r3, [r5, #0] - 8001c94: 7023 strb r3, [r4, #0] - - break; - 8001c96: e059 b.n 8001d4c - - case 0x0600: //PGN BCP LONG - GBT_BAT_STAT_recv = 1; - 8001c98: 4b71 ldr r3, [pc, #452] @ (8001e60 ) - 8001c9a: 2201 movs r2, #1 - 8001c9c: 701a strb r2, [r3, #0] - memcpy (&GBT_BATStat, j_rx.data, sizeof(GBT_BATStat)); - 8001c9e: 4a71 ldr r2, [pc, #452] @ (8001e64 ) - 8001ca0: 4b6a ldr r3, [pc, #424] @ (8001e4c ) - 8001ca2: 4614 mov r4, r2 - 8001ca4: cb0f ldmia r3, {r0, r1, r2, r3} - 8001ca6: c407 stmia r4!, {r0, r1, r2} - 8001ca8: 7023 strb r3, [r4, #0] - break; - 8001caa: e04f b.n 8001d4c - - case 0x0900: //PGN BRO - GBT_BRO_recv = 1; - 8001cac: 4b6e ldr r3, [pc, #440] @ (8001e68 ) - 8001cae: 2201 movs r2, #1 - 8001cb0: 701a strb r2, [r3, #0] - if(j_rx.data[0] == 0xAA) EV_ready = 1; - 8001cb2: 4b66 ldr r3, [pc, #408] @ (8001e4c ) - 8001cb4: 781b ldrb r3, [r3, #0] - 8001cb6: 2baa cmp r3, #170 @ 0xaa - 8001cb8: d103 bne.n 8001cc2 - 8001cba: 4b6c ldr r3, [pc, #432] @ (8001e6c ) - 8001cbc: 2201 movs r2, #1 - 8001cbe: 701a strb r2, [r3, #0] - 8001cc0: e002 b.n 8001cc8 - else EV_ready = 0; - 8001cc2: 4b6a ldr r3, [pc, #424] @ (8001e6c ) - 8001cc4: 2200 movs r2, #0 - 8001cc6: 701a strb r2, [r3, #0] - GBT_BRO = j_rx.data[0]; - 8001cc8: 4b60 ldr r3, [pc, #384] @ (8001e4c ) - 8001cca: 781a ldrb r2, [r3, #0] - 8001ccc: 4b68 ldr r3, [pc, #416] @ (8001e70 ) - 8001cce: 701a strb r2, [r3, #0] - break; - 8001cd0: e03c b.n 8001d4c - - case 0x1000: //PGN BCL - //TODO: power block - memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); - 8001cd2: 4b68 ldr r3, [pc, #416] @ (8001e74 ) - 8001cd4: 4a5d ldr r2, [pc, #372] @ (8001e4c ) - 8001cd6: e892 0003 ldmia.w r2, {r0, r1} - 8001cda: 6018 str r0, [r3, #0] - 8001cdc: 3304 adds r3, #4 - 8001cde: 7019 strb r1, [r3, #0] - uint16_t volt=GBT_ReqPower.requestedVoltage; - 8001ce0: 4b64 ldr r3, [pc, #400] @ (8001e74 ) - 8001ce2: 881b ldrh r3, [r3, #0] - 8001ce4: 80fb strh r3, [r7, #6] - GBT_EDCAN_Output.requestedVoltage = volt; - 8001ce6: 4b64 ldr r3, [pc, #400] @ (8001e78 ) - 8001ce8: 88fa ldrh r2, [r7, #6] - 8001cea: f8a3 2001 strh.w r2, [r3, #1] - uint16_t curr=4000-GBT_ReqPower.requestedCurrent; - 8001cee: 4b61 ldr r3, [pc, #388] @ (8001e74 ) - 8001cf0: 885b ldrh r3, [r3, #2] - 8001cf2: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 - 8001cf6: 80bb strh r3, [r7, #4] - GBT_EDCAN_Output.requestedCurrent = curr; - 8001cf8: 4b5f ldr r3, [pc, #380] @ (8001e78 ) - 8001cfa: 88ba ldrh r2, [r7, #4] - 8001cfc: f8a3 2003 strh.w r2, [r3, #3] - break; - 8001d00: e024 b.n 8001d4c - - case 0x1100: //PGN BCS - //TODO - memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); - 8001d02: 4b5e ldr r3, [pc, #376] @ (8001e7c ) - 8001d04: 4a51 ldr r2, [pc, #324] @ (8001e4c ) - 8001d06: ca07 ldmia r2, {r0, r1, r2} - 8001d08: c303 stmia r3!, {r0, r1} - 8001d0a: 701a strb r2, [r3, #0] - GBT_EDCAN_Output.chargingRemainingTimeMin = GBT_ChargingStatus.estimatedRemainingChargingTime; - 8001d0c: 4b5b ldr r3, [pc, #364] @ (8001e7c ) - 8001d0e: f8b3 3007 ldrh.w r3, [r3, #7] - 8001d12: b29a uxth r2, r3 - 8001d14: 4b58 ldr r3, [pc, #352] @ (8001e78 ) - 8001d16: f8a3 2007 strh.w r2, [r3, #7] - GBT_EDCAN_Output.chargingPercentage = GBT_ChargingStatus.currentChargeState; - 8001d1a: 4b58 ldr r3, [pc, #352] @ (8001e7c ) - 8001d1c: 799a ldrb r2, [r3, #6] - 8001d1e: 4b56 ldr r3, [pc, #344] @ (8001e78 ) - 8001d20: 719a strb r2, [r3, #6] - break; - 8001d22: e013 b.n 8001d4c - - case 0x1300: //PGN BSM - //TODO - memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); - 8001d24: 4b56 ldr r3, [pc, #344] @ (8001e80 ) - 8001d26: 4a49 ldr r2, [pc, #292] @ (8001e4c ) - 8001d28: e892 0003 ldmia.w r2, {r0, r1} - 8001d2c: 6018 str r0, [r3, #0] - 8001d2e: 3304 adds r3, #4 - 8001d30: 8019 strh r1, [r3, #0] - 8001d32: 3302 adds r3, #2 - 8001d34: 0c0a lsrs r2, r1, #16 - 8001d36: 701a strb r2, [r3, #0] - break; - 8001d38: e008 b.n 8001d4c -// case 0x1900: //PGN BST -// break; - - case 0x1C00: //PGN BSD - //TODO SOC Voltage Temp - GBT_BSD_recv = 1; - 8001d3a: 4b52 ldr r3, [pc, #328] @ (8001e84 ) - 8001d3c: 2201 movs r2, #1 - 8001d3e: 701a strb r2, [r3, #0] - break; - 8001d40: e004 b.n 8001d4c - break; - 8001d42: bf00 nop - 8001d44: e002 b.n 8001d4c - break; - 8001d46: bf00 nop - 8001d48: e000 b.n 8001d4c - break; - 8001d4a: bf00 nop -// break; - - //BSM BMV BMT BSP BST BSD BEM - - } - j_rx.state = 0; - 8001d4c: 4b3f ldr r3, [pc, #252] @ (8001e4c ) - 8001d4e: 2200 movs r2, #0 - 8001d50: f883 210a strb.w r2, [r3, #266] @ 0x10a - } - - if((HAL_GetTick() - GBT_delay_start) < GBT_delay){ - 8001d54: f003 fd6e bl 8005834 - 8001d58: 4602 mov r2, r0 - 8001d5a: 4b4b ldr r3, [pc, #300] @ (8001e88 ) - 8001d5c: 681b ldr r3, [r3, #0] - 8001d5e: 1ad2 subs r2, r2, r3 - 8001d60: 4b4a ldr r3, [pc, #296] @ (8001e8c ) - 8001d62: 681b ldr r3, [r3, #0] - 8001d64: 429a cmp r2, r3 - 8001d66: f0c0 839b bcc.w 80024a0 - //waiting - }else switch (GBT_State){ - 8001d6a: 4b49 ldr r3, [pc, #292] @ (8001e90 ) - 8001d6c: 781b ldrb r3, [r3, #0] - 8001d6e: 3b10 subs r3, #16 - 8001d70: 2b15 cmp r3, #21 - 8001d72: f200 837c bhi.w 800246e - 8001d76: a201 add r2, pc, #4 @ (adr r2, 8001d7c ) - 8001d78: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8001d7c: 08001dd5 .word 0x08001dd5 - 8001d80: 0800246f .word 0x0800246f - 8001d84: 0800246f .word 0x0800246f - 8001d88: 08001df1 .word 0x08001df1 - 8001d8c: 08001e01 .word 0x08001e01 - 8001d90: 08001ea1 .word 0x08001ea1 - 8001d94: 08001f1d .word 0x08001f1d - 8001d98: 08002027 .word 0x08002027 - 8001d9c: 08002125 .word 0x08002125 - 8001da0: 0800224b .word 0x0800224b - 8001da4: 0800246f .word 0x0800246f - 8001da8: 0800246f .word 0x0800246f - 8001dac: 0800246f .word 0x0800246f - 8001db0: 0800246f .word 0x0800246f - 8001db4: 0800246f .word 0x0800246f - 8001db8: 0800246f .word 0x0800246f - 8001dbc: 08002279 .word 0x08002279 - 8001dc0: 080022d7 .word 0x080022d7 - 8001dc4: 080023eb .word 0x080023eb - 8001dc8: 0800242d .word 0x0800242d - 8001dcc: 0800244d .word 0x0800244d - 8001dd0: 0800245f .word 0x0800245f - case GBT_DISABLED: - RELAY_Write(RELAY_AUX, 0); - 8001dd4: 2100 movs r1, #0 - 8001dd6: 2000 movs r0, #0 - 8001dd8: f7ff fc6e bl 80016b8 - if(connectorState == CONN_Charging){ - 8001ddc: 4b2d ldr r3, [pc, #180] @ (8001e94 ) - 8001dde: 781b ldrb r3, [r3, #0] - 8001de0: 2b05 cmp r3, #5 - 8001de2: f040 8348 bne.w 8002476 - GBT_Reset(); - 8001de6: f000 fd0f bl 8002808 - GBT_Start();//TODO IF protections (maybe not needed) - 8001dea: f000 fd81 bl 80028f0 - } - break; - 8001dee: e342 b.n 8002476 -// GBT_Delay(500); -// } -// break; - - case GBT_S3_STARTED: - GBT_SwitchState(GBT_S31_WAIT_BHM); - 8001df0: 2014 movs r0, #20 - 8001df2: f000 fb83 bl 80024fc - GBT_Delay(500); - 8001df6: f44f 70fa mov.w r0, #500 @ 0x1f4 - 8001dfa: f000 fcaf bl 800275c - break; - 8001dfe: e34f b.n 80024a0 - - case GBT_S31_WAIT_BHM: - if(j_rx.state == 0) GBT_SendCHM(); - 8001e00: 4b12 ldr r3, [pc, #72] @ (8001e4c ) - 8001e02: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8001e06: 2b00 cmp r3, #0 - 8001e08: d101 bne.n 8001e0e - 8001e0a: f001 fd69 bl 80038e0 - GBT_Delay(250); - 8001e0e: 20fa movs r0, #250 @ 0xfa - 8001e10: f000 fca4 bl 800275c - - if(GBT_BHM_recv) { - 8001e14: 4b0e ldr r3, [pc, #56] @ (8001e50 ) - 8001e16: 781b ldrb r3, [r3, #0] - 8001e18: 2b00 cmp r3, #0 - 8001e1a: d002 beq.n 8001e22 - GBT_SwitchState(GBT_S4_ISOTEST); - 8001e1c: 2015 movs r0, #21 - 8001e1e: f000 fb6d bl 80024fc - } - - //Timeout 10S - if((GBT_BHM_recv == 0) && (GBT_StateTick()>10000)) { //BHM Timeout - 8001e22: 4b0b ldr r3, [pc, #44] @ (8001e50 ) - 8001e24: 781b ldrb r3, [r3, #0] - 8001e26: 2b00 cmp r3, #0 - 8001e28: f040 8327 bne.w 800247a - 8001e2c: f000 fc8a bl 8002744 - 8001e30: 4603 mov r3, r0 - 8001e32: f242 7210 movw r2, #10000 @ 0x2710 - 8001e36: 4293 cmp r3, r2 - 8001e38: f240 831f bls.w 800247a - GBT_Error(0xFCF0C0FC); - 8001e3c: 4816 ldr r0, [pc, #88] @ (8001e98 ) - 8001e3e: f000 fcb7 bl 80027b0 - EDCAN_printf(LOG_WARN, "BHM Timeout\n"); - 8001e42: 4916 ldr r1, [pc, #88] @ (8001e9c ) - 8001e44: 2004 movs r0, #4 - 8001e46: f002 ff63 bl 8004d10 - } - break; - 8001e4a: e316 b.n 800247a - 8001e4c: 200004bc .word 0x200004bc - 8001e50: 200002ef .word 0x200002ef - 8001e54: 20000304 .word 0x20000304 - 8001e58: 200002ec .word 0x200002ec - 8001e5c: 20000308 .word 0x20000308 - 8001e60: 200002ed .word 0x200002ed - 8001e64: 2000033c .word 0x2000033c - 8001e68: 200002ee .word 0x200002ee - 8001e6c: 200002f1 .word 0x200002f1 - 8001e70: 20000380 .word 0x20000380 - 8001e74: 2000034c .word 0x2000034c - 8001e78: 200004a4 .word 0x200004a4 - 8001e7c: 2000035c .word 0x2000035c - 8001e80: 20000368 .word 0x20000368 - 8001e84: 200002f0 .word 0x200002f0 - 8001e88: 200002e4 .word 0x200002e4 - 8001e8c: 200002e8 .word 0x200002e8 - 8001e90: 200002dc .word 0x200002dc - 8001e94: 20000390 .word 0x20000390 - 8001e98: fcf0c0fc .word 0xfcf0c0fc - 8001e9c: 0800d640 .word 0x0800d640 - - case GBT_S4_ISOTEST: - if(j_rx.state == 0) GBT_SendCHM(); - 8001ea0: 4bb7 ldr r3, [pc, #732] @ (8002180 ) - 8001ea2: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8001ea6: 2b00 cmp r3, #0 - 8001ea8: d101 bne.n 8001eae - 8001eaa: f001 fd19 bl 80038e0 - GBT_Delay(250); - 8001eae: 20fa movs r0, #250 @ 0xfa - 8001eb0: f000 fc54 bl 800275c - - GBT_EDCAN_Output.requestedVoltage = GBT_MaxVoltage.maxOutputVoltage; - 8001eb4: 4bb3 ldr r3, [pc, #716] @ (8002184 ) - 8001eb6: 881a ldrh r2, [r3, #0] - 8001eb8: 4bb3 ldr r3, [pc, #716] @ (8002188 ) - 8001eba: f8a3 2001 strh.w r2, [r3, #1] - GBT_EDCAN_Output.requestedCurrent = 10; // 1A max - 8001ebe: 4bb2 ldr r3, [pc, #712] @ (8002188 ) - 8001ec0: 2200 movs r2, #0 - 8001ec2: f042 020a orr.w r2, r2, #10 - 8001ec6: 70da strb r2, [r3, #3] - 8001ec8: 2200 movs r2, #0 - 8001eca: 711a strb r2, [r3, #4] - GBT_EDCAN_Output.enablePSU = 1; - 8001ecc: 4bae ldr r3, [pc, #696] @ (8002188 ) - 8001ece: 2201 movs r2, #1 - 8001ed0: 701a strb r2, [r3, #0] - - //TODO: Isolation test trigger - if(GBT_EDCAN_Input.chargingError == GBT_ERR_INSULATION){ - 8001ed2: 4bae ldr r3, [pc, #696] @ (800218c ) - 8001ed4: 799b ldrb r3, [r3, #6] - 8001ed6: 2b01 cmp r3, #1 - 8001ed8: d103 bne.n 8001ee2 - GBT_Stop(GBT_CST_OTHERFALUT); - 8001eda: f24f 40f0 movw r0, #62704 @ 0xf4f0 - 8001ede: f000 fc51 bl 8002784 - } - - if(GBT_StateTick()>5000){ - 8001ee2: f000 fc2f bl 8002744 - 8001ee6: 4603 mov r3, r0 - 8001ee8: f241 3288 movw r2, #5000 @ 0x1388 - 8001eec: 4293 cmp r3, r2 - 8001eee: f240 82c6 bls.w 800247e - GBT_SwitchState(GBT_S5_BAT_INFO); - 8001ef2: 2016 movs r0, #22 - 8001ef4: f000 fb02 bl 80024fc - GBT_EDCAN_Output.requestedVoltage = 50; - 8001ef8: 4ba3 ldr r3, [pc, #652] @ (8002188 ) - 8001efa: 2200 movs r2, #0 - 8001efc: f042 0232 orr.w r2, r2, #50 @ 0x32 - 8001f00: 705a strb r2, [r3, #1] - 8001f02: 2200 movs r2, #0 - 8001f04: 709a strb r2, [r3, #2] - GBT_EDCAN_Output.requestedCurrent = 10; // 1A max - 8001f06: 4ba0 ldr r3, [pc, #640] @ (8002188 ) - 8001f08: 2200 movs r2, #0 - 8001f0a: f042 020a orr.w r2, r2, #10 - 8001f0e: 70da strb r2, [r3, #3] - 8001f10: 2200 movs r2, #0 - 8001f12: 711a strb r2, [r3, #4] - GBT_EDCAN_Output.enablePSU = 0; - 8001f14: 4b9c ldr r3, [pc, #624] @ (8002188 ) - 8001f16: 2200 movs r2, #0 - 8001f18: 701a strb r2, [r3, #0] - } - - break; - 8001f1a: e2b0 b.n 800247e - - case GBT_S5_BAT_INFO: - if(j_rx.state == 0) GBT_SendCRM(0x00); - 8001f1c: 4b98 ldr r3, [pc, #608] @ (8002180 ) - 8001f1e: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8001f22: 2b00 cmp r3, #0 - 8001f24: d102 bne.n 8001f2c - 8001f26: 2000 movs r0, #0 - 8001f28: f001 fcee bl 8003908 - GBT_Delay(250); - 8001f2c: 20fa movs r0, #250 @ 0xfa - 8001f2e: f000 fc15 bl 800275c - if(GBT_BAT_INFO_recv){ //BRM - 8001f32: 4b97 ldr r3, [pc, #604] @ (8002190 ) - 8001f34: 781b ldrb r3, [r3, #0] - 8001f36: 2b00 cmp r3, #0 - 8001f38: d060 beq.n 8001ffc - //Got battery info - GBT_SwitchState(GBT_S6_BAT_STAT); - 8001f3a: 2017 movs r0, #23 - 8001f3c: f000 fade bl 80024fc - EDCAN_printf(LOG_INFO, "EV info:\n"); - 8001f40: 4994 ldr r1, [pc, #592] @ (8002194 ) - 8001f42: 2006 movs r0, #6 - 8001f44: f002 fee4 bl 8004d10 - EDCAN_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); - 8001f48: 4b93 ldr r3, [pc, #588] @ (8002198 ) - 8001f4a: 781b ldrb r3, [r3, #0] - 8001f4c: 461a mov r2, r3 - 8001f4e: 4b92 ldr r3, [pc, #584] @ (8002198 ) - 8001f50: 785b ldrb r3, [r3, #1] - 8001f52: 4619 mov r1, r3 - 8001f54: 4b90 ldr r3, [pc, #576] @ (8002198 ) - 8001f56: 789b ldrb r3, [r3, #2] - 8001f58: 9300 str r3, [sp, #0] - 8001f5a: 460b mov r3, r1 - 8001f5c: 498f ldr r1, [pc, #572] @ (800219c ) - 8001f5e: 2006 movs r0, #6 - 8001f60: f002 fed6 bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); - 8001f64: 4b8c ldr r3, [pc, #560] @ (8002198 ) - 8001f66: 78db ldrb r3, [r3, #3] - 8001f68: 461a mov r2, r3 - 8001f6a: 498d ldr r1, [pc, #564] @ (80021a0 ) - 8001f6c: 2006 movs r0, #6 - 8001f6e: f002 fecf bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit - 8001f72: 4b89 ldr r3, [pc, #548] @ (8002198 ) - 8001f74: 889b ldrh r3, [r3, #4] - 8001f76: 461a mov r2, r3 - 8001f78: 498a ldr r1, [pc, #552] @ (80021a4 ) - 8001f7a: 2006 movs r0, #6 - 8001f7c: f002 fec8 bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit - 8001f80: 4b85 ldr r3, [pc, #532] @ (8002198 ) - 8001f82: 88db ldrh r3, [r3, #6] - 8001f84: 461a mov r2, r3 - 8001f86: 4988 ldr r1, [pc, #544] @ (80021a8 ) - 8001f88: 2006 movs r0, #6 - 8001f8a: f002 fec1 bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) - 8001f8e: 4a87 ldr r2, [pc, #540] @ (80021ac ) - 8001f90: 4987 ldr r1, [pc, #540] @ (80021b0 ) - 8001f92: 2006 movs r0, #6 - 8001f94: f002 febc bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int - 8001f98: 4b7f ldr r3, [pc, #508] @ (8002198 ) - 8001f9a: 68db ldr r3, [r3, #12] - 8001f9c: 461a mov r2, r3 - 8001f9e: 4985 ldr r1, [pc, #532] @ (80021b4 ) - 8001fa0: 2006 movs r0, #6 - 8001fa2: f002 feb5 bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) - 8001fa6: 4b7c ldr r3, [pc, #496] @ (8002198 ) - 8001fa8: 7c9b ldrb r3, [r3, #18] - 8001faa: 461a mov r2, r3 - 8001fac: 4b7a ldr r3, [pc, #488] @ (8002198 ) - 8001fae: 7c5b ldrb r3, [r3, #17] - 8001fb0: 4619 mov r1, r3 - 8001fb2: 4b79 ldr r3, [pc, #484] @ (8002198 ) - 8001fb4: 7c1b ldrb r3, [r3, #16] - 8001fb6: f203 73c1 addw r3, r3, #1985 @ 0x7c1 - 8001fba: 9300 str r3, [sp, #0] - 8001fbc: 460b mov r3, r1 - 8001fbe: 497e ldr r1, [pc, #504] @ (80021b8 ) - 8001fc0: 2006 movs r0, #6 - 8001fc2: f002 fea5 bl 8004d10 - EDCAN_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t - 8001fc6: 4b74 ldr r3, [pc, #464] @ (8002198 ) - 8001fc8: 7cda ldrb r2, [r3, #19] - 8001fca: 8a9b ldrh r3, [r3, #20] - 8001fcc: 021b lsls r3, r3, #8 - 8001fce: 4313 orrs r3, r2 - 8001fd0: 461a mov r2, r3 - 8001fd2: 497a ldr r1, [pc, #488] @ (80021bc ) - 8001fd4: 2006 movs r0, #6 - 8001fd6: f002 fe9b bl 8004d10 - EDCAN_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto - 8001fda: 4b6f ldr r3, [pc, #444] @ (8002198 ) - 8001fdc: 7d9b ldrb r3, [r3, #22] - 8001fde: 461a mov r2, r3 - 8001fe0: 4977 ldr r1, [pc, #476] @ (80021c0 ) - 8001fe2: 2006 movs r0, #6 - 8001fe4: f002 fe94 bl 8004d10 - EDCAN_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN - 8001fe8: 4a76 ldr r2, [pc, #472] @ (80021c4 ) - 8001fea: 4977 ldr r1, [pc, #476] @ (80021c8 ) - 8001fec: 2006 movs r0, #6 - 8001fee: f002 fe8f bl 8004d10 - EDCAN_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); - 8001ff2: 4a76 ldr r2, [pc, #472] @ (80021cc ) - 8001ff4: 4976 ldr r1, [pc, #472] @ (80021d0 ) - 8001ff6: 2006 movs r0, #6 - 8001ff8: f002 fe8a bl 8004d10 - - } - //Timeout - if((GBT_StateTick()>5000) && (GBT_BAT_INFO_recv == 0)){ - 8001ffc: f000 fba2 bl 8002744 - 8002000: 4603 mov r3, r0 - 8002002: f241 3288 movw r2, #5000 @ 0x1388 - 8002006: 4293 cmp r3, r2 - 8002008: f240 823b bls.w 8002482 - 800200c: 4b60 ldr r3, [pc, #384] @ (8002190 ) - 800200e: 781b ldrb r3, [r3, #0] - 8002010: 2b00 cmp r3, #0 - 8002012: f040 8236 bne.w 8002482 - GBT_Error(0xFDF0C0FC); //BRM Timeout - 8002016: 486f ldr r0, [pc, #444] @ (80021d4 ) - 8002018: f000 fbca bl 80027b0 - EDCAN_printf(LOG_WARN, "BRM Timeout\n"); - 800201c: 496e ldr r1, [pc, #440] @ (80021d8 ) - 800201e: 2004 movs r0, #4 - 8002020: f002 fe76 bl 8004d10 - } - break; - 8002024: e22d b.n 8002482 - - case GBT_S6_BAT_STAT: - if(j_rx.state == 0) GBT_SendCRM(0xAA); - 8002026: 4b56 ldr r3, [pc, #344] @ (8002180 ) - 8002028: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 800202c: 2b00 cmp r3, #0 - 800202e: d102 bne.n 8002036 - 8002030: 20aa movs r0, #170 @ 0xaa - 8002032: f001 fc69 bl 8003908 - GBT_Delay(250); - 8002036: 20fa movs r0, #250 @ 0xfa - 8002038: f000 fb90 bl 800275c - if(GBT_BAT_STAT_recv){ - 800203c: 4b67 ldr r3, [pc, #412] @ (80021dc ) - 800203e: 781b ldrb r3, [r3, #0] - 8002040: 2b00 cmp r3, #0 - 8002042: d05a beq.n 80020fa - //Got battery status - GBT_SwitchState(GBT_S7_BMS_WAIT); - 8002044: 2018 movs r0, #24 - 8002046: f000 fa59 bl 80024fc - EDCAN_printf(LOG_INFO, "Battery info:\n"); - 800204a: 4965 ldr r1, [pc, #404] @ (80021e0 ) - 800204c: 2006 movs r0, #6 - 800204e: f002 fe5f bl 8004d10 - EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit - 8002052: 4b64 ldr r3, [pc, #400] @ (80021e4 ) - 8002054: 881b ldrh r3, [r3, #0] - 8002056: 4a64 ldr r2, [pc, #400] @ (80021e8 ) - 8002058: fba2 2303 umull r2, r3, r2, r3 - 800205c: 095b lsrs r3, r3, #5 - 800205e: b29b uxth r3, r3 - 8002060: 461a mov r2, r3 - 8002062: 4962 ldr r1, [pc, #392] @ (80021ec ) - 8002064: 2006 movs r0, #6 - 8002066: f002 fe53 bl 8004d10 - EDCAN_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit - 800206a: 4b5e ldr r3, [pc, #376] @ (80021e4 ) - 800206c: 885b ldrh r3, [r3, #2] - 800206e: 4a60 ldr r2, [pc, #384] @ (80021f0 ) - 8002070: fba2 2303 umull r2, r3, r2, r3 - 8002074: 08db lsrs r3, r3, #3 - 8002076: b29b uxth r3, r3 - 8002078: 461a mov r2, r3 - 800207a: 495e ldr r1, [pc, #376] @ (80021f4 ) - 800207c: 2006 movs r0, #6 - 800207e: f002 fe47 bl 8004d10 - EDCAN_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh - 8002082: 4b58 ldr r3, [pc, #352] @ (80021e4 ) - 8002084: 889b ldrh r3, [r3, #4] - 8002086: 4a5a ldr r2, [pc, #360] @ (80021f0 ) - 8002088: fba2 2303 umull r2, r3, r2, r3 - 800208c: 08db lsrs r3, r3, #3 - 800208e: b29b uxth r3, r3 - 8002090: 461a mov r2, r3 - 8002092: 4959 ldr r1, [pc, #356] @ (80021f8 ) - 8002094: 2006 movs r0, #6 - 8002096: f002 fe3b bl 8004d10 - EDCAN_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit - 800209a: 4b52 ldr r3, [pc, #328] @ (80021e4 ) - 800209c: 88db ldrh r3, [r3, #6] - 800209e: 4a54 ldr r2, [pc, #336] @ (80021f0 ) - 80020a0: fba2 2303 umull r2, r3, r2, r3 - 80020a4: 08db lsrs r3, r3, #3 - 80020a6: b29b uxth r3, r3 - 80020a8: 461a mov r2, r3 - 80020aa: 4950 ldr r1, [pc, #320] @ (80021ec ) - 80020ac: 2006 movs r0, #6 - 80020ae: f002 fe2f bl 8004d10 - EDCAN_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset - 80020b2: 4b4c ldr r3, [pc, #304] @ (80021e4 ) - 80020b4: 7a1b ldrb r3, [r3, #8] - 80020b6: 3b32 subs r3, #50 @ 0x32 - 80020b8: 461a mov r2, r3 - 80020ba: 4950 ldr r1, [pc, #320] @ (80021fc ) - 80020bc: 2006 movs r0, #6 - 80020be: f002 fe27 bl 8004d10 - EDCAN_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% - 80020c2: 4b48 ldr r3, [pc, #288] @ (80021e4 ) - 80020c4: f8b3 3009 ldrh.w r3, [r3, #9] - 80020c8: b29b uxth r3, r3 - 80020ca: 4a49 ldr r2, [pc, #292] @ (80021f0 ) - 80020cc: fba2 2303 umull r2, r3, r2, r3 - 80020d0: 08db lsrs r3, r3, #3 - 80020d2: b29b uxth r3, r3 - 80020d4: 461a mov r2, r3 - 80020d6: 494a ldr r1, [pc, #296] @ (8002200 ) - 80020d8: 2006 movs r0, #6 - 80020da: f002 fe19 bl 8004d10 - EDCAN_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit - 80020de: 4b41 ldr r3, [pc, #260] @ (80021e4 ) - 80020e0: f8b3 300b ldrh.w r3, [r3, #11] - 80020e4: b29b uxth r3, r3 - 80020e6: 4a42 ldr r2, [pc, #264] @ (80021f0 ) - 80020e8: fba2 2303 umull r2, r3, r2, r3 - 80020ec: 08db lsrs r3, r3, #3 - 80020ee: b29b uxth r3, r3 - 80020f0: 461a mov r2, r3 - 80020f2: 4944 ldr r1, [pc, #272] @ (8002204 ) - 80020f4: 2006 movs r0, #6 - 80020f6: f002 fe0b bl 8004d10 - - } - if((GBT_StateTick()>5000) && (GBT_BAT_STAT_recv == 0)){ - 80020fa: f000 fb23 bl 8002744 - 80020fe: 4603 mov r3, r0 - 8002100: f241 3288 movw r2, #5000 @ 0x1388 - 8002104: 4293 cmp r3, r2 - 8002106: f240 81be bls.w 8002486 - 800210a: 4b34 ldr r3, [pc, #208] @ (80021dc ) - 800210c: 781b ldrb r3, [r3, #0] - 800210e: 2b00 cmp r3, #0 - 8002110: f040 81b9 bne.w 8002486 - GBT_Error(0xFCF1C0FC); //BCP Timeout - 8002114: 483c ldr r0, [pc, #240] @ (8002208 ) - 8002116: f000 fb4b bl 80027b0 - EDCAN_printf(LOG_WARN, "BCP Timeout\n"); - 800211a: 493c ldr r1, [pc, #240] @ (800220c ) - 800211c: 2004 movs r0, #4 - 800211e: f002 fdf7 bl 8004d10 - } - break; - 8002122: e1b0 b.n 8002486 - - case GBT_S7_BMS_WAIT: - if(j_rx.state == 0) GBT_SendCTS(); - 8002124: 4b16 ldr r3, [pc, #88] @ (8002180 ) - 8002126: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 800212a: 2b00 cmp r3, #0 - 800212c: d101 bne.n 8002132 - 800212e: f001 fbb3 bl 8003898 - HAL_Delay(2); - 8002132: 2002 movs r0, #2 - 8002134: f003 fb88 bl 8005848 - if(j_rx.state == 0) GBT_SendCML(); - 8002138: 4b11 ldr r3, [pc, #68] @ (8002180 ) - 800213a: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 800213e: 2b00 cmp r3, #0 - 8002140: d101 bne.n 8002146 - 8002142: f001 fbbf bl 80038c4 - GBT_Delay(250); - 8002146: 20fa movs r0, #250 @ 0xfa - 8002148: f000 fb08 bl 800275c - if((GBT_StateTick()>5000) && (GBT_BRO_recv == 0)){ - 800214c: f000 fafa bl 8002744 - 8002150: 4603 mov r3, r0 - 8002152: f241 3288 movw r2, #5000 @ 0x1388 - 8002156: 4293 cmp r3, r2 - 8002158: d90a bls.n 8002170 - 800215a: 4b2d ldr r3, [pc, #180] @ (8002210 ) - 800215c: 781b ldrb r3, [r3, #0] - 800215e: 2b00 cmp r3, #0 - 8002160: d106 bne.n 8002170 - GBT_Error(0xFCF4C0FC); //BRO Timeout - 8002162: 482c ldr r0, [pc, #176] @ (8002214 ) - 8002164: f000 fb24 bl 80027b0 - EDCAN_printf(LOG_WARN, "BRO Timeout\n"); - 8002168: 492b ldr r1, [pc, #172] @ (8002218 ) - 800216a: 2004 movs r0, #4 - 800216c: f002 fdd0 bl 8004d10 - } - if(EV_ready){ - 8002170: 4b2a ldr r3, [pc, #168] @ (800221c ) - 8002172: 781b ldrb r3, [r3, #0] - 8002174: 2b00 cmp r3, #0 - 8002176: d053 beq.n 8002220 - //EV ready (AA) - GBT_SwitchState(GBT_S8_INIT_CHARGER); - 8002178: 2019 movs r0, #25 - 800217a: f000 f9bf bl 80024fc - if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ - GBT_Error(0xFCF4C0FC); //BRO Timeout - EDCAN_printf(LOG_WARN, "BRO Timeout\n"); - } - } - break; - 800217e: e184 b.n 800248a - 8002180: 200004bc .word 0x200004bc - 8002184: 20000304 .word 0x20000304 - 8002188: 200004a4 .word 0x200004a4 - 800218c: 200004b4 .word 0x200004b4 - 8002190: 200002ec .word 0x200002ec - 8002194: 0800d650 .word 0x0800d650 - 8002198: 20000308 .word 0x20000308 - 800219c: 0800d65c .word 0x0800d65c - 80021a0: 0800d670 .word 0x0800d670 - 80021a4: 0800d684 .word 0x0800d684 - 80021a8: 0800d69c .word 0x0800d69c - 80021ac: 20000310 .word 0x20000310 - 80021b0: 0800d6b4 .word 0x0800d6b4 - 80021b4: 0800d6cc .word 0x0800d6cc - 80021b8: 0800d6e0 .word 0x0800d6e0 - 80021bc: 0800d70c .word 0x0800d70c - 80021c0: 0800d720 .word 0x0800d720 - 80021c4: 20000320 .word 0x20000320 - 80021c8: 0800d730 .word 0x0800d730 - 80021cc: 20000331 .word 0x20000331 - 80021d0: 0800d740 .word 0x0800d740 - 80021d4: fdf0c0fc .word 0xfdf0c0fc - 80021d8: 0800d754 .word 0x0800d754 - 80021dc: 200002ed .word 0x200002ed - 80021e0: 0800d764 .word 0x0800d764 - 80021e4: 2000033c .word 0x2000033c - 80021e8: 51eb851f .word 0x51eb851f - 80021ec: 0800d774 .word 0x0800d774 - 80021f0: cccccccd .word 0xcccccccd - 80021f4: 0800d780 .word 0x0800d780 - 80021f8: 0800d78c .word 0x0800d78c - 80021fc: 0800d798 .word 0x0800d798 - 8002200: 0800d7a4 .word 0x0800d7a4 - 8002204: 0800d7b0 .word 0x0800d7b0 - 8002208: fcf1c0fc .word 0xfcf1c0fc - 800220c: 0800d7bc .word 0x0800d7bc - 8002210: 200002ee .word 0x200002ee - 8002214: fcf4c0fc .word 0xfcf4c0fc - 8002218: 0800d7cc .word 0x0800d7cc - 800221c: 200002f1 .word 0x200002f1 - if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ - 8002220: f000 fa90 bl 8002744 - 8002224: 4603 mov r3, r0 - 8002226: f64e 2260 movw r2, #60000 @ 0xea60 - 800222a: 4293 cmp r3, r2 - 800222c: f240 812d bls.w 800248a - 8002230: 4b9d ldr r3, [pc, #628] @ (80024a8 ) - 8002232: 781b ldrb r3, [r3, #0] - 8002234: 2b01 cmp r3, #1 - 8002236: f040 8128 bne.w 800248a - GBT_Error(0xFCF4C0FC); //BRO Timeout - 800223a: 489c ldr r0, [pc, #624] @ (80024ac ) - 800223c: f000 fab8 bl 80027b0 - EDCAN_printf(LOG_WARN, "BRO Timeout\n"); - 8002240: 499b ldr r1, [pc, #620] @ (80024b0 ) - 8002242: 2004 movs r0, #4 - 8002244: f002 fd64 bl 8004d10 - break; - 8002248: e11f b.n 800248a - - case GBT_S8_INIT_CHARGER: - if(j_rx.state == 0) GBT_SendCRO(0x00); - 800224a: 4b9a ldr r3, [pc, #616] @ (80024b4 ) - 800224c: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8002250: 2b00 cmp r3, #0 - 8002252: d102 bne.n 800225a - 8002254: 2000 movs r0, #0 - 8002256: f001 fb6d bl 8003934 - //TODO - GBT_Delay(250); - 800225a: 20fa movs r0, #250 @ 0xfa - 800225c: f000 fa7e bl 800275c - if(GBT_StateTick()>1500){ - 8002260: f000 fa70 bl 8002744 - 8002264: 4603 mov r3, r0 - 8002266: f240 52dc movw r2, #1500 @ 0x5dc - 800226a: 4293 cmp r3, r2 - 800226c: f240 810f bls.w 800248e - //Power Modules initiated - GBT_SwitchState(GBT_S9_WAIT_BCL); - 8002270: 2020 movs r0, #32 - 8002272: f000 f943 bl 80024fc - } - break; - 8002276: e10a b.n 800248e - - case GBT_S9_WAIT_BCL: - if(j_rx.state == 0) GBT_SendCRO(0xAA); - 8002278: 4b8e ldr r3, [pc, #568] @ (80024b4 ) - 800227a: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 800227e: 2b00 cmp r3, #0 - 8002280: d102 bne.n 8002288 - 8002282: 20aa movs r0, #170 @ 0xaa - 8002284: f001 fb56 bl 8003934 - GBT_Delay(250); - 8002288: 20fa movs r0, #250 @ 0xfa - 800228a: f000 fa67 bl 800275c - if(GBT_ReqPower.chargingMode != 0){ //REFACTORING - 800228e: 4b8a ldr r3, [pc, #552] @ (80024b8 ) - 8002290: 791b ldrb r3, [r3, #4] - 8002292: 2b00 cmp r3, #0 - 8002294: f000 80fd beq.w 8002492 - //BCL power requirements received - - GBT_SwitchState(GBT_S10_CHARGING); - 8002298: 2021 movs r0, #33 @ 0x21 - 800229a: f000 f92f bl 80024fc - CONN_SetState(CONN_Charging); - 800229e: 2005 movs r0, #5 - 80022a0: f000 fbba bl 8002a18 - uint16_t curr=4000-GBT_ReqPower.requestedCurrent; - 80022a4: 4b84 ldr r3, [pc, #528] @ (80024b8 ) - 80022a6: 885b ldrh r3, [r3, #2] - 80022a8: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 - 80022ac: 807b strh r3, [r7, #2] - uint16_t volt=GBT_ReqPower.requestedVoltage; - 80022ae: 4b82 ldr r3, [pc, #520] @ (80024b8 ) - 80022b0: 881b ldrh r3, [r3, #0] - 80022b2: 803b strh r3, [r7, #0] - //TODO Limits - - GBT_EDCAN_Output.requestedVoltage = volt; - 80022b4: 4b81 ldr r3, [pc, #516] @ (80024bc ) - 80022b6: 883a ldrh r2, [r7, #0] - 80022b8: f8a3 2001 strh.w r2, [r3, #1] - GBT_EDCAN_Output.requestedCurrent = curr; - 80022bc: 4b7f ldr r3, [pc, #508] @ (80024bc ) - 80022be: 887a ldrh r2, [r7, #2] - 80022c0: f8a3 2003 strh.w r2, [r3, #3] - GBT_EDCAN_Output.enablePSU = 1; - 80022c4: 4b7d ldr r3, [pc, #500] @ (80024bc ) - 80022c6: 2201 movs r2, #1 - 80022c8: 701a strb r2, [r3, #0] - GBT_TimeChargingStarted = get_Current_Time(); - 80022ca: f002 fecf bl 800506c - 80022ce: 4603 mov r3, r0 - 80022d0: 4a7b ldr r2, [pc, #492] @ (80024c0 ) - 80022d2: 6013 str r3, [r2, #0] - - } - break; - 80022d4: e0dd b.n 8002492 - - case GBT_S10_CHARGING: - //CHARGING - //TODO BCL BCS BSM missing ERRORS - if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); - 80022d6: 4b7b ldr r3, [pc, #492] @ (80024c4 ) - 80022d8: 795b ldrb r3, [r3, #5] - 80022da: 2b01 cmp r3, #1 - 80022dc: d102 bne.n 80022e4 - 80022de: 487a ldr r0, [pc, #488] @ (80024c8 ) - 80022e0: f000 fa50 bl 8002784 - if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK) GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY);//GBT_ForceStop(); - 80022e4: 4b77 ldr r3, [pc, #476] @ (80024c4 ) - 80022e6: 795b ldrb r3, [r3, #5] - 80022e8: 2b03 cmp r3, #3 - 80022ea: d102 bne.n 80022f2 - 80022ec: 4876 ldr r0, [pc, #472] @ (80024c8 ) - 80022ee: f000 fa49 bl 8002784 - if(GBT_LockState.error) GBT_Stop(GBT_CST_OTHERFALUT); - 80022f2: 4b76 ldr r3, [pc, #472] @ (80024cc ) - 80022f4: 785b ldrb r3, [r3, #1] - 80022f6: 2b00 cmp r3, #0 - 80022f8: d003 beq.n 8002302 - 80022fa: f24f 40f0 movw r0, #62704 @ 0xf4f0 - 80022fe: f000 fa41 bl 8002784 - if((GBT_ReadTemp(0) > 90) || (GBT_ReadTemp(1) > 90)) { - 8002302: 2000 movs r0, #0 - 8002304: f7ff fa7a bl 80017fc - 8002308: 4603 mov r3, r0 - 800230a: 2b5a cmp r3, #90 @ 0x5a - 800230c: dc05 bgt.n 800231a - 800230e: 2001 movs r0, #1 - 8002310: f7ff fa74 bl 80017fc - 8002314: 4603 mov r3, r0 - 8002316: 2b5a cmp r3, #90 @ 0x5a - 8002318: dd10 ble.n 800233c - GBT_Stop(GBT_CST_CONNECTOR_OVER_TEMP); - 800231a: 486d ldr r0, [pc, #436] @ (80024d0 ) - 800231c: f000 fa32 bl 8002784 - EDCAN_printf(LOG_WARN, "Connector overheat %d %d\n", GBT_ReadTemp(0), GBT_ReadTemp(1)); - 8002320: 2000 movs r0, #0 - 8002322: f7ff fa6b bl 80017fc - 8002326: 4603 mov r3, r0 - 8002328: 461c mov r4, r3 - 800232a: 2001 movs r0, #1 - 800232c: f7ff fa66 bl 80017fc - 8002330: 4603 mov r3, r0 - 8002332: 4622 mov r2, r4 - 8002334: 4967 ldr r1, [pc, #412] @ (80024d4 ) - 8002336: 2004 movs r0, #4 - 8002338: f002 fcea bl 8004d10 - } - if(GBT_EDCAN_Input.chargingError == GBT_ERR_INSULATION) { - 800233c: 4b61 ldr r3, [pc, #388] @ (80024c4 ) - 800233e: 799b ldrb r3, [r3, #6] - 8002340: 2b01 cmp r3, #1 - 8002342: d107 bne.n 8002354 - GBT_Stop(GBT_CST_OTHERFALUT); - 8002344: f24f 40f0 movw r0, #62704 @ 0xf4f0 - 8002348: f000 fa1c bl 8002784 - EDCAN_printf(LOG_WARN, "Isolation error\n"); - 800234c: 4962 ldr r1, [pc, #392] @ (80024d8 ) - 800234e: 2004 movs r0, #4 - 8002350: f002 fcde bl 8004d10 - } - - //GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111100;//NOT PERMITTED - GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111101; - 8002354: 4b61 ldr r3, [pc, #388] @ (80024dc ) - 8002356: f64f 72fd movw r2, #65533 @ 0xfffd - 800235a: 80da strh r2, [r3, #6] - GBT_ChargerCurrentStatus.chargingTime = (get_Current_Time() - GBT_TimeChargingStarted)/60; - 800235c: f002 fe86 bl 800506c - 8002360: 4602 mov r2, r0 - 8002362: 4b57 ldr r3, [pc, #348] @ (80024c0 ) - 8002364: 681b ldr r3, [r3, #0] - 8002366: 1ad3 subs r3, r2, r3 - 8002368: 4a5d ldr r2, [pc, #372] @ (80024e0 ) - 800236a: fba2 2303 umull r2, r3, r2, r3 - 800236e: 095b lsrs r3, r3, #5 - 8002370: b29a uxth r2, r3 - 8002372: 4b5a ldr r3, [pc, #360] @ (80024dc ) - 8002374: 809a strh r2, [r3, #4] -// GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Output.requestedCurrent; -// GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Output.requestedVoltage; - GBT_ChargerCurrentStatus.outputCurrent = 4000 - GBT_EDCAN_Input.measuredCurrent; - 8002376: 4b53 ldr r3, [pc, #332] @ (80024c4 ) - 8002378: f8b3 3003 ldrh.w r3, [r3, #3] - 800237c: b29b uxth r3, r3 - 800237e: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 - 8002382: b29a uxth r2, r3 - 8002384: 4b55 ldr r3, [pc, #340] @ (80024dc ) - 8002386: 805a strh r2, [r3, #2] - GBT_ChargerCurrentStatus.outputVoltage = GBT_EDCAN_Input.measuredVoltage; - 8002388: 4b4e ldr r3, [pc, #312] @ (80024c4 ) - 800238a: f8b3 3001 ldrh.w r3, [r3, #1] - 800238e: b29a uxth r2, r3 - 8002390: 4b52 ldr r3, [pc, #328] @ (80024dc ) - 8002392: 801a strh r2, [r3, #0] - GBT_EDCAN_Output.chargingElapsedTimeMin = (get_Current_Time() - GBT_TimeChargingStarted)/60; - 8002394: f002 fe6a bl 800506c - 8002398: 4602 mov r2, r0 - 800239a: 4b49 ldr r3, [pc, #292] @ (80024c0 ) - 800239c: 681b ldr r3, [r3, #0] - 800239e: 1ad3 subs r3, r2, r3 - 80023a0: 4a4f ldr r2, [pc, #316] @ (80024e0 ) - 80023a2: fba2 2303 umull r2, r3, r2, r3 - 80023a6: 095b lsrs r3, r3, #5 - 80023a8: b29a uxth r2, r3 - 80023aa: 4b44 ldr r3, [pc, #272] @ (80024bc ) - 80023ac: f8a3 2009 strh.w r2, [r3, #9] - GBT_EDCAN_Output.chargingElapsedTimeSec = (get_Current_Time() - GBT_TimeChargingStarted)%60; - 80023b0: f002 fe5c bl 800506c - 80023b4: 4602 mov r2, r0 - 80023b6: 4b42 ldr r3, [pc, #264] @ (80024c0 ) - 80023b8: 681b ldr r3, [r3, #0] - 80023ba: 1ad1 subs r1, r2, r3 - 80023bc: 4b48 ldr r3, [pc, #288] @ (80024e0 ) - 80023be: fba3 2301 umull r2, r3, r3, r1 - 80023c2: 095a lsrs r2, r3, #5 - 80023c4: 4613 mov r3, r2 - 80023c6: 011b lsls r3, r3, #4 - 80023c8: 1a9b subs r3, r3, r2 - 80023ca: 009b lsls r3, r3, #2 - 80023cc: 1aca subs r2, r1, r3 - 80023ce: b2d2 uxtb r2, r2 - 80023d0: 4b3a ldr r3, [pc, #232] @ (80024bc ) - 80023d2: 72da strb r2, [r3, #11] - - if(j_rx.state == 0) GBT_SendCCS(); - 80023d4: 4b37 ldr r3, [pc, #220] @ (80024b4 ) - 80023d6: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 80023da: 2b00 cmp r3, #0 - 80023dc: d101 bne.n 80023e2 - 80023de: f001 fabd bl 800395c - - GBT_Delay(50); - 80023e2: 2032 movs r0, #50 @ 0x32 - 80023e4: f000 f9ba bl 800275c - //TODO: снижение тока если перегрев контактов - - break; - 80023e8: e05a b.n 80024a0 - - case GBT_STOP: - GBT_Delay(10); - 80023ea: 200a movs r0, #10 - 80023ec: f000 f9b6 bl 800275c - GBT_EDCAN_Output.enablePSU = 0; - 80023f0: 4b32 ldr r3, [pc, #200] @ (80024bc ) - 80023f2: 2200 movs r2, #0 - 80023f4: 701a strb r2, [r3, #0] - GBT_SendCST(GBT_StopCauseCode); - 80023f6: 4b3b ldr r3, [pc, #236] @ (80024e4 ) - 80023f8: 681b ldr r3, [r3, #0] - 80023fa: 4618 mov r0, r3 - 80023fc: f001 fabc bl 8003978 - //RELAY_Write(RELAY_OUTPUT, 0); - //GBT_SwitchState(GBT_DISABLED); - if(GBT_StateTick()>10000){ - 8002400: f000 f9a0 bl 8002744 - 8002404: 4603 mov r3, r0 - 8002406: f242 7210 movw r2, #10000 @ 0x2710 - 800240a: 4293 cmp r3, r2 - 800240c: d906 bls.n 800241c - EDCAN_printf(LOG_WARN, "BSD Timeout\n"); - 800240e: 4936 ldr r1, [pc, #216] @ (80024e8 ) - 8002410: 2004 movs r0, #4 - 8002412: f002 fc7d bl 8004d10 - GBT_Error(0xFCF0C0FD); //BSD Timeout - 8002416: 4835 ldr r0, [pc, #212] @ (80024ec ) - 8002418: f000 f9ca bl 80027b0 - - } - - if(GBT_BSD_recv != 0){ - 800241c: 4b34 ldr r3, [pc, #208] @ (80024f0 ) - 800241e: 781b ldrb r3, [r3, #0] - 8002420: 2b00 cmp r3, #0 - 8002422: d038 beq.n 8002496 - GBT_SwitchState(GBT_STOP_CSD); - 8002424: 2023 movs r0, #35 @ 0x23 - 8002426: f000 f869 bl 80024fc - } - - break; - 800242a: e034 b.n 8002496 - case GBT_STOP_CSD: - GBT_Delay(250); - 800242c: 20fa movs r0, #250 @ 0xfa - 800242e: f000 f995 bl 800275c - GBT_SendCSD(); - 8002432: f001 fac1 bl 80039b8 - if(GBT_StateTick()>2500){ //2.5S - 8002436: f000 f985 bl 8002744 - 800243a: 4603 mov r3, r0 - 800243c: f640 12c4 movw r2, #2500 @ 0x9c4 - 8002440: 4293 cmp r3, r2 - 8002442: d92a bls.n 800249a - GBT_SwitchState(GBT_COMPLETE); - 8002444: 2025 movs r0, #37 @ 0x25 - 8002446: f000 f859 bl 80024fc -// GBT_Reset(); - //CONN_SetState(CONN_Occupied_complete); - //if(connectorState == CONN_Occupied_charging) - //PSU_Mode(0x0100); - } - break; - 800244a: e026 b.n 800249a - - - case GBT_ERROR: - GBT_SendCEM(GBT_ErrorCode); //2.5S - 800244c: 4b29 ldr r3, [pc, #164] @ (80024f4 ) - 800244e: 681b ldr r3, [r3, #0] - 8002450: 4618 mov r0, r3 - 8002452: f001 fad1 bl 80039f8 - GBT_SwitchState(GBT_COMPLETE); - 8002456: 2025 movs r0, #37 @ 0x25 - 8002458: f000 f850 bl 80024fc -// GBT_Reset(); - // - break; - 800245c: e020 b.n 80024a0 - - case GBT_COMPLETE: - if(connectorState != CONN_Finishing) GBT_SwitchState(GBT_DISABLED); - 800245e: 4b26 ldr r3, [pc, #152] @ (80024f8 ) - 8002460: 781b ldrb r3, [r3, #0] - 8002462: 2b06 cmp r3, #6 - 8002464: d01b beq.n 800249e - 8002466: 2010 movs r0, #16 - 8002468: f000 f848 bl 80024fc - break; - 800246c: e017 b.n 800249e - - default: - GBT_SwitchState(GBT_DISABLED); - 800246e: 2010 movs r0, #16 - 8002470: f000 f844 bl 80024fc - } -} - 8002474: e014 b.n 80024a0 - break; - 8002476: bf00 nop - 8002478: e012 b.n 80024a0 - break; - 800247a: bf00 nop - 800247c: e010 b.n 80024a0 - break; - 800247e: bf00 nop - 8002480: e00e b.n 80024a0 - break; - 8002482: bf00 nop - 8002484: e00c b.n 80024a0 - break; - 8002486: bf00 nop - 8002488: e00a b.n 80024a0 - break; - 800248a: bf00 nop - 800248c: e008 b.n 80024a0 - break; - 800248e: bf00 nop - 8002490: e006 b.n 80024a0 - break; - 8002492: bf00 nop - 8002494: e004 b.n 80024a0 - break; - 8002496: bf00 nop - 8002498: e002 b.n 80024a0 - break; - 800249a: bf00 nop - 800249c: e000 b.n 80024a0 - break; - 800249e: bf00 nop -} - 80024a0: bf00 nop - 80024a2: 3708 adds r7, #8 - 80024a4: 46bd mov sp, r7 - 80024a6: bdb0 pop {r4, r5, r7, pc} - 80024a8: 200002ee .word 0x200002ee - 80024ac: fcf4c0fc .word 0xfcf4c0fc - 80024b0: 0800d7cc .word 0x0800d7cc - 80024b4: 200004bc .word 0x200004bc - 80024b8: 2000034c .word 0x2000034c - 80024bc: 200004a4 .word 0x200004a4 - 80024c0: 20000384 .word 0x20000384 - 80024c4: 200004b4 .word 0x200004b4 - 80024c8: 0400f0f0 .word 0x0400f0f0 - 80024cc: 200005cc .word 0x200005cc - 80024d0: 0001f0f0 .word 0x0001f0f0 - 80024d4: 0800d7dc .word 0x0800d7dc - 80024d8: 0800d7f8 .word 0x0800d7f8 - 80024dc: 20000370 .word 0x20000370 - 80024e0: 88888889 .word 0x88888889 - 80024e4: 20000388 .word 0x20000388 - 80024e8: 0800d80c .word 0x0800d80c - 80024ec: fcf0c0fd .word 0xfcf0c0fd - 80024f0: 200002f0 .word 0x200002f0 - 80024f4: 2000038c .word 0x2000038c - 80024f8: 20000390 .word 0x20000390 - -080024fc : - - - -void GBT_SwitchState(gbtState_t state){ - 80024fc: b580 push {r7, lr} - 80024fe: b082 sub sp, #8 - 8002500: af00 add r7, sp, #0 - 8002502: 4603 mov r3, r0 - 8002504: 71fb strb r3, [r7, #7] - GBT_State = state; - 8002506: 4a70 ldr r2, [pc, #448] @ (80026c8 ) - 8002508: 79fb ldrb r3, [r7, #7] - 800250a: 7013 strb r3, [r2, #0] - ED_status = state; - 800250c: 4a6f ldr r2, [pc, #444] @ (80026cc ) - 800250e: 79fb ldrb r3, [r7, #7] - 8002510: 7013 strb r3, [r2, #0] - GBT_state_tick = HAL_GetTick(); - 8002512: f003 f98f bl 8005834 - 8002516: 4603 mov r3, r0 - 8002518: 4a6d ldr r2, [pc, #436] @ (80026d0 ) - 800251a: 6013 str r3, [r2, #0] - if(GBT_State == GBT_DISABLED) printf ("GBT_DISABLED\n"); - 800251c: 4b6a ldr r3, [pc, #424] @ (80026c8 ) - 800251e: 781b ldrb r3, [r3, #0] - 8002520: 2b10 cmp r3, #16 - 8002522: d102 bne.n 800252a - 8002524: 486b ldr r0, [pc, #428] @ (80026d4 ) - 8002526: f007 fd91 bl 800a04c -// if(GBT_State == GBT_S0_UNCONNECTED) printf ("GBT_S0_UNCONNECTED\n"); -// if(GBT_State == GBT_S1_CONNECTED) printf ("GBT_S1_CONNECTED\n"); -// if(GBT_State == GBT_S2_LOCKED) printf ("GBT_S2_LOCKED\n"); - if(GBT_State == GBT_S3_STARTED) printf ("GBT_S3_STARTED\n"); - 800252a: 4b67 ldr r3, [pc, #412] @ (80026c8 ) - 800252c: 781b ldrb r3, [r3, #0] - 800252e: 2b13 cmp r3, #19 - 8002530: d102 bne.n 8002538 - 8002532: 4869 ldr r0, [pc, #420] @ (80026d8 ) - 8002534: f007 fd8a bl 800a04c - if(GBT_State == GBT_S31_WAIT_BHM) printf ("GBT_S31_WAIT_BHM\n"); - 8002538: 4b63 ldr r3, [pc, #396] @ (80026c8 ) - 800253a: 781b ldrb r3, [r3, #0] - 800253c: 2b14 cmp r3, #20 - 800253e: d102 bne.n 8002546 - 8002540: 4866 ldr r0, [pc, #408] @ (80026dc ) - 8002542: f007 fd83 bl 800a04c - if(GBT_State == GBT_S4_ISOTEST) printf ("GBT_S4_ISOTEST\n"); - 8002546: 4b60 ldr r3, [pc, #384] @ (80026c8 ) - 8002548: 781b ldrb r3, [r3, #0] - 800254a: 2b15 cmp r3, #21 - 800254c: d102 bne.n 8002554 - 800254e: 4864 ldr r0, [pc, #400] @ (80026e0 ) - 8002550: f007 fd7c bl 800a04c - if(GBT_State == GBT_S5_BAT_INFO) printf ("GBT_S5_BAT_INFO\n"); - 8002554: 4b5c ldr r3, [pc, #368] @ (80026c8 ) - 8002556: 781b ldrb r3, [r3, #0] - 8002558: 2b16 cmp r3, #22 - 800255a: d102 bne.n 8002562 - 800255c: 4861 ldr r0, [pc, #388] @ (80026e4 ) - 800255e: f007 fd75 bl 800a04c - if(GBT_State == GBT_S6_BAT_STAT) printf ("GBT_S6_BAT_STAT\n"); - 8002562: 4b59 ldr r3, [pc, #356] @ (80026c8 ) - 8002564: 781b ldrb r3, [r3, #0] - 8002566: 2b17 cmp r3, #23 - 8002568: d102 bne.n 8002570 - 800256a: 485f ldr r0, [pc, #380] @ (80026e8 ) - 800256c: f007 fd6e bl 800a04c - if(GBT_State == GBT_S7_BMS_WAIT) printf ("GBT_S7_BMS_WAIT\n"); - 8002570: 4b55 ldr r3, [pc, #340] @ (80026c8 ) - 8002572: 781b ldrb r3, [r3, #0] - 8002574: 2b18 cmp r3, #24 - 8002576: d102 bne.n 800257e - 8002578: 485c ldr r0, [pc, #368] @ (80026ec ) - 800257a: f007 fd67 bl 800a04c - if(GBT_State == GBT_S8_INIT_CHARGER)printf ("GBT_S8_INIT_CHARGER\n"); - 800257e: 4b52 ldr r3, [pc, #328] @ (80026c8 ) - 8002580: 781b ldrb r3, [r3, #0] - 8002582: 2b19 cmp r3, #25 - 8002584: d102 bne.n 800258c - 8002586: 485a ldr r0, [pc, #360] @ (80026f0 ) - 8002588: f007 fd60 bl 800a04c - if(GBT_State == GBT_S9_WAIT_BCL) printf ("GBT_S9_WAIT_BCL\n"); - 800258c: 4b4e ldr r3, [pc, #312] @ (80026c8 ) - 800258e: 781b ldrb r3, [r3, #0] - 8002590: 2b20 cmp r3, #32 - 8002592: d102 bne.n 800259a - 8002594: 4857 ldr r0, [pc, #348] @ (80026f4 ) - 8002596: f007 fd59 bl 800a04c - if(GBT_State == GBT_S10_CHARGING) printf ("GBT_S10_CHARGING\n"); - 800259a: 4b4b ldr r3, [pc, #300] @ (80026c8 ) - 800259c: 781b ldrb r3, [r3, #0] - 800259e: 2b21 cmp r3, #33 @ 0x21 - 80025a0: d102 bne.n 80025a8 - 80025a2: 4855 ldr r0, [pc, #340] @ (80026f8 ) - 80025a4: f007 fd52 bl 800a04c - if(GBT_State == GBT_STOP) printf ("GBT_STOP\n"); - 80025a8: 4b47 ldr r3, [pc, #284] @ (80026c8 ) - 80025aa: 781b ldrb r3, [r3, #0] - 80025ac: 2b22 cmp r3, #34 @ 0x22 - 80025ae: d102 bne.n 80025b6 - 80025b0: 4852 ldr r0, [pc, #328] @ (80026fc ) - 80025b2: f007 fd4b bl 800a04c - if(GBT_State == GBT_STOP_CSD) printf ("GBT_STOP_CSD\n"); - 80025b6: 4b44 ldr r3, [pc, #272] @ (80026c8 ) - 80025b8: 781b ldrb r3, [r3, #0] - 80025ba: 2b23 cmp r3, #35 @ 0x23 - 80025bc: d102 bne.n 80025c4 - 80025be: 4850 ldr r0, [pc, #320] @ (8002700 ) - 80025c0: f007 fd44 bl 800a04c - if(GBT_State == GBT_ERROR) printf ("GBT_ERROR\n"); - 80025c4: 4b40 ldr r3, [pc, #256] @ (80026c8 ) - 80025c6: 781b ldrb r3, [r3, #0] - 80025c8: 2b24 cmp r3, #36 @ 0x24 - 80025ca: d102 bne.n 80025d2 - 80025cc: 484d ldr r0, [pc, #308] @ (8002704 ) - 80025ce: f007 fd3d bl 800a04c - if(GBT_State == GBT_COMPLETE) printf ("GBT_COMPLETE\n"); - 80025d2: 4b3d ldr r3, [pc, #244] @ (80026c8 ) - 80025d4: 781b ldrb r3, [r3, #0] - 80025d6: 2b25 cmp r3, #37 @ 0x25 - 80025d8: d102 bne.n 80025e0 - 80025da: 484b ldr r0, [pc, #300] @ (8002708 ) - 80025dc: f007 fd36 bl 800a04c - - if(GBT_State == GBT_DISABLED) EDCAN_printf(LOG_INFO, "GBT_DISABLED\n"); - 80025e0: 4b39 ldr r3, [pc, #228] @ (80026c8 ) - 80025e2: 781b ldrb r3, [r3, #0] - 80025e4: 2b10 cmp r3, #16 - 80025e6: d103 bne.n 80025f0 - 80025e8: 4948 ldr r1, [pc, #288] @ (800270c ) - 80025ea: 2006 movs r0, #6 - 80025ec: f002 fb90 bl 8004d10 - if(GBT_State == GBT_S3_STARTED) EDCAN_printf(LOG_INFO, "GBT_S3_STARTED\n"); - 80025f0: 4b35 ldr r3, [pc, #212] @ (80026c8 ) - 80025f2: 781b ldrb r3, [r3, #0] - 80025f4: 2b13 cmp r3, #19 - 80025f6: d103 bne.n 8002600 - 80025f8: 4945 ldr r1, [pc, #276] @ (8002710 ) - 80025fa: 2006 movs r0, #6 - 80025fc: f002 fb88 bl 8004d10 - if(GBT_State == GBT_S31_WAIT_BHM) EDCAN_printf(LOG_INFO, "GBT_S31_WAIT_BHM\n"); - 8002600: 4b31 ldr r3, [pc, #196] @ (80026c8 ) - 8002602: 781b ldrb r3, [r3, #0] - 8002604: 2b14 cmp r3, #20 - 8002606: d103 bne.n 8002610 - 8002608: 4942 ldr r1, [pc, #264] @ (8002714 ) - 800260a: 2006 movs r0, #6 - 800260c: f002 fb80 bl 8004d10 - if(GBT_State == GBT_S4_ISOTEST) EDCAN_printf(LOG_INFO, "GBT_S4_ISOTEST\n"); - 8002610: 4b2d ldr r3, [pc, #180] @ (80026c8 ) - 8002612: 781b ldrb r3, [r3, #0] - 8002614: 2b15 cmp r3, #21 - 8002616: d103 bne.n 8002620 - 8002618: 493f ldr r1, [pc, #252] @ (8002718 ) - 800261a: 2006 movs r0, #6 - 800261c: f002 fb78 bl 8004d10 - if(GBT_State == GBT_S5_BAT_INFO) EDCAN_printf(LOG_INFO, "GBT_S5_BAT_INFO\n"); - 8002620: 4b29 ldr r3, [pc, #164] @ (80026c8 ) - 8002622: 781b ldrb r3, [r3, #0] - 8002624: 2b16 cmp r3, #22 - 8002626: d103 bne.n 8002630 - 8002628: 493c ldr r1, [pc, #240] @ (800271c ) - 800262a: 2006 movs r0, #6 - 800262c: f002 fb70 bl 8004d10 - if(GBT_State == GBT_S6_BAT_STAT) EDCAN_printf(LOG_INFO, "GBT_S6_BAT_STAT\n"); - 8002630: 4b25 ldr r3, [pc, #148] @ (80026c8 ) - 8002632: 781b ldrb r3, [r3, #0] - 8002634: 2b17 cmp r3, #23 - 8002636: d103 bne.n 8002640 - 8002638: 4939 ldr r1, [pc, #228] @ (8002720 ) - 800263a: 2006 movs r0, #6 - 800263c: f002 fb68 bl 8004d10 - if(GBT_State == GBT_S7_BMS_WAIT) EDCAN_printf(LOG_INFO, "GBT_S7_BMS_WAIT\n"); - 8002640: 4b21 ldr r3, [pc, #132] @ (80026c8 ) - 8002642: 781b ldrb r3, [r3, #0] - 8002644: 2b18 cmp r3, #24 - 8002646: d103 bne.n 8002650 - 8002648: 4936 ldr r1, [pc, #216] @ (8002724 ) - 800264a: 2006 movs r0, #6 - 800264c: f002 fb60 bl 8004d10 - if(GBT_State == GBT_S8_INIT_CHARGER)EDCAN_printf(LOG_INFO, "GBT_S8_INIT_CHARGER\n"); - 8002650: 4b1d ldr r3, [pc, #116] @ (80026c8 ) - 8002652: 781b ldrb r3, [r3, #0] - 8002654: 2b19 cmp r3, #25 - 8002656: d103 bne.n 8002660 - 8002658: 4933 ldr r1, [pc, #204] @ (8002728 ) - 800265a: 2006 movs r0, #6 - 800265c: f002 fb58 bl 8004d10 - if(GBT_State == GBT_S9_WAIT_BCL) EDCAN_printf(LOG_INFO, "GBT_S9_WAIT_BCL\n"); - 8002660: 4b19 ldr r3, [pc, #100] @ (80026c8 ) - 8002662: 781b ldrb r3, [r3, #0] - 8002664: 2b20 cmp r3, #32 - 8002666: d103 bne.n 8002670 - 8002668: 4930 ldr r1, [pc, #192] @ (800272c ) - 800266a: 2006 movs r0, #6 - 800266c: f002 fb50 bl 8004d10 - if(GBT_State == GBT_S10_CHARGING) EDCAN_printf(LOG_INFO, "GBT_S10_CHARGING\n"); - 8002670: 4b15 ldr r3, [pc, #84] @ (80026c8 ) - 8002672: 781b ldrb r3, [r3, #0] - 8002674: 2b21 cmp r3, #33 @ 0x21 - 8002676: d103 bne.n 8002680 - 8002678: 492d ldr r1, [pc, #180] @ (8002730 ) - 800267a: 2006 movs r0, #6 - 800267c: f002 fb48 bl 8004d10 - if(GBT_State == GBT_STOP) EDCAN_printf(LOG_INFO, "GBT_STOP\n"); - 8002680: 4b11 ldr r3, [pc, #68] @ (80026c8 ) - 8002682: 781b ldrb r3, [r3, #0] - 8002684: 2b22 cmp r3, #34 @ 0x22 - 8002686: d103 bne.n 8002690 - 8002688: 492a ldr r1, [pc, #168] @ (8002734 ) - 800268a: 2006 movs r0, #6 - 800268c: f002 fb40 bl 8004d10 - if(GBT_State == GBT_STOP_CSD) EDCAN_printf(LOG_INFO, "GBT_STOP_CSD\n"); - 8002690: 4b0d ldr r3, [pc, #52] @ (80026c8 ) - 8002692: 781b ldrb r3, [r3, #0] - 8002694: 2b23 cmp r3, #35 @ 0x23 - 8002696: d103 bne.n 80026a0 - 8002698: 4927 ldr r1, [pc, #156] @ (8002738 ) - 800269a: 2006 movs r0, #6 - 800269c: f002 fb38 bl 8004d10 - if(GBT_State == GBT_ERROR) EDCAN_printf(LOG_WARN, "GBT_ERROR\n"); - 80026a0: 4b09 ldr r3, [pc, #36] @ (80026c8 ) - 80026a2: 781b ldrb r3, [r3, #0] - 80026a4: 2b24 cmp r3, #36 @ 0x24 - 80026a6: d103 bne.n 80026b0 - 80026a8: 4924 ldr r1, [pc, #144] @ (800273c ) - 80026aa: 2004 movs r0, #4 - 80026ac: f002 fb30 bl 8004d10 - if(GBT_State == GBT_COMPLETE) EDCAN_printf(LOG_INFO, "GBT_COMPLETE\n"); - 80026b0: 4b05 ldr r3, [pc, #20] @ (80026c8 ) - 80026b2: 781b ldrb r3, [r3, #0] - 80026b4: 2b25 cmp r3, #37 @ 0x25 - 80026b6: d103 bne.n 80026c0 - 80026b8: 4921 ldr r1, [pc, #132] @ (8002740 ) - 80026ba: 2006 movs r0, #6 - 80026bc: f002 fb28 bl 8004d10 - - -} - 80026c0: bf00 nop - 80026c2: 3708 adds r7, #8 - 80026c4: 46bd mov sp, r7 - 80026c6: bd80 pop {r7, pc} - 80026c8: 200002dc .word 0x200002dc - 80026cc: 20003328 .word 0x20003328 - 80026d0: 200002e0 .word 0x200002e0 - 80026d4: 0800d81c .word 0x0800d81c - 80026d8: 0800d82c .word 0x0800d82c - 80026dc: 0800d83c .word 0x0800d83c - 80026e0: 0800d850 .word 0x0800d850 - 80026e4: 0800d860 .word 0x0800d860 - 80026e8: 0800d870 .word 0x0800d870 - 80026ec: 0800d880 .word 0x0800d880 - 80026f0: 0800d890 .word 0x0800d890 - 80026f4: 0800d8a4 .word 0x0800d8a4 - 80026f8: 0800d8b4 .word 0x0800d8b4 - 80026fc: 0800d8c8 .word 0x0800d8c8 - 8002700: 0800d8d4 .word 0x0800d8d4 - 8002704: 0800d8e4 .word 0x0800d8e4 - 8002708: 0800d8f0 .word 0x0800d8f0 - 800270c: 0800d900 .word 0x0800d900 - 8002710: 0800d910 .word 0x0800d910 - 8002714: 0800d920 .word 0x0800d920 - 8002718: 0800d934 .word 0x0800d934 - 800271c: 0800d944 .word 0x0800d944 - 8002720: 0800d958 .word 0x0800d958 - 8002724: 0800d96c .word 0x0800d96c - 8002728: 0800d980 .word 0x0800d980 - 800272c: 0800d998 .word 0x0800d998 - 8002730: 0800d9ac .word 0x0800d9ac - 8002734: 0800d9c0 .word 0x0800d9c0 - 8002738: 0800d9cc .word 0x0800d9cc - 800273c: 0800d9dc .word 0x0800d9dc - 8002740: 0800d9e8 .word 0x0800d9e8 - -08002744 : - -uint32_t GBT_StateTick(){ - 8002744: b580 push {r7, lr} - 8002746: af00 add r7, sp, #0 - return HAL_GetTick() - GBT_state_tick; - 8002748: f003 f874 bl 8005834 - 800274c: 4602 mov r2, r0 - 800274e: 4b02 ldr r3, [pc, #8] @ (8002758 ) - 8002750: 681b ldr r3, [r3, #0] - 8002752: 1ad3 subs r3, r2, r3 -} - 8002754: 4618 mov r0, r3 - 8002756: bd80 pop {r7, pc} - 8002758: 200002e0 .word 0x200002e0 - -0800275c : - -void GBT_Delay(uint32_t delay){ - 800275c: b580 push {r7, lr} - 800275e: b082 sub sp, #8 - 8002760: af00 add r7, sp, #0 - 8002762: 6078 str r0, [r7, #4] - GBT_delay_start = HAL_GetTick(); - 8002764: f003 f866 bl 8005834 - 8002768: 4603 mov r3, r0 - 800276a: 4a04 ldr r2, [pc, #16] @ (800277c ) - 800276c: 6013 str r3, [r2, #0] - GBT_delay = delay; - 800276e: 4a04 ldr r2, [pc, #16] @ (8002780 ) - 8002770: 687b ldr r3, [r7, #4] - 8002772: 6013 str r3, [r2, #0] -} - 8002774: bf00 nop - 8002776: 3708 adds r7, #8 - 8002778: 46bd mov sp, r7 - 800277a: bd80 pop {r7, pc} - 800277c: 200002e4 .word 0x200002e4 - 8002780: 200002e8 .word 0x200002e8 - -08002784 : - -void GBT_Stop(uint32_t causecode){ - 8002784: b580 push {r7, lr} - 8002786: b082 sub sp, #8 - 8002788: af00 add r7, sp, #0 - 800278a: 6078 str r0, [r7, #4] - GBT_StopCauseCode = causecode; - 800278c: 4a06 ldr r2, [pc, #24] @ (80027a8 ) - 800278e: 687b ldr r3, [r7, #4] - 8002790: 6013 str r3, [r2, #0] - if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); - 8002792: 4b06 ldr r3, [pc, #24] @ (80027ac ) - 8002794: 781b ldrb r3, [r3, #0] - 8002796: 2b22 cmp r3, #34 @ 0x22 - 8002798: d002 beq.n 80027a0 - 800279a: 2022 movs r0, #34 @ 0x22 - 800279c: f7ff feae bl 80024fc -} - 80027a0: bf00 nop - 80027a2: 3708 adds r7, #8 - 80027a4: 46bd mov sp, r7 - 80027a6: bd80 pop {r7, pc} - 80027a8: 20000388 .word 0x20000388 - 80027ac: 200002dc .word 0x200002dc - -080027b0 : - -void GBT_Error(uint32_t errorcode){ - 80027b0: b580 push {r7, lr} - 80027b2: b082 sub sp, #8 - 80027b4: af00 add r7, sp, #0 - 80027b6: 6078 str r0, [r7, #4] - EDCAN_printf(LOG_WARN, "GBT Error code: 0x%X\n", errorcode); - 80027b8: 687a ldr r2, [r7, #4] - 80027ba: 4907 ldr r1, [pc, #28] @ (80027d8 ) - 80027bc: 2004 movs r0, #4 - 80027be: f002 faa7 bl 8004d10 - GBT_ErrorCode = errorcode; - 80027c2: 4a06 ldr r2, [pc, #24] @ (80027dc ) - 80027c4: 687b ldr r3, [r7, #4] - 80027c6: 6013 str r3, [r2, #0] - GBT_SwitchState(GBT_ERROR); - 80027c8: 2024 movs r0, #36 @ 0x24 - 80027ca: f7ff fe97 bl 80024fc -} - 80027ce: bf00 nop - 80027d0: 3708 adds r7, #8 - 80027d2: 46bd mov sp, r7 - 80027d4: bd80 pop {r7, pc} - 80027d6: bf00 nop - 80027d8: 0800d9f8 .word 0x0800d9f8 - 80027dc: 2000038c .word 0x2000038c - -080027e0 : - -void GBT_ForceStop(){ - 80027e0: b580 push {r7, lr} - 80027e2: af00 add r7, sp, #0 - GBT_EDCAN_Output.enablePSU = 0; - 80027e4: 4b07 ldr r3, [pc, #28] @ (8002804 ) - 80027e6: 2200 movs r2, #0 - 80027e8: 701a strb r2, [r3, #0] - GBT_SwitchState(GBT_COMPLETE); - 80027ea: 2025 movs r0, #37 @ 0x25 - 80027ec: f7ff fe86 bl 80024fc - GBT_Lock(0); - 80027f0: 2000 movs r0, #0 - 80027f2: f001 fcad bl 8004150 - RELAY_Write(RELAY_AUX, 0); - 80027f6: 2100 movs r1, #0 - 80027f8: 2000 movs r0, #0 - 80027fa: f7fe ff5d bl 80016b8 -} - 80027fe: bf00 nop - 8002800: bd80 pop {r7, pc} - 8002802: bf00 nop - 8002804: 200004a4 .word 0x200004a4 - -08002808 : - -void GBT_Reset(){ - 8002808: b580 push {r7, lr} - 800280a: af00 add r7, sp, #0 - GBT_BAT_INFO_recv = 0; - 800280c: 4b27 ldr r3, [pc, #156] @ (80028ac ) - 800280e: 2200 movs r2, #0 - 8002810: 701a strb r2, [r3, #0] - GBT_BAT_STAT_recv = 0; - 8002812: 4b27 ldr r3, [pc, #156] @ (80028b0 ) - 8002814: 2200 movs r2, #0 - 8002816: 701a strb r2, [r3, #0] - GBT_BRO_recv = 0; - 8002818: 4b26 ldr r3, [pc, #152] @ (80028b4 ) - 800281a: 2200 movs r2, #0 - 800281c: 701a strb r2, [r3, #0] - GBT_BHM_recv = 0; - 800281e: 4b26 ldr r3, [pc, #152] @ (80028b8 ) - 8002820: 2200 movs r2, #0 - 8002822: 701a strb r2, [r3, #0] - GBT_BSD_recv = 0; - 8002824: 4b25 ldr r3, [pc, #148] @ (80028bc ) - 8002826: 2200 movs r2, #0 - 8002828: 701a strb r2, [r3, #0] - EV_ready = 0; - 800282a: 4b25 ldr r3, [pc, #148] @ (80028c0 ) - 800282c: 2200 movs r2, #0 - 800282e: 701a strb r2, [r3, #0] - memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); - 8002830: 2231 movs r2, #49 @ 0x31 - 8002832: 2100 movs r1, #0 - 8002834: 4823 ldr r0, [pc, #140] @ (80028c4 ) - 8002836: f007 fc23 bl 800a080 - memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); - 800283a: 220d movs r2, #13 - 800283c: 2100 movs r1, #0 - 800283e: 4822 ldr r0, [pc, #136] @ (80028c8 ) - 8002840: f007 fc1e bl 800a080 - memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); - 8002844: 2205 movs r2, #5 - 8002846: 2100 movs r1, #0 - 8002848: 4820 ldr r0, [pc, #128] @ (80028cc ) - 800284a: f007 fc19 bl 800a080 - memset(&GBT_CurrPower, 0, sizeof (GBT_CurrPower)); - 800284e: 2205 movs r2, #5 - 8002850: 2100 movs r1, #0 - 8002852: 481f ldr r0, [pc, #124] @ (80028d0 ) - 8002854: f007 fc14 bl 800a080 - memset(&GBT_MaxVoltage, 0, sizeof (GBT_MaxVoltage)); - 8002858: 2202 movs r2, #2 - 800285a: 2100 movs r1, #0 - 800285c: 481d ldr r0, [pc, #116] @ (80028d4 ) - 800285e: f007 fc0f bl 800a080 - memset(&GBT_ChargingStatus, 0, sizeof (GBT_ChargingStatus)); - 8002862: 2209 movs r2, #9 - 8002864: 2100 movs r1, #0 - 8002866: 481c ldr r0, [pc, #112] @ (80028d8 ) - 8002868: f007 fc0a bl 800a080 - memset(&GBT_BatteryStatus, 0, sizeof (GBT_BatteryStatus)); - 800286c: 2207 movs r2, #7 - 800286e: 2100 movs r1, #0 - 8002870: 481a ldr r0, [pc, #104] @ (80028dc ) - 8002872: f007 fc05 bl 800a080 - memset(&GBT_ChargerCurrentStatus, 0, sizeof (GBT_ChargerCurrentStatus)); - 8002876: 2208 movs r2, #8 - 8002878: 2100 movs r1, #0 - 800287a: 4819 ldr r0, [pc, #100] @ (80028e0 ) - 800287c: f007 fc00 bl 800a080 - memset(&GBT_ChargerStop, 0, sizeof (GBT_ChargerStop)); - 8002880: 2208 movs r2, #8 - 8002882: 2100 movs r1, #0 - 8002884: 4817 ldr r0, [pc, #92] @ (80028e4 ) - 8002886: f007 fbfb bl 800a080 - GBT_CurrPower.requestedCurrent = 4000; //0A - 800288a: 4b11 ldr r3, [pc, #68] @ (80028d0 ) - 800288c: f44f 627a mov.w r2, #4000 @ 0xfa0 - 8002890: 805a strh r2, [r3, #2] - GBT_CurrPower.requestedVoltage = 500; //50V - 8002892: 4b0f ldr r3, [pc, #60] @ (80028d0 ) - 8002894: f44f 72fa mov.w r2, #500 @ 0x1f4 - 8002898: 801a strh r2, [r3, #0] - GBT_TimeChargingStarted = 0; - 800289a: 4b13 ldr r3, [pc, #76] @ (80028e8 ) - 800289c: 2200 movs r2, #0 - 800289e: 601a str r2, [r3, #0] - GBT_BRO = 0x00; - 80028a0: 4b12 ldr r3, [pc, #72] @ (80028ec ) - 80028a2: 2200 movs r2, #0 - 80028a4: 701a strb r2, [r3, #0] -} - 80028a6: bf00 nop - 80028a8: bd80 pop {r7, pc} - 80028aa: bf00 nop - 80028ac: 200002ec .word 0x200002ec - 80028b0: 200002ed .word 0x200002ed - 80028b4: 200002ee .word 0x200002ee - 80028b8: 200002ef .word 0x200002ef - 80028bc: 200002f0 .word 0x200002f0 - 80028c0: 200002f1 .word 0x200002f1 - 80028c4: 20000308 .word 0x20000308 - 80028c8: 2000033c .word 0x2000033c - 80028cc: 2000034c .word 0x2000034c - 80028d0: 20000354 .word 0x20000354 - 80028d4: 20000304 .word 0x20000304 - 80028d8: 2000035c .word 0x2000035c - 80028dc: 20000368 .word 0x20000368 - 80028e0: 20000370 .word 0x20000370 - 80028e4: 20000378 .word 0x20000378 - 80028e8: 20000384 .word 0x20000384 - 80028ec: 20000380 .word 0x20000380 - -080028f0 : -void GBT_Start(){ - 80028f0: b580 push {r7, lr} - 80028f2: af00 add r7, sp, #0 - RELAY_Write(RELAY_AUX, 1); - 80028f4: 2101 movs r1, #1 - 80028f6: 2000 movs r0, #0 - 80028f8: f7fe fede bl 80016b8 - GBT_SwitchState(GBT_S3_STARTED); - 80028fc: 2013 movs r0, #19 - 80028fe: f7ff fdfd bl 80024fc -} - 8002902: bf00 nop - 8002904: bd80 pop {r7, pc} - -08002906 : -extern GBT_EDCAN_Output_t GBT_EDCAN_Output; -extern GBT_EDCAN_Input_t GBT_EDCAN_Input; - -uint8_t CC_STATE_FILTERED; - -void CONN_Init(){ - 8002906: b580 push {r7, lr} - 8002908: af00 add r7, sp, #0 - CONN_SetState(CONN_Initializing); - 800290a: 2001 movs r0, #1 - 800290c: f000 f884 bl 8002a18 -} - 8002910: bf00 nop - 8002912: bd80 pop {r7, pc} - -08002914 : - -void CONN_Task(){ - 8002914: b580 push {r7, lr} - 8002916: af00 add r7, sp, #0 - - switch (connectorState){ - 8002918: 4b3b ldr r3, [pc, #236] @ (8002a08 ) - 800291a: 781b ldrb r3, [r3, #0] - 800291c: 3b01 subs r3, #1 - 800291e: 2b05 cmp r3, #5 - 8002920: d864 bhi.n 80029ec - 8002922: a201 add r2, pc, #4 @ (adr r2, 8002928 ) - 8002924: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8002928: 08002941 .word 0x08002941 - 800292c: 08002955 .word 0x08002955 - 8002930: 0800295d .word 0x0800295d - 8002934: 08002989 .word 0x08002989 - 8002938: 080029bf .word 0x080029bf - 800293c: 080029d5 .word 0x080029d5 - case CONN_Initializing: // unlocked - GBT_Lock(0); - 8002940: 2000 movs r0, #0 - 8002942: f001 fc05 bl 8004150 - CONN_SetState(CONN_Available); - 8002946: 2003 movs r0, #3 - 8002948: f000 f866 bl 8002a18 - GBT_LockState.error = 0; - 800294c: 4b2f ldr r3, [pc, #188] @ (8002a0c ) - 800294e: 2200 movs r2, #0 - 8002950: 705a strb r2, [r3, #1] - break; - 8002952: e056 b.n 8002a02 - case CONN_Faulted: //unlocked - GBT_Lock(0); - 8002954: 2000 movs r0, #0 - 8002956: f001 fbfb bl 8004150 - - break; - 800295a: e052 b.n 8002a02 - case CONN_Available: //unlocked, waiting to connect - GBT_Lock(0); - 800295c: 2000 movs r0, #0 - 800295e: f001 fbf7 bl 8004150 - GBT_LockState.error = 0; - 8002962: 4b2a ldr r3, [pc, #168] @ (8002a0c ) - 8002964: 2200 movs r2, #0 - 8002966: 705a strb r2, [r3, #1] - if((CONN_CC_GetState()==GBT_CC_4V) && (GBT_EDCAN_Input.chargeControl != FORCE_UNLOCK)){ // Исправить - 8002968: f000 f8dc bl 8002b24 - 800296c: 4603 mov r3, r0 - 800296e: 2b03 cmp r3, #3 - 8002970: d140 bne.n 80029f4 - 8002972: 4b27 ldr r3, [pc, #156] @ (8002a10 ) - 8002974: 795b ldrb r3, [r3, #5] - 8002976: 2b03 cmp r3, #3 - 8002978: d03c beq.n 80029f4 - CONN_SetState(CONN_Preparing); - 800297a: 2004 movs r0, #4 - 800297c: f000 f84c bl 8002a18 - GBT_Lock(1); - 8002980: 2001 movs r0, #1 - 8002982: f001 fbe5 bl 8004150 - - } - break; - 8002986: e035 b.n 80029f4 - - // Выйти из двух состояний в Finished если force unlock - case CONN_Preparing: //locked, waiting to charge - GBT_Lock(1); - 8002988: 2001 movs r0, #1 - 800298a: f001 fbe1 bl 8004150 - if(CONN_CC_GetState()==GBT_CC_4V){ - 800298e: f000 f8c9 bl 8002b24 - 8002992: 4603 mov r3, r0 - 8002994: 2b03 cmp r3, #3 - 8002996: d10e bne.n 80029b6 - if(GBT_EDCAN_Input.chargeControl == CHARGING_ALLOWED){ - 8002998: 4b1d ldr r3, [pc, #116] @ (8002a10 ) - 800299a: 795b ldrb r3, [r3, #5] - 800299c: 2b02 cmp r3, #2 - 800299e: d102 bne.n 80029a6 -// RELAY_Write(RELAY_AUX, 1); -// GBT_Start(); - CONN_SetState(CONN_Charging); - 80029a0: 2005 movs r0, #5 - 80029a2: f000 f839 bl 8002a18 - } - if(GBT_EDCAN_Input.chargeControl == FORCE_UNLOCK){ - 80029a6: 4b1a ldr r3, [pc, #104] @ (8002a10 ) - 80029a8: 795b ldrb r3, [r3, #5] - 80029aa: 2b03 cmp r3, #3 - 80029ac: d124 bne.n 80029f8 - CONN_SetState(CONN_Available);//TODO: CONN_Occupied_complete - 80029ae: 2003 movs r0, #3 - 80029b0: f000 f832 bl 8002a18 - } - //if (CHARGING_NOT_ALLOWED) stay here - }else{ - CONN_SetState(CONN_Available); - } - break; - 80029b4: e020 b.n 80029f8 - CONN_SetState(CONN_Available); - 80029b6: 2003 movs r0, #3 - 80029b8: f000 f82e bl 8002a18 - break; - 80029bc: e01c b.n 80029f8 - case CONN_Charging://charging, locked - GBT_Lock(1); - 80029be: 2001 movs r0, #1 - 80029c0: f001 fbc6 bl 8004150 - - if(GBT_State == GBT_COMPLETE){ - 80029c4: 4b13 ldr r3, [pc, #76] @ (8002a14 ) - 80029c6: 781b ldrb r3, [r3, #0] - 80029c8: 2b25 cmp r3, #37 @ 0x25 - 80029ca: d117 bne.n 80029fc - CONN_SetState(CONN_Finishing); - 80029cc: 2006 movs r0, #6 - 80029ce: f000 f823 bl 8002a18 - } - // - - break; - 80029d2: e013 b.n 80029fc - case CONN_Finishing://charging completed, waiting to disconnect, unlocked - GBT_Lock(0); - 80029d4: 2000 movs r0, #0 - 80029d6: f001 fbbb bl 8004150 -// RELAY_Write(RELAY_AUX, 0); - //TODO: Reconnection -// if(GBT_EDCAN_Input.chargeControl == CHARGING_NOT_ALLOWED){ -// CONN_SetState(CONN_Initializing); -// } - if(CONN_CC_GetState()==GBT_CC_6V){ - 80029da: f000 f8a3 bl 8002b24 - 80029de: 4603 mov r3, r0 - 80029e0: 2b02 cmp r3, #2 - 80029e2: d10d bne.n 8002a00 - CONN_SetState(CONN_Initializing); - 80029e4: 2001 movs r0, #1 - 80029e6: f000 f817 bl 8002a18 - } - //Проблема, если нажать кнопку и не вынуть пистолет, то он снова блочится - break; - 80029ea: e009 b.n 8002a00 - default: - CONN_SetState(CONN_Initializing); - 80029ec: 2001 movs r0, #1 - 80029ee: f000 f813 bl 8002a18 - - } - - -} - 80029f2: e006 b.n 8002a02 - break; - 80029f4: bf00 nop - 80029f6: e004 b.n 8002a02 - break; - 80029f8: bf00 nop - 80029fa: e002 b.n 8002a02 - break; - 80029fc: bf00 nop - 80029fe: e000 b.n 8002a02 - break; - 8002a00: bf00 nop -} - 8002a02: bf00 nop - 8002a04: bd80 pop {r7, pc} - 8002a06: bf00 nop - 8002a08: 20000390 .word 0x20000390 - 8002a0c: 200005cc .word 0x200005cc - 8002a10: 200004b4 .word 0x200004b4 - 8002a14: 200002dc .word 0x200002dc - -08002a18 : -//external -//CONN_SetState(CONN_Error); -//CONN_SetState(CONN_Occupied_charging); -//CONN_SetState(CONN_Occupied_Complete); - -void CONN_SetState(CONN_State_t state){ - 8002a18: b580 push {r7, lr} - 8002a1a: b082 sub sp, #8 - 8002a1c: af00 add r7, sp, #0 - 8002a1e: 4603 mov r3, r0 - 8002a20: 71fb strb r3, [r7, #7] - connectorState = state; - 8002a22: 4a1a ldr r2, [pc, #104] @ (8002a8c ) - 8002a24: 79fb ldrb r3, [r7, #7] - 8002a26: 7013 strb r3, [r2, #0] - if(connectorState == CONN_Initializing) printf ("CONN_Initializing\n"); - 8002a28: 4b18 ldr r3, [pc, #96] @ (8002a8c ) - 8002a2a: 781b ldrb r3, [r3, #0] - 8002a2c: 2b01 cmp r3, #1 - 8002a2e: d102 bne.n 8002a36 - 8002a30: 4817 ldr r0, [pc, #92] @ (8002a90 ) - 8002a32: f007 fb0b bl 800a04c - if(connectorState == CONN_Faulted) printf ("CONN_Error\n"); - 8002a36: 4b15 ldr r3, [pc, #84] @ (8002a8c ) - 8002a38: 781b ldrb r3, [r3, #0] - 8002a3a: 2b02 cmp r3, #2 - 8002a3c: d102 bne.n 8002a44 - 8002a3e: 4815 ldr r0, [pc, #84] @ (8002a94 ) - 8002a40: f007 fb04 bl 800a04c - if(connectorState == CONN_Available) printf ("CONN_Available\n"); - 8002a44: 4b11 ldr r3, [pc, #68] @ (8002a8c ) - 8002a46: 781b ldrb r3, [r3, #0] - 8002a48: 2b03 cmp r3, #3 - 8002a4a: d102 bne.n 8002a52 - 8002a4c: 4812 ldr r0, [pc, #72] @ (8002a98 ) - 8002a4e: f007 fafd bl 800a04c - if(connectorState == CONN_Preparing) printf ("CONN_Occupied_waiting\n"); - 8002a52: 4b0e ldr r3, [pc, #56] @ (8002a8c ) - 8002a54: 781b ldrb r3, [r3, #0] - 8002a56: 2b04 cmp r3, #4 - 8002a58: d102 bne.n 8002a60 - 8002a5a: 4810 ldr r0, [pc, #64] @ (8002a9c ) - 8002a5c: f007 faf6 bl 800a04c - if(connectorState == CONN_Charging) printf ("CONN_Occupied_charging\n"); - 8002a60: 4b0a ldr r3, [pc, #40] @ (8002a8c ) - 8002a62: 781b ldrb r3, [r3, #0] - 8002a64: 2b05 cmp r3, #5 - 8002a66: d102 bne.n 8002a6e - 8002a68: 480d ldr r0, [pc, #52] @ (8002aa0 ) - 8002a6a: f007 faef bl 800a04c - if(connectorState == CONN_Finishing) printf ("CONN_Occupied_complete\n"); - 8002a6e: 4b07 ldr r3, [pc, #28] @ (8002a8c ) - 8002a70: 781b ldrb r3, [r3, #0] - 8002a72: 2b06 cmp r3, #6 - 8002a74: d102 bne.n 8002a7c - 8002a76: 480b ldr r0, [pc, #44] @ (8002aa4 ) - 8002a78: f007 fae8 bl 800a04c - GBT_EDCAN_Output.connectorState = state; - 8002a7c: 4a0a ldr r2, [pc, #40] @ (8002aa8 ) - 8002a7e: 79fb ldrb r3, [r7, #7] - 8002a80: 7313 strb r3, [r2, #12] -} - 8002a82: bf00 nop - 8002a84: 3708 adds r7, #8 - 8002a86: 46bd mov sp, r7 - 8002a88: bd80 pop {r7, pc} - 8002a8a: bf00 nop - 8002a8c: 20000390 .word 0x20000390 - 8002a90: 0800da10 .word 0x0800da10 - 8002a94: 0800da24 .word 0x0800da24 - 8002a98: 0800da30 .word 0x0800da30 - 8002a9c: 0800da40 .word 0x0800da40 - 8002aa0: 0800da58 .word 0x0800da58 - 8002aa4: 0800da70 .word 0x0800da70 - 8002aa8: 200004a4 .word 0x200004a4 - -08002aac : - -void CONN_CC_ReadStateFiltered() { - 8002aac: b580 push {r7, lr} - 8002aae: b082 sub sp, #8 - 8002ab0: af00 add r7, sp, #0 - static uint32_t last_change_time; - static uint32_t last_check_time; - static uint8_t prev_state; - -// if((last_check_time+100)>HAL_GetTick()) return; - if((HAL_GetTick()-last_check_time)<100) return; - 8002ab2: f002 febf bl 8005834 - 8002ab6: 4602 mov r2, r0 - 8002ab8: 4b16 ldr r3, [pc, #88] @ (8002b14 ) - 8002aba: 681b ldr r3, [r3, #0] - 8002abc: 1ad3 subs r3, r2, r3 - 8002abe: 2b63 cmp r3, #99 @ 0x63 - 8002ac0: d924 bls.n 8002b0c - - last_check_time = HAL_GetTick(); - 8002ac2: f002 feb7 bl 8005834 - 8002ac6: 4603 mov r3, r0 - 8002ac8: 4a12 ldr r2, [pc, #72] @ (8002b14 ) - 8002aca: 6013 str r3, [r2, #0] - - uint8_t new_state = CONN_CC_GetStateRaw(); - 8002acc: f000 f834 bl 8002b38 - 8002ad0: 4603 mov r3, r0 - 8002ad2: 71fb strb r3, [r7, #7] - - if (new_state != prev_state) { - 8002ad4: 4b10 ldr r3, [pc, #64] @ (8002b18 ) - 8002ad6: 781b ldrb r3, [r3, #0] - 8002ad8: 79fa ldrb r2, [r7, #7] - 8002ada: 429a cmp r2, r3 - 8002adc: d008 beq.n 8002af0 - last_change_time = HAL_GetTick(); - 8002ade: f002 fea9 bl 8005834 - 8002ae2: 4603 mov r3, r0 - 8002ae4: 4a0d ldr r2, [pc, #52] @ (8002b1c ) - 8002ae6: 6013 str r3, [r2, #0] - prev_state = new_state; - 8002ae8: 4a0b ldr r2, [pc, #44] @ (8002b18 ) - 8002aea: 79fb ldrb r3, [r7, #7] - 8002aec: 7013 strb r3, [r2, #0] - 8002aee: e00e b.n 8002b0e - } else if ((HAL_GetTick() - last_change_time) >= 300) { - 8002af0: f002 fea0 bl 8005834 - 8002af4: 4602 mov r2, r0 - 8002af6: 4b09 ldr r3, [pc, #36] @ (8002b1c ) - 8002af8: 681b ldr r3, [r3, #0] - 8002afa: 1ad3 subs r3, r2, r3 - 8002afc: f5b3 7f96 cmp.w r3, #300 @ 0x12c - 8002b00: d305 bcc.n 8002b0e - CC_STATE_FILTERED = prev_state; - 8002b02: 4b05 ldr r3, [pc, #20] @ (8002b18 ) - 8002b04: 781a ldrb r2, [r3, #0] - 8002b06: 4b06 ldr r3, [pc, #24] @ (8002b20 ) - 8002b08: 701a strb r2, [r3, #0] - 8002b0a: e000 b.n 8002b0e - if((HAL_GetTick()-last_check_time)<100) return; - 8002b0c: bf00 nop -// case GBT_CC_2V: -// printf("FGBT_CC_2V\n"); -// break; -// -// } -} - 8002b0e: 3708 adds r7, #8 - 8002b10: 46bd mov sp, r7 - 8002b12: bd80 pop {r7, pc} - 8002b14: 20000394 .word 0x20000394 - 8002b18: 20000398 .word 0x20000398 - 8002b1c: 2000039c .word 0x2000039c - 8002b20: 20000391 .word 0x20000391 - -08002b24 : - -uint8_t CONN_CC_GetState(){ - 8002b24: b480 push {r7} - 8002b26: af00 add r7, sp, #0 - return CC_STATE_FILTERED; - 8002b28: 4b02 ldr r3, [pc, #8] @ (8002b34 ) - 8002b2a: 781b ldrb r3, [r3, #0] -} - 8002b2c: 4618 mov r0, r3 - 8002b2e: 46bd mov sp, r7 - 8002b30: bc80 pop {r7} - 8002b32: 4770 bx lr - 8002b34: 20000391 .word 0x20000391 - -08002b38 : -uint8_t CONN_CC_GetStateRaw(){ - 8002b38: b580 push {r7, lr} - 8002b3a: b082 sub sp, #8 - 8002b3c: af00 add r7, sp, #0 - //Vin*k= 1.09v - //12vin = 1353 ADC -//TODO: Filter 100ms - uint32_t adc; - float volt; - ADC_Select_Channel(ADC_CHANNEL_6); - 8002b3e: 2006 movs r0, #6 - 8002b40: f7fe fea2 bl 8001888 - HAL_ADC_Start(&hadc1); - 8002b44: 482e ldr r0, [pc, #184] @ (8002c00 ) - 8002b46: f002 ff7b bl 8005a40 - HAL_ADC_PollForConversion(&hadc1, 100); - 8002b4a: 2164 movs r1, #100 @ 0x64 - 8002b4c: 482c ldr r0, [pc, #176] @ (8002c00 ) - 8002b4e: f003 f851 bl 8005bf4 - adc = HAL_ADC_GetValue(&hadc1); - 8002b52: 482b ldr r0, [pc, #172] @ (8002c00 ) - 8002b54: f003 f954 bl 8005e00 - 8002b58: 6078 str r0, [r7, #4] - HAL_ADC_Stop(&hadc1); - 8002b5a: 4829 ldr r0, [pc, #164] @ (8002c00 ) - 8002b5c: f003 f81e bl 8005b9c - - volt = (float)adc/113.4f; - 8002b60: 6878 ldr r0, [r7, #4] - 8002b62: f7fe f90d bl 8000d80 <__aeabi_ui2f> - 8002b66: 4603 mov r3, r0 - 8002b68: 4926 ldr r1, [pc, #152] @ (8002c04 ) - 8002b6a: 4618 mov r0, r3 - 8002b6c: f7fe fa14 bl 8000f98 <__aeabi_fdiv> - 8002b70: 4603 mov r3, r0 - 8002b72: 603b str r3, [r7, #0] -// if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; -// if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; -// if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; -// if((volt<2.8f) && (volt>1.2f)) return GBT_CC_2V; - if((volt<13.0f) && (volt>11.0f)) return GBT_CC_12V; - 8002b74: 4924 ldr r1, [pc, #144] @ (8002c08 ) - 8002b76: 6838 ldr r0, [r7, #0] - 8002b78: f7fe faf8 bl 800116c <__aeabi_fcmplt> - 8002b7c: 4603 mov r3, r0 - 8002b7e: 2b00 cmp r3, #0 - 8002b80: d008 beq.n 8002b94 - 8002b82: 4922 ldr r1, [pc, #136] @ (8002c0c ) - 8002b84: 6838 ldr r0, [r7, #0] - 8002b86: f7fe fb0f bl 80011a8 <__aeabi_fcmpgt> - 8002b8a: 4603 mov r3, r0 - 8002b8c: 2b00 cmp r3, #0 - 8002b8e: d001 beq.n 8002b94 - 8002b90: 2301 movs r3, #1 - 8002b92: e031 b.n 8002bf8 - if((volt<7.2f) && (volt>4.8f)) return GBT_CC_6V; - 8002b94: 491e ldr r1, [pc, #120] @ (8002c10 ) - 8002b96: 6838 ldr r0, [r7, #0] - 8002b98: f7fe fae8 bl 800116c <__aeabi_fcmplt> - 8002b9c: 4603 mov r3, r0 - 8002b9e: 2b00 cmp r3, #0 - 8002ba0: d008 beq.n 8002bb4 - 8002ba2: 491c ldr r1, [pc, #112] @ (8002c14 ) - 8002ba4: 6838 ldr r0, [r7, #0] - 8002ba6: f7fe faff bl 80011a8 <__aeabi_fcmpgt> - 8002baa: 4603 mov r3, r0 - 8002bac: 2b00 cmp r3, #0 - 8002bae: d001 beq.n 8002bb4 - 8002bb0: 2302 movs r3, #2 - 8002bb2: e021 b.n 8002bf8 - if((volt<4.8f) && (volt>3.0f)) return GBT_CC_4V; - 8002bb4: 4917 ldr r1, [pc, #92] @ (8002c14 ) - 8002bb6: 6838 ldr r0, [r7, #0] - 8002bb8: f7fe fad8 bl 800116c <__aeabi_fcmplt> - 8002bbc: 4603 mov r3, r0 - 8002bbe: 2b00 cmp r3, #0 - 8002bc0: d008 beq.n 8002bd4 - 8002bc2: 4915 ldr r1, [pc, #84] @ (8002c18 ) - 8002bc4: 6838 ldr r0, [r7, #0] - 8002bc6: f7fe faef bl 80011a8 <__aeabi_fcmpgt> - 8002bca: 4603 mov r3, r0 - 8002bcc: 2b00 cmp r3, #0 - 8002bce: d001 beq.n 8002bd4 - 8002bd0: 2303 movs r3, #3 - 8002bd2: e011 b.n 8002bf8 - if((volt<3.0f) && (volt>1.0f)) return GBT_CC_2V; - 8002bd4: 4910 ldr r1, [pc, #64] @ (8002c18 ) - 8002bd6: 6838 ldr r0, [r7, #0] - 8002bd8: f7fe fac8 bl 800116c <__aeabi_fcmplt> - 8002bdc: 4603 mov r3, r0 - 8002bde: 2b00 cmp r3, #0 - 8002be0: d009 beq.n 8002bf6 - 8002be2: f04f 517e mov.w r1, #1065353216 @ 0x3f800000 - 8002be6: 6838 ldr r0, [r7, #0] - 8002be8: f7fe fade bl 80011a8 <__aeabi_fcmpgt> - 8002bec: 4603 mov r3, r0 - 8002bee: 2b00 cmp r3, #0 - 8002bf0: d001 beq.n 8002bf6 - 8002bf2: 2304 movs r3, #4 - 8002bf4: e000 b.n 8002bf8 - return GBT_CC_UNKNOWN; - 8002bf6: 2300 movs r3, #0 -} - 8002bf8: 4618 mov r0, r3 - 8002bfa: 3708 adds r7, #8 - 8002bfc: 46bd mov sp, r7 - 8002bfe: bd80 pop {r7, pc} - 8002c00: 20000258 .word 0x20000258 - 8002c04: 42e2cccd .word 0x42e2cccd - 8002c08: 41500000 .word 0x41500000 - 8002c0c: 41300000 .word 0x41300000 - 8002c10: 40e66666 .word 0x40e66666 - 8002c14: 4099999a .word 0x4099999a - 8002c18: 40400000 .word 0x40400000 - -08002c1c : - -float CONN_CC_GetAdc(){ - 8002c1c: b580 push {r7, lr} - 8002c1e: b082 sub sp, #8 - 8002c20: af00 add r7, sp, #0 - //Vin*k= 1.09v - //12vin = 1353 ADC - - uint32_t adc; - float volt; - ADC_Select_Channel(ADC_CHANNEL_6); - 8002c22: 2006 movs r0, #6 - 8002c24: f7fe fe30 bl 8001888 - HAL_ADC_Start(&hadc1); - 8002c28: 480e ldr r0, [pc, #56] @ (8002c64 ) - 8002c2a: f002 ff09 bl 8005a40 - HAL_ADC_PollForConversion(&hadc1, 100); - 8002c2e: 2164 movs r1, #100 @ 0x64 - 8002c30: 480c ldr r0, [pc, #48] @ (8002c64 ) - 8002c32: f002 ffdf bl 8005bf4 - adc = HAL_ADC_GetValue(&hadc1); - 8002c36: 480b ldr r0, [pc, #44] @ (8002c64 ) - 8002c38: f003 f8e2 bl 8005e00 - 8002c3c: 6078 str r0, [r7, #4] - HAL_ADC_Stop(&hadc1); - 8002c3e: 4809 ldr r0, [pc, #36] @ (8002c64 ) - 8002c40: f002 ffac bl 8005b9c - - volt = (float)adc/113.4f; - 8002c44: 6878 ldr r0, [r7, #4] - 8002c46: f7fe f89b bl 8000d80 <__aeabi_ui2f> - 8002c4a: 4603 mov r3, r0 - 8002c4c: 4906 ldr r1, [pc, #24] @ (8002c68 ) - 8002c4e: 4618 mov r0, r3 - 8002c50: f7fe f9a2 bl 8000f98 <__aeabi_fdiv> - 8002c54: 4603 mov r3, r0 - 8002c56: 603b str r3, [r7, #0] - - return volt; - 8002c58: 683b ldr r3, [r7, #0] -} - 8002c5a: 4618 mov r0, r3 - 8002c5c: 3708 adds r7, #8 - 8002c5e: 46bd mov sp, r7 - 8002c60: bd80 pop {r7, pc} - 8002c62: bf00 nop - 8002c64: 20000258 .word 0x20000258 - 8002c68: 42e2cccd .word 0x42e2cccd - -08002c6c <__NVIC_SystemReset>: -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - 8002c6c: b480 push {r7} - 8002c6e: af00 add r7, sp, #0 - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); - 8002c70: f3bf 8f4f dsb sy -} - 8002c74: bf00 nop - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - 8002c76: 4b06 ldr r3, [pc, #24] @ (8002c90 <__NVIC_SystemReset+0x24>) - 8002c78: 68db ldr r3, [r3, #12] - 8002c7a: f403 62e0 and.w r2, r3, #1792 @ 0x700 - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8002c7e: 4904 ldr r1, [pc, #16] @ (8002c90 <__NVIC_SystemReset+0x24>) - 8002c80: 4b04 ldr r3, [pc, #16] @ (8002c94 <__NVIC_SystemReset+0x28>) - 8002c82: 4313 orrs r3, r2 - 8002c84: 60cb str r3, [r1, #12] - __ASM volatile ("dsb 0xF":::"memory"); - 8002c86: f3bf 8f4f dsb sy -} - 8002c8a: bf00 nop - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - 8002c8c: bf00 nop - 8002c8e: e7fd b.n 8002c8c <__NVIC_SystemReset+0x20> - 8002c90: e000ed00 .word 0xe000ed00 - 8002c94: 05fa0004 .word 0x05fa0004 - -08002c98 <_write>: - -extern UART_HandleTypeDef huart2; - -#if defined(__GNUC__) -int _write(int fd, char * ptr, int len) -{ - 8002c98: b580 push {r7, lr} - 8002c9a: b084 sub sp, #16 - 8002c9c: af00 add r7, sp, #0 - 8002c9e: 60f8 str r0, [r7, #12] - 8002ca0: 60b9 str r1, [r7, #8] - 8002ca2: 607a str r2, [r7, #4] - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 1); - 8002ca4: 2201 movs r2, #1 - 8002ca6: 2110 movs r1, #16 - 8002ca8: 480a ldr r0, [pc, #40] @ (8002cd4 <_write+0x3c>) - 8002caa: f004 fd8c bl 80077c6 - HAL_UART_Transmit(&huart2, (uint8_t *) ptr, len, HAL_MAX_DELAY); - 8002cae: 687b ldr r3, [r7, #4] - 8002cb0: b29a uxth r2, r3 - 8002cb2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 8002cb6: 68b9 ldr r1, [r7, #8] - 8002cb8: 4807 ldr r0, [pc, #28] @ (8002cd8 <_write+0x40>) - 8002cba: f005 fecb bl 8008a54 - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, 0); - 8002cbe: 2200 movs r2, #0 - 8002cc0: 2110 movs r1, #16 - 8002cc2: 4804 ldr r0, [pc, #16] @ (8002cd4 <_write+0x3c>) - 8002cc4: f004 fd7f bl 80077c6 - return len; - 8002cc8: 687b ldr r3, [r7, #4] -} - 8002cca: 4618 mov r0, r3 - 8002ccc: 3710 adds r7, #16 - 8002cce: 46bd mov sp, r7 - 8002cd0: bd80 pop {r7, pc} - 8002cd2: bf00 nop - 8002cd4: 40011400 .word 0x40011400 - 8002cd8: 20003354 .word 0x20003354 - -08002cdc : -#endif - -void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size){ - 8002cdc: b580 push {r7, lr} - 8002cde: b082 sub sp, #8 - 8002ce0: af00 add r7, sp, #0 - 8002ce2: 6078 str r0, [r7, #4] - 8002ce4: 460b mov r3, r1 - 8002ce6: 807b strh r3, [r7, #2] - -// if(huart->Instance == USART1){ -// mm_rx_interrupt(huart, Size); -// } - if(huart->Instance == USART2){ - 8002ce8: 687b ldr r3, [r7, #4] - 8002cea: 681b ldr r3, [r3, #0] - 8002cec: 4a05 ldr r2, [pc, #20] @ (8002d04 ) - 8002cee: 4293 cmp r3, r2 - 8002cf0: d104 bne.n 8002cfc - debug_rx_interrupt(huart, Size); - 8002cf2: 887b ldrh r3, [r7, #2] - 8002cf4: 4619 mov r1, r3 - 8002cf6: 6878 ldr r0, [r7, #4] - 8002cf8: f000 f806 bl 8002d08 - } -} - 8002cfc: bf00 nop - 8002cfe: 3708 adds r7, #8 - 8002d00: 46bd mov sp, r7 - 8002d02: bd80 pop {r7, pc} - 8002d04: 40004400 .word 0x40004400 - -08002d08 : - -void debug_rx_interrupt(UART_HandleTypeDef *huart, uint16_t Size){ - 8002d08: b480 push {r7} - 8002d0a: b083 sub sp, #12 - 8002d0c: af00 add r7, sp, #0 - 8002d0e: 6078 str r0, [r7, #4] - 8002d10: 460b mov r3, r1 - 8002d12: 807b strh r3, [r7, #2] - debug_rx_buffer[Size] = '\0'; - 8002d14: 887b ldrh r3, [r7, #2] - 8002d16: 4a07 ldr r2, [pc, #28] @ (8002d34 ) - 8002d18: 2100 movs r1, #0 - 8002d1a: 54d1 strb r1, [r2, r3] - debug_rx_buffer_size = Size; - 8002d1c: 887b ldrh r3, [r7, #2] - 8002d1e: b2da uxtb r2, r3 - 8002d20: 4b05 ldr r3, [pc, #20] @ (8002d38 ) - 8002d22: 701a strb r2, [r3, #0] - debug_cmd_received = 1; - 8002d24: 4b05 ldr r3, [pc, #20] @ (8002d3c ) - 8002d26: 2201 movs r2, #1 - 8002d28: 701a strb r2, [r3, #0] -} - 8002d2a: bf00 nop - 8002d2c: 370c adds r7, #12 - 8002d2e: 46bd mov sp, r7 - 8002d30: bc80 pop {r7} - 8002d32: 4770 bx lr - 8002d34: 200003a0 .word 0x200003a0 - 8002d38: 200004a1 .word 0x200004a1 - 8002d3c: 200004a0 .word 0x200004a0 - -08002d40 : - -void debug_init(){ - 8002d40: b580 push {r7, lr} - 8002d42: af00 add r7, sp, #0 - HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); - 8002d44: 22ff movs r2, #255 @ 0xff - 8002d46: 4903 ldr r1, [pc, #12] @ (8002d54 ) - 8002d48: 4803 ldr r0, [pc, #12] @ (8002d58 ) - 8002d4a: f005 ff15 bl 8008b78 - // mm_schedule_write(0x02, 0x00FF, 0xFFFF); - //for (int i=0;i<60;i++) - // mm_schedule_write(0x02, 0x0000, 0xFF00); - // mm_schedule_write(0x01, 0x0000, 0x0100); - // mm_schedule_write(0x01, 0x0000, 0x0100); -} - 8002d4e: bf00 nop - 8002d50: bd80 pop {r7, pc} - 8002d52: bf00 nop - 8002d54: 200003a0 .word 0x200003a0 - 8002d58: 20003354 .word 0x20003354 - -08002d5c : - -void parse_command(uint8_t* buffer, size_t length) { - 8002d5c: b5b0 push {r4, r5, r7, lr} - 8002d5e: b086 sub sp, #24 - 8002d60: af00 add r7, sp, #0 - 8002d62: 6078 str r0, [r7, #4] - 8002d64: 6039 str r1, [r7, #0] - // ignore \r \n symbols - size_t i = 0; - 8002d66: 2300 movs r3, #0 - 8002d68: 617b str r3, [r7, #20] - for (i = 0; i < length; i++) { - 8002d6a: 2300 movs r3, #0 - 8002d6c: 617b str r3, [r7, #20] - 8002d6e: e016 b.n 8002d9e - if (buffer[i] == '\r' || buffer[i] == '\n') { - 8002d70: 687a ldr r2, [r7, #4] - 8002d72: 697b ldr r3, [r7, #20] - 8002d74: 4413 add r3, r2 - 8002d76: 781b ldrb r3, [r3, #0] - 8002d78: 2b0d cmp r3, #13 - 8002d7a: d005 beq.n 8002d88 - 8002d7c: 687a ldr r2, [r7, #4] - 8002d7e: 697b ldr r3, [r7, #20] - 8002d80: 4413 add r3, r2 - 8002d82: 781b ldrb r3, [r3, #0] - 8002d84: 2b0a cmp r3, #10 - 8002d86: d107 bne.n 8002d98 - buffer[i] = '\0'; - 8002d88: 687a ldr r2, [r7, #4] - 8002d8a: 697b ldr r3, [r7, #20] - 8002d8c: 4413 add r3, r2 - 8002d8e: 2200 movs r2, #0 - 8002d90: 701a strb r2, [r3, #0] - length = i; - 8002d92: 697b ldr r3, [r7, #20] - 8002d94: 603b str r3, [r7, #0] - break; - 8002d96: e006 b.n 8002da6 - for (i = 0; i < length; i++) { - 8002d98: 697b ldr r3, [r7, #20] - 8002d9a: 3301 adds r3, #1 - 8002d9c: 617b str r3, [r7, #20] - 8002d9e: 697a ldr r2, [r7, #20] - 8002da0: 683b ldr r3, [r7, #0] - 8002da2: 429a cmp r2, r3 - 8002da4: d3e4 bcc.n 8002d70 - } - } - if (buffer[0] == 0) return; - 8002da6: 687b ldr r3, [r7, #4] - 8002da8: 781b ldrb r3, [r3, #0] - 8002daa: 2b00 cmp r3, #0 - 8002dac: f000 82d4 beq.w 8003358 - if (strncmp((const char*)buffer, "reset", length) == 0) { - 8002db0: 683a ldr r2, [r7, #0] - 8002db2: 49ad ldr r1, [pc, #692] @ (8003068 ) - 8002db4: 6878 ldr r0, [r7, #4] - 8002db6: f007 f951 bl 800a05c - 8002dba: 4603 mov r3, r0 - 8002dbc: 2b00 cmp r3, #0 - 8002dbe: d104 bne.n 8002dca - printf("Resetting...\n"); - 8002dc0: 48aa ldr r0, [pc, #680] @ (800306c ) - 8002dc2: f007 f943 bl 800a04c - NVIC_SystemReset(); - 8002dc6: f7ff ff51 bl 8002c6c <__NVIC_SystemReset> - - } else if (strncmp((const char*)buffer, "relayaux", length) == 0) { - 8002dca: 683a ldr r2, [r7, #0] - 8002dcc: 49a8 ldr r1, [pc, #672] @ (8003070 ) - 8002dce: 6878 ldr r0, [r7, #4] - 8002dd0: f007 f944 bl 800a05c - 8002dd4: 4603 mov r3, r0 - 8002dd6: 2b00 cmp r3, #0 - 8002dd8: d10e bne.n 8002df8 - printf("Relaying...\n"); - 8002dda: 48a6 ldr r0, [pc, #664] @ (8003074 ) - 8002ddc: f007 f936 bl 800a04c - RELAY_Write(RELAY_AUX, 1); - 8002de0: 2101 movs r1, #1 - 8002de2: 2000 movs r0, #0 - 8002de4: f7fe fc68 bl 80016b8 - HAL_Delay(200); - 8002de8: 20c8 movs r0, #200 @ 0xc8 - 8002dea: f002 fd2d bl 8005848 - RELAY_Write(RELAY_AUX, 0); - 8002dee: 2100 movs r1, #0 - 8002df0: 2000 movs r0, #0 - 8002df2: f7fe fc61 bl 80016b8 - 8002df6: e2b0 b.n 800335a - } else if (strncmp((const char*)buffer, "relaycc", length) == 0) { - 8002df8: 683a ldr r2, [r7, #0] - 8002dfa: 499f ldr r1, [pc, #636] @ (8003078 ) - 8002dfc: 6878 ldr r0, [r7, #4] - 8002dfe: f007 f92d bl 800a05c - 8002e02: 4603 mov r3, r0 - 8002e04: 2b00 cmp r3, #0 - 8002e06: d10e bne.n 8002e26 - printf("Relaying...\n"); - 8002e08: 489a ldr r0, [pc, #616] @ (8003074 ) - 8002e0a: f007 f91f bl 800a04c - RELAY_Write(RELAY_CC, 1); - 8002e0e: 2101 movs r1, #1 - 8002e10: 2001 movs r0, #1 - 8002e12: f7fe fc51 bl 80016b8 - HAL_Delay(200); - 8002e16: 20c8 movs r0, #200 @ 0xc8 - 8002e18: f002 fd16 bl 8005848 - RELAY_Write(RELAY_CC, 0); - 8002e1c: 2100 movs r1, #0 - 8002e1e: 2001 movs r0, #1 - 8002e20: f7fe fc4a bl 80016b8 - 8002e24: e299 b.n 800335a - -// } else if (strncmp((const char*)buffer, "voltage", length) == 0) { -// printf("Voltaging...\n"); -// mm_schedule_read(0x02, 0x0001); - - } else if (strncmp((const char*)buffer, "adc", length) == 0) { - 8002e26: 683a ldr r2, [r7, #0] - 8002e28: 4994 ldr r1, [pc, #592] @ (800307c ) - 8002e2a: 6878 ldr r0, [r7, #4] - 8002e2c: f007 f916 bl 800a05c - 8002e30: 4603 mov r3, r0 - 8002e32: 2b00 cmp r3, #0 - 8002e34: d10b bne.n 8002e4e - printf("CC1=%.2f\n", CONN_CC_GetAdc()); - 8002e36: f7ff fef1 bl 8002c1c - 8002e3a: 4603 mov r3, r0 - 8002e3c: 4618 mov r0, r3 - 8002e3e: f7fd fb69 bl 8000514 <__aeabi_f2d> - 8002e42: 4602 mov r2, r0 - 8002e44: 460b mov r3, r1 - 8002e46: 488e ldr r0, [pc, #568] @ (8003080 ) - 8002e48: f007 f898 bl 8009f7c - 8002e4c: e285 b.n 800335a - - } else if (strncmp((const char*)buffer, "lock_state", length) == 0) { - 8002e4e: 683a ldr r2, [r7, #0] - 8002e50: 498c ldr r1, [pc, #560] @ (8003084 ) - 8002e52: 6878 ldr r0, [r7, #4] - 8002e54: f007 f902 bl 800a05c - 8002e58: 4603 mov r3, r0 - 8002e5a: 2b00 cmp r3, #0 - 8002e5c: d107 bne.n 8002e6e - printf("Lock state=%d\n", GBT_LockGetState()); - 8002e5e: f001 f959 bl 8004114 - 8002e62: 4603 mov r3, r0 - 8002e64: 4619 mov r1, r3 - 8002e66: 4888 ldr r0, [pc, #544] @ (8003088 ) - 8002e68: f007 f888 bl 8009f7c - 8002e6c: e275 b.n 800335a - - } else if (strncmp((const char*)buffer, "lock_lock", length) == 0) { - 8002e6e: 683a ldr r2, [r7, #0] - 8002e70: 4986 ldr r1, [pc, #536] @ (800308c ) - 8002e72: 6878 ldr r0, [r7, #4] - 8002e74: f007 f8f2 bl 800a05c - 8002e78: 4603 mov r3, r0 - 8002e7a: 2b00 cmp r3, #0 - 8002e7c: d106 bne.n 8002e8c - printf("Locked\n"); - 8002e7e: 4884 ldr r0, [pc, #528] @ (8003090 ) - 8002e80: f007 f8e4 bl 800a04c - GBT_Lock(1); - 8002e84: 2001 movs r0, #1 - 8002e86: f001 f963 bl 8004150 - 8002e8a: e266 b.n 800335a - - } else if (strncmp((const char*)buffer, "lock_unlock", length) == 0) { - 8002e8c: 683a ldr r2, [r7, #0] - 8002e8e: 4981 ldr r1, [pc, #516] @ (8003094 ) - 8002e90: 6878 ldr r0, [r7, #4] - 8002e92: f007 f8e3 bl 800a05c - 8002e96: 4603 mov r3, r0 - 8002e98: 2b00 cmp r3, #0 - 8002e9a: d106 bne.n 8002eaa - printf("Unlocked\n"); - 8002e9c: 487e ldr r0, [pc, #504] @ (8003098 ) - 8002e9e: f007 f8d5 bl 800a04c - GBT_Lock(0); - 8002ea2: 2000 movs r0, #0 - 8002ea4: f001 f954 bl 8004150 - 8002ea8: e257 b.n 800335a - - } else if (strncmp((const char*)buffer, "complete", length) == 0) { - 8002eaa: 683a ldr r2, [r7, #0] - 8002eac: 497b ldr r1, [pc, #492] @ (800309c ) - 8002eae: 6878 ldr r0, [r7, #4] - 8002eb0: f007 f8d4 bl 800a05c - 8002eb4: 4603 mov r3, r0 - 8002eb6: 2b00 cmp r3, #0 - 8002eb8: d103 bne.n 8002ec2 - CONN_SetState(CONN_Finishing); - 8002eba: 2006 movs r0, #6 - 8002ebc: f7ff fdac bl 8002a18 - 8002ec0: e24b b.n 800335a - - } else if (strncmp((const char*)buffer, "start", length) == 0) { - 8002ec2: 683a ldr r2, [r7, #0] - 8002ec4: 4976 ldr r1, [pc, #472] @ (80030a0 ) - 8002ec6: 6878 ldr r0, [r7, #4] - 8002ec8: f007 f8c8 bl 800a05c - 8002ecc: 4603 mov r3, r0 - 8002ece: 2b00 cmp r3, #0 - 8002ed0: d105 bne.n 8002ede - printf("Started\n"); - 8002ed2: 4874 ldr r0, [pc, #464] @ (80030a4 ) - 8002ed4: f007 f8ba bl 800a04c - GBT_Start(); - 8002ed8: f7ff fd0a bl 80028f0 - 8002edc: e23d b.n 800335a - - } else if (strncmp((const char*)buffer, "stop", length) == 0) { - 8002ede: 683a ldr r2, [r7, #0] - 8002ee0: 4971 ldr r1, [pc, #452] @ (80030a8 ) - 8002ee2: 6878 ldr r0, [r7, #4] - 8002ee4: f007 f8ba bl 800a05c - 8002ee8: 4603 mov r3, r0 - 8002eea: 2b00 cmp r3, #0 - 8002eec: d106 bne.n 8002efc - printf("Stopped\n"); - 8002eee: 486f ldr r0, [pc, #444] @ (80030ac ) - 8002ef0: f007 f8ac bl 800a04c - GBT_Stop(GBT_CST_SUSPENDS_ARTIFICIALLY); - 8002ef4: 486e ldr r0, [pc, #440] @ (80030b0 ) - 8002ef6: f7ff fc45 bl 8002784 - 8002efa: e22e b.n 800335a - - } else if (strncmp((const char*)buffer, "stop1", length) == 0) { - 8002efc: 683a ldr r2, [r7, #0] - 8002efe: 496d ldr r1, [pc, #436] @ (80030b4 ) - 8002f00: 6878 ldr r0, [r7, #4] - 8002f02: f007 f8ab bl 800a05c - 8002f06: 4603 mov r3, r0 - 8002f08: 2b00 cmp r3, #0 - 8002f0a: d105 bne.n 8002f18 - printf("Stopped\n"); - 8002f0c: 4867 ldr r0, [pc, #412] @ (80030ac ) - 8002f0e: f007 f89d bl 800a04c - GBT_ForceStop(); - 8002f12: f7ff fc65 bl 80027e0 - 8002f16: e220 b.n 800335a -// printf("Stopped\n"); -// GBT_Lock(1); -// GBT_SwitchState(GBT_S2_LOCKED); -// GBT_Delay(500); - - } else if (strncmp((const char*)buffer, "cc_state", length) == 0) { - 8002f18: 683a ldr r2, [r7, #0] - 8002f1a: 4967 ldr r1, [pc, #412] @ (80030b8 ) - 8002f1c: 6878 ldr r0, [r7, #4] - 8002f1e: f007 f89d bl 800a05c - 8002f22: 4603 mov r3, r0 - 8002f24: 2b00 cmp r3, #0 - 8002f26: d127 bne.n 8002f78 - switch(CONN_CC_GetState()){ - 8002f28: f7ff fdfc bl 8002b24 - 8002f2c: 4603 mov r3, r0 - 8002f2e: 2b04 cmp r3, #4 - 8002f30: f200 8213 bhi.w 800335a - 8002f34: a201 add r2, pc, #4 @ (adr r2, 8002f3c ) - 8002f36: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8002f3a: bf00 nop - 8002f3c: 08002f51 .word 0x08002f51 - 8002f40: 08002f59 .word 0x08002f59 - 8002f44: 08002f61 .word 0x08002f61 - 8002f48: 08002f69 .word 0x08002f69 - 8002f4c: 08002f71 .word 0x08002f71 - case GBT_CC_UNKNOWN: - printf("GBT_CC_UNKNOWN\n"); - 8002f50: 485a ldr r0, [pc, #360] @ (80030bc ) - 8002f52: f007 f87b bl 800a04c - break; - 8002f56: e200 b.n 800335a - case GBT_CC_12V: - printf("GBT_CC_12V\n"); - 8002f58: 4859 ldr r0, [pc, #356] @ (80030c0 ) - 8002f5a: f007 f877 bl 800a04c - break; - 8002f5e: e1fc b.n 800335a - case GBT_CC_6V: - printf("GBT_CC_6V\n"); - 8002f60: 4858 ldr r0, [pc, #352] @ (80030c4 ) - 8002f62: f007 f873 bl 800a04c - break; - 8002f66: e1f8 b.n 800335a - case GBT_CC_4V: - printf("GBT_CC_4V\n"); - 8002f68: 4857 ldr r0, [pc, #348] @ (80030c8 ) - 8002f6a: f007 f86f bl 800a04c - break; - 8002f6e: e1f4 b.n 800335a - case GBT_CC_2V: - printf("GBT_CC_2V\n"); - 8002f70: 4856 ldr r0, [pc, #344] @ (80030cc ) - 8002f72: f007 f86b bl 800a04c - break; - 8002f76: e1f0 b.n 800335a - - } - } else if (strncmp((const char*)buffer, "temp", length) == 0) { - 8002f78: 683a ldr r2, [r7, #0] - 8002f7a: 4955 ldr r1, [pc, #340] @ (80030d0 ) - 8002f7c: 6878 ldr r0, [r7, #4] - 8002f7e: f007 f86d bl 800a05c - 8002f82: 4603 mov r3, r0 - 8002f84: 2b00 cmp r3, #0 - 8002f86: d110 bne.n 8002faa - printf("temp1 %d\n",GBT_ReadTemp(0)); - 8002f88: 2000 movs r0, #0 - 8002f8a: f7fe fc37 bl 80017fc - 8002f8e: 4603 mov r3, r0 - 8002f90: 4619 mov r1, r3 - 8002f92: 4850 ldr r0, [pc, #320] @ (80030d4 ) - 8002f94: f006 fff2 bl 8009f7c - printf("temp2 %d\n",GBT_ReadTemp(1)); - 8002f98: 2001 movs r0, #1 - 8002f9a: f7fe fc2f bl 80017fc - 8002f9e: 4603 mov r3, r0 - 8002fa0: 4619 mov r1, r3 - 8002fa2: 484d ldr r0, [pc, #308] @ (80030d8 ) - 8002fa4: f006 ffea bl 8009f7c - 8002fa8: e1d7 b.n 800335a - } else if (strncmp((const char*)buffer, "info1", length) == 0) { - 8002faa: 683a ldr r2, [r7, #0] - 8002fac: 494b ldr r1, [pc, #300] @ (80030dc ) - 8002fae: 6878 ldr r0, [r7, #4] - 8002fb0: f007 f854 bl 800a05c - 8002fb4: 4603 mov r3, r0 - 8002fb6: 2b00 cmp r3, #0 - 8002fb8: f040 80a6 bne.w 8003108 - printf("Battery info:\n"); - 8002fbc: 4848 ldr r0, [pc, #288] @ (80030e0 ) - 8002fbe: f007 f845 bl 800a04c - printf("maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit - 8002fc2: 4b48 ldr r3, [pc, #288] @ (80030e4 ) - 8002fc4: 881b ldrh r3, [r3, #0] - 8002fc6: b29b uxth r3, r3 - 8002fc8: 4a47 ldr r2, [pc, #284] @ (80030e8 ) - 8002fca: fba2 2303 umull r2, r3, r2, r3 - 8002fce: 095b lsrs r3, r3, #5 - 8002fd0: b29b uxth r3, r3 - 8002fd2: 4619 mov r1, r3 - 8002fd4: 4845 ldr r0, [pc, #276] @ (80030ec ) - 8002fd6: f006 ffd1 bl 8009f7c - printf("maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit - 8002fda: 4b42 ldr r3, [pc, #264] @ (80030e4 ) - 8002fdc: 885b ldrh r3, [r3, #2] - 8002fde: b29b uxth r3, r3 - 8002fe0: 4a43 ldr r2, [pc, #268] @ (80030f0 ) - 8002fe2: fba2 2303 umull r2, r3, r2, r3 - 8002fe6: 08db lsrs r3, r3, #3 - 8002fe8: b29b uxth r3, r3 - 8002fea: 4619 mov r1, r3 - 8002fec: 4841 ldr r0, [pc, #260] @ (80030f4 ) - 8002fee: f006 ffc5 bl 8009f7c - printf("totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh - 8002ff2: 4b3c ldr r3, [pc, #240] @ (80030e4 ) - 8002ff4: 889b ldrh r3, [r3, #4] - 8002ff6: b29b uxth r3, r3 - 8002ff8: 4a3d ldr r2, [pc, #244] @ (80030f0 ) - 8002ffa: fba2 2303 umull r2, r3, r2, r3 - 8002ffe: 08db lsrs r3, r3, #3 - 8003000: b29b uxth r3, r3 - 8003002: 4619 mov r1, r3 - 8003004: 483c ldr r0, [pc, #240] @ (80030f8 ) - 8003006: f006 ffb9 bl 8009f7c - printf("maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit - 800300a: 4b36 ldr r3, [pc, #216] @ (80030e4 ) - 800300c: 88db ldrh r3, [r3, #6] - 800300e: b29b uxth r3, r3 - 8003010: 4a37 ldr r2, [pc, #220] @ (80030f0 ) - 8003012: fba2 2303 umull r2, r3, r2, r3 - 8003016: 08db lsrs r3, r3, #3 - 8003018: b29b uxth r3, r3 - 800301a: 4619 mov r1, r3 - 800301c: 4833 ldr r0, [pc, #204] @ (80030ec ) - 800301e: f006 ffad bl 8009f7c - printf("maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset - 8003022: 4b30 ldr r3, [pc, #192] @ (80030e4 ) - 8003024: 7a1b ldrb r3, [r3, #8] - 8003026: 3b32 subs r3, #50 @ 0x32 - 8003028: 4619 mov r1, r3 - 800302a: 4834 ldr r0, [pc, #208] @ (80030fc ) - 800302c: f006 ffa6 bl 8009f7c - printf("SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% - 8003030: 4b2c ldr r3, [pc, #176] @ (80030e4 ) - 8003032: f8b3 3009 ldrh.w r3, [r3, #9] - 8003036: b29b uxth r3, r3 - 8003038: 4a2d ldr r2, [pc, #180] @ (80030f0 ) - 800303a: fba2 2303 umull r2, r3, r2, r3 - 800303e: 08db lsrs r3, r3, #3 - 8003040: b29b uxth r3, r3 - 8003042: 4619 mov r1, r3 - 8003044: 482e ldr r0, [pc, #184] @ (8003100 ) - 8003046: f006 ff99 bl 8009f7c - printf("Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit - 800304a: 4b26 ldr r3, [pc, #152] @ (80030e4 ) - 800304c: f8b3 300b ldrh.w r3, [r3, #11] - 8003050: b29b uxth r3, r3 - 8003052: 4a27 ldr r2, [pc, #156] @ (80030f0 ) - 8003054: fba2 2303 umull r2, r3, r2, r3 - 8003058: 08db lsrs r3, r3, #3 - 800305a: b29b uxth r3, r3 - 800305c: 4619 mov r1, r3 - 800305e: 4829 ldr r0, [pc, #164] @ (8003104 ) - 8003060: f006 ff8c bl 8009f7c - 8003064: e179 b.n 800335a - 8003066: bf00 nop - 8003068: 0800da88 .word 0x0800da88 - 800306c: 0800da90 .word 0x0800da90 - 8003070: 0800daa0 .word 0x0800daa0 - 8003074: 0800daac .word 0x0800daac - 8003078: 0800dab8 .word 0x0800dab8 - 800307c: 0800dac0 .word 0x0800dac0 - 8003080: 0800dac4 .word 0x0800dac4 - 8003084: 0800dad0 .word 0x0800dad0 - 8003088: 0800dadc .word 0x0800dadc - 800308c: 0800daec .word 0x0800daec - 8003090: 0800daf8 .word 0x0800daf8 - 8003094: 0800db00 .word 0x0800db00 - 8003098: 0800db0c .word 0x0800db0c - 800309c: 0800db18 .word 0x0800db18 - 80030a0: 0800db24 .word 0x0800db24 - 80030a4: 0800db2c .word 0x0800db2c - 80030a8: 0800db34 .word 0x0800db34 - 80030ac: 0800db3c .word 0x0800db3c - 80030b0: 0400f0f0 .word 0x0400f0f0 - 80030b4: 0800db44 .word 0x0800db44 - 80030b8: 0800db4c .word 0x0800db4c - 80030bc: 0800db58 .word 0x0800db58 - 80030c0: 0800db68 .word 0x0800db68 - 80030c4: 0800db74 .word 0x0800db74 - 80030c8: 0800db80 .word 0x0800db80 - 80030cc: 0800db8c .word 0x0800db8c - 80030d0: 0800db98 .word 0x0800db98 - 80030d4: 0800dba0 .word 0x0800dba0 - 80030d8: 0800dbac .word 0x0800dbac - 80030dc: 0800dbb8 .word 0x0800dbb8 - 80030e0: 0800dbc0 .word 0x0800dbc0 - 80030e4: 2000033c .word 0x2000033c - 80030e8: 51eb851f .word 0x51eb851f - 80030ec: 0800dbd0 .word 0x0800dbd0 - 80030f0: cccccccd .word 0xcccccccd - 80030f4: 0800dbdc .word 0x0800dbdc - 80030f8: 0800dbe8 .word 0x0800dbe8 - 80030fc: 0800dbf4 .word 0x0800dbf4 - 8003100: 0800dc00 .word 0x0800dc00 - 8003104: 0800dc0c .word 0x0800dc0c - - } else if (strncmp((const char*)buffer, "info2", length) == 0) { - 8003108: 683a ldr r2, [r7, #0] - 800310a: 4995 ldr r1, [pc, #596] @ (8003360 ) - 800310c: 6878 ldr r0, [r7, #4] - 800310e: f006 ffa5 bl 800a05c - 8003112: 4603 mov r3, r0 - 8003114: 2b00 cmp r3, #0 - 8003116: d153 bne.n 80031c0 - printf("EV info:\n"); - 8003118: 4892 ldr r0, [pc, #584] @ (8003364 ) - 800311a: f006 ff97 bl 800a04c - printf("GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); - 800311e: 4b92 ldr r3, [pc, #584] @ (8003368 ) - 8003120: 781b ldrb r3, [r3, #0] - 8003122: 4619 mov r1, r3 - 8003124: 4b90 ldr r3, [pc, #576] @ (8003368 ) - 8003126: 785b ldrb r3, [r3, #1] - 8003128: 461a mov r2, r3 - 800312a: 4b8f ldr r3, [pc, #572] @ (8003368 ) - 800312c: 789b ldrb r3, [r3, #2] - 800312e: 488f ldr r0, [pc, #572] @ (800336c ) - 8003130: f006 ff24 bl 8009f7c - printf("Battery type: %d\n",GBT_EVInfo.batteryType); - 8003134: 4b8c ldr r3, [pc, #560] @ (8003368 ) - 8003136: 78db ldrb r3, [r3, #3] - 8003138: 4619 mov r1, r3 - 800313a: 488d ldr r0, [pc, #564] @ (8003370 ) - 800313c: f006 ff1e bl 8009f7c - printf("Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit - 8003140: 4b89 ldr r3, [pc, #548] @ (8003368 ) - 8003142: 889b ldrh r3, [r3, #4] - 8003144: b29b uxth r3, r3 - 8003146: 4619 mov r1, r3 - 8003148: 488a ldr r0, [pc, #552] @ (8003374 ) - 800314a: f006 ff17 bl 8009f7c - printf("Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit - 800314e: 4b86 ldr r3, [pc, #536] @ (8003368 ) - 8003150: 88db ldrh r3, [r3, #6] - 8003152: b29b uxth r3, r3 - 8003154: 4619 mov r1, r3 - 8003156: 4888 ldr r0, [pc, #544] @ (8003378 ) - 8003158: f006 ff10 bl 8009f7c - printf("Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) - 800315c: 4987 ldr r1, [pc, #540] @ (800337c ) - 800315e: 4888 ldr r0, [pc, #544] @ (8003380 ) - 8003160: f006 ff0c bl 8009f7c - printf("Battery SN: %lu\n", GBT_EVInfo.batterySN); // int - 8003164: 4b80 ldr r3, [pc, #512] @ (8003368 ) - 8003166: 68db ldr r3, [r3, #12] - 8003168: 4619 mov r1, r3 - 800316a: 4886 ldr r0, [pc, #536] @ (8003384 ) - 800316c: f006 ff06 bl 8009f7c - printf("Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) - 8003170: 4b7d ldr r3, [pc, #500] @ (8003368 ) - 8003172: 7c9b ldrb r3, [r3, #18] - 8003174: 4619 mov r1, r3 - 8003176: 4b7c ldr r3, [pc, #496] @ (8003368 ) - 8003178: 7c5b ldrb r3, [r3, #17] - 800317a: 461a mov r2, r3 - 800317c: 4b7a ldr r3, [pc, #488] @ (8003368 ) - 800317e: 7c1b ldrb r3, [r3, #16] - 8003180: f203 73c1 addw r3, r3, #1985 @ 0x7c1 - 8003184: 4880 ldr r0, [pc, #512] @ (8003388 ) - 8003186: f006 fef9 bl 8009f7c - printf("Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t - 800318a: 4b77 ldr r3, [pc, #476] @ (8003368 ) - 800318c: 7cda ldrb r2, [r3, #19] - 800318e: 7d19 ldrb r1, [r3, #20] - 8003190: 0209 lsls r1, r1, #8 - 8003192: 430a orrs r2, r1 - 8003194: 7d5b ldrb r3, [r3, #21] - 8003196: 041b lsls r3, r3, #16 - 8003198: 4313 orrs r3, r2 - 800319a: 4619 mov r1, r3 - 800319c: 487b ldr r0, [pc, #492] @ (800338c ) - 800319e: f006 feed bl 8009f7c - printf("Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto - 80031a2: 4b71 ldr r3, [pc, #452] @ (8003368 ) - 80031a4: 7d9b ldrb r3, [r3, #22] - 80031a6: 4619 mov r1, r3 - 80031a8: 4879 ldr r0, [pc, #484] @ (8003390 ) - 80031aa: f006 fee7 bl 8009f7c - printf("EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN - 80031ae: 4979 ldr r1, [pc, #484] @ (8003394 ) - 80031b0: 4879 ldr r0, [pc, #484] @ (8003398 ) - 80031b2: f006 fee3 bl 8009f7c - printf("EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); - 80031b6: 4979 ldr r1, [pc, #484] @ (800339c ) - 80031b8: 4879 ldr r0, [pc, #484] @ (80033a0 ) - 80031ba: f006 fedf bl 8009f7c - 80031be: e0cc b.n 800335a - - } else if (strncmp((const char*)buffer, "info3", length) == 0) { - 80031c0: 683a ldr r2, [r7, #0] - 80031c2: 4978 ldr r1, [pc, #480] @ (80033a4 ) - 80031c4: 6878 ldr r0, [r7, #4] - 80031c6: f006 ff49 bl 800a05c - 80031ca: 4603 mov r3, r0 - 80031cc: 2b00 cmp r3, #0 - 80031ce: d133 bne.n 8003238 - printf("GBT_MaxLoad info:\n"); - 80031d0: 4875 ldr r0, [pc, #468] @ (80033a8 ) - 80031d2: f006 ff3b bl 800a04c - printf("Output max current: %d\n",GBT_MaxLoad.maxOutputCurrent); - 80031d6: 4b75 ldr r3, [pc, #468] @ (80033ac ) - 80031d8: 889b ldrh r3, [r3, #4] - 80031da: b29b uxth r3, r3 - 80031dc: 4619 mov r1, r3 - 80031de: 4874 ldr r0, [pc, #464] @ (80033b0 ) - 80031e0: f006 fecc bl 8009f7c - printf("Output min current: %d\n",GBT_MaxLoad.minOutputCurrent); - 80031e4: 4b71 ldr r3, [pc, #452] @ (80033ac ) - 80031e6: 88db ldrh r3, [r3, #6] - 80031e8: b29b uxth r3, r3 - 80031ea: 4619 mov r1, r3 - 80031ec: 4871 ldr r0, [pc, #452] @ (80033b4 ) - 80031ee: f006 fec5 bl 8009f7c - printf("Output max voltage: %d\n",GBT_MaxLoad.maxOutputVoltage); - 80031f2: 4b6e ldr r3, [pc, #440] @ (80033ac ) - 80031f4: 881b ldrh r3, [r3, #0] - 80031f6: b29b uxth r3, r3 - 80031f8: 4619 mov r1, r3 - 80031fa: 486f ldr r0, [pc, #444] @ (80033b8 ) - 80031fc: f006 febe bl 8009f7c - printf("Output min voltage: %d\n",GBT_MaxLoad.minOutputVoltage); - 8003200: 4b6a ldr r3, [pc, #424] @ (80033ac ) - 8003202: 885b ldrh r3, [r3, #2] - 8003204: b29b uxth r3, r3 - 8003206: 4619 mov r1, r3 - 8003208: 486c ldr r0, [pc, #432] @ (80033bc ) - 800320a: f006 feb7 bl 8009f7c - printf("\nGBT_ChargerInfo info:\n"); - 800320e: 486c ldr r0, [pc, #432] @ (80033c0 ) - 8003210: f006 ff1c bl 800a04c - printf("BMS Recognized: %d\n",GBT_ChargerInfo.bmsIdentified); - 8003214: 4b6b ldr r3, [pc, #428] @ (80033c4 ) - 8003216: 781b ldrb r3, [r3, #0] - 8003218: 4619 mov r1, r3 - 800321a: 486b ldr r0, [pc, #428] @ (80033c8 ) - 800321c: f006 feae bl 8009f7c - printf("Charger location: %.3s\n",GBT_ChargerInfo.chargerLocation); - 8003220: 496a ldr r1, [pc, #424] @ (80033cc ) - 8003222: 486b ldr r0, [pc, #428] @ (80033d0 ) - 8003224: f006 feaa bl 8009f7c - printf("Charger number: %lu\n",GBT_ChargerInfo.chargerNumber); - 8003228: 4b66 ldr r3, [pc, #408] @ (80033c4 ) - 800322a: f8d3 3001 ldr.w r3, [r3, #1] - 800322e: 4619 mov r1, r3 - 8003230: 4868 ldr r0, [pc, #416] @ (80033d4 ) - 8003232: f006 fea3 bl 8009f7c - 8003236: e090 b.n 800335a - - - } else if (strncmp((const char*)buffer, "help", length) == 0) { - 8003238: 683a ldr r2, [r7, #0] - 800323a: 4967 ldr r1, [pc, #412] @ (80033d8 ) - 800323c: 6878 ldr r0, [r7, #4] - 800323e: f006 ff0d bl 800a05c - 8003242: 4603 mov r3, r0 - 8003244: 2b00 cmp r3, #0 - 8003246: d136 bne.n 80032b6 - printf("Command list:\n"); - 8003248: 4864 ldr r0, [pc, #400] @ (80033dc ) - 800324a: f006 feff bl 800a04c - printf("reset\n"); - 800324e: 4864 ldr r0, [pc, #400] @ (80033e0 ) - 8003250: f006 fefc bl 800a04c - printf("help\n"); - 8003254: 4860 ldr r0, [pc, #384] @ (80033d8 ) - 8003256: f006 fef9 bl 800a04c - printf("cc_state\n"); - 800325a: 4862 ldr r0, [pc, #392] @ (80033e4 ) - 800325c: f006 fef6 bl 800a04c - printf("lock_lock\n"); - 8003260: 4861 ldr r0, [pc, #388] @ (80033e8 ) - 8003262: f006 fef3 bl 800a04c - printf("lock_unlock\n"); - 8003266: 4861 ldr r0, [pc, #388] @ (80033ec ) - 8003268: f006 fef0 bl 800a04c - printf("lock_state\n"); - 800326c: 4860 ldr r0, [pc, #384] @ (80033f0 ) - 800326e: f006 feed bl 800a04c - printf("adc\n"); - 8003272: 4860 ldr r0, [pc, #384] @ (80033f4 ) - 8003274: f006 feea bl 800a04c - printf("relay(cc,aux)\n"); - 8003278: 485f ldr r0, [pc, #380] @ (80033f8 ) - 800327a: f006 fee7 bl 800a04c - printf("start\n"); - 800327e: 485f ldr r0, [pc, #380] @ (80033fc ) - 8003280: f006 fee4 bl 800a04c - printf("stop\n"); - 8003284: 485e ldr r0, [pc, #376] @ (8003400 ) - 8003286: f006 fee1 bl 800a04c - printf("stop1\n"); - 800328a: 485e ldr r0, [pc, #376] @ (8003404 ) - 800328c: f006 fede bl 800a04c -// printf("force\n"); - printf("temp\n"); - 8003290: 485d ldr r0, [pc, #372] @ (8003408 ) - 8003292: f006 fedb bl 800a04c - printf("info1\n"); - 8003296: 485d ldr r0, [pc, #372] @ (800340c ) - 8003298: f006 fed8 bl 800a04c - printf("info2\n"); - 800329c: 4830 ldr r0, [pc, #192] @ (8003360 ) - 800329e: f006 fed5 bl 800a04c - printf("info3\n"); - 80032a2: 4840 ldr r0, [pc, #256] @ (80033a4 ) - 80032a4: f006 fed2 bl 800a04c - printf("time\n"); - 80032a8: 4859 ldr r0, [pc, #356] @ (8003410 ) - 80032aa: f006 fecf bl 800a04c - printf("cantest\n"); - 80032ae: 4859 ldr r0, [pc, #356] @ (8003414 ) - 80032b0: f006 fecc bl 800a04c - 80032b4: e051 b.n 800335a - - //TODO: info commands - - } else if (strncmp((const char*)buffer, "time", length) == 0) { - 80032b6: 683a ldr r2, [r7, #0] - 80032b8: 4955 ldr r1, [pc, #340] @ (8003410 ) - 80032ba: 6878 ldr r0, [r7, #4] - 80032bc: f006 fece bl 800a05c - 80032c0: 4603 mov r3, r0 - 80032c2: 2b00 cmp r3, #0 - 80032c4: d135 bne.n 8003332 - - time_t unix_time = (time_t)get_Current_Time(); - 80032c6: f001 fed1 bl 800506c - 80032ca: 4603 mov r3, r0 - 80032cc: 17da asrs r2, r3, #31 - 80032ce: 461c mov r4, r3 - 80032d0: 4615 mov r5, r2 - 80032d2: e9c7 4502 strd r4, r5, [r7, #8] - struct tm *parts = localtime(&unix_time); - 80032d6: f107 0308 add.w r3, r7, #8 - 80032da: 4618 mov r0, r3 - 80032dc: f006 ff9c bl 800a218 - 80032e0: 6138 str r0, [r7, #16] - - printf("Year: %d\n", parts->tm_year + 1900); - 80032e2: 693b ldr r3, [r7, #16] - 80032e4: 695b ldr r3, [r3, #20] - 80032e6: f203 736c addw r3, r3, #1900 @ 0x76c - 80032ea: 4619 mov r1, r3 - 80032ec: 484a ldr r0, [pc, #296] @ (8003418 ) - 80032ee: f006 fe45 bl 8009f7c - printf("Month: %d\n", parts->tm_mon + 1); - 80032f2: 693b ldr r3, [r7, #16] - 80032f4: 691b ldr r3, [r3, #16] - 80032f6: 3301 adds r3, #1 - 80032f8: 4619 mov r1, r3 - 80032fa: 4848 ldr r0, [pc, #288] @ (800341c ) - 80032fc: f006 fe3e bl 8009f7c - printf("Day: %d\n", parts->tm_mday); - 8003300: 693b ldr r3, [r7, #16] - 8003302: 68db ldr r3, [r3, #12] - 8003304: 4619 mov r1, r3 - 8003306: 4846 ldr r0, [pc, #280] @ (8003420 ) - 8003308: f006 fe38 bl 8009f7c - printf("Hour: %d\n", parts->tm_hour); - 800330c: 693b ldr r3, [r7, #16] - 800330e: 689b ldr r3, [r3, #8] - 8003310: 4619 mov r1, r3 - 8003312: 4844 ldr r0, [pc, #272] @ (8003424 ) - 8003314: f006 fe32 bl 8009f7c - printf("Minute: %d\n", parts->tm_min); - 8003318: 693b ldr r3, [r7, #16] - 800331a: 685b ldr r3, [r3, #4] - 800331c: 4619 mov r1, r3 - 800331e: 4842 ldr r0, [pc, #264] @ (8003428 ) - 8003320: f006 fe2c bl 8009f7c - printf("Second: %d\n", parts->tm_sec); - 8003324: 693b ldr r3, [r7, #16] - 8003326: 681b ldr r3, [r3, #0] - 8003328: 4619 mov r1, r3 - 800332a: 4840 ldr r0, [pc, #256] @ (800342c ) - 800332c: f006 fe26 bl 8009f7c - 8003330: e013 b.n 800335a - - } else if (strncmp((const char*)buffer, "cantest", length) == 0) { - 8003332: 683a ldr r2, [r7, #0] - 8003334: 4937 ldr r1, [pc, #220] @ (8003414 ) - 8003336: 6878 ldr r0, [r7, #4] - 8003338: f006 fe90 bl 800a05c - 800333c: 4603 mov r3, r0 - 800333e: 2b00 cmp r3, #0 - 8003340: d106 bne.n 8003350 - //GBT_SendCHM(); - GBT_Error(0xFDF0C0FC); //BRM Timeout - 8003342: 483b ldr r0, [pc, #236] @ (8003430 ) - 8003344: f7ff fa34 bl 80027b0 - printf("can test\n"); - 8003348: 483a ldr r0, [pc, #232] @ (8003434 ) - 800334a: f006 fe7f bl 800a04c - 800334e: e004 b.n 800335a - - } else { - printf("Unknown command\n"); - 8003350: 4839 ldr r0, [pc, #228] @ (8003438 ) - 8003352: f006 fe7b bl 800a04c - 8003356: e000 b.n 800335a - if (buffer[0] == 0) return; - 8003358: bf00 nop - } -} - 800335a: 3718 adds r7, #24 - 800335c: 46bd mov sp, r7 - 800335e: bdb0 pop {r4, r5, r7, pc} - 8003360: 0800dc18 .word 0x0800dc18 - 8003364: 0800dc20 .word 0x0800dc20 - 8003368: 20000308 .word 0x20000308 - 800336c: 0800dc2c .word 0x0800dc2c - 8003370: 0800dc40 .word 0x0800dc40 - 8003374: 0800dc54 .word 0x0800dc54 - 8003378: 0800dc6c .word 0x0800dc6c - 800337c: 20000310 .word 0x20000310 - 8003380: 0800dc84 .word 0x0800dc84 - 8003384: 0800dc9c .word 0x0800dc9c - 8003388: 0800dcb0 .word 0x0800dcb0 - 800338c: 0800dcdc .word 0x0800dcdc - 8003390: 0800dcf0 .word 0x0800dcf0 - 8003394: 20000320 .word 0x20000320 - 8003398: 0800dd00 .word 0x0800dd00 - 800339c: 20000331 .word 0x20000331 - 80033a0: 0800dd10 .word 0x0800dd10 - 80033a4: 0800dd24 .word 0x0800dd24 - 80033a8: 0800dd2c .word 0x0800dd2c - 80033ac: 200002f4 .word 0x200002f4 - 80033b0: 0800dd40 .word 0x0800dd40 - 80033b4: 0800dd58 .word 0x0800dd58 - 80033b8: 0800dd70 .word 0x0800dd70 - 80033bc: 0800dd88 .word 0x0800dd88 - 80033c0: 0800dda0 .word 0x0800dda0 - 80033c4: 200002fc .word 0x200002fc - 80033c8: 0800ddb8 .word 0x0800ddb8 - 80033cc: 20000301 .word 0x20000301 - 80033d0: 0800ddcc .word 0x0800ddcc - 80033d4: 0800dde4 .word 0x0800dde4 - 80033d8: 0800ddfc .word 0x0800ddfc - 80033dc: 0800de04 .word 0x0800de04 - 80033e0: 0800da88 .word 0x0800da88 - 80033e4: 0800db4c .word 0x0800db4c - 80033e8: 0800daec .word 0x0800daec - 80033ec: 0800db00 .word 0x0800db00 - 80033f0: 0800dad0 .word 0x0800dad0 - 80033f4: 0800dac0 .word 0x0800dac0 - 80033f8: 0800de14 .word 0x0800de14 - 80033fc: 0800db24 .word 0x0800db24 - 8003400: 0800db34 .word 0x0800db34 - 8003404: 0800db44 .word 0x0800db44 - 8003408: 0800db98 .word 0x0800db98 - 800340c: 0800dbb8 .word 0x0800dbb8 - 8003410: 0800de24 .word 0x0800de24 - 8003414: 0800de2c .word 0x0800de2c - 8003418: 0800de34 .word 0x0800de34 - 800341c: 0800de40 .word 0x0800de40 - 8003420: 0800de4c .word 0x0800de4c - 8003424: 0800de58 .word 0x0800de58 - 8003428: 0800de64 .word 0x0800de64 - 800342c: 0800de70 .word 0x0800de70 - 8003430: fdf0c0fc .word 0xfdf0c0fc - 8003434: 0800de7c .word 0x0800de7c - 8003438: 0800de88 .word 0x0800de88 - -0800343c : - -void debug_task(){ - 800343c: b580 push {r7, lr} - 800343e: af00 add r7, sp, #0 - if(debug_cmd_received){ - 8003440: 4b09 ldr r3, [pc, #36] @ (8003468 ) - 8003442: 781b ldrb r3, [r3, #0] - 8003444: 2b00 cmp r3, #0 - 8003446: d00d beq.n 8003464 - parse_command(debug_rx_buffer, debug_rx_buffer_size); - 8003448: 4b08 ldr r3, [pc, #32] @ (800346c ) - 800344a: 781b ldrb r3, [r3, #0] - 800344c: 4619 mov r1, r3 - 800344e: 4808 ldr r0, [pc, #32] @ (8003470 ) - 8003450: f7ff fc84 bl 8002d5c - HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); - 8003454: 22ff movs r2, #255 @ 0xff - 8003456: 4906 ldr r1, [pc, #24] @ (8003470 ) - 8003458: 4806 ldr r0, [pc, #24] @ (8003474 ) - 800345a: f005 fb8d bl 8008b78 - debug_cmd_received = 0; - 800345e: 4b02 ldr r3, [pc, #8] @ (8003468 ) - 8003460: 2200 movs r2, #0 - 8003462: 701a strb r2, [r3, #0] - } -} - 8003464: bf00 nop - 8003466: bd80 pop {r7, pc} - 8003468: 200004a0 .word 0x200004a0 - 800346c: 200004a1 .word 0x200004a1 - 8003470: 200003a0 .word 0x200003a0 - 8003474: 20003354 .word 0x20003354 - -08003478 : - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_ReadHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ - 8003478: b480 push {r7} - 800347a: b085 sub sp, #20 - 800347c: af00 add r7, sp, #0 - 800347e: 603b str r3, [r7, #0] - 8003480: 4603 mov r3, r0 - 8003482: 71fb strb r3, [r7, #7] - 8003484: 460b mov r3, r1 - 8003486: 71bb strb r3, [r7, #6] - 8003488: 4613 mov r3, r2 - 800348a: 80bb strh r3, [r7, #4] -// printf("Destination ID = %d\n", DestinationID); -// printf("Address = %d\n", Addr); -// printf("Len = %d\n", len); -// printf("\n"); - - for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler - 800348c: 2300 movs r3, #0 - 800348e: 81fb strh r3, [r7, #14] - 8003490: e002 b.n 8003498 - 8003492: 89fb ldrh r3, [r7, #14] - 8003494: 3301 adds r3, #1 - 8003496: 81fb strh r3, [r7, #14] - 8003498: 7e3b ldrb r3, [r7, #24] - 800349a: b29b uxth r3, r3 - 800349c: 89fa ldrh r2, [r7, #14] - 800349e: 429a cmp r2, r3 - 80034a0: d3f7 bcc.n 8003492 -// } -// } - - } -// printf("\n"); -} - 80034a2: bf00 nop - 80034a4: bf00 nop - 80034a6: 3714 adds r7, #20 - 80034a8: 46bd mov sp, r7 - 80034aa: bc80 pop {r7} - 80034ac: 4770 bx lr - ... - -080034b0 : - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_WriteUserRegister(uint16_t addr, uint8_t value){ - 80034b0: b580 push {r7, lr} - 80034b2: b082 sub sp, #8 - 80034b4: af00 add r7, sp, #0 - 80034b6: 4603 mov r3, r0 - 80034b8: 460a mov r2, r1 - 80034ba: 80fb strh r3, [r7, #6] - 80034bc: 4613 mov r3, r2 - 80034be: 717b strb r3, [r7, #5] - switch(addr){ - 80034c0: 88fb ldrh r3, [r7, #6] - 80034c2: f5b3 7f0a cmp.w r3, #552 @ 0x228 - 80034c6: dc5d bgt.n 8003584 - 80034c8: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 80034cc: f2c0 808f blt.w 80035ee - 80034d0: f5a3 7300 sub.w r3, r3, #512 @ 0x200 - 80034d4: 2b28 cmp r3, #40 @ 0x28 - 80034d6: f200 808a bhi.w 80035ee - 80034da: a201 add r2, pc, #4 @ (adr r2, 80034e0 ) - 80034dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80034e0: 080035cf .word 0x080035cf - 80034e4: 080035cf .word 0x080035cf - 80034e8: 080035cf .word 0x080035cf - 80034ec: 080035cf .word 0x080035cf - 80034f0: 080035cf .word 0x080035cf - 80034f4: 080035cf .word 0x080035cf - 80034f8: 080035cf .word 0x080035cf - 80034fc: 080035cf .word 0x080035cf - 8003500: 080035cf .word 0x080035cf - 8003504: 080035ef .word 0x080035ef - 8003508: 080035ef .word 0x080035ef - 800350c: 080035ef .word 0x080035ef - 8003510: 080035ef .word 0x080035ef - 8003514: 080035ef .word 0x080035ef - 8003518: 080035ef .word 0x080035ef - 800351c: 080035ef .word 0x080035ef - 8003520: 0800358f .word 0x0800358f - 8003524: 0800359b .word 0x0800359b - 8003528: 080035a7 .word 0x080035a7 - 800352c: 080035b3 .word 0x080035b3 - 8003530: 080035ef .word 0x080035ef - 8003534: 080035ef .word 0x080035ef - 8003538: 080035ef .word 0x080035ef - 800353c: 080035ef .word 0x080035ef - 8003540: 080035ef .word 0x080035ef - 8003544: 080035ef .word 0x080035ef - 8003548: 080035ef .word 0x080035ef - 800354c: 080035ef .word 0x080035ef - 8003550: 080035ef .word 0x080035ef - 8003554: 080035ef .word 0x080035ef - 8003558: 080035ef .word 0x080035ef - 800355c: 080035ef .word 0x080035ef - 8003560: 080035bf .word 0x080035bf - 8003564: 080035bf .word 0x080035bf - 8003568: 080035bf .word 0x080035bf - 800356c: 080035bf .word 0x080035bf - 8003570: 080035bf .word 0x080035bf - 8003574: 080035bf .word 0x080035bf - 8003578: 080035bf .word 0x080035bf - 800357c: 080035bf .word 0x080035bf - 8003580: 080035bf .word 0x080035bf - 8003584: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 - 8003588: 2b07 cmp r3, #7 - 800358a: d830 bhi.n 80035ee - 800358c: e027 b.n 80035de -// if(value)GBT_Charger_Enable = 1; -// else GBT_Charger_Enable = 0; -// break; - - case EDCAN_REG_TIME_0: - writeTimeReg(0, value); - 800358e: 797b ldrb r3, [r7, #5] - 8003590: 4619 mov r1, r3 - 8003592: 2000 movs r0, #0 - 8003594: f001 fe12 bl 80051bc - break; - 8003598: e02d b.n 80035f6 - case EDCAN_REG_TIME_1: - writeTimeReg(1, value); - 800359a: 797b ldrb r3, [r7, #5] - 800359c: 4619 mov r1, r3 - 800359e: 2001 movs r0, #1 - 80035a0: f001 fe0c bl 80051bc - break; - 80035a4: e027 b.n 80035f6 - case EDCAN_REG_TIME_2: - writeTimeReg(2, value); - 80035a6: 797b ldrb r3, [r7, #5] - 80035a8: 4619 mov r1, r3 - 80035aa: 2002 movs r0, #2 - 80035ac: f001 fe06 bl 80051bc - break; - 80035b0: e021 b.n 80035f6 - case EDCAN_REG_TIME_3: - writeTimeReg(3, value); - 80035b2: 797b ldrb r3, [r7, #5] - 80035b4: 4619 mov r1, r3 - 80035b6: 2003 movs r0, #3 - 80035b8: f001 fe00 bl 80051bc - break; - 80035bc: e01b b.n 80035f6 - - - - //0x220 - case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): - ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD] = value; - 80035be: 88fb ldrh r3, [r7, #6] - 80035c0: f5a3 7308 sub.w r3, r3, #544 @ 0x220 - 80035c4: 4a0e ldr r2, [pc, #56] @ (8003600 ) - 80035c6: 4413 add r3, r2 - 80035c8: 797a ldrb r2, [r7, #5] - 80035ca: 701a strb r2, [r3, #0] - break; - 80035cc: e013 b.n 80035f6 - - //0x200 - case EDCAN_REG_CHARGER_INFO ... (EDCAN_REG_CHARGER_INFO+sizeof(GBT_CRM_t)): - ((uint8_t*)&GBT_ChargerInfo)[addr - EDCAN_REG_CHARGER_INFO] = value; - 80035ce: 88fb ldrh r3, [r7, #6] - 80035d0: f5a3 7300 sub.w r3, r3, #512 @ 0x200 - 80035d4: 4a0b ldr r2, [pc, #44] @ (8003604 ) - 80035d6: 4413 add r3, r2 - 80035d8: 797a ldrb r2, [r7, #5] - 80035da: 701a strb r2, [r3, #0] - break; - 80035dc: e00b b.n 80035f6 - - //0x580 - case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): - ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT] = value; - 80035de: 88fb ldrh r3, [r7, #6] - 80035e0: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 - 80035e4: 4a08 ldr r2, [pc, #32] @ (8003608 ) - 80035e6: 4413 add r3, r2 - 80035e8: 797a ldrb r2, [r7, #5] - 80035ea: 701a strb r2, [r3, #0] - - //TODO - //GBT_EDCAN_Input.measuredCurrent; - break; - 80035ec: e003 b.n 80035f6 - - - - default: - printf ("Unknown register\n"); - 80035ee: 4807 ldr r0, [pc, #28] @ (800360c ) - 80035f0: f006 fd2c bl 800a04c - } - -} - 80035f4: bf00 nop - 80035f6: bf00 nop - 80035f8: 3708 adds r7, #8 - 80035fa: 46bd mov sp, r7 - 80035fc: bd80 pop {r7, pc} - 80035fe: bf00 nop - 8003600: 200002f4 .word 0x200002f4 - 8003604: 200002fc .word 0x200002fc - 8003608: 200004b4 .word 0x200004b4 - 800360c: 0800de98 .word 0x0800de98 - -08003610 : - - -uint8_t EDCAN_GetUserRegisterValue(uint16_t addr){ - 8003610: b580 push {r7, lr} - 8003612: b082 sub sp, #8 - 8003614: af00 add r7, sp, #0 - 8003616: 4603 mov r3, r0 - 8003618: 80fb strh r3, [r7, #6] - switch (addr){ - 800361a: 88fb ldrh r3, [r7, #6] - 800361c: f5b3 6fb1 cmp.w r3, #1416 @ 0x588 - 8003620: f280 8122 bge.w 8003868 - 8003624: f5b3 6fb0 cmp.w r3, #1408 @ 0x580 - 8003628: f280 8117 bge.w 800385a - 800362c: f240 520d movw r2, #1293 @ 0x50d - 8003630: 4293 cmp r3, r2 - 8003632: f300 8119 bgt.w 8003868 - 8003636: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 - 800363a: f280 8107 bge.w 800384c - 800363e: f5b3 7f62 cmp.w r3, #904 @ 0x388 - 8003642: f280 8111 bge.w 8003868 - 8003646: f5b3 7f54 cmp.w r3, #848 @ 0x350 - 800364a: da07 bge.n 800365c - 800364c: f5b3 7f0a cmp.w r3, #552 @ 0x228 - 8003650: f300 80b6 bgt.w 80037c0 - 8003654: f5b3 7f04 cmp.w r3, #528 @ 0x210 - 8003658: da78 bge.n 800374c - 800365a: e105 b.n 8003868 - 800365c: f5a3 7354 sub.w r3, r3, #848 @ 0x350 - 8003660: 2b37 cmp r3, #55 @ 0x37 - 8003662: f200 8101 bhi.w 8003868 - 8003666: a201 add r2, pc, #4 @ (adr r2, 800366c ) - 8003668: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800366c: 0800380f .word 0x0800380f - 8003670: 0800380f .word 0x0800380f - 8003674: 0800380f .word 0x0800380f - 8003678: 0800380f .word 0x0800380f - 800367c: 0800380f .word 0x0800380f - 8003680: 0800380f .word 0x0800380f - 8003684: 0800380f .word 0x0800380f - 8003688: 0800380f .word 0x0800380f - 800368c: 0800380f .word 0x0800380f - 8003690: 0800380f .word 0x0800380f - 8003694: 0800380f .word 0x0800380f - 8003698: 0800380f .word 0x0800380f - 800369c: 0800380f .word 0x0800380f - 80036a0: 0800380f .word 0x0800380f - 80036a4: 08003869 .word 0x08003869 - 80036a8: 0800381d .word 0x0800381d - 80036ac: 08003823 .word 0x08003823 - 80036b0: 08003823 .word 0x08003823 - 80036b4: 08003823 .word 0x08003823 - 80036b8: 08003823 .word 0x08003823 - 80036bc: 08003823 .word 0x08003823 - 80036c0: 08003823 .word 0x08003823 - 80036c4: 08003869 .word 0x08003869 - 80036c8: 08003869 .word 0x08003869 - 80036cc: 08003869 .word 0x08003869 - 80036d0: 08003869 .word 0x08003869 - 80036d4: 08003869 .word 0x08003869 - 80036d8: 08003869 .word 0x08003869 - 80036dc: 08003869 .word 0x08003869 - 80036e0: 08003869 .word 0x08003869 - 80036e4: 08003869 .word 0x08003869 - 80036e8: 08003869 .word 0x08003869 - 80036ec: 08003831 .word 0x08003831 - 80036f0: 08003831 .word 0x08003831 - 80036f4: 08003831 .word 0x08003831 - 80036f8: 08003831 .word 0x08003831 - 80036fc: 08003831 .word 0x08003831 - 8003700: 08003831 .word 0x08003831 - 8003704: 08003831 .word 0x08003831 - 8003708: 08003831 .word 0x08003831 - 800370c: 08003831 .word 0x08003831 - 8003710: 08003831 .word 0x08003831 - 8003714: 08003869 .word 0x08003869 - 8003718: 08003869 .word 0x08003869 - 800371c: 08003869 .word 0x08003869 - 8003720: 08003869 .word 0x08003869 - 8003724: 08003869 .word 0x08003869 - 8003728: 08003869 .word 0x08003869 - 800372c: 0800383f .word 0x0800383f - 8003730: 0800383f .word 0x0800383f - 8003734: 0800383f .word 0x0800383f - 8003738: 0800383f .word 0x0800383f - 800373c: 0800383f .word 0x0800383f - 8003740: 0800383f .word 0x0800383f - 8003744: 0800383f .word 0x0800383f - 8003748: 0800383f .word 0x0800383f - 800374c: f5a3 7304 sub.w r3, r3, #528 @ 0x210 - 8003750: 2b18 cmp r3, #24 - 8003752: f200 8089 bhi.w 8003868 - 8003756: a201 add r2, pc, #4 @ (adr r2, 800375c ) - 8003758: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800375c: 080037cb .word 0x080037cb - 8003760: 080037d5 .word 0x080037d5 - 8003764: 080037df .word 0x080037df - 8003768: 080037e9 .word 0x080037e9 - 800376c: 08003869 .word 0x08003869 - 8003770: 08003869 .word 0x08003869 - 8003774: 08003869 .word 0x08003869 - 8003778: 08003869 .word 0x08003869 - 800377c: 08003869 .word 0x08003869 - 8003780: 08003869 .word 0x08003869 - 8003784: 08003869 .word 0x08003869 - 8003788: 08003869 .word 0x08003869 - 800378c: 08003869 .word 0x08003869 - 8003790: 08003869 .word 0x08003869 - 8003794: 08003869 .word 0x08003869 - 8003798: 08003869 .word 0x08003869 - 800379c: 080037f3 .word 0x080037f3 - 80037a0: 080037f3 .word 0x080037f3 - 80037a4: 080037f3 .word 0x080037f3 - 80037a8: 080037f3 .word 0x080037f3 - 80037ac: 080037f3 .word 0x080037f3 - 80037b0: 080037f3 .word 0x080037f3 - 80037b4: 080037f3 .word 0x080037f3 - 80037b8: 080037f3 .word 0x080037f3 - 80037bc: 080037f3 .word 0x080037f3 - 80037c0: f5a3 7344 sub.w r3, r3, #784 @ 0x310 - 80037c4: 2b30 cmp r3, #48 @ 0x30 - 80037c6: d84f bhi.n 8003868 - 80037c8: e01a b.n 8003800 - -// /* регистры 256..2047 используются пользовательских нужд */ - -// 0x400 - case EDCAN_REG_TIME_0: - return getTimeReg(0); - 80037ca: 2000 movs r0, #0 - 80037cc: f001 fd1e bl 800520c - 80037d0: 4603 mov r3, r0 - 80037d2: e04a b.n 800386a - break; - - case EDCAN_REG_TIME_1: - return getTimeReg(1); - 80037d4: 2001 movs r0, #1 - 80037d6: f001 fd19 bl 800520c - 80037da: 4603 mov r3, r0 - 80037dc: e045 b.n 800386a - break; - - case EDCAN_REG_TIME_2: - return getTimeReg(2); - 80037de: 2002 movs r0, #2 - 80037e0: f001 fd14 bl 800520c - 80037e4: 4603 mov r3, r0 - 80037e6: e040 b.n 800386a - break; - - case EDCAN_REG_TIME_3: - return getTimeReg(3); - 80037e8: 2003 movs r0, #3 - 80037ea: f001 fd0f bl 800520c - 80037ee: 4603 mov r3, r0 - 80037f0: e03b b.n 800386a - break; - - - //0x220 - case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): - return ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD]; - 80037f2: 88fb ldrh r3, [r7, #6] - 80037f4: f5a3 7308 sub.w r3, r3, #544 @ 0x220 - 80037f8: 4a1e ldr r2, [pc, #120] @ (8003874 ) - 80037fa: 4413 add r3, r2 - 80037fc: 781b ldrb r3, [r3, #0] - 80037fe: e034 b.n 800386a - - //0x310 - case EDCAN_REG_BRM ... (EDCAN_REG_BRM+sizeof(GBT_BRM_t)-1): - return ((uint8_t*)&GBT_EVInfo)[addr - EDCAN_REG_BRM]; - 8003800: 88fb ldrh r3, [r7, #6] - 8003802: f5a3 7344 sub.w r3, r3, #784 @ 0x310 - 8003806: 4a1c ldr r2, [pc, #112] @ (8003878 ) - 8003808: 4413 add r3, r2 - 800380a: 781b ldrb r3, [r3, #0] - 800380c: e02d b.n 800386a - - //0x340 - case EDCAN_REG_BCP ... (EDCAN_REG_BCP+sizeof(GBT_BCP_t)): - return ((uint8_t*)&GBT_BATStat)[addr - EDCAN_REG_BCP]; - 800380e: 88fb ldrh r3, [r7, #6] - 8003810: f5a3 7354 sub.w r3, r3, #848 @ 0x350 - 8003814: 4a19 ldr r2, [pc, #100] @ (800387c ) - 8003816: 4413 add r3, r2 - 8003818: 781b ldrb r3, [r3, #0] - 800381a: e026 b.n 800386a - - //0x34F - case EDCAN_REG_BRO: - return GBT_BRO; - 800381c: 4b18 ldr r3, [pc, #96] @ (8003880 ) - 800381e: 781b ldrb r3, [r3, #0] - 8003820: e023 b.n 800386a - - //0x350 - case EDCAN_REG_BCL ... (EDCAN_REG_BCL+sizeof(GBT_BCL_t)): - return ((uint8_t*)&GBT_ReqPower)[addr - EDCAN_REG_BCL]; - 8003822: 88fb ldrh r3, [r7, #6] - 8003824: f5a3 7358 sub.w r3, r3, #864 @ 0x360 - 8003828: 4a16 ldr r2, [pc, #88] @ (8003884 ) - 800382a: 4413 add r3, r2 - 800382c: 781b ldrb r3, [r3, #0] - 800382e: e01c b.n 800386a - - //0x360 - case EDCAN_REG_BCS ... (EDCAN_REG_BCS+sizeof(GBT_BCS_t)): - return ((uint8_t*)&GBT_ChargingStatus)[addr - EDCAN_REG_BCS]; - 8003830: 88fb ldrh r3, [r7, #6] - 8003832: f5a3 735c sub.w r3, r3, #880 @ 0x370 - 8003836: 4a14 ldr r2, [pc, #80] @ (8003888 ) - 8003838: 4413 add r3, r2 - 800383a: 781b ldrb r3, [r3, #0] - 800383c: e015 b.n 800386a - - //0x370 - case EDCAN_REG_BSM ... (EDCAN_REG_BSM+sizeof(GBT_BSM_t)): - return ((uint8_t*)&GBT_BatteryStatus)[addr - EDCAN_REG_BSM]; - 800383e: 88fb ldrh r3, [r7, #6] - 8003840: f5a3 7360 sub.w r3, r3, #896 @ 0x380 - 8003844: 4a11 ldr r2, [pc, #68] @ (800388c ) - 8003846: 4413 add r3, r2 - 8003848: 781b ldrb r3, [r3, #0] - 800384a: e00e b.n 800386a - - - //0x500 - case EDCAN_REG_OUTPUT ... (EDCAN_REG_OUTPUT+sizeof(GBT_EDCAN_Output_t)): - return ((uint8_t*)&GBT_EDCAN_Output)[addr - EDCAN_REG_OUTPUT]; - 800384c: 88fb ldrh r3, [r7, #6] - 800384e: f5a3 63a0 sub.w r3, r3, #1280 @ 0x500 - 8003852: 4a0f ldr r2, [pc, #60] @ (8003890 ) - 8003854: 4413 add r3, r2 - 8003856: 781b ldrb r3, [r3, #0] - 8003858: e007 b.n 800386a - - //0x580 - case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): - return ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT]; - 800385a: 88fb ldrh r3, [r7, #6] - 800385c: f5a3 63b0 sub.w r3, r3, #1408 @ 0x580 - 8003860: 4a0c ldr r2, [pc, #48] @ (8003894 ) - 8003862: 4413 add r3, r2 - 8003864: 781b ldrb r3, [r3, #0] - 8003866: e000 b.n 800386a - - - default: - return 0x00; - 8003868: 2300 movs r3, #0 - } -} - 800386a: 4618 mov r0, r3 - 800386c: 3708 adds r7, #8 - 800386e: 46bd mov sp, r7 - 8003870: bd80 pop {r7, pc} - 8003872: bf00 nop - 8003874: 200002f4 .word 0x200002f4 - 8003878: 20000308 .word 0x20000308 - 800387c: 2000033c .word 0x2000033c - 8003880: 20000380 .word 0x20000380 - 8003884: 2000034c .word 0x2000034c - 8003888: 2000035c .word 0x2000035c - 800388c: 20000368 .word 0x20000368 - 8003890: 200004a4 .word 0x200004a4 - 8003894: 200004b4 .word 0x200004b4 - -08003898 : -// GB/T Time Synchronization Packet -#include "main.h" -#include "soft_rtc.h" -#include "charger_gbt.h" - -void GBT_SendCTS(){ - 8003898: b580 push {r7, lr} - 800389a: b082 sub sp, #8 - 800389c: af00 add r7, sp, #0 - - uint8_t data[7]; - unix_to_bcd(get_Current_Time(), data); - 800389e: f001 fbe5 bl 800506c - 80038a2: 4602 mov r2, r0 - 80038a4: 463b mov r3, r7 - 80038a6: 4619 mov r1, r3 - 80038a8: 4610 mov r0, r2 - 80038aa: f001 fc1b bl 80050e4 -// data[3] = 0x05; //days -// data[4] = 0x05; //month -// data[5] = 0x24; //years -// data[6] = 0x20; //centuries - - J_SendPacket(0x000700, 6, 7, data); - 80038ae: 463b mov r3, r7 - 80038b0: 2207 movs r2, #7 - 80038b2: 2106 movs r1, #6 - 80038b4: f44f 60e0 mov.w r0, #1792 @ 0x700 - 80038b8: f000 fb06 bl 8003ec8 -} - 80038bc: bf00 nop - 80038be: 3708 adds r7, #8 - 80038c0: 46bd mov sp, r7 - 80038c2: bd80 pop {r7, pc} - -080038c4 : - -//GB/T Max Load Packet -void GBT_SendCML(){ - 80038c4: b580 push {r7, lr} - 80038c6: af00 add r7, sp, #0 -// data[4] = 0xC4; //-150A maximum output current -// data[5] = 0x09; // -// data[6] = 0x8C; //-2A minimum output current -// data[7] = 0x0F; // - - J_SendPacket(0x000800, 6, 8, (uint8_t*)&GBT_MaxLoad); - 80038c8: 4b04 ldr r3, [pc, #16] @ (80038dc ) - 80038ca: 2208 movs r2, #8 - 80038cc: 2106 movs r1, #6 - 80038ce: f44f 6000 mov.w r0, #2048 @ 0x800 - 80038d2: f000 faf9 bl 8003ec8 - -} - 80038d6: bf00 nop - 80038d8: bd80 pop {r7, pc} - 80038da: bf00 nop - 80038dc: 200002f4 .word 0x200002f4 - -080038e0 : - -//GB/T Version packet -void GBT_SendCHM(){ - 80038e0: b580 push {r7, lr} - 80038e2: b082 sub sp, #8 - 80038e4: af00 add r7, sp, #0 - uint8_t data[3]; - data[0] = 0x01; - 80038e6: 2301 movs r3, #1 - 80038e8: 713b strb r3, [r7, #4] - data[1] = 0x01; - 80038ea: 2301 movs r3, #1 - 80038ec: 717b strb r3, [r7, #5] - data[2] = 0x00; - 80038ee: 2300 movs r3, #0 - 80038f0: 71bb strb r3, [r7, #6] - J_SendPacket(0x2600, 6, 3, data); - 80038f2: 1d3b adds r3, r7, #4 - 80038f4: 2203 movs r2, #3 - 80038f6: 2106 movs r1, #6 - 80038f8: f44f 5018 mov.w r0, #9728 @ 0x2600 - 80038fc: f000 fae4 bl 8003ec8 -} - 8003900: bf00 nop - 8003902: 3708 adds r7, #8 - 8003904: 46bd mov sp, r7 - 8003906: bd80 pop {r7, pc} - -08003908 : - -//GB/T CRM Packet (state=BMS identified) -void GBT_SendCRM(uint8_t state){ - 8003908: b580 push {r7, lr} - 800390a: b082 sub sp, #8 - 800390c: af00 add r7, sp, #0 - 800390e: 4603 mov r3, r0 - 8003910: 71fb strb r3, [r7, #7] -// data[3] = 0x01; -// data[4] = 0x00; -// data[5] = 0x42; //TODO: location BFG -// data[6] = 0x46; -// data[7] = 0x47; - GBT_ChargerInfo.bmsIdentified = state; - 8003912: 4a07 ldr r2, [pc, #28] @ (8003930 ) - 8003914: 79fb ldrb r3, [r7, #7] - 8003916: 7013 strb r3, [r2, #0] - J_SendPacket(0x100, 6, 8, (uint8_t *)&GBT_ChargerInfo); - 8003918: 4b05 ldr r3, [pc, #20] @ (8003930 ) - 800391a: 2208 movs r2, #8 - 800391c: 2106 movs r1, #6 - 800391e: f44f 7080 mov.w r0, #256 @ 0x100 - 8003922: f000 fad1 bl 8003ec8 -} - 8003926: bf00 nop - 8003928: 3708 adds r7, #8 - 800392a: 46bd mov sp, r7 - 800392c: bd80 pop {r7, pc} - 800392e: bf00 nop - 8003930: 200002fc .word 0x200002fc - -08003934 : - -//GB/T CRO packet (Charger ready) -void GBT_SendCRO(uint8_t state){ - 8003934: b580 push {r7, lr} - 8003936: b084 sub sp, #16 - 8003938: af00 add r7, sp, #0 - 800393a: 4603 mov r3, r0 - 800393c: 71fb strb r3, [r7, #7] - uint8_t data[1]; - data[0] = state; - 800393e: 79fb ldrb r3, [r7, #7] - 8003940: 733b strb r3, [r7, #12] - J_SendPacket(0xA00, 4, 1, data); - 8003942: f107 030c add.w r3, r7, #12 - 8003946: 2201 movs r2, #1 - 8003948: 2104 movs r1, #4 - 800394a: f44f 6020 mov.w r0, #2560 @ 0xa00 - 800394e: f000 fabb bl 8003ec8 -} - 8003952: bf00 nop - 8003954: 3710 adds r7, #16 - 8003956: 46bd mov sp, r7 - 8003958: bd80 pop {r7, pc} - ... - -0800395c : - -//GB/T CCS packet (Charger current status) -void GBT_SendCCS(){ - 800395c: b580 push {r7, lr} - 800395e: af00 add r7, sp, #0 -// data[3] = GBT_CurrPower.requestedCurrent>>8; //TODO: current -// data[4] = GBT_StateTick()/60000; //charging time (min) -// data[5] = 0; //TODO: 255 min+ -// data[6] = 0b11111101; //charging not permitted -// data[7] = 0xFF; - J_SendPacket(0x1200, 6, 8, (uint8_t *)&GBT_ChargerCurrentStatus); - 8003960: 4b04 ldr r3, [pc, #16] @ (8003974 ) - 8003962: 2208 movs r2, #8 - 8003964: 2106 movs r1, #6 - 8003966: f44f 5090 mov.w r0, #4608 @ 0x1200 - 800396a: f000 faad bl 8003ec8 -} - 800396e: bf00 nop - 8003970: bd80 pop {r7, pc} - 8003972: bf00 nop - 8003974: 20000370 .word 0x20000370 - -08003978 : - -// GB/T Charging Stop packet -void GBT_SendCST(uint32_t Cause){ - 8003978: b580 push {r7, lr} - 800397a: b084 sub sp, #16 - 800397c: af00 add r7, sp, #0 - 800397e: 6078 str r0, [r7, #4] - uint8_t data[8]; - data[0] = (Cause>>24) & 0xFF; // Error - 8003980: 687b ldr r3, [r7, #4] - 8003982: 0e1b lsrs r3, r3, #24 - 8003984: b2db uxtb r3, r3 - 8003986: 723b strb r3, [r7, #8] - data[1] = (Cause>>16) & 0xFF; // - 8003988: 687b ldr r3, [r7, #4] - 800398a: 0c1b lsrs r3, r3, #16 - 800398c: b2db uxtb r3, r3 - 800398e: 727b strb r3, [r7, #9] - data[2] = (Cause>>8) & 0xFF; // - 8003990: 687b ldr r3, [r7, #4] - 8003992: 0a1b lsrs r3, r3, #8 - 8003994: b2db uxtb r3, r3 - 8003996: 72bb strb r3, [r7, #10] - data[3] = Cause & 0xFF; // - 8003998: 687b ldr r3, [r7, #4] - 800399a: b2db uxtb r3, r3 - 800399c: 72fb strb r3, [r7, #11] - - J_SendPacket(0x1A00, 4, 4, data); - 800399e: f107 0308 add.w r3, r7, #8 - 80039a2: 2204 movs r2, #4 - 80039a4: 2104 movs r1, #4 - 80039a6: f44f 50d0 mov.w r0, #6656 @ 0x1a00 - 80039aa: f000 fa8d bl 8003ec8 -} - 80039ae: bf00 nop - 80039b0: 3710 adds r7, #16 - 80039b2: 46bd mov sp, r7 - 80039b4: bd80 pop {r7, pc} - ... - -080039b8 : - -void GBT_SendCSD(){ - 80039b8: b580 push {r7, lr} - 80039ba: af00 add r7, sp, #0 - GBT_ChargerStop.chargerNumber = GBT_ChargerInfo.chargerNumber; - 80039bc: 4b0b ldr r3, [pc, #44] @ (80039ec ) - 80039be: f8d3 3001 ldr.w r3, [r3, #1] - 80039c2: 4a0b ldr r2, [pc, #44] @ (80039f0 ) - 80039c4: 6053 str r3, [r2, #4] - GBT_ChargerStop.outputEnergy = 0; //TODO Energy meters - 80039c6: 4b0a ldr r3, [pc, #40] @ (80039f0 ) - 80039c8: 2200 movs r2, #0 - 80039ca: 709a strb r2, [r3, #2] - 80039cc: 2200 movs r2, #0 - 80039ce: 70da strb r2, [r3, #3] - GBT_ChargerStop.chargingTime = GBT_ChargerCurrentStatus.chargingTime; - 80039d0: 4b08 ldr r3, [pc, #32] @ (80039f4 ) - 80039d2: 889b ldrh r3, [r3, #4] - 80039d4: b29a uxth r2, r3 - 80039d6: 4b06 ldr r3, [pc, #24] @ (80039f0 ) - 80039d8: 801a strh r2, [r3, #0] - J_SendPacket(0x1D00, 6, 7, (uint8_t *)&GBT_ChargerStop); - 80039da: 4b05 ldr r3, [pc, #20] @ (80039f0 ) - 80039dc: 2207 movs r2, #7 - 80039de: 2106 movs r1, #6 - 80039e0: f44f 50e8 mov.w r0, #7424 @ 0x1d00 - 80039e4: f000 fa70 bl 8003ec8 - -} - 80039e8: bf00 nop - 80039ea: bd80 pop {r7, pc} - 80039ec: 200002fc .word 0x200002fc - 80039f0: 20000378 .word 0x20000378 - 80039f4: 20000370 .word 0x20000370 - -080039f8 : - -void GBT_SendCEM(uint32_t ErrorCode){ - 80039f8: b580 push {r7, lr} - 80039fa: b084 sub sp, #16 - 80039fc: af00 add r7, sp, #0 - 80039fe: 6078 str r0, [r7, #4] - uint8_t data[8]; - data[0] = (ErrorCode>>24) & 0xFF; // Error - 8003a00: 687b ldr r3, [r7, #4] - 8003a02: 0e1b lsrs r3, r3, #24 - 8003a04: b2db uxtb r3, r3 - 8003a06: 723b strb r3, [r7, #8] - data[1] = (ErrorCode>>16) & 0xFF; // - 8003a08: 687b ldr r3, [r7, #4] - 8003a0a: 0c1b lsrs r3, r3, #16 - 8003a0c: b2db uxtb r3, r3 - 8003a0e: 727b strb r3, [r7, #9] - data[2] = (ErrorCode>>8) & 0xFF; // - 8003a10: 687b ldr r3, [r7, #4] - 8003a12: 0a1b lsrs r3, r3, #8 - 8003a14: b2db uxtb r3, r3 - 8003a16: 72bb strb r3, [r7, #10] - data[3] = ErrorCode & 0xFF; // - 8003a18: 687b ldr r3, [r7, #4] - 8003a1a: b2db uxtb r3, r3 - 8003a1c: 72fb strb r3, [r7, #11] - - J_SendPacket(0x1F00, 4, 4, data); - 8003a1e: f107 0308 add.w r3, r7, #8 - 8003a22: 2204 movs r2, #4 - 8003a24: 2104 movs r1, #4 - 8003a26: f44f 50f8 mov.w r0, #7936 @ 0x1f00 - 8003a2a: f000 fa4d bl 8003ec8 -} - 8003a2e: bf00 nop - 8003a30: 3710 adds r7, #16 - 8003a32: 46bd mov sp, r7 - 8003a34: bd80 pop {r7, pc} - ... - -08003a38 : - * Output - * EVENT_OUT - * EXTI -*/ -void MX_GPIO_Init(void) -{ - 8003a38: b580 push {r7, lr} - 8003a3a: b08a sub sp, #40 @ 0x28 - 8003a3c: af00 add r7, sp, #0 - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8003a3e: f107 0318 add.w r3, r7, #24 - 8003a42: 2200 movs r2, #0 - 8003a44: 601a str r2, [r3, #0] - 8003a46: 605a str r2, [r3, #4] - 8003a48: 609a str r2, [r3, #8] - 8003a4a: 60da str r2, [r3, #12] - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - 8003a4c: 4b53 ldr r3, [pc, #332] @ (8003b9c ) - 8003a4e: 699b ldr r3, [r3, #24] - 8003a50: 4a52 ldr r2, [pc, #328] @ (8003b9c ) - 8003a52: f043 0310 orr.w r3, r3, #16 - 8003a56: 6193 str r3, [r2, #24] - 8003a58: 4b50 ldr r3, [pc, #320] @ (8003b9c ) - 8003a5a: 699b ldr r3, [r3, #24] - 8003a5c: f003 0310 and.w r3, r3, #16 - 8003a60: 617b str r3, [r7, #20] - 8003a62: 697b ldr r3, [r7, #20] - __HAL_RCC_GPIOA_CLK_ENABLE(); - 8003a64: 4b4d ldr r3, [pc, #308] @ (8003b9c ) - 8003a66: 699b ldr r3, [r3, #24] - 8003a68: 4a4c ldr r2, [pc, #304] @ (8003b9c ) - 8003a6a: f043 0304 orr.w r3, r3, #4 - 8003a6e: 6193 str r3, [r2, #24] - 8003a70: 4b4a ldr r3, [pc, #296] @ (8003b9c ) - 8003a72: 699b ldr r3, [r3, #24] - 8003a74: f003 0304 and.w r3, r3, #4 - 8003a78: 613b str r3, [r7, #16] - 8003a7a: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 8003a7c: 4b47 ldr r3, [pc, #284] @ (8003b9c ) - 8003a7e: 699b ldr r3, [r3, #24] - 8003a80: 4a46 ldr r2, [pc, #280] @ (8003b9c ) - 8003a82: f043 0308 orr.w r3, r3, #8 - 8003a86: 6193 str r3, [r2, #24] - 8003a88: 4b44 ldr r3, [pc, #272] @ (8003b9c ) - 8003a8a: 699b ldr r3, [r3, #24] - 8003a8c: f003 0308 and.w r3, r3, #8 - 8003a90: 60fb str r3, [r7, #12] - 8003a92: 68fb ldr r3, [r7, #12] - __HAL_RCC_GPIOE_CLK_ENABLE(); - 8003a94: 4b41 ldr r3, [pc, #260] @ (8003b9c ) - 8003a96: 699b ldr r3, [r3, #24] - 8003a98: 4a40 ldr r2, [pc, #256] @ (8003b9c ) - 8003a9a: f043 0340 orr.w r3, r3, #64 @ 0x40 - 8003a9e: 6193 str r3, [r2, #24] - 8003aa0: 4b3e ldr r3, [pc, #248] @ (8003b9c ) - 8003aa2: 699b ldr r3, [r3, #24] - 8003aa4: f003 0340 and.w r3, r3, #64 @ 0x40 - 8003aa8: 60bb str r3, [r7, #8] - 8003aaa: 68bb ldr r3, [r7, #8] - __HAL_RCC_GPIOD_CLK_ENABLE(); - 8003aac: 4b3b ldr r3, [pc, #236] @ (8003b9c ) - 8003aae: 699b ldr r3, [r3, #24] - 8003ab0: 4a3a ldr r2, [pc, #232] @ (8003b9c ) - 8003ab2: f043 0320 orr.w r3, r3, #32 - 8003ab6: 6193 str r3, [r2, #24] - 8003ab8: 4b38 ldr r3, [pc, #224] @ (8003b9c ) - 8003aba: 699b ldr r3, [r3, #24] - 8003abc: f003 0320 and.w r3, r3, #32 - 8003ac0: 607b str r3, [r7, #4] - 8003ac2: 687b ldr r3, [r7, #4] - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); - 8003ac4: 2200 movs r2, #0 - 8003ac6: 2130 movs r1, #48 @ 0x30 - 8003ac8: 4835 ldr r0, [pc, #212] @ (8003ba0 ) - 8003aca: f003 fe7c bl 80077c6 - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); - 8003ace: 2200 movs r2, #0 - 8003ad0: f44f 4100 mov.w r1, #32768 @ 0x8000 - 8003ad4: 4833 ldr r0, [pc, #204] @ (8003ba4 ) - 8003ad6: f003 fe76 bl 80077c6 - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); - 8003ada: 2200 movs r2, #0 - 8003adc: 2110 movs r1, #16 - 8003ade: 4832 ldr r0, [pc, #200] @ (8003ba8 ) - 8003ae0: f003 fe71 bl 80077c6 - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, GPIO_PIN_RESET); - 8003ae4: 2200 movs r2, #0 - 8003ae6: 2110 movs r1, #16 - 8003ae8: 4830 ldr r0, [pc, #192] @ (8003bac ) - 8003aea: f003 fe6c bl 80077c6 - - /*Configure GPIO pins : PCPin PCPin */ - GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; - 8003aee: 2330 movs r3, #48 @ 0x30 - 8003af0: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8003af2: 2301 movs r3, #1 - 8003af4: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003af6: 2300 movs r3, #0 - 8003af8: 623b str r3, [r7, #32] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8003afa: 2302 movs r3, #2 - 8003afc: 627b str r3, [r7, #36] @ 0x24 - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8003afe: f107 0318 add.w r3, r7, #24 - 8003b02: 4619 mov r1, r3 - 8003b04: 4826 ldr r0, [pc, #152] @ (8003ba0 ) - 8003b06: f003 fcc3 bl 8007490 - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = LOCK_FB_Pin; - 8003b0a: f44f 7300 mov.w r3, #512 @ 0x200 - 8003b0e: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8003b10: 2300 movs r3, #0 - 8003b12: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003b14: 2300 movs r3, #0 - 8003b16: 623b str r3, [r7, #32] - HAL_GPIO_Init(LOCK_FB_GPIO_Port, &GPIO_InitStruct); - 8003b18: f107 0318 add.w r3, r7, #24 - 8003b1c: 4619 mov r1, r3 - 8003b1e: 4821 ldr r0, [pc, #132] @ (8003ba4 ) - 8003b20: f003 fcb6 bl 8007490 - - /*Configure GPIO pins : PEPin PEPin */ - GPIO_InitStruct.Pin = ADDR_0_Pin|ADDR_1_Pin; - 8003b24: f44f 6340 mov.w r3, #3072 @ 0xc00 - 8003b28: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8003b2a: 2300 movs r3, #0 - 8003b2c: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_PULLUP; - 8003b2e: 2301 movs r3, #1 - 8003b30: 623b str r3, [r7, #32] - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - 8003b32: f107 0318 add.w r3, r7, #24 - 8003b36: 4619 mov r1, r3 - 8003b38: 481a ldr r0, [pc, #104] @ (8003ba4 ) - 8003b3a: f003 fca9 bl 8007490 - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = RELAY_CC_Pin; - 8003b3e: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8003b42: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8003b44: 2301 movs r3, #1 - 8003b46: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003b48: 2300 movs r3, #0 - 8003b4a: 623b str r3, [r7, #32] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8003b4c: 2302 movs r3, #2 - 8003b4e: 627b str r3, [r7, #36] @ 0x24 - HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); - 8003b50: f107 0318 add.w r3, r7, #24 - 8003b54: 4619 mov r1, r3 - 8003b56: 4813 ldr r0, [pc, #76] @ (8003ba4 ) - 8003b58: f003 fc9a bl 8007490 - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USART2_DIR_Pin; - 8003b5c: 2310 movs r3, #16 - 8003b5e: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8003b60: 2301 movs r3, #1 - 8003b62: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003b64: 2300 movs r3, #0 - 8003b66: 623b str r3, [r7, #32] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8003b68: 2302 movs r3, #2 - 8003b6a: 627b str r3, [r7, #36] @ 0x24 - HAL_GPIO_Init(USART2_DIR_GPIO_Port, &GPIO_InitStruct); - 8003b6c: f107 0318 add.w r3, r7, #24 - 8003b70: 4619 mov r1, r3 - 8003b72: 480d ldr r0, [pc, #52] @ (8003ba8 ) - 8003b74: f003 fc8c bl 8007490 - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = RELAY_AUX_Pin; - 8003b78: 2310 movs r3, #16 - 8003b7a: 61bb str r3, [r7, #24] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8003b7c: 2301 movs r3, #1 - 8003b7e: 61fb str r3, [r7, #28] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003b80: 2300 movs r3, #0 - 8003b82: 623b str r3, [r7, #32] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8003b84: 2302 movs r3, #2 - 8003b86: 627b str r3, [r7, #36] @ 0x24 - HAL_GPIO_Init(RELAY_AUX_GPIO_Port, &GPIO_InitStruct); - 8003b88: f107 0318 add.w r3, r7, #24 - 8003b8c: 4619 mov r1, r3 - 8003b8e: 4807 ldr r0, [pc, #28] @ (8003bac ) - 8003b90: f003 fc7e bl 8007490 - -} - 8003b94: bf00 nop - 8003b96: 3728 adds r7, #40 @ 0x28 - 8003b98: 46bd mov sp, r7 - 8003b9a: bd80 pop {r7, pc} - 8003b9c: 40021000 .word 0x40021000 - 8003ba0: 40011000 .word 0x40011000 - 8003ba4: 40011800 .word 0x40011800 - 8003ba8: 40011400 .word 0x40011400 - 8003bac: 40010c00 .word 0x40010c00 - -08003bb0 : -extern GBT_BCL_t GBT_CurrPower; - -j_receive_t j_rx; - -void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - 8003bb0: b590 push {r4, r7, lr} - 8003bb2: b0cd sub sp, #308 @ 0x134 - 8003bb4: af40 add r7, sp, #256 @ 0x100 - 8003bb6: 6078 str r0, [r7, #4] - CAN_RxHeaderTypeDef RxHeader; - uint8_t RxData[8] = {0,}; - 8003bb8: 2300 movs r3, #0 - 8003bba: 60fb str r3, [r7, #12] - 8003bbc: 2300 movs r3, #0 - 8003bbe: 613b str r3, [r7, #16] - - if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) == HAL_OK) - 8003bc0: f107 030c add.w r3, r7, #12 - 8003bc4: f107 0214 add.w r2, r7, #20 - 8003bc8: 2100 movs r1, #0 - 8003bca: 6878 ldr r0, [r7, #4] - 8003bcc: f002 fedb bl 8006986 - 8003bd0: 4603 mov r3, r0 - 8003bd2: 2b00 cmp r3, #0 - 8003bd4: f040 8152 bne.w 8003e7c - { - if((RxHeader.ExtId & 0x00FFFF) == ((J_ID_SE << 8) | J_ID_EV)){ // SA, DA match - 8003bd8: 69bb ldr r3, [r7, #24] - 8003bda: b29b uxth r3, r3 - 8003bdc: f245 62f4 movw r2, #22260 @ 0x56f4 - 8003be0: 4293 cmp r3, r2 - 8003be2: f040 814b bne.w 8003e7c - switch ((RxHeader.ExtId>>8) & 0x00FF00){ - 8003be6: 69bb ldr r3, [r7, #24] - 8003be8: 0a1b lsrs r3, r3, #8 - 8003bea: f403 437f and.w r3, r3, #65280 @ 0xff00 - 8003bee: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 - 8003bf2: d013 beq.n 8003c1c - 8003bf4: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 - 8003bf8: f200 810b bhi.w 8003e12 - 8003bfc: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 - 8003c00: d056 beq.n 8003cb0 - 8003c02: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 - 8003c06: f200 8104 bhi.w 8003e12 - 8003c0a: f5b3 5fc8 cmp.w r3, #6400 @ 0x1900 - 8003c0e: f000 80dc beq.w 8003dca - 8003c12: f5b3 5ff0 cmp.w r3, #7680 @ 0x1e00 - 8003c16: f000 80b5 beq.w 8003d84 - 8003c1a: e0fa b.n 8003e12 - - case 0xEC00: //PGN Connection Management Message - if(RxData[0] == 16){ //Request to Send - 8003c1c: 7b3b ldrb r3, [r7, #12] - 8003c1e: 2b10 cmp r3, #16 - 8003c20: d13d bne.n 8003c9e - /* Set the RTS values */ - j_rx.size = RxData[1] | (RxData[2]<<8); - 8003c22: 7b7b ldrb r3, [r7, #13] - 8003c24: b21a sxth r2, r3 - 8003c26: 7bbb ldrb r3, [r7, #14] - 8003c28: 021b lsls r3, r3, #8 - 8003c2a: b21b sxth r3, r3 - 8003c2c: 4313 orrs r3, r2 - 8003c2e: b21b sxth r3, r3 - 8003c30: b29a uxth r2, r3 - 8003c32: 4b94 ldr r3, [pc, #592] @ (8003e84 ) - 8003c34: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 - j_rx.packet = 1; - 8003c38: 4b92 ldr r3, [pc, #584] @ (8003e84 ) - 8003c3a: 2201 movs r2, #1 - 8003c3c: f883 2107 strb.w r2, [r3, #263] @ 0x107 - j_rx.packets = RxData[3]; - 8003c40: 7bfa ldrb r2, [r7, #15] - 8003c42: 4b90 ldr r3, [pc, #576] @ (8003e84 ) - 8003c44: f883 2106 strb.w r2, [r3, #262] @ 0x106 - j_rx.step = 2; //TODO - 8003c48: 4b8e ldr r3, [pc, #568] @ (8003e84 ) - 8003c4a: 2202 movs r2, #2 - 8003c4c: f883 2108 strb.w r2, [r3, #264] @ 0x108 - j_rx.step_cts_remain = j_rx.step; - 8003c50: 4b8c ldr r3, [pc, #560] @ (8003e84 ) - 8003c52: f893 2108 ldrb.w r2, [r3, #264] @ 0x108 - 8003c56: 4b8b ldr r3, [pc, #556] @ (8003e84 ) - 8003c58: f883 2109 strb.w r2, [r3, #265] @ 0x109 - j_rx.PGN = (RxData[7] << 16) | (RxData[6] << 8) | RxData[5]; - 8003c5c: 7cfb ldrb r3, [r7, #19] - 8003c5e: 041a lsls r2, r3, #16 - 8003c60: 7cbb ldrb r3, [r7, #18] - 8003c62: 021b lsls r3, r3, #8 - 8003c64: 4313 orrs r3, r2 - 8003c66: 7c7a ldrb r2, [r7, #17] - 8003c68: 4313 orrs r3, r2 - 8003c6a: 461a mov r2, r3 - 8003c6c: 4b85 ldr r3, [pc, #532] @ (8003e84 ) - 8003c6e: f8c3 2100 str.w r2, [r3, #256] @ 0x100 - if(j_rx.size<256) { //TODO: valid check - 8003c72: 4b84 ldr r3, [pc, #528] @ (8003e84 ) - 8003c74: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 - 8003c78: 2bff cmp r3, #255 @ 0xff - 8003c7a: d810 bhi.n 8003c9e - J_SendCTS(j_rx); - 8003c7c: 4c81 ldr r4, [pc, #516] @ (8003e84 ) - 8003c7e: 4668 mov r0, sp - 8003c80: f104 0310 add.w r3, r4, #16 - 8003c84: f44f 7280 mov.w r2, #256 @ 0x100 - 8003c88: 4619 mov r1, r3 - 8003c8a: f006 fef4 bl 800aa76 - 8003c8e: e894 000f ldmia.w r4, {r0, r1, r2, r3} - 8003c92: f000 f941 bl 8003f18 - j_rx.state = 1; - 8003c96: 4b7b ldr r3, [pc, #492] @ (8003e84 ) - 8003c98: 2201 movs r2, #1 - 8003c9a: f883 210a strb.w r2, [r3, #266] @ 0x10a - } - } - if(RxData[0] == 255){ //Connection Abort - 8003c9e: 7b3b ldrb r3, [r7, #12] - 8003ca0: 2bff cmp r3, #255 @ 0xff - 8003ca2: f040 80e6 bne.w 8003e72 - j_rx.state = 0; - 8003ca6: 4b77 ldr r3, [pc, #476] @ (8003e84 ) - 8003ca8: 2200 movs r2, #0 - 8003caa: f883 210a strb.w r2, [r3, #266] @ 0x10a - * 1CECF456 11 02 01 FF FF 00 02 00 - * 1CEB56F4 01 01 01 00 03 46 05 40 - * 1CEC56F4 FF FF FF FF FF 00 00 00 - */ - - break; - 8003cae: e0e0 b.n 8003e72 - - case 0xEB00: //PGN Data Message - if(j_rx.state != 1) break; - 8003cb0: 4b74 ldr r3, [pc, #464] @ (8003e84 ) - 8003cb2: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8003cb6: 2b01 cmp r3, #1 - 8003cb8: f040 80dd bne.w 8003e76 - if((RxData[0]>0) && (RxData[0]<35)){ //Array limit check - 8003cbc: 7b3b ldrb r3, [r7, #12] - 8003cbe: 2b00 cmp r3, #0 - 8003cc0: f000 80db beq.w 8003e7a - 8003cc4: 7b3b ldrb r3, [r7, #12] - 8003cc6: 2b22 cmp r3, #34 @ 0x22 - 8003cc8: f200 80d7 bhi.w 8003e7a - if(j_rx.packet == RxData[0]){ //step check - 8003ccc: 4b6d ldr r3, [pc, #436] @ (8003e84 ) - 8003cce: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 - 8003cd2: 7b3b ldrb r3, [r7, #12] - 8003cd4: 429a cmp r2, r3 - 8003cd6: f040 80d0 bne.w 8003e7a - memcpy (&j_rx.data[(RxData[0]-1)*7], &RxData[1],7); - 8003cda: 7b3b ldrb r3, [r7, #12] - 8003cdc: 1e5a subs r2, r3, #1 - 8003cde: 4613 mov r3, r2 - 8003ce0: 00db lsls r3, r3, #3 - 8003ce2: 1a9b subs r3, r3, r2 - 8003ce4: 4a67 ldr r2, [pc, #412] @ (8003e84 ) - 8003ce6: 1898 adds r0, r3, r2 - 8003ce8: f107 030c add.w r3, r7, #12 - 8003cec: 3301 adds r3, #1 - 8003cee: 2207 movs r2, #7 - 8003cf0: 4619 mov r1, r3 - 8003cf2: f006 fec0 bl 800aa76 - j_rx.packet++; - 8003cf6: 4b63 ldr r3, [pc, #396] @ (8003e84 ) - 8003cf8: f893 3107 ldrb.w r3, [r3, #263] @ 0x107 - 8003cfc: 3301 adds r3, #1 - 8003cfe: b2da uxtb r2, r3 - 8003d00: 4b60 ldr r3, [pc, #384] @ (8003e84 ) - 8003d02: f883 2107 strb.w r2, [r3, #263] @ 0x107 - if(j_rx.packet > j_rx.packets){ - 8003d06: 4b5f ldr r3, [pc, #380] @ (8003e84 ) - 8003d08: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 - 8003d0c: 4b5d ldr r3, [pc, #372] @ (8003e84 ) - 8003d0e: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 - 8003d12: 429a cmp r2, r3 - 8003d14: d911 bls.n 8003d3a - //End of transmission - J_SendACK(j_rx); - 8003d16: 4c5b ldr r4, [pc, #364] @ (8003e84 ) - 8003d18: 4668 mov r0, sp - 8003d1a: f104 0310 add.w r3, r4, #16 - 8003d1e: f44f 7280 mov.w r2, #256 @ 0x100 - 8003d22: 4619 mov r1, r3 - 8003d24: f006 fea7 bl 800aa76 - 8003d28: e894 000f ldmia.w r4, {r0, r1, r2, r3} - 8003d2c: f000 f93a bl 8003fa4 - - j_rx.state = 2; - 8003d30: 4b54 ldr r3, [pc, #336] @ (8003e84 ) - 8003d32: 2202 movs r2, #2 - 8003d34: f883 210a strb.w r2, [r3, #266] @ 0x10a - j_rx.step_cts_remain = 2; - } - } - } - } - break; - 8003d38: e09f b.n 8003e7a - if(j_rx.step_cts_remain > 0) j_rx.step_cts_remain--; - 8003d3a: 4b52 ldr r3, [pc, #328] @ (8003e84 ) - 8003d3c: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 - 8003d40: 2b00 cmp r3, #0 - 8003d42: d007 beq.n 8003d54 - 8003d44: 4b4f ldr r3, [pc, #316] @ (8003e84 ) - 8003d46: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 - 8003d4a: 3b01 subs r3, #1 - 8003d4c: b2da uxtb r2, r3 - 8003d4e: 4b4d ldr r3, [pc, #308] @ (8003e84 ) - 8003d50: f883 2109 strb.w r2, [r3, #265] @ 0x109 - if(j_rx.step_cts_remain == 0){ - 8003d54: 4b4b ldr r3, [pc, #300] @ (8003e84 ) - 8003d56: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 - 8003d5a: 2b00 cmp r3, #0 - 8003d5c: f040 808d bne.w 8003e7a - J_SendCTS(j_rx); - 8003d60: 4c48 ldr r4, [pc, #288] @ (8003e84 ) - 8003d62: 4668 mov r0, sp - 8003d64: f104 0310 add.w r3, r4, #16 - 8003d68: f44f 7280 mov.w r2, #256 @ 0x100 - 8003d6c: 4619 mov r1, r3 - 8003d6e: f006 fe82 bl 800aa76 - 8003d72: e894 000f ldmia.w r4, {r0, r1, r2, r3} - 8003d76: f000 f8cf bl 8003f18 - j_rx.step_cts_remain = 2; - 8003d7a: 4b42 ldr r3, [pc, #264] @ (8003e84 ) - 8003d7c: 2202 movs r2, #2 - 8003d7e: f883 2109 strb.w r2, [r3, #265] @ 0x109 - break; - 8003d82: e07a b.n 8003e7a - - case 0x1E00: //PGN BEM (ERROR) - //Error force stop - EDCAN_printf(LOG_WARN, "BEM Received, force stopping...\n"); - 8003d84: 4940 ldr r1, [pc, #256] @ (8003e88 ) - 8003d86: 2004 movs r0, #4 - 8003d88: f000 ffc2 bl 8004d10 - EDCAN_printf(LOG_WARN, "BEM: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); - 8003d8c: 7b3b ldrb r3, [r7, #12] - 8003d8e: 4619 mov r1, r3 - 8003d90: 7b7b ldrb r3, [r7, #13] - 8003d92: 4618 mov r0, r3 - 8003d94: 7bbb ldrb r3, [r7, #14] - 8003d96: 7bfa ldrb r2, [r7, #15] - 8003d98: 9201 str r2, [sp, #4] - 8003d9a: 9300 str r3, [sp, #0] - 8003d9c: 4603 mov r3, r0 - 8003d9e: 460a mov r2, r1 - 8003da0: 493a ldr r1, [pc, #232] @ (8003e8c ) - 8003da2: 2004 movs r0, #4 - 8003da4: f000 ffb4 bl 8004d10 - EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); - 8003da8: 7c3b ldrb r3, [r7, #16] - 8003daa: 4619 mov r1, r3 - 8003dac: 7c7b ldrb r3, [r7, #17] - 8003dae: 4618 mov r0, r3 - 8003db0: 7cbb ldrb r3, [r7, #18] - 8003db2: 7cfa ldrb r2, [r7, #19] - 8003db4: 9201 str r2, [sp, #4] - 8003db6: 9300 str r3, [sp, #0] - 8003db8: 4603 mov r3, r0 - 8003dba: 460a mov r2, r1 - 8003dbc: 4934 ldr r1, [pc, #208] @ (8003e90 ) - 8003dbe: 2004 movs r0, #4 - 8003dc0: f000 ffa6 bl 8004d10 - GBT_ForceStop(); - 8003dc4: f7fe fd0c bl 80027e0 - break; - 8003dc8: e058 b.n 8003e7c - - case 0x1900: //PGN BST (STOP) - //Normal stop - EDCAN_printf(LOG_WARN, "BST Received, stopping...\n"); - 8003dca: 4932 ldr r1, [pc, #200] @ (8003e94 ) - 8003dcc: 2004 movs r0, #4 - 8003dce: f000 ff9f bl 8004d10 - EDCAN_printf(LOG_WARN, "BST: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); - 8003dd2: 7b3b ldrb r3, [r7, #12] - 8003dd4: 4619 mov r1, r3 - 8003dd6: 7b7b ldrb r3, [r7, #13] - 8003dd8: 4618 mov r0, r3 - 8003dda: 7bbb ldrb r3, [r7, #14] - 8003ddc: 7bfa ldrb r2, [r7, #15] - 8003dde: 9201 str r2, [sp, #4] - 8003de0: 9300 str r3, [sp, #0] - 8003de2: 4603 mov r3, r0 - 8003de4: 460a mov r2, r1 - 8003de6: 492c ldr r1, [pc, #176] @ (8003e98 ) - 8003de8: 2004 movs r0, #4 - 8003dea: f000 ff91 bl 8004d10 - EDCAN_printf(LOG_WARN, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); - 8003dee: 7c3b ldrb r3, [r7, #16] - 8003df0: 4619 mov r1, r3 - 8003df2: 7c7b ldrb r3, [r7, #17] - 8003df4: 4618 mov r0, r3 - 8003df6: 7cbb ldrb r3, [r7, #18] - 8003df8: 7cfa ldrb r2, [r7, #19] - 8003dfa: 9201 str r2, [sp, #4] - 8003dfc: 9300 str r3, [sp, #0] - 8003dfe: 4603 mov r3, r0 - 8003e00: 460a mov r2, r1 - 8003e02: 4923 ldr r1, [pc, #140] @ (8003e90 ) - 8003e04: 2004 movs r0, #4 - 8003e06: f000 ff83 bl 8004d10 - GBT_Stop(GBT_CST_BMS_ACTIVELY_SUSPENDS); - 8003e0a: 4824 ldr r0, [pc, #144] @ (8003e9c ) - 8003e0c: f7fe fcba bl 8002784 - - break; - 8003e10: e034 b.n 8003e7c - - default: - if(j_rx.state == 0){//TODO protections - 8003e12: 4b1c ldr r3, [pc, #112] @ (8003e84 ) - 8003e14: f893 310a ldrb.w r3, [r3, #266] @ 0x10a - 8003e18: 2b00 cmp r3, #0 - 8003e1a: d12f bne.n 8003e7c - //Short packet - j_rx.size = RxHeader.DLC; - 8003e1c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8003e1e: b29a uxth r2, r3 - 8003e20: 4b18 ldr r3, [pc, #96] @ (8003e84 ) - 8003e22: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 - j_rx.packet = 1; - 8003e26: 4b17 ldr r3, [pc, #92] @ (8003e84 ) - 8003e28: 2201 movs r2, #1 - 8003e2a: f883 2107 strb.w r2, [r3, #263] @ 0x107 - j_rx.packets = 1; - 8003e2e: 4b15 ldr r3, [pc, #84] @ (8003e84 ) - 8003e30: 2201 movs r2, #1 - 8003e32: f883 2106 strb.w r2, [r3, #262] @ 0x106 - j_rx.step = 1; - 8003e36: 4b13 ldr r3, [pc, #76] @ (8003e84 ) - 8003e38: 2201 movs r2, #1 - 8003e3a: f883 2108 strb.w r2, [r3, #264] @ 0x108 - j_rx.step_cts_remain = 0; - 8003e3e: 4b11 ldr r3, [pc, #68] @ (8003e84 ) - 8003e40: 2200 movs r2, #0 - 8003e42: f883 2109 strb.w r2, [r3, #265] @ 0x109 - j_rx.PGN = (RxHeader.ExtId>>8) & 0x00FF00; - 8003e46: 69bb ldr r3, [r7, #24] - 8003e48: 0a1b lsrs r3, r3, #8 - 8003e4a: f403 437f and.w r3, r3, #65280 @ 0xff00 - 8003e4e: 4a0d ldr r2, [pc, #52] @ (8003e84 ) - 8003e50: f8c2 3100 str.w r3, [r2, #256] @ 0x100 - j_rx.state = 2; - 8003e54: 4b0b ldr r3, [pc, #44] @ (8003e84 ) - 8003e56: 2202 movs r2, #2 - 8003e58: f883 210a strb.w r2, [r3, #266] @ 0x10a - memcpy (j_rx.data, RxData, j_rx.size); - 8003e5c: 4b09 ldr r3, [pc, #36] @ (8003e84 ) - 8003e5e: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 - 8003e62: 461a mov r2, r3 - 8003e64: f107 030c add.w r3, r7, #12 - 8003e68: 4619 mov r1, r3 - 8003e6a: 4806 ldr r0, [pc, #24] @ (8003e84 ) - 8003e6c: f006 fe03 bl 800aa76 - } - } - } - } -} - 8003e70: e004 b.n 8003e7c - break; - 8003e72: bf00 nop - 8003e74: e002 b.n 8003e7c - if(j_rx.state != 1) break; - 8003e76: bf00 nop - 8003e78: e000 b.n 8003e7c - break; - 8003e7a: bf00 nop -} - 8003e7c: bf00 nop - 8003e7e: 3734 adds r7, #52 @ 0x34 - 8003e80: 46bd mov sp, r7 - 8003e82: bd90 pop {r4, r7, pc} - 8003e84: 200004bc .word 0x200004bc - 8003e88: 0800deac .word 0x0800deac - 8003e8c: 0800ded0 .word 0x0800ded0 - 8003e90: 0800deec .word 0x0800deec - 8003e94: 0800df04 .word 0x0800df04 - 8003e98: 0800df20 .word 0x0800df20 - 8003e9c: 4000f0f0 .word 0x4000f0f0 - -08003ea0 : - -void GBT_CAN_ReInit(){ - 8003ea0: b580 push {r7, lr} - 8003ea2: af00 add r7, sp, #0 - HAL_CAN_Stop(&hcan1); - 8003ea4: 4807 ldr r0, [pc, #28] @ (8003ec4 ) - 8003ea6: f002 fc17 bl 80066d8 - MX_CAN1_Init(); - 8003eaa: f7fd fd2f bl 800190c - HAL_CAN_Start(&hcan1); - 8003eae: 4805 ldr r0, [pc, #20] @ (8003ec4 ) - 8003eb0: f002 fbce bl 8006650 - HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); - 8003eb4: 2102 movs r1, #2 - 8003eb6: 4803 ldr r0, [pc, #12] @ (8003ec4 ) - 8003eb8: f002 fe76 bl 8006ba8 - GBT_CAN_FilterInit(); - 8003ebc: f000 f8ac bl 8004018 -} - 8003ec0: bf00 nop - 8003ec2: bd80 pop {r7, pc} - 8003ec4: 20000288 .word 0x20000288 - -08003ec8 : - -void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ - 8003ec8: b580 push {r7, lr} - 8003eca: b08c sub sp, #48 @ 0x30 - 8003ecc: af00 add r7, sp, #0 - 8003ece: 60f8 str r0, [r7, #12] - 8003ed0: 607b str r3, [r7, #4] - 8003ed2: 460b mov r3, r1 - 8003ed4: 72fb strb r3, [r7, #11] - 8003ed6: 4613 mov r3, r2 - 8003ed8: 72bb strb r3, [r7, #10] - - CAN_TxHeaderTypeDef tx_header; - uint32_t tx_mailbox; - - tx_header.ExtId = (pri << 26) | (PGN << 8) | (J_ID_EV << 8) | J_ID_SE; - 8003eda: 7afb ldrb r3, [r7, #11] - 8003edc: 069a lsls r2, r3, #26 - 8003ede: 68fb ldr r3, [r7, #12] - 8003ee0: 021b lsls r3, r3, #8 - 8003ee2: 4313 orrs r3, r2 - 8003ee4: f443 4374 orr.w r3, r3, #62464 @ 0xf400 - 8003ee8: f043 0356 orr.w r3, r3, #86 @ 0x56 - 8003eec: 61fb str r3, [r7, #28] - tx_header.RTR = CAN_RTR_DATA; - 8003eee: 2300 movs r3, #0 - 8003ef0: 627b str r3, [r7, #36] @ 0x24 - tx_header.IDE = CAN_ID_EXT; - 8003ef2: 2304 movs r3, #4 - 8003ef4: 623b str r3, [r7, #32] - tx_header.DLC = DLC; - 8003ef6: 7abb ldrb r3, [r7, #10] - 8003ef8: 62bb str r3, [r7, #40] @ 0x28 - - //TODO buffer wait - HAL_CAN_AddTxMessage(&hcan1, &tx_header, data, &tx_mailbox); - 8003efa: f107 0314 add.w r3, r7, #20 - 8003efe: f107 0118 add.w r1, r7, #24 - 8003f02: 687a ldr r2, [r7, #4] - 8003f04: 4803 ldr r0, [pc, #12] @ (8003f14 ) - 8003f06: f002 fc30 bl 800676a - //HAL_Delay(2); - -} - 8003f0a: bf00 nop - 8003f0c: 3730 adds r7, #48 @ 0x30 - 8003f0e: 46bd mov sp, r7 - 8003f10: bd80 pop {r7, pc} - 8003f12: bf00 nop - 8003f14: 20000288 .word 0x20000288 - -08003f18 : -//void J_SendPacketLong(){ -// //TODO (no need) -//} - -// J1939 sequence Clear To Send packet -void J_SendCTS(j_receive_t rx){ - 8003f18: b084 sub sp, #16 - 8003f1a: b580 push {r7, lr} - 8003f1c: b082 sub sp, #8 - 8003f1e: af00 add r7, sp, #0 - 8003f20: f107 0c10 add.w ip, r7, #16 - 8003f24: e88c 000f stmia.w ip, {r0, r1, r2, r3} - - //if(rx.packets <= rx.packet) return; TODO - uint8_t data[8]; - data[0] = 17; //CONTROL_BYTE_TP_CM_CTS - 8003f28: 2311 movs r3, #17 - 8003f2a: 703b strb r3, [r7, #0] - data[1] = rx.step;//total_number_of_packages_transmitted - 8003f2c: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 - 8003f30: 707b strb r3, [r7, #1] - if (rx.step > (rx.packets - rx.packet+1)) data[1] = rx.packets - rx.packet+1; - 8003f32: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 - 8003f36: 461a mov r2, r3 - 8003f38: f897 3116 ldrb.w r3, [r7, #278] @ 0x116 - 8003f3c: 4619 mov r1, r3 - 8003f3e: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 - 8003f42: 1acb subs r3, r1, r3 - 8003f44: 3301 adds r3, #1 - 8003f46: 429a cmp r2, r3 - 8003f48: dd08 ble.n 8003f5c - 8003f4a: f897 2116 ldrb.w r2, [r7, #278] @ 0x116 - 8003f4e: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 - 8003f52: 1ad3 subs r3, r2, r3 - 8003f54: b2db uxtb r3, r3 - 8003f56: 3301 adds r3, #1 - 8003f58: b2db uxtb r3, r3 - 8003f5a: 707b strb r3, [r7, #1] - data[2] = rx.packet;//next_packet_number_transmitted - 8003f5c: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 - 8003f60: 70bb strb r3, [r7, #2] - data[3] = 0xFF; /* Reserved */ - 8003f62: 23ff movs r3, #255 @ 0xff - 8003f64: 70fb strb r3, [r7, #3] - data[4] = 0xFF; - 8003f66: 23ff movs r3, #255 @ 0xff - 8003f68: 713b strb r3, [r7, #4] - data[5] = rx.PGN; - 8003f6a: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003f6e: b2db uxtb r3, r3 - 8003f70: 717b strb r3, [r7, #5] - data[6] = rx.PGN >> 8; - 8003f72: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003f76: 0a1b lsrs r3, r3, #8 - 8003f78: b2db uxtb r3, r3 - 8003f7a: 71bb strb r3, [r7, #6] - data[7] = rx.PGN >> 16; - 8003f7c: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003f80: 0c1b lsrs r3, r3, #16 - 8003f82: b2db uxtb r3, r3 - 8003f84: 71fb strb r3, [r7, #7] - - J_SendPacket(0x00EC00, 7, 8, data); - 8003f86: 463b mov r3, r7 - 8003f88: 2208 movs r2, #8 - 8003f8a: 2107 movs r1, #7 - 8003f8c: f44f 406c mov.w r0, #60416 @ 0xec00 - 8003f90: f7ff ff9a bl 8003ec8 -} - 8003f94: bf00 nop - 8003f96: 3708 adds r7, #8 - 8003f98: 46bd mov sp, r7 - 8003f9a: e8bd 4080 ldmia.w sp!, {r7, lr} - 8003f9e: b004 add sp, #16 - 8003fa0: 4770 bx lr - ... - -08003fa4 : - -// J1939 sequence ACK packet -void J_SendACK(j_receive_t rx){//uint32_t PGN, uint8_t step, uint8_t packet){ - 8003fa4: b084 sub sp, #16 - 8003fa6: b580 push {r7, lr} - 8003fa8: b082 sub sp, #8 - 8003faa: af00 add r7, sp, #0 - 8003fac: f107 0c10 add.w ip, r7, #16 - 8003fb0: e88c 000f stmia.w ip, {r0, r1, r2, r3} - - uint8_t data[8]; - data[0] = 19; //CONTROL_BYTE_TP_CM_ACK - 8003fb4: 2313 movs r3, #19 - 8003fb6: 703b strb r3, [r7, #0] - data[1] = j_rx.size; - 8003fb8: 4b16 ldr r3, [pc, #88] @ (8004014 ) - 8003fba: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 - 8003fbe: b2db uxtb r3, r3 - 8003fc0: 707b strb r3, [r7, #1] - data[2] = j_rx.size>>8; - 8003fc2: 4b14 ldr r3, [pc, #80] @ (8004014 ) - 8003fc4: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 - 8003fc8: 0a1b lsrs r3, r3, #8 - 8003fca: b29b uxth r3, r3 - 8003fcc: b2db uxtb r3, r3 - 8003fce: 70bb strb r3, [r7, #2] - data[3] = j_rx.packets; - 8003fd0: 4b10 ldr r3, [pc, #64] @ (8004014 ) - 8003fd2: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 - 8003fd6: 70fb strb r3, [r7, #3] - data[4] = 0xFF;//TODO - 8003fd8: 23ff movs r3, #255 @ 0xff - 8003fda: 713b strb r3, [r7, #4] - data[5] = rx.PGN; - 8003fdc: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003fe0: b2db uxtb r3, r3 - 8003fe2: 717b strb r3, [r7, #5] - data[6] = rx.PGN >> 8; - 8003fe4: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003fe8: 0a1b lsrs r3, r3, #8 - 8003fea: b2db uxtb r3, r3 - 8003fec: 71bb strb r3, [r7, #6] - data[7] = rx.PGN >> 16; - 8003fee: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 - 8003ff2: 0c1b lsrs r3, r3, #16 - 8003ff4: b2db uxtb r3, r3 - 8003ff6: 71fb strb r3, [r7, #7] - - J_SendPacket(0x00EC00, 7, 8, data); - 8003ff8: 463b mov r3, r7 - 8003ffa: 2208 movs r2, #8 - 8003ffc: 2107 movs r1, #7 - 8003ffe: f44f 406c mov.w r0, #60416 @ 0xec00 - 8004002: f7ff ff61 bl 8003ec8 -} - 8004006: bf00 nop - 8004008: 3708 adds r7, #8 - 800400a: 46bd mov sp, r7 - 800400c: e8bd 4080 ldmia.w sp!, {r7, lr} - 8004010: b004 add sp, #16 - 8004012: 4770 bx lr - 8004014: 200004bc .word 0x200004bc - -08004018 : - -void GBT_CAN_FilterInit(){ - 8004018: b580 push {r7, lr} - 800401a: b08a sub sp, #40 @ 0x28 - 800401c: af00 add r7, sp, #0 - CAN_FilterTypeDef sFilterConfig; - - sFilterConfig.FilterBank = 0; - 800401e: 2300 movs r3, #0 - 8004020: 617b str r3, [r7, #20] - sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; - 8004022: 2300 movs r3, #0 - 8004024: 61bb str r3, [r7, #24] - sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; - 8004026: 2301 movs r3, #1 - 8004028: 61fb str r3, [r7, #28] - sFilterConfig.FilterIdHigh = 0x0000; - 800402a: 2300 movs r3, #0 - 800402c: 603b str r3, [r7, #0] - sFilterConfig.FilterIdLow = 0x0000; - 800402e: 2300 movs r3, #0 - 8004030: 607b str r3, [r7, #4] - sFilterConfig.FilterMaskIdHigh = 0x0000; - 8004032: 2300 movs r3, #0 - 8004034: 60bb str r3, [r7, #8] - sFilterConfig.FilterMaskIdLow = 0x0000; - 8004036: 2300 movs r3, #0 - 8004038: 60fb str r3, [r7, #12] - sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; - 800403a: 2300 movs r3, #0 - 800403c: 613b str r3, [r7, #16] - sFilterConfig.FilterActivation = ENABLE; - 800403e: 2301 movs r3, #1 - 8004040: 623b str r3, [r7, #32] - //sFilterConfig.SlaveStartFilterBank = 14; - if(HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK) - 8004042: 463b mov r3, r7 - 8004044: 4619 mov r1, r3 - 8004046: 4806 ldr r0, [pc, #24] @ (8004060 ) - 8004048: f002 fa22 bl 8006490 - 800404c: 4603 mov r3, r0 - 800404e: 2b00 cmp r3, #0 - 8004050: d001 beq.n 8004056 - { - Error_Handler(); - 8004052: f000 ffc5 bl 8004fe0 - } - -} - 8004056: bf00 nop - 8004058: 3728 adds r7, #40 @ 0x28 - 800405a: 46bd mov sp, r7 - 800405c: bd80 pop {r7, pc} - 800405e: bf00 nop - 8004060: 20000288 .word 0x20000288 - -08004064 : -uint8_t LOCK_DELAY = 50; - -GBT_LockState_t GBT_LockState; - - -void GBT_ForceLock(uint8_t state){ - 8004064: b580 push {r7, lr} - 8004066: b082 sub sp, #8 - 8004068: af00 add r7, sp, #0 - 800406a: 4603 mov r3, r0 - 800406c: 71fb strb r3, [r7, #7] - if(LOCK_MOTOR_POLARITY){ - 800406e: 4b26 ldr r3, [pc, #152] @ (8004108 ) - 8004070: 781b ldrb r3, [r3, #0] - 8004072: 2b00 cmp r3, #0 - 8004074: d022 beq.n 80040bc - if(state){//LOCK - 8004076: 79fb ldrb r3, [r7, #7] - 8004078: 2b00 cmp r3, #0 - 800407a: d00f beq.n 800409c - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); - 800407c: 2201 movs r2, #1 - 800407e: 2120 movs r1, #32 - 8004080: 4822 ldr r0, [pc, #136] @ (800410c ) - 8004082: f003 fba0 bl 80077c6 - HAL_Delay(LOCK_DELAY); - 8004086: 4b22 ldr r3, [pc, #136] @ (8004110 ) - 8004088: 781b ldrb r3, [r3, #0] - 800408a: 4618 mov r0, r3 - 800408c: f001 fbdc bl 8005848 - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); - 8004090: 2200 movs r2, #0 - 8004092: 2120 movs r1, #32 - 8004094: 481d ldr r0, [pc, #116] @ (800410c ) - 8004096: f003 fb96 bl 80077c6 - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); - HAL_Delay(LOCK_DELAY); - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); - } - } -} - 800409a: e031 b.n 8004100 - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); - 800409c: 2201 movs r2, #1 - 800409e: 2110 movs r1, #16 - 80040a0: 481a ldr r0, [pc, #104] @ (800410c ) - 80040a2: f003 fb90 bl 80077c6 - HAL_Delay(LOCK_DELAY); - 80040a6: 4b1a ldr r3, [pc, #104] @ (8004110 ) - 80040a8: 781b ldrb r3, [r3, #0] - 80040aa: 4618 mov r0, r3 - 80040ac: f001 fbcc bl 8005848 - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); - 80040b0: 2200 movs r2, #0 - 80040b2: 2110 movs r1, #16 - 80040b4: 4815 ldr r0, [pc, #84] @ (800410c ) - 80040b6: f003 fb86 bl 80077c6 -} - 80040ba: e021 b.n 8004100 - if(state){//LOCK - 80040bc: 79fb ldrb r3, [r7, #7] - 80040be: 2b00 cmp r3, #0 - 80040c0: d00f beq.n 80040e2 - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); - 80040c2: 2201 movs r2, #1 - 80040c4: 2110 movs r1, #16 - 80040c6: 4811 ldr r0, [pc, #68] @ (800410c ) - 80040c8: f003 fb7d bl 80077c6 - HAL_Delay(LOCK_DELAY); - 80040cc: 4b10 ldr r3, [pc, #64] @ (8004110 ) - 80040ce: 781b ldrb r3, [r3, #0] - 80040d0: 4618 mov r0, r3 - 80040d2: f001 fbb9 bl 8005848 - HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); - 80040d6: 2200 movs r2, #0 - 80040d8: 2110 movs r1, #16 - 80040da: 480c ldr r0, [pc, #48] @ (800410c ) - 80040dc: f003 fb73 bl 80077c6 -} - 80040e0: e00e b.n 8004100 - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); - 80040e2: 2201 movs r2, #1 - 80040e4: 2120 movs r1, #32 - 80040e6: 4809 ldr r0, [pc, #36] @ (800410c ) - 80040e8: f003 fb6d bl 80077c6 - HAL_Delay(LOCK_DELAY); - 80040ec: 4b08 ldr r3, [pc, #32] @ (8004110 ) - 80040ee: 781b ldrb r3, [r3, #0] - 80040f0: 4618 mov r0, r3 - 80040f2: f001 fba9 bl 8005848 - HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); - 80040f6: 2200 movs r2, #0 - 80040f8: 2120 movs r1, #32 - 80040fa: 4804 ldr r0, [pc, #16] @ (800410c ) - 80040fc: f003 fb63 bl 80077c6 -} - 8004100: bf00 nop - 8004102: 3708 adds r7, #8 - 8004104: 46bd mov sp, r7 - 8004106: bd80 pop {r7, pc} - 8004108: 20000001 .word 0x20000001 - 800410c: 40011000 .word 0x40011000 - 8004110: 20000002 .word 0x20000002 - -08004114 : - -uint8_t GBT_LockGetState(){ - 8004114: b580 push {r7, lr} - 8004116: af00 add r7, sp, #0 - //1 = locked - //0 = unlocked - if(LOCK_POLARITY){ - 8004118: 4b0b ldr r3, [pc, #44] @ (8004148 ) - 800411a: 781b ldrb r3, [r3, #0] - 800411c: 2b00 cmp r3, #0 - 800411e: d006 beq.n 800412e - return HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); - 8004120: f44f 7100 mov.w r1, #512 @ 0x200 - 8004124: 4809 ldr r0, [pc, #36] @ (800414c ) - 8004126: f003 fb37 bl 8007798 - 800412a: 4603 mov r3, r0 - 800412c: e00a b.n 8004144 - }else{ - return !HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); - 800412e: f44f 7100 mov.w r1, #512 @ 0x200 - 8004132: 4806 ldr r0, [pc, #24] @ (800414c ) - 8004134: f003 fb30 bl 8007798 - 8004138: 4603 mov r3, r0 - 800413a: 2b00 cmp r3, #0 - 800413c: bf0c ite eq - 800413e: 2301 moveq r3, #1 - 8004140: 2300 movne r3, #0 - 8004142: b2db uxtb r3, r3 - - } -} - 8004144: 4618 mov r0, r3 - 8004146: bd80 pop {r7, pc} - 8004148: 20000000 .word 0x20000000 - 800414c: 40011800 .word 0x40011800 - -08004150 : - -void GBT_Lock(uint8_t state){ - 8004150: b480 push {r7} - 8004152: b083 sub sp, #12 - 8004154: af00 add r7, sp, #0 - 8004156: 4603 mov r3, r0 - 8004158: 71fb strb r3, [r7, #7] - GBT_LockState.demand = state; - 800415a: 4a04 ldr r2, [pc, #16] @ (800416c ) - 800415c: 79fb ldrb r3, [r7, #7] - 800415e: 7013 strb r3, [r2, #0] -} - 8004160: bf00 nop - 8004162: 370c adds r7, #12 - 8004164: 46bd mov sp, r7 - 8004166: bc80 pop {r7} - 8004168: 4770 bx lr - 800416a: bf00 nop - 800416c: 200005cc .word 0x200005cc - -08004170 : - -void GBT_ManageLock(){ - 8004170: b580 push {r7, lr} - 8004172: b082 sub sp, #8 - 8004174: af00 add r7, sp, #0 - uint8_t MAX_RETRIES = 5; - 8004176: 2305 movs r3, #5 - 8004178: 71bb strb r3, [r7, #6] - if (GBT_LockState.error) { - 800417a: 4b25 ldr r3, [pc, #148] @ (8004210 ) - 800417c: 785b ldrb r3, [r3, #1] - 800417e: 2b00 cmp r3, #0 - 8004180: d142 bne.n 8004208 - return; - } - - bool lock_is_open = GBT_LockGetState() == 0; - 8004182: f7ff ffc7 bl 8004114 - 8004186: 4603 mov r3, r0 - 8004188: 2b00 cmp r3, #0 - 800418a: bf0c ite eq - 800418c: 2301 moveq r3, #1 - 800418e: 2300 movne r3, #0 - 8004190: 717b strb r3, [r7, #5] - bool lock_should_be_open = GBT_LockState.demand == 0; - 8004192: 4b1f ldr r3, [pc, #124] @ (8004210 ) - 8004194: 781b ldrb r3, [r3, #0] - 8004196: 2b00 cmp r3, #0 - 8004198: bf0c ite eq - 800419a: 2301 moveq r3, #1 - 800419c: 2300 movne r3, #0 - 800419e: 713b strb r3, [r7, #4] - uint8_t retry_count = 0; - 80041a0: 2300 movs r3, #0 - 80041a2: 71fb strb r3, [r7, #7] - - if (lock_is_open != lock_should_be_open) { - 80041a4: 797a ldrb r2, [r7, #5] - 80041a6: 793b ldrb r3, [r7, #4] - 80041a8: 429a cmp r2, r3 - 80041aa: d02e beq.n 800420a - while (retry_count < MAX_RETRIES) { - 80041ac: e018 b.n 80041e0 - if (lock_should_be_open) { - 80041ae: 793b ldrb r3, [r7, #4] - 80041b0: 2b00 cmp r3, #0 - 80041b2: d003 beq.n 80041bc - GBT_ForceLock(0); - 80041b4: 2000 movs r0, #0 - 80041b6: f7ff ff55 bl 8004064 - 80041ba: e002 b.n 80041c2 - } else { - GBT_ForceLock(1); - 80041bc: 2001 movs r0, #1 - 80041be: f7ff ff51 bl 8004064 - } - - lock_is_open = GBT_LockGetState() == 0; - 80041c2: f7ff ffa7 bl 8004114 - 80041c6: 4603 mov r3, r0 - 80041c8: 2b00 cmp r3, #0 - 80041ca: bf0c ite eq - 80041cc: 2301 moveq r3, #1 - 80041ce: 2300 movne r3, #0 - 80041d0: 717b strb r3, [r7, #5] - - if (lock_is_open == lock_should_be_open) { - 80041d2: 797a ldrb r2, [r7, #5] - 80041d4: 793b ldrb r3, [r7, #4] - 80041d6: 429a cmp r2, r3 - 80041d8: d007 beq.n 80041ea - break; - } - - retry_count++; - 80041da: 79fb ldrb r3, [r7, #7] - 80041dc: 3301 adds r3, #1 - 80041de: 71fb strb r3, [r7, #7] - while (retry_count < MAX_RETRIES) { - 80041e0: 79fa ldrb r2, [r7, #7] - 80041e2: 79bb ldrb r3, [r7, #6] - 80041e4: 429a cmp r2, r3 - 80041e6: d3e2 bcc.n 80041ae - 80041e8: e000 b.n 80041ec - break; - 80041ea: bf00 nop - } - - if (retry_count >= MAX_RETRIES) { - 80041ec: 79fa ldrb r2, [r7, #7] - 80041ee: 79bb ldrb r3, [r7, #6] - 80041f0: 429a cmp r2, r3 - 80041f2: d30a bcc.n 800420a - GBT_LockState.error = 1; - 80041f4: 4b06 ldr r3, [pc, #24] @ (8004210 ) - 80041f6: 2201 movs r2, #1 - 80041f8: 705a strb r2, [r3, #1] - GBT_ForceLock(0); - 80041fa: 2000 movs r0, #0 - 80041fc: f7ff ff32 bl 8004064 - printf ("Lock error\n"); - 8004200: 4804 ldr r0, [pc, #16] @ (8004214 ) - 8004202: f005 ff23 bl 800a04c - 8004206: e000 b.n 800420a - return; - 8004208: bf00 nop - } - } -} - 800420a: 3708 adds r7, #8 - 800420c: 46bd mov sp, r7 - 800420e: bd80 pop {r7, pc} - 8004210: 200005cc .word 0x200005cc - 8004214: 0800df3c .word 0x0800df3c - -08004218 <__NVIC_SystemReset>: -{ - 8004218: b480 push {r7} - 800421a: af00 add r7, sp, #0 - __ASM volatile ("dsb 0xF":::"memory"); - 800421c: f3bf 8f4f dsb sy -} - 8004220: bf00 nop - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - 8004222: 4b06 ldr r3, [pc, #24] @ (800423c <__NVIC_SystemReset+0x24>) - 8004224: 68db ldr r3, [r3, #12] - 8004226: f403 62e0 and.w r2, r3, #1792 @ 0x700 - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 800422a: 4904 ldr r1, [pc, #16] @ (800423c <__NVIC_SystemReset+0x24>) - 800422c: 4b04 ldr r3, [pc, #16] @ (8004240 <__NVIC_SystemReset+0x28>) - 800422e: 4313 orrs r3, r2 - 8004230: 60cb str r3, [r1, #12] - __ASM volatile ("dsb 0xF":::"memory"); - 8004232: f3bf 8f4f dsb sy -} - 8004236: bf00 nop - __NOP(); - 8004238: bf00 nop - 800423a: e7fd b.n 8004238 <__NVIC_SystemReset+0x20> - 800423c: e000ed00 .word 0xe000ed00 - 8004240: 05fa0004 .word 0x05fa0004 - -08004244 : - -/** - * @brief CAN Interrupt Handler for EDCAN (CAN2) - * - */ -void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ - 8004244: b580 push {r7, lr} - 8004246: b082 sub sp, #8 - 8004248: af00 add r7, sp, #0 - 800424a: 6078 str r0, [r7, #4] - if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) - 800424c: 4b21 ldr r3, [pc, #132] @ (80042d4 ) - 800424e: 4a22 ldr r2, [pc, #136] @ (80042d8 ) - 8004250: 2101 movs r1, #1 - 8004252: 6878 ldr r0, [r7, #4] - 8004254: f002 fb97 bl 8006986 - 8004258: 4603 mov r3, r0 - 800425a: 2b00 cmp r3, #0 - 800425c: d136 bne.n 80042cc - { - memcpy(&RxFrame.ExtID, &RxHeader.ExtId, sizeof(RxFrame.ExtID)); - 800425e: 4b1e ldr r3, [pc, #120] @ (80042d8 ) - 8004260: 685b ldr r3, [r3, #4] - 8004262: 4a1e ldr r2, [pc, #120] @ (80042dc ) - 8004264: 6013 str r3, [r2, #0] - RxFrame.DLC = RxHeader.DLC; - 8004266: 4b1c ldr r3, [pc, #112] @ (80042d8 ) - 8004268: 691b ldr r3, [r3, #16] - 800426a: b2da uxtb r2, r3 - 800426c: 4b1b ldr r3, [pc, #108] @ (80042dc ) - 800426e: 731a strb r2, [r3, #12] - memcpy(RxFrame.data, RxData, RxHeader.DLC); - 8004270: 4b19 ldr r3, [pc, #100] @ (80042d8 ) - 8004272: 691b ldr r3, [r3, #16] - 8004274: 461a mov r2, r3 - 8004276: 4917 ldr r1, [pc, #92] @ (80042d4 ) - 8004278: 4819 ldr r0, [pc, #100] @ (80042e0 ) - 800427a: f006 fbfc bl 800aa76 - - if((RxFrame.ExtID.DestinationID == ED_OwnID) || (RxFrame.ExtID.DestinationID == 0xFF) || (RxFrame.ExtID.DestinationID == ED_SecondID)){ - 800427e: 4b17 ldr r3, [pc, #92] @ (80042dc ) - 8004280: 781a ldrb r2, [r3, #0] - 8004282: 4b18 ldr r3, [pc, #96] @ (80042e4 ) - 8004284: 781b ldrb r3, [r3, #0] - 8004286: 429a cmp r2, r3 - 8004288: d009 beq.n 800429e - 800428a: 4b14 ldr r3, [pc, #80] @ (80042dc ) - 800428c: 781b ldrb r3, [r3, #0] - 800428e: 2bff cmp r3, #255 @ 0xff - 8004290: d005 beq.n 800429e - 8004292: 4b12 ldr r3, [pc, #72] @ (80042dc ) - 8004294: 781a ldrb r2, [r3, #0] - 8004296: 4b14 ldr r3, [pc, #80] @ (80042e8 ) - 8004298: 781b ldrb r3, [r3, #0] - 800429a: 429a cmp r2, r3 - 800429c: d116 bne.n 80042cc - //Мгновенная перезагрузка -#ifndef EDCAN_RESET_REG - if(RxFrame.ExtID.RegisterAddress == 0x26){ - 800429e: 4b0f ldr r3, [pc, #60] @ (80042dc ) - 80042a0: 885b ldrh r3, [r3, #2] - 80042a2: f3c3 030a ubfx r3, r3, #0, #11 - 80042a6: b29b uxth r3, r3 - 80042a8: 2b26 cmp r3, #38 @ 0x26 - 80042aa: d105 bne.n 80042b8 - if(RxFrame.data[0] == 0x66) NVIC_SystemReset(); - 80042ac: 4b0b ldr r3, [pc, #44] @ (80042dc ) - 80042ae: 791b ldrb r3, [r3, #4] - 80042b0: 2b66 cmp r3, #102 @ 0x66 - 80042b2: d101 bne.n 80042b8 - 80042b4: f7ff ffb0 bl 8004218 <__NVIC_SystemReset> - if(RxFrame.ExtID.RegisterAddress == EDCAN_RESET_REG){ - if(RxFrame.data[0] == 0x66) NVIC_SystemReset(); - } -#endif - //Выходим из Silent Mode сразу после получения любого пакета - if(silentmode_enable) EDCAN_EnterSilentMode(0); - 80042b8: 4b0c ldr r3, [pc, #48] @ (80042ec ) - 80042ba: 681b ldr r3, [r3, #0] - 80042bc: 2b00 cmp r3, #0 - 80042be: d002 beq.n 80042c6 - 80042c0: 2000 movs r0, #0 - 80042c2: f000 f999 bl 80045f8 - EDCAN_RxBufferAdd (&RxFrame); - 80042c6: 4805 ldr r0, [pc, #20] @ (80042dc ) - 80042c8: f000 fb04 bl 80048d4 -// EDCAN_ExchangeRxBuffer(); - } - } -} - 80042cc: bf00 nop - 80042ce: 3708 adds r7, #8 - 80042d0: 46bd mov sp, r7 - 80042d2: bd80 pop {r7, pc} - 80042d4: 200005d0 .word 0x200005d0 - 80042d8: 200005d8 .word 0x200005d8 - 80042dc: 200005f4 .word 0x200005f4 - 80042e0: 200005f8 .word 0x200005f8 - 80042e4: 200005ce .word 0x200005ce - 80042e8: 20000003 .word 0x20000003 - 80042ec: 2000060c .word 0x2000060c - -080042f0 : -#endif - -void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan_){ - 80042f0: b580 push {r7, lr} - 80042f2: b082 sub sp, #8 - 80042f4: af00 add r7, sp, #0 - 80042f6: 6078 str r0, [r7, #4] - if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ - 80042f8: 687b ldr r3, [r7, #4] - 80042fa: 681a ldr r2, [r3, #0] - 80042fc: 4b07 ldr r3, [pc, #28] @ (800431c ) - 80042fe: 681b ldr r3, [r3, #0] - 8004300: 429a cmp r2, r3 - 8004302: d107 bne.n 8004314 - lasttxexchangetime = HAL_GetTick() + 1; - 8004304: f001 fa96 bl 8005834 - 8004308: 4603 mov r3, r0 - 800430a: 3301 adds r3, #1 - 800430c: 4a04 ldr r2, [pc, #16] @ (8004320 ) - 800430e: 6013 str r3, [r2, #0] - EDCAN_ExchangeTxBuffer(); - 8004310: f000 fa88 bl 8004824 - } -} - 8004314: bf00 nop - 8004316: 3708 adds r7, #8 - 8004318: 46bd mov sp, r7 - 800431a: bd80 pop {r7, pc} - 800431c: 200002b0 .word 0x200002b0 - 8004320: 20000610 .word 0x20000610 - -08004324 : - -void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan_){ - 8004324: b580 push {r7, lr} - 8004326: b082 sub sp, #8 - 8004328: af00 add r7, sp, #0 - 800432a: 6078 str r0, [r7, #4] - if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ - 800432c: 687b ldr r3, [r7, #4] - 800432e: 681a ldr r2, [r3, #0] - 8004330: 4b07 ldr r3, [pc, #28] @ (8004350 ) - 8004332: 681b ldr r3, [r3, #0] - 8004334: 429a cmp r2, r3 - 8004336: d107 bne.n 8004348 - lasttxexchangetime = HAL_GetTick() + 1; - 8004338: f001 fa7c bl 8005834 - 800433c: 4603 mov r3, r0 - 800433e: 3301 adds r3, #1 - 8004340: 4a04 ldr r2, [pc, #16] @ (8004354 ) - 8004342: 6013 str r3, [r2, #0] - EDCAN_ExchangeTxBuffer(); - 8004344: f000 fa6e bl 8004824 - } -} - 8004348: bf00 nop - 800434a: 3708 adds r7, #8 - 800434c: 46bd mov sp, r7 - 800434e: bd80 pop {r7, pc} - 8004350: 200002b0 .word 0x200002b0 - 8004354: 20000610 .word 0x20000610 - -08004358 : - -void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan_){ - 8004358: b580 push {r7, lr} - 800435a: b082 sub sp, #8 - 800435c: af00 add r7, sp, #0 - 800435e: 6078 str r0, [r7, #4] - if (hcan_->Instance == ED_CAN_INSTANCE.Instance){ - 8004360: 687b ldr r3, [r7, #4] - 8004362: 681a ldr r2, [r3, #0] - 8004364: 4b07 ldr r3, [pc, #28] @ (8004384 ) - 8004366: 681b ldr r3, [r3, #0] - 8004368: 429a cmp r2, r3 - 800436a: d107 bne.n 800437c - lasttxexchangetime = HAL_GetTick() + 1; - 800436c: f001 fa62 bl 8005834 - 8004370: 4603 mov r3, r0 - 8004372: 3301 adds r3, #1 - 8004374: 4a04 ldr r2, [pc, #16] @ (8004388 ) - 8004376: 6013 str r3, [r2, #0] - EDCAN_ExchangeTxBuffer(); - 8004378: f000 fa54 bl 8004824 - } -} - 800437c: bf00 nop - 800437e: 3708 adds r7, #8 - 8004380: 46bd mov sp, r7 - 8004382: bd80 pop {r7, pc} - 8004384: 200002b0 .word 0x200002b0 - 8004388: 20000610 .word 0x20000610 - -0800438c : -/** - * @brief EDCAN Initialization function - * - * @param _OwnID: EDCAN Device ID - */ -void EDCAN_Init(uint8_t _OwnID){ - 800438c: b480 push {r7} - 800438e: b083 sub sp, #12 - 8004390: af00 add r7, sp, #0 - 8004392: 4603 mov r3, r0 - 8004394: 71fb strb r3, [r7, #7] - ED_OwnID = _OwnID; - 8004396: 4a04 ldr r2, [pc, #16] @ (80043a8 ) - 8004398: 79fb ldrb r3, [r7, #7] - 800439a: 7013 strb r3, [r2, #0] -}; - 800439c: bf00 nop - 800439e: 370c adds r7, #12 - 80043a0: 46bd mov sp, r7 - 80043a2: bc80 pop {r7} - 80043a4: 4770 bx lr - 80043a6: bf00 nop - 80043a8: 200005ce .word 0x200005ce - -080043ac : -/** - * @brief CAN Reinitialization function - * - * - */ -void CAN_ReInit(){ - 80043ac: b580 push {r7, lr} - 80043ae: af00 add r7, sp, #0 - - HAL_CAN_Stop(&ED_CAN_INSTANCE); - 80043b0: 4807 ldr r0, [pc, #28] @ (80043d0 ) - 80043b2: f002 f991 bl 80066d8 -#ifdef ED_CAN1 - MX_CAN1_Init(); -#endif - -#ifdef ED_CAN2 - MX_CAN2_Init(); - 80043b6: f7fd fadf bl 8001978 -#endif - - EDCAN_FilterInit(); - 80043ba: f000 f80b bl 80043d4 - HAL_CAN_Start(&ED_CAN_INSTANCE); - 80043be: 4804 ldr r0, [pc, #16] @ (80043d0 ) - 80043c0: f002 f946 bl 8006650 -#ifdef ED_CAN1 - HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO0_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); -#endif - -#ifdef ED_CAN2 - HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO1_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); - 80043c4: 2111 movs r1, #17 - 80043c6: 4802 ldr r0, [pc, #8] @ (80043d0 ) - 80043c8: f002 fbee bl 8006ba8 -#endif - -} - 80043cc: bf00 nop - 80043ce: bd80 pop {r7, pc} - 80043d0: 200002b0 .word 0x200002b0 - -080043d4 : - * - * @param _OwnID: EDCAN Device ID - * - * @retval HAL status - */ -void EDCAN_FilterInit(){ - 80043d4: b580 push {r7, lr} - 80043d6: b08a sub sp, #40 @ 0x28 - 80043d8: af00 add r7, sp, #0 - CAN_FilterTypeDef sFilterConfig; - - //Filter for Own ID - - sFilterConfig.FilterBank = 0; - 80043da: 2300 movs r3, #0 - 80043dc: 617b str r3, [r7, #20] - sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; - 80043de: 2300 movs r3, #0 - 80043e0: 61bb str r3, [r7, #24] - sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; - 80043e2: 2301 movs r3, #1 - 80043e4: 61fb str r3, [r7, #28] - sFilterConfig.FilterIdHigh = 0x0000; - 80043e6: 2300 movs r3, #0 - 80043e8: 603b str r3, [r7, #0] - sFilterConfig.FilterIdLow = (uint16_t)(ED_OwnID<<3)|0b100; - 80043ea: 4b33 ldr r3, [pc, #204] @ (80044b8 ) - 80043ec: 781b ldrb r3, [r3, #0] - 80043ee: 00db lsls r3, r3, #3 - 80043f0: b29b uxth r3, r3 - 80043f2: f043 0304 orr.w r3, r3, #4 - 80043f6: b29b uxth r3, r3 - 80043f8: 607b str r3, [r7, #4] - sFilterConfig.FilterMaskIdHigh = 0x0000; - 80043fa: 2300 movs r3, #0 - 80043fc: 60bb str r3, [r7, #8] - sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; - 80043fe: f240 73fc movw r3, #2044 @ 0x7fc - 8004402: 60fb str r3, [r7, #12] - sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; - 8004404: 2300 movs r3, #0 - 8004406: 613b str r3, [r7, #16] - sFilterConfig.FilterActivation = ENABLE; - 8004408: 2301 movs r3, #1 - 800440a: 623b str r3, [r7, #32] - -#ifdef ED_CAN2 - sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; - 800440c: 2301 movs r3, #1 - 800440e: 613b str r3, [r7, #16] - sFilterConfig.SlaveStartFilterBank = 14; - 8004410: 230e movs r3, #14 - 8004412: 627b str r3, [r7, #36] @ 0x24 - sFilterConfig.FilterBank = 14; - 8004414: 230e movs r3, #14 - 8004416: 617b str r3, [r7, #20] -#endif - - if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK){ - 8004418: 463b mov r3, r7 - 800441a: 4619 mov r1, r3 - 800441c: 4827 ldr r0, [pc, #156] @ (80044bc ) - 800441e: f002 f837 bl 8006490 - 8004422: 4603 mov r3, r0 - 8004424: 2b00 cmp r3, #0 - 8004426: d001 beq.n 800442c - Error_Handler(); - 8004428: f000 fdda bl 8004fe0 - } - - // Filter for broadcast ID - - sFilterConfig.FilterBank = 1; - 800442c: 2301 movs r3, #1 - 800442e: 617b str r3, [r7, #20] - sFilterConfig.FilterIdHigh = 0x0000; - 8004430: 2300 movs r3, #0 - 8004432: 603b str r3, [r7, #0] - sFilterConfig.FilterIdLow = (uint16_t)(0xFF<<3)|0b100; - 8004434: f240 73fc movw r3, #2044 @ 0x7fc - 8004438: 607b str r3, [r7, #4] - sFilterConfig.FilterMaskIdHigh = 0x0000; - 800443a: 2300 movs r3, #0 - 800443c: 60bb str r3, [r7, #8] - sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; - 800443e: f240 73fc movw r3, #2044 @ 0x7fc - 8004442: 60fb str r3, [r7, #12] - -#ifdef ED_CAN2 - sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; - 8004444: 2301 movs r3, #1 - 8004446: 613b str r3, [r7, #16] - sFilterConfig.SlaveStartFilterBank = 14; - 8004448: 230e movs r3, #14 - 800444a: 627b str r3, [r7, #36] @ 0x24 - sFilterConfig.FilterBank = 15; - 800444c: 230f movs r3, #15 - 800444e: 617b str r3, [r7, #20] -#endif - - if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) - 8004450: 463b mov r3, r7 - 8004452: 4619 mov r1, r3 - 8004454: 4819 ldr r0, [pc, #100] @ (80044bc ) - 8004456: f002 f81b bl 8006490 - 800445a: 4603 mov r3, r0 - 800445c: 2b00 cmp r3, #0 - 800445e: d001 beq.n 8004464 - { - Error_Handler(); - 8004460: f000 fdbe bl 8004fe0 - } - - // Filter for second ID - if(ED_SecondID != 0xFF){ - 8004464: 4b16 ldr r3, [pc, #88] @ (80044c0 ) - 8004466: 781b ldrb r3, [r3, #0] - 8004468: 2bff cmp r3, #255 @ 0xff - 800446a: d020 beq.n 80044ae - - sFilterConfig.FilterBank = 2; - 800446c: 2302 movs r3, #2 - 800446e: 617b str r3, [r7, #20] - sFilterConfig.FilterIdHigh = 0x0000; - 8004470: 2300 movs r3, #0 - 8004472: 603b str r3, [r7, #0] - sFilterConfig.FilterIdLow = (uint16_t)(ED_SecondID<<3)|0b100; - 8004474: 4b12 ldr r3, [pc, #72] @ (80044c0 ) - 8004476: 781b ldrb r3, [r3, #0] - 8004478: 00db lsls r3, r3, #3 - 800447a: b29b uxth r3, r3 - 800447c: f043 0304 orr.w r3, r3, #4 - 8004480: b29b uxth r3, r3 - 8004482: 607b str r3, [r7, #4] - sFilterConfig.FilterMaskIdHigh = 0x0000; - 8004484: 2300 movs r3, #0 - 8004486: 60bb str r3, [r7, #8] - sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; - 8004488: f240 73fc movw r3, #2044 @ 0x7fc - 800448c: 60fb str r3, [r7, #12] - - #ifdef ED_CAN2 - sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; - 800448e: 2301 movs r3, #1 - 8004490: 613b str r3, [r7, #16] - sFilterConfig.SlaveStartFilterBank = 14; - 8004492: 230e movs r3, #14 - 8004494: 627b str r3, [r7, #36] @ 0x24 - sFilterConfig.FilterBank = 16; - 8004496: 2310 movs r3, #16 - 8004498: 617b str r3, [r7, #20] - #endif - - if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) - 800449a: 463b mov r3, r7 - 800449c: 4619 mov r1, r3 - 800449e: 4807 ldr r0, [pc, #28] @ (80044bc ) - 80044a0: f001 fff6 bl 8006490 - 80044a4: 4603 mov r3, r0 - 80044a6: 2b00 cmp r3, #0 - 80044a8: d001 beq.n 80044ae - { - Error_Handler(); - 80044aa: f000 fd99 bl 8004fe0 - } - } - -} - 80044ae: bf00 nop - 80044b0: 3728 adds r7, #40 @ 0x28 - 80044b2: 46bd mov sp, r7 - 80044b4: bd80 pop {r7, pc} - 80044b6: bf00 nop - 80044b8: 200005ce .word 0x200005ce - 80044bc: 200002b0 .word 0x200002b0 - 80044c0: 20000003 .word 0x20000003 - -080044c4 : - * @param DestinationID: Packet Destination ID - * @param RegAddr: First register address in sequence - * @param *data: pointer to data array to be send - * @param len: length of data (1..8) - */ -void EDCAN_SendPacketRead(uint8_t DestinationID, uint16_t RegAddr, const uint8_t *data, uint8_t len){ - 80044c4: b580 push {r7, lr} - 80044c6: b08c sub sp, #48 @ 0x30 - 80044c8: af00 add r7, sp, #0 - 80044ca: 603a str r2, [r7, #0] - 80044cc: 461a mov r2, r3 - 80044ce: 4603 mov r3, r0 - 80044d0: 71fb strb r3, [r7, #7] - 80044d2: 460b mov r3, r1 - 80044d4: 80bb strh r3, [r7, #4] - 80044d6: 4613 mov r3, r2 - 80044d8: 71bb strb r3, [r7, #6] - EDCAN_TxFrame_t tx_frame; - EDCAN_frameId_t ExtID; - //CAN_TxHeaderTypeDef tx_header; - //uint32_t tx_mailbox; - - ExtID.DestinationID = DestinationID; - 80044da: 79fb ldrb r3, [r7, #7] - 80044dc: 733b strb r3, [r7, #12] - ExtID.SourceID = ED_OwnID; - 80044de: 4b15 ldr r3, [pc, #84] @ (8004534 ) - 80044e0: 781b ldrb r3, [r3, #0] - 80044e2: 737b strb r3, [r7, #13] - ExtID.RegisterAddress = RegAddr; - 80044e4: 88bb ldrh r3, [r7, #4] - 80044e6: f3c3 030a ubfx r3, r3, #0, #11 - 80044ea: b29a uxth r2, r3 - 80044ec: 89fb ldrh r3, [r7, #14] - 80044ee: f362 030a bfi r3, r2, #0, #11 - 80044f2: 81fb strh r3, [r7, #14] - ExtID.PacketType = ED_READ; - 80044f4: 7bfb ldrb r3, [r7, #15] - 80044f6: 2202 movs r2, #2 - 80044f8: f362 03c4 bfi r3, r2, #3, #2 - 80044fc: 73fb strb r3, [r7, #15] - - memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); - 80044fe: 68fb ldr r3, [r7, #12] - 8004500: 617b str r3, [r7, #20] - - tx_frame.tx_header.RTR = CAN_RTR_DATA; - 8004502: 2300 movs r3, #0 - 8004504: 61fb str r3, [r7, #28] - tx_frame.tx_header.IDE = CAN_ID_EXT; - 8004506: 2304 movs r3, #4 - 8004508: 61bb str r3, [r7, #24] - tx_frame.tx_header.DLC = len; - 800450a: 79bb ldrb r3, [r7, #6] - 800450c: 623b str r3, [r7, #32] - - memcpy(&tx_frame.data, data, len); - 800450e: 79ba ldrb r2, [r7, #6] - 8004510: f107 0310 add.w r3, r7, #16 - 8004514: 3318 adds r3, #24 - 8004516: 6839 ldr r1, [r7, #0] - 8004518: 4618 mov r0, r3 - 800451a: f006 faac bl 800aa76 - - //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); - - //Добавление пакета в буфер - EDCAN_TxBufferAdd(&tx_frame); - 800451e: f107 0310 add.w r3, r7, #16 - 8004522: 4618 mov r0, r3 - 8004524: f000 f8be bl 80046a4 - - //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) - //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера - EDCAN_ExchangeTxBuffer(); - 8004528: f000 f97c bl 8004824 - -} - 800452c: bf00 nop - 800452e: 3730 adds r7, #48 @ 0x30 - 8004530: 46bd mov sp, r7 - 8004532: bd80 pop {r7, pc} - 8004534: 200005ce .word 0x200005ce - -08004538 : -/** - * @brief EDCAN loop function - * Функция для управления буферами, должна быть в while(1) - * - */ -void EDCAN_Loop(){ - 8004538: b580 push {r7, lr} - 800453a: af00 add r7, sp, #0 - //Функция переинициализации пока что не используется -// if(can_error){ -// CAN_ReInit(); -// can_error=0; -// } - if(silentmode_enable){ - 800453c: 4b1f ldr r3, [pc, #124] @ (80045bc ) - 800453e: 681b ldr r3, [r3, #0] - 8004540: 2b00 cmp r3, #0 - 8004542: d00f beq.n 8004564 - if((HAL_GetTick() - silentmode_start_time) > silentmode_delay){ - 8004544: f001 f976 bl 8005834 - 8004548: 4602 mov r2, r0 - 800454a: 4b1d ldr r3, [pc, #116] @ (80045c0 ) - 800454c: 681b ldr r3, [r3, #0] - 800454e: 1ad2 subs r2, r2, r3 - 8004550: 4b1c ldr r3, [pc, #112] @ (80045c4 ) - 8004552: 681b ldr r3, [r3, #0] - 8004554: 429a cmp r2, r3 - 8004556: d905 bls.n 8004564 - silentmode_enable = 0; - 8004558: 4b18 ldr r3, [pc, #96] @ (80045bc ) - 800455a: 2200 movs r2, #0 - 800455c: 601a str r2, [r3, #0] - EDCAN_SetSilentMode(0); - 800455e: 2000 movs r0, #0 - 8004560: f000 f87a bl 8004658 - } - } - //every 2ms exchange buffer -// if (HAL_GetTick() > lasttxexchangetime){ - if(EDCAN_getTxBufferElementCount()>0){ - 8004564: f000 f8ec bl 8004740 - 8004568: 4603 mov r3, r0 - 800456a: 2b00 cmp r3, #0 - 800456c: d007 beq.n 800457e - lasttxexchangetime = HAL_GetTick() + 1; - 800456e: f001 f961 bl 8005834 - 8004572: 4603 mov r3, r0 - 8004574: 3301 adds r3, #1 - 8004576: 4a14 ldr r2, [pc, #80] @ (80045c8 ) - 8004578: 6013 str r3, [r2, #0] - //__disable_irq(); - EDCAN_ExchangeTxBuffer(); - 800457a: f000 f953 bl 8004824 - //__enable_irq(); - } -// } - //every 1s alive packet - if ((HAL_GetTick() - lastalivepackettime) > 1000){ - 800457e: f001 f959 bl 8005834 - 8004582: 4602 mov r2, r0 - 8004584: 4b11 ldr r3, [pc, #68] @ (80045cc ) - 8004586: 681b ldr r3, [r3, #0] - 8004588: 1ad3 subs r3, r2, r3 - 800458a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 800458e: d906 bls.n 800459e - lastalivepackettime = HAL_GetTick(); - 8004590: f001 f950 bl 8005834 - 8004594: 4603 mov r3, r0 - 8004596: 4a0d ldr r2, [pc, #52] @ (80045cc ) - 8004598: 6013 str r3, [r2, #0] - EDCAN_SendAlivePacket(); - 800459a: f000 f819 bl 80045d0 - } - //exchange buffer -// if (HAL_GetTick() > lastrxexchangetime){ - if((EDCAN_getRxBufferElementCount()>0)&&(EDCAN_getTxBufferElementCount()<(BUFFER_SIZE*3/4))){ - 800459e: f000 fa1f bl 80049e0 - 80045a2: 4603 mov r3, r0 - 80045a4: 2b00 cmp r3, #0 - 80045a6: d006 beq.n 80045b6 - 80045a8: f000 f8ca bl 8004740 - 80045ac: 4603 mov r3, r0 - 80045ae: 2bbf cmp r3, #191 @ 0xbf - 80045b0: d801 bhi.n 80045b6 -// lastrxexchangetime = HAL_GetTick() + 1; - EDCAN_ExchangeRxBuffer(); - 80045b2: f000 fa21 bl 80049f8 - } -// } -} - 80045b6: bf00 nop - 80045b8: bd80 pop {r7, pc} - 80045ba: bf00 nop - 80045bc: 2000060c .word 0x2000060c - 80045c0: 20000604 .word 0x20000604 - 80045c4: 20000608 .word 0x20000608 - 80045c8: 20000610 .word 0x20000610 - 80045cc: 20000614 .word 0x20000614 - -080045d0 : - -void EDCAN_SendAlivePacket(){ - 80045d0: b580 push {r7, lr} - 80045d2: b082 sub sp, #8 - 80045d4: af00 add r7, sp, #0 - uint8_t data[1]; - uint8_t DestinationID = 0x00; - 80045d6: 2300 movs r3, #0 - 80045d8: 71fb strb r3, [r7, #7] - data[0] = EDCAN_GetOwnRegisterValue(EDCAN_REG_SYS_STATUS); - 80045da: 2000 movs r0, #0 - 80045dc: f000 fb14 bl 8004c08 - 80045e0: 4603 mov r3, r0 - 80045e2: 713b strb r3, [r7, #4] - EDCAN_SendPacketRead(DestinationID, EDCAN_REG_SYS_STATUS, data, 1); - 80045e4: 1d3a adds r2, r7, #4 - 80045e6: 79f8 ldrb r0, [r7, #7] - 80045e8: 2301 movs r3, #1 - 80045ea: 2100 movs r1, #0 - 80045ec: f7ff ff6a bl 80044c4 -} - 80045f0: bf00 nop - 80045f2: 3708 adds r7, #8 - 80045f4: 46bd mov sp, r7 - 80045f6: bd80 pop {r7, pc} - -080045f8 : - -//функция установки таймера для входа в Silent режим -//По истечении времени time выход из режима silent -//если time = 0, выход из режима silent и сброс таймера - -void EDCAN_EnterSilentMode(uint8_t time){ - 80045f8: b580 push {r7, lr} - 80045fa: b082 sub sp, #8 - 80045fc: af00 add r7, sp, #0 - 80045fe: 4603 mov r3, r0 - 8004600: 71fb strb r3, [r7, #7] - if(time==0){ - 8004602: 79fb ldrb r3, [r7, #7] - 8004604: 2b00 cmp r3, #0 - 8004606: d10b bne.n 8004620 - EDCAN_SetSilentMode(0); - 8004608: 2000 movs r0, #0 - 800460a: f000 f825 bl 8004658 - silentmode_start_time = HAL_GetTick(); - 800460e: f001 f911 bl 8005834 - 8004612: 4603 mov r3, r0 - 8004614: 4a0d ldr r2, [pc, #52] @ (800464c ) - 8004616: 6013 str r3, [r2, #0] - silentmode_enable = 0; - 8004618: 4b0d ldr r3, [pc, #52] @ (8004650 ) - 800461a: 2200 movs r2, #0 - 800461c: 601a str r2, [r3, #0] - EDCAN_SetSilentMode(1); - silentmode_delay = ((uint32_t)time * 1000); - silentmode_start_time = HAL_GetTick(); - silentmode_enable = 1; - } -} - 800461e: e011 b.n 8004644 - EDCAN_SetSilentMode(1); - 8004620: 2001 movs r0, #1 - 8004622: f000 f819 bl 8004658 - silentmode_delay = ((uint32_t)time * 1000); - 8004626: 79fb ldrb r3, [r7, #7] - 8004628: f44f 727a mov.w r2, #1000 @ 0x3e8 - 800462c: fb02 f303 mul.w r3, r2, r3 - 8004630: 4a08 ldr r2, [pc, #32] @ (8004654 ) - 8004632: 6013 str r3, [r2, #0] - silentmode_start_time = HAL_GetTick(); - 8004634: f001 f8fe bl 8005834 - 8004638: 4603 mov r3, r0 - 800463a: 4a04 ldr r2, [pc, #16] @ (800464c ) - 800463c: 6013 str r3, [r2, #0] - silentmode_enable = 1; - 800463e: 4b04 ldr r3, [pc, #16] @ (8004650 ) - 8004640: 2201 movs r2, #1 - 8004642: 601a str r2, [r3, #0] -} - 8004644: bf00 nop - 8004646: 3708 adds r7, #8 - 8004648: 46bd mov sp, r7 - 800464a: bd80 pop {r7, pc} - 800464c: 20000604 .word 0x20000604 - 8004650: 2000060c .word 0x2000060c - 8004654: 20000608 .word 0x20000608 - -08004658 : - -//Функция входа в Silent Режим -void EDCAN_SetSilentMode(uint8_t state){ - 8004658: b580 push {r7, lr} - 800465a: b082 sub sp, #8 - 800465c: af00 add r7, sp, #0 - 800465e: 4603 mov r3, r0 - 8004660: 71fb strb r3, [r7, #7] - HAL_CAN_Stop(&ED_CAN_INSTANCE); - 8004662: 480f ldr r0, [pc, #60] @ (80046a0 ) - 8004664: f002 f838 bl 80066d8 - if(state){ - 8004668: 79fb ldrb r3, [r7, #7] - 800466a: 2b00 cmp r3, #0 - 800466c: d008 beq.n 8004680 - ED_CAN_INSTANCE.Instance->BTR |= CAN_MODE_SILENT; - 800466e: 4b0c ldr r3, [pc, #48] @ (80046a0 ) - 8004670: 681b ldr r3, [r3, #0] - 8004672: 69da ldr r2, [r3, #28] - 8004674: 4b0a ldr r3, [pc, #40] @ (80046a0 ) - 8004676: 681b ldr r3, [r3, #0] - 8004678: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 - 800467c: 61da str r2, [r3, #28] - 800467e: e007 b.n 8004690 - }else{ - ED_CAN_INSTANCE.Instance->BTR &= ~CAN_MODE_SILENT; - 8004680: 4b07 ldr r3, [pc, #28] @ (80046a0 ) - 8004682: 681b ldr r3, [r3, #0] - 8004684: 69da ldr r2, [r3, #28] - 8004686: 4b06 ldr r3, [pc, #24] @ (80046a0 ) - 8004688: 681b ldr r3, [r3, #0] - 800468a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 - 800468e: 61da str r2, [r3, #28] - } - HAL_CAN_Start(&ED_CAN_INSTANCE); - 8004690: 4803 ldr r0, [pc, #12] @ (80046a0 ) - 8004692: f001 ffdd bl 8006650 -} - 8004696: bf00 nop - 8004698: 3708 adds r7, #8 - 800469a: 46bd mov sp, r7 - 800469c: bd80 pop {r7, pc} - 800469e: bf00 nop - 80046a0: 200002b0 .word 0x200002b0 - -080046a4 : -TxCircularBuffer_t txBuffer = { .head = 0, .tail = 0, .count = 0, .busy = 0 }; -RxCircularBuffer_t rxBuffer = { .head = 0, .tail = 0, .count = 0, .busy = 0 }; - - -// Добавление элемента в буфер -void EDCAN_TxBufferAdd(EDCAN_TxFrame_t *frame) { - 80046a4: b580 push {r7, lr} - 80046a6: b082 sub sp, #8 - 80046a8: af00 add r7, sp, #0 - 80046aa: 6078 str r0, [r7, #4] - __ASM volatile ("cpsid i" : : : "memory"); - 80046ac: b672 cpsid i -} - 80046ae: bf00 nop - __disable_irq(); - - memcpy(&txBuffer.buffer[txBuffer.head], frame, sizeof(EDCAN_TxFrame_t)); - 80046b0: 4b22 ldr r3, [pc, #136] @ (800473c ) - 80046b2: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80046b6: 881b ldrh r3, [r3, #0] - 80046b8: 015b lsls r3, r3, #5 - 80046ba: 4a20 ldr r2, [pc, #128] @ (800473c ) - 80046bc: 4413 add r3, r2 - 80046be: 2220 movs r2, #32 - 80046c0: 6879 ldr r1, [r7, #4] - 80046c2: 4618 mov r0, r3 - 80046c4: f006 f9d7 bl 800aa76 - txBuffer.head = (txBuffer.head + 1) % BUFFER_SIZE; - 80046c8: 4b1c ldr r3, [pc, #112] @ (800473c ) - 80046ca: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80046ce: 881b ldrh r3, [r3, #0] - 80046d0: 3301 adds r3, #1 - 80046d2: 425a negs r2, r3 - 80046d4: b2db uxtb r3, r3 - 80046d6: b2d2 uxtb r2, r2 - 80046d8: bf58 it pl - 80046da: 4253 negpl r3, r2 - 80046dc: b29a uxth r2, r3 - 80046de: 4b17 ldr r3, [pc, #92] @ (800473c ) - 80046e0: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80046e4: 801a strh r2, [r3, #0] - - if (txBuffer.count == BUFFER_SIZE) { - 80046e6: 4b15 ldr r3, [pc, #84] @ (800473c ) - 80046e8: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80046ec: f9b3 3004 ldrsh.w r3, [r3, #4] - 80046f0: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 80046f4: d10f bne.n 8004716 - txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных - 80046f6: 4b11 ldr r3, [pc, #68] @ (800473c ) - 80046f8: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80046fc: 885b ldrh r3, [r3, #2] - 80046fe: 3301 adds r3, #1 - 8004700: 425a negs r2, r3 - 8004702: b2db uxtb r3, r3 - 8004704: b2d2 uxtb r2, r2 - 8004706: bf58 it pl - 8004708: 4253 negpl r3, r2 - 800470a: b29a uxth r2, r3 - 800470c: 4b0b ldr r3, [pc, #44] @ (800473c ) - 800470e: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 8004712: 805a strh r2, [r3, #2] - 8004714: e00c b.n 8004730 - } else { - txBuffer.count++; - 8004716: 4b09 ldr r3, [pc, #36] @ (800473c ) - 8004718: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800471c: f9b3 3004 ldrsh.w r3, [r3, #4] - 8004720: b29b uxth r3, r3 - 8004722: 3301 adds r3, #1 - 8004724: b29b uxth r3, r3 - 8004726: b21a sxth r2, r3 - 8004728: 4b04 ldr r3, [pc, #16] @ (800473c ) - 800472a: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800472e: 809a strh r2, [r3, #4] - __ASM volatile ("cpsie i" : : : "memory"); - 8004730: b662 cpsie i -} - 8004732: bf00 nop - } - - __enable_irq(); -} - 8004734: bf00 nop - 8004736: 3708 adds r7, #8 - 8004738: 46bd mov sp, r7 - 800473a: bd80 pop {r7, pc} - 800473c: 20000618 .word 0x20000618 - -08004740 : - -//Количество элементов в буфере -uint16_t EDCAN_getTxBufferElementCount() { - 8004740: b480 push {r7} - 8004742: af00 add r7, sp, #0 - return txBuffer.count; - 8004744: 4b04 ldr r3, [pc, #16] @ (8004758 ) - 8004746: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800474a: f9b3 3004 ldrsh.w r3, [r3, #4] - 800474e: b29b uxth r3, r3 -} - 8004750: 4618 mov r0, r3 - 8004752: 46bd mov sp, r7 - 8004754: bc80 pop {r7} - 8004756: 4770 bx lr - 8004758: 20000618 .word 0x20000618 - -0800475c : - -// функция для получения первого элемента без удаления его из буфера -bool EDCAN_TxBufferPeekFirst(EDCAN_TxFrame_t *frame) { - 800475c: b580 push {r7, lr} - 800475e: b082 sub sp, #8 - 8004760: af00 add r7, sp, #0 - 8004762: 6078 str r0, [r7, #4] - - if (txBuffer.count > 0) { - 8004764: 4b0c ldr r3, [pc, #48] @ (8004798 ) - 8004766: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800476a: f9b3 3004 ldrsh.w r3, [r3, #4] - 800476e: 2b00 cmp r3, #0 - 8004770: dd0d ble.n 800478e - memcpy(frame, &txBuffer.buffer[txBuffer.tail], sizeof(EDCAN_TxFrame_t)); - 8004772: 4b09 ldr r3, [pc, #36] @ (8004798 ) - 8004774: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 8004778: 885b ldrh r3, [r3, #2] - 800477a: 015b lsls r3, r3, #5 - 800477c: 4a06 ldr r2, [pc, #24] @ (8004798 ) - 800477e: 4413 add r3, r2 - 8004780: 2220 movs r2, #32 - 8004782: 4619 mov r1, r3 - 8004784: 6878 ldr r0, [r7, #4] - 8004786: f006 f976 bl 800aa76 - return true; - 800478a: 2301 movs r3, #1 - 800478c: e000 b.n 8004790 - } else { - // Буфер пуст, можно добавить обработку ошибки - return false; - 800478e: 2300 movs r3, #0 - } - -} - 8004790: 4618 mov r0, r3 - 8004792: 3708 adds r7, #8 - 8004794: 46bd mov sp, r7 - 8004796: bd80 pop {r7, pc} - 8004798: 20000618 .word 0x20000618 - -0800479c : - -// функция для удаления первого элемента из буфера -bool EDCAN_TxBufferRemoveFirst() { - 800479c: b480 push {r7} - 800479e: af00 add r7, sp, #0 - if (txBuffer.count > 0) { - 80047a0: 4b1f ldr r3, [pc, #124] @ (8004820 ) - 80047a2: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047a6: f9b3 3004 ldrsh.w r3, [r3, #4] - 80047aa: 2b00 cmp r3, #0 - 80047ac: dd33 ble.n 8004816 - txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; - 80047ae: 4b1c ldr r3, [pc, #112] @ (8004820 ) - 80047b0: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047b4: 885b ldrh r3, [r3, #2] - 80047b6: 3301 adds r3, #1 - 80047b8: 425a negs r2, r3 - 80047ba: b2db uxtb r3, r3 - 80047bc: b2d2 uxtb r2, r2 - 80047be: bf58 it pl - 80047c0: 4253 negpl r3, r2 - 80047c2: b29a uxth r2, r3 - 80047c4: 4b16 ldr r3, [pc, #88] @ (8004820 ) - 80047c6: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047ca: 805a strh r2, [r3, #2] - txBuffer.count--; - 80047cc: 4b14 ldr r3, [pc, #80] @ (8004820 ) - 80047ce: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047d2: f9b3 3004 ldrsh.w r3, [r3, #4] - 80047d6: b29b uxth r3, r3 - 80047d8: 3b01 subs r3, #1 - 80047da: b29b uxth r3, r3 - 80047dc: b21a sxth r2, r3 - 80047de: 4b10 ldr r3, [pc, #64] @ (8004820 ) - 80047e0: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047e4: 809a strh r2, [r3, #4] - if(txBuffer.count < 0){ - 80047e6: 4b0e ldr r3, [pc, #56] @ (8004820 ) - 80047e8: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047ec: f9b3 3004 ldrsh.w r3, [r3, #4] - 80047f0: 2b00 cmp r3, #0 - 80047f2: da0e bge.n 8004812 - //printf("hueta\n"); - txBuffer.count = 0; - 80047f4: 4b0a ldr r3, [pc, #40] @ (8004820 ) - 80047f6: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80047fa: 2200 movs r2, #0 - 80047fc: 809a strh r2, [r3, #4] - txBuffer.tail = 0; - 80047fe: 4b08 ldr r3, [pc, #32] @ (8004820 ) - 8004800: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 8004804: 2200 movs r2, #0 - 8004806: 805a strh r2, [r3, #2] - txBuffer.head = 0; - 8004808: 4b05 ldr r3, [pc, #20] @ (8004820 ) - 800480a: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800480e: 2200 movs r2, #0 - 8004810: 801a strh r2, [r3, #0] - } - return true; - 8004812: 2301 movs r3, #1 - 8004814: e000 b.n 8004818 - } else { - // Буфер пуст, можно добавить обработку ошибки - return false; - 8004816: 2300 movs r3, #0 - } -} - 8004818: 4618 mov r0, r3 - 800481a: 46bd mov sp, r7 - 800481c: bc80 pop {r7} - 800481e: 4770 bx lr - 8004820: 20000618 .word 0x20000618 - -08004824 : - -//Функция для передачи данных из буфера в mailbox CAN шины -void EDCAN_ExchangeTxBuffer(){ - 8004824: b580 push {r7, lr} - 8004826: b08a sub sp, #40 @ 0x28 - 8004828: af00 add r7, sp, #0 - EDCAN_TxFrame_t TxFrame; - uint32_t tx_mailbox; - HAL_StatusTypeDef CAN_result; - - //если буфер занят, то выходим нах - if (txBuffer.busy) return; - 800482a: 4b26 ldr r3, [pc, #152] @ (80048c4 ) - 800482c: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 8004830: 799b ldrb r3, [r3, #6] - 8004832: 2b00 cmp r3, #0 - 8004834: d142 bne.n 80048bc - txBuffer.busy = 1; - 8004836: 4b23 ldr r3, [pc, #140] @ (80048c4 ) - 8004838: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 800483c: 2201 movs r2, #1 - 800483e: 719a strb r2, [r3, #6] - - //Если есть свободные Mailbox - if(HAL_CAN_GetTxMailboxesFreeLevel(&ED_CAN_INSTANCE) > 0){ - 8004840: 4821 ldr r0, [pc, #132] @ (80048c8 ) - 8004842: f002 f86c bl 800691e - 8004846: 4603 mov r3, r0 - 8004848: 2b00 cmp r3, #0 - 800484a: d031 beq.n 80048b0 - - //Если есть элементы в буфере, извлечь первый элемент буфера - if(EDCAN_TxBufferPeekFirst(&TxFrame)) { - 800484c: 1d3b adds r3, r7, #4 - 800484e: 4618 mov r0, r3 - 8004850: f7ff ff84 bl 800475c - 8004854: 4603 mov r3, r0 - 8004856: 2b00 cmp r3, #0 - 8004858: d02a beq.n 80048b0 - - /* отправка сообщения */ - CAN_result = HAL_CAN_AddTxMessage(&ED_CAN_INSTANCE, &TxFrame.tx_header, TxFrame.data, &tx_mailbox); - 800485a: 4638 mov r0, r7 - 800485c: 1d3b adds r3, r7, #4 - 800485e: f103 0218 add.w r2, r3, #24 - 8004862: 1d39 adds r1, r7, #4 - 8004864: 4603 mov r3, r0 - 8004866: 4818 ldr r0, [pc, #96] @ (80048c8 ) - 8004868: f001 ff7f bl 800676a - 800486c: 4603 mov r3, r0 - 800486e: f887 3027 strb.w r3, [r7, #39] @ 0x27 - - /* если отправка удалась, выход */ - if(CAN_result == HAL_OK) { - 8004872: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 - 8004876: 2b00 cmp r3, #0 - 8004878: d102 bne.n 8004880 - //Удаление элемента буфера в случае успешной передачи - EDCAN_TxBufferRemoveFirst(); - 800487a: f7ff ff8f bl 800479c - 800487e: e017 b.n 80048b0 - //printf("tx ok\n"); - - }else if(CAN_result == HAL_ERROR) { - 8004880: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 - 8004884: 2b01 cmp r3, #1 - 8004886: d113 bne.n 80048b0 - /* если ошибка, обработка ошибки */ - - if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_NOT_INITIALIZED) { - 8004888: 4b0f ldr r3, [pc, #60] @ (80048c8 ) - 800488a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800488c: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8004890: 2b00 cmp r3, #0 - 8004892: d004 beq.n 800489e - CAN_ReInit(); //CAN не инициализирован, переинициализация - 8004894: f7ff fd8a bl 80043ac - printf("CAN Reinit\n"); - 8004898: 480c ldr r0, [pc, #48] @ (80048cc ) - 800489a: f005 fbd7 bl 800a04c - } - //if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_PARAM) printf("tx full\n"); - printf("CAN.ErrorCode = %d\n",(int)ED_CAN_INSTANCE.ErrorCode); - 800489e: 4b0a ldr r3, [pc, #40] @ (80048c8 ) - 80048a0: 6a5b ldr r3, [r3, #36] @ 0x24 - 80048a2: 4619 mov r1, r3 - 80048a4: 480a ldr r0, [pc, #40] @ (80048d0 ) - 80048a6: f005 fb69 bl 8009f7c - ED_CAN_INSTANCE.ErrorCode = 0; //Clear errors - 80048aa: 4b07 ldr r3, [pc, #28] @ (80048c8 ) - 80048ac: 2200 movs r2, #0 - 80048ae: 625a str r2, [r3, #36] @ 0x24 - } - } - - } - - txBuffer.busy = 0; - 80048b0: 4b04 ldr r3, [pc, #16] @ (80048c4 ) - 80048b2: f503 5300 add.w r3, r3, #8192 @ 0x2000 - 80048b6: 2200 movs r2, #0 - 80048b8: 719a strb r2, [r3, #6] - 80048ba: e000 b.n 80048be - if (txBuffer.busy) return; - 80048bc: bf00 nop -} - 80048be: 3728 adds r7, #40 @ 0x28 - 80048c0: 46bd mov sp, r7 - 80048c2: bd80 pop {r7, pc} - 80048c4: 20000618 .word 0x20000618 - 80048c8: 200002b0 .word 0x200002b0 - 80048cc: 0800df48 .word 0x0800df48 - 80048d0: 0800df54 .word 0x0800df54 - -080048d4 : -// return false; -// } -//} - -// Функции работы с Rx буфером -void EDCAN_RxBufferAdd(EDCAN_RxFrame_t *frame) { - 80048d4: b580 push {r7, lr} - 80048d6: b082 sub sp, #8 - 80048d8: af00 add r7, sp, #0 - 80048da: 6078 str r0, [r7, #4] - // Исполнение из прерывания - - memcpy(&rxBuffer.buffer[rxBuffer.head], frame, sizeof(EDCAN_RxFrame_t)); - 80048dc: 4b1f ldr r3, [pc, #124] @ (800495c ) - 80048de: f8b3 3d00 ldrh.w r3, [r3, #3328] @ 0xd00 - 80048e2: 461a mov r2, r3 - 80048e4: 4613 mov r3, r2 - 80048e6: 005b lsls r3, r3, #1 - 80048e8: 4413 add r3, r2 - 80048ea: 009b lsls r3, r3, #2 - 80048ec: 4413 add r3, r2 - 80048ee: 4a1b ldr r2, [pc, #108] @ (800495c ) - 80048f0: 4413 add r3, r2 - 80048f2: 220d movs r2, #13 - 80048f4: 6879 ldr r1, [r7, #4] - 80048f6: 4618 mov r0, r3 - 80048f8: f006 f8bd bl 800aa76 - rxBuffer.head = (rxBuffer.head + 1) % BUFFER_SIZE; - 80048fc: 4b17 ldr r3, [pc, #92] @ (800495c ) - 80048fe: f8b3 3d00 ldrh.w r3, [r3, #3328] @ 0xd00 - 8004902: 3301 adds r3, #1 - 8004904: 425a negs r2, r3 - 8004906: b2db uxtb r3, r3 - 8004908: b2d2 uxtb r2, r2 - 800490a: bf58 it pl - 800490c: 4253 negpl r3, r2 - 800490e: b29a uxth r2, r3 - 8004910: 4b12 ldr r3, [pc, #72] @ (800495c ) - 8004912: f8a3 2d00 strh.w r2, [r3, #3328] @ 0xd00 - - if (rxBuffer.count == BUFFER_SIZE) { - 8004916: 4b11 ldr r3, [pc, #68] @ (800495c ) - 8004918: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 - 800491c: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 8004920: d10d bne.n 800493e - rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных - 8004922: 4b0e ldr r3, [pc, #56] @ (800495c ) - 8004924: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 - 8004928: 3301 adds r3, #1 - 800492a: 425a negs r2, r3 - 800492c: b2db uxtb r3, r3 - 800492e: b2d2 uxtb r2, r2 - 8004930: bf58 it pl - 8004932: 4253 negpl r3, r2 - 8004934: b29a uxth r2, r3 - 8004936: 4b09 ldr r3, [pc, #36] @ (800495c ) - 8004938: f8a3 2d02 strh.w r2, [r3, #3330] @ 0xd02 - } else { - rxBuffer.count++; - } - -} - 800493c: e009 b.n 8004952 - rxBuffer.count++; - 800493e: 4b07 ldr r3, [pc, #28] @ (800495c ) - 8004940: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 - 8004944: b29b uxth r3, r3 - 8004946: 3301 adds r3, #1 - 8004948: b29b uxth r3, r3 - 800494a: b21a sxth r2, r3 - 800494c: 4b03 ldr r3, [pc, #12] @ (800495c ) - 800494e: f8a3 2d04 strh.w r2, [r3, #3332] @ 0xd04 -} - 8004952: bf00 nop - 8004954: 3708 adds r7, #8 - 8004956: 46bd mov sp, r7 - 8004958: bd80 pop {r7, pc} - 800495a: bf00 nop - 800495c: 20002620 .word 0x20002620 - -08004960 : - -//Извлечь и удалить первый элемент буфера -bool EDCAN_RxBufferGet(EDCAN_RxFrame_t *frame) { - 8004960: b580 push {r7, lr} - 8004962: b082 sub sp, #8 - 8004964: af00 add r7, sp, #0 - 8004966: 6078 str r0, [r7, #4] - __ASM volatile ("cpsid i" : : : "memory"); - 8004968: b672 cpsid i -} - 800496a: bf00 nop - //LOCKED function - __disable_irq(); - if (rxBuffer.count > 0) { - 800496c: 4b1b ldr r3, [pc, #108] @ (80049dc ) - 800496e: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 - 8004972: 2b00 cmp r3, #0 - 8004974: dd2a ble.n 80049cc - memcpy(frame, &rxBuffer.buffer[rxBuffer.tail], sizeof(EDCAN_RxFrame_t)); - 8004976: 4b19 ldr r3, [pc, #100] @ (80049dc ) - 8004978: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 - 800497c: 461a mov r2, r3 - 800497e: 4613 mov r3, r2 - 8004980: 005b lsls r3, r3, #1 - 8004982: 4413 add r3, r2 - 8004984: 009b lsls r3, r3, #2 - 8004986: 4413 add r3, r2 - 8004988: 4a14 ldr r2, [pc, #80] @ (80049dc ) - 800498a: 4413 add r3, r2 - 800498c: 220d movs r2, #13 - 800498e: 4619 mov r1, r3 - 8004990: 6878 ldr r0, [r7, #4] - 8004992: f006 f870 bl 800aa76 - rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; - 8004996: 4b11 ldr r3, [pc, #68] @ (80049dc ) - 8004998: f8b3 3d02 ldrh.w r3, [r3, #3330] @ 0xd02 - 800499c: 3301 adds r3, #1 - 800499e: 425a negs r2, r3 - 80049a0: b2db uxtb r3, r3 - 80049a2: b2d2 uxtb r2, r2 - 80049a4: bf58 it pl - 80049a6: 4253 negpl r3, r2 - 80049a8: b29a uxth r2, r3 - 80049aa: 4b0c ldr r3, [pc, #48] @ (80049dc ) - 80049ac: f8a3 2d02 strh.w r2, [r3, #3330] @ 0xd02 - rxBuffer.count--; - 80049b0: 4b0a ldr r3, [pc, #40] @ (80049dc ) - 80049b2: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 - 80049b6: b29b uxth r3, r3 - 80049b8: 3b01 subs r3, #1 - 80049ba: b29b uxth r3, r3 - 80049bc: b21a sxth r2, r3 - 80049be: 4b07 ldr r3, [pc, #28] @ (80049dc ) - 80049c0: f8a3 2d04 strh.w r2, [r3, #3332] @ 0xd04 - __ASM volatile ("cpsie i" : : : "memory"); - 80049c4: b662 cpsie i -} - 80049c6: bf00 nop - __enable_irq(); - return true; - 80049c8: 2301 movs r3, #1 - 80049ca: e002 b.n 80049d2 - __ASM volatile ("cpsie i" : : : "memory"); - 80049cc: b662 cpsie i -} - 80049ce: bf00 nop - } else { - // Буфер пуст, можно добавить обработку ошибки - __enable_irq(); - return false; - 80049d0: 2300 movs r3, #0 - } - -} - 80049d2: 4618 mov r0, r3 - 80049d4: 3708 adds r7, #8 - 80049d6: 46bd mov sp, r7 - 80049d8: bd80 pop {r7, pc} - 80049da: bf00 nop - 80049dc: 20002620 .word 0x20002620 - -080049e0 : - -//Количество элементов в буфере -uint16_t EDCAN_getRxBufferElementCount() { - 80049e0: b480 push {r7} - 80049e2: af00 add r7, sp, #0 - return rxBuffer.count; - 80049e4: 4b03 ldr r3, [pc, #12] @ (80049f4 ) - 80049e6: f9b3 3d04 ldrsh.w r3, [r3, #3332] @ 0xd04 - 80049ea: b29b uxth r3, r3 -} - 80049ec: 4618 mov r0, r3 - 80049ee: 46bd mov sp, r7 - 80049f0: bc80 pop {r7} - 80049f2: 4770 bx lr - 80049f4: 20002620 .word 0x20002620 - -080049f8 : - -//Функция для обработки входящих пакетов из буфера -void EDCAN_ExchangeRxBuffer(){ - 80049f8: b590 push {r4, r7, lr} - 80049fa: b087 sub sp, #28 - 80049fc: af02 add r7, sp, #8 - EDCAN_RxFrame_t Rxframe; - - if (EDCAN_RxBufferGet(&Rxframe)){ - 80049fe: 463b mov r3, r7 - 8004a00: 4618 mov r0, r3 - 8004a02: f7ff ffad bl 8004960 - 8004a06: 4603 mov r3, r0 - 8004a08: 2b00 cmp r3, #0 - 8004a0a: d039 beq.n 8004a80 - - if(Rxframe.ExtID.PacketType == ED_WRITE){ - 8004a0c: 78fb ldrb r3, [r7, #3] - 8004a0e: f003 0318 and.w r3, r3, #24 - 8004a12: b2db uxtb r3, r3 - 8004a14: 2b00 cmp r3, #0 - 8004a16: d10e bne.n 8004a36 - EDCAN_WriteHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); - 8004a18: 7878 ldrb r0, [r7, #1] - 8004a1a: 7839 ldrb r1, [r7, #0] - 8004a1c: 887b ldrh r3, [r7, #2] - 8004a1e: f3c3 030a ubfx r3, r3, #0, #11 - 8004a22: b29b uxth r3, r3 - 8004a24: 461c mov r4, r3 - 8004a26: 7b3b ldrb r3, [r7, #12] - 8004a28: 463a mov r2, r7 - 8004a2a: 3204 adds r2, #4 - 8004a2c: 9300 str r3, [sp, #0] - 8004a2e: 4613 mov r3, r2 - 8004a30: 4622 mov r2, r4 - 8004a32: f000 f829 bl 8004a88 - } - - if(Rxframe.ExtID.PacketType == ED_READREQ){ - 8004a36: 78fb ldrb r3, [r7, #3] - 8004a38: f003 0318 and.w r3, r3, #24 - 8004a3c: b2db uxtb r3, r3 - 8004a3e: 2b08 cmp r3, #8 - 8004a40: d109 bne.n 8004a56 - EDCAN_ReadRequestHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data[0]); - 8004a42: 7878 ldrb r0, [r7, #1] - 8004a44: 7839 ldrb r1, [r7, #0] - 8004a46: 887b ldrh r3, [r7, #2] - 8004a48: f3c3 030a ubfx r3, r3, #0, #11 - 8004a4c: b29b uxth r3, r3 - 8004a4e: 461a mov r2, r3 - 8004a50: 793b ldrb r3, [r7, #4] - 8004a52: f000 f8f0 bl 8004c36 - } - - if(Rxframe.ExtID.PacketType == ED_READ){ - 8004a56: 78fb ldrb r3, [r7, #3] - 8004a58: f003 0318 and.w r3, r3, #24 - 8004a5c: b2db uxtb r3, r3 - 8004a5e: 2b10 cmp r3, #16 - 8004a60: d10e bne.n 8004a80 - EDCAN_ReadHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); - 8004a62: 7878 ldrb r0, [r7, #1] - 8004a64: 7839 ldrb r1, [r7, #0] - 8004a66: 887b ldrh r3, [r7, #2] - 8004a68: f3c3 030a ubfx r3, r3, #0, #11 - 8004a6c: b29b uxth r3, r3 - 8004a6e: 461c mov r4, r3 - 8004a70: 7b3b ldrb r3, [r7, #12] - 8004a72: 463a mov r2, r7 - 8004a74: 3204 adds r2, #4 - 8004a76: 9300 str r3, [sp, #0] - 8004a78: 4613 mov r3, r2 - 8004a7a: 4622 mov r2, r4 - 8004a7c: f7fe fcfc bl 8003478 - } - } - -} - 8004a80: bf00 nop - 8004a82: 3714 adds r7, #20 - 8004a84: 46bd mov sp, r7 - 8004a86: bd90 pop {r4, r7, pc} - -08004a88 : - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_WriteHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ - 8004a88: b580 push {r7, lr} - 8004a8a: b084 sub sp, #16 - 8004a8c: af00 add r7, sp, #0 - 8004a8e: 603b str r3, [r7, #0] - 8004a90: 4603 mov r3, r0 - 8004a92: 71fb strb r3, [r7, #7] - 8004a94: 460b mov r3, r1 - 8004a96: 71bb strb r3, [r7, #6] - 8004a98: 4613 mov r3, r2 - 8004a9a: 80bb strh r3, [r7, #4] -// printf("Destination ID = %d\n", DestinationID); -// printf("Address = %d\n", Addr); -// printf("Len = %d\n", len); -// printf("\n"); - - for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler - 8004a9c: 2300 movs r3, #0 - 8004a9e: 81fb strh r3, [r7, #14] - 8004aa0: e01e b.n 8004ae0 - -// printf ("register[%d] = %d\n", Addr+AddrOffset, data[AddrOffset]); - if((Addr+AddrOffset)>=256){ - 8004aa2: 88ba ldrh r2, [r7, #4] - 8004aa4: 89fb ldrh r3, [r7, #14] - 8004aa6: 4413 add r3, r2 - 8004aa8: 2bff cmp r3, #255 @ 0xff - 8004aaa: dd0b ble.n 8004ac4 - EDCAN_WriteUserRegister(Addr+AddrOffset, data[AddrOffset]); - 8004aac: 88ba ldrh r2, [r7, #4] - 8004aae: 89fb ldrh r3, [r7, #14] - 8004ab0: 4413 add r3, r2 - 8004ab2: b298 uxth r0, r3 - 8004ab4: 89fb ldrh r3, [r7, #14] - 8004ab6: 683a ldr r2, [r7, #0] - 8004ab8: 4413 add r3, r2 - 8004aba: 781b ldrb r3, [r3, #0] - 8004abc: 4619 mov r1, r3 - 8004abe: f7fe fcf7 bl 80034b0 - 8004ac2: e00a b.n 8004ada - }else{ - EDCAN_WriteSystemRegister(Addr+AddrOffset, data[AddrOffset]); - 8004ac4: 88ba ldrh r2, [r7, #4] - 8004ac6: 89fb ldrh r3, [r7, #14] - 8004ac8: 4413 add r3, r2 - 8004aca: b298 uxth r0, r3 - 8004acc: 89fb ldrh r3, [r7, #14] - 8004ace: 683a ldr r2, [r7, #0] - 8004ad0: 4413 add r3, r2 - 8004ad2: 781b ldrb r3, [r3, #0] - 8004ad4: 4619 mov r1, r3 - 8004ad6: f000 f80d bl 8004af4 - for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler - 8004ada: 89fb ldrh r3, [r7, #14] - 8004adc: 3301 adds r3, #1 - 8004ade: 81fb strh r3, [r7, #14] - 8004ae0: 7e3b ldrb r3, [r7, #24] - 8004ae2: b29b uxth r3, r3 - 8004ae4: 89fa ldrh r2, [r7, #14] - 8004ae6: 429a cmp r2, r3 - 8004ae8: d3db bcc.n 8004aa2 - } - } -} - 8004aea: bf00 nop - 8004aec: bf00 nop - 8004aee: 3710 adds r7, #16 - 8004af0: 46bd mov sp, r7 - 8004af2: bd80 pop {r7, pc} - -08004af4 : - -void EDCAN_WriteSystemRegister(uint16_t addr, uint8_t value){ - 8004af4: b580 push {r7, lr} - 8004af6: b082 sub sp, #8 - 8004af8: af00 add r7, sp, #0 - 8004afa: 4603 mov r3, r0 - 8004afc: 460a mov r2, r1 - 8004afe: 80fb strh r3, [r7, #6] - 8004b00: 4613 mov r3, r2 - 8004b02: 717b strb r3, [r7, #5] - switch(addr){ - 8004b04: 88fb ldrh r3, [r7, #6] - 8004b06: 2b00 cmp r3, #0 - 8004b08: d002 beq.n 8004b10 - 8004b0a: 2b20 cmp r3, #32 - 8004b0c: d00b beq.n 8004b26 -// break; - //default: -// printf ("Unknown register\n"); - } - -} - 8004b0e: e010 b.n 8004b32 - if(value == 0x10){ - 8004b10: 797b ldrb r3, [r7, #5] - 8004b12: 2b10 cmp r3, #16 - 8004b14: d10c bne.n 8004b30 - if(ED_status==0)ED_status = 0x10; - 8004b16: 4b09 ldr r3, [pc, #36] @ (8004b3c ) - 8004b18: 781b ldrb r3, [r3, #0] - 8004b1a: 2b00 cmp r3, #0 - 8004b1c: d108 bne.n 8004b30 - 8004b1e: 4b07 ldr r3, [pc, #28] @ (8004b3c ) - 8004b20: 2210 movs r2, #16 - 8004b22: 701a strb r2, [r3, #0] - break; - 8004b24: e004 b.n 8004b30 - EDCAN_EnterSilentMode(value); - 8004b26: 797b ldrb r3, [r7, #5] - 8004b28: 4618 mov r0, r3 - 8004b2a: f7ff fd65 bl 80045f8 - break; - 8004b2e: e000 b.n 8004b32 - break; - 8004b30: bf00 nop -} - 8004b32: bf00 nop - 8004b34: 3708 adds r7, #8 - 8004b36: 46bd mov sp, r7 - 8004b38: bd80 pop {r7, pc} - 8004b3a: bf00 nop - 8004b3c: 20003328 .word 0x20003328 - -08004b40 : - * @brief Handler to get System register values (0..255) - * - * @param addr: register address - * @retval register value (uint8_t) - */ -uint8_t EDCAN_GetSystemRegisterValue(uint16_t addr){ - 8004b40: b580 push {r7, lr} - 8004b42: b082 sub sp, #8 - 8004b44: af00 add r7, sp, #0 - 8004b46: 4603 mov r3, r0 - 8004b48: 80fb strh r3, [r7, #6] - static uint32_t uptime_buffer; - switch (addr){ - 8004b4a: 88fb ldrh r3, [r7, #6] - 8004b4c: 2b17 cmp r3, #23 - 8004b4e: d852 bhi.n 8004bf6 - 8004b50: a201 add r2, pc, #4 @ (adr r2, 8004b58 ) - 8004b52: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8004b56: bf00 nop - 8004b58: 08004bb9 .word 0x08004bb9 - 8004b5c: 08004bc3 .word 0x08004bc3 - 8004b60: 08004bbf .word 0x08004bbf - 8004b64: 08004bf7 .word 0x08004bf7 - 8004b68: 08004bf7 .word 0x08004bf7 - 8004b6c: 08004bf7 .word 0x08004bf7 - 8004b70: 08004bf7 .word 0x08004bf7 - 8004b74: 08004bf7 .word 0x08004bf7 - 8004b78: 08004bf7 .word 0x08004bf7 - 8004b7c: 08004bf7 .word 0x08004bf7 - 8004b80: 08004bf7 .word 0x08004bf7 - 8004b84: 08004bf7 .word 0x08004bf7 - 8004b88: 08004bf7 .word 0x08004bf7 - 8004b8c: 08004bf7 .word 0x08004bf7 - 8004b90: 08004bf7 .word 0x08004bf7 - 8004b94: 08004bf7 .word 0x08004bf7 - 8004b98: 08004bf7 .word 0x08004bf7 - 8004b9c: 08004bf7 .word 0x08004bf7 - 8004ba0: 08004bf7 .word 0x08004bf7 - 8004ba4: 08004bf7 .word 0x08004bf7 - 8004ba8: 08004bc7 .word 0x08004bc7 - 8004bac: 08004bd9 .word 0x08004bd9 - 8004bb0: 08004be3 .word 0x08004be3 - 8004bb4: 08004bed .word 0x08004bed - - /* регистры 0..255 используются для Системных регистров*/ - - case EDCAN_REG_SYS_STATUS: - return ED_status; - 8004bb8: 4b11 ldr r3, [pc, #68] @ (8004c00 ) - 8004bba: 781b ldrb r3, [r3, #0] - 8004bbc: e01c b.n 8004bf8 - break; - case EDCAN_REG_SYS_FWVER: - return FWVER; - 8004bbe: 2301 movs r3, #1 - 8004bc0: e01a b.n 8004bf8 - break; - case EDCAN_REG_SYS_DEVICEID: - return DEVICE_ID; - 8004bc2: 2320 movs r3, #32 - 8004bc4: e018 b.n 8004bf8 - break; - - case EDCAN_REG_SYS_UPTIME0: - uptime_buffer = HAL_GetTick(); - 8004bc6: f000 fe35 bl 8005834 - 8004bca: 4603 mov r3, r0 - 8004bcc: 4a0d ldr r2, [pc, #52] @ (8004c04 ) - 8004bce: 6013 str r3, [r2, #0] - return uptime_buffer & 0xFF; - 8004bd0: 4b0c ldr r3, [pc, #48] @ (8004c04 ) - 8004bd2: 681b ldr r3, [r3, #0] - 8004bd4: b2db uxtb r3, r3 - 8004bd6: e00f b.n 8004bf8 - break; - case EDCAN_REG_SYS_UPTIME1: - return (uptime_buffer>>8) & 0xFF; - 8004bd8: 4b0a ldr r3, [pc, #40] @ (8004c04 ) - 8004bda: 681b ldr r3, [r3, #0] - 8004bdc: 0a1b lsrs r3, r3, #8 - 8004bde: b2db uxtb r3, r3 - 8004be0: e00a b.n 8004bf8 - break; - case EDCAN_REG_SYS_UPTIME2: - return (uptime_buffer>>16) & 0xFF; - 8004be2: 4b08 ldr r3, [pc, #32] @ (8004c04 ) - 8004be4: 681b ldr r3, [r3, #0] - 8004be6: 0c1b lsrs r3, r3, #16 - 8004be8: b2db uxtb r3, r3 - 8004bea: e005 b.n 8004bf8 - break; - case EDCAN_REG_SYS_UPTIME3: - return (uptime_buffer>>24) & 0xFF; - 8004bec: 4b05 ldr r3, [pc, #20] @ (8004c04 ) - 8004bee: 681b ldr r3, [r3, #0] - 8004bf0: 0e1b lsrs r3, r3, #24 - 8004bf2: b2db uxtb r3, r3 - 8004bf4: e000 b.n 8004bf8 - break; - - - default: - return 0x00; - 8004bf6: 2300 movs r3, #0 - } -} - 8004bf8: 4618 mov r0, r3 - 8004bfa: 3708 adds r7, #8 - 8004bfc: 46bd mov sp, r7 - 8004bfe: bd80 pop {r7, pc} - 8004c00: 20003328 .word 0x20003328 - 8004c04: 2000332c .word 0x2000332c - -08004c08 : - * @brief Handler to get own register values - * - * @param addr: register address - * @retval register value (uint8_t) - */ -uint8_t EDCAN_GetOwnRegisterValue (uint16_t addr){ - 8004c08: b580 push {r7, lr} - 8004c0a: b082 sub sp, #8 - 8004c0c: af00 add r7, sp, #0 - 8004c0e: 4603 mov r3, r0 - 8004c10: 80fb strh r3, [r7, #6] - - if(addr<256){ - 8004c12: 88fb ldrh r3, [r7, #6] - 8004c14: 2bff cmp r3, #255 @ 0xff - 8004c16: d805 bhi.n 8004c24 - return EDCAN_GetSystemRegisterValue(addr); // 0..255 - 8004c18: 88fb ldrh r3, [r7, #6] - 8004c1a: 4618 mov r0, r3 - 8004c1c: f7ff ff90 bl 8004b40 - 8004c20: 4603 mov r3, r0 - 8004c22: e004 b.n 8004c2e - }else { - return EDCAN_GetUserRegisterValue(addr); // 256..2047 - 8004c24: 88fb ldrh r3, [r7, #6] - 8004c26: 4618 mov r0, r3 - 8004c28: f7fe fcf2 bl 8003610 - 8004c2c: 4603 mov r3, r0 - } -} - 8004c2e: 4618 mov r0, r3 - 8004c30: 3708 adds r7, #8 - 8004c32: 46bd mov sp, r7 - 8004c34: bd80 pop {r7, pc} - -08004c36 : - * DestinationID: Packet Destination ID - * Addr: First register address in sequence - * *data: pointer for data array - * len: length of data (1..255) - */ -void EDCAN_ReadRequestHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t len){ - 8004c36: b590 push {r4, r7, lr} - 8004c38: b087 sub sp, #28 - 8004c3a: af00 add r7, sp, #0 - 8004c3c: 4604 mov r4, r0 - 8004c3e: 4608 mov r0, r1 - 8004c40: 4611 mov r1, r2 - 8004c42: 461a mov r2, r3 - 8004c44: 4623 mov r3, r4 - 8004c46: 71fb strb r3, [r7, #7] - 8004c48: 4603 mov r3, r0 - 8004c4a: 71bb strb r3, [r7, #6] - 8004c4c: 460b mov r3, r1 - 8004c4e: 80bb strh r3, [r7, #4] - 8004c50: 4613 mov r3, r2 - 8004c52: 70fb strb r3, [r7, #3] - //Получили пакет Read (запрошенное значение регистров) - uint8_t TxData[8]; - uint16_t AddrOffset = Addr; - 8004c54: 88bb ldrh r3, [r7, #4] - 8004c56: 82fb strh r3, [r7, #22] -// printf("Destination ID = %d\n", DestinationID); -// printf("Address = %d\n", Addr); -// printf("Len = %d\n", len); -// printf("\n"); - - while (len>0){ //по очереди перебираем все полученные регистры через Handler - 8004c58: e051 b.n 8004cfe - if(len>=8){ //если количество регистров больше 8, отправляем 8 и разбиваем на несколько пакетов - 8004c5a: 78fb ldrb r3, [r7, #3] - 8004c5c: 2b07 cmp r3, #7 - 8004c5e: d926 bls.n 8004cae - for(uint8_t n = 0; n < 8; n++){ - 8004c60: 2300 movs r3, #0 - 8004c62: 757b strb r3, [r7, #21] - 8004c64: e012 b.n 8004c8c - TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); - 8004c66: 7d7b ldrb r3, [r7, #21] - 8004c68: b29a uxth r2, r3 - 8004c6a: 8afb ldrh r3, [r7, #22] - 8004c6c: 4413 add r3, r2 - 8004c6e: b29b uxth r3, r3 - 8004c70: 7d7c ldrb r4, [r7, #21] - 8004c72: 4618 mov r0, r3 - 8004c74: f7ff ffc8 bl 8004c08 - 8004c78: 4603 mov r3, r0 - 8004c7a: 461a mov r2, r3 - 8004c7c: f104 0318 add.w r3, r4, #24 - 8004c80: 443b add r3, r7 - 8004c82: f803 2c0c strb.w r2, [r3, #-12] - for(uint8_t n = 0; n < 8; n++){ - 8004c86: 7d7b ldrb r3, [r7, #21] - 8004c88: 3301 adds r3, #1 - 8004c8a: 757b strb r3, [r7, #21] - 8004c8c: 7d7b ldrb r3, [r7, #21] - 8004c8e: 2b07 cmp r3, #7 - 8004c90: d9e9 bls.n 8004c66 - //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); - } - EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, 8); /* отправляем ответный пакет со значениями собственных регистров */ - 8004c92: f107 020c add.w r2, r7, #12 - 8004c96: 8af9 ldrh r1, [r7, #22] - 8004c98: 79f8 ldrb r0, [r7, #7] - 8004c9a: 2308 movs r3, #8 - 8004c9c: f7ff fc12 bl 80044c4 - //printf ("sent%d, %d\n", AddrOffset, len); - AddrOffset +=8; - 8004ca0: 8afb ldrh r3, [r7, #22] - 8004ca2: 3308 adds r3, #8 - 8004ca4: 82fb strh r3, [r7, #22] - len -=8; - 8004ca6: 78fb ldrb r3, [r7, #3] - 8004ca8: 3b08 subs r3, #8 - 8004caa: 70fb strb r3, [r7, #3] - 8004cac: e027 b.n 8004cfe - - }else{ - for(uint8_t n = 0; n < len; n++){ - 8004cae: 2300 movs r3, #0 - 8004cb0: 753b strb r3, [r7, #20] - 8004cb2: e012 b.n 8004cda - TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); - 8004cb4: 7d3b ldrb r3, [r7, #20] - 8004cb6: b29a uxth r2, r3 - 8004cb8: 8afb ldrh r3, [r7, #22] - 8004cba: 4413 add r3, r2 - 8004cbc: b29b uxth r3, r3 - 8004cbe: 7d3c ldrb r4, [r7, #20] - 8004cc0: 4618 mov r0, r3 - 8004cc2: f7ff ffa1 bl 8004c08 - 8004cc6: 4603 mov r3, r0 - 8004cc8: 461a mov r2, r3 - 8004cca: f104 0318 add.w r3, r4, #24 - 8004cce: 443b add r3, r7 - 8004cd0: f803 2c0c strb.w r2, [r3, #-12] - for(uint8_t n = 0; n < len; n++){ - 8004cd4: 7d3b ldrb r3, [r7, #20] - 8004cd6: 3301 adds r3, #1 - 8004cd8: 753b strb r3, [r7, #20] - 8004cda: 7d3a ldrb r2, [r7, #20] - 8004cdc: 78fb ldrb r3, [r7, #3] - 8004cde: 429a cmp r2, r3 - 8004ce0: d3e8 bcc.n 8004cb4 - //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); - } - EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, len); /* отправляем ответный пакет со значениями собственных регистров */ - 8004ce2: 78fb ldrb r3, [r7, #3] - 8004ce4: f107 020c add.w r2, r7, #12 - 8004ce8: 8af9 ldrh r1, [r7, #22] - 8004cea: 79f8 ldrb r0, [r7, #7] - 8004cec: f7ff fbea bl 80044c4 - //printf ("sent%d, %d\n", AddrOffset, len); - - AddrOffset +=len; - 8004cf0: 78fb ldrb r3, [r7, #3] - 8004cf2: b29a uxth r2, r3 - 8004cf4: 8afb ldrh r3, [r7, #22] - 8004cf6: 4413 add r3, r2 - 8004cf8: 82fb strh r3, [r7, #22] - len = 0; - 8004cfa: 2300 movs r3, #0 - 8004cfc: 70fb strb r3, [r7, #3] - while (len>0){ //по очереди перебираем все полученные регистры через Handler - 8004cfe: 78fb ldrb r3, [r7, #3] - 8004d00: 2b00 cmp r3, #0 - 8004d02: d1aa bne.n 8004c5a - } - } -// printf("\n"); -} - 8004d04: bf00 nop - 8004d06: bf00 nop - 8004d08: 371c adds r7, #28 - 8004d0a: 46bd mov sp, r7 - 8004d0c: bd90 pop {r4, r7, pc} - ... - -08004d10 : -// EDCAN_printf(LOG_WARN, "LOG_WARN test\n"); -// EDCAN_printf(LOG_NOTICE, "LOG_NOTICE test\n"); -// EDCAN_printf(LOG_INFO, "LOG_INFO test\n"); -// EDCAN_printf(LOG_DEBUG, "LOG_DEBUG test\n"); - -void EDCAN_printf(EDCAN_LogLevel_t loglevel, const char *format, ...) { - 8004d10: b40e push {r1, r2, r3} - 8004d12: b580 push {r7, lr} - 8004d14: f2ad 4d14 subw sp, sp, #1044 @ 0x414 - 8004d18: af00 add r7, sp, #0 - 8004d1a: 4602 mov r2, r0 - 8004d1c: f507 6382 add.w r3, r7, #1040 @ 0x410 - 8004d20: f2a3 4309 subw r3, r3, #1033 @ 0x409 - 8004d24: 701a strb r2, [r3, #0] - char buffer[1024]; // Размер буфера можно изменить в зависимости от потребностей - va_list args; - - va_start(args, format); - 8004d26: f507 6284 add.w r2, r7, #1056 @ 0x420 - 8004d2a: f507 6382 add.w r3, r7, #1040 @ 0x410 - 8004d2e: f5a3 6381 sub.w r3, r3, #1032 @ 0x408 - 8004d32: 601a str r2, [r3, #0] - int offset = snprintf(buffer, sizeof(buffer), "%d", loglevel); // Записываем лог-уровень в начало - 8004d34: f507 6382 add.w r3, r7, #1040 @ 0x410 - 8004d38: f2a3 4309 subw r3, r3, #1033 @ 0x409 - 8004d3c: 781b ldrb r3, [r3, #0] - 8004d3e: f107 000c add.w r0, r7, #12 - 8004d42: 4a17 ldr r2, [pc, #92] @ (8004da0 ) - 8004d44: f44f 6180 mov.w r1, #1024 @ 0x400 - 8004d48: f004 ffe8 bl 8009d1c - 8004d4c: f8c7 040c str.w r0, [r7, #1036] @ 0x40c - vsnprintf(buffer + offset, sizeof(buffer) - offset, format, args); // Записываем основное сообщение с учётом смещения - 8004d50: f8d7 340c ldr.w r3, [r7, #1036] @ 0x40c - 8004d54: f107 020c add.w r2, r7, #12 - 8004d58: 18d0 adds r0, r2, r3 - 8004d5a: f8d7 340c ldr.w r3, [r7, #1036] @ 0x40c - 8004d5e: f5c3 6180 rsb r1, r3, #1024 @ 0x400 - 8004d62: f507 6382 add.w r3, r7, #1040 @ 0x410 - 8004d66: f5a3 6381 sub.w r3, r3, #1032 @ 0x408 - 8004d6a: 681b ldr r3, [r3, #0] - 8004d6c: f8d7 241c ldr.w r2, [r7, #1052] @ 0x41c - 8004d70: f005 f8f6 bl 8009f60 - va_end(args); - - EDCAN_Log(buffer, strlen(buffer)); - 8004d74: f107 030c add.w r3, r7, #12 - 8004d78: 4618 mov r0, r3 - 8004d7a: f7fb fa55 bl 8000228 - 8004d7e: 4603 mov r3, r0 - 8004d80: b29a uxth r2, r3 - 8004d82: f107 030c add.w r3, r7, #12 - 8004d86: 4611 mov r1, r2 - 8004d88: 4618 mov r0, r3 - 8004d8a: f000 f80b bl 8004da4 -} - 8004d8e: bf00 nop - 8004d90: f207 4714 addw r7, r7, #1044 @ 0x414 - 8004d94: 46bd mov sp, r7 - 8004d96: e8bd 4080 ldmia.w sp!, {r7, lr} - 8004d9a: b003 add sp, #12 - 8004d9c: 4770 bx lr - 8004d9e: bf00 nop - 8004da0: 0800df68 .word 0x0800df68 - -08004da4 : - * @param DestinationID: Packet Destination ID - * @param RegAddr: First register address in sequence - * @param *data: pointer to data array to be send - * @param len: length of data to be sent - */ -void EDCAN_Log(const char *data, uint16_t len) { - 8004da4: b580 push {r7, lr} - 8004da6: b086 sub sp, #24 - 8004da8: af00 add r7, sp, #0 - 8004daa: 6078 str r0, [r7, #4] - 8004dac: 460b mov r3, r1 - 8004dae: 807b strh r3, [r7, #2] - uint8_t DestinationID = 0x00; - 8004db0: 2300 movs r3, #0 - 8004db2: 73fb strb r3, [r7, #15] - uint16_t remainingBytes = len;//strlen(data)+1; //add zero symbol - 8004db4: 887b ldrh r3, [r7, #2] - 8004db6: 82fb strh r3, [r7, #22] - uint16_t currentRegAddr = 0x00; //LOG reg addr - 8004db8: 2300 movs r3, #0 - 8004dba: 81bb strh r3, [r7, #12] - uint8_t *currentDataPtr = data; - 8004dbc: 687b ldr r3, [r7, #4] - 8004dbe: 613b str r3, [r7, #16] - - while (remainingBytes > 0) { - 8004dc0: e014 b.n 8004dec - uint8_t packetSize = (remainingBytes > 8) ? 8 : remainingBytes; - 8004dc2: 8afb ldrh r3, [r7, #22] - 8004dc4: 2b08 cmp r3, #8 - 8004dc6: bf28 it cs - 8004dc8: 2308 movcs r3, #8 - 8004dca: b29b uxth r3, r3 - 8004dcc: 72fb strb r3, [r7, #11] - EDCAN_SendPacketLog(DestinationID, currentRegAddr, currentDataPtr, packetSize); - 8004dce: 7afb ldrb r3, [r7, #11] - 8004dd0: 89b9 ldrh r1, [r7, #12] - 8004dd2: 7bf8 ldrb r0, [r7, #15] - 8004dd4: 693a ldr r2, [r7, #16] - 8004dd6: f000 f811 bl 8004dfc - - remainingBytes -= packetSize; - 8004dda: 7afb ldrb r3, [r7, #11] - 8004ddc: b29b uxth r3, r3 - 8004dde: 8afa ldrh r2, [r7, #22] - 8004de0: 1ad3 subs r3, r2, r3 - 8004de2: 82fb strh r3, [r7, #22] - //currentRegAddr += packetSize; // Assuming the register address increments by the number of bytes sent - currentDataPtr += packetSize; - 8004de4: 7afb ldrb r3, [r7, #11] - 8004de6: 693a ldr r2, [r7, #16] - 8004de8: 4413 add r3, r2 - 8004dea: 613b str r3, [r7, #16] - while (remainingBytes > 0) { - 8004dec: 8afb ldrh r3, [r7, #22] - 8004dee: 2b00 cmp r3, #0 - 8004df0: d1e7 bne.n 8004dc2 - } -} - 8004df2: bf00 nop - 8004df4: bf00 nop - 8004df6: 3718 adds r7, #24 - 8004df8: 46bd mov sp, r7 - 8004dfa: bd80 pop {r7, pc} - -08004dfc : - * @param DestinationID: Packet Destination ID - * @param RegAddr: First register address in sequence - * @param *data: pointer to data array to be send - * @param len: length of data (1..8) - */ -void EDCAN_SendPacketLog(uint8_t DestinationID, uint16_t RegAddr, const uint8_t *data, uint8_t len){ - 8004dfc: b580 push {r7, lr} - 8004dfe: b08c sub sp, #48 @ 0x30 - 8004e00: af00 add r7, sp, #0 - 8004e02: 603a str r2, [r7, #0] - 8004e04: 461a mov r2, r3 - 8004e06: 4603 mov r3, r0 - 8004e08: 71fb strb r3, [r7, #7] - 8004e0a: 460b mov r3, r1 - 8004e0c: 80bb strh r3, [r7, #4] - 8004e0e: 4613 mov r3, r2 - 8004e10: 71bb strb r3, [r7, #6] - EDCAN_TxFrame_t tx_frame; - EDCAN_frameId_t ExtID; - //CAN_TxHeaderTypeDef tx_header; - //uint32_t tx_mailbox; - - ExtID.DestinationID = DestinationID; - 8004e12: 79fb ldrb r3, [r7, #7] - 8004e14: 733b strb r3, [r7, #12] - ExtID.SourceID = ED_OwnID; - 8004e16: 4b15 ldr r3, [pc, #84] @ (8004e6c ) - 8004e18: 781b ldrb r3, [r3, #0] - 8004e1a: 737b strb r3, [r7, #13] - ExtID.RegisterAddress = RegAddr; - 8004e1c: 88bb ldrh r3, [r7, #4] - 8004e1e: f3c3 030a ubfx r3, r3, #0, #11 - 8004e22: b29a uxth r2, r3 - 8004e24: 89fb ldrh r3, [r7, #14] - 8004e26: f362 030a bfi r3, r2, #0, #11 - 8004e2a: 81fb strh r3, [r7, #14] - ExtID.PacketType = ED_LOG; - 8004e2c: 7bfb ldrb r3, [r7, #15] - 8004e2e: f043 0318 orr.w r3, r3, #24 - 8004e32: 73fb strb r3, [r7, #15] - - memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); - 8004e34: 68fb ldr r3, [r7, #12] - 8004e36: 617b str r3, [r7, #20] - - tx_frame.tx_header.RTR = CAN_RTR_DATA; - 8004e38: 2300 movs r3, #0 - 8004e3a: 61fb str r3, [r7, #28] - tx_frame.tx_header.IDE = CAN_ID_EXT; - 8004e3c: 2304 movs r3, #4 - 8004e3e: 61bb str r3, [r7, #24] - tx_frame.tx_header.DLC = len; - 8004e40: 79bb ldrb r3, [r7, #6] - 8004e42: 623b str r3, [r7, #32] - - memcpy(&tx_frame.data, data, len); - 8004e44: 79ba ldrb r2, [r7, #6] - 8004e46: f107 0310 add.w r3, r7, #16 - 8004e4a: 3318 adds r3, #24 - 8004e4c: 6839 ldr r1, [r7, #0] - 8004e4e: 4618 mov r0, r3 - 8004e50: f005 fe11 bl 800aa76 - - //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); - - //Добавление пакета в буфер - EDCAN_TxBufferAdd(&tx_frame); - 8004e54: f107 0310 add.w r3, r7, #16 - 8004e58: 4618 mov r0, r3 - 8004e5a: f7ff fc23 bl 80046a4 - - //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) - //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера - EDCAN_ExchangeTxBuffer(); - 8004e5e: f7ff fce1 bl 8004824 - - -} - 8004e62: bf00 nop - 8004e64: 3730 adds r7, #48 @ 0x30 - 8004e66: 46bd mov sp, r7 - 8004e68: bd80 pop {r7, pc} - 8004e6a: bf00 nop - 8004e6c: 200005ce .word 0x200005ce - -08004e70
: -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - 8004e70: b580 push {r7, lr} - 8004e72: af00 add r7, sp, #0 - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - 8004e74: f000 fc86 bl 8005784 - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - 8004e78: f000 f842 bl 8004f00 - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - 8004e7c: f7fe fddc bl 8003a38 - MX_ADC1_Init(); - 8004e80: f7fc fb88 bl 8001594 - MX_CAN1_Init(); - 8004e84: f7fc fd42 bl 800190c - MX_CAN2_Init(); - 8004e88: f7fc fd76 bl 8001978 - MX_USART2_UART_Init(); - 8004e8c: f000 fbc8 bl 8005620 - MX_RTC_Init(); - 8004e90: f000 f8ac bl 8004fec - /* USER CODE BEGIN 2 */ - CAN_ReInit(); - 8004e94: f7ff fa8a bl 80043ac - Init_Peripheral(); - 8004e98: f7fc fc32 bl 8001700 - - HAL_Delay(300); - 8004e9c: f44f 7096 mov.w r0, #300 @ 0x12c - 8004ea0: f000 fcd2 bl 8005848 - GBT_Init(); - 8004ea4: f7fc fe7c bl 8001ba0 - set_Time(1721651966); - 8004ea8: 4812 ldr r0, [pc, #72] @ (8004ef4 ) - 8004eaa: f000 f8e9 bl 8005080 - printf("Startup (type \'help\' for command list)\n"); - 8004eae: 4812 ldr r0, [pc, #72] @ (8004ef8 ) - 8004eb0: f005 f8cc bl 800a04c - debug_init(); - 8004eb4: f7fd ff44 bl 8002d40 - EDCAN_Init(SW_GetAddr()); //0x20..0x23 - 8004eb8: f7fc fd02 bl 80018c0 - 8004ebc: 4603 mov r3, r0 - 8004ebe: 4618 mov r0, r3 - 8004ec0: f7ff fa64 bl 800438c - EDCAN_printf(LOG_INFO, "Startup\n"); - 8004ec4: 490d ldr r1, [pc, #52] @ (8004efc ) - 8004ec6: 2006 movs r0, #6 - 8004ec8: f7ff ff22 bl 8004d10 - //EDCAN_Init(0x20); //Адрес EDCAN - GBT_CAN_ReInit(); - 8004ecc: f7fe ffe8 bl 8003ea0 - CAN_ReInit(); - 8004ed0: f7ff fa6c bl 80043ac - - CONN_Init(); - 8004ed4: f7fd fd17 bl 8002906 - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ -// HAL_Delay(1); - EDCAN_Loop(); - 8004ed8: f7ff fb2e bl 8004538 - //can_task(); - debug_task(); - 8004edc: f7fe faae bl 800343c - CONN_CC_ReadStateFiltered(); - 8004ee0: f7fd fde4 bl 8002aac - GBT_ManageLock(); - 8004ee4: f7ff f944 bl 8004170 - CONN_Task(); - 8004ee8: f7fd fd14 bl 8002914 - GBT_ChargerTask(); - 8004eec: f7fc fe68 bl 8001bc0 - { - 8004ef0: bf00 nop - 8004ef2: e7f1 b.n 8004ed8 - 8004ef4: 669e52fe .word 0x669e52fe - 8004ef8: 0800df6c .word 0x0800df6c - 8004efc: 0800df94 .word 0x0800df94 - -08004f00 : -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - 8004f00: b580 push {r7, lr} - 8004f02: b09c sub sp, #112 @ 0x70 - 8004f04: af00 add r7, sp, #0 - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 8004f06: f107 0338 add.w r3, r7, #56 @ 0x38 - 8004f0a: 2238 movs r2, #56 @ 0x38 - 8004f0c: 2100 movs r1, #0 - 8004f0e: 4618 mov r0, r3 - 8004f10: f005 f8b6 bl 800a080 - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8004f14: f107 0324 add.w r3, r7, #36 @ 0x24 - 8004f18: 2200 movs r2, #0 - 8004f1a: 601a str r2, [r3, #0] - 8004f1c: 605a str r2, [r3, #4] - 8004f1e: 609a str r2, [r3, #8] - 8004f20: 60da str r2, [r3, #12] - 8004f22: 611a str r2, [r3, #16] - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8004f24: 1d3b adds r3, r7, #4 - 8004f26: 2220 movs r2, #32 - 8004f28: 2100 movs r1, #0 - 8004f2a: 4618 mov r0, r3 - 8004f2c: f005 f8a8 bl 800a080 - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; - 8004f30: 2305 movs r3, #5 - 8004f32: 63bb str r3, [r7, #56] @ 0x38 - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 8004f34: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8004f38: 643b str r3, [r7, #64] @ 0x40 - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; - 8004f3a: 2304 movs r3, #4 - 8004f3c: 647b str r3, [r7, #68] @ 0x44 - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - 8004f3e: 2301 movs r3, #1 - 8004f40: 64bb str r3, [r7, #72] @ 0x48 - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8004f42: 2301 movs r3, #1 - 8004f44: 64fb str r3, [r7, #76] @ 0x4c - RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; - 8004f46: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8004f4a: 63fb str r3, [r7, #60] @ 0x3c - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 8004f4c: 2302 movs r3, #2 - 8004f4e: 65bb str r3, [r7, #88] @ 0x58 - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 8004f50: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8004f54: 65fb str r3, [r7, #92] @ 0x5c - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; - 8004f56: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 - 8004f5a: 663b str r3, [r7, #96] @ 0x60 - RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; - 8004f5c: 2302 movs r3, #2 - 8004f5e: 667b str r3, [r7, #100] @ 0x64 - RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; - 8004f60: f44f 63c0 mov.w r3, #1536 @ 0x600 - 8004f64: 66bb str r3, [r7, #104] @ 0x68 - RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; - 8004f66: 2340 movs r3, #64 @ 0x40 - 8004f68: 66fb str r3, [r7, #108] @ 0x6c - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8004f6a: f107 0338 add.w r3, r7, #56 @ 0x38 - 8004f6e: 4618 mov r0, r3 - 8004f70: f002 fc4e bl 8007810 - 8004f74: 4603 mov r3, r0 - 8004f76: 2b00 cmp r3, #0 - 8004f78: d001 beq.n 8004f7e - { - Error_Handler(); - 8004f7a: f000 f831 bl 8004fe0 - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8004f7e: 230f movs r3, #15 - 8004f80: 627b str r3, [r7, #36] @ 0x24 - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 8004f82: 2302 movs r3, #2 - 8004f84: 62bb str r3, [r7, #40] @ 0x28 - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 8004f86: 2300 movs r3, #0 - 8004f88: 62fb str r3, [r7, #44] @ 0x2c - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - 8004f8a: f44f 6380 mov.w r3, #1024 @ 0x400 - 8004f8e: 633b str r3, [r7, #48] @ 0x30 - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 8004f90: 2300 movs r3, #0 - 8004f92: 637b str r3, [r7, #52] @ 0x34 - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - 8004f94: f107 0324 add.w r3, r7, #36 @ 0x24 - 8004f98: 2102 movs r1, #2 - 8004f9a: 4618 mov r0, r3 - 8004f9c: f002 ff4e bl 8007e3c - 8004fa0: 4603 mov r3, r0 - 8004fa2: 2b00 cmp r3, #0 - 8004fa4: d001 beq.n 8004faa - { - Error_Handler(); - 8004fa6: f000 f81b bl 8004fe0 - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; - 8004faa: 2303 movs r3, #3 - 8004fac: 607b str r3, [r7, #4] - PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - 8004fae: f44f 7380 mov.w r3, #256 @ 0x100 - 8004fb2: 60bb str r3, [r7, #8] - PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; - 8004fb4: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8004fb8: 60fb str r3, [r7, #12] - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8004fba: 1d3b adds r3, r7, #4 - 8004fbc: 4618 mov r0, r3 - 8004fbe: f003 f955 bl 800826c - 8004fc2: 4603 mov r3, r0 - 8004fc4: 2b00 cmp r3, #0 - 8004fc6: d001 beq.n 8004fcc - { - Error_Handler(); - 8004fc8: f000 f80a bl 8004fe0 - } - - /** Configure the Systick interrupt time - */ - __HAL_RCC_PLLI2S_ENABLE(); - 8004fcc: 4b03 ldr r3, [pc, #12] @ (8004fdc ) - 8004fce: 2201 movs r2, #1 - 8004fd0: 601a str r2, [r3, #0] -} - 8004fd2: bf00 nop - 8004fd4: 3770 adds r7, #112 @ 0x70 - 8004fd6: 46bd mov sp, r7 - 8004fd8: bd80 pop {r7, pc} - 8004fda: bf00 nop - 8004fdc: 42420070 .word 0x42420070 - -08004fe0 : -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - 8004fe0: b480 push {r7} - 8004fe2: af00 add r7, sp, #0 - __ASM volatile ("cpsid i" : : : "memory"); - 8004fe4: b672 cpsid i -} - 8004fe6: bf00 nop - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - 8004fe8: bf00 nop - 8004fea: e7fd b.n 8004fe8 - -08004fec : - -RTC_HandleTypeDef hrtc; - -/* RTC init function */ -void MX_RTC_Init(void) -{ - 8004fec: b580 push {r7, lr} - 8004fee: af00 add r7, sp, #0 - - /* USER CODE END RTC_Init 1 */ - - /** Initialize RTC Only - */ - hrtc.Instance = RTC; - 8004ff0: 4b0a ldr r3, [pc, #40] @ (800501c ) - 8004ff2: 4a0b ldr r2, [pc, #44] @ (8005020 ) - 8004ff4: 601a str r2, [r3, #0] - hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; - 8004ff6: 4b09 ldr r3, [pc, #36] @ (800501c ) - 8004ff8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 8004ffc: 605a str r2, [r3, #4] - hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; - 8004ffe: 4b07 ldr r3, [pc, #28] @ (800501c ) - 8005000: f44f 7280 mov.w r2, #256 @ 0x100 - 8005004: 609a str r2, [r3, #8] - if (HAL_RTC_Init(&hrtc) != HAL_OK) - 8005006: 4805 ldr r0, [pc, #20] @ (800501c ) - 8005008: f003 fbc4 bl 8008794 - 800500c: 4603 mov r3, r0 - 800500e: 2b00 cmp r3, #0 - 8005010: d001 beq.n 8005016 - { - Error_Handler(); - 8005012: f7ff ffe5 bl 8004fe0 - } - /* USER CODE BEGIN RTC_Init 2 */ - - /* USER CODE END RTC_Init 2 */ - -} - 8005016: bf00 nop - 8005018: bd80 pop {r7, pc} - 800501a: bf00 nop - 800501c: 20003330 .word 0x20003330 - 8005020: 40002800 .word 0x40002800 - -08005024 : - -void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) -{ - 8005024: b580 push {r7, lr} - 8005026: b084 sub sp, #16 - 8005028: af00 add r7, sp, #0 - 800502a: 6078 str r0, [r7, #4] - - if(rtcHandle->Instance==RTC) - 800502c: 687b ldr r3, [r7, #4] - 800502e: 681b ldr r3, [r3, #0] - 8005030: 4a0b ldr r2, [pc, #44] @ (8005060 ) - 8005032: 4293 cmp r3, r2 - 8005034: d110 bne.n 8005058 - { - /* USER CODE BEGIN RTC_MspInit 0 */ - - /* USER CODE END RTC_MspInit 0 */ - HAL_PWR_EnableBkUpAccess(); - 8005036: f002 fbdf bl 80077f8 - /* Enable BKP CLK enable for backup registers */ - __HAL_RCC_BKP_CLK_ENABLE(); - 800503a: 4b0a ldr r3, [pc, #40] @ (8005064 ) - 800503c: 69db ldr r3, [r3, #28] - 800503e: 4a09 ldr r2, [pc, #36] @ (8005064 ) - 8005040: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 - 8005044: 61d3 str r3, [r2, #28] - 8005046: 4b07 ldr r3, [pc, #28] @ (8005064 ) - 8005048: 69db ldr r3, [r3, #28] - 800504a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - 800504e: 60fb str r3, [r7, #12] - 8005050: 68fb ldr r3, [r7, #12] - /* RTC clock enable */ - __HAL_RCC_RTC_ENABLE(); - 8005052: 4b05 ldr r3, [pc, #20] @ (8005068 ) - 8005054: 2201 movs r2, #1 - 8005056: 601a str r2, [r3, #0] - /* USER CODE BEGIN RTC_MspInit 1 */ - - /* USER CODE END RTC_MspInit 1 */ - } -} - 8005058: bf00 nop - 800505a: 3710 adds r7, #16 - 800505c: 46bd mov sp, r7 - 800505e: bd80 pop {r7, pc} - 8005060: 40002800 .word 0x40002800 - 8005064: 40021000 .word 0x40021000 - 8005068: 4242043c .word 0x4242043c - -0800506c : -static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc); -static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc); -static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc); - - -uint32_t get_Current_Time(){ - 800506c: b580 push {r7, lr} - 800506e: af00 add r7, sp, #0 - return RTC1_ReadTimeCounter(&hrtc); - 8005070: 4802 ldr r0, [pc, #8] @ (800507c ) - 8005072: f000 f8fb bl 800526c - 8005076: 4603 mov r3, r0 -} - 8005078: 4618 mov r0, r3 - 800507a: bd80 pop {r7, pc} - 800507c: 20003330 .word 0x20003330 - -08005080 : - -void set_Time(uint32_t unix_time){ - 8005080: b580 push {r7, lr} - 8005082: b082 sub sp, #8 - 8005084: af00 add r7, sp, #0 - 8005086: 6078 str r0, [r7, #4] - RTC1_WriteTimeCounter(&hrtc, unix_time); - 8005088: 6879 ldr r1, [r7, #4] - 800508a: 4803 ldr r0, [pc, #12] @ (8005098 ) - 800508c: f000 f91e bl 80052cc -} - 8005090: bf00 nop - 8005092: 3708 adds r7, #8 - 8005094: 46bd mov sp, r7 - 8005096: bd80 pop {r7, pc} - 8005098: 20003330 .word 0x20003330 - -0800509c : - -uint8_t to_bcd(int value) { - 800509c: b480 push {r7} - 800509e: b083 sub sp, #12 - 80050a0: af00 add r7, sp, #0 - 80050a2: 6078 str r0, [r7, #4] - return ((value / 10) << 4) | (value % 10); - 80050a4: 687b ldr r3, [r7, #4] - 80050a6: 4a0e ldr r2, [pc, #56] @ (80050e0 ) - 80050a8: fb82 1203 smull r1, r2, r2, r3 - 80050ac: 1092 asrs r2, r2, #2 - 80050ae: 17db asrs r3, r3, #31 - 80050b0: 1ad3 subs r3, r2, r3 - 80050b2: 011b lsls r3, r3, #4 - 80050b4: b258 sxtb r0, r3 - 80050b6: 687a ldr r2, [r7, #4] - 80050b8: 4b09 ldr r3, [pc, #36] @ (80050e0 ) - 80050ba: fb83 1302 smull r1, r3, r3, r2 - 80050be: 1099 asrs r1, r3, #2 - 80050c0: 17d3 asrs r3, r2, #31 - 80050c2: 1ac9 subs r1, r1, r3 - 80050c4: 460b mov r3, r1 - 80050c6: 009b lsls r3, r3, #2 - 80050c8: 440b add r3, r1 - 80050ca: 005b lsls r3, r3, #1 - 80050cc: 1ad1 subs r1, r2, r3 - 80050ce: b24b sxtb r3, r1 - 80050d0: 4303 orrs r3, r0 - 80050d2: b25b sxtb r3, r3 - 80050d4: b2db uxtb r3, r3 -} - 80050d6: 4618 mov r0, r3 - 80050d8: 370c adds r7, #12 - 80050da: 46bd mov sp, r7 - 80050dc: bc80 pop {r7} - 80050de: 4770 bx lr - 80050e0: 66666667 .word 0x66666667 - -080050e4 : - -void unix_to_bcd(uint32_t unix_time, uint8_t *time) { - 80050e4: b590 push {r4, r7, lr} - 80050e6: b087 sub sp, #28 - 80050e8: af00 add r7, sp, #0 - 80050ea: 6078 str r0, [r7, #4] - 80050ec: 6039 str r1, [r7, #0] - struct tm *tm_info; - time_t raw_time = (time_t)unix_time; - 80050ee: 6879 ldr r1, [r7, #4] - 80050f0: 2000 movs r0, #0 - 80050f2: 460a mov r2, r1 - 80050f4: 4603 mov r3, r0 - 80050f6: e9c7 2302 strd r2, r3, [r7, #8] - tm_info = gmtime(&raw_time); - 80050fa: f107 0308 add.w r3, r7, #8 - 80050fe: 4618 mov r0, r3 - 8005100: f004 ffc6 bl 800a090 - 8005104: 6178 str r0, [r7, #20] - - time[0] = to_bcd(tm_info->tm_sec); - 8005106: 697b ldr r3, [r7, #20] - 8005108: 681b ldr r3, [r3, #0] - 800510a: 4618 mov r0, r3 - 800510c: f7ff ffc6 bl 800509c - 8005110: 4603 mov r3, r0 - 8005112: 461a mov r2, r3 - 8005114: 683b ldr r3, [r7, #0] - 8005116: 701a strb r2, [r3, #0] - time[1] = to_bcd(tm_info->tm_min); - 8005118: 697b ldr r3, [r7, #20] - 800511a: 685a ldr r2, [r3, #4] - 800511c: 683b ldr r3, [r7, #0] - 800511e: 1c5c adds r4, r3, #1 - 8005120: 4610 mov r0, r2 - 8005122: f7ff ffbb bl 800509c - 8005126: 4603 mov r3, r0 - 8005128: 7023 strb r3, [r4, #0] - time[2] = to_bcd(tm_info->tm_hour); - 800512a: 697b ldr r3, [r7, #20] - 800512c: 689a ldr r2, [r3, #8] - 800512e: 683b ldr r3, [r7, #0] - 8005130: 1c9c adds r4, r3, #2 - 8005132: 4610 mov r0, r2 - 8005134: f7ff ffb2 bl 800509c - 8005138: 4603 mov r3, r0 - 800513a: 7023 strb r3, [r4, #0] - time[3] = to_bcd(tm_info->tm_mday); - 800513c: 697b ldr r3, [r7, #20] - 800513e: 68da ldr r2, [r3, #12] - 8005140: 683b ldr r3, [r7, #0] - 8005142: 1cdc adds r4, r3, #3 - 8005144: 4610 mov r0, r2 - 8005146: f7ff ffa9 bl 800509c - 800514a: 4603 mov r3, r0 - 800514c: 7023 strb r3, [r4, #0] - time[4] = to_bcd(tm_info->tm_mon + 1); // tm_mon is 0-11 - 800514e: 697b ldr r3, [r7, #20] - 8005150: 691b ldr r3, [r3, #16] - 8005152: 1c5a adds r2, r3, #1 - 8005154: 683b ldr r3, [r7, #0] - 8005156: 1d1c adds r4, r3, #4 - 8005158: 4610 mov r0, r2 - 800515a: f7ff ff9f bl 800509c - 800515e: 4603 mov r3, r0 - 8005160: 7023 strb r3, [r4, #0] - time[5] = to_bcd((tm_info->tm_year + 1900) % 100); // Year in 2 digits - 8005162: 697b ldr r3, [r7, #20] - 8005164: 695b ldr r3, [r3, #20] - 8005166: f203 736c addw r3, r3, #1900 @ 0x76c - 800516a: 4a13 ldr r2, [pc, #76] @ (80051b8 ) - 800516c: fb82 1203 smull r1, r2, r2, r3 - 8005170: 1151 asrs r1, r2, #5 - 8005172: 17da asrs r2, r3, #31 - 8005174: 1a8a subs r2, r1, r2 - 8005176: 2164 movs r1, #100 @ 0x64 - 8005178: fb01 f202 mul.w r2, r1, r2 - 800517c: 1a9a subs r2, r3, r2 - 800517e: 683b ldr r3, [r7, #0] - 8005180: 1d5c adds r4, r3, #5 - 8005182: 4610 mov r0, r2 - 8005184: f7ff ff8a bl 800509c - 8005188: 4603 mov r3, r0 - 800518a: 7023 strb r3, [r4, #0] - time[6] = to_bcd((tm_info->tm_year + 1900) / 100); // Century in 2 digits - 800518c: 697b ldr r3, [r7, #20] - 800518e: 695b ldr r3, [r3, #20] - 8005190: f203 736c addw r3, r3, #1900 @ 0x76c - 8005194: 4a08 ldr r2, [pc, #32] @ (80051b8 ) - 8005196: fb82 1203 smull r1, r2, r2, r3 - 800519a: 1152 asrs r2, r2, #5 - 800519c: 17db asrs r3, r3, #31 - 800519e: 1ad2 subs r2, r2, r3 - 80051a0: 683b ldr r3, [r7, #0] - 80051a2: 1d9c adds r4, r3, #6 - 80051a4: 4610 mov r0, r2 - 80051a6: f7ff ff79 bl 800509c - 80051aa: 4603 mov r3, r0 - 80051ac: 7023 strb r3, [r4, #0] -} - 80051ae: bf00 nop - 80051b0: 371c adds r7, #28 - 80051b2: 46bd mov sp, r7 - 80051b4: bd90 pop {r4, r7, pc} - 80051b6: bf00 nop - 80051b8: 51eb851f .word 0x51eb851f - -080051bc : - -void writeTimeReg(uint8_t reg_number, uint8_t value){ - 80051bc: b580 push {r7, lr} - 80051be: b082 sub sp, #8 - 80051c0: af00 add r7, sp, #0 - 80051c2: 4603 mov r3, r0 - 80051c4: 460a mov r2, r1 - 80051c6: 71fb strb r3, [r7, #7] - 80051c8: 4613 mov r3, r2 - 80051ca: 71bb strb r3, [r7, #6] - tmp_time[reg_number] = value; - 80051cc: 79fb ldrb r3, [r7, #7] - 80051ce: 490e ldr r1, [pc, #56] @ (8005208 ) - 80051d0: 79ba ldrb r2, [r7, #6] - 80051d2: 54ca strb r2, [r1, r3] - if(reg_number == 3) set_Time((tmp_time[0])+(tmp_time[1]<<8)+(tmp_time[2]<<16)+(tmp_time[3]<<24)); - 80051d4: 79fb ldrb r3, [r7, #7] - 80051d6: 2b03 cmp r3, #3 - 80051d8: d111 bne.n 80051fe - 80051da: 4b0b ldr r3, [pc, #44] @ (8005208 ) - 80051dc: 781b ldrb r3, [r3, #0] - 80051de: 461a mov r2, r3 - 80051e0: 4b09 ldr r3, [pc, #36] @ (8005208 ) - 80051e2: 785b ldrb r3, [r3, #1] - 80051e4: 021b lsls r3, r3, #8 - 80051e6: 441a add r2, r3 - 80051e8: 4b07 ldr r3, [pc, #28] @ (8005208 ) - 80051ea: 789b ldrb r3, [r3, #2] - 80051ec: 041b lsls r3, r3, #16 - 80051ee: 441a add r2, r3 - 80051f0: 4b05 ldr r3, [pc, #20] @ (8005208 ) - 80051f2: 78db ldrb r3, [r3, #3] - 80051f4: 061b lsls r3, r3, #24 - 80051f6: 4413 add r3, r2 - 80051f8: 4618 mov r0, r3 - 80051fa: f7ff ff41 bl 8005080 -}; - 80051fe: bf00 nop - 8005200: 3708 adds r7, #8 - 8005202: 46bd mov sp, r7 - 8005204: bd80 pop {r7, pc} - 8005206: bf00 nop - 8005208: 20003344 .word 0x20003344 - -0800520c : - -uint8_t getTimeReg(uint8_t reg_number){ - 800520c: b580 push {r7, lr} - 800520e: b082 sub sp, #8 - 8005210: af00 add r7, sp, #0 - 8005212: 4603 mov r3, r0 - 8005214: 71fb strb r3, [r7, #7] - if(reg_number == 0){ - 8005216: 79fb ldrb r3, [r7, #7] - 8005218: 2b00 cmp r3, #0 - 800521a: d108 bne.n 800522e - tmp_time32 = get_Current_Time(); - 800521c: f7ff ff26 bl 800506c - 8005220: 4603 mov r3, r0 - 8005222: 4a11 ldr r2, [pc, #68] @ (8005268 ) - 8005224: 6013 str r3, [r2, #0] - return tmp_time32 & 0xFF; - 8005226: 4b10 ldr r3, [pc, #64] @ (8005268 ) - 8005228: 681b ldr r3, [r3, #0] - 800522a: b2db uxtb r3, r3 - 800522c: e018 b.n 8005260 - }else if(reg_number == 1){ - 800522e: 79fb ldrb r3, [r7, #7] - 8005230: 2b01 cmp r3, #1 - 8005232: d104 bne.n 800523e - return (tmp_time32>>8) & 0xFF; - 8005234: 4b0c ldr r3, [pc, #48] @ (8005268 ) - 8005236: 681b ldr r3, [r3, #0] - 8005238: 0a1b lsrs r3, r3, #8 - 800523a: b2db uxtb r3, r3 - 800523c: e010 b.n 8005260 - }else if(reg_number == 2){ - 800523e: 79fb ldrb r3, [r7, #7] - 8005240: 2b02 cmp r3, #2 - 8005242: d104 bne.n 800524e - return (tmp_time32>>16) & 0xFF; - 8005244: 4b08 ldr r3, [pc, #32] @ (8005268 ) - 8005246: 681b ldr r3, [r3, #0] - 8005248: 0c1b lsrs r3, r3, #16 - 800524a: b2db uxtb r3, r3 - 800524c: e008 b.n 8005260 - }else if(reg_number == 3){ - 800524e: 79fb ldrb r3, [r7, #7] - 8005250: 2b03 cmp r3, #3 - 8005252: d104 bne.n 800525e - return (tmp_time32>>24) & 0xFF; - 8005254: 4b04 ldr r3, [pc, #16] @ (8005268 ) - 8005256: 681b ldr r3, [r3, #0] - 8005258: 0e1b lsrs r3, r3, #24 - 800525a: b2db uxtb r3, r3 - 800525c: e000 b.n 8005260 - }else{ - return 0x00; - 800525e: 2300 movs r3, #0 - } -}; - 8005260: 4618 mov r0, r3 - 8005262: 3708 adds r7, #8 - 8005264: 46bd mov sp, r7 - 8005266: bd80 pop {r7, pc} - 8005268: 20003348 .word 0x20003348 - -0800526c : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Time counter - */ -static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc) -{ - 800526c: b480 push {r7} - 800526e: b087 sub sp, #28 - 8005270: af00 add r7, sp, #0 - 8005272: 6078 str r0, [r7, #4] - uint16_t high1 = 0U, high2 = 0U, low = 0U; - 8005274: 2300 movs r3, #0 - 8005276: 827b strh r3, [r7, #18] - 8005278: 2300 movs r3, #0 - 800527a: 823b strh r3, [r7, #16] - 800527c: 2300 movs r3, #0 - 800527e: 81fb strh r3, [r7, #14] - uint32_t timecounter = 0U; - 8005280: 2300 movs r3, #0 - 8005282: 617b str r3, [r7, #20] - - high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); - 8005284: 687b ldr r3, [r7, #4] - 8005286: 681b ldr r3, [r3, #0] - 8005288: 699b ldr r3, [r3, #24] - 800528a: 827b strh r3, [r7, #18] - low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); - 800528c: 687b ldr r3, [r7, #4] - 800528e: 681b ldr r3, [r3, #0] - 8005290: 69db ldr r3, [r3, #28] - 8005292: 81fb strh r3, [r7, #14] - high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); - 8005294: 687b ldr r3, [r7, #4] - 8005296: 681b ldr r3, [r3, #0] - 8005298: 699b ldr r3, [r3, #24] - 800529a: 823b strh r3, [r7, #16] - - if (high1 != high2) - 800529c: 8a7a ldrh r2, [r7, #18] - 800529e: 8a3b ldrh r3, [r7, #16] - 80052a0: 429a cmp r2, r3 - 80052a2: d008 beq.n 80052b6 - { - /* In this case the counter roll over during reading of CNTL and CNTH registers, - read again CNTL register then return the counter value */ - timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); - 80052a4: 8a3b ldrh r3, [r7, #16] - 80052a6: 041a lsls r2, r3, #16 - 80052a8: 687b ldr r3, [r7, #4] - 80052aa: 681b ldr r3, [r3, #0] - 80052ac: 69db ldr r3, [r3, #28] - 80052ae: b29b uxth r3, r3 - 80052b0: 4313 orrs r3, r2 - 80052b2: 617b str r3, [r7, #20] - 80052b4: e004 b.n 80052c0 - } - else - { - /* No counter roll over during reading of CNTL and CNTH registers, counter - value is equal to first value of CNTL and CNTH */ - timecounter = (((uint32_t) high1 << 16U) | low); - 80052b6: 8a7b ldrh r3, [r7, #18] - 80052b8: 041a lsls r2, r3, #16 - 80052ba: 89fb ldrh r3, [r7, #14] - 80052bc: 4313 orrs r3, r2 - 80052be: 617b str r3, [r7, #20] - } - - return timecounter; - 80052c0: 697b ldr r3, [r7, #20] -} - 80052c2: 4618 mov r0, r3 - 80052c4: 371c adds r7, #28 - 80052c6: 46bd mov sp, r7 - 80052c8: bc80 pop {r7} - 80052ca: 4770 bx lr - -080052cc : - * the configuration information for RTC. - * @param TimeCounter: Counter to write in RTC_CNT registers - * @retval HAL status - */ -static HAL_StatusTypeDef RTC1_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) -{ - 80052cc: b580 push {r7, lr} - 80052ce: b084 sub sp, #16 - 80052d0: af00 add r7, sp, #0 - 80052d2: 6078 str r0, [r7, #4] - 80052d4: 6039 str r1, [r7, #0] - HAL_StatusTypeDef status = HAL_OK; - 80052d6: 2300 movs r3, #0 - 80052d8: 73fb strb r3, [r7, #15] - - /* Set Initialization mode */ - if (RTC1_EnterInitMode(hrtc) != HAL_OK) - 80052da: 6878 ldr r0, [r7, #4] - 80052dc: f000 f81d bl 800531a - 80052e0: 4603 mov r3, r0 - 80052e2: 2b00 cmp r3, #0 - 80052e4: d002 beq.n 80052ec - { - status = HAL_ERROR; - 80052e6: 2301 movs r3, #1 - 80052e8: 73fb strb r3, [r7, #15] - 80052ea: e011 b.n 8005310 - } - else - { - /* Set RTC COUNTER MSB word */ - WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); - 80052ec: 687b ldr r3, [r7, #4] - 80052ee: 681b ldr r3, [r3, #0] - 80052f0: 683a ldr r2, [r7, #0] - 80052f2: 0c12 lsrs r2, r2, #16 - 80052f4: 619a str r2, [r3, #24] - /* Set RTC COUNTER LSB word */ - WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); - 80052f6: 687b ldr r3, [r7, #4] - 80052f8: 681b ldr r3, [r3, #0] - 80052fa: 683a ldr r2, [r7, #0] - 80052fc: b292 uxth r2, r2 - 80052fe: 61da str r2, [r3, #28] - - /* Wait for synchro */ - if (RTC1_ExitInitMode(hrtc) != HAL_OK) - 8005300: 6878 ldr r0, [r7, #4] - 8005302: f000 f832 bl 800536a - 8005306: 4603 mov r3, r0 - 8005308: 2b00 cmp r3, #0 - 800530a: d001 beq.n 8005310 - { - status = HAL_ERROR; - 800530c: 2301 movs r3, #1 - 800530e: 73fb strb r3, [r7, #15] - } - } - - return status; - 8005310: 7bfb ldrb r3, [r7, #15] -} - 8005312: 4618 mov r0, r3 - 8005314: 3710 adds r7, #16 - 8005316: 46bd mov sp, r7 - 8005318: bd80 pop {r7, pc} - -0800531a : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc) -{ - 800531a: b580 push {r7, lr} - 800531c: b084 sub sp, #16 - 800531e: af00 add r7, sp, #0 - 8005320: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 8005322: 2300 movs r3, #0 - 8005324: 60fb str r3, [r7, #12] - - tickstart = HAL_GetTick(); - 8005326: f000 fa85 bl 8005834 - 800532a: 60f8 str r0, [r7, #12] - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 800532c: e009 b.n 8005342 - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 800532e: f000 fa81 bl 8005834 - 8005332: 4602 mov r2, r0 - 8005334: 68fb ldr r3, [r7, #12] - 8005336: 1ad3 subs r3, r2, r3 - 8005338: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 800533c: d901 bls.n 8005342 - { - return HAL_TIMEOUT; - 800533e: 2303 movs r3, #3 - 8005340: e00f b.n 8005362 - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 8005342: 687b ldr r3, [r7, #4] - 8005344: 681b ldr r3, [r3, #0] - 8005346: 685b ldr r3, [r3, #4] - 8005348: f003 0320 and.w r3, r3, #32 - 800534c: 2b00 cmp r3, #0 - 800534e: d0ee beq.n 800532e - } - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - 8005350: 687b ldr r3, [r7, #4] - 8005352: 681b ldr r3, [r3, #0] - 8005354: 685a ldr r2, [r3, #4] - 8005356: 687b ldr r3, [r7, #4] - 8005358: 681b ldr r3, [r3, #0] - 800535a: f042 0210 orr.w r2, r2, #16 - 800535e: 605a str r2, [r3, #4] - - - return HAL_OK; - 8005360: 2300 movs r3, #0 -} - 8005362: 4618 mov r0, r3 - 8005364: 3710 adds r7, #16 - 8005366: 46bd mov sp, r7 - 8005368: bd80 pop {r7, pc} - -0800536a : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc) -{ - 800536a: b580 push {r7, lr} - 800536c: b084 sub sp, #16 - 800536e: af00 add r7, sp, #0 - 8005370: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 8005372: 2300 movs r3, #0 - 8005374: 60fb str r3, [r7, #12] - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8005376: 687b ldr r3, [r7, #4] - 8005378: 681b ldr r3, [r3, #0] - 800537a: 685a ldr r2, [r3, #4] - 800537c: 687b ldr r3, [r7, #4] - 800537e: 681b ldr r3, [r3, #0] - 8005380: f022 0210 bic.w r2, r2, #16 - 8005384: 605a str r2, [r3, #4] - - tickstart = HAL_GetTick(); - 8005386: f000 fa55 bl 8005834 - 800538a: 60f8 str r0, [r7, #12] - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 800538c: e009 b.n 80053a2 - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 800538e: f000 fa51 bl 8005834 - 8005392: 4602 mov r2, r0 - 8005394: 68fb ldr r3, [r7, #12] - 8005396: 1ad3 subs r3, r2, r3 - 8005398: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 800539c: d901 bls.n 80053a2 - { - return HAL_TIMEOUT; - 800539e: 2303 movs r3, #3 - 80053a0: e007 b.n 80053b2 - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 80053a2: 687b ldr r3, [r7, #4] - 80053a4: 681b ldr r3, [r3, #0] - 80053a6: 685b ldr r3, [r3, #4] - 80053a8: f003 0320 and.w r3, r3, #32 - 80053ac: 2b00 cmp r3, #0 - 80053ae: d0ee beq.n 800538e - } - } - - return HAL_OK; - 80053b0: 2300 movs r3, #0 -} - 80053b2: 4618 mov r0, r3 - 80053b4: 3710 adds r7, #16 - 80053b6: 46bd mov sp, r7 - 80053b8: bd80 pop {r7, pc} - ... - -080053bc : -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - 80053bc: b480 push {r7} - 80053be: b085 sub sp, #20 - 80053c0: af00 add r7, sp, #0 - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_AFIO_CLK_ENABLE(); - 80053c2: 4b15 ldr r3, [pc, #84] @ (8005418 ) - 80053c4: 699b ldr r3, [r3, #24] - 80053c6: 4a14 ldr r2, [pc, #80] @ (8005418 ) - 80053c8: f043 0301 orr.w r3, r3, #1 - 80053cc: 6193 str r3, [r2, #24] - 80053ce: 4b12 ldr r3, [pc, #72] @ (8005418 ) - 80053d0: 699b ldr r3, [r3, #24] - 80053d2: f003 0301 and.w r3, r3, #1 - 80053d6: 60bb str r3, [r7, #8] - 80053d8: 68bb ldr r3, [r7, #8] - __HAL_RCC_PWR_CLK_ENABLE(); - 80053da: 4b0f ldr r3, [pc, #60] @ (8005418 ) - 80053dc: 69db ldr r3, [r3, #28] - 80053de: 4a0e ldr r2, [pc, #56] @ (8005418 ) - 80053e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 80053e4: 61d3 str r3, [r2, #28] - 80053e6: 4b0c ldr r3, [pc, #48] @ (8005418 ) - 80053e8: 69db ldr r3, [r3, #28] - 80053ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80053ee: 607b str r3, [r7, #4] - 80053f0: 687b ldr r3, [r7, #4] - - /* System interrupt init*/ - - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled - */ - __HAL_AFIO_REMAP_SWJ_NOJTAG(); - 80053f2: 4b0a ldr r3, [pc, #40] @ (800541c ) - 80053f4: 685b ldr r3, [r3, #4] - 80053f6: 60fb str r3, [r7, #12] - 80053f8: 68fb ldr r3, [r7, #12] - 80053fa: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 - 80053fe: 60fb str r3, [r7, #12] - 8005400: 68fb ldr r3, [r7, #12] - 8005402: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 8005406: 60fb str r3, [r7, #12] - 8005408: 4a04 ldr r2, [pc, #16] @ (800541c ) - 800540a: 68fb ldr r3, [r7, #12] - 800540c: 6053 str r3, [r2, #4] - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - 800540e: bf00 nop - 8005410: 3714 adds r7, #20 - 8005412: 46bd mov sp, r7 - 8005414: bc80 pop {r7} - 8005416: 4770 bx lr - 8005418: 40021000 .word 0x40021000 - 800541c: 40010000 .word 0x40010000 - -08005420 : -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - 8005420: b480 push {r7} - 8005422: af00 add r7, sp, #0 - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - 8005424: bf00 nop - 8005426: e7fd b.n 8005424 - -08005428 : - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - 8005428: b480 push {r7} - 800542a: af00 add r7, sp, #0 - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - 800542c: bf00 nop - 800542e: e7fd b.n 800542c - -08005430 : - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - 8005430: b480 push {r7} - 8005432: af00 add r7, sp, #0 - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - 8005434: bf00 nop - 8005436: e7fd b.n 8005434 - -08005438 : - -/** - * @brief This function handles Prefetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - 8005438: b480 push {r7} - 800543a: af00 add r7, sp, #0 - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - 800543c: bf00 nop - 800543e: e7fd b.n 800543c - -08005440 : - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - 8005440: b480 push {r7} - 8005442: af00 add r7, sp, #0 - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - 8005444: bf00 nop - 8005446: e7fd b.n 8005444 - -08005448 : - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - 8005448: b480 push {r7} - 800544a: af00 add r7, sp, #0 - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - 800544c: bf00 nop - 800544e: 46bd mov sp, r7 - 8005450: bc80 pop {r7} - 8005452: 4770 bx lr - -08005454 : - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - 8005454: b480 push {r7} - 8005456: af00 add r7, sp, #0 - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - 8005458: bf00 nop - 800545a: 46bd mov sp, r7 - 800545c: bc80 pop {r7} - 800545e: 4770 bx lr - -08005460 : - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - 8005460: b480 push {r7} - 8005462: af00 add r7, sp, #0 - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - 8005464: bf00 nop - 8005466: 46bd mov sp, r7 - 8005468: bc80 pop {r7} - 800546a: 4770 bx lr - -0800546c : - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - 800546c: b580 push {r7, lr} - 800546e: af00 add r7, sp, #0 - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - 8005470: f000 f9ce bl 8005810 - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - 8005474: bf00 nop - 8005476: bd80 pop {r7, pc} - -08005478 : - -/** - * @brief This function handles CAN1 RX0 interrupt. - */ -void CAN1_RX0_IRQHandler(void) -{ - 8005478: b580 push {r7, lr} - 800547a: af00 add r7, sp, #0 - /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ - - /* USER CODE END CAN1_RX0_IRQn 0 */ - HAL_CAN_IRQHandler(&hcan1); - 800547c: 4802 ldr r0, [pc, #8] @ (8005488 ) - 800547e: f001 fbb8 bl 8006bf2 - /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ - - /* USER CODE END CAN1_RX0_IRQn 1 */ -} - 8005482: bf00 nop - 8005484: bd80 pop {r7, pc} - 8005486: bf00 nop - 8005488: 20000288 .word 0x20000288 - -0800548c : - -/** - * @brief This function handles USART2 global interrupt. - */ -void USART2_IRQHandler(void) -{ - 800548c: b580 push {r7, lr} - 800548e: af00 add r7, sp, #0 - /* USER CODE BEGIN USART2_IRQn 0 */ - - /* USER CODE END USART2_IRQn 0 */ - HAL_UART_IRQHandler(&huart2); - 8005490: 4802 ldr r0, [pc, #8] @ (800549c ) - 8005492: f003 fbc1 bl 8008c18 - /* USER CODE BEGIN USART2_IRQn 1 */ - - /* USER CODE END USART2_IRQn 1 */ -} - 8005496: bf00 nop - 8005498: bd80 pop {r7, pc} - 800549a: bf00 nop - 800549c: 20003354 .word 0x20003354 - -080054a0 : - -/** - * @brief This function handles CAN2 TX interrupt. - */ -void CAN2_TX_IRQHandler(void) -{ - 80054a0: b580 push {r7, lr} - 80054a2: af00 add r7, sp, #0 - /* USER CODE BEGIN CAN2_TX_IRQn 0 */ - - /* USER CODE END CAN2_TX_IRQn 0 */ - HAL_CAN_IRQHandler(&hcan2); - 80054a4: 4802 ldr r0, [pc, #8] @ (80054b0 ) - 80054a6: f001 fba4 bl 8006bf2 - /* USER CODE BEGIN CAN2_TX_IRQn 1 */ - - /* USER CODE END CAN2_TX_IRQn 1 */ -} - 80054aa: bf00 nop - 80054ac: bd80 pop {r7, pc} - 80054ae: bf00 nop - 80054b0: 200002b0 .word 0x200002b0 - -080054b4 : - -/** - * @brief This function handles CAN2 RX1 interrupt. - */ -void CAN2_RX1_IRQHandler(void) -{ - 80054b4: b580 push {r7, lr} - 80054b6: af00 add r7, sp, #0 - /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ - - /* USER CODE END CAN2_RX1_IRQn 0 */ - HAL_CAN_IRQHandler(&hcan2); - 80054b8: 4802 ldr r0, [pc, #8] @ (80054c4 ) - 80054ba: f001 fb9a bl 8006bf2 - /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ - - /* USER CODE END CAN2_RX1_IRQn 1 */ -} - 80054be: bf00 nop - 80054c0: bd80 pop {r7, pc} - 80054c2: bf00 nop - 80054c4: 200002b0 .word 0x200002b0 - -080054c8 <_getpid>: -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - 80054c8: b480 push {r7} - 80054ca: af00 add r7, sp, #0 - return 1; - 80054cc: 2301 movs r3, #1 -} - 80054ce: 4618 mov r0, r3 - 80054d0: 46bd mov sp, r7 - 80054d2: bc80 pop {r7} - 80054d4: 4770 bx lr - -080054d6 <_kill>: - -int _kill(int pid, int sig) -{ - 80054d6: b580 push {r7, lr} - 80054d8: b082 sub sp, #8 - 80054da: af00 add r7, sp, #0 - 80054dc: 6078 str r0, [r7, #4] - 80054de: 6039 str r1, [r7, #0] - (void)pid; - (void)sig; - errno = EINVAL; - 80054e0: f005 fa8c bl 800a9fc <__errno> - 80054e4: 4603 mov r3, r0 - 80054e6: 2216 movs r2, #22 - 80054e8: 601a str r2, [r3, #0] - return -1; - 80054ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff -} - 80054ee: 4618 mov r0, r3 - 80054f0: 3708 adds r7, #8 - 80054f2: 46bd mov sp, r7 - 80054f4: bd80 pop {r7, pc} - -080054f6 <_exit>: - -void _exit (int status) -{ - 80054f6: b580 push {r7, lr} - 80054f8: b082 sub sp, #8 - 80054fa: af00 add r7, sp, #0 - 80054fc: 6078 str r0, [r7, #4] - _kill(status, -1); - 80054fe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff - 8005502: 6878 ldr r0, [r7, #4] - 8005504: f7ff ffe7 bl 80054d6 <_kill> - while (1) {} /* Make sure we hang here */ - 8005508: bf00 nop - 800550a: e7fd b.n 8005508 <_exit+0x12> - -0800550c <_read>: -} - -__attribute__((weak)) int _read(int file, char *ptr, int len) -{ - 800550c: b580 push {r7, lr} - 800550e: b086 sub sp, #24 - 8005510: af00 add r7, sp, #0 - 8005512: 60f8 str r0, [r7, #12] - 8005514: 60b9 str r1, [r7, #8] - 8005516: 607a str r2, [r7, #4] - (void)file; - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - 8005518: 2300 movs r3, #0 - 800551a: 617b str r3, [r7, #20] - 800551c: e00a b.n 8005534 <_read+0x28> - { - *ptr++ = __io_getchar(); - 800551e: f3af 8000 nop.w - 8005522: 4601 mov r1, r0 - 8005524: 68bb ldr r3, [r7, #8] - 8005526: 1c5a adds r2, r3, #1 - 8005528: 60ba str r2, [r7, #8] - 800552a: b2ca uxtb r2, r1 - 800552c: 701a strb r2, [r3, #0] - for (DataIdx = 0; DataIdx < len; DataIdx++) - 800552e: 697b ldr r3, [r7, #20] - 8005530: 3301 adds r3, #1 - 8005532: 617b str r3, [r7, #20] - 8005534: 697a ldr r2, [r7, #20] - 8005536: 687b ldr r3, [r7, #4] - 8005538: 429a cmp r2, r3 - 800553a: dbf0 blt.n 800551e <_read+0x12> - } - - return len; - 800553c: 687b ldr r3, [r7, #4] -} - 800553e: 4618 mov r0, r3 - 8005540: 3718 adds r7, #24 - 8005542: 46bd mov sp, r7 - 8005544: bd80 pop {r7, pc} - -08005546 <_close>: - } - return len; -} - -int _close(int file) -{ - 8005546: b480 push {r7} - 8005548: b083 sub sp, #12 - 800554a: af00 add r7, sp, #0 - 800554c: 6078 str r0, [r7, #4] - (void)file; - return -1; - 800554e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff -} - 8005552: 4618 mov r0, r3 - 8005554: 370c adds r7, #12 - 8005556: 46bd mov sp, r7 - 8005558: bc80 pop {r7} - 800555a: 4770 bx lr - -0800555c <_fstat>: - - -int _fstat(int file, struct stat *st) -{ - 800555c: b480 push {r7} - 800555e: b083 sub sp, #12 - 8005560: af00 add r7, sp, #0 - 8005562: 6078 str r0, [r7, #4] - 8005564: 6039 str r1, [r7, #0] - (void)file; - st->st_mode = S_IFCHR; - 8005566: 683b ldr r3, [r7, #0] - 8005568: f44f 5200 mov.w r2, #8192 @ 0x2000 - 800556c: 605a str r2, [r3, #4] - return 0; - 800556e: 2300 movs r3, #0 -} - 8005570: 4618 mov r0, r3 - 8005572: 370c adds r7, #12 - 8005574: 46bd mov sp, r7 - 8005576: bc80 pop {r7} - 8005578: 4770 bx lr - -0800557a <_isatty>: - -int _isatty(int file) -{ - 800557a: b480 push {r7} - 800557c: b083 sub sp, #12 - 800557e: af00 add r7, sp, #0 - 8005580: 6078 str r0, [r7, #4] - (void)file; - return 1; - 8005582: 2301 movs r3, #1 -} - 8005584: 4618 mov r0, r3 - 8005586: 370c adds r7, #12 - 8005588: 46bd mov sp, r7 - 800558a: bc80 pop {r7} - 800558c: 4770 bx lr - -0800558e <_lseek>: - -int _lseek(int file, int ptr, int dir) -{ - 800558e: b480 push {r7} - 8005590: b085 sub sp, #20 - 8005592: af00 add r7, sp, #0 - 8005594: 60f8 str r0, [r7, #12] - 8005596: 60b9 str r1, [r7, #8] - 8005598: 607a str r2, [r7, #4] - (void)file; - (void)ptr; - (void)dir; - return 0; - 800559a: 2300 movs r3, #0 -} - 800559c: 4618 mov r0, r3 - 800559e: 3714 adds r7, #20 - 80055a0: 46bd mov sp, r7 - 80055a2: bc80 pop {r7} - 80055a4: 4770 bx lr - ... - -080055a8 <_sbrk>: - * - * @param incr Memory size - * @return Pointer to allocated memory - */ -void *_sbrk(ptrdiff_t incr) -{ - 80055a8: b580 push {r7, lr} - 80055aa: b086 sub sp, #24 - 80055ac: af00 add r7, sp, #0 - 80055ae: 6078 str r0, [r7, #4] - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - 80055b0: 4a14 ldr r2, [pc, #80] @ (8005604 <_sbrk+0x5c>) - 80055b2: 4b15 ldr r3, [pc, #84] @ (8005608 <_sbrk+0x60>) - 80055b4: 1ad3 subs r3, r2, r3 - 80055b6: 617b str r3, [r7, #20] - const uint8_t *max_heap = (uint8_t *)stack_limit; - 80055b8: 697b ldr r3, [r7, #20] - 80055ba: 613b str r3, [r7, #16] - uint8_t *prev_heap_end; - - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - 80055bc: 4b13 ldr r3, [pc, #76] @ (800560c <_sbrk+0x64>) - 80055be: 681b ldr r3, [r3, #0] - 80055c0: 2b00 cmp r3, #0 - 80055c2: d102 bne.n 80055ca <_sbrk+0x22> - { - __sbrk_heap_end = &_end; - 80055c4: 4b11 ldr r3, [pc, #68] @ (800560c <_sbrk+0x64>) - 80055c6: 4a12 ldr r2, [pc, #72] @ (8005610 <_sbrk+0x68>) - 80055c8: 601a str r2, [r3, #0] - } - - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - 80055ca: 4b10 ldr r3, [pc, #64] @ (800560c <_sbrk+0x64>) - 80055cc: 681a ldr r2, [r3, #0] - 80055ce: 687b ldr r3, [r7, #4] - 80055d0: 4413 add r3, r2 - 80055d2: 693a ldr r2, [r7, #16] - 80055d4: 429a cmp r2, r3 - 80055d6: d207 bcs.n 80055e8 <_sbrk+0x40> - { - errno = ENOMEM; - 80055d8: f005 fa10 bl 800a9fc <__errno> - 80055dc: 4603 mov r3, r0 - 80055de: 220c movs r2, #12 - 80055e0: 601a str r2, [r3, #0] - return (void *)-1; - 80055e2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 80055e6: e009 b.n 80055fc <_sbrk+0x54> - } - - prev_heap_end = __sbrk_heap_end; - 80055e8: 4b08 ldr r3, [pc, #32] @ (800560c <_sbrk+0x64>) - 80055ea: 681b ldr r3, [r3, #0] - 80055ec: 60fb str r3, [r7, #12] - __sbrk_heap_end += incr; - 80055ee: 4b07 ldr r3, [pc, #28] @ (800560c <_sbrk+0x64>) - 80055f0: 681a ldr r2, [r3, #0] - 80055f2: 687b ldr r3, [r7, #4] - 80055f4: 4413 add r3, r2 - 80055f6: 4a05 ldr r2, [pc, #20] @ (800560c <_sbrk+0x64>) - 80055f8: 6013 str r3, [r2, #0] - - return (void *)prev_heap_end; - 80055fa: 68fb ldr r3, [r7, #12] -} - 80055fc: 4618 mov r0, r3 - 80055fe: 3718 adds r7, #24 - 8005600: 46bd mov sp, r7 - 8005602: bd80 pop {r7, pc} - 8005604: 20010000 .word 0x20010000 - 8005608: 00000400 .word 0x00000400 - 800560c: 20003350 .word 0x20003350 - 8005610: 20003510 .word 0x20003510 - -08005614 : - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - 8005614: b480 push {r7} - 8005616: af00 add r7, sp, #0 - - /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#endif /* USER_VECT_TAB_ADDRESS */ -} - 8005618: bf00 nop - 800561a: 46bd mov sp, r7 - 800561c: bc80 pop {r7} - 800561e: 4770 bx lr - -08005620 : -UART_HandleTypeDef huart2; - -/* USART2 init function */ - -void MX_USART2_UART_Init(void) -{ - 8005620: b580 push {r7, lr} - 8005622: af00 add r7, sp, #0 - /* USER CODE END USART2_Init 0 */ - - /* USER CODE BEGIN USART2_Init 1 */ - - /* USER CODE END USART2_Init 1 */ - huart2.Instance = USART2; - 8005624: 4b11 ldr r3, [pc, #68] @ (800566c ) - 8005626: 4a12 ldr r2, [pc, #72] @ (8005670 ) - 8005628: 601a str r2, [r3, #0] - huart2.Init.BaudRate = 115200; - 800562a: 4b10 ldr r3, [pc, #64] @ (800566c ) - 800562c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 - 8005630: 605a str r2, [r3, #4] - huart2.Init.WordLength = UART_WORDLENGTH_8B; - 8005632: 4b0e ldr r3, [pc, #56] @ (800566c ) - 8005634: 2200 movs r2, #0 - 8005636: 609a str r2, [r3, #8] - huart2.Init.StopBits = UART_STOPBITS_1; - 8005638: 4b0c ldr r3, [pc, #48] @ (800566c ) - 800563a: 2200 movs r2, #0 - 800563c: 60da str r2, [r3, #12] - huart2.Init.Parity = UART_PARITY_NONE; - 800563e: 4b0b ldr r3, [pc, #44] @ (800566c ) - 8005640: 2200 movs r2, #0 - 8005642: 611a str r2, [r3, #16] - huart2.Init.Mode = UART_MODE_TX_RX; - 8005644: 4b09 ldr r3, [pc, #36] @ (800566c ) - 8005646: 220c movs r2, #12 - 8005648: 615a str r2, [r3, #20] - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 800564a: 4b08 ldr r3, [pc, #32] @ (800566c ) - 800564c: 2200 movs r2, #0 - 800564e: 619a str r2, [r3, #24] - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 8005650: 4b06 ldr r3, [pc, #24] @ (800566c ) - 8005652: 2200 movs r2, #0 - 8005654: 61da str r2, [r3, #28] - if (HAL_UART_Init(&huart2) != HAL_OK) - 8005656: 4805 ldr r0, [pc, #20] @ (800566c ) - 8005658: f003 f9af bl 80089ba - 800565c: 4603 mov r3, r0 - 800565e: 2b00 cmp r3, #0 - 8005660: d001 beq.n 8005666 - { - Error_Handler(); - 8005662: f7ff fcbd bl 8004fe0 - } - /* USER CODE BEGIN USART2_Init 2 */ - - /* USER CODE END USART2_Init 2 */ - -} - 8005666: bf00 nop - 8005668: bd80 pop {r7, pc} - 800566a: bf00 nop - 800566c: 20003354 .word 0x20003354 - 8005670: 40004400 .word 0x40004400 - -08005674 : - -void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) -{ - 8005674: b580 push {r7, lr} - 8005676: b08a sub sp, #40 @ 0x28 - 8005678: af00 add r7, sp, #0 - 800567a: 6078 str r0, [r7, #4] - - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800567c: f107 0314 add.w r3, r7, #20 - 8005680: 2200 movs r2, #0 - 8005682: 601a str r2, [r3, #0] - 8005684: 605a str r2, [r3, #4] - 8005686: 609a str r2, [r3, #8] - 8005688: 60da str r2, [r3, #12] - if(uartHandle->Instance==USART2) - 800568a: 687b ldr r3, [r7, #4] - 800568c: 681b ldr r3, [r3, #0] - 800568e: 4a26 ldr r2, [pc, #152] @ (8005728 ) - 8005690: 4293 cmp r3, r2 - 8005692: d145 bne.n 8005720 - { - /* USER CODE BEGIN USART2_MspInit 0 */ - - /* USER CODE END USART2_MspInit 0 */ - /* USART2 clock enable */ - __HAL_RCC_USART2_CLK_ENABLE(); - 8005694: 4b25 ldr r3, [pc, #148] @ (800572c ) - 8005696: 69db ldr r3, [r3, #28] - 8005698: 4a24 ldr r2, [pc, #144] @ (800572c ) - 800569a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 800569e: 61d3 str r3, [r2, #28] - 80056a0: 4b22 ldr r3, [pc, #136] @ (800572c ) - 80056a2: 69db ldr r3, [r3, #28] - 80056a4: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80056a8: 613b str r3, [r7, #16] - 80056aa: 693b ldr r3, [r7, #16] - - __HAL_RCC_GPIOD_CLK_ENABLE(); - 80056ac: 4b1f ldr r3, [pc, #124] @ (800572c ) - 80056ae: 699b ldr r3, [r3, #24] - 80056b0: 4a1e ldr r2, [pc, #120] @ (800572c ) - 80056b2: f043 0320 orr.w r3, r3, #32 - 80056b6: 6193 str r3, [r2, #24] - 80056b8: 4b1c ldr r3, [pc, #112] @ (800572c ) - 80056ba: 699b ldr r3, [r3, #24] - 80056bc: f003 0320 and.w r3, r3, #32 - 80056c0: 60fb str r3, [r7, #12] - 80056c2: 68fb ldr r3, [r7, #12] - /**USART2 GPIO Configuration - PD5 ------> USART2_TX - PD6 ------> USART2_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_5; - 80056c4: 2320 movs r3, #32 - 80056c6: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80056c8: 2302 movs r3, #2 - 80056ca: 61bb str r3, [r7, #24] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - 80056cc: 2303 movs r3, #3 - 80056ce: 623b str r3, [r7, #32] - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 80056d0: f107 0314 add.w r3, r7, #20 - 80056d4: 4619 mov r1, r3 - 80056d6: 4816 ldr r0, [pc, #88] @ (8005730 ) - 80056d8: f001 feda bl 8007490 - - GPIO_InitStruct.Pin = GPIO_PIN_6; - 80056dc: 2340 movs r3, #64 @ 0x40 - 80056de: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 80056e0: 2300 movs r3, #0 - 80056e2: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 80056e4: 2300 movs r3, #0 - 80056e6: 61fb str r3, [r7, #28] - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 80056e8: f107 0314 add.w r3, r7, #20 - 80056ec: 4619 mov r1, r3 - 80056ee: 4810 ldr r0, [pc, #64] @ (8005730 ) - 80056f0: f001 fece bl 8007490 - - __HAL_AFIO_REMAP_USART2_ENABLE(); - 80056f4: 4b0f ldr r3, [pc, #60] @ (8005734 ) - 80056f6: 685b ldr r3, [r3, #4] - 80056f8: 627b str r3, [r7, #36] @ 0x24 - 80056fa: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056fc: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 - 8005700: 627b str r3, [r7, #36] @ 0x24 - 8005702: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005704: f043 0308 orr.w r3, r3, #8 - 8005708: 627b str r3, [r7, #36] @ 0x24 - 800570a: 4a0a ldr r2, [pc, #40] @ (8005734 ) - 800570c: 6a7b ldr r3, [r7, #36] @ 0x24 - 800570e: 6053 str r3, [r2, #4] - - /* USART2 interrupt Init */ - HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); - 8005710: 2200 movs r2, #0 - 8005712: 2100 movs r1, #0 - 8005714: 2026 movs r0, #38 @ 0x26 - 8005716: f001 fd42 bl 800719e - HAL_NVIC_EnableIRQ(USART2_IRQn); - 800571a: 2026 movs r0, #38 @ 0x26 - 800571c: f001 fd5b bl 80071d6 - /* USER CODE BEGIN USART2_MspInit 1 */ - - /* USER CODE END USART2_MspInit 1 */ - } -} - 8005720: bf00 nop - 8005722: 3728 adds r7, #40 @ 0x28 - 8005724: 46bd mov sp, r7 - 8005726: bd80 pop {r7, pc} - 8005728: 40004400 .word 0x40004400 - 800572c: 40021000 .word 0x40021000 - 8005730: 40011400 .word 0x40011400 - 8005734: 40010000 .word 0x40010000 - -08005738 : - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Call the clock system initialization function.*/ - bl SystemInit - 8005738: f7ff ff6c bl 8005614 - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - 800573c: 480b ldr r0, [pc, #44] @ (800576c ) - ldr r1, =_edata - 800573e: 490c ldr r1, [pc, #48] @ (8005770 ) - ldr r2, =_sidata - 8005740: 4a0c ldr r2, [pc, #48] @ (8005774 ) - movs r3, #0 - 8005742: 2300 movs r3, #0 - b LoopCopyDataInit - 8005744: e002 b.n 800574c - -08005746 : - -CopyDataInit: - ldr r4, [r2, r3] - 8005746: 58d4 ldr r4, [r2, r3] - str r4, [r0, r3] - 8005748: 50c4 str r4, [r0, r3] - adds r3, r3, #4 - 800574a: 3304 adds r3, #4 - -0800574c : - -LoopCopyDataInit: - adds r4, r0, r3 - 800574c: 18c4 adds r4, r0, r3 - cmp r4, r1 - 800574e: 428c cmp r4, r1 - bcc CopyDataInit - 8005750: d3f9 bcc.n 8005746 - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - 8005752: 4a09 ldr r2, [pc, #36] @ (8005778 ) - ldr r4, =_ebss - 8005754: 4c09 ldr r4, [pc, #36] @ (800577c ) - movs r3, #0 - 8005756: 2300 movs r3, #0 - b LoopFillZerobss - 8005758: e001 b.n 800575e - -0800575a : - -FillZerobss: - str r3, [r2] - 800575a: 6013 str r3, [r2, #0] - adds r2, r2, #4 - 800575c: 3204 adds r2, #4 - -0800575e : - -LoopFillZerobss: - cmp r2, r4 - 800575e: 42a2 cmp r2, r4 - bcc FillZerobss - 8005760: d3fb bcc.n 800575a - - -/* Call static constructors */ - bl __libc_init_array - 8005762: f005 f951 bl 800aa08 <__libc_init_array> -/* Call the application's entry point.*/ - bl main - 8005766: f7ff fb83 bl 8004e70
- bx lr - 800576a: 4770 bx lr - ldr r0, =_sdata - 800576c: 20000000 .word 0x20000000 - ldr r1, =_edata - 8005770: 2000023c .word 0x2000023c - ldr r2, =_sidata - 8005774: 0800e500 .word 0x0800e500 - ldr r2, =_sbss - 8005778: 2000023c .word 0x2000023c - ldr r4, =_ebss - 800577c: 2000350c .word 0x2000350c - -08005780 : - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - 8005780: e7fe b.n 8005780 - ... - -08005784 : - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - 8005784: b580 push {r7, lr} - 8005786: af00 add r7, sp, #0 - defined(STM32F102x6) || defined(STM32F102xB) || \ - defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ - defined(STM32F105xC) || defined(STM32F107xC) - - /* Prefetch buffer is not available on value line devices */ - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 8005788: 4b08 ldr r3, [pc, #32] @ (80057ac ) - 800578a: 681b ldr r3, [r3, #0] - 800578c: 4a07 ldr r2, [pc, #28] @ (80057ac ) - 800578e: f043 0310 orr.w r3, r3, #16 - 8005792: 6013 str r3, [r2, #0] -#endif -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8005794: 2003 movs r0, #3 - 8005796: f001 fcf7 bl 8007188 - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - 800579a: 200f movs r0, #15 - 800579c: f000 f808 bl 80057b0 - - /* Init the low level hardware */ - HAL_MspInit(); - 80057a0: f7ff fe0c bl 80053bc - - /* Return function status */ - return HAL_OK; - 80057a4: 2300 movs r3, #0 -} - 80057a6: 4618 mov r0, r3 - 80057a8: bd80 pop {r7, pc} - 80057aa: bf00 nop - 80057ac: 40022000 .word 0x40022000 - -080057b0 : - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - 80057b0: b580 push {r7, lr} - 80057b2: b082 sub sp, #8 - 80057b4: af00 add r7, sp, #0 - 80057b6: 6078 str r0, [r7, #4] - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 80057b8: 4b12 ldr r3, [pc, #72] @ (8005804 ) - 80057ba: 681a ldr r2, [r3, #0] - 80057bc: 4b12 ldr r3, [pc, #72] @ (8005808 ) - 80057be: 781b ldrb r3, [r3, #0] - 80057c0: 4619 mov r1, r3 - 80057c2: f44f 737a mov.w r3, #1000 @ 0x3e8 - 80057c6: fbb3 f3f1 udiv r3, r3, r1 - 80057ca: fbb2 f3f3 udiv r3, r2, r3 - 80057ce: 4618 mov r0, r3 - 80057d0: f001 fd0f bl 80071f2 - 80057d4: 4603 mov r3, r0 - 80057d6: 2b00 cmp r3, #0 - 80057d8: d001 beq.n 80057de - { - return HAL_ERROR; - 80057da: 2301 movs r3, #1 - 80057dc: e00e b.n 80057fc - } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 80057de: 687b ldr r3, [r7, #4] - 80057e0: 2b0f cmp r3, #15 - 80057e2: d80a bhi.n 80057fa - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80057e4: 2200 movs r2, #0 - 80057e6: 6879 ldr r1, [r7, #4] - 80057e8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 80057ec: f001 fcd7 bl 800719e - uwTickPrio = TickPriority; - 80057f0: 4a06 ldr r2, [pc, #24] @ (800580c ) - 80057f2: 687b ldr r3, [r7, #4] - 80057f4: 6013 str r3, [r2, #0] - { - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; - 80057f6: 2300 movs r3, #0 - 80057f8: e000 b.n 80057fc - return HAL_ERROR; - 80057fa: 2301 movs r3, #1 -} - 80057fc: 4618 mov r0, r3 - 80057fe: 3708 adds r7, #8 - 8005800: 46bd mov sp, r7 - 8005802: bd80 pop {r7, pc} - 8005804: 20000008 .word 0x20000008 - 8005808: 20000010 .word 0x20000010 - 800580c: 2000000c .word 0x2000000c - -08005810 : - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - 8005810: b480 push {r7} - 8005812: af00 add r7, sp, #0 - uwTick += uwTickFreq; - 8005814: 4b05 ldr r3, [pc, #20] @ (800582c ) - 8005816: 781b ldrb r3, [r3, #0] - 8005818: 461a mov r2, r3 - 800581a: 4b05 ldr r3, [pc, #20] @ (8005830 ) - 800581c: 681b ldr r3, [r3, #0] - 800581e: 4413 add r3, r2 - 8005820: 4a03 ldr r2, [pc, #12] @ (8005830 ) - 8005822: 6013 str r3, [r2, #0] -} - 8005824: bf00 nop - 8005826: 46bd mov sp, r7 - 8005828: bc80 pop {r7} - 800582a: 4770 bx lr - 800582c: 20000010 .word 0x20000010 - 8005830: 20003398 .word 0x20003398 - -08005834 : - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - 8005834: b480 push {r7} - 8005836: af00 add r7, sp, #0 - return uwTick; - 8005838: 4b02 ldr r3, [pc, #8] @ (8005844 ) - 800583a: 681b ldr r3, [r3, #0] -} - 800583c: 4618 mov r0, r3 - 800583e: 46bd mov sp, r7 - 8005840: bc80 pop {r7} - 8005842: 4770 bx lr - 8005844: 20003398 .word 0x20003398 - -08005848 : - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - 8005848: b580 push {r7, lr} - 800584a: b084 sub sp, #16 - 800584c: af00 add r7, sp, #0 - 800584e: 6078 str r0, [r7, #4] - uint32_t tickstart = HAL_GetTick(); - 8005850: f7ff fff0 bl 8005834 - 8005854: 60b8 str r0, [r7, #8] - uint32_t wait = Delay; - 8005856: 687b ldr r3, [r7, #4] - 8005858: 60fb str r3, [r7, #12] - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - 800585a: 68fb ldr r3, [r7, #12] - 800585c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8005860: d005 beq.n 800586e - { - wait += (uint32_t)(uwTickFreq); - 8005862: 4b0a ldr r3, [pc, #40] @ (800588c ) - 8005864: 781b ldrb r3, [r3, #0] - 8005866: 461a mov r2, r3 - 8005868: 68fb ldr r3, [r7, #12] - 800586a: 4413 add r3, r2 - 800586c: 60fb str r3, [r7, #12] - } - - while ((HAL_GetTick() - tickstart) < wait) - 800586e: bf00 nop - 8005870: f7ff ffe0 bl 8005834 - 8005874: 4602 mov r2, r0 - 8005876: 68bb ldr r3, [r7, #8] - 8005878: 1ad3 subs r3, r2, r3 - 800587a: 68fa ldr r2, [r7, #12] - 800587c: 429a cmp r2, r3 - 800587e: d8f7 bhi.n 8005870 - { - } -} - 8005880: bf00 nop - 8005882: bf00 nop - 8005884: 3710 adds r7, #16 - 8005886: 46bd mov sp, r7 - 8005888: bd80 pop {r7, pc} - 800588a: bf00 nop - 800588c: 20000010 .word 0x20000010 - -08005890 : - * of structure "ADC_InitTypeDef". - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - 8005890: b580 push {r7, lr} - 8005892: b086 sub sp, #24 - 8005894: af00 add r7, sp, #0 - 8005896: 6078 str r0, [r7, #4] - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8005898: 2300 movs r3, #0 - 800589a: 75fb strb r3, [r7, #23] - uint32_t tmp_cr1 = 0U; - 800589c: 2300 movs r3, #0 - 800589e: 613b str r3, [r7, #16] - uint32_t tmp_cr2 = 0U; - 80058a0: 2300 movs r3, #0 - 80058a2: 60bb str r3, [r7, #8] - uint32_t tmp_sqr1 = 0U; - 80058a4: 2300 movs r3, #0 - 80058a6: 60fb str r3, [r7, #12] - - /* Check ADC handle */ - if(hadc == NULL) - 80058a8: 687b ldr r3, [r7, #4] - 80058aa: 2b00 cmp r3, #0 - 80058ac: d101 bne.n 80058b2 - { - return HAL_ERROR; - 80058ae: 2301 movs r3, #1 - 80058b0: e0be b.n 8005a30 - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 80058b2: 687b ldr r3, [r7, #4] - 80058b4: 689b ldr r3, [r3, #8] - 80058b6: 2b00 cmp r3, #0 - /* Refer to header of this file for more details on clock enabling */ - /* procedure. */ - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) - 80058b8: 687b ldr r3, [r7, #4] - 80058ba: 6a9b ldr r3, [r3, #40] @ 0x28 - 80058bc: 2b00 cmp r3, #0 - 80058be: d109 bne.n 80058d4 - { - /* Initialize ADC error code */ - ADC_CLEAR_ERRORCODE(hadc); - 80058c0: 687b ldr r3, [r7, #4] - 80058c2: 2200 movs r2, #0 - 80058c4: 62da str r2, [r3, #44] @ 0x2c - - /* Allocate lock resource and initialize it */ - hadc->Lock = HAL_UNLOCKED; - 80058c6: 687b ldr r3, [r7, #4] - 80058c8: 2200 movs r2, #0 - 80058ca: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Init the low level hardware */ - hadc->MspInitCallback(hadc); -#else - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); - 80058ce: 6878 ldr r0, [r7, #4] - 80058d0: f7fb fe9e bl 8001610 - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - /* Note: In case of ADC already enabled, precaution to not launch an */ - /* unwanted conversion while modifying register CR2 by writing 1 to */ - /* bit ADON. */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - 80058d4: 6878 ldr r0, [r7, #4] - 80058d6: f000 fbf1 bl 80060bc - 80058da: 4603 mov r3, r0 - 80058dc: 75fb strb r3, [r7, #23] - - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - 80058de: 687b ldr r3, [r7, #4] - 80058e0: 6a9b ldr r3, [r3, #40] @ 0x28 - 80058e2: f003 0310 and.w r3, r3, #16 - 80058e6: 2b00 cmp r3, #0 - 80058e8: f040 8099 bne.w 8005a1e - 80058ec: 7dfb ldrb r3, [r7, #23] - 80058ee: 2b00 cmp r3, #0 - 80058f0: f040 8095 bne.w 8005a1e - (tmp_hal_status == HAL_OK) ) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - 80058f4: 687b ldr r3, [r7, #4] - 80058f6: 6a9b ldr r3, [r3, #40] @ 0x28 - 80058f8: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 80058fc: f023 0302 bic.w r3, r3, #2 - 8005900: f043 0202 orr.w r2, r3, #2 - 8005904: 687b ldr r3, [r7, #4] - 8005906: 629a str r2, [r3, #40] @ 0x28 - /* - continuous conversion mode */ - /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ - /* HAL_ADC_Start_xxx functions because if set in this function, */ - /* a conversion on injected group would start a conversion also on */ - /* regular group after ADC enabling. */ - tmp_cr2 |= (hadc->Init.DataAlign | - 8005908: 687b ldr r3, [r7, #4] - 800590a: 685a ldr r2, [r3, #4] - ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | - 800590c: 687b ldr r3, [r7, #4] - 800590e: 69db ldr r3, [r3, #28] - tmp_cr2 |= (hadc->Init.DataAlign | - 8005910: 431a orrs r2, r3 - ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); - 8005912: 687b ldr r3, [r7, #4] - 8005914: 7b1b ldrb r3, [r3, #12] - 8005916: 005b lsls r3, r3, #1 - ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | - 8005918: 4313 orrs r3, r2 - tmp_cr2 |= (hadc->Init.DataAlign | - 800591a: 68ba ldr r2, [r7, #8] - 800591c: 4313 orrs r3, r2 - 800591e: 60bb str r3, [r7, #8] - - /* Configuration of ADC: */ - /* - scan mode */ - /* - discontinuous mode disable/enable */ - /* - discontinuous mode number of conversions */ - tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); - 8005920: 687b ldr r3, [r7, #4] - 8005922: 689b ldr r3, [r3, #8] - 8005924: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 8005928: d003 beq.n 8005932 - 800592a: 687b ldr r3, [r7, #4] - 800592c: 689b ldr r3, [r3, #8] - 800592e: 2b01 cmp r3, #1 - 8005930: d102 bne.n 8005938 - 8005932: f44f 7380 mov.w r3, #256 @ 0x100 - 8005936: e000 b.n 800593a - 8005938: 2300 movs r3, #0 - 800593a: 693a ldr r2, [r7, #16] - 800593c: 4313 orrs r3, r2 - 800593e: 613b str r3, [r7, #16] - - /* Enable discontinuous mode only if continuous mode is disabled */ - /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ - /* discontinuous is set anyway, but will have no effect on ADC HW. */ - if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8005940: 687b ldr r3, [r7, #4] - 8005942: 7d1b ldrb r3, [r3, #20] - 8005944: 2b01 cmp r3, #1 - 8005946: d119 bne.n 800597c - { - if (hadc->Init.ContinuousConvMode == DISABLE) - 8005948: 687b ldr r3, [r7, #4] - 800594a: 7b1b ldrb r3, [r3, #12] - 800594c: 2b00 cmp r3, #0 - 800594e: d109 bne.n 8005964 - { - /* Enable the selected ADC regular discontinuous mode */ - /* Set the number of channels to be converted in discontinuous mode */ - SET_BIT(tmp_cr1, ADC_CR1_DISCEN | - 8005950: 687b ldr r3, [r7, #4] - 8005952: 699b ldr r3, [r3, #24] - 8005954: 3b01 subs r3, #1 - 8005956: 035a lsls r2, r3, #13 - 8005958: 693b ldr r3, [r7, #16] - 800595a: 4313 orrs r3, r2 - 800595c: f443 6300 orr.w r3, r3, #2048 @ 0x800 - 8005960: 613b str r3, [r7, #16] - 8005962: e00b b.n 800597c - { - /* ADC regular group settings continuous and sequencer discontinuous*/ - /* cannot be enabled simultaneously. */ - - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8005964: 687b ldr r3, [r7, #4] - 8005966: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005968: f043 0220 orr.w r2, r3, #32 - 800596c: 687b ldr r3, [r7, #4] - 800596e: 629a str r2, [r3, #40] @ 0x28 - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8005970: 687b ldr r3, [r7, #4] - 8005972: 6adb ldr r3, [r3, #44] @ 0x2c - 8005974: f043 0201 orr.w r2, r3, #1 - 8005978: 687b ldr r3, [r7, #4] - 800597a: 62da str r2, [r3, #44] @ 0x2c - } - } - - /* Update ADC configuration register CR1 with previous settings */ - MODIFY_REG(hadc->Instance->CR1, - 800597c: 687b ldr r3, [r7, #4] - 800597e: 681b ldr r3, [r3, #0] - 8005980: 685b ldr r3, [r3, #4] - 8005982: f423 4169 bic.w r1, r3, #59648 @ 0xe900 - 8005986: 687b ldr r3, [r7, #4] - 8005988: 681b ldr r3, [r3, #0] - 800598a: 693a ldr r2, [r7, #16] - 800598c: 430a orrs r2, r1 - 800598e: 605a str r2, [r3, #4] - ADC_CR1_DISCEN | - ADC_CR1_DISCNUM , - tmp_cr1 ); - - /* Update ADC configuration register CR2 with previous settings */ - MODIFY_REG(hadc->Instance->CR2, - 8005990: 687b ldr r3, [r7, #4] - 8005992: 681b ldr r3, [r3, #0] - 8005994: 689a ldr r2, [r3, #8] - 8005996: 4b28 ldr r3, [pc, #160] @ (8005a38 ) - 8005998: 4013 ands r3, r2 - 800599a: 687a ldr r2, [r7, #4] - 800599c: 6812 ldr r2, [r2, #0] - 800599e: 68b9 ldr r1, [r7, #8] - 80059a0: 430b orrs r3, r1 - 80059a2: 6093 str r3, [r2, #8] - /* Note: Scan mode is present by hardware on this device and, if */ - /* disabled, discards automatically nb of conversions. Anyway, nb of */ - /* conversions is forced to 0x00 for alignment over all STM32 devices. */ - /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion" */ - if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) - 80059a4: 687b ldr r3, [r7, #4] - 80059a6: 689b ldr r3, [r3, #8] - 80059a8: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 80059ac: d003 beq.n 80059b6 - 80059ae: 687b ldr r3, [r7, #4] - 80059b0: 689b ldr r3, [r3, #8] - 80059b2: 2b01 cmp r3, #1 - 80059b4: d104 bne.n 80059c0 - { - tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); - 80059b6: 687b ldr r3, [r7, #4] - 80059b8: 691b ldr r3, [r3, #16] - 80059ba: 3b01 subs r3, #1 - 80059bc: 051b lsls r3, r3, #20 - 80059be: 60fb str r3, [r7, #12] - } - - MODIFY_REG(hadc->Instance->SQR1, - 80059c0: 687b ldr r3, [r7, #4] - 80059c2: 681b ldr r3, [r3, #0] - 80059c4: 6adb ldr r3, [r3, #44] @ 0x2c - 80059c6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 - 80059ca: 687b ldr r3, [r7, #4] - 80059cc: 681b ldr r3, [r3, #0] - 80059ce: 68fa ldr r2, [r7, #12] - 80059d0: 430a orrs r2, r1 - 80059d2: 62da str r2, [r3, #44] @ 0x2c - /* ensure of no potential problem of ADC core IP clocking. */ - /* Check through register CR2 (excluding bits set in other functions: */ - /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ - /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ - /* measurement path bit (TSVREFE). */ - if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | - 80059d4: 687b ldr r3, [r7, #4] - 80059d6: 681b ldr r3, [r3, #0] - 80059d8: 689a ldr r2, [r3, #8] - 80059da: 4b18 ldr r3, [pc, #96] @ (8005a3c ) - 80059dc: 4013 ands r3, r2 - 80059de: 68ba ldr r2, [r7, #8] - 80059e0: 429a cmp r2, r3 - 80059e2: d10b bne.n 80059fc - ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | - ADC_CR2_TSVREFE )) - == tmp_cr2) - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - 80059e4: 687b ldr r3, [r7, #4] - 80059e6: 2200 movs r2, #0 - 80059e8: 62da str r2, [r3, #44] @ 0x2c - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - 80059ea: 687b ldr r3, [r7, #4] - 80059ec: 6a9b ldr r3, [r3, #40] @ 0x28 - 80059ee: f023 0303 bic.w r3, r3, #3 - 80059f2: f043 0201 orr.w r2, r3, #1 - 80059f6: 687b ldr r3, [r7, #4] - 80059f8: 629a str r2, [r3, #40] @ 0x28 - if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | - 80059fa: e018 b.n 8005a2e - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - 80059fc: 687b ldr r3, [r7, #4] - 80059fe: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005a00: f023 0312 bic.w r3, r3, #18 - 8005a04: f043 0210 orr.w r2, r3, #16 - 8005a08: 687b ldr r3, [r7, #4] - 8005a0a: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8005a0c: 687b ldr r3, [r7, #4] - 8005a0e: 6adb ldr r3, [r3, #44] @ 0x2c - 8005a10: f043 0201 orr.w r2, r3, #1 - 8005a14: 687b ldr r3, [r7, #4] - 8005a16: 62da str r2, [r3, #44] @ 0x2c - - tmp_hal_status = HAL_ERROR; - 8005a18: 2301 movs r3, #1 - 8005a1a: 75fb strb r3, [r7, #23] - if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | - 8005a1c: e007 b.n 8005a2e - - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8005a1e: 687b ldr r3, [r7, #4] - 8005a20: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005a22: f043 0210 orr.w r2, r3, #16 - 8005a26: 687b ldr r3, [r7, #4] - 8005a28: 629a str r2, [r3, #40] @ 0x28 - - tmp_hal_status = HAL_ERROR; - 8005a2a: 2301 movs r3, #1 - 8005a2c: 75fb strb r3, [r7, #23] - } - - /* Return function status */ - return tmp_hal_status; - 8005a2e: 7dfb ldrb r3, [r7, #23] -} - 8005a30: 4618 mov r0, r3 - 8005a32: 3718 adds r7, #24 - 8005a34: 46bd mov sp, r7 - 8005a36: bd80 pop {r7, pc} - 8005a38: ffe1f7fd .word 0xffe1f7fd - 8005a3c: ff1f0efe .word 0xff1f0efe - -08005a40 : - * Interruptions enabled in this function: None. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - 8005a40: b580 push {r7, lr} - 8005a42: b084 sub sp, #16 - 8005a44: af00 add r7, sp, #0 - 8005a46: 6078 str r0, [r7, #4] - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8005a48: 2300 movs r3, #0 - 8005a4a: 73fb strb r3, [r7, #15] - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - 8005a4c: 687b ldr r3, [r7, #4] - 8005a4e: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 8005a52: 2b01 cmp r3, #1 - 8005a54: d101 bne.n 8005a5a - 8005a56: 2302 movs r3, #2 - 8005a58: e098 b.n 8005b8c - 8005a5a: 687b ldr r3, [r7, #4] - 8005a5c: 2201 movs r2, #1 - 8005a5e: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - 8005a62: 6878 ldr r0, [r7, #4] - 8005a64: f000 fad0 bl 8006008 - 8005a68: 4603 mov r3, r0 - 8005a6a: 73fb strb r3, [r7, #15] - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - 8005a6c: 7bfb ldrb r3, [r7, #15] - 8005a6e: 2b00 cmp r3, #0 - 8005a70: f040 8087 bne.w 8005b82 - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - 8005a74: 687b ldr r3, [r7, #4] - 8005a76: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005a78: f423 7340 bic.w r3, r3, #768 @ 0x300 - 8005a7c: f023 0301 bic.w r3, r3, #1 - 8005a80: f443 7280 orr.w r2, r3, #256 @ 0x100 - 8005a84: 687b ldr r3, [r7, #4] - 8005a86: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_REG_BUSY); - - /* Set group injected state (from auto-injection) and multimode state */ - /* for all cases of multimode: independent mode, multimode ADC master */ - /* or multimode ADC slave (for devices with several ADCs): */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - 8005a88: 687b ldr r3, [r7, #4] - 8005a8a: 681b ldr r3, [r3, #0] - 8005a8c: 4a41 ldr r2, [pc, #260] @ (8005b94 ) - 8005a8e: 4293 cmp r3, r2 - 8005a90: d105 bne.n 8005a9e - 8005a92: 4b41 ldr r3, [pc, #260] @ (8005b98 ) - 8005a94: 685b ldr r3, [r3, #4] - 8005a96: f403 2370 and.w r3, r3, #983040 @ 0xf0000 - 8005a9a: 2b00 cmp r3, #0 - 8005a9c: d115 bne.n 8005aca - { - /* Set ADC state (ADC independent or master) */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 8005a9e: 687b ldr r3, [r7, #4] - 8005aa0: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005aa2: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 - 8005aa6: 687b ldr r3, [r7, #4] - 8005aa8: 629a str r2, [r3, #40] @ 0x28 - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - 8005aaa: 687b ldr r3, [r7, #4] - 8005aac: 681b ldr r3, [r3, #0] - 8005aae: 685b ldr r3, [r3, #4] - 8005ab0: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8005ab4: 2b00 cmp r3, #0 - 8005ab6: d026 beq.n 8005b06 - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 8005ab8: 687b ldr r3, [r7, #4] - 8005aba: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005abc: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 8005ac0: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 8005ac4: 687b ldr r3, [r7, #4] - 8005ac6: 629a str r2, [r3, #40] @ 0x28 - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - 8005ac8: e01d b.n 8005b06 - } - } - else - { - /* Set ADC state (ADC slave) */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 8005aca: 687b ldr r3, [r7, #4] - 8005acc: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005ace: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 - 8005ad2: 687b ldr r3, [r7, #4] - 8005ad4: 629a str r2, [r3, #40] @ 0x28 - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) - 8005ad6: 687b ldr r3, [r7, #4] - 8005ad8: 681b ldr r3, [r3, #0] - 8005ada: 4a2f ldr r2, [pc, #188] @ (8005b98 ) - 8005adc: 4293 cmp r3, r2 - 8005ade: d004 beq.n 8005aea - 8005ae0: 687b ldr r3, [r7, #4] - 8005ae2: 681b ldr r3, [r3, #0] - 8005ae4: 4a2b ldr r2, [pc, #172] @ (8005b94 ) - 8005ae6: 4293 cmp r3, r2 - 8005ae8: d10d bne.n 8005b06 - 8005aea: 4b2b ldr r3, [pc, #172] @ (8005b98 ) - 8005aec: 685b ldr r3, [r3, #4] - 8005aee: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8005af2: 2b00 cmp r3, #0 - 8005af4: d007 beq.n 8005b06 - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 8005af6: 687b ldr r3, [r7, #4] - 8005af8: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005afa: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 8005afe: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 8005b02: 687b ldr r3, [r7, #4] - 8005b04: 629a str r2, [r3, #40] @ 0x28 - } - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 8005b06: 687b ldr r3, [r7, #4] - 8005b08: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005b0a: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8005b0e: 2b00 cmp r3, #0 - 8005b10: d006 beq.n 8005b20 - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - 8005b12: 687b ldr r3, [r7, #4] - 8005b14: 6adb ldr r3, [r3, #44] @ 0x2c - 8005b16: f023 0206 bic.w r2, r3, #6 - 8005b1a: 687b ldr r3, [r7, #4] - 8005b1c: 62da str r2, [r3, #44] @ 0x2c - 8005b1e: e002 b.n 8005b26 - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - 8005b20: 687b ldr r3, [r7, #4] - 8005b22: 2200 movs r2, #0 - 8005b24: 62da str r2, [r3, #44] @ 0x2c - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - 8005b26: 687b ldr r3, [r7, #4] - 8005b28: 2200 movs r2, #0 - 8005b2a: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Clear regular group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - 8005b2e: 687b ldr r3, [r7, #4] - 8005b30: 681b ldr r3, [r3, #0] - 8005b32: f06f 0202 mvn.w r2, #2 - 8005b36: 601a str r2, [r3, #0] - /* - if ADC is slave, ADC is enabled only (conversion is not started). */ - /* - if ADC is master, ADC is enabled and conversion is started. */ - /* If ADC is master, ADC is enabled and conversion is started. */ - /* Note: Alternate trigger for single conversion could be to force an */ - /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ - if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8005b38: 687b ldr r3, [r7, #4] - 8005b3a: 681b ldr r3, [r3, #0] - 8005b3c: 689b ldr r3, [r3, #8] - 8005b3e: f403 2360 and.w r3, r3, #917504 @ 0xe0000 - 8005b42: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 - 8005b46: d113 bne.n 8005b70 - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - 8005b48: 687b ldr r3, [r7, #4] - 8005b4a: 681b ldr r3, [r3, #0] - if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8005b4c: 4a11 ldr r2, [pc, #68] @ (8005b94 ) - 8005b4e: 4293 cmp r3, r2 - 8005b50: d105 bne.n 8005b5e - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - 8005b52: 4b11 ldr r3, [pc, #68] @ (8005b98 ) - 8005b54: 685b ldr r3, [r3, #4] - 8005b56: f403 2370 and.w r3, r3, #983040 @ 0xf0000 - if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8005b5a: 2b00 cmp r3, #0 - 8005b5c: d108 bne.n 8005b70 - { - /* Start ADC conversion on regular group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); - 8005b5e: 687b ldr r3, [r7, #4] - 8005b60: 681b ldr r3, [r3, #0] - 8005b62: 689a ldr r2, [r3, #8] - 8005b64: 687b ldr r3, [r7, #4] - 8005b66: 681b ldr r3, [r3, #0] - 8005b68: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 - 8005b6c: 609a str r2, [r3, #8] - 8005b6e: e00c b.n 8005b8a - } - else - { - /* Start ADC conversion on regular group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); - 8005b70: 687b ldr r3, [r7, #4] - 8005b72: 681b ldr r3, [r3, #0] - 8005b74: 689a ldr r2, [r3, #8] - 8005b76: 687b ldr r3, [r7, #4] - 8005b78: 681b ldr r3, [r3, #0] - 8005b7a: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 - 8005b7e: 609a str r2, [r3, #8] - 8005b80: e003 b.n 8005b8a - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005b82: 687b ldr r3, [r7, #4] - 8005b84: 2200 movs r2, #0 - 8005b86: f883 2024 strb.w r2, [r3, #36] @ 0x24 - } - - /* Return function status */ - return tmp_hal_status; - 8005b8a: 7bfb ldrb r3, [r7, #15] -} - 8005b8c: 4618 mov r0, r3 - 8005b8e: 3710 adds r7, #16 - 8005b90: 46bd mov sp, r7 - 8005b92: bd80 pop {r7, pc} - 8005b94: 40012800 .word 0x40012800 - 8005b98: 40012400 .word 0x40012400 - -08005b9c : - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - 8005b9c: b580 push {r7, lr} - 8005b9e: b084 sub sp, #16 - 8005ba0: af00 add r7, sp, #0 - 8005ba2: 6078 str r0, [r7, #4] - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8005ba4: 2300 movs r3, #0 - 8005ba6: 73fb strb r3, [r7, #15] - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - 8005ba8: 687b ldr r3, [r7, #4] - 8005baa: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 8005bae: 2b01 cmp r3, #1 - 8005bb0: d101 bne.n 8005bb6 - 8005bb2: 2302 movs r3, #2 - 8005bb4: e01a b.n 8005bec - 8005bb6: 687b ldr r3, [r7, #4] - 8005bb8: 2201 movs r2, #1 - 8005bba: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - 8005bbe: 6878 ldr r0, [r7, #4] - 8005bc0: f000 fa7c bl 80060bc - 8005bc4: 4603 mov r3, r0 - 8005bc6: 73fb strb r3, [r7, #15] - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - 8005bc8: 7bfb ldrb r3, [r7, #15] - 8005bca: 2b00 cmp r3, #0 - 8005bcc: d109 bne.n 8005be2 - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - 8005bce: 687b ldr r3, [r7, #4] - 8005bd0: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005bd2: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 8005bd6: f023 0301 bic.w r3, r3, #1 - 8005bda: f043 0201 orr.w r2, r3, #1 - 8005bde: 687b ldr r3, [r7, #4] - 8005be0: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005be2: 687b ldr r3, [r7, #4] - 8005be4: 2200 movs r2, #0 - 8005be6: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Return function status */ - return tmp_hal_status; - 8005bea: 7bfb ldrb r3, [r7, #15] -} - 8005bec: 4618 mov r0, r3 - 8005bee: 3710 adds r7, #16 - 8005bf0: 46bd mov sp, r7 - 8005bf2: bd80 pop {r7, pc} - -08005bf4 : - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - 8005bf4: b590 push {r4, r7, lr} - 8005bf6: b087 sub sp, #28 - 8005bf8: af00 add r7, sp, #0 - 8005bfa: 6078 str r0, [r7, #4] - 8005bfc: 6039 str r1, [r7, #0] - uint32_t tickstart = 0U; - 8005bfe: 2300 movs r3, #0 - 8005c00: 617b str r3, [r7, #20] - - /* Variables for polling in case of scan mode enabled and polling for each */ - /* conversion. */ - __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; - 8005c02: 2300 movs r3, #0 - 8005c04: 60fb str r3, [r7, #12] - uint32_t Conversion_Timeout_CPU_cycles_max = 0U; - 8005c06: 2300 movs r3, #0 - 8005c08: 613b str r3, [r7, #16] - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - 8005c0a: f7ff fe13 bl 8005834 - 8005c0e: 6178 str r0, [r7, #20] - - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode */ - if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) - 8005c10: 687b ldr r3, [r7, #4] - 8005c12: 681b ldr r3, [r3, #0] - 8005c14: 689b ldr r3, [r3, #8] - 8005c16: f403 7380 and.w r3, r3, #256 @ 0x100 - 8005c1a: 2b00 cmp r3, #0 - 8005c1c: d00b beq.n 8005c36 - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8005c1e: 687b ldr r3, [r7, #4] - 8005c20: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005c22: f043 0220 orr.w r2, r3, #32 - 8005c26: 687b ldr r3, [r7, #4] - 8005c28: 629a str r2, [r3, #40] @ 0x28 - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005c2a: 687b ldr r3, [r7, #4] - 8005c2c: 2200 movs r2, #0 - 8005c2e: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8005c32: 2301 movs r3, #1 - 8005c34: e0d3 b.n 8005dde - /* from ADC conversion time (selected sampling time + conversion time of */ - /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ - /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ - /* As flag EOC is not set after each conversion, no timeout status can */ - /* be set. */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && - 8005c36: 687b ldr r3, [r7, #4] - 8005c38: 681b ldr r3, [r3, #0] - 8005c3a: 685b ldr r3, [r3, #4] - 8005c3c: f403 7380 and.w r3, r3, #256 @ 0x100 - 8005c40: 2b00 cmp r3, #0 - 8005c42: d131 bne.n 8005ca8 - HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) - 8005c44: 687b ldr r3, [r7, #4] - 8005c46: 681b ldr r3, [r3, #0] - 8005c48: 6adb ldr r3, [r3, #44] @ 0x2c - 8005c4a: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && - 8005c4e: 2b00 cmp r3, #0 - 8005c50: d12a bne.n 8005ca8 - { - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - 8005c52: e021 b.n 8005c98 - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - 8005c54: 683b ldr r3, [r7, #0] - 8005c56: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8005c5a: d01d beq.n 8005c98 - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) - 8005c5c: 683b ldr r3, [r7, #0] - 8005c5e: 2b00 cmp r3, #0 - 8005c60: d007 beq.n 8005c72 - 8005c62: f7ff fde7 bl 8005834 - 8005c66: 4602 mov r2, r0 - 8005c68: 697b ldr r3, [r7, #20] - 8005c6a: 1ad3 subs r3, r2, r3 - 8005c6c: 683a ldr r2, [r7, #0] - 8005c6e: 429a cmp r2, r3 - 8005c70: d212 bcs.n 8005c98 - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - 8005c72: 687b ldr r3, [r7, #4] - 8005c74: 681b ldr r3, [r3, #0] - 8005c76: 681b ldr r3, [r3, #0] - 8005c78: f003 0302 and.w r3, r3, #2 - 8005c7c: 2b00 cmp r3, #0 - 8005c7e: d10b bne.n 8005c98 - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - 8005c80: 687b ldr r3, [r7, #4] - 8005c82: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005c84: f043 0204 orr.w r2, r3, #4 - 8005c88: 687b ldr r3, [r7, #4] - 8005c8a: 629a str r2, [r3, #40] @ 0x28 - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005c8c: 687b ldr r3, [r7, #4] - 8005c8e: 2200 movs r2, #0 - 8005c90: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_TIMEOUT; - 8005c94: 2303 movs r3, #3 - 8005c96: e0a2 b.n 8005dde - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - 8005c98: 687b ldr r3, [r7, #4] - 8005c9a: 681b ldr r3, [r3, #0] - 8005c9c: 681b ldr r3, [r3, #0] - 8005c9e: f003 0302 and.w r3, r3, #2 - 8005ca2: 2b00 cmp r3, #0 - 8005ca4: d0d6 beq.n 8005c54 - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && - 8005ca6: e070 b.n 8005d8a - /* Replace polling by wait for maximum conversion time */ - /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ - /* and ADC maximum conversion cycles on all channels. */ - /* - Wait for the expected ADC clock cycles delay */ - Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock - / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) - 8005ca8: 4b4f ldr r3, [pc, #316] @ (8005de8 ) - 8005caa: 681c ldr r4, [r3, #0] - 8005cac: 2002 movs r0, #2 - 8005cae: f002 fc0f bl 80084d0 - 8005cb2: 4603 mov r3, r0 - 8005cb4: fbb4 f2f3 udiv r2, r4, r3 - * ADC_CONVCYCLES_MAX_RANGE(hadc) ); - 8005cb8: 687b ldr r3, [r7, #4] - 8005cba: 681b ldr r3, [r3, #0] - 8005cbc: 6919 ldr r1, [r3, #16] - 8005cbe: 4b4b ldr r3, [pc, #300] @ (8005dec ) - 8005cc0: 400b ands r3, r1 - 8005cc2: 2b00 cmp r3, #0 - 8005cc4: d118 bne.n 8005cf8 - 8005cc6: 687b ldr r3, [r7, #4] - 8005cc8: 681b ldr r3, [r3, #0] - 8005cca: 68d9 ldr r1, [r3, #12] - 8005ccc: 4b48 ldr r3, [pc, #288] @ (8005df0 ) - 8005cce: 400b ands r3, r1 - 8005cd0: 2b00 cmp r3, #0 - 8005cd2: d111 bne.n 8005cf8 - 8005cd4: 687b ldr r3, [r7, #4] - 8005cd6: 681b ldr r3, [r3, #0] - 8005cd8: 6919 ldr r1, [r3, #16] - 8005cda: 4b46 ldr r3, [pc, #280] @ (8005df4 ) - 8005cdc: 400b ands r3, r1 - 8005cde: 2b00 cmp r3, #0 - 8005ce0: d108 bne.n 8005cf4 - 8005ce2: 687b ldr r3, [r7, #4] - 8005ce4: 681b ldr r3, [r3, #0] - 8005ce6: 68d9 ldr r1, [r3, #12] - 8005ce8: 4b43 ldr r3, [pc, #268] @ (8005df8 ) - 8005cea: 400b ands r3, r1 - 8005cec: 2b00 cmp r3, #0 - 8005cee: d101 bne.n 8005cf4 - 8005cf0: 2314 movs r3, #20 - 8005cf2: e020 b.n 8005d36 - 8005cf4: 2329 movs r3, #41 @ 0x29 - 8005cf6: e01e b.n 8005d36 - 8005cf8: 687b ldr r3, [r7, #4] - 8005cfa: 681b ldr r3, [r3, #0] - 8005cfc: 6919 ldr r1, [r3, #16] - 8005cfe: 4b3d ldr r3, [pc, #244] @ (8005df4 ) - 8005d00: 400b ands r3, r1 - 8005d02: 2b00 cmp r3, #0 - 8005d04: d106 bne.n 8005d14 - 8005d06: 687b ldr r3, [r7, #4] - 8005d08: 681b ldr r3, [r3, #0] - 8005d0a: 68d9 ldr r1, [r3, #12] - 8005d0c: 4b3a ldr r3, [pc, #232] @ (8005df8 ) - 8005d0e: 400b ands r3, r1 - 8005d10: 2b00 cmp r3, #0 - 8005d12: d00d beq.n 8005d30 - 8005d14: 687b ldr r3, [r7, #4] - 8005d16: 681b ldr r3, [r3, #0] - 8005d18: 6919 ldr r1, [r3, #16] - 8005d1a: 4b38 ldr r3, [pc, #224] @ (8005dfc ) - 8005d1c: 400b ands r3, r1 - 8005d1e: 2b00 cmp r3, #0 - 8005d20: d108 bne.n 8005d34 - 8005d22: 687b ldr r3, [r7, #4] - 8005d24: 681b ldr r3, [r3, #0] - 8005d26: 68d9 ldr r1, [r3, #12] - 8005d28: 4b34 ldr r3, [pc, #208] @ (8005dfc ) - 8005d2a: 400b ands r3, r1 - 8005d2c: 2b00 cmp r3, #0 - 8005d2e: d101 bne.n 8005d34 - 8005d30: 2354 movs r3, #84 @ 0x54 - 8005d32: e000 b.n 8005d36 - 8005d34: 23fc movs r3, #252 @ 0xfc - Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock - 8005d36: fb02 f303 mul.w r3, r2, r3 - 8005d3a: 613b str r3, [r7, #16] - - while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - 8005d3c: e021 b.n 8005d82 - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - 8005d3e: 683b ldr r3, [r7, #0] - 8005d40: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8005d44: d01a beq.n 8005d7c - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - 8005d46: 683b ldr r3, [r7, #0] - 8005d48: 2b00 cmp r3, #0 - 8005d4a: d007 beq.n 8005d5c - 8005d4c: f7ff fd72 bl 8005834 - 8005d50: 4602 mov r2, r0 - 8005d52: 697b ldr r3, [r7, #20] - 8005d54: 1ad3 subs r3, r2, r3 - 8005d56: 683a ldr r2, [r7, #0] - 8005d58: 429a cmp r2, r3 - 8005d5a: d20f bcs.n 8005d7c - { - /* New check to avoid false timeout detection in case of preemption */ - if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - 8005d5c: 68fb ldr r3, [r7, #12] - 8005d5e: 693a ldr r2, [r7, #16] - 8005d60: 429a cmp r2, r3 - 8005d62: d90b bls.n 8005d7c - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - 8005d64: 687b ldr r3, [r7, #4] - 8005d66: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005d68: f043 0204 orr.w r2, r3, #4 - 8005d6c: 687b ldr r3, [r7, #4] - 8005d6e: 629a str r2, [r3, #40] @ 0x28 - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005d70: 687b ldr r3, [r7, #4] - 8005d72: 2200 movs r2, #0 - 8005d74: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_TIMEOUT; - 8005d78: 2303 movs r3, #3 - 8005d7a: e030 b.n 8005dde - } - } - } - Conversion_Timeout_CPU_cycles ++; - 8005d7c: 68fb ldr r3, [r7, #12] - 8005d7e: 3301 adds r3, #1 - 8005d80: 60fb str r3, [r7, #12] - while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - 8005d82: 68fb ldr r3, [r7, #12] - 8005d84: 693a ldr r2, [r7, #16] - 8005d86: 429a cmp r2, r3 - 8005d88: d8d9 bhi.n 8005d3e - } - } - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - 8005d8a: 687b ldr r3, [r7, #4] - 8005d8c: 681b ldr r3, [r3, #0] - 8005d8e: f06f 0212 mvn.w r2, #18 - 8005d92: 601a str r2, [r3, #0] - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 8005d94: 687b ldr r3, [r7, #4] - 8005d96: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005d98: f443 7200 orr.w r2, r3, #512 @ 0x200 - 8005d9c: 687b ldr r3, [r7, #4] - 8005d9e: 629a str r2, [r3, #40] @ 0x28 - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ - /* (several ranks selected), end of conversion flag is raised */ - /* at the end of the sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8005da0: 687b ldr r3, [r7, #4] - 8005da2: 681b ldr r3, [r3, #0] - 8005da4: 689b ldr r3, [r3, #8] - 8005da6: f403 2360 and.w r3, r3, #917504 @ 0xe0000 - 8005daa: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 - 8005dae: d115 bne.n 8005ddc - (hadc->Init.ContinuousConvMode == DISABLE) ) - 8005db0: 687b ldr r3, [r7, #4] - 8005db2: 7b1b ldrb r3, [r3, #12] - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - 8005db4: 2b00 cmp r3, #0 - 8005db6: d111 bne.n 8005ddc - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 8005db8: 687b ldr r3, [r7, #4] - 8005dba: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005dbc: f423 7280 bic.w r2, r3, #256 @ 0x100 - 8005dc0: 687b ldr r3, [r7, #4] - 8005dc2: 629a str r2, [r3, #40] @ 0x28 - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 8005dc4: 687b ldr r3, [r7, #4] - 8005dc6: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005dc8: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8005dcc: 2b00 cmp r3, #0 - 8005dce: d105 bne.n 8005ddc - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8005dd0: 687b ldr r3, [r7, #4] - 8005dd2: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005dd4: f043 0201 orr.w r2, r3, #1 - 8005dd8: 687b ldr r3, [r7, #4] - 8005dda: 629a str r2, [r3, #40] @ 0x28 - } - } - - /* Return ADC state */ - return HAL_OK; - 8005ddc: 2300 movs r3, #0 -} - 8005dde: 4618 mov r0, r3 - 8005de0: 371c adds r7, #28 - 8005de2: 46bd mov sp, r7 - 8005de4: bd90 pop {r4, r7, pc} - 8005de6: bf00 nop - 8005de8: 20000008 .word 0x20000008 - 8005dec: 24924924 .word 0x24924924 - 8005df0: 00924924 .word 0x00924924 - 8005df4: 12492492 .word 0x12492492 - 8005df8: 00492492 .word 0x00492492 - 8005dfc: 00249249 .word 0x00249249 - -08005e00 : - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle - * @retval ADC group regular conversion data - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - 8005e00: b480 push {r7} - 8005e02: b083 sub sp, #12 - 8005e04: af00 add r7, sp, #0 - 8005e06: 6078 str r0, [r7, #4] - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; - 8005e08: 687b ldr r3, [r7, #4] - 8005e0a: 681b ldr r3, [r3, #0] - 8005e0c: 6cdb ldr r3, [r3, #76] @ 0x4c -} - 8005e0e: 4618 mov r0, r3 - 8005e10: 370c adds r7, #12 - 8005e12: 46bd mov sp, r7 - 8005e14: bc80 pop {r7} - 8005e16: 4770 bx lr - -08005e18 : - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel for regular group. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - 8005e18: b480 push {r7} - 8005e1a: b085 sub sp, #20 - 8005e1c: af00 add r7, sp, #0 - 8005e1e: 6078 str r0, [r7, #4] - 8005e20: 6039 str r1, [r7, #0] - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8005e22: 2300 movs r3, #0 - 8005e24: 73fb strb r3, [r7, #15] - __IO uint32_t wait_loop_index = 0U; - 8005e26: 2300 movs r3, #0 - 8005e28: 60bb str r3, [r7, #8] - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - - /* Process locked */ - __HAL_LOCK(hadc); - 8005e2a: 687b ldr r3, [r7, #4] - 8005e2c: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 8005e30: 2b01 cmp r3, #1 - 8005e32: d101 bne.n 8005e38 - 8005e34: 2302 movs r3, #2 - 8005e36: e0dc b.n 8005ff2 - 8005e38: 687b ldr r3, [r7, #4] - 8005e3a: 2201 movs r2, #1 - 8005e3c: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - - /* Regular sequence configuration */ - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7U) - 8005e40: 683b ldr r3, [r7, #0] - 8005e42: 685b ldr r3, [r3, #4] - 8005e44: 2b06 cmp r3, #6 - 8005e46: d81c bhi.n 8005e82 - { - MODIFY_REG(hadc->Instance->SQR3 , - 8005e48: 687b ldr r3, [r7, #4] - 8005e4a: 681b ldr r3, [r3, #0] - 8005e4c: 6b59 ldr r1, [r3, #52] @ 0x34 - 8005e4e: 683b ldr r3, [r7, #0] - 8005e50: 685a ldr r2, [r3, #4] - 8005e52: 4613 mov r3, r2 - 8005e54: 009b lsls r3, r3, #2 - 8005e56: 4413 add r3, r2 - 8005e58: 3b05 subs r3, #5 - 8005e5a: 221f movs r2, #31 - 8005e5c: fa02 f303 lsl.w r3, r2, r3 - 8005e60: 43db mvns r3, r3 - 8005e62: 4019 ands r1, r3 - 8005e64: 683b ldr r3, [r7, #0] - 8005e66: 6818 ldr r0, [r3, #0] - 8005e68: 683b ldr r3, [r7, #0] - 8005e6a: 685a ldr r2, [r3, #4] - 8005e6c: 4613 mov r3, r2 - 8005e6e: 009b lsls r3, r3, #2 - 8005e70: 4413 add r3, r2 - 8005e72: 3b05 subs r3, #5 - 8005e74: fa00 f203 lsl.w r2, r0, r3 - 8005e78: 687b ldr r3, [r7, #4] - 8005e7a: 681b ldr r3, [r3, #0] - 8005e7c: 430a orrs r2, r1 - 8005e7e: 635a str r2, [r3, #52] @ 0x34 - 8005e80: e03c b.n 8005efc - ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , - ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13U) - 8005e82: 683b ldr r3, [r7, #0] - 8005e84: 685b ldr r3, [r3, #4] - 8005e86: 2b0c cmp r3, #12 - 8005e88: d81c bhi.n 8005ec4 - { - MODIFY_REG(hadc->Instance->SQR2 , - 8005e8a: 687b ldr r3, [r7, #4] - 8005e8c: 681b ldr r3, [r3, #0] - 8005e8e: 6b19 ldr r1, [r3, #48] @ 0x30 - 8005e90: 683b ldr r3, [r7, #0] - 8005e92: 685a ldr r2, [r3, #4] - 8005e94: 4613 mov r3, r2 - 8005e96: 009b lsls r3, r3, #2 - 8005e98: 4413 add r3, r2 - 8005e9a: 3b23 subs r3, #35 @ 0x23 - 8005e9c: 221f movs r2, #31 - 8005e9e: fa02 f303 lsl.w r3, r2, r3 - 8005ea2: 43db mvns r3, r3 - 8005ea4: 4019 ands r1, r3 - 8005ea6: 683b ldr r3, [r7, #0] - 8005ea8: 6818 ldr r0, [r3, #0] - 8005eaa: 683b ldr r3, [r7, #0] - 8005eac: 685a ldr r2, [r3, #4] - 8005eae: 4613 mov r3, r2 - 8005eb0: 009b lsls r3, r3, #2 - 8005eb2: 4413 add r3, r2 - 8005eb4: 3b23 subs r3, #35 @ 0x23 - 8005eb6: fa00 f203 lsl.w r2, r0, r3 - 8005eba: 687b ldr r3, [r7, #4] - 8005ebc: 681b ldr r3, [r3, #0] - 8005ebe: 430a orrs r2, r1 - 8005ec0: 631a str r2, [r3, #48] @ 0x30 - 8005ec2: e01b b.n 8005efc - ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 13 to 16 */ - else - { - MODIFY_REG(hadc->Instance->SQR1 , - 8005ec4: 687b ldr r3, [r7, #4] - 8005ec6: 681b ldr r3, [r3, #0] - 8005ec8: 6ad9 ldr r1, [r3, #44] @ 0x2c - 8005eca: 683b ldr r3, [r7, #0] - 8005ecc: 685a ldr r2, [r3, #4] - 8005ece: 4613 mov r3, r2 - 8005ed0: 009b lsls r3, r3, #2 - 8005ed2: 4413 add r3, r2 - 8005ed4: 3b41 subs r3, #65 @ 0x41 - 8005ed6: 221f movs r2, #31 - 8005ed8: fa02 f303 lsl.w r3, r2, r3 - 8005edc: 43db mvns r3, r3 - 8005ede: 4019 ands r1, r3 - 8005ee0: 683b ldr r3, [r7, #0] - 8005ee2: 6818 ldr r0, [r3, #0] - 8005ee4: 683b ldr r3, [r7, #0] - 8005ee6: 685a ldr r2, [r3, #4] - 8005ee8: 4613 mov r3, r2 - 8005eea: 009b lsls r3, r3, #2 - 8005eec: 4413 add r3, r2 - 8005eee: 3b41 subs r3, #65 @ 0x41 - 8005ef0: fa00 f203 lsl.w r2, r0, r3 - 8005ef4: 687b ldr r3, [r7, #4] - 8005ef6: 681b ldr r3, [r3, #0] - 8005ef8: 430a orrs r2, r1 - 8005efa: 62da str r2, [r3, #44] @ 0x2c - } - - - /* Channel sampling time configuration */ - /* For channels 10 to 17 */ - if (sConfig->Channel >= ADC_CHANNEL_10) - 8005efc: 683b ldr r3, [r7, #0] - 8005efe: 681b ldr r3, [r3, #0] - 8005f00: 2b09 cmp r3, #9 - 8005f02: d91c bls.n 8005f3e - { - MODIFY_REG(hadc->Instance->SMPR1 , - 8005f04: 687b ldr r3, [r7, #4] - 8005f06: 681b ldr r3, [r3, #0] - 8005f08: 68d9 ldr r1, [r3, #12] - 8005f0a: 683b ldr r3, [r7, #0] - 8005f0c: 681a ldr r2, [r3, #0] - 8005f0e: 4613 mov r3, r2 - 8005f10: 005b lsls r3, r3, #1 - 8005f12: 4413 add r3, r2 - 8005f14: 3b1e subs r3, #30 - 8005f16: 2207 movs r2, #7 - 8005f18: fa02 f303 lsl.w r3, r2, r3 - 8005f1c: 43db mvns r3, r3 - 8005f1e: 4019 ands r1, r3 - 8005f20: 683b ldr r3, [r7, #0] - 8005f22: 6898 ldr r0, [r3, #8] - 8005f24: 683b ldr r3, [r7, #0] - 8005f26: 681a ldr r2, [r3, #0] - 8005f28: 4613 mov r3, r2 - 8005f2a: 005b lsls r3, r3, #1 - 8005f2c: 4413 add r3, r2 - 8005f2e: 3b1e subs r3, #30 - 8005f30: fa00 f203 lsl.w r2, r0, r3 - 8005f34: 687b ldr r3, [r7, #4] - 8005f36: 681b ldr r3, [r3, #0] - 8005f38: 430a orrs r2, r1 - 8005f3a: 60da str r2, [r3, #12] - 8005f3c: e019 b.n 8005f72 - ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , - ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); - } - else /* For channels 0 to 9 */ - { - MODIFY_REG(hadc->Instance->SMPR2 , - 8005f3e: 687b ldr r3, [r7, #4] - 8005f40: 681b ldr r3, [r3, #0] - 8005f42: 6919 ldr r1, [r3, #16] - 8005f44: 683b ldr r3, [r7, #0] - 8005f46: 681a ldr r2, [r3, #0] - 8005f48: 4613 mov r3, r2 - 8005f4a: 005b lsls r3, r3, #1 - 8005f4c: 4413 add r3, r2 - 8005f4e: 2207 movs r2, #7 - 8005f50: fa02 f303 lsl.w r3, r2, r3 - 8005f54: 43db mvns r3, r3 - 8005f56: 4019 ands r1, r3 - 8005f58: 683b ldr r3, [r7, #0] - 8005f5a: 6898 ldr r0, [r3, #8] - 8005f5c: 683b ldr r3, [r7, #0] - 8005f5e: 681a ldr r2, [r3, #0] - 8005f60: 4613 mov r3, r2 - 8005f62: 005b lsls r3, r3, #1 - 8005f64: 4413 add r3, r2 - 8005f66: fa00 f203 lsl.w r2, r0, r3 - 8005f6a: 687b ldr r3, [r7, #4] - 8005f6c: 681b ldr r3, [r3, #0] - 8005f6e: 430a orrs r2, r1 - 8005f70: 611a str r2, [r3, #16] - ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); - } - - /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || - 8005f72: 683b ldr r3, [r7, #0] - 8005f74: 681b ldr r3, [r3, #0] - 8005f76: 2b10 cmp r3, #16 - 8005f78: d003 beq.n 8005f82 - (sConfig->Channel == ADC_CHANNEL_VREFINT) ) - 8005f7a: 683b ldr r3, [r7, #0] - 8005f7c: 681b ldr r3, [r3, #0] - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || - 8005f7e: 2b11 cmp r3, #17 - 8005f80: d132 bne.n 8005fe8 - { - /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ - /* measurement channels (VrefInt/TempSensor). If these channels are */ - /* intended to be set on other ADC instances, an error is reported. */ - if (hadc->Instance == ADC1) - 8005f82: 687b ldr r3, [r7, #4] - 8005f84: 681b ldr r3, [r3, #0] - 8005f86: 4a1d ldr r2, [pc, #116] @ (8005ffc ) - 8005f88: 4293 cmp r3, r2 - 8005f8a: d125 bne.n 8005fd8 - { - if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) - 8005f8c: 687b ldr r3, [r7, #4] - 8005f8e: 681b ldr r3, [r3, #0] - 8005f90: 689b ldr r3, [r3, #8] - 8005f92: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8005f96: 2b00 cmp r3, #0 - 8005f98: d126 bne.n 8005fe8 - { - SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); - 8005f9a: 687b ldr r3, [r7, #4] - 8005f9c: 681b ldr r3, [r3, #0] - 8005f9e: 689a ldr r2, [r3, #8] - 8005fa0: 687b ldr r3, [r7, #4] - 8005fa2: 681b ldr r3, [r3, #0] - 8005fa4: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 - 8005fa8: 609a str r2, [r3, #8] - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - 8005faa: 683b ldr r3, [r7, #0] - 8005fac: 681b ldr r3, [r3, #0] - 8005fae: 2b10 cmp r3, #16 - 8005fb0: d11a bne.n 8005fe8 - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - 8005fb2: 4b13 ldr r3, [pc, #76] @ (8006000 ) - 8005fb4: 681b ldr r3, [r3, #0] - 8005fb6: 4a13 ldr r2, [pc, #76] @ (8006004 ) - 8005fb8: fba2 2303 umull r2, r3, r2, r3 - 8005fbc: 0c9a lsrs r2, r3, #18 - 8005fbe: 4613 mov r3, r2 - 8005fc0: 009b lsls r3, r3, #2 - 8005fc2: 4413 add r3, r2 - 8005fc4: 005b lsls r3, r3, #1 - 8005fc6: 60bb str r3, [r7, #8] - while(wait_loop_index != 0U) - 8005fc8: e002 b.n 8005fd0 - { - wait_loop_index--; - 8005fca: 68bb ldr r3, [r7, #8] - 8005fcc: 3b01 subs r3, #1 - 8005fce: 60bb str r3, [r7, #8] - while(wait_loop_index != 0U) - 8005fd0: 68bb ldr r3, [r7, #8] - 8005fd2: 2b00 cmp r3, #0 - 8005fd4: d1f9 bne.n 8005fca - 8005fd6: e007 b.n 8005fe8 - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8005fd8: 687b ldr r3, [r7, #4] - 8005fda: 6a9b ldr r3, [r3, #40] @ 0x28 - 8005fdc: f043 0220 orr.w r2, r3, #32 - 8005fe0: 687b ldr r3, [r7, #4] - 8005fe2: 629a str r2, [r3, #40] @ 0x28 - - tmp_hal_status = HAL_ERROR; - 8005fe4: 2301 movs r3, #1 - 8005fe6: 73fb strb r3, [r7, #15] - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8005fe8: 687b ldr r3, [r7, #4] - 8005fea: 2200 movs r2, #0 - 8005fec: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Return function status */ - return tmp_hal_status; - 8005ff0: 7bfb ldrb r3, [r7, #15] -} - 8005ff2: 4618 mov r0, r3 - 8005ff4: 3714 adds r7, #20 - 8005ff6: 46bd mov sp, r7 - 8005ff8: bc80 pop {r7} - 8005ffa: 4770 bx lr - 8005ffc: 40012400 .word 0x40012400 - 8006000: 20000008 .word 0x20000008 - 8006004: 431bde83 .word 0x431bde83 - -08006008 : - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) -{ - 8006008: b580 push {r7, lr} - 800600a: b084 sub sp, #16 - 800600c: af00 add r7, sp, #0 - 800600e: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 8006010: 2300 movs r3, #0 - 8006012: 60fb str r3, [r7, #12] - __IO uint32_t wait_loop_index = 0U; - 8006014: 2300 movs r3, #0 - 8006016: 60bb str r3, [r7, #8] - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (ADC_IS_ENABLE(hadc) == RESET) - 8006018: 687b ldr r3, [r7, #4] - 800601a: 681b ldr r3, [r3, #0] - 800601c: 689b ldr r3, [r3, #8] - 800601e: f003 0301 and.w r3, r3, #1 - 8006022: 2b01 cmp r3, #1 - 8006024: d040 beq.n 80060a8 - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - 8006026: 687b ldr r3, [r7, #4] - 8006028: 681b ldr r3, [r3, #0] - 800602a: 689a ldr r2, [r3, #8] - 800602c: 687b ldr r3, [r7, #4] - 800602e: 681b ldr r3, [r3, #0] - 8006030: f042 0201 orr.w r2, r2, #1 - 8006034: 609a str r2, [r3, #8] - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - 8006036: 4b1f ldr r3, [pc, #124] @ (80060b4 ) - 8006038: 681b ldr r3, [r3, #0] - 800603a: 4a1f ldr r2, [pc, #124] @ (80060b8 ) - 800603c: fba2 2303 umull r2, r3, r2, r3 - 8006040: 0c9b lsrs r3, r3, #18 - 8006042: 60bb str r3, [r7, #8] - while(wait_loop_index != 0U) - 8006044: e002 b.n 800604c - { - wait_loop_index--; - 8006046: 68bb ldr r3, [r7, #8] - 8006048: 3b01 subs r3, #1 - 800604a: 60bb str r3, [r7, #8] - while(wait_loop_index != 0U) - 800604c: 68bb ldr r3, [r7, #8] - 800604e: 2b00 cmp r3, #0 - 8006050: d1f9 bne.n 8006046 - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - 8006052: f7ff fbef bl 8005834 - 8006056: 60f8 str r0, [r7, #12] - - /* Wait for ADC effectively enabled */ - while(ADC_IS_ENABLE(hadc) == RESET) - 8006058: e01f b.n 800609a - { - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - 800605a: f7ff fbeb bl 8005834 - 800605e: 4602 mov r2, r0 - 8006060: 68fb ldr r3, [r7, #12] - 8006062: 1ad3 subs r3, r2, r3 - 8006064: 2b02 cmp r3, #2 - 8006066: d918 bls.n 800609a - { - /* New check to avoid false timeout detection in case of preemption */ - if(ADC_IS_ENABLE(hadc) == RESET) - 8006068: 687b ldr r3, [r7, #4] - 800606a: 681b ldr r3, [r3, #0] - 800606c: 689b ldr r3, [r3, #8] - 800606e: f003 0301 and.w r3, r3, #1 - 8006072: 2b01 cmp r3, #1 - 8006074: d011 beq.n 800609a - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8006076: 687b ldr r3, [r7, #4] - 8006078: 6a9b ldr r3, [r3, #40] @ 0x28 - 800607a: f043 0210 orr.w r2, r3, #16 - 800607e: 687b ldr r3, [r7, #4] - 8006080: 629a str r2, [r3, #40] @ 0x28 - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8006082: 687b ldr r3, [r7, #4] - 8006084: 6adb ldr r3, [r3, #44] @ 0x2c - 8006086: f043 0201 orr.w r2, r3, #1 - 800608a: 687b ldr r3, [r7, #4] - 800608c: 62da str r2, [r3, #44] @ 0x2c - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 800608e: 687b ldr r3, [r7, #4] - 8006090: 2200 movs r2, #0 - 8006092: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006096: 2301 movs r3, #1 - 8006098: e007 b.n 80060aa - while(ADC_IS_ENABLE(hadc) == RESET) - 800609a: 687b ldr r3, [r7, #4] - 800609c: 681b ldr r3, [r3, #0] - 800609e: 689b ldr r3, [r3, #8] - 80060a0: f003 0301 and.w r3, r3, #1 - 80060a4: 2b01 cmp r3, #1 - 80060a6: d1d8 bne.n 800605a - } - } - } - - /* Return HAL status */ - return HAL_OK; - 80060a8: 2300 movs r3, #0 -} - 80060aa: 4618 mov r0, r3 - 80060ac: 3710 adds r7, #16 - 80060ae: 46bd mov sp, r7 - 80060b0: bd80 pop {r7, pc} - 80060b2: bf00 nop - 80060b4: 20000008 .word 0x20000008 - 80060b8: 431bde83 .word 0x431bde83 - -080060bc : - * stopped to disable the ADC. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) -{ - 80060bc: b580 push {r7, lr} - 80060be: b084 sub sp, #16 - 80060c0: af00 add r7, sp, #0 - 80060c2: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 80060c4: 2300 movs r3, #0 - 80060c6: 60fb str r3, [r7, #12] - - /* Verification if ADC is not already disabled */ - if (ADC_IS_ENABLE(hadc) != RESET) - 80060c8: 687b ldr r3, [r7, #4] - 80060ca: 681b ldr r3, [r3, #0] - 80060cc: 689b ldr r3, [r3, #8] - 80060ce: f003 0301 and.w r3, r3, #1 - 80060d2: 2b01 cmp r3, #1 - 80060d4: d12e bne.n 8006134 - { - /* Disable the ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - 80060d6: 687b ldr r3, [r7, #4] - 80060d8: 681b ldr r3, [r3, #0] - 80060da: 689a ldr r2, [r3, #8] - 80060dc: 687b ldr r3, [r7, #4] - 80060de: 681b ldr r3, [r3, #0] - 80060e0: f022 0201 bic.w r2, r2, #1 - 80060e4: 609a str r2, [r3, #8] - - /* Get tick count */ - tickstart = HAL_GetTick(); - 80060e6: f7ff fba5 bl 8005834 - 80060ea: 60f8 str r0, [r7, #12] - - /* Wait for ADC effectively disabled */ - while(ADC_IS_ENABLE(hadc) != RESET) - 80060ec: e01b b.n 8006126 - { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - 80060ee: f7ff fba1 bl 8005834 - 80060f2: 4602 mov r2, r0 - 80060f4: 68fb ldr r3, [r7, #12] - 80060f6: 1ad3 subs r3, r2, r3 - 80060f8: 2b02 cmp r3, #2 - 80060fa: d914 bls.n 8006126 - { - /* New check to avoid false timeout detection in case of preemption */ - if(ADC_IS_ENABLE(hadc) != RESET) - 80060fc: 687b ldr r3, [r7, #4] - 80060fe: 681b ldr r3, [r3, #0] - 8006100: 689b ldr r3, [r3, #8] - 8006102: f003 0301 and.w r3, r3, #1 - 8006106: 2b01 cmp r3, #1 - 8006108: d10d bne.n 8006126 - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800610a: 687b ldr r3, [r7, #4] - 800610c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800610e: f043 0210 orr.w r2, r3, #16 - 8006112: 687b ldr r3, [r7, #4] - 8006114: 629a str r2, [r3, #40] @ 0x28 - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8006116: 687b ldr r3, [r7, #4] - 8006118: 6adb ldr r3, [r3, #44] @ 0x2c - 800611a: f043 0201 orr.w r2, r3, #1 - 800611e: 687b ldr r3, [r7, #4] - 8006120: 62da str r2, [r3, #44] @ 0x2c - - return HAL_ERROR; - 8006122: 2301 movs r3, #1 - 8006124: e007 b.n 8006136 - while(ADC_IS_ENABLE(hadc) != RESET) - 8006126: 687b ldr r3, [r7, #4] - 8006128: 681b ldr r3, [r3, #0] - 800612a: 689b ldr r3, [r3, #8] - 800612c: f003 0301 and.w r3, r3, #1 - 8006130: 2b01 cmp r3, #1 - 8006132: d0dc beq.n 80060ee - } - } - } - - /* Return HAL status */ - return HAL_OK; - 8006134: 2300 movs r3, #0 -} - 8006136: 4618 mov r0, r3 - 8006138: 3710 adds r7, #16 - 800613a: 46bd mov sp, r7 - 800613c: bd80 pop {r7, pc} - ... - -08006140 : - * the completion of this function. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) -{ - 8006140: b590 push {r4, r7, lr} - 8006142: b087 sub sp, #28 - 8006144: af00 add r7, sp, #0 - 8006146: 6078 str r0, [r7, #4] - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8006148: 2300 movs r3, #0 - 800614a: 75fb strb r3, [r7, #23] - uint32_t tickstart; - __IO uint32_t wait_loop_index = 0U; - 800614c: 2300 movs r3, #0 - 800614e: 60fb str r3, [r7, #12] - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - 8006150: 687b ldr r3, [r7, #4] - 8006152: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 8006156: 2b01 cmp r3, #1 - 8006158: d101 bne.n 800615e - 800615a: 2302 movs r3, #2 - 800615c: e095 b.n 800628a - 800615e: 687b ldr r3, [r7, #4] - 8006160: 2201 movs r2, #1 - 8006162: f883 2024 strb.w r2, [r3, #36] @ 0x24 - /* 1. Calibration prerequisite: */ - /* - ADC must be disabled for at least two ADC clock cycles in disable */ - /* mode before ADC enable */ - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - 8006166: 6878 ldr r0, [r7, #4] - 8006168: f7ff ffa8 bl 80060bc - 800616c: 4603 mov r3, r0 - 800616e: 75fb strb r3, [r7, #23] - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - 8006170: 7dfb ldrb r3, [r7, #23] - 8006172: 2b00 cmp r3, #0 - 8006174: f040 8084 bne.w 8006280 - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - 8006178: 687b ldr r3, [r7, #4] - 800617a: 6a9b ldr r3, [r3, #40] @ 0x28 - 800617c: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 8006180: f023 0302 bic.w r3, r3, #2 - 8006184: f043 0202 orr.w r2, r3, #2 - 8006188: 687b ldr r3, [r7, #4] - 800618a: 629a str r2, [r3, #40] @ 0x28 - - /* Hardware prerequisite: delay before starting the calibration. */ - /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ - /* - Wait for the expected ADC clock cycles delay */ - wait_loop_index = ((SystemCoreClock - / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) - 800618c: 4b41 ldr r3, [pc, #260] @ (8006294 ) - 800618e: 681c ldr r4, [r3, #0] - 8006190: 2002 movs r0, #2 - 8006192: f002 f99d bl 80084d0 - 8006196: 4603 mov r3, r0 - 8006198: fbb4 f3f3 udiv r3, r4, r3 - * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); - 800619c: 005b lsls r3, r3, #1 - wait_loop_index = ((SystemCoreClock - 800619e: 60fb str r3, [r7, #12] - - while(wait_loop_index != 0U) - 80061a0: e002 b.n 80061a8 - { - wait_loop_index--; - 80061a2: 68fb ldr r3, [r7, #12] - 80061a4: 3b01 subs r3, #1 - 80061a6: 60fb str r3, [r7, #12] - while(wait_loop_index != 0U) - 80061a8: 68fb ldr r3, [r7, #12] - 80061aa: 2b00 cmp r3, #0 - 80061ac: d1f9 bne.n 80061a2 - } - - /* 2. Enable the ADC peripheral */ - ADC_Enable(hadc); - 80061ae: 6878 ldr r0, [r7, #4] - 80061b0: f7ff ff2a bl 8006008 - - /* 3. Resets ADC calibration registers */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); - 80061b4: 687b ldr r3, [r7, #4] - 80061b6: 681b ldr r3, [r3, #0] - 80061b8: 689a ldr r2, [r3, #8] - 80061ba: 687b ldr r3, [r7, #4] - 80061bc: 681b ldr r3, [r3, #0] - 80061be: f042 0208 orr.w r2, r2, #8 - 80061c2: 609a str r2, [r3, #8] - - tickstart = HAL_GetTick(); - 80061c4: f7ff fb36 bl 8005834 - 80061c8: 6138 str r0, [r7, #16] - - /* Wait for calibration reset completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) - 80061ca: e01b b.n 8006204 - { - if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) - 80061cc: f7ff fb32 bl 8005834 - 80061d0: 4602 mov r2, r0 - 80061d2: 693b ldr r3, [r7, #16] - 80061d4: 1ad3 subs r3, r2, r3 - 80061d6: 2b0a cmp r3, #10 - 80061d8: d914 bls.n 8006204 - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) - 80061da: 687b ldr r3, [r7, #4] - 80061dc: 681b ldr r3, [r3, #0] - 80061de: 689b ldr r3, [r3, #8] - 80061e0: f003 0308 and.w r3, r3, #8 - 80061e4: 2b00 cmp r3, #0 - 80061e6: d00d beq.n 8006204 - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - 80061e8: 687b ldr r3, [r7, #4] - 80061ea: 6a9b ldr r3, [r3, #40] @ 0x28 - 80061ec: f023 0312 bic.w r3, r3, #18 - 80061f0: f043 0210 orr.w r2, r3, #16 - 80061f4: 687b ldr r3, [r7, #4] - 80061f6: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 80061f8: 687b ldr r3, [r7, #4] - 80061fa: 2200 movs r2, #0 - 80061fc: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006200: 2301 movs r3, #1 - 8006202: e042 b.n 800628a - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) - 8006204: 687b ldr r3, [r7, #4] - 8006206: 681b ldr r3, [r3, #0] - 8006208: 689b ldr r3, [r3, #8] - 800620a: f003 0308 and.w r3, r3, #8 - 800620e: 2b00 cmp r3, #0 - 8006210: d1dc bne.n 80061cc - } - } - } - - /* 4. Start ADC calibration */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); - 8006212: 687b ldr r3, [r7, #4] - 8006214: 681b ldr r3, [r3, #0] - 8006216: 689a ldr r2, [r3, #8] - 8006218: 687b ldr r3, [r7, #4] - 800621a: 681b ldr r3, [r3, #0] - 800621c: f042 0204 orr.w r2, r2, #4 - 8006220: 609a str r2, [r3, #8] - - tickstart = HAL_GetTick(); - 8006222: f7ff fb07 bl 8005834 - 8006226: 6138 str r0, [r7, #16] - - /* Wait for calibration completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) - 8006228: e01b b.n 8006262 - { - if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) - 800622a: f7ff fb03 bl 8005834 - 800622e: 4602 mov r2, r0 - 8006230: 693b ldr r3, [r7, #16] - 8006232: 1ad3 subs r3, r2, r3 - 8006234: 2b0a cmp r3, #10 - 8006236: d914 bls.n 8006262 - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) - 8006238: 687b ldr r3, [r7, #4] - 800623a: 681b ldr r3, [r3, #0] - 800623c: 689b ldr r3, [r3, #8] - 800623e: f003 0304 and.w r3, r3, #4 - 8006242: 2b00 cmp r3, #0 - 8006244: d00d beq.n 8006262 - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - 8006246: 687b ldr r3, [r7, #4] - 8006248: 6a9b ldr r3, [r3, #40] @ 0x28 - 800624a: f023 0312 bic.w r3, r3, #18 - 800624e: f043 0210 orr.w r2, r3, #16 - 8006252: 687b ldr r3, [r7, #4] - 8006254: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8006256: 687b ldr r3, [r7, #4] - 8006258: 2200 movs r2, #0 - 800625a: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 800625e: 2301 movs r3, #1 - 8006260: e013 b.n 800628a - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) - 8006262: 687b ldr r3, [r7, #4] - 8006264: 681b ldr r3, [r3, #0] - 8006266: 689b ldr r3, [r3, #8] - 8006268: f003 0304 and.w r3, r3, #4 - 800626c: 2b00 cmp r3, #0 - 800626e: d1dc bne.n 800622a - } - } - } - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - 8006270: 687b ldr r3, [r7, #4] - 8006272: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006274: f023 0303 bic.w r3, r3, #3 - 8006278: f043 0201 orr.w r2, r3, #1 - 800627c: 687b ldr r3, [r7, #4] - 800627e: 629a str r2, [r3, #40] @ 0x28 - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - 8006280: 687b ldr r3, [r7, #4] - 8006282: 2200 movs r2, #0 - 8006284: f883 2024 strb.w r2, [r3, #36] @ 0x24 - - /* Return function status */ - return tmp_hal_status; - 8006288: 7dfb ldrb r3, [r7, #23] -} - 800628a: 4618 mov r0, r3 - 800628c: 371c adds r7, #28 - 800628e: 46bd mov sp, r7 - 8006290: bd90 pop {r4, r7, pc} - 8006292: bf00 nop - 8006294: 20000008 .word 0x20000008 - -08006298 : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) -{ - 8006298: b580 push {r7, lr} - 800629a: b084 sub sp, #16 - 800629c: af00 add r7, sp, #0 - 800629e: 6078 str r0, [r7, #4] - uint32_t tickstart; - - /* Check CAN handle */ - if (hcan == NULL) - 80062a0: 687b ldr r3, [r7, #4] - 80062a2: 2b00 cmp r3, #0 - 80062a4: d101 bne.n 80062aa - { - return HAL_ERROR; - 80062a6: 2301 movs r3, #1 - 80062a8: e0ed b.n 8006486 - /* Init the low level hardware: CLOCK, NVIC */ - hcan->MspInitCallback(hcan); - } - -#else - if (hcan->State == HAL_CAN_STATE_RESET) - 80062aa: 687b ldr r3, [r7, #4] - 80062ac: f893 3020 ldrb.w r3, [r3, #32] - 80062b0: b2db uxtb r3, r3 - 80062b2: 2b00 cmp r3, #0 - 80062b4: d102 bne.n 80062bc - { - /* Init the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspInit(hcan); - 80062b6: 6878 ldr r0, [r7, #4] - 80062b8: f7fb fb94 bl 80019e4 - } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 80062bc: 687b ldr r3, [r7, #4] - 80062be: 681b ldr r3, [r3, #0] - 80062c0: 681a ldr r2, [r3, #0] - 80062c2: 687b ldr r3, [r7, #4] - 80062c4: 681b ldr r3, [r3, #0] - 80062c6: f042 0201 orr.w r2, r2, #1 - 80062ca: 601a str r2, [r3, #0] - - /* Get tick */ - tickstart = HAL_GetTick(); - 80062cc: f7ff fab2 bl 8005834 - 80062d0: 60f8 str r0, [r7, #12] - - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 80062d2: e012 b.n 80062fa - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 80062d4: f7ff faae bl 8005834 - 80062d8: 4602 mov r2, r0 - 80062da: 68fb ldr r3, [r7, #12] - 80062dc: 1ad3 subs r3, r2, r3 - 80062de: 2b0a cmp r3, #10 - 80062e0: d90b bls.n 80062fa - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 80062e2: 687b ldr r3, [r7, #4] - 80062e4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80062e6: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 80062ea: 687b ldr r3, [r7, #4] - 80062ec: 625a str r2, [r3, #36] @ 0x24 - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - 80062ee: 687b ldr r3, [r7, #4] - 80062f0: 2205 movs r2, #5 - 80062f2: f883 2020 strb.w r2, [r3, #32] - - return HAL_ERROR; - 80062f6: 2301 movs r3, #1 - 80062f8: e0c5 b.n 8006486 - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 80062fa: 687b ldr r3, [r7, #4] - 80062fc: 681b ldr r3, [r3, #0] - 80062fe: 685b ldr r3, [r3, #4] - 8006300: f003 0301 and.w r3, r3, #1 - 8006304: 2b00 cmp r3, #0 - 8006306: d0e5 beq.n 80062d4 - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - 8006308: 687b ldr r3, [r7, #4] - 800630a: 681b ldr r3, [r3, #0] - 800630c: 681a ldr r2, [r3, #0] - 800630e: 687b ldr r3, [r7, #4] - 8006310: 681b ldr r3, [r3, #0] - 8006312: f022 0202 bic.w r2, r2, #2 - 8006316: 601a str r2, [r3, #0] - - /* Get tick */ - tickstart = HAL_GetTick(); - 8006318: f7ff fa8c bl 8005834 - 800631c: 60f8 str r0, [r7, #12] - - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 800631e: e012 b.n 8006346 - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8006320: f7ff fa88 bl 8005834 - 8006324: 4602 mov r2, r0 - 8006326: 68fb ldr r3, [r7, #12] - 8006328: 1ad3 subs r3, r2, r3 - 800632a: 2b0a cmp r3, #10 - 800632c: d90b bls.n 8006346 - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 800632e: 687b ldr r3, [r7, #4] - 8006330: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006332: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 8006336: 687b ldr r3, [r7, #4] - 8006338: 625a str r2, [r3, #36] @ 0x24 - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - 800633a: 687b ldr r3, [r7, #4] - 800633c: 2205 movs r2, #5 - 800633e: f883 2020 strb.w r2, [r3, #32] - - return HAL_ERROR; - 8006342: 2301 movs r3, #1 - 8006344: e09f b.n 8006486 - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - 8006346: 687b ldr r3, [r7, #4] - 8006348: 681b ldr r3, [r3, #0] - 800634a: 685b ldr r3, [r3, #4] - 800634c: f003 0302 and.w r3, r3, #2 - 8006350: 2b00 cmp r3, #0 - 8006352: d1e5 bne.n 8006320 - } - } - - /* Set the time triggered communication mode */ - if (hcan->Init.TimeTriggeredMode == ENABLE) - 8006354: 687b ldr r3, [r7, #4] - 8006356: 7e1b ldrb r3, [r3, #24] - 8006358: 2b01 cmp r3, #1 - 800635a: d108 bne.n 800636e - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 800635c: 687b ldr r3, [r7, #4] - 800635e: 681b ldr r3, [r3, #0] - 8006360: 681a ldr r2, [r3, #0] - 8006362: 687b ldr r3, [r7, #4] - 8006364: 681b ldr r3, [r3, #0] - 8006366: f042 0280 orr.w r2, r2, #128 @ 0x80 - 800636a: 601a str r2, [r3, #0] - 800636c: e007 b.n 800637e - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - 800636e: 687b ldr r3, [r7, #4] - 8006370: 681b ldr r3, [r3, #0] - 8006372: 681a ldr r2, [r3, #0] - 8006374: 687b ldr r3, [r7, #4] - 8006376: 681b ldr r3, [r3, #0] - 8006378: f022 0280 bic.w r2, r2, #128 @ 0x80 - 800637c: 601a str r2, [r3, #0] - } - - /* Set the automatic bus-off management */ - if (hcan->Init.AutoBusOff == ENABLE) - 800637e: 687b ldr r3, [r7, #4] - 8006380: 7e5b ldrb r3, [r3, #25] - 8006382: 2b01 cmp r3, #1 - 8006384: d108 bne.n 8006398 - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 8006386: 687b ldr r3, [r7, #4] - 8006388: 681b ldr r3, [r3, #0] - 800638a: 681a ldr r2, [r3, #0] - 800638c: 687b ldr r3, [r7, #4] - 800638e: 681b ldr r3, [r3, #0] - 8006390: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8006394: 601a str r2, [r3, #0] - 8006396: e007 b.n 80063a8 - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - 8006398: 687b ldr r3, [r7, #4] - 800639a: 681b ldr r3, [r3, #0] - 800639c: 681a ldr r2, [r3, #0] - 800639e: 687b ldr r3, [r7, #4] - 80063a0: 681b ldr r3, [r3, #0] - 80063a2: f022 0240 bic.w r2, r2, #64 @ 0x40 - 80063a6: 601a str r2, [r3, #0] - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AutoWakeUp == ENABLE) - 80063a8: 687b ldr r3, [r7, #4] - 80063aa: 7e9b ldrb r3, [r3, #26] - 80063ac: 2b01 cmp r3, #1 - 80063ae: d108 bne.n 80063c2 - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80063b0: 687b ldr r3, [r7, #4] - 80063b2: 681b ldr r3, [r3, #0] - 80063b4: 681a ldr r2, [r3, #0] - 80063b6: 687b ldr r3, [r7, #4] - 80063b8: 681b ldr r3, [r3, #0] - 80063ba: f042 0220 orr.w r2, r2, #32 - 80063be: 601a str r2, [r3, #0] - 80063c0: e007 b.n 80063d2 - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - 80063c2: 687b ldr r3, [r7, #4] - 80063c4: 681b ldr r3, [r3, #0] - 80063c6: 681a ldr r2, [r3, #0] - 80063c8: 687b ldr r3, [r7, #4] - 80063ca: 681b ldr r3, [r3, #0] - 80063cc: f022 0220 bic.w r2, r2, #32 - 80063d0: 601a str r2, [r3, #0] - } - - /* Set the automatic retransmission */ - if (hcan->Init.AutoRetransmission == ENABLE) - 80063d2: 687b ldr r3, [r7, #4] - 80063d4: 7edb ldrb r3, [r3, #27] - 80063d6: 2b01 cmp r3, #1 - 80063d8: d108 bne.n 80063ec - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 80063da: 687b ldr r3, [r7, #4] - 80063dc: 681b ldr r3, [r3, #0] - 80063de: 681a ldr r2, [r3, #0] - 80063e0: 687b ldr r3, [r7, #4] - 80063e2: 681b ldr r3, [r3, #0] - 80063e4: f022 0210 bic.w r2, r2, #16 - 80063e8: 601a str r2, [r3, #0] - 80063ea: e007 b.n 80063fc - } - else - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - 80063ec: 687b ldr r3, [r7, #4] - 80063ee: 681b ldr r3, [r3, #0] - 80063f0: 681a ldr r2, [r3, #0] - 80063f2: 687b ldr r3, [r7, #4] - 80063f4: 681b ldr r3, [r3, #0] - 80063f6: f042 0210 orr.w r2, r2, #16 - 80063fa: 601a str r2, [r3, #0] - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.ReceiveFifoLocked == ENABLE) - 80063fc: 687b ldr r3, [r7, #4] - 80063fe: 7f1b ldrb r3, [r3, #28] - 8006400: 2b01 cmp r3, #1 - 8006402: d108 bne.n 8006416 - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 8006404: 687b ldr r3, [r7, #4] - 8006406: 681b ldr r3, [r3, #0] - 8006408: 681a ldr r2, [r3, #0] - 800640a: 687b ldr r3, [r7, #4] - 800640c: 681b ldr r3, [r3, #0] - 800640e: f042 0208 orr.w r2, r2, #8 - 8006412: 601a str r2, [r3, #0] - 8006414: e007 b.n 8006426 - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - 8006416: 687b ldr r3, [r7, #4] - 8006418: 681b ldr r3, [r3, #0] - 800641a: 681a ldr r2, [r3, #0] - 800641c: 687b ldr r3, [r7, #4] - 800641e: 681b ldr r3, [r3, #0] - 8006420: f022 0208 bic.w r2, r2, #8 - 8006424: 601a str r2, [r3, #0] - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TransmitFifoPriority == ENABLE) - 8006426: 687b ldr r3, [r7, #4] - 8006428: 7f5b ldrb r3, [r3, #29] - 800642a: 2b01 cmp r3, #1 - 800642c: d108 bne.n 8006440 - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 800642e: 687b ldr r3, [r7, #4] - 8006430: 681b ldr r3, [r3, #0] - 8006432: 681a ldr r2, [r3, #0] - 8006434: 687b ldr r3, [r7, #4] - 8006436: 681b ldr r3, [r3, #0] - 8006438: f042 0204 orr.w r2, r2, #4 - 800643c: 601a str r2, [r3, #0] - 800643e: e007 b.n 8006450 - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - 8006440: 687b ldr r3, [r7, #4] - 8006442: 681b ldr r3, [r3, #0] - 8006444: 681a ldr r2, [r3, #0] - 8006446: 687b ldr r3, [r7, #4] - 8006448: 681b ldr r3, [r3, #0] - 800644a: f022 0204 bic.w r2, r2, #4 - 800644e: 601a str r2, [r3, #0] - } - - /* Set the bit timing register */ - WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - 8006450: 687b ldr r3, [r7, #4] - 8006452: 689a ldr r2, [r3, #8] - 8006454: 687b ldr r3, [r7, #4] - 8006456: 68db ldr r3, [r3, #12] - 8006458: 431a orrs r2, r3 - 800645a: 687b ldr r3, [r7, #4] - 800645c: 691b ldr r3, [r3, #16] - 800645e: 431a orrs r2, r3 - 8006460: 687b ldr r3, [r7, #4] - 8006462: 695b ldr r3, [r3, #20] - 8006464: ea42 0103 orr.w r1, r2, r3 - 8006468: 687b ldr r3, [r7, #4] - 800646a: 685b ldr r3, [r3, #4] - 800646c: 1e5a subs r2, r3, #1 - 800646e: 687b ldr r3, [r7, #4] - 8006470: 681b ldr r3, [r3, #0] - 8006472: 430a orrs r2, r1 - 8006474: 61da str r2, [r3, #28] - hcan->Init.TimeSeg1 | - hcan->Init.TimeSeg2 | - (hcan->Init.Prescaler - 1U))); - - /* Initialize the error code */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 8006476: 687b ldr r3, [r7, #4] - 8006478: 2200 movs r2, #0 - 800647a: 625a str r2, [r3, #36] @ 0x24 - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - 800647c: 687b ldr r3, [r7, #4] - 800647e: 2201 movs r2, #1 - 8006480: f883 2020 strb.w r2, [r3, #32] - - /* Return function status */ - return HAL_OK; - 8006484: 2300 movs r3, #0 -} - 8006486: 4618 mov r0, r3 - 8006488: 3710 adds r7, #16 - 800648a: 46bd mov sp, r7 - 800648c: bd80 pop {r7, pc} - ... - -08006490 : - * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) -{ - 8006490: b480 push {r7} - 8006492: b087 sub sp, #28 - 8006494: af00 add r7, sp, #0 - 8006496: 6078 str r0, [r7, #4] - 8006498: 6039 str r1, [r7, #0] - uint32_t filternbrbitpos; - CAN_TypeDef *can_ip = hcan->Instance; - 800649a: 687b ldr r3, [r7, #4] - 800649c: 681b ldr r3, [r3, #0] - 800649e: 617b str r3, [r7, #20] - HAL_CAN_StateTypeDef state = hcan->State; - 80064a0: 687b ldr r3, [r7, #4] - 80064a2: f893 3020 ldrb.w r3, [r3, #32] - 80064a6: 74fb strb r3, [r7, #19] - - if ((state == HAL_CAN_STATE_READY) || - 80064a8: 7cfb ldrb r3, [r7, #19] - 80064aa: 2b01 cmp r3, #1 - 80064ac: d003 beq.n 80064b6 - 80064ae: 7cfb ldrb r3, [r7, #19] - 80064b0: 2b02 cmp r3, #2 - 80064b2: f040 80be bne.w 8006632 - assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); - -#if defined(CAN2) - /* CAN1 and CAN2 are dual instances with 28 common filters banks */ - /* Select master instance to access the filter banks */ - can_ip = CAN1; - 80064b6: 4b65 ldr r3, [pc, #404] @ (800664c ) - 80064b8: 617b str r3, [r7, #20] - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif - - /* Initialisation mode for the filter */ - SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - 80064ba: 697b ldr r3, [r7, #20] - 80064bc: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 80064c0: f043 0201 orr.w r2, r3, #1 - 80064c4: 697b ldr r3, [r7, #20] - 80064c6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 - -#if defined(CAN2) - /* Select the start filter number of CAN2 slave instance */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); - 80064ca: 697b ldr r3, [r7, #20] - 80064cc: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 80064d0: f423 527c bic.w r2, r3, #16128 @ 0x3f00 - 80064d4: 697b ldr r3, [r7, #20] - 80064d6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 - SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); - 80064da: 697b ldr r3, [r7, #20] - 80064dc: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 - 80064e0: 683b ldr r3, [r7, #0] - 80064e2: 6a5b ldr r3, [r3, #36] @ 0x24 - 80064e4: 021b lsls r3, r3, #8 - 80064e6: 431a orrs r2, r3 - 80064e8: 697b ldr r3, [r7, #20] - 80064ea: f8c3 2200 str.w r2, [r3, #512] @ 0x200 - -#endif - /* Convert filter number into bit position */ - filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - 80064ee: 683b ldr r3, [r7, #0] - 80064f0: 695b ldr r3, [r3, #20] - 80064f2: f003 031f and.w r3, r3, #31 - 80064f6: 2201 movs r2, #1 - 80064f8: fa02 f303 lsl.w r3, r2, r3 - 80064fc: 60fb str r3, [r7, #12] - - /* Filter Deactivation */ - CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - 80064fe: 697b ldr r3, [r7, #20] - 8006500: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 8006504: 68fb ldr r3, [r7, #12] - 8006506: 43db mvns r3, r3 - 8006508: 401a ands r2, r3 - 800650a: 697b ldr r3, [r7, #20] - 800650c: f8c3 221c str.w r2, [r3, #540] @ 0x21c - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - 8006510: 683b ldr r3, [r7, #0] - 8006512: 69db ldr r3, [r3, #28] - 8006514: 2b00 cmp r3, #0 - 8006516: d123 bne.n 8006560 - { - /* 16-bit scale for the filter */ - CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - 8006518: 697b ldr r3, [r7, #20] - 800651a: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 800651e: 68fb ldr r3, [r7, #12] - 8006520: 43db mvns r3, r3 - 8006522: 401a ands r2, r3 - 8006524: 697b ldr r3, [r7, #20] - 8006526: f8c3 220c str.w r2, [r3, #524] @ 0x20c - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 800652a: 683b ldr r3, [r7, #0] - 800652c: 68db ldr r3, [r3, #12] - 800652e: 0419 lsls r1, r3, #16 - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 8006530: 683b ldr r3, [r7, #0] - 8006532: 685b ldr r3, [r3, #4] - 8006534: b29b uxth r3, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8006536: 683a ldr r2, [r7, #0] - 8006538: 6952 ldr r2, [r2, #20] - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - 800653a: 4319 orrs r1, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 800653c: 697b ldr r3, [r7, #20] - 800653e: 3248 adds r2, #72 @ 0x48 - 8006540: f843 1032 str.w r1, [r3, r2, lsl #3] - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8006544: 683b ldr r3, [r7, #0] - 8006546: 689b ldr r3, [r3, #8] - 8006548: 0419 lsls r1, r3, #16 - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - 800654a: 683b ldr r3, [r7, #0] - 800654c: 681b ldr r3, [r3, #0] - 800654e: b29a uxth r2, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 8006550: 683b ldr r3, [r7, #0] - 8006552: 695b ldr r3, [r3, #20] - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8006554: 430a orrs r2, r1 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 8006556: 6979 ldr r1, [r7, #20] - 8006558: 3348 adds r3, #72 @ 0x48 - 800655a: 00db lsls r3, r3, #3 - 800655c: 440b add r3, r1 - 800655e: 605a str r2, [r3, #4] - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - 8006560: 683b ldr r3, [r7, #0] - 8006562: 69db ldr r3, [r3, #28] - 8006564: 2b01 cmp r3, #1 - 8006566: d122 bne.n 80065ae - { - /* 32-bit scale for the filter */ - SET_BIT(can_ip->FS1R, filternbrbitpos); - 8006568: 697b ldr r3, [r7, #20] - 800656a: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c - 800656e: 68fb ldr r3, [r7, #12] - 8006570: 431a orrs r2, r3 - 8006572: 697b ldr r3, [r7, #20] - 8006574: f8c3 220c str.w r2, [r3, #524] @ 0x20c - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 8006578: 683b ldr r3, [r7, #0] - 800657a: 681b ldr r3, [r3, #0] - 800657c: 0419 lsls r1, r3, #16 - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - 800657e: 683b ldr r3, [r7, #0] - 8006580: 685b ldr r3, [r3, #4] - 8006582: b29b uxth r3, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 8006584: 683a ldr r2, [r7, #0] - 8006586: 6952 ldr r2, [r2, #20] - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - 8006588: 4319 orrs r1, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - 800658a: 697b ldr r3, [r7, #20] - 800658c: 3248 adds r2, #72 @ 0x48 - 800658e: f843 1032 str.w r1, [r3, r2, lsl #3] - - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 8006592: 683b ldr r3, [r7, #0] - 8006594: 689b ldr r3, [r3, #8] - 8006596: 0419 lsls r1, r3, #16 - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - 8006598: 683b ldr r3, [r7, #0] - 800659a: 68db ldr r3, [r3, #12] - 800659c: b29a uxth r2, r3 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 800659e: 683b ldr r3, [r7, #0] - 80065a0: 695b ldr r3, [r3, #20] - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - 80065a2: 430a orrs r2, r1 - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - 80065a4: 6979 ldr r1, [r7, #20] - 80065a6: 3348 adds r3, #72 @ 0x48 - 80065a8: 00db lsls r3, r3, #3 - 80065aa: 440b add r3, r1 - 80065ac: 605a str r2, [r3, #4] - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - 80065ae: 683b ldr r3, [r7, #0] - 80065b0: 699b ldr r3, [r3, #24] - 80065b2: 2b00 cmp r3, #0 - 80065b4: d109 bne.n 80065ca - { - /* Id/Mask mode for the filter*/ - CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - 80065b6: 697b ldr r3, [r7, #20] - 80065b8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 80065bc: 68fb ldr r3, [r7, #12] - 80065be: 43db mvns r3, r3 - 80065c0: 401a ands r2, r3 - 80065c2: 697b ldr r3, [r7, #20] - 80065c4: f8c3 2204 str.w r2, [r3, #516] @ 0x204 - 80065c8: e007 b.n 80065da - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /* Identifier list mode for the filter*/ - SET_BIT(can_ip->FM1R, filternbrbitpos); - 80065ca: 697b ldr r3, [r7, #20] - 80065cc: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 - 80065d0: 68fb ldr r3, [r7, #12] - 80065d2: 431a orrs r2, r3 - 80065d4: 697b ldr r3, [r7, #20] - 80065d6: f8c3 2204 str.w r2, [r3, #516] @ 0x204 - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - 80065da: 683b ldr r3, [r7, #0] - 80065dc: 691b ldr r3, [r3, #16] - 80065de: 2b00 cmp r3, #0 - 80065e0: d109 bne.n 80065f6 - { - /* FIFO 0 assignation for the filter */ - CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - 80065e2: 697b ldr r3, [r7, #20] - 80065e4: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 80065e8: 68fb ldr r3, [r7, #12] - 80065ea: 43db mvns r3, r3 - 80065ec: 401a ands r2, r3 - 80065ee: 697b ldr r3, [r7, #20] - 80065f0: f8c3 2214 str.w r2, [r3, #532] @ 0x214 - 80065f4: e007 b.n 8006606 - } - else - { - /* FIFO 1 assignation for the filter */ - SET_BIT(can_ip->FFA1R, filternbrbitpos); - 80065f6: 697b ldr r3, [r7, #20] - 80065f8: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 - 80065fc: 68fb ldr r3, [r7, #12] - 80065fe: 431a orrs r2, r3 - 8006600: 697b ldr r3, [r7, #20] - 8006602: f8c3 2214 str.w r2, [r3, #532] @ 0x214 - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - 8006606: 683b ldr r3, [r7, #0] - 8006608: 6a1b ldr r3, [r3, #32] - 800660a: 2b01 cmp r3, #1 - 800660c: d107 bne.n 800661e - { - SET_BIT(can_ip->FA1R, filternbrbitpos); - 800660e: 697b ldr r3, [r7, #20] - 8006610: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c - 8006614: 68fb ldr r3, [r7, #12] - 8006616: 431a orrs r2, r3 - 8006618: 697b ldr r3, [r7, #20] - 800661a: f8c3 221c str.w r2, [r3, #540] @ 0x21c - } - - /* Leave the initialisation mode for the filter */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - 800661e: 697b ldr r3, [r7, #20] - 8006620: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 - 8006624: f023 0201 bic.w r2, r3, #1 - 8006628: 697b ldr r3, [r7, #20] - 800662a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 - - /* Return function status */ - return HAL_OK; - 800662e: 2300 movs r3, #0 - 8006630: e006 b.n 8006640 - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8006632: 687b ldr r3, [r7, #4] - 8006634: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006636: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 800663a: 687b ldr r3, [r7, #4] - 800663c: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 800663e: 2301 movs r3, #1 - } -} - 8006640: 4618 mov r0, r3 - 8006642: 371c adds r7, #28 - 8006644: 46bd mov sp, r7 - 8006646: bc80 pop {r7} - 8006648: 4770 bx lr - 800664a: bf00 nop - 800664c: 40006400 .word 0x40006400 - -08006650 : - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) -{ - 8006650: b580 push {r7, lr} - 8006652: b084 sub sp, #16 - 8006654: af00 add r7, sp, #0 - 8006656: 6078 str r0, [r7, #4] - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_READY) - 8006658: 687b ldr r3, [r7, #4] - 800665a: f893 3020 ldrb.w r3, [r3, #32] - 800665e: b2db uxtb r3, r3 - 8006660: 2b01 cmp r3, #1 - 8006662: d12e bne.n 80066c2 - { - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_LISTENING; - 8006664: 687b ldr r3, [r7, #4] - 8006666: 2202 movs r2, #2 - 8006668: f883 2020 strb.w r2, [r3, #32] - - /* Request leave initialisation */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 800666c: 687b ldr r3, [r7, #4] - 800666e: 681b ldr r3, [r3, #0] - 8006670: 681a ldr r2, [r3, #0] - 8006672: 687b ldr r3, [r7, #4] - 8006674: 681b ldr r3, [r3, #0] - 8006676: f022 0201 bic.w r2, r2, #1 - 800667a: 601a str r2, [r3, #0] - - /* Get tick */ - tickstart = HAL_GetTick(); - 800667c: f7ff f8da bl 8005834 - 8006680: 60f8 str r0, [r7, #12] - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 8006682: e012 b.n 80066aa - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8006684: f7ff f8d6 bl 8005834 - 8006688: 4602 mov r2, r0 - 800668a: 68fb ldr r3, [r7, #12] - 800668c: 1ad3 subs r3, r2, r3 - 800668e: 2b0a cmp r3, #10 - 8006690: d90b bls.n 80066aa - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 8006692: 687b ldr r3, [r7, #4] - 8006694: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006696: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 800669a: 687b ldr r3, [r7, #4] - 800669c: 625a str r2, [r3, #36] @ 0x24 - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - 800669e: 687b ldr r3, [r7, #4] - 80066a0: 2205 movs r2, #5 - 80066a2: f883 2020 strb.w r2, [r3, #32] - - return HAL_ERROR; - 80066a6: 2301 movs r3, #1 - 80066a8: e012 b.n 80066d0 - while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - 80066aa: 687b ldr r3, [r7, #4] - 80066ac: 681b ldr r3, [r3, #0] - 80066ae: 685b ldr r3, [r3, #4] - 80066b0: f003 0301 and.w r3, r3, #1 - 80066b4: 2b00 cmp r3, #0 - 80066b6: d1e5 bne.n 8006684 - } - } - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - 80066b8: 687b ldr r3, [r7, #4] - 80066ba: 2200 movs r2, #0 - 80066bc: 625a str r2, [r3, #36] @ 0x24 - - /* Return function status */ - return HAL_OK; - 80066be: 2300 movs r3, #0 - 80066c0: e006 b.n 80066d0 - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - 80066c2: 687b ldr r3, [r7, #4] - 80066c4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80066c6: f443 2200 orr.w r2, r3, #524288 @ 0x80000 - 80066ca: 687b ldr r3, [r7, #4] - 80066cc: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 80066ce: 2301 movs r3, #1 - } -} - 80066d0: 4618 mov r0, r3 - 80066d2: 3710 adds r7, #16 - 80066d4: 46bd mov sp, r7 - 80066d6: bd80 pop {r7, pc} - -080066d8 : - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) -{ - 80066d8: b580 push {r7, lr} - 80066da: b084 sub sp, #16 - 80066dc: af00 add r7, sp, #0 - 80066de: 6078 str r0, [r7, #4] - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_LISTENING) - 80066e0: 687b ldr r3, [r7, #4] - 80066e2: f893 3020 ldrb.w r3, [r3, #32] - 80066e6: b2db uxtb r3, r3 - 80066e8: 2b02 cmp r3, #2 - 80066ea: d133 bne.n 8006754 - { - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - 80066ec: 687b ldr r3, [r7, #4] - 80066ee: 681b ldr r3, [r3, #0] - 80066f0: 681a ldr r2, [r3, #0] - 80066f2: 687b ldr r3, [r7, #4] - 80066f4: 681b ldr r3, [r3, #0] - 80066f6: f042 0201 orr.w r2, r2, #1 - 80066fa: 601a str r2, [r3, #0] - - /* Get tick */ - tickstart = HAL_GetTick(); - 80066fc: f7ff f89a bl 8005834 - 8006700: 60f8 str r0, [r7, #12] - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 8006702: e012 b.n 800672a - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - 8006704: f7ff f896 bl 8005834 - 8006708: 4602 mov r2, r0 - 800670a: 68fb ldr r3, [r7, #12] - 800670c: 1ad3 subs r3, r2, r3 - 800670e: 2b0a cmp r3, #10 - 8006710: d90b bls.n 800672a - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - 8006712: 687b ldr r3, [r7, #4] - 8006714: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006716: f443 3200 orr.w r2, r3, #131072 @ 0x20000 - 800671a: 687b ldr r3, [r7, #4] - 800671c: 625a str r2, [r3, #36] @ 0x24 - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - 800671e: 687b ldr r3, [r7, #4] - 8006720: 2205 movs r2, #5 - 8006722: f883 2020 strb.w r2, [r3, #32] - - return HAL_ERROR; - 8006726: 2301 movs r3, #1 - 8006728: e01b b.n 8006762 - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - 800672a: 687b ldr r3, [r7, #4] - 800672c: 681b ldr r3, [r3, #0] - 800672e: 685b ldr r3, [r3, #4] - 8006730: f003 0301 and.w r3, r3, #1 - 8006734: 2b00 cmp r3, #0 - 8006736: d0e5 beq.n 8006704 - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - 8006738: 687b ldr r3, [r7, #4] - 800673a: 681b ldr r3, [r3, #0] - 800673c: 681a ldr r2, [r3, #0] - 800673e: 687b ldr r3, [r7, #4] - 8006740: 681b ldr r3, [r3, #0] - 8006742: f022 0202 bic.w r2, r2, #2 - 8006746: 601a str r2, [r3, #0] - - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_READY; - 8006748: 687b ldr r3, [r7, #4] - 800674a: 2201 movs r2, #1 - 800674c: f883 2020 strb.w r2, [r3, #32] - - /* Return function status */ - return HAL_OK; - 8006750: 2300 movs r3, #0 - 8006752: e006 b.n 8006762 - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - 8006754: 687b ldr r3, [r7, #4] - 8006756: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006758: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 - 800675c: 687b ldr r3, [r7, #4] - 800675e: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006760: 2301 movs r3, #1 - } -} - 8006762: 4618 mov r0, r3 - 8006764: 3710 adds r7, #16 - 8006766: 46bd mov sp, r7 - 8006768: bd80 pop {r7, pc} - -0800676a : - * the TxMailbox used to store the Tx message. - * This parameter can be a value of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) -{ - 800676a: b480 push {r7} - 800676c: b089 sub sp, #36 @ 0x24 - 800676e: af00 add r7, sp, #0 - 8006770: 60f8 str r0, [r7, #12] - 8006772: 60b9 str r1, [r7, #8] - 8006774: 607a str r2, [r7, #4] - 8006776: 603b str r3, [r7, #0] - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - 8006778: 68fb ldr r3, [r7, #12] - 800677a: f893 3020 ldrb.w r3, [r3, #32] - 800677e: 77fb strb r3, [r7, #31] - uint32_t tsr = READ_REG(hcan->Instance->TSR); - 8006780: 68fb ldr r3, [r7, #12] - 8006782: 681b ldr r3, [r3, #0] - 8006784: 689b ldr r3, [r3, #8] - 8006786: 61bb str r3, [r7, #24] - { - assert_param(IS_CAN_EXTID(pHeader->ExtId)); - } - assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - - if ((state == HAL_CAN_STATE_READY) || - 8006788: 7ffb ldrb r3, [r7, #31] - 800678a: 2b01 cmp r3, #1 - 800678c: d003 beq.n 8006796 - 800678e: 7ffb ldrb r3, [r7, #31] - 8006790: 2b02 cmp r3, #2 - 8006792: f040 80b8 bne.w 8006906 - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check that all the Tx mailboxes are not full */ - if (((tsr & CAN_TSR_TME0) != 0U) || - 8006796: 69bb ldr r3, [r7, #24] - 8006798: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 800679c: 2b00 cmp r3, #0 - 800679e: d10a bne.n 80067b6 - ((tsr & CAN_TSR_TME1) != 0U) || - 80067a0: 69bb ldr r3, [r7, #24] - 80067a2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - if (((tsr & CAN_TSR_TME0) != 0U) || - 80067a6: 2b00 cmp r3, #0 - 80067a8: d105 bne.n 80067b6 - ((tsr & CAN_TSR_TME2) != 0U)) - 80067aa: 69bb ldr r3, [r7, #24] - 80067ac: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - ((tsr & CAN_TSR_TME1) != 0U) || - 80067b0: 2b00 cmp r3, #0 - 80067b2: f000 80a0 beq.w 80068f6 - { - /* Select an empty transmit mailbox */ - transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - 80067b6: 69bb ldr r3, [r7, #24] - 80067b8: 0e1b lsrs r3, r3, #24 - 80067ba: f003 0303 and.w r3, r3, #3 - 80067be: 617b str r3, [r7, #20] - - /* Check transmit mailbox value */ - if (transmitmailbox > 2U) - 80067c0: 697b ldr r3, [r7, #20] - 80067c2: 2b02 cmp r3, #2 - 80067c4: d907 bls.n 80067d6 - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; - 80067c6: 68fb ldr r3, [r7, #12] - 80067c8: 6a5b ldr r3, [r3, #36] @ 0x24 - 80067ca: f443 0200 orr.w r2, r3, #8388608 @ 0x800000 - 80067ce: 68fb ldr r3, [r7, #12] - 80067d0: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 80067d2: 2301 movs r3, #1 - 80067d4: e09e b.n 8006914 - } - - /* Store the Tx mailbox */ - *pTxMailbox = (uint32_t)1 << transmitmailbox; - 80067d6: 2201 movs r2, #1 - 80067d8: 697b ldr r3, [r7, #20] - 80067da: 409a lsls r2, r3 - 80067dc: 683b ldr r3, [r7, #0] - 80067de: 601a str r2, [r3, #0] - - /* Set up the Id */ - if (pHeader->IDE == CAN_ID_STD) - 80067e0: 68bb ldr r3, [r7, #8] - 80067e2: 689b ldr r3, [r3, #8] - 80067e4: 2b00 cmp r3, #0 - 80067e6: d10d bne.n 8006804 - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 80067e8: 68bb ldr r3, [r7, #8] - 80067ea: 681b ldr r3, [r3, #0] - 80067ec: 055a lsls r2, r3, #21 - pHeader->RTR); - 80067ee: 68bb ldr r3, [r7, #8] - 80067f0: 68db ldr r3, [r3, #12] - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - 80067f2: 68f9 ldr r1, [r7, #12] - 80067f4: 6809 ldr r1, [r1, #0] - 80067f6: 431a orrs r2, r3 - 80067f8: 697b ldr r3, [r7, #20] - 80067fa: 3318 adds r3, #24 - 80067fc: 011b lsls r3, r3, #4 - 80067fe: 440b add r3, r1 - 8006800: 601a str r2, [r3, #0] - 8006802: e00f b.n 8006824 - } - else - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8006804: 68bb ldr r3, [r7, #8] - 8006806: 685b ldr r3, [r3, #4] - 8006808: 00da lsls r2, r3, #3 - pHeader->IDE | - 800680a: 68bb ldr r3, [r7, #8] - 800680c: 689b ldr r3, [r3, #8] - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 800680e: 431a orrs r2, r3 - pHeader->RTR); - 8006810: 68bb ldr r3, [r7, #8] - 8006812: 68db ldr r3, [r3, #12] - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 8006814: 68f9 ldr r1, [r7, #12] - 8006816: 6809 ldr r1, [r1, #0] - pHeader->IDE | - 8006818: 431a orrs r2, r3 - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - 800681a: 697b ldr r3, [r7, #20] - 800681c: 3318 adds r3, #24 - 800681e: 011b lsls r3, r3, #4 - 8006820: 440b add r3, r1 - 8006822: 601a str r2, [r3, #0] - } - - /* Set up the DLC */ - hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - 8006824: 68fb ldr r3, [r7, #12] - 8006826: 6819 ldr r1, [r3, #0] - 8006828: 68bb ldr r3, [r7, #8] - 800682a: 691a ldr r2, [r3, #16] - 800682c: 697b ldr r3, [r7, #20] - 800682e: 3318 adds r3, #24 - 8006830: 011b lsls r3, r3, #4 - 8006832: 440b add r3, r1 - 8006834: 3304 adds r3, #4 - 8006836: 601a str r2, [r3, #0] - - /* Set up the Transmit Global Time mode */ - if (pHeader->TransmitGlobalTime == ENABLE) - 8006838: 68bb ldr r3, [r7, #8] - 800683a: 7d1b ldrb r3, [r3, #20] - 800683c: 2b01 cmp r3, #1 - 800683e: d111 bne.n 8006864 - { - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - 8006840: 68fb ldr r3, [r7, #12] - 8006842: 681a ldr r2, [r3, #0] - 8006844: 697b ldr r3, [r7, #20] - 8006846: 3318 adds r3, #24 - 8006848: 011b lsls r3, r3, #4 - 800684a: 4413 add r3, r2 - 800684c: 3304 adds r3, #4 - 800684e: 681b ldr r3, [r3, #0] - 8006850: 68fa ldr r2, [r7, #12] - 8006852: 6811 ldr r1, [r2, #0] - 8006854: f443 7280 orr.w r2, r3, #256 @ 0x100 - 8006858: 697b ldr r3, [r7, #20] - 800685a: 3318 adds r3, #24 - 800685c: 011b lsls r3, r3, #4 - 800685e: 440b add r3, r1 - 8006860: 3304 adds r3, #4 - 8006862: 601a str r2, [r3, #0] - } - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - 8006864: 687b ldr r3, [r7, #4] - 8006866: 3307 adds r3, #7 - 8006868: 781b ldrb r3, [r3, #0] - 800686a: 061a lsls r2, r3, #24 - 800686c: 687b ldr r3, [r7, #4] - 800686e: 3306 adds r3, #6 - 8006870: 781b ldrb r3, [r3, #0] - 8006872: 041b lsls r3, r3, #16 - 8006874: 431a orrs r2, r3 - 8006876: 687b ldr r3, [r7, #4] - 8006878: 3305 adds r3, #5 - 800687a: 781b ldrb r3, [r3, #0] - 800687c: 021b lsls r3, r3, #8 - 800687e: 4313 orrs r3, r2 - 8006880: 687a ldr r2, [r7, #4] - 8006882: 3204 adds r2, #4 - 8006884: 7812 ldrb r2, [r2, #0] - 8006886: 4610 mov r0, r2 - 8006888: 68fa ldr r2, [r7, #12] - 800688a: 6811 ldr r1, [r2, #0] - 800688c: ea43 0200 orr.w r2, r3, r0 - 8006890: 697b ldr r3, [r7, #20] - 8006892: 011b lsls r3, r3, #4 - 8006894: 440b add r3, r1 - 8006896: f503 73c6 add.w r3, r3, #396 @ 0x18c - 800689a: 601a str r2, [r3, #0] - ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | - ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | - ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | - ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - 800689c: 687b ldr r3, [r7, #4] - 800689e: 3303 adds r3, #3 - 80068a0: 781b ldrb r3, [r3, #0] - 80068a2: 061a lsls r2, r3, #24 - 80068a4: 687b ldr r3, [r7, #4] - 80068a6: 3302 adds r3, #2 - 80068a8: 781b ldrb r3, [r3, #0] - 80068aa: 041b lsls r3, r3, #16 - 80068ac: 431a orrs r2, r3 - 80068ae: 687b ldr r3, [r7, #4] - 80068b0: 3301 adds r3, #1 - 80068b2: 781b ldrb r3, [r3, #0] - 80068b4: 021b lsls r3, r3, #8 - 80068b6: 4313 orrs r3, r2 - 80068b8: 687a ldr r2, [r7, #4] - 80068ba: 7812 ldrb r2, [r2, #0] - 80068bc: 4610 mov r0, r2 - 80068be: 68fa ldr r2, [r7, #12] - 80068c0: 6811 ldr r1, [r2, #0] - 80068c2: ea43 0200 orr.w r2, r3, r0 - 80068c6: 697b ldr r3, [r7, #20] - 80068c8: 011b lsls r3, r3, #4 - 80068ca: 440b add r3, r1 - 80068cc: f503 73c4 add.w r3, r3, #392 @ 0x188 - 80068d0: 601a str r2, [r3, #0] - ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); - - /* Request transmission */ - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - 80068d2: 68fb ldr r3, [r7, #12] - 80068d4: 681a ldr r2, [r3, #0] - 80068d6: 697b ldr r3, [r7, #20] - 80068d8: 3318 adds r3, #24 - 80068da: 011b lsls r3, r3, #4 - 80068dc: 4413 add r3, r2 - 80068de: 681b ldr r3, [r3, #0] - 80068e0: 68fa ldr r2, [r7, #12] - 80068e2: 6811 ldr r1, [r2, #0] - 80068e4: f043 0201 orr.w r2, r3, #1 - 80068e8: 697b ldr r3, [r7, #20] - 80068ea: 3318 adds r3, #24 - 80068ec: 011b lsls r3, r3, #4 - 80068ee: 440b add r3, r1 - 80068f0: 601a str r2, [r3, #0] - - /* Return function status */ - return HAL_OK; - 80068f2: 2300 movs r3, #0 - 80068f4: e00e b.n 8006914 - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 80068f6: 68fb ldr r3, [r7, #12] - 80068f8: 6a5b ldr r3, [r3, #36] @ 0x24 - 80068fa: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 80068fe: 68fb ldr r3, [r7, #12] - 8006900: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006902: 2301 movs r3, #1 - 8006904: e006 b.n 8006914 - } - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8006906: 68fb ldr r3, [r7, #12] - 8006908: 6a5b ldr r3, [r3, #36] @ 0x24 - 800690a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 800690e: 68fb ldr r3, [r7, #12] - 8006910: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006912: 2301 movs r3, #1 - } -} - 8006914: 4618 mov r0, r3 - 8006916: 3724 adds r7, #36 @ 0x24 - 8006918: 46bd mov sp, r7 - 800691a: bc80 pop {r7} - 800691c: 4770 bx lr - -0800691e : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Number of free Tx Mailboxes. - */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) -{ - 800691e: b480 push {r7} - 8006920: b085 sub sp, #20 - 8006922: af00 add r7, sp, #0 - 8006924: 6078 str r0, [r7, #4] - uint32_t freelevel = 0U; - 8006926: 2300 movs r3, #0 - 8006928: 60fb str r3, [r7, #12] - HAL_CAN_StateTypeDef state = hcan->State; - 800692a: 687b ldr r3, [r7, #4] - 800692c: f893 3020 ldrb.w r3, [r3, #32] - 8006930: 72fb strb r3, [r7, #11] - - if ((state == HAL_CAN_STATE_READY) || - 8006932: 7afb ldrb r3, [r7, #11] - 8006934: 2b01 cmp r3, #1 - 8006936: d002 beq.n 800693e - 8006938: 7afb ldrb r3, [r7, #11] - 800693a: 2b02 cmp r3, #2 - 800693c: d11d bne.n 800697a - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) - 800693e: 687b ldr r3, [r7, #4] - 8006940: 681b ldr r3, [r3, #0] - 8006942: 689b ldr r3, [r3, #8] - 8006944: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 8006948: 2b00 cmp r3, #0 - 800694a: d002 beq.n 8006952 - { - freelevel++; - 800694c: 68fb ldr r3, [r7, #12] - 800694e: 3301 adds r3, #1 - 8006950: 60fb str r3, [r7, #12] - } - - /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) - 8006952: 687b ldr r3, [r7, #4] - 8006954: 681b ldr r3, [r3, #0] - 8006956: 689b ldr r3, [r3, #8] - 8006958: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - 800695c: 2b00 cmp r3, #0 - 800695e: d002 beq.n 8006966 - { - freelevel++; - 8006960: 68fb ldr r3, [r7, #12] - 8006962: 3301 adds r3, #1 - 8006964: 60fb str r3, [r7, #12] - } - - /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) - 8006966: 687b ldr r3, [r7, #4] - 8006968: 681b ldr r3, [r3, #0] - 800696a: 689b ldr r3, [r3, #8] - 800696c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8006970: 2b00 cmp r3, #0 - 8006972: d002 beq.n 800697a - { - freelevel++; - 8006974: 68fb ldr r3, [r7, #12] - 8006976: 3301 adds r3, #1 - 8006978: 60fb str r3, [r7, #12] - } - } - - /* Return Tx Mailboxes free level */ - return freelevel; - 800697a: 68fb ldr r3, [r7, #12] -} - 800697c: 4618 mov r0, r3 - 800697e: 3714 adds r7, #20 - 8006980: 46bd mov sp, r7 - 8006982: bc80 pop {r7} - 8006984: 4770 bx lr - -08006986 : - * of the Rx frame will be stored. - * @param aData array where the payload of the Rx frame will be stored. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) -{ - 8006986: b480 push {r7} - 8006988: b087 sub sp, #28 - 800698a: af00 add r7, sp, #0 - 800698c: 60f8 str r0, [r7, #12] - 800698e: 60b9 str r1, [r7, #8] - 8006990: 607a str r2, [r7, #4] - 8006992: 603b str r3, [r7, #0] - HAL_CAN_StateTypeDef state = hcan->State; - 8006994: 68fb ldr r3, [r7, #12] - 8006996: f893 3020 ldrb.w r3, [r3, #32] - 800699a: 75fb strb r3, [r7, #23] - - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - 800699c: 7dfb ldrb r3, [r7, #23] - 800699e: 2b01 cmp r3, #1 - 80069a0: d003 beq.n 80069aa - 80069a2: 7dfb ldrb r3, [r7, #23] - 80069a4: 2b02 cmp r3, #2 - 80069a6: f040 80f3 bne.w 8006b90 - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the Rx FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 80069aa: 68bb ldr r3, [r7, #8] - 80069ac: 2b00 cmp r3, #0 - 80069ae: d10e bne.n 80069ce - { - /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - 80069b0: 68fb ldr r3, [r7, #12] - 80069b2: 681b ldr r3, [r3, #0] - 80069b4: 68db ldr r3, [r3, #12] - 80069b6: f003 0303 and.w r3, r3, #3 - 80069ba: 2b00 cmp r3, #0 - 80069bc: d116 bne.n 80069ec - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 80069be: 68fb ldr r3, [r7, #12] - 80069c0: 6a5b ldr r3, [r3, #36] @ 0x24 - 80069c2: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 80069c6: 68fb ldr r3, [r7, #12] - 80069c8: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 80069ca: 2301 movs r3, #1 - 80069cc: e0e7 b.n 8006b9e - } - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - 80069ce: 68fb ldr r3, [r7, #12] - 80069d0: 681b ldr r3, [r3, #0] - 80069d2: 691b ldr r3, [r3, #16] - 80069d4: f003 0303 and.w r3, r3, #3 - 80069d8: 2b00 cmp r3, #0 - 80069da: d107 bne.n 80069ec - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - 80069dc: 68fb ldr r3, [r7, #12] - 80069de: 6a5b ldr r3, [r3, #36] @ 0x24 - 80069e0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 - 80069e4: 68fb ldr r3, [r7, #12] - 80069e6: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 80069e8: 2301 movs r3, #1 - 80069ea: e0d8 b.n 8006b9e - } - } - - /* Get the header */ - pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - 80069ec: 68fb ldr r3, [r7, #12] - 80069ee: 681a ldr r2, [r3, #0] - 80069f0: 68bb ldr r3, [r7, #8] - 80069f2: 331b adds r3, #27 - 80069f4: 011b lsls r3, r3, #4 - 80069f6: 4413 add r3, r2 - 80069f8: 681b ldr r3, [r3, #0] - 80069fa: f003 0204 and.w r2, r3, #4 - 80069fe: 687b ldr r3, [r7, #4] - 8006a00: 609a str r2, [r3, #8] - if (pHeader->IDE == CAN_ID_STD) - 8006a02: 687b ldr r3, [r7, #4] - 8006a04: 689b ldr r3, [r3, #8] - 8006a06: 2b00 cmp r3, #0 - 8006a08: d10c bne.n 8006a24 - { - pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - 8006a0a: 68fb ldr r3, [r7, #12] - 8006a0c: 681a ldr r2, [r3, #0] - 8006a0e: 68bb ldr r3, [r7, #8] - 8006a10: 331b adds r3, #27 - 8006a12: 011b lsls r3, r3, #4 - 8006a14: 4413 add r3, r2 - 8006a16: 681b ldr r3, [r3, #0] - 8006a18: 0d5b lsrs r3, r3, #21 - 8006a1a: f3c3 020a ubfx r2, r3, #0, #11 - 8006a1e: 687b ldr r3, [r7, #4] - 8006a20: 601a str r2, [r3, #0] - 8006a22: e00b b.n 8006a3c - } - else - { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; - 8006a24: 68fb ldr r3, [r7, #12] - 8006a26: 681a ldr r2, [r3, #0] - 8006a28: 68bb ldr r3, [r7, #8] - 8006a2a: 331b adds r3, #27 - 8006a2c: 011b lsls r3, r3, #4 - 8006a2e: 4413 add r3, r2 - 8006a30: 681b ldr r3, [r3, #0] - 8006a32: 08db lsrs r3, r3, #3 - 8006a34: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 - 8006a38: 687b ldr r3, [r7, #4] - 8006a3a: 605a str r2, [r3, #4] - } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - 8006a3c: 68fb ldr r3, [r7, #12] - 8006a3e: 681a ldr r2, [r3, #0] - 8006a40: 68bb ldr r3, [r7, #8] - 8006a42: 331b adds r3, #27 - 8006a44: 011b lsls r3, r3, #4 - 8006a46: 4413 add r3, r2 - 8006a48: 681b ldr r3, [r3, #0] - 8006a4a: f003 0202 and.w r2, r3, #2 - 8006a4e: 687b ldr r3, [r7, #4] - 8006a50: 60da str r2, [r3, #12] - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - 8006a52: 68fb ldr r3, [r7, #12] - 8006a54: 681a ldr r2, [r3, #0] - 8006a56: 68bb ldr r3, [r7, #8] - 8006a58: 331b adds r3, #27 - 8006a5a: 011b lsls r3, r3, #4 - 8006a5c: 4413 add r3, r2 - 8006a5e: 3304 adds r3, #4 - 8006a60: 681b ldr r3, [r3, #0] - 8006a62: f003 020f and.w r2, r3, #15 - 8006a66: 687b ldr r3, [r7, #4] - 8006a68: 611a str r2, [r3, #16] - pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; - 8006a6a: 68fb ldr r3, [r7, #12] - 8006a6c: 681a ldr r2, [r3, #0] - 8006a6e: 68bb ldr r3, [r7, #8] - 8006a70: 331b adds r3, #27 - 8006a72: 011b lsls r3, r3, #4 - 8006a74: 4413 add r3, r2 - 8006a76: 3304 adds r3, #4 - 8006a78: 681b ldr r3, [r3, #0] - 8006a7a: 0a1b lsrs r3, r3, #8 - 8006a7c: b2da uxtb r2, r3 - 8006a7e: 687b ldr r3, [r7, #4] - 8006a80: 619a str r2, [r3, #24] - pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - 8006a82: 68fb ldr r3, [r7, #12] - 8006a84: 681a ldr r2, [r3, #0] - 8006a86: 68bb ldr r3, [r7, #8] - 8006a88: 331b adds r3, #27 - 8006a8a: 011b lsls r3, r3, #4 - 8006a8c: 4413 add r3, r2 - 8006a8e: 3304 adds r3, #4 - 8006a90: 681b ldr r3, [r3, #0] - 8006a92: 0c1b lsrs r3, r3, #16 - 8006a94: b29a uxth r2, r3 - 8006a96: 687b ldr r3, [r7, #4] - 8006a98: 615a str r2, [r3, #20] - - /* Get the data */ - aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - 8006a9a: 68fb ldr r3, [r7, #12] - 8006a9c: 681a ldr r2, [r3, #0] - 8006a9e: 68bb ldr r3, [r7, #8] - 8006aa0: 011b lsls r3, r3, #4 - 8006aa2: 4413 add r3, r2 - 8006aa4: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8006aa8: 681b ldr r3, [r3, #0] - 8006aaa: b2da uxtb r2, r3 - 8006aac: 683b ldr r3, [r7, #0] - 8006aae: 701a strb r2, [r3, #0] - aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - 8006ab0: 68fb ldr r3, [r7, #12] - 8006ab2: 681a ldr r2, [r3, #0] - 8006ab4: 68bb ldr r3, [r7, #8] - 8006ab6: 011b lsls r3, r3, #4 - 8006ab8: 4413 add r3, r2 - 8006aba: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8006abe: 681b ldr r3, [r3, #0] - 8006ac0: 0a1a lsrs r2, r3, #8 - 8006ac2: 683b ldr r3, [r7, #0] - 8006ac4: 3301 adds r3, #1 - 8006ac6: b2d2 uxtb r2, r2 - 8006ac8: 701a strb r2, [r3, #0] - aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - 8006aca: 68fb ldr r3, [r7, #12] - 8006acc: 681a ldr r2, [r3, #0] - 8006ace: 68bb ldr r3, [r7, #8] - 8006ad0: 011b lsls r3, r3, #4 - 8006ad2: 4413 add r3, r2 - 8006ad4: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8006ad8: 681b ldr r3, [r3, #0] - 8006ada: 0c1a lsrs r2, r3, #16 - 8006adc: 683b ldr r3, [r7, #0] - 8006ade: 3302 adds r3, #2 - 8006ae0: b2d2 uxtb r2, r2 - 8006ae2: 701a strb r2, [r3, #0] - aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - 8006ae4: 68fb ldr r3, [r7, #12] - 8006ae6: 681a ldr r2, [r3, #0] - 8006ae8: 68bb ldr r3, [r7, #8] - 8006aea: 011b lsls r3, r3, #4 - 8006aec: 4413 add r3, r2 - 8006aee: f503 73dc add.w r3, r3, #440 @ 0x1b8 - 8006af2: 681b ldr r3, [r3, #0] - 8006af4: 0e1a lsrs r2, r3, #24 - 8006af6: 683b ldr r3, [r7, #0] - 8006af8: 3303 adds r3, #3 - 8006afa: b2d2 uxtb r2, r2 - 8006afc: 701a strb r2, [r3, #0] - aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - 8006afe: 68fb ldr r3, [r7, #12] - 8006b00: 681a ldr r2, [r3, #0] - 8006b02: 68bb ldr r3, [r7, #8] - 8006b04: 011b lsls r3, r3, #4 - 8006b06: 4413 add r3, r2 - 8006b08: f503 73de add.w r3, r3, #444 @ 0x1bc - 8006b0c: 681a ldr r2, [r3, #0] - 8006b0e: 683b ldr r3, [r7, #0] - 8006b10: 3304 adds r3, #4 - 8006b12: b2d2 uxtb r2, r2 - 8006b14: 701a strb r2, [r3, #0] - aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - 8006b16: 68fb ldr r3, [r7, #12] - 8006b18: 681a ldr r2, [r3, #0] - 8006b1a: 68bb ldr r3, [r7, #8] - 8006b1c: 011b lsls r3, r3, #4 - 8006b1e: 4413 add r3, r2 - 8006b20: f503 73de add.w r3, r3, #444 @ 0x1bc - 8006b24: 681b ldr r3, [r3, #0] - 8006b26: 0a1a lsrs r2, r3, #8 - 8006b28: 683b ldr r3, [r7, #0] - 8006b2a: 3305 adds r3, #5 - 8006b2c: b2d2 uxtb r2, r2 - 8006b2e: 701a strb r2, [r3, #0] - aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - 8006b30: 68fb ldr r3, [r7, #12] - 8006b32: 681a ldr r2, [r3, #0] - 8006b34: 68bb ldr r3, [r7, #8] - 8006b36: 011b lsls r3, r3, #4 - 8006b38: 4413 add r3, r2 - 8006b3a: f503 73de add.w r3, r3, #444 @ 0x1bc - 8006b3e: 681b ldr r3, [r3, #0] - 8006b40: 0c1a lsrs r2, r3, #16 - 8006b42: 683b ldr r3, [r7, #0] - 8006b44: 3306 adds r3, #6 - 8006b46: b2d2 uxtb r2, r2 - 8006b48: 701a strb r2, [r3, #0] - aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - 8006b4a: 68fb ldr r3, [r7, #12] - 8006b4c: 681a ldr r2, [r3, #0] - 8006b4e: 68bb ldr r3, [r7, #8] - 8006b50: 011b lsls r3, r3, #4 - 8006b52: 4413 add r3, r2 - 8006b54: f503 73de add.w r3, r3, #444 @ 0x1bc - 8006b58: 681b ldr r3, [r3, #0] - 8006b5a: 0e1a lsrs r2, r3, #24 - 8006b5c: 683b ldr r3, [r7, #0] - 8006b5e: 3307 adds r3, #7 - 8006b60: b2d2 uxtb r2, r2 - 8006b62: 701a strb r2, [r3, #0] - - /* Release the FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - 8006b64: 68bb ldr r3, [r7, #8] - 8006b66: 2b00 cmp r3, #0 - 8006b68: d108 bne.n 8006b7c - { - /* Release RX FIFO 0 */ - SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - 8006b6a: 68fb ldr r3, [r7, #12] - 8006b6c: 681b ldr r3, [r3, #0] - 8006b6e: 68da ldr r2, [r3, #12] - 8006b70: 68fb ldr r3, [r7, #12] - 8006b72: 681b ldr r3, [r3, #0] - 8006b74: f042 0220 orr.w r2, r2, #32 - 8006b78: 60da str r2, [r3, #12] - 8006b7a: e007 b.n 8006b8c - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Release RX FIFO 1 */ - SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - 8006b7c: 68fb ldr r3, [r7, #12] - 8006b7e: 681b ldr r3, [r3, #0] - 8006b80: 691a ldr r2, [r3, #16] - 8006b82: 68fb ldr r3, [r7, #12] - 8006b84: 681b ldr r3, [r3, #0] - 8006b86: f042 0220 orr.w r2, r2, #32 - 8006b8a: 611a str r2, [r3, #16] - } - - /* Return function status */ - return HAL_OK; - 8006b8c: 2300 movs r3, #0 - 8006b8e: e006 b.n 8006b9e - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8006b90: 68fb ldr r3, [r7, #12] - 8006b92: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006b94: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8006b98: 68fb ldr r3, [r7, #12] - 8006b9a: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006b9c: 2301 movs r3, #1 - } -} - 8006b9e: 4618 mov r0, r3 - 8006ba0: 371c adds r7, #28 - 8006ba2: 46bd mov sp, r7 - 8006ba4: bc80 pop {r7} - 8006ba6: 4770 bx lr - -08006ba8 : - * @param ActiveITs indicates which interrupts will be enabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) -{ - 8006ba8: b480 push {r7} - 8006baa: b085 sub sp, #20 - 8006bac: af00 add r7, sp, #0 - 8006bae: 6078 str r0, [r7, #4] - 8006bb0: 6039 str r1, [r7, #0] - HAL_CAN_StateTypeDef state = hcan->State; - 8006bb2: 687b ldr r3, [r7, #4] - 8006bb4: f893 3020 ldrb.w r3, [r3, #32] - 8006bb8: 73fb strb r3, [r7, #15] - - /* Check function parameters */ - assert_param(IS_CAN_IT(ActiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - 8006bba: 7bfb ldrb r3, [r7, #15] - 8006bbc: 2b01 cmp r3, #1 - 8006bbe: d002 beq.n 8006bc6 - 8006bc0: 7bfb ldrb r3, [r7, #15] - 8006bc2: 2b02 cmp r3, #2 - 8006bc4: d109 bne.n 8006bda - (state == HAL_CAN_STATE_LISTENING)) - { - /* Enable the selected interrupts */ - __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - 8006bc6: 687b ldr r3, [r7, #4] - 8006bc8: 681b ldr r3, [r3, #0] - 8006bca: 6959 ldr r1, [r3, #20] - 8006bcc: 687b ldr r3, [r7, #4] - 8006bce: 681b ldr r3, [r3, #0] - 8006bd0: 683a ldr r2, [r7, #0] - 8006bd2: 430a orrs r2, r1 - 8006bd4: 615a str r2, [r3, #20] - - /* Return function status */ - return HAL_OK; - 8006bd6: 2300 movs r3, #0 - 8006bd8: e006 b.n 8006be8 - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - 8006bda: 687b ldr r3, [r7, #4] - 8006bdc: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006bde: f443 2280 orr.w r2, r3, #262144 @ 0x40000 - 8006be2: 687b ldr r3, [r7, #4] - 8006be4: 625a str r2, [r3, #36] @ 0x24 - - return HAL_ERROR; - 8006be6: 2301 movs r3, #1 - } -} - 8006be8: 4618 mov r0, r3 - 8006bea: 3714 adds r7, #20 - 8006bec: 46bd mov sp, r7 - 8006bee: bc80 pop {r7} - 8006bf0: 4770 bx lr - -08006bf2 : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) -{ - 8006bf2: b580 push {r7, lr} - 8006bf4: b08a sub sp, #40 @ 0x28 - 8006bf6: af00 add r7, sp, #0 - 8006bf8: 6078 str r0, [r7, #4] - uint32_t errorcode = HAL_CAN_ERROR_NONE; - 8006bfa: 2300 movs r3, #0 - 8006bfc: 627b str r3, [r7, #36] @ 0x24 - uint32_t interrupts = READ_REG(hcan->Instance->IER); - 8006bfe: 687b ldr r3, [r7, #4] - 8006c00: 681b ldr r3, [r3, #0] - 8006c02: 695b ldr r3, [r3, #20] - 8006c04: 623b str r3, [r7, #32] - uint32_t msrflags = READ_REG(hcan->Instance->MSR); - 8006c06: 687b ldr r3, [r7, #4] - 8006c08: 681b ldr r3, [r3, #0] - 8006c0a: 685b ldr r3, [r3, #4] - 8006c0c: 61fb str r3, [r7, #28] - uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - 8006c0e: 687b ldr r3, [r7, #4] - 8006c10: 681b ldr r3, [r3, #0] - 8006c12: 689b ldr r3, [r3, #8] - 8006c14: 61bb str r3, [r7, #24] - uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - 8006c16: 687b ldr r3, [r7, #4] - 8006c18: 681b ldr r3, [r3, #0] - 8006c1a: 68db ldr r3, [r3, #12] - 8006c1c: 617b str r3, [r7, #20] - uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - 8006c1e: 687b ldr r3, [r7, #4] - 8006c20: 681b ldr r3, [r3, #0] - 8006c22: 691b ldr r3, [r3, #16] - 8006c24: 613b str r3, [r7, #16] - uint32_t esrflags = READ_REG(hcan->Instance->ESR); - 8006c26: 687b ldr r3, [r7, #4] - 8006c28: 681b ldr r3, [r3, #0] - 8006c2a: 699b ldr r3, [r3, #24] - 8006c2c: 60fb str r3, [r7, #12] - - /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - 8006c2e: 6a3b ldr r3, [r7, #32] - 8006c30: f003 0301 and.w r3, r3, #1 - 8006c34: 2b00 cmp r3, #0 - 8006c36: d07c beq.n 8006d32 - { - /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != 0U) - 8006c38: 69bb ldr r3, [r7, #24] - 8006c3a: f003 0301 and.w r3, r3, #1 - 8006c3e: 2b00 cmp r3, #0 - 8006c40: d023 beq.n 8006c8a - { - /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - 8006c42: 687b ldr r3, [r7, #4] - 8006c44: 681b ldr r3, [r3, #0] - 8006c46: 2201 movs r2, #1 - 8006c48: 609a str r2, [r3, #8] - - if ((tsrflags & CAN_TSR_TXOK0) != 0U) - 8006c4a: 69bb ldr r3, [r7, #24] - 8006c4c: f003 0302 and.w r3, r3, #2 - 8006c50: 2b00 cmp r3, #0 - 8006c52: d003 beq.n 8006c5c -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0CompleteCallback(hcan); - 8006c54: 6878 ldr r0, [r7, #4] - 8006c56: f7fd fb4b bl 80042f0 - 8006c5a: e016 b.n 8006c8a -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST0) != 0U) - 8006c5c: 69bb ldr r3, [r7, #24] - 8006c5e: f003 0304 and.w r3, r3, #4 - 8006c62: 2b00 cmp r3, #0 - 8006c64: d004 beq.n 8006c70 - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST0; - 8006c66: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006c68: f443 6300 orr.w r3, r3, #2048 @ 0x800 - 8006c6c: 627b str r3, [r7, #36] @ 0x24 - 8006c6e: e00c b.n 8006c8a - } - else if ((tsrflags & CAN_TSR_TERR0) != 0U) - 8006c70: 69bb ldr r3, [r7, #24] - 8006c72: f003 0308 and.w r3, r3, #8 - 8006c76: 2b00 cmp r3, #0 - 8006c78: d004 beq.n 8006c84 - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR0; - 8006c7a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006c7c: f443 5380 orr.w r3, r3, #4096 @ 0x1000 - 8006c80: 627b str r3, [r7, #36] @ 0x24 - 8006c82: e002 b.n 8006c8a -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0AbortCallback(hcan); - 8006c84: 6878 ldr r0, [r7, #4] - 8006c86: f000 f96b bl 8006f60 - } - } - } - - /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != 0U) - 8006c8a: 69bb ldr r3, [r7, #24] - 8006c8c: f403 7380 and.w r3, r3, #256 @ 0x100 - 8006c90: 2b00 cmp r3, #0 - 8006c92: d024 beq.n 8006cde - { - /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - 8006c94: 687b ldr r3, [r7, #4] - 8006c96: 681b ldr r3, [r3, #0] - 8006c98: f44f 7280 mov.w r2, #256 @ 0x100 - 8006c9c: 609a str r2, [r3, #8] - - if ((tsrflags & CAN_TSR_TXOK1) != 0U) - 8006c9e: 69bb ldr r3, [r7, #24] - 8006ca0: f403 7300 and.w r3, r3, #512 @ 0x200 - 8006ca4: 2b00 cmp r3, #0 - 8006ca6: d003 beq.n 8006cb0 -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1CompleteCallback(hcan); - 8006ca8: 6878 ldr r0, [r7, #4] - 8006caa: f7fd fb3b bl 8004324 - 8006cae: e016 b.n 8006cde -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST1) != 0U) - 8006cb0: 69bb ldr r3, [r7, #24] - 8006cb2: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8006cb6: 2b00 cmp r3, #0 - 8006cb8: d004 beq.n 8006cc4 - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST1; - 8006cba: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006cbc: f443 5300 orr.w r3, r3, #8192 @ 0x2000 - 8006cc0: 627b str r3, [r7, #36] @ 0x24 - 8006cc2: e00c b.n 8006cde - } - else if ((tsrflags & CAN_TSR_TERR1) != 0U) - 8006cc4: 69bb ldr r3, [r7, #24] - 8006cc6: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8006cca: 2b00 cmp r3, #0 - 8006ccc: d004 beq.n 8006cd8 - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR1; - 8006cce: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006cd0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 8006cd4: 627b str r3, [r7, #36] @ 0x24 - 8006cd6: e002 b.n 8006cde -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1AbortCallback(hcan); - 8006cd8: 6878 ldr r0, [r7, #4] - 8006cda: f000 f94a bl 8006f72 - } - } - } - - /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != 0U) - 8006cde: 69bb ldr r3, [r7, #24] - 8006ce0: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8006ce4: 2b00 cmp r3, #0 - 8006ce6: d024 beq.n 8006d32 - { - /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - 8006ce8: 687b ldr r3, [r7, #4] - 8006cea: 681b ldr r3, [r3, #0] - 8006cec: f44f 3280 mov.w r2, #65536 @ 0x10000 - 8006cf0: 609a str r2, [r3, #8] - - if ((tsrflags & CAN_TSR_TXOK2) != 0U) - 8006cf2: 69bb ldr r3, [r7, #24] - 8006cf4: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8006cf8: 2b00 cmp r3, #0 - 8006cfa: d003 beq.n 8006d04 -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2CompleteCallback(hcan); - 8006cfc: 6878 ldr r0, [r7, #4] - 8006cfe: f7fd fb2b bl 8004358 - 8006d02: e016 b.n 8006d32 -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST2) != 0U) - 8006d04: 69bb ldr r3, [r7, #24] - 8006d06: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8006d0a: 2b00 cmp r3, #0 - 8006d0c: d004 beq.n 8006d18 - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST2; - 8006d0e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006d10: f443 4300 orr.w r3, r3, #32768 @ 0x8000 - 8006d14: 627b str r3, [r7, #36] @ 0x24 - 8006d16: e00c b.n 8006d32 - } - else if ((tsrflags & CAN_TSR_TERR2) != 0U) - 8006d18: 69bb ldr r3, [r7, #24] - 8006d1a: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8006d1e: 2b00 cmp r3, #0 - 8006d20: d004 beq.n 8006d2c - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR2; - 8006d22: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006d24: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8006d28: 627b str r3, [r7, #36] @ 0x24 - 8006d2a: e002 b.n 8006d32 -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2AbortCallback(hcan); - 8006d2c: 6878 ldr r0, [r7, #4] - 8006d2e: f000 f929 bl 8006f84 - } - } - } - - /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - 8006d32: 6a3b ldr r3, [r7, #32] - 8006d34: f003 0308 and.w r3, r3, #8 - 8006d38: 2b00 cmp r3, #0 - 8006d3a: d00c beq.n 8006d56 - { - if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - 8006d3c: 697b ldr r3, [r7, #20] - 8006d3e: f003 0310 and.w r3, r3, #16 - 8006d42: 2b00 cmp r3, #0 - 8006d44: d007 beq.n 8006d56 - { - /* Set CAN error code to Rx Fifo 0 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV0; - 8006d46: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006d48: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8006d4c: 627b str r3, [r7, #36] @ 0x24 - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - 8006d4e: 687b ldr r3, [r7, #4] - 8006d50: 681b ldr r3, [r3, #0] - 8006d52: 2210 movs r2, #16 - 8006d54: 60da str r2, [r3, #12] - } - } - - /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - 8006d56: 6a3b ldr r3, [r7, #32] - 8006d58: f003 0304 and.w r3, r3, #4 - 8006d5c: 2b00 cmp r3, #0 - 8006d5e: d00b beq.n 8006d78 - { - if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - 8006d60: 697b ldr r3, [r7, #20] - 8006d62: f003 0308 and.w r3, r3, #8 - 8006d66: 2b00 cmp r3, #0 - 8006d68: d006 beq.n 8006d78 - { - /* Clear FIFO 0 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - 8006d6a: 687b ldr r3, [r7, #4] - 8006d6c: 681b ldr r3, [r3, #0] - 8006d6e: 2208 movs r2, #8 - 8006d70: 60da str r2, [r3, #12] -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0FullCallback(hcan); - 8006d72: 6878 ldr r0, [r7, #4] - 8006d74: f000 f90f bl 8006f96 -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - 8006d78: 6a3b ldr r3, [r7, #32] - 8006d7a: f003 0302 and.w r3, r3, #2 - 8006d7e: 2b00 cmp r3, #0 - 8006d80: d009 beq.n 8006d96 - { - /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - 8006d82: 687b ldr r3, [r7, #4] - 8006d84: 681b ldr r3, [r3, #0] - 8006d86: 68db ldr r3, [r3, #12] - 8006d88: f003 0303 and.w r3, r3, #3 - 8006d8c: 2b00 cmp r3, #0 - 8006d8e: d002 beq.n 8006d96 -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0MsgPendingCallback(hcan); - 8006d90: 6878 ldr r0, [r7, #4] - 8006d92: f7fc ff0d bl 8003bb0 -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - 8006d96: 6a3b ldr r3, [r7, #32] - 8006d98: f003 0340 and.w r3, r3, #64 @ 0x40 - 8006d9c: 2b00 cmp r3, #0 - 8006d9e: d00c beq.n 8006dba - { - if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - 8006da0: 693b ldr r3, [r7, #16] - 8006da2: f003 0310 and.w r3, r3, #16 - 8006da6: 2b00 cmp r3, #0 - 8006da8: d007 beq.n 8006dba - { - /* Set CAN error code to Rx Fifo 1 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV1; - 8006daa: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006dac: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 8006db0: 627b str r3, [r7, #36] @ 0x24 - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - 8006db2: 687b ldr r3, [r7, #4] - 8006db4: 681b ldr r3, [r3, #0] - 8006db6: 2210 movs r2, #16 - 8006db8: 611a str r2, [r3, #16] - } - } - - /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - 8006dba: 6a3b ldr r3, [r7, #32] - 8006dbc: f003 0320 and.w r3, r3, #32 - 8006dc0: 2b00 cmp r3, #0 - 8006dc2: d00b beq.n 8006ddc - { - if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - 8006dc4: 693b ldr r3, [r7, #16] - 8006dc6: f003 0308 and.w r3, r3, #8 - 8006dca: 2b00 cmp r3, #0 - 8006dcc: d006 beq.n 8006ddc - { - /* Clear FIFO 1 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - 8006dce: 687b ldr r3, [r7, #4] - 8006dd0: 681b ldr r3, [r3, #0] - 8006dd2: 2208 movs r2, #8 - 8006dd4: 611a str r2, [r3, #16] -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1FullCallback(hcan); - 8006dd6: 6878 ldr r0, [r7, #4] - 8006dd8: f000 f8e6 bl 8006fa8 -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - 8006ddc: 6a3b ldr r3, [r7, #32] - 8006dde: f003 0310 and.w r3, r3, #16 - 8006de2: 2b00 cmp r3, #0 - 8006de4: d009 beq.n 8006dfa - { - /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - 8006de6: 687b ldr r3, [r7, #4] - 8006de8: 681b ldr r3, [r3, #0] - 8006dea: 691b ldr r3, [r3, #16] - 8006dec: f003 0303 and.w r3, r3, #3 - 8006df0: 2b00 cmp r3, #0 - 8006df2: d002 beq.n 8006dfa -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1MsgPendingCallback(hcan); - 8006df4: 6878 ldr r0, [r7, #4] - 8006df6: f7fd fa25 bl 8004244 -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - 8006dfa: 6a3b ldr r3, [r7, #32] - 8006dfc: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8006e00: 2b00 cmp r3, #0 - 8006e02: d00b beq.n 8006e1c - { - if ((msrflags & CAN_MSR_SLAKI) != 0U) - 8006e04: 69fb ldr r3, [r7, #28] - 8006e06: f003 0310 and.w r3, r3, #16 - 8006e0a: 2b00 cmp r3, #0 - 8006e0c: d006 beq.n 8006e1c - { - /* Clear Sleep interrupt Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - 8006e0e: 687b ldr r3, [r7, #4] - 8006e10: 681b ldr r3, [r3, #0] - 8006e12: 2210 movs r2, #16 - 8006e14: 605a str r2, [r3, #4] -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->SleepCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_SleepCallback(hcan); - 8006e16: 6878 ldr r0, [r7, #4] - 8006e18: f000 f8cf bl 8006fba -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != 0U) - 8006e1c: 6a3b ldr r3, [r7, #32] - 8006e1e: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8006e22: 2b00 cmp r3, #0 - 8006e24: d00b beq.n 8006e3e - { - if ((msrflags & CAN_MSR_WKUI) != 0U) - 8006e26: 69fb ldr r3, [r7, #28] - 8006e28: f003 0308 and.w r3, r3, #8 - 8006e2c: 2b00 cmp r3, #0 - 8006e2e: d006 beq.n 8006e3e - { - /* Clear WakeUp Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - 8006e30: 687b ldr r3, [r7, #4] - 8006e32: 681b ldr r3, [r3, #0] - 8006e34: 2208 movs r2, #8 - 8006e36: 605a str r2, [r3, #4] -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->WakeUpFromRxMsgCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_WakeUpFromRxMsgCallback(hcan); - 8006e38: 6878 ldr r0, [r7, #4] - 8006e3a: f000 f8c7 bl 8006fcc -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != 0U) - 8006e3e: 6a3b ldr r3, [r7, #32] - 8006e40: f403 4300 and.w r3, r3, #32768 @ 0x8000 - 8006e44: 2b00 cmp r3, #0 - 8006e46: d07b beq.n 8006f40 - { - if ((msrflags & CAN_MSR_ERRI) != 0U) - 8006e48: 69fb ldr r3, [r7, #28] - 8006e4a: f003 0304 and.w r3, r3, #4 - 8006e4e: 2b00 cmp r3, #0 - 8006e50: d072 beq.n 8006f38 - { - /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 8006e52: 6a3b ldr r3, [r7, #32] - 8006e54: f403 7380 and.w r3, r3, #256 @ 0x100 - 8006e58: 2b00 cmp r3, #0 - 8006e5a: d008 beq.n 8006e6e - ((esrflags & CAN_ESR_EWGF) != 0U)) - 8006e5c: 68fb ldr r3, [r7, #12] - 8006e5e: f003 0301 and.w r3, r3, #1 - if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - 8006e62: 2b00 cmp r3, #0 - 8006e64: d003 beq.n 8006e6e - { - /* Set CAN error code to Error Warning */ - errorcode |= HAL_CAN_ERROR_EWG; - 8006e66: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006e68: f043 0301 orr.w r3, r3, #1 - 8006e6c: 627b str r3, [r7, #36] @ 0x24 - - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8006e6e: 6a3b ldr r3, [r7, #32] - 8006e70: f403 7300 and.w r3, r3, #512 @ 0x200 - 8006e74: 2b00 cmp r3, #0 - 8006e76: d008 beq.n 8006e8a - ((esrflags & CAN_ESR_EPVF) != 0U)) - 8006e78: 68fb ldr r3, [r7, #12] - 8006e7a: f003 0302 and.w r3, r3, #2 - if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - 8006e7e: 2b00 cmp r3, #0 - 8006e80: d003 beq.n 8006e8a - { - /* Set CAN error code to Error Passive */ - errorcode |= HAL_CAN_ERROR_EPV; - 8006e82: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006e84: f043 0302 orr.w r3, r3, #2 - 8006e88: 627b str r3, [r7, #36] @ 0x24 - - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8006e8a: 6a3b ldr r3, [r7, #32] - 8006e8c: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8006e90: 2b00 cmp r3, #0 - 8006e92: d008 beq.n 8006ea6 - ((esrflags & CAN_ESR_BOFF) != 0U)) - 8006e94: 68fb ldr r3, [r7, #12] - 8006e96: f003 0304 and.w r3, r3, #4 - if (((interrupts & CAN_IT_BUSOFF) != 0U) && - 8006e9a: 2b00 cmp r3, #0 - 8006e9c: d003 beq.n 8006ea6 - { - /* Set CAN error code to Bus-Off */ - errorcode |= HAL_CAN_ERROR_BOF; - 8006e9e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006ea0: f043 0304 orr.w r3, r3, #4 - 8006ea4: 627b str r3, [r7, #36] @ 0x24 - - /* No need for clear of Error Bus-Off as read-only */ - } - - /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 8006ea6: 6a3b ldr r3, [r7, #32] - 8006ea8: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8006eac: 2b00 cmp r3, #0 - 8006eae: d043 beq.n 8006f38 - ((esrflags & CAN_ESR_LEC) != 0U)) - 8006eb0: 68fb ldr r3, [r7, #12] - 8006eb2: f003 0370 and.w r3, r3, #112 @ 0x70 - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - 8006eb6: 2b00 cmp r3, #0 - 8006eb8: d03e beq.n 8006f38 - { - switch (esrflags & CAN_ESR_LEC) - 8006eba: 68fb ldr r3, [r7, #12] - 8006ebc: f003 0370 and.w r3, r3, #112 @ 0x70 - 8006ec0: 2b60 cmp r3, #96 @ 0x60 - 8006ec2: d02b beq.n 8006f1c - 8006ec4: 2b60 cmp r3, #96 @ 0x60 - 8006ec6: d82e bhi.n 8006f26 - 8006ec8: 2b50 cmp r3, #80 @ 0x50 - 8006eca: d022 beq.n 8006f12 - 8006ecc: 2b50 cmp r3, #80 @ 0x50 - 8006ece: d82a bhi.n 8006f26 - 8006ed0: 2b40 cmp r3, #64 @ 0x40 - 8006ed2: d019 beq.n 8006f08 - 8006ed4: 2b40 cmp r3, #64 @ 0x40 - 8006ed6: d826 bhi.n 8006f26 - 8006ed8: 2b30 cmp r3, #48 @ 0x30 - 8006eda: d010 beq.n 8006efe - 8006edc: 2b30 cmp r3, #48 @ 0x30 - 8006ede: d822 bhi.n 8006f26 - 8006ee0: 2b10 cmp r3, #16 - 8006ee2: d002 beq.n 8006eea - 8006ee4: 2b20 cmp r3, #32 - 8006ee6: d005 beq.n 8006ef4 - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - errorcode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - 8006ee8: e01d b.n 8006f26 - errorcode |= HAL_CAN_ERROR_STF; - 8006eea: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006eec: f043 0308 orr.w r3, r3, #8 - 8006ef0: 627b str r3, [r7, #36] @ 0x24 - break; - 8006ef2: e019 b.n 8006f28 - errorcode |= HAL_CAN_ERROR_FOR; - 8006ef4: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006ef6: f043 0310 orr.w r3, r3, #16 - 8006efa: 627b str r3, [r7, #36] @ 0x24 - break; - 8006efc: e014 b.n 8006f28 - errorcode |= HAL_CAN_ERROR_ACK; - 8006efe: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f00: f043 0320 orr.w r3, r3, #32 - 8006f04: 627b str r3, [r7, #36] @ 0x24 - break; - 8006f06: e00f b.n 8006f28 - errorcode |= HAL_CAN_ERROR_BR; - 8006f08: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f0a: f043 0340 orr.w r3, r3, #64 @ 0x40 - 8006f0e: 627b str r3, [r7, #36] @ 0x24 - break; - 8006f10: e00a b.n 8006f28 - errorcode |= HAL_CAN_ERROR_BD; - 8006f12: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f14: f043 0380 orr.w r3, r3, #128 @ 0x80 - 8006f18: 627b str r3, [r7, #36] @ 0x24 - break; - 8006f1a: e005 b.n 8006f28 - errorcode |= HAL_CAN_ERROR_CRC; - 8006f1c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f1e: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8006f22: 627b str r3, [r7, #36] @ 0x24 - break; - 8006f24: e000 b.n 8006f28 - break; - 8006f26: bf00 nop - } - - /* Clear Last error code Flag */ - CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - 8006f28: 687b ldr r3, [r7, #4] - 8006f2a: 681b ldr r3, [r3, #0] - 8006f2c: 699a ldr r2, [r3, #24] - 8006f2e: 687b ldr r3, [r7, #4] - 8006f30: 681b ldr r3, [r3, #0] - 8006f32: f022 0270 bic.w r2, r2, #112 @ 0x70 - 8006f36: 619a str r2, [r3, #24] - } - } - - /* Clear ERRI Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - 8006f38: 687b ldr r3, [r7, #4] - 8006f3a: 681b ldr r3, [r3, #0] - 8006f3c: 2204 movs r2, #4 - 8006f3e: 605a str r2, [r3, #4] - } - - /* Call the Error call Back in case of Errors */ - if (errorcode != HAL_CAN_ERROR_NONE) - 8006f40: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f42: 2b00 cmp r3, #0 - 8006f44: d008 beq.n 8006f58 - { - /* Update error code in handle */ - hcan->ErrorCode |= errorcode; - 8006f46: 687b ldr r3, [r7, #4] - 8006f48: 6a5a ldr r2, [r3, #36] @ 0x24 - 8006f4a: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006f4c: 431a orrs r2, r3 - 8006f4e: 687b ldr r3, [r7, #4] - 8006f50: 625a str r2, [r3, #36] @ 0x24 -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->ErrorCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_ErrorCallback(hcan); - 8006f52: 6878 ldr r0, [r7, #4] - 8006f54: f000 f843 bl 8006fde -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } -} - 8006f58: bf00 nop - 8006f5a: 3728 adds r7, #40 @ 0x28 - 8006f5c: 46bd mov sp, r7 - 8006f5e: bd80 pop {r7, pc} - -08006f60 : - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) -{ - 8006f60: b480 push {r7} - 8006f62: b083 sub sp, #12 - 8006f64: af00 add r7, sp, #0 - 8006f66: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0AbortCallback could be implemented in the - user file - */ -} - 8006f68: bf00 nop - 8006f6a: 370c adds r7, #12 - 8006f6c: 46bd mov sp, r7 - 8006f6e: bc80 pop {r7} - 8006f70: 4770 bx lr - -08006f72 : - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) -{ - 8006f72: b480 push {r7} - 8006f74: b083 sub sp, #12 - 8006f76: af00 add r7, sp, #0 - 8006f78: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1AbortCallback could be implemented in the - user file - */ -} - 8006f7a: bf00 nop - 8006f7c: 370c adds r7, #12 - 8006f7e: 46bd mov sp, r7 - 8006f80: bc80 pop {r7} - 8006f82: 4770 bx lr - -08006f84 : - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) -{ - 8006f84: b480 push {r7} - 8006f86: b083 sub sp, #12 - 8006f88: af00 add r7, sp, #0 - 8006f8a: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2AbortCallback could be implemented in the - user file - */ -} - 8006f8c: bf00 nop - 8006f8e: 370c adds r7, #12 - 8006f90: 46bd mov sp, r7 - 8006f92: bc80 pop {r7} - 8006f94: 4770 bx lr - -08006f96 : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) -{ - 8006f96: b480 push {r7} - 8006f98: b083 sub sp, #12 - 8006f9a: af00 add r7, sp, #0 - 8006f9c: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0FullCallback could be implemented in the user - file - */ -} - 8006f9e: bf00 nop - 8006fa0: 370c adds r7, #12 - 8006fa2: 46bd mov sp, r7 - 8006fa4: bc80 pop {r7} - 8006fa6: 4770 bx lr - -08006fa8 : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) -{ - 8006fa8: b480 push {r7} - 8006faa: b083 sub sp, #12 - 8006fac: af00 add r7, sp, #0 - 8006fae: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1FullCallback could be implemented in the user - file - */ -} - 8006fb0: bf00 nop - 8006fb2: 370c adds r7, #12 - 8006fb4: 46bd mov sp, r7 - 8006fb6: bc80 pop {r7} - 8006fb8: 4770 bx lr - -08006fba : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) -{ - 8006fba: b480 push {r7} - 8006fbc: b083 sub sp, #12 - 8006fbe: af00 add r7, sp, #0 - 8006fc0: 6078 str r0, [r7, #4] - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_SleepCallback could be implemented in the user file - */ -} - 8006fc2: bf00 nop - 8006fc4: 370c adds r7, #12 - 8006fc6: 46bd mov sp, r7 - 8006fc8: bc80 pop {r7} - 8006fca: 4770 bx lr - -08006fcc : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) -{ - 8006fcc: b480 push {r7} - 8006fce: b083 sub sp, #12 - 8006fd0: af00 add r7, sp, #0 - 8006fd2: 6078 str r0, [r7, #4] - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the - user file - */ -} - 8006fd4: bf00 nop - 8006fd6: 370c adds r7, #12 - 8006fd8: 46bd mov sp, r7 - 8006fda: bc80 pop {r7} - 8006fdc: 4770 bx lr - -08006fde : - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) -{ - 8006fde: b480 push {r7} - 8006fe0: b083 sub sp, #12 - 8006fe2: af00 add r7, sp, #0 - 8006fe4: 6078 str r0, [r7, #4] - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_ErrorCallback could be implemented in the user file - */ -} - 8006fe6: bf00 nop - 8006fe8: 370c adds r7, #12 - 8006fea: 46bd mov sp, r7 - 8006fec: bc80 pop {r7} - 8006fee: 4770 bx lr - -08006ff0 <__NVIC_SetPriorityGrouping>: -{ - 8006ff0: b480 push {r7} - 8006ff2: b085 sub sp, #20 - 8006ff4: af00 add r7, sp, #0 - 8006ff6: 6078 str r0, [r7, #4] - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8006ff8: 687b ldr r3, [r7, #4] - 8006ffa: f003 0307 and.w r3, r3, #7 - 8006ffe: 60fb str r3, [r7, #12] - reg_value = SCB->AIRCR; /* read old register configuration */ - 8007000: 4b0c ldr r3, [pc, #48] @ (8007034 <__NVIC_SetPriorityGrouping+0x44>) - 8007002: 68db ldr r3, [r3, #12] - 8007004: 60bb str r3, [r7, #8] - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8007006: 68ba ldr r2, [r7, #8] - 8007008: f64f 03ff movw r3, #63743 @ 0xf8ff - 800700c: 4013 ands r3, r2 - 800700e: 60bb str r3, [r7, #8] - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8007010: 68fb ldr r3, [r7, #12] - 8007012: 021a lsls r2, r3, #8 - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8007014: 68bb ldr r3, [r7, #8] - 8007016: 4313 orrs r3, r2 - reg_value = (reg_value | - 8007018: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 800701c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8007020: 60bb str r3, [r7, #8] - SCB->AIRCR = reg_value; - 8007022: 4a04 ldr r2, [pc, #16] @ (8007034 <__NVIC_SetPriorityGrouping+0x44>) - 8007024: 68bb ldr r3, [r7, #8] - 8007026: 60d3 str r3, [r2, #12] -} - 8007028: bf00 nop - 800702a: 3714 adds r7, #20 - 800702c: 46bd mov sp, r7 - 800702e: bc80 pop {r7} - 8007030: 4770 bx lr - 8007032: bf00 nop - 8007034: e000ed00 .word 0xe000ed00 - -08007038 <__NVIC_GetPriorityGrouping>: -{ - 8007038: b480 push {r7} - 800703a: af00 add r7, sp, #0 - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 800703c: 4b04 ldr r3, [pc, #16] @ (8007050 <__NVIC_GetPriorityGrouping+0x18>) - 800703e: 68db ldr r3, [r3, #12] - 8007040: 0a1b lsrs r3, r3, #8 - 8007042: f003 0307 and.w r3, r3, #7 -} - 8007046: 4618 mov r0, r3 - 8007048: 46bd mov sp, r7 - 800704a: bc80 pop {r7} - 800704c: 4770 bx lr - 800704e: bf00 nop - 8007050: e000ed00 .word 0xe000ed00 - -08007054 <__NVIC_EnableIRQ>: -{ - 8007054: b480 push {r7} - 8007056: b083 sub sp, #12 - 8007058: af00 add r7, sp, #0 - 800705a: 4603 mov r3, r0 - 800705c: 71fb strb r3, [r7, #7] - if ((int32_t)(IRQn) >= 0) - 800705e: f997 3007 ldrsb.w r3, [r7, #7] - 8007062: 2b00 cmp r3, #0 - 8007064: db0b blt.n 800707e <__NVIC_EnableIRQ+0x2a> - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8007066: 79fb ldrb r3, [r7, #7] - 8007068: f003 021f and.w r2, r3, #31 - 800706c: 4906 ldr r1, [pc, #24] @ (8007088 <__NVIC_EnableIRQ+0x34>) - 800706e: f997 3007 ldrsb.w r3, [r7, #7] - 8007072: 095b lsrs r3, r3, #5 - 8007074: 2001 movs r0, #1 - 8007076: fa00 f202 lsl.w r2, r0, r2 - 800707a: f841 2023 str.w r2, [r1, r3, lsl #2] -} - 800707e: bf00 nop - 8007080: 370c adds r7, #12 - 8007082: 46bd mov sp, r7 - 8007084: bc80 pop {r7} - 8007086: 4770 bx lr - 8007088: e000e100 .word 0xe000e100 - -0800708c <__NVIC_SetPriority>: -{ - 800708c: b480 push {r7} - 800708e: b083 sub sp, #12 - 8007090: af00 add r7, sp, #0 - 8007092: 4603 mov r3, r0 - 8007094: 6039 str r1, [r7, #0] - 8007096: 71fb strb r3, [r7, #7] - if ((int32_t)(IRQn) >= 0) - 8007098: f997 3007 ldrsb.w r3, [r7, #7] - 800709c: 2b00 cmp r3, #0 - 800709e: db0a blt.n 80070b6 <__NVIC_SetPriority+0x2a> - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80070a0: 683b ldr r3, [r7, #0] - 80070a2: b2da uxtb r2, r3 - 80070a4: 490c ldr r1, [pc, #48] @ (80070d8 <__NVIC_SetPriority+0x4c>) - 80070a6: f997 3007 ldrsb.w r3, [r7, #7] - 80070aa: 0112 lsls r2, r2, #4 - 80070ac: b2d2 uxtb r2, r2 - 80070ae: 440b add r3, r1 - 80070b0: f883 2300 strb.w r2, [r3, #768] @ 0x300 -} - 80070b4: e00a b.n 80070cc <__NVIC_SetPriority+0x40> - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80070b6: 683b ldr r3, [r7, #0] - 80070b8: b2da uxtb r2, r3 - 80070ba: 4908 ldr r1, [pc, #32] @ (80070dc <__NVIC_SetPriority+0x50>) - 80070bc: 79fb ldrb r3, [r7, #7] - 80070be: f003 030f and.w r3, r3, #15 - 80070c2: 3b04 subs r3, #4 - 80070c4: 0112 lsls r2, r2, #4 - 80070c6: b2d2 uxtb r2, r2 - 80070c8: 440b add r3, r1 - 80070ca: 761a strb r2, [r3, #24] -} - 80070cc: bf00 nop - 80070ce: 370c adds r7, #12 - 80070d0: 46bd mov sp, r7 - 80070d2: bc80 pop {r7} - 80070d4: 4770 bx lr - 80070d6: bf00 nop - 80070d8: e000e100 .word 0xe000e100 - 80070dc: e000ed00 .word 0xe000ed00 - -080070e0 : -{ - 80070e0: b480 push {r7} - 80070e2: b089 sub sp, #36 @ 0x24 - 80070e4: af00 add r7, sp, #0 - 80070e6: 60f8 str r0, [r7, #12] - 80070e8: 60b9 str r1, [r7, #8] - 80070ea: 607a str r2, [r7, #4] - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 80070ec: 68fb ldr r3, [r7, #12] - 80070ee: f003 0307 and.w r3, r3, #7 - 80070f2: 61fb str r3, [r7, #28] - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 80070f4: 69fb ldr r3, [r7, #28] - 80070f6: f1c3 0307 rsb r3, r3, #7 - 80070fa: 2b04 cmp r3, #4 - 80070fc: bf28 it cs - 80070fe: 2304 movcs r3, #4 - 8007100: 61bb str r3, [r7, #24] - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8007102: 69fb ldr r3, [r7, #28] - 8007104: 3304 adds r3, #4 - 8007106: 2b06 cmp r3, #6 - 8007108: d902 bls.n 8007110 - 800710a: 69fb ldr r3, [r7, #28] - 800710c: 3b03 subs r3, #3 - 800710e: e000 b.n 8007112 - 8007110: 2300 movs r3, #0 - 8007112: 617b str r3, [r7, #20] - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8007114: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 8007118: 69bb ldr r3, [r7, #24] - 800711a: fa02 f303 lsl.w r3, r2, r3 - 800711e: 43da mvns r2, r3 - 8007120: 68bb ldr r3, [r7, #8] - 8007122: 401a ands r2, r3 - 8007124: 697b ldr r3, [r7, #20] - 8007126: 409a lsls r2, r3 - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8007128: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff - 800712c: 697b ldr r3, [r7, #20] - 800712e: fa01 f303 lsl.w r3, r1, r3 - 8007132: 43d9 mvns r1, r3 - 8007134: 687b ldr r3, [r7, #4] - 8007136: 400b ands r3, r1 - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8007138: 4313 orrs r3, r2 -} - 800713a: 4618 mov r0, r3 - 800713c: 3724 adds r7, #36 @ 0x24 - 800713e: 46bd mov sp, r7 - 8007140: bc80 pop {r7} - 8007142: 4770 bx lr - -08007144 : - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - 8007144: b580 push {r7, lr} - 8007146: b082 sub sp, #8 - 8007148: af00 add r7, sp, #0 - 800714a: 6078 str r0, [r7, #4] - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 800714c: 687b ldr r3, [r7, #4] - 800714e: 3b01 subs r3, #1 - 8007150: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 8007154: d301 bcc.n 800715a - { - return (1UL); /* Reload value impossible */ - 8007156: 2301 movs r3, #1 - 8007158: e00f b.n 800717a - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 800715a: 4a0a ldr r2, [pc, #40] @ (8007184 ) - 800715c: 687b ldr r3, [r7, #4] - 800715e: 3b01 subs r3, #1 - 8007160: 6053 str r3, [r2, #4] - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8007162: 210f movs r1, #15 - 8007164: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8007168: f7ff ff90 bl 800708c <__NVIC_SetPriority> - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 800716c: 4b05 ldr r3, [pc, #20] @ (8007184 ) - 800716e: 2200 movs r2, #0 - 8007170: 609a str r2, [r3, #8] - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8007172: 4b04 ldr r3, [pc, #16] @ (8007184 ) - 8007174: 2207 movs r2, #7 - 8007176: 601a str r2, [r3, #0] - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ - 8007178: 2300 movs r3, #0 -} - 800717a: 4618 mov r0, r3 - 800717c: 3708 adds r7, #8 - 800717e: 46bd mov sp, r7 - 8007180: bd80 pop {r7, pc} - 8007182: bf00 nop - 8007184: e000e010 .word 0xe000e010 - -08007188 : - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - 8007188: b580 push {r7, lr} - 800718a: b082 sub sp, #8 - 800718c: af00 add r7, sp, #0 - 800718e: 6078 str r0, [r7, #4] - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); - 8007190: 6878 ldr r0, [r7, #4] - 8007192: f7ff ff2d bl 8006ff0 <__NVIC_SetPriorityGrouping> -} - 8007196: bf00 nop - 8007198: 3708 adds r7, #8 - 800719a: 46bd mov sp, r7 - 800719c: bd80 pop {r7, pc} - -0800719e : - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - 800719e: b580 push {r7, lr} - 80071a0: b086 sub sp, #24 - 80071a2: af00 add r7, sp, #0 - 80071a4: 4603 mov r3, r0 - 80071a6: 60b9 str r1, [r7, #8] - 80071a8: 607a str r2, [r7, #4] - 80071aa: 73fb strb r3, [r7, #15] - uint32_t prioritygroup = 0x00U; - 80071ac: 2300 movs r3, #0 - 80071ae: 617b str r3, [r7, #20] - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - 80071b0: f7ff ff42 bl 8007038 <__NVIC_GetPriorityGrouping> - 80071b4: 6178 str r0, [r7, #20] - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 80071b6: 687a ldr r2, [r7, #4] - 80071b8: 68b9 ldr r1, [r7, #8] - 80071ba: 6978 ldr r0, [r7, #20] - 80071bc: f7ff ff90 bl 80070e0 - 80071c0: 4602 mov r2, r0 - 80071c2: f997 300f ldrsb.w r3, [r7, #15] - 80071c6: 4611 mov r1, r2 - 80071c8: 4618 mov r0, r3 - 80071ca: f7ff ff5f bl 800708c <__NVIC_SetPriority> -} - 80071ce: bf00 nop - 80071d0: 3718 adds r7, #24 - 80071d2: 46bd mov sp, r7 - 80071d4: bd80 pop {r7, pc} - -080071d6 : - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - 80071d6: b580 push {r7, lr} - 80071d8: b082 sub sp, #8 - 80071da: af00 add r7, sp, #0 - 80071dc: 4603 mov r3, r0 - 80071de: 71fb strb r3, [r7, #7] - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); - 80071e0: f997 3007 ldrsb.w r3, [r7, #7] - 80071e4: 4618 mov r0, r3 - 80071e6: f7ff ff35 bl 8007054 <__NVIC_EnableIRQ> -} - 80071ea: bf00 nop - 80071ec: 3708 adds r7, #8 - 80071ee: 46bd mov sp, r7 - 80071f0: bd80 pop {r7, pc} - -080071f2 : - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - 80071f2: b580 push {r7, lr} - 80071f4: b082 sub sp, #8 - 80071f6: af00 add r7, sp, #0 - 80071f8: 6078 str r0, [r7, #4] - return SysTick_Config(TicksNumb); - 80071fa: 6878 ldr r0, [r7, #4] - 80071fc: f7ff ffa2 bl 8007144 - 8007200: 4603 mov r3, r0 -} - 8007202: 4618 mov r0, r3 - 8007204: 3708 adds r7, #8 - 8007206: 46bd mov sp, r7 - 8007208: bd80 pop {r7, pc} - -0800720a : - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - 800720a: b480 push {r7} - 800720c: b085 sub sp, #20 - 800720e: af00 add r7, sp, #0 - 8007210: 6078 str r0, [r7, #4] - HAL_StatusTypeDef status = HAL_OK; - 8007212: 2300 movs r3, #0 - 8007214: 73fb strb r3, [r7, #15] - - if(hdma->State != HAL_DMA_STATE_BUSY) - 8007216: 687b ldr r3, [r7, #4] - 8007218: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 - 800721c: 2b02 cmp r3, #2 - 800721e: d008 beq.n 8007232 - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 8007220: 687b ldr r3, [r7, #4] - 8007222: 2204 movs r2, #4 - 8007224: 639a str r2, [r3, #56] @ 0x38 - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - 8007226: 687b ldr r3, [r7, #4] - 8007228: 2200 movs r2, #0 - 800722a: f883 2020 strb.w r2, [r3, #32] - - return HAL_ERROR; - 800722e: 2301 movs r3, #1 - 8007230: e020 b.n 8007274 - } - else - - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8007232: 687b ldr r3, [r7, #4] - 8007234: 681b ldr r3, [r3, #0] - 8007236: 681a ldr r2, [r3, #0] - 8007238: 687b ldr r3, [r7, #4] - 800723a: 681b ldr r3, [r3, #0] - 800723c: f022 020e bic.w r2, r2, #14 - 8007240: 601a str r2, [r3, #0] - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - 8007242: 687b ldr r3, [r7, #4] - 8007244: 681b ldr r3, [r3, #0] - 8007246: 681a ldr r2, [r3, #0] - 8007248: 687b ldr r3, [r7, #4] - 800724a: 681b ldr r3, [r3, #0] - 800724c: f022 0201 bic.w r2, r2, #1 - 8007250: 601a str r2, [r3, #0] - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - 8007252: 687b ldr r3, [r7, #4] - 8007254: 6c1a ldr r2, [r3, #64] @ 0x40 - 8007256: 687b ldr r3, [r7, #4] - 8007258: 6bdb ldr r3, [r3, #60] @ 0x3c - 800725a: 2101 movs r1, #1 - 800725c: fa01 f202 lsl.w r2, r1, r2 - 8007260: 605a str r2, [r3, #4] - } - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - 8007262: 687b ldr r3, [r7, #4] - 8007264: 2201 movs r2, #1 - 8007266: f883 2021 strb.w r2, [r3, #33] @ 0x21 - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - 800726a: 687b ldr r3, [r7, #4] - 800726c: 2200 movs r2, #0 - 800726e: f883 2020 strb.w r2, [r3, #32] - - return status; - 8007272: 7bfb ldrb r3, [r7, #15] -} - 8007274: 4618 mov r0, r3 - 8007276: 3714 adds r7, #20 - 8007278: 46bd mov sp, r7 - 800727a: bc80 pop {r7} - 800727c: 4770 bx lr - ... - -08007280 : - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - 8007280: b580 push {r7, lr} - 8007282: b084 sub sp, #16 - 8007284: af00 add r7, sp, #0 - 8007286: 6078 str r0, [r7, #4] - HAL_StatusTypeDef status = HAL_OK; - 8007288: 2300 movs r3, #0 - 800728a: 73fb strb r3, [r7, #15] - - if(HAL_DMA_STATE_BUSY != hdma->State) - 800728c: 687b ldr r3, [r7, #4] - 800728e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 - 8007292: 2b02 cmp r3, #2 - 8007294: d005 beq.n 80072a2 - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 8007296: 687b ldr r3, [r7, #4] - 8007298: 2204 movs r2, #4 - 800729a: 639a str r2, [r3, #56] @ 0x38 - - status = HAL_ERROR; - 800729c: 2301 movs r3, #1 - 800729e: 73fb strb r3, [r7, #15] - 80072a0: e0d6 b.n 8007450 - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 80072a2: 687b ldr r3, [r7, #4] - 80072a4: 681b ldr r3, [r3, #0] - 80072a6: 681a ldr r2, [r3, #0] - 80072a8: 687b ldr r3, [r7, #4] - 80072aa: 681b ldr r3, [r3, #0] - 80072ac: f022 020e bic.w r2, r2, #14 - 80072b0: 601a str r2, [r3, #0] - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - 80072b2: 687b ldr r3, [r7, #4] - 80072b4: 681b ldr r3, [r3, #0] - 80072b6: 681a ldr r2, [r3, #0] - 80072b8: 687b ldr r3, [r7, #4] - 80072ba: 681b ldr r3, [r3, #0] - 80072bc: f022 0201 bic.w r2, r2, #1 - 80072c0: 601a str r2, [r3, #0] - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); - 80072c2: 687b ldr r3, [r7, #4] - 80072c4: 681b ldr r3, [r3, #0] - 80072c6: 461a mov r2, r3 - 80072c8: 4b64 ldr r3, [pc, #400] @ (800745c ) - 80072ca: 429a cmp r2, r3 - 80072cc: d958 bls.n 8007380 - 80072ce: 687b ldr r3, [r7, #4] - 80072d0: 681b ldr r3, [r3, #0] - 80072d2: 4a63 ldr r2, [pc, #396] @ (8007460 ) - 80072d4: 4293 cmp r3, r2 - 80072d6: d04f beq.n 8007378 - 80072d8: 687b ldr r3, [r7, #4] - 80072da: 681b ldr r3, [r3, #0] - 80072dc: 4a61 ldr r2, [pc, #388] @ (8007464 ) - 80072de: 4293 cmp r3, r2 - 80072e0: d048 beq.n 8007374 - 80072e2: 687b ldr r3, [r7, #4] - 80072e4: 681b ldr r3, [r3, #0] - 80072e6: 4a60 ldr r2, [pc, #384] @ (8007468 ) - 80072e8: 4293 cmp r3, r2 - 80072ea: d040 beq.n 800736e - 80072ec: 687b ldr r3, [r7, #4] - 80072ee: 681b ldr r3, [r3, #0] - 80072f0: 4a5e ldr r2, [pc, #376] @ (800746c ) - 80072f2: 4293 cmp r3, r2 - 80072f4: d038 beq.n 8007368 - 80072f6: 687b ldr r3, [r7, #4] - 80072f8: 681b ldr r3, [r3, #0] - 80072fa: 4a5d ldr r2, [pc, #372] @ (8007470 ) - 80072fc: 4293 cmp r3, r2 - 80072fe: d030 beq.n 8007362 - 8007300: 687b ldr r3, [r7, #4] - 8007302: 681b ldr r3, [r3, #0] - 8007304: 4a5b ldr r2, [pc, #364] @ (8007474 ) - 8007306: 4293 cmp r3, r2 - 8007308: d028 beq.n 800735c - 800730a: 687b ldr r3, [r7, #4] - 800730c: 681b ldr r3, [r3, #0] - 800730e: 4a53 ldr r2, [pc, #332] @ (800745c ) - 8007310: 4293 cmp r3, r2 - 8007312: d020 beq.n 8007356 - 8007314: 687b ldr r3, [r7, #4] - 8007316: 681b ldr r3, [r3, #0] - 8007318: 4a57 ldr r2, [pc, #348] @ (8007478 ) - 800731a: 4293 cmp r3, r2 - 800731c: d019 beq.n 8007352 - 800731e: 687b ldr r3, [r7, #4] - 8007320: 681b ldr r3, [r3, #0] - 8007322: 4a56 ldr r2, [pc, #344] @ (800747c ) - 8007324: 4293 cmp r3, r2 - 8007326: d012 beq.n 800734e - 8007328: 687b ldr r3, [r7, #4] - 800732a: 681b ldr r3, [r3, #0] - 800732c: 4a54 ldr r2, [pc, #336] @ (8007480 ) - 800732e: 4293 cmp r3, r2 - 8007330: d00a beq.n 8007348 - 8007332: 687b ldr r3, [r7, #4] - 8007334: 681b ldr r3, [r3, #0] - 8007336: 4a53 ldr r2, [pc, #332] @ (8007484 ) - 8007338: 4293 cmp r3, r2 - 800733a: d102 bne.n 8007342 - 800733c: f44f 5380 mov.w r3, #4096 @ 0x1000 - 8007340: e01b b.n 800737a - 8007342: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8007346: e018 b.n 800737a - 8007348: f44f 7380 mov.w r3, #256 @ 0x100 - 800734c: e015 b.n 800737a - 800734e: 2310 movs r3, #16 - 8007350: e013 b.n 800737a - 8007352: 2301 movs r3, #1 - 8007354: e011 b.n 800737a - 8007356: f04f 7380 mov.w r3, #16777216 @ 0x1000000 - 800735a: e00e b.n 800737a - 800735c: f44f 1380 mov.w r3, #1048576 @ 0x100000 - 8007360: e00b b.n 800737a - 8007362: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8007366: e008 b.n 800737a - 8007368: f44f 5380 mov.w r3, #4096 @ 0x1000 - 800736c: e005 b.n 800737a - 800736e: f44f 7380 mov.w r3, #256 @ 0x100 - 8007372: e002 b.n 800737a - 8007374: 2310 movs r3, #16 - 8007376: e000 b.n 800737a - 8007378: 2301 movs r3, #1 - 800737a: 4a43 ldr r2, [pc, #268] @ (8007488 ) - 800737c: 6053 str r3, [r2, #4] - 800737e: e057 b.n 8007430 - 8007380: 687b ldr r3, [r7, #4] - 8007382: 681b ldr r3, [r3, #0] - 8007384: 4a36 ldr r2, [pc, #216] @ (8007460 ) - 8007386: 4293 cmp r3, r2 - 8007388: d04f beq.n 800742a - 800738a: 687b ldr r3, [r7, #4] - 800738c: 681b ldr r3, [r3, #0] - 800738e: 4a35 ldr r2, [pc, #212] @ (8007464 ) - 8007390: 4293 cmp r3, r2 - 8007392: d048 beq.n 8007426 - 8007394: 687b ldr r3, [r7, #4] - 8007396: 681b ldr r3, [r3, #0] - 8007398: 4a33 ldr r2, [pc, #204] @ (8007468 ) - 800739a: 4293 cmp r3, r2 - 800739c: d040 beq.n 8007420 - 800739e: 687b ldr r3, [r7, #4] - 80073a0: 681b ldr r3, [r3, #0] - 80073a2: 4a32 ldr r2, [pc, #200] @ (800746c ) - 80073a4: 4293 cmp r3, r2 - 80073a6: d038 beq.n 800741a - 80073a8: 687b ldr r3, [r7, #4] - 80073aa: 681b ldr r3, [r3, #0] - 80073ac: 4a30 ldr r2, [pc, #192] @ (8007470 ) - 80073ae: 4293 cmp r3, r2 - 80073b0: d030 beq.n 8007414 - 80073b2: 687b ldr r3, [r7, #4] - 80073b4: 681b ldr r3, [r3, #0] - 80073b6: 4a2f ldr r2, [pc, #188] @ (8007474 ) - 80073b8: 4293 cmp r3, r2 - 80073ba: d028 beq.n 800740e - 80073bc: 687b ldr r3, [r7, #4] - 80073be: 681b ldr r3, [r3, #0] - 80073c0: 4a26 ldr r2, [pc, #152] @ (800745c ) - 80073c2: 4293 cmp r3, r2 - 80073c4: d020 beq.n 8007408 - 80073c6: 687b ldr r3, [r7, #4] - 80073c8: 681b ldr r3, [r3, #0] - 80073ca: 4a2b ldr r2, [pc, #172] @ (8007478 ) - 80073cc: 4293 cmp r3, r2 - 80073ce: d019 beq.n 8007404 - 80073d0: 687b ldr r3, [r7, #4] - 80073d2: 681b ldr r3, [r3, #0] - 80073d4: 4a29 ldr r2, [pc, #164] @ (800747c ) - 80073d6: 4293 cmp r3, r2 - 80073d8: d012 beq.n 8007400 - 80073da: 687b ldr r3, [r7, #4] - 80073dc: 681b ldr r3, [r3, #0] - 80073de: 4a28 ldr r2, [pc, #160] @ (8007480 ) - 80073e0: 4293 cmp r3, r2 - 80073e2: d00a beq.n 80073fa - 80073e4: 687b ldr r3, [r7, #4] - 80073e6: 681b ldr r3, [r3, #0] - 80073e8: 4a26 ldr r2, [pc, #152] @ (8007484 ) - 80073ea: 4293 cmp r3, r2 - 80073ec: d102 bne.n 80073f4 - 80073ee: f44f 5380 mov.w r3, #4096 @ 0x1000 - 80073f2: e01b b.n 800742c - 80073f4: f44f 3380 mov.w r3, #65536 @ 0x10000 - 80073f8: e018 b.n 800742c - 80073fa: f44f 7380 mov.w r3, #256 @ 0x100 - 80073fe: e015 b.n 800742c - 8007400: 2310 movs r3, #16 - 8007402: e013 b.n 800742c - 8007404: 2301 movs r3, #1 - 8007406: e011 b.n 800742c - 8007408: f04f 7380 mov.w r3, #16777216 @ 0x1000000 - 800740c: e00e b.n 800742c - 800740e: f44f 1380 mov.w r3, #1048576 @ 0x100000 - 8007412: e00b b.n 800742c - 8007414: f44f 3380 mov.w r3, #65536 @ 0x10000 - 8007418: e008 b.n 800742c - 800741a: f44f 5380 mov.w r3, #4096 @ 0x1000 - 800741e: e005 b.n 800742c - 8007420: f44f 7380 mov.w r3, #256 @ 0x100 - 8007424: e002 b.n 800742c - 8007426: 2310 movs r3, #16 - 8007428: e000 b.n 800742c - 800742a: 2301 movs r3, #1 - 800742c: 4a17 ldr r2, [pc, #92] @ (800748c ) - 800742e: 6053 str r3, [r2, #4] - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - 8007430: 687b ldr r3, [r7, #4] - 8007432: 2201 movs r2, #1 - 8007434: f883 2021 strb.w r2, [r3, #33] @ 0x21 - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - 8007438: 687b ldr r3, [r7, #4] - 800743a: 2200 movs r2, #0 - 800743c: f883 2020 strb.w r2, [r3, #32] - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - 8007440: 687b ldr r3, [r7, #4] - 8007442: 6b5b ldr r3, [r3, #52] @ 0x34 - 8007444: 2b00 cmp r3, #0 - 8007446: d003 beq.n 8007450 - { - hdma->XferAbortCallback(hdma); - 8007448: 687b ldr r3, [r7, #4] - 800744a: 6b5b ldr r3, [r3, #52] @ 0x34 - 800744c: 6878 ldr r0, [r7, #4] - 800744e: 4798 blx r3 - } - } - return status; - 8007450: 7bfb ldrb r3, [r7, #15] -} - 8007452: 4618 mov r0, r3 - 8007454: 3710 adds r7, #16 - 8007456: 46bd mov sp, r7 - 8007458: bd80 pop {r7, pc} - 800745a: bf00 nop - 800745c: 40020080 .word 0x40020080 - 8007460: 40020008 .word 0x40020008 - 8007464: 4002001c .word 0x4002001c - 8007468: 40020030 .word 0x40020030 - 800746c: 40020044 .word 0x40020044 - 8007470: 40020058 .word 0x40020058 - 8007474: 4002006c .word 0x4002006c - 8007478: 40020408 .word 0x40020408 - 800747c: 4002041c .word 0x4002041c - 8007480: 40020430 .word 0x40020430 - 8007484: 40020444 .word 0x40020444 - 8007488: 40020400 .word 0x40020400 - 800748c: 40020000 .word 0x40020000 - -08007490 : - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - 8007490: b480 push {r7} - 8007492: b08b sub sp, #44 @ 0x2c - 8007494: af00 add r7, sp, #0 - 8007496: 6078 str r0, [r7, #4] - 8007498: 6039 str r1, [r7, #0] - uint32_t position = 0x00u; - 800749a: 2300 movs r3, #0 - 800749c: 627b str r3, [r7, #36] @ 0x24 - uint32_t ioposition; - uint32_t iocurrent; - uint32_t temp; - uint32_t config = 0x00u; - 800749e: 2300 movs r3, #0 - 80074a0: 623b str r3, [r7, #32] - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0x00u) - 80074a2: e169 b.n 8007778 - { - /* Get the IO position */ - ioposition = (0x01uL << position); - 80074a4: 2201 movs r2, #1 - 80074a6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80074a8: fa02 f303 lsl.w r3, r2, r3 - 80074ac: 61fb str r3, [r7, #28] - - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 80074ae: 683b ldr r3, [r7, #0] - 80074b0: 681b ldr r3, [r3, #0] - 80074b2: 69fa ldr r2, [r7, #28] - 80074b4: 4013 ands r3, r2 - 80074b6: 61bb str r3, [r7, #24] - - if (iocurrent == ioposition) - 80074b8: 69ba ldr r2, [r7, #24] - 80074ba: 69fb ldr r3, [r7, #28] - 80074bc: 429a cmp r2, r3 - 80074be: f040 8158 bne.w 8007772 - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - - /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ - switch (GPIO_Init->Mode) - 80074c2: 683b ldr r3, [r7, #0] - 80074c4: 685b ldr r3, [r3, #4] - 80074c6: 4a9a ldr r2, [pc, #616] @ (8007730 ) - 80074c8: 4293 cmp r3, r2 - 80074ca: d05e beq.n 800758a - 80074cc: 4a98 ldr r2, [pc, #608] @ (8007730 ) - 80074ce: 4293 cmp r3, r2 - 80074d0: d875 bhi.n 80075be - 80074d2: 4a98 ldr r2, [pc, #608] @ (8007734 ) - 80074d4: 4293 cmp r3, r2 - 80074d6: d058 beq.n 800758a - 80074d8: 4a96 ldr r2, [pc, #600] @ (8007734 ) - 80074da: 4293 cmp r3, r2 - 80074dc: d86f bhi.n 80075be - 80074de: 4a96 ldr r2, [pc, #600] @ (8007738 ) - 80074e0: 4293 cmp r3, r2 - 80074e2: d052 beq.n 800758a - 80074e4: 4a94 ldr r2, [pc, #592] @ (8007738 ) - 80074e6: 4293 cmp r3, r2 - 80074e8: d869 bhi.n 80075be - 80074ea: 4a94 ldr r2, [pc, #592] @ (800773c ) - 80074ec: 4293 cmp r3, r2 - 80074ee: d04c beq.n 800758a - 80074f0: 4a92 ldr r2, [pc, #584] @ (800773c ) - 80074f2: 4293 cmp r3, r2 - 80074f4: d863 bhi.n 80075be - 80074f6: 4a92 ldr r2, [pc, #584] @ (8007740 ) - 80074f8: 4293 cmp r3, r2 - 80074fa: d046 beq.n 800758a - 80074fc: 4a90 ldr r2, [pc, #576] @ (8007740 ) - 80074fe: 4293 cmp r3, r2 - 8007500: d85d bhi.n 80075be - 8007502: 2b12 cmp r3, #18 - 8007504: d82a bhi.n 800755c - 8007506: 2b12 cmp r3, #18 - 8007508: d859 bhi.n 80075be - 800750a: a201 add r2, pc, #4 @ (adr r2, 8007510 ) - 800750c: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8007510: 0800758b .word 0x0800758b - 8007514: 08007565 .word 0x08007565 - 8007518: 08007577 .word 0x08007577 - 800751c: 080075b9 .word 0x080075b9 - 8007520: 080075bf .word 0x080075bf - 8007524: 080075bf .word 0x080075bf - 8007528: 080075bf .word 0x080075bf - 800752c: 080075bf .word 0x080075bf - 8007530: 080075bf .word 0x080075bf - 8007534: 080075bf .word 0x080075bf - 8007538: 080075bf .word 0x080075bf - 800753c: 080075bf .word 0x080075bf - 8007540: 080075bf .word 0x080075bf - 8007544: 080075bf .word 0x080075bf - 8007548: 080075bf .word 0x080075bf - 800754c: 080075bf .word 0x080075bf - 8007550: 080075bf .word 0x080075bf - 8007554: 0800756d .word 0x0800756d - 8007558: 08007581 .word 0x08007581 - 800755c: 4a79 ldr r2, [pc, #484] @ (8007744 ) - 800755e: 4293 cmp r3, r2 - 8007560: d013 beq.n 800758a - config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; - break; - - /* Parameters are checked with assert_param */ - default: - break; - 8007562: e02c b.n 80075be - config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; - 8007564: 683b ldr r3, [r7, #0] - 8007566: 68db ldr r3, [r3, #12] - 8007568: 623b str r3, [r7, #32] - break; - 800756a: e029 b.n 80075c0 - config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; - 800756c: 683b ldr r3, [r7, #0] - 800756e: 68db ldr r3, [r3, #12] - 8007570: 3304 adds r3, #4 - 8007572: 623b str r3, [r7, #32] - break; - 8007574: e024 b.n 80075c0 - config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; - 8007576: 683b ldr r3, [r7, #0] - 8007578: 68db ldr r3, [r3, #12] - 800757a: 3308 adds r3, #8 - 800757c: 623b str r3, [r7, #32] - break; - 800757e: e01f b.n 80075c0 - config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; - 8007580: 683b ldr r3, [r7, #0] - 8007582: 68db ldr r3, [r3, #12] - 8007584: 330c adds r3, #12 - 8007586: 623b str r3, [r7, #32] - break; - 8007588: e01a b.n 80075c0 - if (GPIO_Init->Pull == GPIO_NOPULL) - 800758a: 683b ldr r3, [r7, #0] - 800758c: 689b ldr r3, [r3, #8] - 800758e: 2b00 cmp r3, #0 - 8007590: d102 bne.n 8007598 - config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; - 8007592: 2304 movs r3, #4 - 8007594: 623b str r3, [r7, #32] - break; - 8007596: e013 b.n 80075c0 - else if (GPIO_Init->Pull == GPIO_PULLUP) - 8007598: 683b ldr r3, [r7, #0] - 800759a: 689b ldr r3, [r3, #8] - 800759c: 2b01 cmp r3, #1 - 800759e: d105 bne.n 80075ac - config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - 80075a0: 2308 movs r3, #8 - 80075a2: 623b str r3, [r7, #32] - GPIOx->BSRR = ioposition; - 80075a4: 687b ldr r3, [r7, #4] - 80075a6: 69fa ldr r2, [r7, #28] - 80075a8: 611a str r2, [r3, #16] - break; - 80075aa: e009 b.n 80075c0 - config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - 80075ac: 2308 movs r3, #8 - 80075ae: 623b str r3, [r7, #32] - GPIOx->BRR = ioposition; - 80075b0: 687b ldr r3, [r7, #4] - 80075b2: 69fa ldr r2, [r7, #28] - 80075b4: 615a str r2, [r3, #20] - break; - 80075b6: e003 b.n 80075c0 - config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; - 80075b8: 2300 movs r3, #0 - 80075ba: 623b str r3, [r7, #32] - break; - 80075bc: e000 b.n 80075c0 - break; - 80075be: bf00 nop - } - - /* Check if the current bit belongs to first half or last half of the pin count number - in order to address CRH or CRL register*/ - configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; - 80075c0: 69bb ldr r3, [r7, #24] - 80075c2: 2bff cmp r3, #255 @ 0xff - 80075c4: d801 bhi.n 80075ca - 80075c6: 687b ldr r3, [r7, #4] - 80075c8: e001 b.n 80075ce - 80075ca: 687b ldr r3, [r7, #4] - 80075cc: 3304 adds r3, #4 - 80075ce: 617b str r3, [r7, #20] - registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); - 80075d0: 69bb ldr r3, [r7, #24] - 80075d2: 2bff cmp r3, #255 @ 0xff - 80075d4: d802 bhi.n 80075dc - 80075d6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80075d8: 009b lsls r3, r3, #2 - 80075da: e002 b.n 80075e2 - 80075dc: 6a7b ldr r3, [r7, #36] @ 0x24 - 80075de: 3b08 subs r3, #8 - 80075e0: 009b lsls r3, r3, #2 - 80075e2: 613b str r3, [r7, #16] - - /* Apply the new configuration of the pin to the register */ - MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); - 80075e4: 697b ldr r3, [r7, #20] - 80075e6: 681a ldr r2, [r3, #0] - 80075e8: 210f movs r1, #15 - 80075ea: 693b ldr r3, [r7, #16] - 80075ec: fa01 f303 lsl.w r3, r1, r3 - 80075f0: 43db mvns r3, r3 - 80075f2: 401a ands r2, r3 - 80075f4: 6a39 ldr r1, [r7, #32] - 80075f6: 693b ldr r3, [r7, #16] - 80075f8: fa01 f303 lsl.w r3, r1, r3 - 80075fc: 431a orrs r2, r3 - 80075fe: 697b ldr r3, [r7, #20] - 8007600: 601a str r2, [r3, #0] - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 8007602: 683b ldr r3, [r7, #0] - 8007604: 685b ldr r3, [r3, #4] - 8007606: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800760a: 2b00 cmp r3, #0 - 800760c: f000 80b1 beq.w 8007772 - { - /* Enable AFIO Clock */ - __HAL_RCC_AFIO_CLK_ENABLE(); - 8007610: 4b4d ldr r3, [pc, #308] @ (8007748 ) - 8007612: 699b ldr r3, [r3, #24] - 8007614: 4a4c ldr r2, [pc, #304] @ (8007748 ) - 8007616: f043 0301 orr.w r3, r3, #1 - 800761a: 6193 str r3, [r2, #24] - 800761c: 4b4a ldr r3, [pc, #296] @ (8007748 ) - 800761e: 699b ldr r3, [r3, #24] - 8007620: f003 0301 and.w r3, r3, #1 - 8007624: 60bb str r3, [r7, #8] - 8007626: 68bb ldr r3, [r7, #8] - temp = AFIO->EXTICR[position >> 2u]; - 8007628: 4a48 ldr r2, [pc, #288] @ (800774c ) - 800762a: 6a7b ldr r3, [r7, #36] @ 0x24 - 800762c: 089b lsrs r3, r3, #2 - 800762e: 3302 adds r3, #2 - 8007630: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8007634: 60fb str r3, [r7, #12] - CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); - 8007636: 6a7b ldr r3, [r7, #36] @ 0x24 - 8007638: f003 0303 and.w r3, r3, #3 - 800763c: 009b lsls r3, r3, #2 - 800763e: 220f movs r2, #15 - 8007640: fa02 f303 lsl.w r3, r2, r3 - 8007644: 43db mvns r3, r3 - 8007646: 68fa ldr r2, [r7, #12] - 8007648: 4013 ands r3, r2 - 800764a: 60fb str r3, [r7, #12] - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); - 800764c: 687b ldr r3, [r7, #4] - 800764e: 4a40 ldr r2, [pc, #256] @ (8007750 ) - 8007650: 4293 cmp r3, r2 - 8007652: d013 beq.n 800767c - 8007654: 687b ldr r3, [r7, #4] - 8007656: 4a3f ldr r2, [pc, #252] @ (8007754 ) - 8007658: 4293 cmp r3, r2 - 800765a: d00d beq.n 8007678 - 800765c: 687b ldr r3, [r7, #4] - 800765e: 4a3e ldr r2, [pc, #248] @ (8007758 ) - 8007660: 4293 cmp r3, r2 - 8007662: d007 beq.n 8007674 - 8007664: 687b ldr r3, [r7, #4] - 8007666: 4a3d ldr r2, [pc, #244] @ (800775c ) - 8007668: 4293 cmp r3, r2 - 800766a: d101 bne.n 8007670 - 800766c: 2303 movs r3, #3 - 800766e: e006 b.n 800767e - 8007670: 2304 movs r3, #4 - 8007672: e004 b.n 800767e - 8007674: 2302 movs r3, #2 - 8007676: e002 b.n 800767e - 8007678: 2301 movs r3, #1 - 800767a: e000 b.n 800767e - 800767c: 2300 movs r3, #0 - 800767e: 6a7a ldr r2, [r7, #36] @ 0x24 - 8007680: f002 0203 and.w r2, r2, #3 - 8007684: 0092 lsls r2, r2, #2 - 8007686: 4093 lsls r3, r2 - 8007688: 68fa ldr r2, [r7, #12] - 800768a: 4313 orrs r3, r2 - 800768c: 60fb str r3, [r7, #12] - AFIO->EXTICR[position >> 2u] = temp; - 800768e: 492f ldr r1, [pc, #188] @ (800774c ) - 8007690: 6a7b ldr r3, [r7, #36] @ 0x24 - 8007692: 089b lsrs r3, r3, #2 - 8007694: 3302 adds r3, #2 - 8007696: 68fa ldr r2, [r7, #12] - 8007698: f841 2023 str.w r2, [r1, r3, lsl #2] - - - /* Configure the interrupt mask */ - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 800769c: 683b ldr r3, [r7, #0] - 800769e: 685b ldr r3, [r3, #4] - 80076a0: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 80076a4: 2b00 cmp r3, #0 - 80076a6: d006 beq.n 80076b6 - { - SET_BIT(EXTI->IMR, iocurrent); - 80076a8: 4b2d ldr r3, [pc, #180] @ (8007760 ) - 80076aa: 681a ldr r2, [r3, #0] - 80076ac: 492c ldr r1, [pc, #176] @ (8007760 ) - 80076ae: 69bb ldr r3, [r7, #24] - 80076b0: 4313 orrs r3, r2 - 80076b2: 600b str r3, [r1, #0] - 80076b4: e006 b.n 80076c4 - } - else - { - CLEAR_BIT(EXTI->IMR, iocurrent); - 80076b6: 4b2a ldr r3, [pc, #168] @ (8007760 ) - 80076b8: 681a ldr r2, [r3, #0] - 80076ba: 69bb ldr r3, [r7, #24] - 80076bc: 43db mvns r3, r3 - 80076be: 4928 ldr r1, [pc, #160] @ (8007760 ) - 80076c0: 4013 ands r3, r2 - 80076c2: 600b str r3, [r1, #0] - } - - /* Configure the event mask */ - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 80076c4: 683b ldr r3, [r7, #0] - 80076c6: 685b ldr r3, [r3, #4] - 80076c8: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80076cc: 2b00 cmp r3, #0 - 80076ce: d006 beq.n 80076de - { - SET_BIT(EXTI->EMR, iocurrent); - 80076d0: 4b23 ldr r3, [pc, #140] @ (8007760 ) - 80076d2: 685a ldr r2, [r3, #4] - 80076d4: 4922 ldr r1, [pc, #136] @ (8007760 ) - 80076d6: 69bb ldr r3, [r7, #24] - 80076d8: 4313 orrs r3, r2 - 80076da: 604b str r3, [r1, #4] - 80076dc: e006 b.n 80076ec - } - else - { - CLEAR_BIT(EXTI->EMR, iocurrent); - 80076de: 4b20 ldr r3, [pc, #128] @ (8007760 ) - 80076e0: 685a ldr r2, [r3, #4] - 80076e2: 69bb ldr r3, [r7, #24] - 80076e4: 43db mvns r3, r3 - 80076e6: 491e ldr r1, [pc, #120] @ (8007760 ) - 80076e8: 4013 ands r3, r2 - 80076ea: 604b str r3, [r1, #4] - } - - /* Enable or disable the rising trigger */ - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 80076ec: 683b ldr r3, [r7, #0] - 80076ee: 685b ldr r3, [r3, #4] - 80076f0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 80076f4: 2b00 cmp r3, #0 - 80076f6: d006 beq.n 8007706 - { - SET_BIT(EXTI->RTSR, iocurrent); - 80076f8: 4b19 ldr r3, [pc, #100] @ (8007760 ) - 80076fa: 689a ldr r2, [r3, #8] - 80076fc: 4918 ldr r1, [pc, #96] @ (8007760 ) - 80076fe: 69bb ldr r3, [r7, #24] - 8007700: 4313 orrs r3, r2 - 8007702: 608b str r3, [r1, #8] - 8007704: e006 b.n 8007714 - } - else - { - CLEAR_BIT(EXTI->RTSR, iocurrent); - 8007706: 4b16 ldr r3, [pc, #88] @ (8007760 ) - 8007708: 689a ldr r2, [r3, #8] - 800770a: 69bb ldr r3, [r7, #24] - 800770c: 43db mvns r3, r3 - 800770e: 4914 ldr r1, [pc, #80] @ (8007760 ) - 8007710: 4013 ands r3, r2 - 8007712: 608b str r3, [r1, #8] - } - - /* Enable or disable the falling trigger */ - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - 8007714: 683b ldr r3, [r7, #0] - 8007716: 685b ldr r3, [r3, #4] - 8007718: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 800771c: 2b00 cmp r3, #0 - 800771e: d021 beq.n 8007764 - { - SET_BIT(EXTI->FTSR, iocurrent); - 8007720: 4b0f ldr r3, [pc, #60] @ (8007760 ) - 8007722: 68da ldr r2, [r3, #12] - 8007724: 490e ldr r1, [pc, #56] @ (8007760 ) - 8007726: 69bb ldr r3, [r7, #24] - 8007728: 4313 orrs r3, r2 - 800772a: 60cb str r3, [r1, #12] - 800772c: e021 b.n 8007772 - 800772e: bf00 nop - 8007730: 10320000 .word 0x10320000 - 8007734: 10310000 .word 0x10310000 - 8007738: 10220000 .word 0x10220000 - 800773c: 10210000 .word 0x10210000 - 8007740: 10120000 .word 0x10120000 - 8007744: 10110000 .word 0x10110000 - 8007748: 40021000 .word 0x40021000 - 800774c: 40010000 .word 0x40010000 - 8007750: 40010800 .word 0x40010800 - 8007754: 40010c00 .word 0x40010c00 - 8007758: 40011000 .word 0x40011000 - 800775c: 40011400 .word 0x40011400 - 8007760: 40010400 .word 0x40010400 - } - else - { - CLEAR_BIT(EXTI->FTSR, iocurrent); - 8007764: 4b0b ldr r3, [pc, #44] @ (8007794 ) - 8007766: 68da ldr r2, [r3, #12] - 8007768: 69bb ldr r3, [r7, #24] - 800776a: 43db mvns r3, r3 - 800776c: 4909 ldr r1, [pc, #36] @ (8007794 ) - 800776e: 4013 ands r3, r2 - 8007770: 60cb str r3, [r1, #12] - } - } - } - - position++; - 8007772: 6a7b ldr r3, [r7, #36] @ 0x24 - 8007774: 3301 adds r3, #1 - 8007776: 627b str r3, [r7, #36] @ 0x24 - while (((GPIO_Init->Pin) >> position) != 0x00u) - 8007778: 683b ldr r3, [r7, #0] - 800777a: 681a ldr r2, [r3, #0] - 800777c: 6a7b ldr r3, [r7, #36] @ 0x24 - 800777e: fa22 f303 lsr.w r3, r2, r3 - 8007782: 2b00 cmp r3, #0 - 8007784: f47f ae8e bne.w 80074a4 - } -} - 8007788: bf00 nop - 800778a: bf00 nop - 800778c: 372c adds r7, #44 @ 0x2c - 800778e: 46bd mov sp, r7 - 8007790: bc80 pop {r7} - 8007792: 4770 bx lr - 8007794: 40010400 .word 0x40010400 - -08007798 : - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - 8007798: b480 push {r7} - 800779a: b085 sub sp, #20 - 800779c: af00 add r7, sp, #0 - 800779e: 6078 str r0, [r7, #4] - 80077a0: 460b mov r3, r1 - 80077a2: 807b strh r3, [r7, #2] - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - 80077a4: 687b ldr r3, [r7, #4] - 80077a6: 689a ldr r2, [r3, #8] - 80077a8: 887b ldrh r3, [r7, #2] - 80077aa: 4013 ands r3, r2 - 80077ac: 2b00 cmp r3, #0 - 80077ae: d002 beq.n 80077b6 - { - bitstatus = GPIO_PIN_SET; - 80077b0: 2301 movs r3, #1 - 80077b2: 73fb strb r3, [r7, #15] - 80077b4: e001 b.n 80077ba - } - else - { - bitstatus = GPIO_PIN_RESET; - 80077b6: 2300 movs r3, #0 - 80077b8: 73fb strb r3, [r7, #15] - } - return bitstatus; - 80077ba: 7bfb ldrb r3, [r7, #15] -} - 80077bc: 4618 mov r0, r3 - 80077be: 3714 adds r7, #20 - 80077c0: 46bd mov sp, r7 - 80077c2: bc80 pop {r7} - 80077c4: 4770 bx lr - -080077c6 : - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - 80077c6: b480 push {r7} - 80077c8: b083 sub sp, #12 - 80077ca: af00 add r7, sp, #0 - 80077cc: 6078 str r0, [r7, #4] - 80077ce: 460b mov r3, r1 - 80077d0: 807b strh r3, [r7, #2] - 80077d2: 4613 mov r3, r2 - 80077d4: 707b strb r3, [r7, #1] - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - 80077d6: 787b ldrb r3, [r7, #1] - 80077d8: 2b00 cmp r3, #0 - 80077da: d003 beq.n 80077e4 - { - GPIOx->BSRR = GPIO_Pin; - 80077dc: 887a ldrh r2, [r7, #2] - 80077de: 687b ldr r3, [r7, #4] - 80077e0: 611a str r2, [r3, #16] - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; - } -} - 80077e2: e003 b.n 80077ec - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; - 80077e4: 887b ldrh r3, [r7, #2] - 80077e6: 041a lsls r2, r3, #16 - 80077e8: 687b ldr r3, [r7, #4] - 80077ea: 611a str r2, [r3, #16] -} - 80077ec: bf00 nop - 80077ee: 370c adds r7, #12 - 80077f0: 46bd mov sp, r7 - 80077f2: bc80 pop {r7} - 80077f4: 4770 bx lr - ... - -080077f8 : - * @note If the HSE divided by 128 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - 80077f8: b480 push {r7} - 80077fa: af00 add r7, sp, #0 - /* Enable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; - 80077fc: 4b03 ldr r3, [pc, #12] @ (800780c ) - 80077fe: 2201 movs r2, #1 - 8007800: 601a str r2, [r3, #0] -} - 8007802: bf00 nop - 8007804: 46bd mov sp, r7 - 8007806: bc80 pop {r7} - 8007808: 4770 bx lr - 800780a: bf00 nop - 800780c: 420e0020 .word 0x420e0020 - -08007810 : - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - 8007810: b580 push {r7, lr} - 8007812: b086 sub sp, #24 - 8007814: af00 add r7, sp, #0 - 8007816: 6078 str r0, [r7, #4] - uint32_t tickstart; - uint32_t pll_config; - - /* Check Null pointer */ - if (RCC_OscInitStruct == NULL) - 8007818: 687b ldr r3, [r7, #4] - 800781a: 2b00 cmp r3, #0 - 800781c: d101 bne.n 8007822 - { - return HAL_ERROR; - 800781e: 2301 movs r3, #1 - 8007820: e304 b.n 8007e2c - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8007822: 687b ldr r3, [r7, #4] - 8007824: 681b ldr r3, [r3, #0] - 8007826: f003 0301 and.w r3, r3, #1 - 800782a: 2b00 cmp r3, #0 - 800782c: f000 8087 beq.w 800793e - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - 8007830: 4b92 ldr r3, [pc, #584] @ (8007a7c ) - 8007832: 685b ldr r3, [r3, #4] - 8007834: f003 030c and.w r3, r3, #12 - 8007838: 2b04 cmp r3, #4 - 800783a: d00c beq.n 8007856 - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - 800783c: 4b8f ldr r3, [pc, #572] @ (8007a7c ) - 800783e: 685b ldr r3, [r3, #4] - 8007840: f003 030c and.w r3, r3, #12 - 8007844: 2b08 cmp r3, #8 - 8007846: d112 bne.n 800786e - 8007848: 4b8c ldr r3, [pc, #560] @ (8007a7c ) - 800784a: 685b ldr r3, [r3, #4] - 800784c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8007850: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8007854: d10b bne.n 800786e - { - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8007856: 4b89 ldr r3, [pc, #548] @ (8007a7c ) - 8007858: 681b ldr r3, [r3, #0] - 800785a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 800785e: 2b00 cmp r3, #0 - 8007860: d06c beq.n 800793c - 8007862: 687b ldr r3, [r7, #4] - 8007864: 689b ldr r3, [r3, #8] - 8007866: 2b00 cmp r3, #0 - 8007868: d168 bne.n 800793c - { - return HAL_ERROR; - 800786a: 2301 movs r3, #1 - 800786c: e2de b.n 8007e2c - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 800786e: 687b ldr r3, [r7, #4] - 8007870: 689b ldr r3, [r3, #8] - 8007872: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8007876: d106 bne.n 8007886 - 8007878: 4b80 ldr r3, [pc, #512] @ (8007a7c ) - 800787a: 681b ldr r3, [r3, #0] - 800787c: 4a7f ldr r2, [pc, #508] @ (8007a7c ) - 800787e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8007882: 6013 str r3, [r2, #0] - 8007884: e02e b.n 80078e4 - 8007886: 687b ldr r3, [r7, #4] - 8007888: 689b ldr r3, [r3, #8] - 800788a: 2b00 cmp r3, #0 - 800788c: d10c bne.n 80078a8 - 800788e: 4b7b ldr r3, [pc, #492] @ (8007a7c ) - 8007890: 681b ldr r3, [r3, #0] - 8007892: 4a7a ldr r2, [pc, #488] @ (8007a7c ) - 8007894: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8007898: 6013 str r3, [r2, #0] - 800789a: 4b78 ldr r3, [pc, #480] @ (8007a7c ) - 800789c: 681b ldr r3, [r3, #0] - 800789e: 4a77 ldr r2, [pc, #476] @ (8007a7c ) - 80078a0: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 80078a4: 6013 str r3, [r2, #0] - 80078a6: e01d b.n 80078e4 - 80078a8: 687b ldr r3, [r7, #4] - 80078aa: 689b ldr r3, [r3, #8] - 80078ac: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 80078b0: d10c bne.n 80078cc - 80078b2: 4b72 ldr r3, [pc, #456] @ (8007a7c ) - 80078b4: 681b ldr r3, [r3, #0] - 80078b6: 4a71 ldr r2, [pc, #452] @ (8007a7c ) - 80078b8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 80078bc: 6013 str r3, [r2, #0] - 80078be: 4b6f ldr r3, [pc, #444] @ (8007a7c ) - 80078c0: 681b ldr r3, [r3, #0] - 80078c2: 4a6e ldr r2, [pc, #440] @ (8007a7c ) - 80078c4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 80078c8: 6013 str r3, [r2, #0] - 80078ca: e00b b.n 80078e4 - 80078cc: 4b6b ldr r3, [pc, #428] @ (8007a7c ) - 80078ce: 681b ldr r3, [r3, #0] - 80078d0: 4a6a ldr r2, [pc, #424] @ (8007a7c ) - 80078d2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 80078d6: 6013 str r3, [r2, #0] - 80078d8: 4b68 ldr r3, [pc, #416] @ (8007a7c ) - 80078da: 681b ldr r3, [r3, #0] - 80078dc: 4a67 ldr r2, [pc, #412] @ (8007a7c ) - 80078de: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 80078e2: 6013 str r3, [r2, #0] - - - /* Check the HSE State */ - if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 80078e4: 687b ldr r3, [r7, #4] - 80078e6: 689b ldr r3, [r3, #8] - 80078e8: 2b00 cmp r3, #0 - 80078ea: d013 beq.n 8007914 - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80078ec: f7fd ffa2 bl 8005834 - 80078f0: 6138 str r0, [r7, #16] - - /* Wait till HSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80078f2: e008 b.n 8007906 - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 80078f4: f7fd ff9e bl 8005834 - 80078f8: 4602 mov r2, r0 - 80078fa: 693b ldr r3, [r7, #16] - 80078fc: 1ad3 subs r3, r2, r3 - 80078fe: 2b64 cmp r3, #100 @ 0x64 - 8007900: d901 bls.n 8007906 - { - return HAL_TIMEOUT; - 8007902: 2303 movs r3, #3 - 8007904: e292 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8007906: 4b5d ldr r3, [pc, #372] @ (8007a7c ) - 8007908: 681b ldr r3, [r3, #0] - 800790a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 800790e: 2b00 cmp r3, #0 - 8007910: d0f0 beq.n 80078f4 - 8007912: e014 b.n 800793e - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007914: f7fd ff8e bl 8005834 - 8007918: 6138 str r0, [r7, #16] - - /* Wait till HSE is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 800791a: e008 b.n 800792e - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 800791c: f7fd ff8a bl 8005834 - 8007920: 4602 mov r2, r0 - 8007922: 693b ldr r3, [r7, #16] - 8007924: 1ad3 subs r3, r2, r3 - 8007926: 2b64 cmp r3, #100 @ 0x64 - 8007928: d901 bls.n 800792e - { - return HAL_TIMEOUT; - 800792a: 2303 movs r3, #3 - 800792c: e27e b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 800792e: 4b53 ldr r3, [pc, #332] @ (8007a7c ) - 8007930: 681b ldr r3, [r3, #0] - 8007932: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8007936: 2b00 cmp r3, #0 - 8007938: d1f0 bne.n 800791c - 800793a: e000 b.n 800793e - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 800793c: bf00 nop - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 800793e: 687b ldr r3, [r7, #4] - 8007940: 681b ldr r3, [r3, #0] - 8007942: f003 0302 and.w r3, r3, #2 - 8007946: 2b00 cmp r3, #0 - 8007948: d063 beq.n 8007a12 - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - 800794a: 4b4c ldr r3, [pc, #304] @ (8007a7c ) - 800794c: 685b ldr r3, [r3, #4] - 800794e: f003 030c and.w r3, r3, #12 - 8007952: 2b00 cmp r3, #0 - 8007954: d00b beq.n 800796e - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) - 8007956: 4b49 ldr r3, [pc, #292] @ (8007a7c ) - 8007958: 685b ldr r3, [r3, #4] - 800795a: f003 030c and.w r3, r3, #12 - 800795e: 2b08 cmp r3, #8 - 8007960: d11c bne.n 800799c - 8007962: 4b46 ldr r3, [pc, #280] @ (8007a7c ) - 8007964: 685b ldr r3, [r3, #4] - 8007966: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 800796a: 2b00 cmp r3, #0 - 800796c: d116 bne.n 800799c - { - /* When HSI is used as system clock it will not disabled */ - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 800796e: 4b43 ldr r3, [pc, #268] @ (8007a7c ) - 8007970: 681b ldr r3, [r3, #0] - 8007972: f003 0302 and.w r3, r3, #2 - 8007976: 2b00 cmp r3, #0 - 8007978: d005 beq.n 8007986 - 800797a: 687b ldr r3, [r7, #4] - 800797c: 695b ldr r3, [r3, #20] - 800797e: 2b01 cmp r3, #1 - 8007980: d001 beq.n 8007986 - { - return HAL_ERROR; - 8007982: 2301 movs r3, #1 - 8007984: e252 b.n 8007e2c - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8007986: 4b3d ldr r3, [pc, #244] @ (8007a7c ) - 8007988: 681b ldr r3, [r3, #0] - 800798a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 800798e: 687b ldr r3, [r7, #4] - 8007990: 699b ldr r3, [r3, #24] - 8007992: 00db lsls r3, r3, #3 - 8007994: 4939 ldr r1, [pc, #228] @ (8007a7c ) - 8007996: 4313 orrs r3, r2 - 8007998: 600b str r3, [r1, #0] - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 800799a: e03a b.n 8007a12 - } - } - else - { - /* Check the HSI State */ - if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 800799c: 687b ldr r3, [r7, #4] - 800799e: 695b ldr r3, [r3, #20] - 80079a0: 2b00 cmp r3, #0 - 80079a2: d020 beq.n 80079e6 - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - 80079a4: 4b36 ldr r3, [pc, #216] @ (8007a80 ) - 80079a6: 2201 movs r2, #1 - 80079a8: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80079aa: f7fd ff43 bl 8005834 - 80079ae: 6138 str r0, [r7, #16] - - /* Wait till HSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80079b0: e008 b.n 80079c4 - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 80079b2: f7fd ff3f bl 8005834 - 80079b6: 4602 mov r2, r0 - 80079b8: 693b ldr r3, [r7, #16] - 80079ba: 1ad3 subs r3, r2, r3 - 80079bc: 2b02 cmp r3, #2 - 80079be: d901 bls.n 80079c4 - { - return HAL_TIMEOUT; - 80079c0: 2303 movs r3, #3 - 80079c2: e233 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80079c4: 4b2d ldr r3, [pc, #180] @ (8007a7c ) - 80079c6: 681b ldr r3, [r3, #0] - 80079c8: f003 0302 and.w r3, r3, #2 - 80079cc: 2b00 cmp r3, #0 - 80079ce: d0f0 beq.n 80079b2 - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 80079d0: 4b2a ldr r3, [pc, #168] @ (8007a7c ) - 80079d2: 681b ldr r3, [r3, #0] - 80079d4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 - 80079d8: 687b ldr r3, [r7, #4] - 80079da: 699b ldr r3, [r3, #24] - 80079dc: 00db lsls r3, r3, #3 - 80079de: 4927 ldr r1, [pc, #156] @ (8007a7c ) - 80079e0: 4313 orrs r3, r2 - 80079e2: 600b str r3, [r1, #0] - 80079e4: e015 b.n 8007a12 - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - 80079e6: 4b26 ldr r3, [pc, #152] @ (8007a80 ) - 80079e8: 2200 movs r2, #0 - 80079ea: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80079ec: f7fd ff22 bl 8005834 - 80079f0: 6138 str r0, [r7, #16] - - /* Wait till HSI is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 80079f2: e008 b.n 8007a06 - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 80079f4: f7fd ff1e bl 8005834 - 80079f8: 4602 mov r2, r0 - 80079fa: 693b ldr r3, [r7, #16] - 80079fc: 1ad3 subs r3, r2, r3 - 80079fe: 2b02 cmp r3, #2 - 8007a00: d901 bls.n 8007a06 - { - return HAL_TIMEOUT; - 8007a02: 2303 movs r3, #3 - 8007a04: e212 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8007a06: 4b1d ldr r3, [pc, #116] @ (8007a7c ) - 8007a08: 681b ldr r3, [r3, #0] - 8007a0a: f003 0302 and.w r3, r3, #2 - 8007a0e: 2b00 cmp r3, #0 - 8007a10: d1f0 bne.n 80079f4 - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8007a12: 687b ldr r3, [r7, #4] - 8007a14: 681b ldr r3, [r3, #0] - 8007a16: f003 0308 and.w r3, r3, #8 - 8007a1a: 2b00 cmp r3, #0 - 8007a1c: d03a beq.n 8007a94 - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8007a1e: 687b ldr r3, [r7, #4] - 8007a20: 69db ldr r3, [r3, #28] - 8007a22: 2b00 cmp r3, #0 - 8007a24: d019 beq.n 8007a5a - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - 8007a26: 4b17 ldr r3, [pc, #92] @ (8007a84 ) - 8007a28: 2201 movs r2, #1 - 8007a2a: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007a2c: f7fd ff02 bl 8005834 - 8007a30: 6138 str r0, [r7, #16] - - /* Wait till LSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8007a32: e008 b.n 8007a46 - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8007a34: f7fd fefe bl 8005834 - 8007a38: 4602 mov r2, r0 - 8007a3a: 693b ldr r3, [r7, #16] - 8007a3c: 1ad3 subs r3, r2, r3 - 8007a3e: 2b02 cmp r3, #2 - 8007a40: d901 bls.n 8007a46 - { - return HAL_TIMEOUT; - 8007a42: 2303 movs r3, #3 - 8007a44: e1f2 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8007a46: 4b0d ldr r3, [pc, #52] @ (8007a7c ) - 8007a48: 6a5b ldr r3, [r3, #36] @ 0x24 - 8007a4a: f003 0302 and.w r3, r3, #2 - 8007a4e: 2b00 cmp r3, #0 - 8007a50: d0f0 beq.n 8007a34 - } - } - /* To have a fully stabilized clock in the specified range, a software delay of 1ms - should be added.*/ - RCC_Delay(1); - 8007a52: 2001 movs r0, #1 - 8007a54: f000 fbec bl 8008230 - 8007a58: e01c b.n 8007a94 - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - 8007a5a: 4b0a ldr r3, [pc, #40] @ (8007a84 ) - 8007a5c: 2200 movs r2, #0 - 8007a5e: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007a60: f7fd fee8 bl 8005834 - 8007a64: 6138 str r0, [r7, #16] - - /* Wait till LSI is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8007a66: e00f b.n 8007a88 - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8007a68: f7fd fee4 bl 8005834 - 8007a6c: 4602 mov r2, r0 - 8007a6e: 693b ldr r3, [r7, #16] - 8007a70: 1ad3 subs r3, r2, r3 - 8007a72: 2b02 cmp r3, #2 - 8007a74: d908 bls.n 8007a88 - { - return HAL_TIMEOUT; - 8007a76: 2303 movs r3, #3 - 8007a78: e1d8 b.n 8007e2c - 8007a7a: bf00 nop - 8007a7c: 40021000 .word 0x40021000 - 8007a80: 42420000 .word 0x42420000 - 8007a84: 42420480 .word 0x42420480 - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8007a88: 4b9b ldr r3, [pc, #620] @ (8007cf8 ) - 8007a8a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8007a8c: f003 0302 and.w r3, r3, #2 - 8007a90: 2b00 cmp r3, #0 - 8007a92: d1e9 bne.n 8007a68 - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8007a94: 687b ldr r3, [r7, #4] - 8007a96: 681b ldr r3, [r3, #0] - 8007a98: f003 0304 and.w r3, r3, #4 - 8007a9c: 2b00 cmp r3, #0 - 8007a9e: f000 80a6 beq.w 8007bee - { - FlagStatus pwrclkchanged = RESET; - 8007aa2: 2300 movs r3, #0 - 8007aa4: 75fb strb r3, [r7, #23] - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8007aa6: 4b94 ldr r3, [pc, #592] @ (8007cf8 ) - 8007aa8: 69db ldr r3, [r3, #28] - 8007aaa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8007aae: 2b00 cmp r3, #0 - 8007ab0: d10d bne.n 8007ace - { - __HAL_RCC_PWR_CLK_ENABLE(); - 8007ab2: 4b91 ldr r3, [pc, #580] @ (8007cf8 ) - 8007ab4: 69db ldr r3, [r3, #28] - 8007ab6: 4a90 ldr r2, [pc, #576] @ (8007cf8 ) - 8007ab8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8007abc: 61d3 str r3, [r2, #28] - 8007abe: 4b8e ldr r3, [pc, #568] @ (8007cf8 ) - 8007ac0: 69db ldr r3, [r3, #28] - 8007ac2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8007ac6: 60bb str r3, [r7, #8] - 8007ac8: 68bb ldr r3, [r7, #8] - pwrclkchanged = SET; - 8007aca: 2301 movs r3, #1 - 8007acc: 75fb strb r3, [r7, #23] - } - - if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8007ace: 4b8b ldr r3, [pc, #556] @ (8007cfc ) - 8007ad0: 681b ldr r3, [r3, #0] - 8007ad2: f403 7380 and.w r3, r3, #256 @ 0x100 - 8007ad6: 2b00 cmp r3, #0 - 8007ad8: d118 bne.n 8007b0c - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - 8007ada: 4b88 ldr r3, [pc, #544] @ (8007cfc ) - 8007adc: 681b ldr r3, [r3, #0] - 8007ade: 4a87 ldr r2, [pc, #540] @ (8007cfc ) - 8007ae0: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8007ae4: 6013 str r3, [r2, #0] - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - 8007ae6: f7fd fea5 bl 8005834 - 8007aea: 6138 str r0, [r7, #16] - - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8007aec: e008 b.n 8007b00 - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8007aee: f7fd fea1 bl 8005834 - 8007af2: 4602 mov r2, r0 - 8007af4: 693b ldr r3, [r7, #16] - 8007af6: 1ad3 subs r3, r2, r3 - 8007af8: 2b64 cmp r3, #100 @ 0x64 - 8007afa: d901 bls.n 8007b00 - { - return HAL_TIMEOUT; - 8007afc: 2303 movs r3, #3 - 8007afe: e195 b.n 8007e2c - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8007b00: 4b7e ldr r3, [pc, #504] @ (8007cfc ) - 8007b02: 681b ldr r3, [r3, #0] - 8007b04: f403 7380 and.w r3, r3, #256 @ 0x100 - 8007b08: 2b00 cmp r3, #0 - 8007b0a: d0f0 beq.n 8007aee - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8007b0c: 687b ldr r3, [r7, #4] - 8007b0e: 691b ldr r3, [r3, #16] - 8007b10: 2b01 cmp r3, #1 - 8007b12: d106 bne.n 8007b22 - 8007b14: 4b78 ldr r3, [pc, #480] @ (8007cf8 ) - 8007b16: 6a1b ldr r3, [r3, #32] - 8007b18: 4a77 ldr r2, [pc, #476] @ (8007cf8 ) - 8007b1a: f043 0301 orr.w r3, r3, #1 - 8007b1e: 6213 str r3, [r2, #32] - 8007b20: e02d b.n 8007b7e - 8007b22: 687b ldr r3, [r7, #4] - 8007b24: 691b ldr r3, [r3, #16] - 8007b26: 2b00 cmp r3, #0 - 8007b28: d10c bne.n 8007b44 - 8007b2a: 4b73 ldr r3, [pc, #460] @ (8007cf8 ) - 8007b2c: 6a1b ldr r3, [r3, #32] - 8007b2e: 4a72 ldr r2, [pc, #456] @ (8007cf8 ) - 8007b30: f023 0301 bic.w r3, r3, #1 - 8007b34: 6213 str r3, [r2, #32] - 8007b36: 4b70 ldr r3, [pc, #448] @ (8007cf8 ) - 8007b38: 6a1b ldr r3, [r3, #32] - 8007b3a: 4a6f ldr r2, [pc, #444] @ (8007cf8 ) - 8007b3c: f023 0304 bic.w r3, r3, #4 - 8007b40: 6213 str r3, [r2, #32] - 8007b42: e01c b.n 8007b7e - 8007b44: 687b ldr r3, [r7, #4] - 8007b46: 691b ldr r3, [r3, #16] - 8007b48: 2b05 cmp r3, #5 - 8007b4a: d10c bne.n 8007b66 - 8007b4c: 4b6a ldr r3, [pc, #424] @ (8007cf8 ) - 8007b4e: 6a1b ldr r3, [r3, #32] - 8007b50: 4a69 ldr r2, [pc, #420] @ (8007cf8 ) - 8007b52: f043 0304 orr.w r3, r3, #4 - 8007b56: 6213 str r3, [r2, #32] - 8007b58: 4b67 ldr r3, [pc, #412] @ (8007cf8 ) - 8007b5a: 6a1b ldr r3, [r3, #32] - 8007b5c: 4a66 ldr r2, [pc, #408] @ (8007cf8 ) - 8007b5e: f043 0301 orr.w r3, r3, #1 - 8007b62: 6213 str r3, [r2, #32] - 8007b64: e00b b.n 8007b7e - 8007b66: 4b64 ldr r3, [pc, #400] @ (8007cf8 ) - 8007b68: 6a1b ldr r3, [r3, #32] - 8007b6a: 4a63 ldr r2, [pc, #396] @ (8007cf8 ) - 8007b6c: f023 0301 bic.w r3, r3, #1 - 8007b70: 6213 str r3, [r2, #32] - 8007b72: 4b61 ldr r3, [pc, #388] @ (8007cf8 ) - 8007b74: 6a1b ldr r3, [r3, #32] - 8007b76: 4a60 ldr r2, [pc, #384] @ (8007cf8 ) - 8007b78: f023 0304 bic.w r3, r3, #4 - 8007b7c: 6213 str r3, [r2, #32] - /* Check the LSE State */ - if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 8007b7e: 687b ldr r3, [r7, #4] - 8007b80: 691b ldr r3, [r3, #16] - 8007b82: 2b00 cmp r3, #0 - 8007b84: d015 beq.n 8007bb2 - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007b86: f7fd fe55 bl 8005834 - 8007b8a: 6138 str r0, [r7, #16] - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8007b8c: e00a b.n 8007ba4 - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8007b8e: f7fd fe51 bl 8005834 - 8007b92: 4602 mov r2, r0 - 8007b94: 693b ldr r3, [r7, #16] - 8007b96: 1ad3 subs r3, r2, r3 - 8007b98: f241 3288 movw r2, #5000 @ 0x1388 - 8007b9c: 4293 cmp r3, r2 - 8007b9e: d901 bls.n 8007ba4 - { - return HAL_TIMEOUT; - 8007ba0: 2303 movs r3, #3 - 8007ba2: e143 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8007ba4: 4b54 ldr r3, [pc, #336] @ (8007cf8 ) - 8007ba6: 6a1b ldr r3, [r3, #32] - 8007ba8: f003 0302 and.w r3, r3, #2 - 8007bac: 2b00 cmp r3, #0 - 8007bae: d0ee beq.n 8007b8e - 8007bb0: e014 b.n 8007bdc - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007bb2: f7fd fe3f bl 8005834 - 8007bb6: 6138 str r0, [r7, #16] - - /* Wait till LSE is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8007bb8: e00a b.n 8007bd0 - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8007bba: f7fd fe3b bl 8005834 - 8007bbe: 4602 mov r2, r0 - 8007bc0: 693b ldr r3, [r7, #16] - 8007bc2: 1ad3 subs r3, r2, r3 - 8007bc4: f241 3288 movw r2, #5000 @ 0x1388 - 8007bc8: 4293 cmp r3, r2 - 8007bca: d901 bls.n 8007bd0 - { - return HAL_TIMEOUT; - 8007bcc: 2303 movs r3, #3 - 8007bce: e12d b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8007bd0: 4b49 ldr r3, [pc, #292] @ (8007cf8 ) - 8007bd2: 6a1b ldr r3, [r3, #32] - 8007bd4: f003 0302 and.w r3, r3, #2 - 8007bd8: 2b00 cmp r3, #0 - 8007bda: d1ee bne.n 8007bba - } - } - } - - /* Require to disable power clock if necessary */ - if (pwrclkchanged == SET) - 8007bdc: 7dfb ldrb r3, [r7, #23] - 8007bde: 2b01 cmp r3, #1 - 8007be0: d105 bne.n 8007bee - { - __HAL_RCC_PWR_CLK_DISABLE(); - 8007be2: 4b45 ldr r3, [pc, #276] @ (8007cf8 ) - 8007be4: 69db ldr r3, [r3, #28] - 8007be6: 4a44 ldr r2, [pc, #272] @ (8007cf8 ) - 8007be8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8007bec: 61d3 str r3, [r2, #28] - -#if defined(RCC_CR_PLL2ON) - /*-------------------------------- PLL2 Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); - if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) - 8007bee: 687b ldr r3, [r7, #4] - 8007bf0: 6adb ldr r3, [r3, #44] @ 0x2c - 8007bf2: 2b00 cmp r3, #0 - 8007bf4: f000 808c beq.w 8007d10 - { - /* This bit can not be cleared if the PLL2 clock is used indirectly as system - clock (i.e. it is used as PLL clock entry that is used as system clock). */ - if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ - 8007bf8: 4b3f ldr r3, [pc, #252] @ (8007cf8 ) - 8007bfa: 685b ldr r3, [r3, #4] - 8007bfc: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8007c00: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8007c04: d10e bne.n 8007c24 - (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ - 8007c06: 4b3c ldr r3, [pc, #240] @ (8007cf8 ) - 8007c08: 685b ldr r3, [r3, #4] - 8007c0a: f003 030c and.w r3, r3, #12 - if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ - 8007c0e: 2b08 cmp r3, #8 - 8007c10: d108 bne.n 8007c24 - ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) - 8007c12: 4b39 ldr r3, [pc, #228] @ (8007cf8 ) - 8007c14: 6adb ldr r3, [r3, #44] @ 0x2c - 8007c16: f403 3380 and.w r3, r3, #65536 @ 0x10000 - (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ - 8007c1a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8007c1e: d101 bne.n 8007c24 - { - return HAL_ERROR; - 8007c20: 2301 movs r3, #1 - 8007c22: e103 b.n 8007e2c - } - else - { - if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) - 8007c24: 687b ldr r3, [r7, #4] - 8007c26: 6adb ldr r3, [r3, #44] @ 0x2c - 8007c28: 2b02 cmp r3, #2 - 8007c2a: d14e bne.n 8007cca - assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); - assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLLI2S is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ - 8007c2c: 4b32 ldr r3, [pc, #200] @ (8007cf8 ) - 8007c2e: 681b ldr r3, [r3, #0] - 8007c30: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8007c34: 2b00 cmp r3, #0 - 8007c36: d009 beq.n 8007c4c - (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) - 8007c38: 4b2f ldr r3, [pc, #188] @ (8007cf8 ) - 8007c3a: 6adb ldr r3, [r3, #44] @ 0x2c - 8007c3c: f003 02f0 and.w r2, r3, #240 @ 0xf0 - 8007c40: 687b ldr r3, [r7, #4] - 8007c42: 6b5b ldr r3, [r3, #52] @ 0x34 - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ - 8007c44: 429a cmp r2, r3 - 8007c46: d001 beq.n 8007c4c - { - return HAL_ERROR; - 8007c48: 2301 movs r3, #1 - 8007c4a: e0ef b.n 8007e2c - } - - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - 8007c4c: 4b2c ldr r3, [pc, #176] @ (8007d00 ) - 8007c4e: 2200 movs r2, #0 - 8007c50: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007c52: f7fd fdef bl 8005834 - 8007c56: 6138 str r0, [r7, #16] - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - 8007c58: e008 b.n 8007c6c - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - 8007c5a: f7fd fdeb bl 8005834 - 8007c5e: 4602 mov r2, r0 - 8007c60: 693b ldr r3, [r7, #16] - 8007c62: 1ad3 subs r3, r2, r3 - 8007c64: 2b64 cmp r3, #100 @ 0x64 - 8007c66: d901 bls.n 8007c6c - { - return HAL_TIMEOUT; - 8007c68: 2303 movs r3, #3 - 8007c6a: e0df b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - 8007c6c: 4b22 ldr r3, [pc, #136] @ (8007cf8 ) - 8007c6e: 681b ldr r3, [r3, #0] - 8007c70: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - 8007c74: 2b00 cmp r3, #0 - 8007c76: d1f0 bne.n 8007c5a - } - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); - 8007c78: 4b1f ldr r3, [pc, #124] @ (8007cf8 ) - 8007c7a: 6adb ldr r3, [r3, #44] @ 0x2c - 8007c7c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 8007c80: 687b ldr r3, [r7, #4] - 8007c82: 6b5b ldr r3, [r3, #52] @ 0x34 - 8007c84: 491c ldr r1, [pc, #112] @ (8007cf8 ) - 8007c86: 4313 orrs r3, r2 - 8007c88: 62cb str r3, [r1, #44] @ 0x2c - - /* Configure the main PLL2 multiplication factors. */ - __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); - 8007c8a: 4b1b ldr r3, [pc, #108] @ (8007cf8 ) - 8007c8c: 6adb ldr r3, [r3, #44] @ 0x2c - 8007c8e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 - 8007c92: 687b ldr r3, [r7, #4] - 8007c94: 6b1b ldr r3, [r3, #48] @ 0x30 - 8007c96: 4918 ldr r1, [pc, #96] @ (8007cf8 ) - 8007c98: 4313 orrs r3, r2 - 8007c9a: 62cb str r3, [r1, #44] @ 0x2c - - /* Enable the main PLL2. */ - __HAL_RCC_PLL2_ENABLE(); - 8007c9c: 4b18 ldr r3, [pc, #96] @ (8007d00 ) - 8007c9e: 2201 movs r2, #1 - 8007ca0: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007ca2: f7fd fdc7 bl 8005834 - 8007ca6: 6138 str r0, [r7, #16] - - /* Wait till PLL2 is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) - 8007ca8: e008 b.n 8007cbc - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - 8007caa: f7fd fdc3 bl 8005834 - 8007cae: 4602 mov r2, r0 - 8007cb0: 693b ldr r3, [r7, #16] - 8007cb2: 1ad3 subs r3, r2, r3 - 8007cb4: 2b64 cmp r3, #100 @ 0x64 - 8007cb6: d901 bls.n 8007cbc - { - return HAL_TIMEOUT; - 8007cb8: 2303 movs r3, #3 - 8007cba: e0b7 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) - 8007cbc: 4b0e ldr r3, [pc, #56] @ (8007cf8 ) - 8007cbe: 681b ldr r3, [r3, #0] - 8007cc0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - 8007cc4: 2b00 cmp r3, #0 - 8007cc6: d0f0 beq.n 8007caa - 8007cc8: e022 b.n 8007d10 - } - } - else - { - /* Set PREDIV1 source to HSE */ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); - 8007cca: 4b0b ldr r3, [pc, #44] @ (8007cf8 ) - 8007ccc: 6adb ldr r3, [r3, #44] @ 0x2c - 8007cce: 4a0a ldr r2, [pc, #40] @ (8007cf8 ) - 8007cd0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8007cd4: 62d3 str r3, [r2, #44] @ 0x2c - - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - 8007cd6: 4b0a ldr r3, [pc, #40] @ (8007d00 ) - 8007cd8: 2200 movs r2, #0 - 8007cda: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007cdc: f7fd fdaa bl 8005834 - 8007ce0: 6138 str r0, [r7, #16] - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - 8007ce2: e00f b.n 8007d04 - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - 8007ce4: f7fd fda6 bl 8005834 - 8007ce8: 4602 mov r2, r0 - 8007cea: 693b ldr r3, [r7, #16] - 8007cec: 1ad3 subs r3, r2, r3 - 8007cee: 2b64 cmp r3, #100 @ 0x64 - 8007cf0: d908 bls.n 8007d04 - { - return HAL_TIMEOUT; - 8007cf2: 2303 movs r3, #3 - 8007cf4: e09a b.n 8007e2c - 8007cf6: bf00 nop - 8007cf8: 40021000 .word 0x40021000 - 8007cfc: 40007000 .word 0x40007000 - 8007d00: 42420068 .word 0x42420068 - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - 8007d04: 4b4b ldr r3, [pc, #300] @ (8007e34 ) - 8007d06: 681b ldr r3, [r3, #0] - 8007d08: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 - 8007d0c: 2b00 cmp r3, #0 - 8007d0e: d1e9 bne.n 8007ce4 - -#endif /* RCC_CR_PLL2ON */ - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 8007d10: 687b ldr r3, [r7, #4] - 8007d12: 6a1b ldr r3, [r3, #32] - 8007d14: 2b00 cmp r3, #0 - 8007d16: f000 8088 beq.w 8007e2a - { - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8007d1a: 4b46 ldr r3, [pc, #280] @ (8007e34 ) - 8007d1c: 685b ldr r3, [r3, #4] - 8007d1e: f003 030c and.w r3, r3, #12 - 8007d22: 2b08 cmp r3, #8 - 8007d24: d068 beq.n 8007df8 - { - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 8007d26: 687b ldr r3, [r7, #4] - 8007d28: 6a1b ldr r3, [r3, #32] - 8007d2a: 2b02 cmp r3, #2 - 8007d2c: d14d bne.n 8007dca - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 8007d2e: 4b42 ldr r3, [pc, #264] @ (8007e38 ) - 8007d30: 2200 movs r2, #0 - 8007d32: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007d34: f7fd fd7e bl 8005834 - 8007d38: 6138 str r0, [r7, #16] - - /* Wait till PLL is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8007d3a: e008 b.n 8007d4e - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8007d3c: f7fd fd7a bl 8005834 - 8007d40: 4602 mov r2, r0 - 8007d42: 693b ldr r3, [r7, #16] - 8007d44: 1ad3 subs r3, r2, r3 - 8007d46: 2b02 cmp r3, #2 - 8007d48: d901 bls.n 8007d4e - { - return HAL_TIMEOUT; - 8007d4a: 2303 movs r3, #3 - 8007d4c: e06e b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8007d4e: 4b39 ldr r3, [pc, #228] @ (8007e34 ) - 8007d50: 681b ldr r3, [r3, #0] - 8007d52: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8007d56: 2b00 cmp r3, #0 - 8007d58: d1f0 bne.n 8007d3c - } - } - - /* Configure the HSE prediv factor --------------------------------*/ - /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ - if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) - 8007d5a: 687b ldr r3, [r7, #4] - 8007d5c: 6a5b ldr r3, [r3, #36] @ 0x24 - 8007d5e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8007d62: d10f bne.n 8007d84 - assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); -#if defined(RCC_CFGR2_PREDIV1SRC) - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); - - /* Set PREDIV1 source */ - SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); - 8007d64: 4b33 ldr r3, [pc, #204] @ (8007e34 ) - 8007d66: 6ada ldr r2, [r3, #44] @ 0x2c - 8007d68: 687b ldr r3, [r7, #4] - 8007d6a: 685b ldr r3, [r3, #4] - 8007d6c: 4931 ldr r1, [pc, #196] @ (8007e34 ) - 8007d6e: 4313 orrs r3, r2 - 8007d70: 62cb str r3, [r1, #44] @ 0x2c -#endif /* RCC_CFGR2_PREDIV1SRC */ - - /* Set PREDIV1 Value */ - __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); - 8007d72: 4b30 ldr r3, [pc, #192] @ (8007e34 ) - 8007d74: 6adb ldr r3, [r3, #44] @ 0x2c - 8007d76: f023 020f bic.w r2, r3, #15 - 8007d7a: 687b ldr r3, [r7, #4] - 8007d7c: 68db ldr r3, [r3, #12] - 8007d7e: 492d ldr r1, [pc, #180] @ (8007e34 ) - 8007d80: 4313 orrs r3, r2 - 8007d82: 62cb str r3, [r1, #44] @ 0x2c - } - - /* Configure the main PLL clock source and multiplication factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 8007d84: 4b2b ldr r3, [pc, #172] @ (8007e34 ) - 8007d86: 685b ldr r3, [r3, #4] - 8007d88: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 - 8007d8c: 687b ldr r3, [r7, #4] - 8007d8e: 6a59 ldr r1, [r3, #36] @ 0x24 - 8007d90: 687b ldr r3, [r7, #4] - 8007d92: 6a9b ldr r3, [r3, #40] @ 0x28 - 8007d94: 430b orrs r3, r1 - 8007d96: 4927 ldr r1, [pc, #156] @ (8007e34 ) - 8007d98: 4313 orrs r3, r2 - 8007d9a: 604b str r3, [r1, #4] - RCC_OscInitStruct->PLL.PLLMUL); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - 8007d9c: 4b26 ldr r3, [pc, #152] @ (8007e38 ) - 8007d9e: 2201 movs r2, #1 - 8007da0: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007da2: f7fd fd47 bl 8005834 - 8007da6: 6138 str r0, [r7, #16] - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8007da8: e008 b.n 8007dbc - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8007daa: f7fd fd43 bl 8005834 - 8007dae: 4602 mov r2, r0 - 8007db0: 693b ldr r3, [r7, #16] - 8007db2: 1ad3 subs r3, r2, r3 - 8007db4: 2b02 cmp r3, #2 - 8007db6: d901 bls.n 8007dbc - { - return HAL_TIMEOUT; - 8007db8: 2303 movs r3, #3 - 8007dba: e037 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8007dbc: 4b1d ldr r3, [pc, #116] @ (8007e34 ) - 8007dbe: 681b ldr r3, [r3, #0] - 8007dc0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8007dc4: 2b00 cmp r3, #0 - 8007dc6: d0f0 beq.n 8007daa - 8007dc8: e02f b.n 8007e2a - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 8007dca: 4b1b ldr r3, [pc, #108] @ (8007e38 ) - 8007dcc: 2200 movs r2, #0 - 8007dce: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007dd0: f7fd fd30 bl 8005834 - 8007dd4: 6138 str r0, [r7, #16] - - /* Wait till PLL is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8007dd6: e008 b.n 8007dea - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8007dd8: f7fd fd2c bl 8005834 - 8007ddc: 4602 mov r2, r0 - 8007dde: 693b ldr r3, [r7, #16] - 8007de0: 1ad3 subs r3, r2, r3 - 8007de2: 2b02 cmp r3, #2 - 8007de4: d901 bls.n 8007dea - { - return HAL_TIMEOUT; - 8007de6: 2303 movs r3, #3 - 8007de8: e020 b.n 8007e2c - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8007dea: 4b12 ldr r3, [pc, #72] @ (8007e34 ) - 8007dec: 681b ldr r3, [r3, #0] - 8007dee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8007df2: 2b00 cmp r3, #0 - 8007df4: d1f0 bne.n 8007dd8 - 8007df6: e018 b.n 8007e2a - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 8007df8: 687b ldr r3, [r7, #4] - 8007dfa: 6a1b ldr r3, [r3, #32] - 8007dfc: 2b01 cmp r3, #1 - 8007dfe: d101 bne.n 8007e04 - { - return HAL_ERROR; - 8007e00: 2301 movs r3, #1 - 8007e02: e013 b.n 8007e2c - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->CFGR; - 8007e04: 4b0b ldr r3, [pc, #44] @ (8007e34 ) - 8007e06: 685b ldr r3, [r3, #4] - 8007e08: 60fb str r3, [r7, #12] - if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8007e0a: 68fb ldr r3, [r7, #12] - 8007e0c: f403 3280 and.w r2, r3, #65536 @ 0x10000 - 8007e10: 687b ldr r3, [r7, #4] - 8007e12: 6a5b ldr r3, [r3, #36] @ 0x24 - 8007e14: 429a cmp r2, r3 - 8007e16: d106 bne.n 8007e26 - (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) - 8007e18: 68fb ldr r3, [r7, #12] - 8007e1a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 - 8007e1e: 687b ldr r3, [r7, #4] - 8007e20: 6a9b ldr r3, [r3, #40] @ 0x28 - if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8007e22: 429a cmp r2, r3 - 8007e24: d001 beq.n 8007e2a - { - return HAL_ERROR; - 8007e26: 2301 movs r3, #1 - 8007e28: e000 b.n 8007e2c - } - } - } - } - - return HAL_OK; - 8007e2a: 2300 movs r3, #0 -} - 8007e2c: 4618 mov r0, r3 - 8007e2e: 3718 adds r7, #24 - 8007e30: 46bd mov sp, r7 - 8007e32: bd80 pop {r7, pc} - 8007e34: 40021000 .word 0x40021000 - 8007e38: 42420060 .word 0x42420060 - -08007e3c : - * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - 8007e3c: b580 push {r7, lr} - 8007e3e: b084 sub sp, #16 - 8007e40: af00 add r7, sp, #0 - 8007e42: 6078 str r0, [r7, #4] - 8007e44: 6039 str r1, [r7, #0] - uint32_t tickstart; - - /* Check Null pointer */ - if (RCC_ClkInitStruct == NULL) - 8007e46: 687b ldr r3, [r7, #4] - 8007e48: 2b00 cmp r3, #0 - 8007e4a: d101 bne.n 8007e50 - { - return HAL_ERROR; - 8007e4c: 2301 movs r3, #1 - 8007e4e: e0d0 b.n 8007ff2 - must be correctly programmed according to the frequency of the CPU clock - (HCLK) of the device. */ - -#if defined(FLASH_ACR_LATENCY) - /* Increasing the number of wait states because of higher CPU frequency */ - if (FLatency > __HAL_FLASH_GET_LATENCY()) - 8007e50: 4b6a ldr r3, [pc, #424] @ (8007ffc ) - 8007e52: 681b ldr r3, [r3, #0] - 8007e54: f003 0307 and.w r3, r3, #7 - 8007e58: 683a ldr r2, [r7, #0] - 8007e5a: 429a cmp r2, r3 - 8007e5c: d910 bls.n 8007e80 - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 8007e5e: 4b67 ldr r3, [pc, #412] @ (8007ffc ) - 8007e60: 681b ldr r3, [r3, #0] - 8007e62: f023 0207 bic.w r2, r3, #7 - 8007e66: 4965 ldr r1, [pc, #404] @ (8007ffc ) - 8007e68: 683b ldr r3, [r7, #0] - 8007e6a: 4313 orrs r3, r2 - 8007e6c: 600b str r3, [r1, #0] - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - 8007e6e: 4b63 ldr r3, [pc, #396] @ (8007ffc ) - 8007e70: 681b ldr r3, [r3, #0] - 8007e72: f003 0307 and.w r3, r3, #7 - 8007e76: 683a ldr r2, [r7, #0] - 8007e78: 429a cmp r2, r3 - 8007e7a: d001 beq.n 8007e80 - { - return HAL_ERROR; - 8007e7c: 2301 movs r3, #1 - 8007e7e: e0b8 b.n 8007ff2 - } -} - -#endif /* FLASH_ACR_LATENCY */ -/*-------------------------- HCLK Configuration --------------------------*/ -if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8007e80: 687b ldr r3, [r7, #4] - 8007e82: 681b ldr r3, [r3, #0] - 8007e84: f003 0302 and.w r3, r3, #2 - 8007e88: 2b00 cmp r3, #0 - 8007e8a: d020 beq.n 8007ece - { - /* Set the highest APBx dividers in order to ensure that we do not go through - a non-spec phase whatever we decrease or increase HCLK. */ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8007e8c: 687b ldr r3, [r7, #4] - 8007e8e: 681b ldr r3, [r3, #0] - 8007e90: f003 0304 and.w r3, r3, #4 - 8007e94: 2b00 cmp r3, #0 - 8007e96: d005 beq.n 8007ea4 - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 8007e98: 4b59 ldr r3, [pc, #356] @ (8008000 ) - 8007e9a: 685b ldr r3, [r3, #4] - 8007e9c: 4a58 ldr r2, [pc, #352] @ (8008000 ) - 8007e9e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 - 8007ea2: 6053 str r3, [r2, #4] - } - - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8007ea4: 687b ldr r3, [r7, #4] - 8007ea6: 681b ldr r3, [r3, #0] - 8007ea8: f003 0308 and.w r3, r3, #8 - 8007eac: 2b00 cmp r3, #0 - 8007eae: d005 beq.n 8007ebc - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8007eb0: 4b53 ldr r3, [pc, #332] @ (8008000 ) - 8007eb2: 685b ldr r3, [r3, #4] - 8007eb4: 4a52 ldr r2, [pc, #328] @ (8008000 ) - 8007eb6: f443 5360 orr.w r3, r3, #14336 @ 0x3800 - 8007eba: 6053 str r3, [r2, #4] - } - - /* Set the new HCLK clock divider */ - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 8007ebc: 4b50 ldr r3, [pc, #320] @ (8008000 ) - 8007ebe: 685b ldr r3, [r3, #4] - 8007ec0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 8007ec4: 687b ldr r3, [r7, #4] - 8007ec6: 689b ldr r3, [r3, #8] - 8007ec8: 494d ldr r1, [pc, #308] @ (8008000 ) - 8007eca: 4313 orrs r3, r2 - 8007ecc: 604b str r3, [r1, #4] - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8007ece: 687b ldr r3, [r7, #4] - 8007ed0: 681b ldr r3, [r3, #0] - 8007ed2: f003 0301 and.w r3, r3, #1 - 8007ed6: 2b00 cmp r3, #0 - 8007ed8: d040 beq.n 8007f5c - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8007eda: 687b ldr r3, [r7, #4] - 8007edc: 685b ldr r3, [r3, #4] - 8007ede: 2b01 cmp r3, #1 - 8007ee0: d107 bne.n 8007ef2 - { - /* Check the HSE ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8007ee2: 4b47 ldr r3, [pc, #284] @ (8008000 ) - 8007ee4: 681b ldr r3, [r3, #0] - 8007ee6: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8007eea: 2b00 cmp r3, #0 - 8007eec: d115 bne.n 8007f1a - { - return HAL_ERROR; - 8007eee: 2301 movs r3, #1 - 8007ef0: e07f b.n 8007ff2 - } - } - /* PLL is selected as System Clock Source */ - else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8007ef2: 687b ldr r3, [r7, #4] - 8007ef4: 685b ldr r3, [r3, #4] - 8007ef6: 2b02 cmp r3, #2 - 8007ef8: d107 bne.n 8007f0a - { - /* Check the PLL ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8007efa: 4b41 ldr r3, [pc, #260] @ (8008000 ) - 8007efc: 681b ldr r3, [r3, #0] - 8007efe: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8007f02: 2b00 cmp r3, #0 - 8007f04: d109 bne.n 8007f1a - { - return HAL_ERROR; - 8007f06: 2301 movs r3, #1 - 8007f08: e073 b.n 8007ff2 - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8007f0a: 4b3d ldr r3, [pc, #244] @ (8008000 ) - 8007f0c: 681b ldr r3, [r3, #0] - 8007f0e: f003 0302 and.w r3, r3, #2 - 8007f12: 2b00 cmp r3, #0 - 8007f14: d101 bne.n 8007f1a - { - return HAL_ERROR; - 8007f16: 2301 movs r3, #1 - 8007f18: e06b b.n 8007ff2 - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8007f1a: 4b39 ldr r3, [pc, #228] @ (8008000 ) - 8007f1c: 685b ldr r3, [r3, #4] - 8007f1e: f023 0203 bic.w r2, r3, #3 - 8007f22: 687b ldr r3, [r7, #4] - 8007f24: 685b ldr r3, [r3, #4] - 8007f26: 4936 ldr r1, [pc, #216] @ (8008000 ) - 8007f28: 4313 orrs r3, r2 - 8007f2a: 604b str r3, [r1, #4] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8007f2c: f7fd fc82 bl 8005834 - 8007f30: 60f8 str r0, [r7, #12] - - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8007f32: e00a b.n 8007f4a - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8007f34: f7fd fc7e bl 8005834 - 8007f38: 4602 mov r2, r0 - 8007f3a: 68fb ldr r3, [r7, #12] - 8007f3c: 1ad3 subs r3, r2, r3 - 8007f3e: f241 3288 movw r2, #5000 @ 0x1388 - 8007f42: 4293 cmp r3, r2 - 8007f44: d901 bls.n 8007f4a - { - return HAL_TIMEOUT; - 8007f46: 2303 movs r3, #3 - 8007f48: e053 b.n 8007ff2 - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8007f4a: 4b2d ldr r3, [pc, #180] @ (8008000 ) - 8007f4c: 685b ldr r3, [r3, #4] - 8007f4e: f003 020c and.w r2, r3, #12 - 8007f52: 687b ldr r3, [r7, #4] - 8007f54: 685b ldr r3, [r3, #4] - 8007f56: 009b lsls r3, r3, #2 - 8007f58: 429a cmp r2, r3 - 8007f5a: d1eb bne.n 8007f34 - } - } - -#if defined(FLASH_ACR_LATENCY) - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - 8007f5c: 4b27 ldr r3, [pc, #156] @ (8007ffc ) - 8007f5e: 681b ldr r3, [r3, #0] - 8007f60: f003 0307 and.w r3, r3, #7 - 8007f64: 683a ldr r2, [r7, #0] - 8007f66: 429a cmp r2, r3 - 8007f68: d210 bcs.n 8007f8c - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 8007f6a: 4b24 ldr r3, [pc, #144] @ (8007ffc ) - 8007f6c: 681b ldr r3, [r3, #0] - 8007f6e: f023 0207 bic.w r2, r3, #7 - 8007f72: 4922 ldr r1, [pc, #136] @ (8007ffc ) - 8007f74: 683b ldr r3, [r7, #0] - 8007f76: 4313 orrs r3, r2 - 8007f78: 600b str r3, [r1, #0] - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - 8007f7a: 4b20 ldr r3, [pc, #128] @ (8007ffc ) - 8007f7c: 681b ldr r3, [r3, #0] - 8007f7e: f003 0307 and.w r3, r3, #7 - 8007f82: 683a ldr r2, [r7, #0] - 8007f84: 429a cmp r2, r3 - 8007f86: d001 beq.n 8007f8c - { - return HAL_ERROR; - 8007f88: 2301 movs r3, #1 - 8007f8a: e032 b.n 8007ff2 - } -} -#endif /* FLASH_ACR_LATENCY */ - -/*-------------------------- PCLK1 Configuration ---------------------------*/ -if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8007f8c: 687b ldr r3, [r7, #4] - 8007f8e: 681b ldr r3, [r3, #0] - 8007f90: f003 0304 and.w r3, r3, #4 - 8007f94: 2b00 cmp r3, #0 - 8007f96: d008 beq.n 8007faa - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8007f98: 4b19 ldr r3, [pc, #100] @ (8008000 ) - 8007f9a: 685b ldr r3, [r3, #4] - 8007f9c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 - 8007fa0: 687b ldr r3, [r7, #4] - 8007fa2: 68db ldr r3, [r3, #12] - 8007fa4: 4916 ldr r1, [pc, #88] @ (8008000 ) - 8007fa6: 4313 orrs r3, r2 - 8007fa8: 604b str r3, [r1, #4] - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8007faa: 687b ldr r3, [r7, #4] - 8007fac: 681b ldr r3, [r3, #0] - 8007fae: f003 0308 and.w r3, r3, #8 - 8007fb2: 2b00 cmp r3, #0 - 8007fb4: d009 beq.n 8007fca - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - 8007fb6: 4b12 ldr r3, [pc, #72] @ (8008000 ) - 8007fb8: 685b ldr r3, [r3, #4] - 8007fba: f423 5260 bic.w r2, r3, #14336 @ 0x3800 - 8007fbe: 687b ldr r3, [r7, #4] - 8007fc0: 691b ldr r3, [r3, #16] - 8007fc2: 00db lsls r3, r3, #3 - 8007fc4: 490e ldr r1, [pc, #56] @ (8008000 ) - 8007fc6: 4313 orrs r3, r2 - 8007fc8: 604b str r3, [r1, #4] - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - 8007fca: f000 f821 bl 8008010 - 8007fce: 4602 mov r2, r0 - 8007fd0: 4b0b ldr r3, [pc, #44] @ (8008000 ) - 8007fd2: 685b ldr r3, [r3, #4] - 8007fd4: 091b lsrs r3, r3, #4 - 8007fd6: f003 030f and.w r3, r3, #15 - 8007fda: 490a ldr r1, [pc, #40] @ (8008004 ) - 8007fdc: 5ccb ldrb r3, [r1, r3] - 8007fde: fa22 f303 lsr.w r3, r2, r3 - 8007fe2: 4a09 ldr r2, [pc, #36] @ (8008008 ) - 8007fe4: 6013 str r3, [r2, #0] - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick(uwTickPrio); - 8007fe6: 4b09 ldr r3, [pc, #36] @ (800800c ) - 8007fe8: 681b ldr r3, [r3, #0] - 8007fea: 4618 mov r0, r3 - 8007fec: f7fd fbe0 bl 80057b0 - - return HAL_OK; - 8007ff0: 2300 movs r3, #0 -} - 8007ff2: 4618 mov r0, r3 - 8007ff4: 3710 adds r7, #16 - 8007ff6: 46bd mov sp, r7 - 8007ff8: bd80 pop {r7, pc} - 8007ffa: bf00 nop - 8007ffc: 40022000 .word 0x40022000 - 8008000: 40021000 .word 0x40021000 - 8008004: 0800dfec .word 0x0800dfec - 8008008: 20000008 .word 0x20000008 - 800800c: 2000000c .word 0x2000000c - -08008010 : - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - 8008010: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8008014: b099 sub sp, #100 @ 0x64 - 8008016: af00 add r7, sp, #0 -#if defined(RCC_CFGR2_PREDIV1SRC) - const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; - 8008018: 4b66 ldr r3, [pc, #408] @ (80081b4 ) - 800801a: f107 0434 add.w r4, r7, #52 @ 0x34 - 800801e: cb0f ldmia r3, {r0, r1, r2, r3} - 8008020: c407 stmia r4!, {r0, r1, r2} - 8008022: 8023 strh r3, [r4, #0] - const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; - 8008024: 4b64 ldr r3, [pc, #400] @ (80081b8 ) - 8008026: f107 0424 add.w r4, r7, #36 @ 0x24 - 800802a: cb0f ldmia r3, {r0, r1, r2, r3} - 800802c: e884 000f stmia.w r4, {r0, r1, r2, r3} -#else - const uint8_t aPredivFactorTable[2] = {1, 2}; -#endif /*RCC_CFGR2_PREDIV1*/ - -#endif - uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - 8008030: 2300 movs r3, #0 - 8008032: 657b str r3, [r7, #84] @ 0x54 - 8008034: 2300 movs r3, #0 - 8008036: 653b str r3, [r7, #80] @ 0x50 - 8008038: 2300 movs r3, #0 - 800803a: 65fb str r3, [r7, #92] @ 0x5c - 800803c: 2300 movs r3, #0 - 800803e: 64fb str r3, [r7, #76] @ 0x4c - uint32_t sysclockfreq = 0U; - 8008040: 2300 movs r3, #0 - 8008042: 65bb str r3, [r7, #88] @ 0x58 -#if defined(RCC_CFGR2_PREDIV1SRC) - uint32_t prediv2 = 0U, pll2mul = 0U; - 8008044: 2300 movs r3, #0 - 8008046: 64bb str r3, [r7, #72] @ 0x48 - 8008048: 2300 movs r3, #0 - 800804a: 647b str r3, [r7, #68] @ 0x44 -#endif /*RCC_CFGR2_PREDIV1SRC*/ - - tmpreg = RCC->CFGR; - 800804c: 4b5b ldr r3, [pc, #364] @ (80081bc ) - 800804e: 685b ldr r3, [r3, #4] - 8008050: 657b str r3, [r7, #84] @ 0x54 - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - 8008052: 6d7b ldr r3, [r7, #84] @ 0x54 - 8008054: f003 030c and.w r3, r3, #12 - 8008058: 2b04 cmp r3, #4 - 800805a: d002 beq.n 8008062 - 800805c: 2b08 cmp r3, #8 - 800805e: d003 beq.n 8008068 - 8008060: e09f b.n 80081a2 - { - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - 8008062: 4b57 ldr r3, [pc, #348] @ (80081c0 ) - 8008064: 65bb str r3, [r7, #88] @ 0x58 - break; - 8008066: e09f b.n 80081a8 - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ - { - pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; - 8008068: 6d7b ldr r3, [r7, #84] @ 0x54 - 800806a: 0c9b lsrs r3, r3, #18 - 800806c: f003 030f and.w r3, r3, #15 - 8008070: 3340 adds r3, #64 @ 0x40 - 8008072: f107 0220 add.w r2, r7, #32 - 8008076: 4413 add r3, r2 - 8008078: f813 3c2c ldrb.w r3, [r3, #-44] - 800807c: 64fb str r3, [r7, #76] @ 0x4c - if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) - 800807e: 6d7b ldr r3, [r7, #84] @ 0x54 - 8008080: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8008084: 2b00 cmp r3, #0 - 8008086: f000 8084 beq.w 8008192 - { -#if defined(RCC_CFGR2_PREDIV1) - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; - 800808a: 4b4c ldr r3, [pc, #304] @ (80081bc ) - 800808c: 6adb ldr r3, [r3, #44] @ 0x2c - 800808e: f003 030f and.w r3, r3, #15 - 8008092: 3340 adds r3, #64 @ 0x40 - 8008094: f107 0220 add.w r2, r7, #32 - 8008098: 4413 add r3, r2 - 800809a: f813 3c3c ldrb.w r3, [r3, #-60] - 800809e: 653b str r3, [r7, #80] @ 0x50 -#else - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; -#endif /*RCC_CFGR2_PREDIV1*/ -#if defined(RCC_CFGR2_PREDIV1SRC) - - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) - 80080a0: 4b46 ldr r3, [pc, #280] @ (80081bc ) - 80080a2: 6adb ldr r3, [r3, #44] @ 0x2c - 80080a4: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 80080a8: 2b00 cmp r3, #0 - 80080aa: d060 beq.n 800816e - { - /* PLL2 selected as Prediv1 source */ - /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - 80080ac: 4b43 ldr r3, [pc, #268] @ (80081bc ) - 80080ae: 6adb ldr r3, [r3, #44] @ 0x2c - 80080b0: 091b lsrs r3, r3, #4 - 80080b2: f003 030f and.w r3, r3, #15 - 80080b6: 3301 adds r3, #1 - 80080b8: 64bb str r3, [r7, #72] @ 0x48 - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; - 80080ba: 4b40 ldr r3, [pc, #256] @ (80081bc ) - 80080bc: 6adb ldr r3, [r3, #44] @ 0x2c - 80080be: 0a1b lsrs r3, r3, #8 - 80080c0: f003 030f and.w r3, r3, #15 - 80080c4: 3302 adds r3, #2 - 80080c6: 647b str r3, [r7, #68] @ 0x44 - pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); - 80080c8: 6c7b ldr r3, [r7, #68] @ 0x44 - 80080ca: 2200 movs r2, #0 - 80080cc: 613b str r3, [r7, #16] - 80080ce: 617a str r2, [r7, #20] - 80080d0: 6cfb ldr r3, [r7, #76] @ 0x4c - 80080d2: 2200 movs r2, #0 - 80080d4: 61bb str r3, [r7, #24] - 80080d6: 61fa str r2, [r7, #28] - 80080d8: e9d7 3404 ldrd r3, r4, [r7, #16] - 80080dc: 4622 mov r2, r4 - 80080de: e9d7 0106 ldrd r0, r1, [r7, #24] - 80080e2: 4684 mov ip, r0 - 80080e4: fb0c f202 mul.w r2, ip, r2 - 80080e8: e9c7 0106 strd r0, r1, [r7, #24] - 80080ec: 468c mov ip, r1 - 80080ee: 4618 mov r0, r3 - 80080f0: 4621 mov r1, r4 - 80080f2: 4603 mov r3, r0 - 80080f4: fb03 f30c mul.w r3, r3, ip - 80080f8: 4413 add r3, r2 - 80080fa: 4602 mov r2, r0 - 80080fc: 69b9 ldr r1, [r7, #24] - 80080fe: fba2 8901 umull r8, r9, r2, r1 - 8008102: 444b add r3, r9 - 8008104: 4699 mov r9, r3 - 8008106: 4b2e ldr r3, [pc, #184] @ (80081c0 ) - 8008108: fb03 f209 mul.w r2, r3, r9 - 800810c: 2300 movs r3, #0 - 800810e: fb03 f308 mul.w r3, r3, r8 - 8008112: 4413 add r3, r2 - 8008114: 4a2a ldr r2, [pc, #168] @ (80081c0 ) - 8008116: fba8 ab02 umull sl, fp, r8, r2 - 800811a: 445b add r3, fp - 800811c: 469b mov fp, r3 - 800811e: 6cbb ldr r3, [r7, #72] @ 0x48 - 8008120: 2200 movs r2, #0 - 8008122: 60bb str r3, [r7, #8] - 8008124: 60fa str r2, [r7, #12] - 8008126: 6d3b ldr r3, [r7, #80] @ 0x50 - 8008128: 2200 movs r2, #0 - 800812a: 603b str r3, [r7, #0] - 800812c: 607a str r2, [r7, #4] - 800812e: e9d7 3402 ldrd r3, r4, [r7, #8] - 8008132: 4622 mov r2, r4 - 8008134: e9d7 8900 ldrd r8, r9, [r7] - 8008138: 4641 mov r1, r8 - 800813a: fb01 f202 mul.w r2, r1, r2 - 800813e: 46cc mov ip, r9 - 8008140: 4618 mov r0, r3 - 8008142: 4621 mov r1, r4 - 8008144: 4603 mov r3, r0 - 8008146: fb03 f30c mul.w r3, r3, ip - 800814a: 4413 add r3, r2 - 800814c: 4602 mov r2, r0 - 800814e: 4641 mov r1, r8 - 8008150: fba2 5601 umull r5, r6, r2, r1 - 8008154: 4433 add r3, r6 - 8008156: 461e mov r6, r3 - 8008158: 462a mov r2, r5 - 800815a: 4633 mov r3, r6 - 800815c: 4650 mov r0, sl - 800815e: 4659 mov r1, fp - 8008160: f7f9 f8a2 bl 80012a8 <__aeabi_uldivmod> - 8008164: 4602 mov r2, r0 - 8008166: 460b mov r3, r1 - 8008168: 4613 mov r3, r2 - 800816a: 65fb str r3, [r7, #92] @ 0x5c - 800816c: e007 b.n 800817e - } - else - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); - 800816e: 6cfb ldr r3, [r7, #76] @ 0x4c - 8008170: 4a13 ldr r2, [pc, #76] @ (80081c0 ) - 8008172: fb03 f202 mul.w r2, r3, r2 - 8008176: 6d3b ldr r3, [r7, #80] @ 0x50 - 8008178: fbb2 f3f3 udiv r3, r2, r3 - 800817c: 65fb str r3, [r7, #92] @ 0x5c - } - - /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ - /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) - 800817e: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 - 8008182: 461a mov r2, r3 - 8008184: 6cfb ldr r3, [r7, #76] @ 0x4c - 8008186: 4293 cmp r3, r2 - 8008188: d108 bne.n 800819c - { - pllclk = pllclk / 2; - 800818a: 6dfb ldr r3, [r7, #92] @ 0x5c - 800818c: 085b lsrs r3, r3, #1 - 800818e: 65fb str r3, [r7, #92] @ 0x5c - 8008190: e004 b.n 800819c -#endif /*RCC_CFGR2_PREDIV1SRC*/ - } - else - { - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); - 8008192: 6cfb ldr r3, [r7, #76] @ 0x4c - 8008194: 4a0b ldr r2, [pc, #44] @ (80081c4 ) - 8008196: fb02 f303 mul.w r3, r2, r3 - 800819a: 65fb str r3, [r7, #92] @ 0x5c - } - sysclockfreq = pllclk; - 800819c: 6dfb ldr r3, [r7, #92] @ 0x5c - 800819e: 65bb str r3, [r7, #88] @ 0x58 - break; - 80081a0: e002 b.n 80081a8 - } - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - default: /* HSI used as system clock */ - { - sysclockfreq = HSI_VALUE; - 80081a2: 4b09 ldr r3, [pc, #36] @ (80081c8 ) - 80081a4: 65bb str r3, [r7, #88] @ 0x58 - break; - 80081a6: bf00 nop - } - } - return sysclockfreq; - 80081a8: 6dbb ldr r3, [r7, #88] @ 0x58 -} - 80081aa: 4618 mov r0, r3 - 80081ac: 3764 adds r7, #100 @ 0x64 - 80081ae: 46bd mov sp, r7 - 80081b0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 80081b4: 0800dfa0 .word 0x0800dfa0 - 80081b8: 0800dfb0 .word 0x0800dfb0 - 80081bc: 40021000 .word 0x40021000 - 80081c0: 017d7840 .word 0x017d7840 - 80081c4: 003d0900 .word 0x003d0900 - 80081c8: 007a1200 .word 0x007a1200 - -080081cc : - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - 80081cc: b480 push {r7} - 80081ce: af00 add r7, sp, #0 - return SystemCoreClock; - 80081d0: 4b02 ldr r3, [pc, #8] @ (80081dc ) - 80081d2: 681b ldr r3, [r3, #0] -} - 80081d4: 4618 mov r0, r3 - 80081d6: 46bd mov sp, r7 - 80081d8: bc80 pop {r7} - 80081da: 4770 bx lr - 80081dc: 20000008 .word 0x20000008 - -080081e0 : - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - 80081e0: b580 push {r7, lr} - 80081e2: af00 add r7, sp, #0 - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); - 80081e4: f7ff fff2 bl 80081cc - 80081e8: 4602 mov r2, r0 - 80081ea: 4b05 ldr r3, [pc, #20] @ (8008200 ) - 80081ec: 685b ldr r3, [r3, #4] - 80081ee: 0a1b lsrs r3, r3, #8 - 80081f0: f003 0307 and.w r3, r3, #7 - 80081f4: 4903 ldr r1, [pc, #12] @ (8008204 ) - 80081f6: 5ccb ldrb r3, [r1, r3] - 80081f8: fa22 f303 lsr.w r3, r2, r3 -} - 80081fc: 4618 mov r0, r3 - 80081fe: bd80 pop {r7, pc} - 8008200: 40021000 .word 0x40021000 - 8008204: 0800dffc .word 0x0800dffc - -08008208 : - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - 8008208: b580 push {r7, lr} - 800820a: af00 add r7, sp, #0 - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); - 800820c: f7ff ffde bl 80081cc - 8008210: 4602 mov r2, r0 - 8008212: 4b05 ldr r3, [pc, #20] @ (8008228 ) - 8008214: 685b ldr r3, [r3, #4] - 8008216: 0adb lsrs r3, r3, #11 - 8008218: f003 0307 and.w r3, r3, #7 - 800821c: 4903 ldr r1, [pc, #12] @ (800822c ) - 800821e: 5ccb ldrb r3, [r1, r3] - 8008220: fa22 f303 lsr.w r3, r2, r3 -} - 8008224: 4618 mov r0, r3 - 8008226: bd80 pop {r7, pc} - 8008228: 40021000 .word 0x40021000 - 800822c: 0800dffc .word 0x0800dffc - -08008230 : - * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay: specifies the delay time length, in milliseconds. - * @retval None - */ -static void RCC_Delay(uint32_t mdelay) -{ - 8008230: b480 push {r7} - 8008232: b085 sub sp, #20 - 8008234: af00 add r7, sp, #0 - 8008236: 6078 str r0, [r7, #4] - __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - 8008238: 4b0a ldr r3, [pc, #40] @ (8008264 ) - 800823a: 681b ldr r3, [r3, #0] - 800823c: 4a0a ldr r2, [pc, #40] @ (8008268 ) - 800823e: fba2 2303 umull r2, r3, r2, r3 - 8008242: 0a5b lsrs r3, r3, #9 - 8008244: 687a ldr r2, [r7, #4] - 8008246: fb02 f303 mul.w r3, r2, r3 - 800824a: 60fb str r3, [r7, #12] - do - { - __NOP(); - 800824c: bf00 nop - } - while (Delay --); - 800824e: 68fb ldr r3, [r7, #12] - 8008250: 1e5a subs r2, r3, #1 - 8008252: 60fa str r2, [r7, #12] - 8008254: 2b00 cmp r3, #0 - 8008256: d1f9 bne.n 800824c -} - 8008258: bf00 nop - 800825a: bf00 nop - 800825c: 3714 adds r7, #20 - 800825e: 46bd mov sp, r7 - 8008260: bc80 pop {r7} - 8008262: 4770 bx lr - 8008264: 20000008 .word 0x20000008 - 8008268: 10624dd3 .word 0x10624dd3 - -0800826c : - * manually disable it. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - 800826c: b580 push {r7, lr} - 800826e: b088 sub sp, #32 - 8008270: af00 add r7, sp, #0 - 8008272: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U, temp_reg = 0U; - 8008274: 2300 movs r3, #0 - 8008276: 617b str r3, [r7, #20] - 8008278: 2300 movs r3, #0 - 800827a: 613b str r3, [r7, #16] -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t pllactive = 0U; - 800827c: 2300 movs r3, #0 - 800827e: 61fb str r3, [r7, #28] - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ - if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) - 8008280: 687b ldr r3, [r7, #4] - 8008282: 681b ldr r3, [r3, #0] - 8008284: f003 0301 and.w r3, r3, #1 - 8008288: 2b00 cmp r3, #0 - 800828a: d07d beq.n 8008388 - { - FlagStatus pwrclkchanged = RESET; - 800828c: 2300 movs r3, #0 - 800828e: 76fb strb r3, [r7, #27] - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8008290: 4b8b ldr r3, [pc, #556] @ (80084c0 ) - 8008292: 69db ldr r3, [r3, #28] - 8008294: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8008298: 2b00 cmp r3, #0 - 800829a: d10d bne.n 80082b8 - { - __HAL_RCC_PWR_CLK_ENABLE(); - 800829c: 4b88 ldr r3, [pc, #544] @ (80084c0 ) - 800829e: 69db ldr r3, [r3, #28] - 80082a0: 4a87 ldr r2, [pc, #540] @ (80084c0 ) - 80082a2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 80082a6: 61d3 str r3, [r2, #28] - 80082a8: 4b85 ldr r3, [pc, #532] @ (80084c0 ) - 80082aa: 69db ldr r3, [r3, #28] - 80082ac: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80082b0: 60fb str r3, [r7, #12] - 80082b2: 68fb ldr r3, [r7, #12] - pwrclkchanged = SET; - 80082b4: 2301 movs r3, #1 - 80082b6: 76fb strb r3, [r7, #27] - } - - if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80082b8: 4b82 ldr r3, [pc, #520] @ (80084c4 ) - 80082ba: 681b ldr r3, [r3, #0] - 80082bc: f403 7380 and.w r3, r3, #256 @ 0x100 - 80082c0: 2b00 cmp r3, #0 - 80082c2: d118 bne.n 80082f6 - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - 80082c4: 4b7f ldr r3, [pc, #508] @ (80084c4 ) - 80082c6: 681b ldr r3, [r3, #0] - 80082c8: 4a7e ldr r2, [pc, #504] @ (80084c4 ) - 80082ca: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80082ce: 6013 str r3, [r2, #0] - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - 80082d0: f7fd fab0 bl 8005834 - 80082d4: 6178 str r0, [r7, #20] - - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80082d6: e008 b.n 80082ea - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80082d8: f7fd faac bl 8005834 - 80082dc: 4602 mov r2, r0 - 80082de: 697b ldr r3, [r7, #20] - 80082e0: 1ad3 subs r3, r2, r3 - 80082e2: 2b64 cmp r3, #100 @ 0x64 - 80082e4: d901 bls.n 80082ea - { - return HAL_TIMEOUT; - 80082e6: 2303 movs r3, #3 - 80082e8: e0e5 b.n 80084b6 - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80082ea: 4b76 ldr r3, [pc, #472] @ (80084c4 ) - 80082ec: 681b ldr r3, [r3, #0] - 80082ee: f403 7380 and.w r3, r3, #256 @ 0x100 - 80082f2: 2b00 cmp r3, #0 - 80082f4: d0f0 beq.n 80082d8 - } - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - 80082f6: 4b72 ldr r3, [pc, #456] @ (80084c0 ) - 80082f8: 6a1b ldr r3, [r3, #32] - 80082fa: f403 7340 and.w r3, r3, #768 @ 0x300 - 80082fe: 613b str r3, [r7, #16] - if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - 8008300: 693b ldr r3, [r7, #16] - 8008302: 2b00 cmp r3, #0 - 8008304: d02e beq.n 8008364 - 8008306: 687b ldr r3, [r7, #4] - 8008308: 685b ldr r3, [r3, #4] - 800830a: f403 7340 and.w r3, r3, #768 @ 0x300 - 800830e: 693a ldr r2, [r7, #16] - 8008310: 429a cmp r2, r3 - 8008312: d027 beq.n 8008364 - { - /* Store the content of BDCR register before the reset of Backup Domain */ - temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - 8008314: 4b6a ldr r3, [pc, #424] @ (80084c0 ) - 8008316: 6a1b ldr r3, [r3, #32] - 8008318: f423 7340 bic.w r3, r3, #768 @ 0x300 - 800831c: 613b str r3, [r7, #16] - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - 800831e: 4b6a ldr r3, [pc, #424] @ (80084c8 ) - 8008320: 2201 movs r2, #1 - 8008322: 601a str r2, [r3, #0] - __HAL_RCC_BACKUPRESET_RELEASE(); - 8008324: 4b68 ldr r3, [pc, #416] @ (80084c8 ) - 8008326: 2200 movs r2, #0 - 8008328: 601a str r2, [r3, #0] - /* Restore the Content of BDCR register */ - RCC->BDCR = temp_reg; - 800832a: 4a65 ldr r2, [pc, #404] @ (80084c0 ) - 800832c: 693b ldr r3, [r7, #16] - 800832e: 6213 str r3, [r2, #32] - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - 8008330: 693b ldr r3, [r7, #16] - 8008332: f003 0301 and.w r3, r3, #1 - 8008336: 2b00 cmp r3, #0 - 8008338: d014 beq.n 8008364 - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 800833a: f7fd fa7b bl 8005834 - 800833e: 6178 str r0, [r7, #20] - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8008340: e00a b.n 8008358 - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8008342: f7fd fa77 bl 8005834 - 8008346: 4602 mov r2, r0 - 8008348: 697b ldr r3, [r7, #20] - 800834a: 1ad3 subs r3, r2, r3 - 800834c: f241 3288 movw r2, #5000 @ 0x1388 - 8008350: 4293 cmp r3, r2 - 8008352: d901 bls.n 8008358 - { - return HAL_TIMEOUT; - 8008354: 2303 movs r3, #3 - 8008356: e0ae b.n 80084b6 - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8008358: 4b59 ldr r3, [pc, #356] @ (80084c0 ) - 800835a: 6a1b ldr r3, [r3, #32] - 800835c: f003 0302 and.w r3, r3, #2 - 8008360: 2b00 cmp r3, #0 - 8008362: d0ee beq.n 8008342 - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8008364: 4b56 ldr r3, [pc, #344] @ (80084c0 ) - 8008366: 6a1b ldr r3, [r3, #32] - 8008368: f423 7240 bic.w r2, r3, #768 @ 0x300 - 800836c: 687b ldr r3, [r7, #4] - 800836e: 685b ldr r3, [r3, #4] - 8008370: 4953 ldr r1, [pc, #332] @ (80084c0 ) - 8008372: 4313 orrs r3, r2 - 8008374: 620b str r3, [r1, #32] - - /* Require to disable power clock if necessary */ - if (pwrclkchanged == SET) - 8008376: 7efb ldrb r3, [r7, #27] - 8008378: 2b01 cmp r3, #1 - 800837a: d105 bne.n 8008388 - { - __HAL_RCC_PWR_CLK_DISABLE(); - 800837c: 4b50 ldr r3, [pc, #320] @ (80084c0 ) - 800837e: 69db ldr r3, [r3, #28] - 8008380: 4a4f ldr r2, [pc, #316] @ (80084c0 ) - 8008382: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8008386: 61d3 str r3, [r2, #28] - } - } - - /*------------------------------ ADC clock Configuration ------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - 8008388: 687b ldr r3, [r7, #4] - 800838a: 681b ldr r3, [r3, #0] - 800838c: f003 0302 and.w r3, r3, #2 - 8008390: 2b00 cmp r3, #0 - 8008392: d008 beq.n 80083a6 - { - /* Check the parameters */ - assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); - - /* Configure the ADC clock source */ - __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - 8008394: 4b4a ldr r3, [pc, #296] @ (80084c0 ) - 8008396: 685b ldr r3, [r3, #4] - 8008398: f423 4240 bic.w r2, r3, #49152 @ 0xc000 - 800839c: 687b ldr r3, [r7, #4] - 800839e: 689b ldr r3, [r3, #8] - 80083a0: 4947 ldr r1, [pc, #284] @ (80084c0 ) - 80083a2: 4313 orrs r3, r2 - 80083a4: 604b str r3, [r1, #4] - } - -#if defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ I2S2 Configuration ------------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) - 80083a6: 687b ldr r3, [r7, #4] - 80083a8: 681b ldr r3, [r3, #0] - 80083aa: f003 0304 and.w r3, r3, #4 - 80083ae: 2b00 cmp r3, #0 - 80083b0: d008 beq.n 80083c4 - { - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); - - /* Configure the I2S2 clock source */ - __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); - 80083b2: 4b43 ldr r3, [pc, #268] @ (80084c0 ) - 80083b4: 6adb ldr r3, [r3, #44] @ 0x2c - 80083b6: f423 3200 bic.w r2, r3, #131072 @ 0x20000 - 80083ba: 687b ldr r3, [r7, #4] - 80083bc: 68db ldr r3, [r3, #12] - 80083be: 4940 ldr r1, [pc, #256] @ (80084c0 ) - 80083c0: 4313 orrs r3, r2 - 80083c2: 62cb str r3, [r1, #44] @ 0x2c - } - - /*------------------------------ I2S3 Configuration ------------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) - 80083c4: 687b ldr r3, [r7, #4] - 80083c6: 681b ldr r3, [r3, #0] - 80083c8: f003 0308 and.w r3, r3, #8 - 80083cc: 2b00 cmp r3, #0 - 80083ce: d008 beq.n 80083e2 - { - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); - - /* Configure the I2S3 clock source */ - __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); - 80083d0: 4b3b ldr r3, [pc, #236] @ (80084c0 ) - 80083d2: 6adb ldr r3, [r3, #44] @ 0x2c - 80083d4: f423 2280 bic.w r2, r3, #262144 @ 0x40000 - 80083d8: 687b ldr r3, [r7, #4] - 80083da: 691b ldr r3, [r3, #16] - 80083dc: 4938 ldr r1, [pc, #224] @ (80084c0 ) - 80083de: 4313 orrs r3, r2 - 80083e0: 62cb str r3, [r1, #44] @ 0x2c - } - - /*------------------------------ PLL I2S Configuration ----------------------*/ - /* Check that PLLI2S need to be enabled */ - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) - 80083e2: 4b37 ldr r3, [pc, #220] @ (80084c0 ) - 80083e4: 6adb ldr r3, [r3, #44] @ 0x2c - 80083e6: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80083ea: 2b00 cmp r3, #0 - 80083ec: d105 bne.n 80083fa - 80083ee: 4b34 ldr r3, [pc, #208] @ (80084c0 ) - 80083f0: 6adb ldr r3, [r3, #44] @ 0x2c - 80083f2: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 80083f6: 2b00 cmp r3, #0 - 80083f8: d001 beq.n 80083fe - { - /* Update flag to indicate that PLL I2S should be active */ - pllactive = 1; - 80083fa: 2301 movs r3, #1 - 80083fc: 61fb str r3, [r7, #28] - } - - /* Check if PLL I2S need to be enabled */ - if (pllactive == 1) - 80083fe: 69fb ldr r3, [r7, #28] - 8008400: 2b01 cmp r3, #1 - 8008402: d148 bne.n 8008496 - { - /* Enable PLL I2S only if not active */ - if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) - 8008404: 4b2e ldr r3, [pc, #184] @ (80084c0 ) - 8008406: 681b ldr r3, [r3, #0] - 8008408: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800840c: 2b00 cmp r3, #0 - 800840e: d138 bne.n 8008482 - assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); - assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLL2 is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ - 8008410: 4b2b ldr r3, [pc, #172] @ (80084c0 ) - 8008412: 681b ldr r3, [r3, #0] - 8008414: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 8008418: 2b00 cmp r3, #0 - 800841a: d009 beq.n 8008430 - (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) - 800841c: 4b28 ldr r3, [pc, #160] @ (80084c0 ) - 800841e: 6adb ldr r3, [r3, #44] @ 0x2c - 8008420: f003 02f0 and.w r2, r3, #240 @ 0xf0 - 8008424: 687b ldr r3, [r7, #4] - 8008426: 699b ldr r3, [r3, #24] - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ - 8008428: 429a cmp r2, r3 - 800842a: d001 beq.n 8008430 - { - return HAL_ERROR; - 800842c: 2301 movs r3, #1 - 800842e: e042 b.n 80084b6 - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); - 8008430: 4b23 ldr r3, [pc, #140] @ (80084c0 ) - 8008432: 6adb ldr r3, [r3, #44] @ 0x2c - 8008434: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 8008438: 687b ldr r3, [r7, #4] - 800843a: 699b ldr r3, [r3, #24] - 800843c: 4920 ldr r1, [pc, #128] @ (80084c0 ) - 800843e: 4313 orrs r3, r2 - 8008440: 62cb str r3, [r1, #44] @ 0x2c - - /* Configure the main PLLI2S multiplication factors. */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); - 8008442: 4b1f ldr r3, [pc, #124] @ (80084c0 ) - 8008444: 6adb ldr r3, [r3, #44] @ 0x2c - 8008446: f423 4270 bic.w r2, r3, #61440 @ 0xf000 - 800844a: 687b ldr r3, [r7, #4] - 800844c: 695b ldr r3, [r3, #20] - 800844e: 491c ldr r1, [pc, #112] @ (80084c0 ) - 8008450: 4313 orrs r3, r2 - 8008452: 62cb str r3, [r1, #44] @ 0x2c - - /* Enable the main PLLI2S. */ - __HAL_RCC_PLLI2S_ENABLE(); - 8008454: 4b1d ldr r3, [pc, #116] @ (80084cc ) - 8008456: 2201 movs r2, #1 - 8008458: 601a str r2, [r3, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 800845a: f7fd f9eb bl 8005834 - 800845e: 6178 str r0, [r7, #20] - - /* Wait till PLLI2S is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 8008460: e008 b.n 8008474 - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - 8008462: f7fd f9e7 bl 8005834 - 8008466: 4602 mov r2, r0 - 8008468: 697b ldr r3, [r7, #20] - 800846a: 1ad3 subs r3, r2, r3 - 800846c: 2b64 cmp r3, #100 @ 0x64 - 800846e: d901 bls.n 8008474 - { - return HAL_TIMEOUT; - 8008470: 2303 movs r3, #3 - 8008472: e020 b.n 80084b6 - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 8008474: 4b12 ldr r3, [pc, #72] @ (80084c0 ) - 8008476: 681b ldr r3, [r3, #0] - 8008478: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 - 800847c: 2b00 cmp r3, #0 - 800847e: d0f0 beq.n 8008462 - 8008480: e009 b.n 8008496 - } - } - else - { - /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ - if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) - 8008482: 4b0f ldr r3, [pc, #60] @ (80084c0 ) - 8008484: 6adb ldr r3, [r3, #44] @ 0x2c - 8008486: f403 4270 and.w r2, r3, #61440 @ 0xf000 - 800848a: 687b ldr r3, [r7, #4] - 800848c: 695b ldr r3, [r3, #20] - 800848e: 429a cmp r2, r3 - 8008490: d001 beq.n 8008496 - { - return HAL_ERROR; - 8008492: 2301 movs r3, #1 - 8008494: e00f b.n 80084b6 - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ USB clock Configuration ------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - 8008496: 687b ldr r3, [r7, #4] - 8008498: 681b ldr r3, [r3, #0] - 800849a: f003 0310 and.w r3, r3, #16 - 800849e: 2b00 cmp r3, #0 - 80084a0: d008 beq.n 80084b4 - { - /* Check the parameters */ - assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); - - /* Configure the USB clock source */ - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - 80084a2: 4b07 ldr r3, [pc, #28] @ (80084c0 ) - 80084a4: 685b ldr r3, [r3, #4] - 80084a6: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 - 80084aa: 687b ldr r3, [r7, #4] - 80084ac: 69db ldr r3, [r3, #28] - 80084ae: 4904 ldr r1, [pc, #16] @ (80084c0 ) - 80084b0: 4313 orrs r3, r2 - 80084b2: 604b str r3, [r1, #4] - } -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - - return HAL_OK; - 80084b4: 2300 movs r3, #0 -} - 80084b6: 4618 mov r0, r3 - 80084b8: 3720 adds r7, #32 - 80084ba: 46bd mov sp, r7 - 80084bc: bd80 pop {r7, pc} - 80084be: bf00 nop - 80084c0: 40021000 .word 0x40021000 - 80084c4: 40007000 .word 0x40007000 - 80084c8: 42420440 .word 0x42420440 - 80084cc: 42420070 .word 0x42420070 - -080084d0 : - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - * @retval Frequency in Hz (0: means that no available frequency for the peripheral) - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - 80084d0: b590 push {r4, r7, lr} - 80084d2: b093 sub sp, #76 @ 0x4c - 80084d4: af00 add r7, sp, #0 - 80084d6: 6078 str r0, [r7, #4] -#if defined(STM32F105xC) || defined(STM32F107xC) - const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; - 80084d8: 4ba7 ldr r3, [pc, #668] @ (8008778 ) - 80084da: f107 0418 add.w r4, r7, #24 - 80084de: cb0f ldmia r3, {r0, r1, r2, r3} - 80084e0: c407 stmia r4!, {r0, r1, r2} - 80084e2: 8023 strh r3, [r4, #0] - const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; - 80084e4: 4ba5 ldr r3, [pc, #660] @ (800877c ) - 80084e6: f107 0408 add.w r4, r7, #8 - 80084ea: cb0f ldmia r3, {r0, r1, r2, r3} - 80084ec: e884 000f stmia.w r4, {r0, r1, r2, r3} - - uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; - 80084f0: 2300 movs r3, #0 - 80084f2: 63fb str r3, [r7, #60] @ 0x3c - 80084f4: 2300 movs r3, #0 - 80084f6: 647b str r3, [r7, #68] @ 0x44 - 80084f8: 2300 movs r3, #0 - 80084fa: 63bb str r3, [r7, #56] @ 0x38 - uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; - 80084fc: 2300 movs r3, #0 - 80084fe: 637b str r3, [r7, #52] @ 0x34 - 8008500: 2300 movs r3, #0 - 8008502: 633b str r3, [r7, #48] @ 0x30 - 8008504: 2300 movs r3, #0 - 8008506: 62fb str r3, [r7, #44] @ 0x2c - const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; - const uint8_t aPredivFactorTable[2] = {1, 2}; - - uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - uint32_t temp_reg = 0U, frequency = 0U; - 8008508: 2300 movs r3, #0 - 800850a: 62bb str r3, [r7, #40] @ 0x28 - 800850c: 2300 movs r3, #0 - 800850e: 643b str r3, [r7, #64] @ 0x40 - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - switch (PeriphClk) - 8008510: 687b ldr r3, [r7, #4] - 8008512: 3b01 subs r3, #1 - 8008514: 2b0f cmp r3, #15 - 8008516: f200 8121 bhi.w 800875c - 800851a: a201 add r2, pc, #4 @ (adr r2, 8008520 ) - 800851c: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8008520: 080086dd .word 0x080086dd - 8008524: 08008741 .word 0x08008741 - 8008528: 0800875d .word 0x0800875d - 800852c: 0800863b .word 0x0800863b - 8008530: 0800875d .word 0x0800875d - 8008534: 0800875d .word 0x0800875d - 8008538: 0800875d .word 0x0800875d - 800853c: 0800868d .word 0x0800868d - 8008540: 0800875d .word 0x0800875d - 8008544: 0800875d .word 0x0800875d - 8008548: 0800875d .word 0x0800875d - 800854c: 0800875d .word 0x0800875d - 8008550: 0800875d .word 0x0800875d - 8008554: 0800875d .word 0x0800875d - 8008558: 0800875d .word 0x0800875d - 800855c: 08008561 .word 0x08008561 - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - case RCC_PERIPHCLK_USB: - { - /* Get RCC configuration ------------------------------------------------------*/ - temp_reg = RCC->CFGR; - 8008560: 4b87 ldr r3, [pc, #540] @ (8008780 ) - 8008562: 685b ldr r3, [r3, #4] - 8008564: 62bb str r3, [r7, #40] @ 0x28 - - /* Check if PLL is enabled */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) - 8008566: 4b86 ldr r3, [pc, #536] @ (8008780 ) - 8008568: 681b ldr r3, [r3, #0] - 800856a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 - 800856e: 2b00 cmp r3, #0 - 8008570: f000 80f6 beq.w 8008760 - { - pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; - 8008574: 6abb ldr r3, [r7, #40] @ 0x28 - 8008576: 0c9b lsrs r3, r3, #18 - 8008578: f003 030f and.w r3, r3, #15 - 800857c: 3348 adds r3, #72 @ 0x48 - 800857e: 443b add r3, r7 - 8008580: f813 3c30 ldrb.w r3, [r3, #-48] - 8008584: 63bb str r3, [r7, #56] @ 0x38 - if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) - 8008586: 6abb ldr r3, [r7, #40] @ 0x28 - 8008588: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 800858c: 2b00 cmp r3, #0 - 800858e: d03d beq.n 800860c - { -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; - 8008590: 4b7b ldr r3, [pc, #492] @ (8008780 ) - 8008592: 6adb ldr r3, [r3, #44] @ 0x2c - 8008594: f003 030f and.w r3, r3, #15 - 8008598: 3348 adds r3, #72 @ 0x48 - 800859a: 443b add r3, r7 - 800859c: f813 3c40 ldrb.w r3, [r3, #-64] - 80085a0: 63fb str r3, [r7, #60] @ 0x3c -#else - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) - 80085a2: 4b77 ldr r3, [pc, #476] @ (8008780 ) - 80085a4: 6adb ldr r3, [r3, #44] @ 0x2c - 80085a6: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 80085aa: 2b00 cmp r3, #0 - 80085ac: d01c beq.n 80085e8 - { - /* PLL2 selected as Prediv1 source */ - /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - 80085ae: 4b74 ldr r3, [pc, #464] @ (8008780 ) - 80085b0: 6adb ldr r3, [r3, #44] @ 0x2c - 80085b2: 091b lsrs r3, r3, #4 - 80085b4: f003 030f and.w r3, r3, #15 - 80085b8: 3301 adds r3, #1 - 80085ba: 62fb str r3, [r7, #44] @ 0x2c - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; - 80085bc: 4b70 ldr r3, [pc, #448] @ (8008780 ) - 80085be: 6adb ldr r3, [r3, #44] @ 0x2c - 80085c0: 0a1b lsrs r3, r3, #8 - 80085c2: f003 030f and.w r3, r3, #15 - 80085c6: 3302 adds r3, #2 - 80085c8: 637b str r3, [r7, #52] @ 0x34 - pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); - 80085ca: 4a6e ldr r2, [pc, #440] @ (8008784 ) - 80085cc: 6afb ldr r3, [r7, #44] @ 0x2c - 80085ce: fbb2 f3f3 udiv r3, r2, r3 - 80085d2: 6b7a ldr r2, [r7, #52] @ 0x34 - 80085d4: fb03 f202 mul.w r2, r3, r2 - 80085d8: 6bfb ldr r3, [r7, #60] @ 0x3c - 80085da: fbb2 f2f3 udiv r2, r2, r3 - 80085de: 6bbb ldr r3, [r7, #56] @ 0x38 - 80085e0: fb02 f303 mul.w r3, r2, r3 - 80085e4: 647b str r3, [r7, #68] @ 0x44 - 80085e6: e007 b.n 80085f8 - } - else - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); - 80085e8: 4a66 ldr r2, [pc, #408] @ (8008784 ) - 80085ea: 6bfb ldr r3, [r7, #60] @ 0x3c - 80085ec: fbb2 f2f3 udiv r2, r2, r3 - 80085f0: 6bbb ldr r3, [r7, #56] @ 0x38 - 80085f2: fb02 f303 mul.w r3, r2, r3 - 80085f6: 647b str r3, [r7, #68] @ 0x44 - } - - /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ - /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) - 80085f8: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 - 80085fc: 461a mov r2, r3 - 80085fe: 6bbb ldr r3, [r7, #56] @ 0x38 - 8008600: 4293 cmp r3, r2 - 8008602: d108 bne.n 8008616 - { - pllclk = pllclk / 2; - 8008604: 6c7b ldr r3, [r7, #68] @ 0x44 - 8008606: 085b lsrs r3, r3, #1 - 8008608: 647b str r3, [r7, #68] @ 0x44 - 800860a: e004 b.n 8008616 -#endif /* STM32F105xC || STM32F107xC */ - } - else - { - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); - 800860c: 6bbb ldr r3, [r7, #56] @ 0x38 - 800860e: 4a5e ldr r2, [pc, #376] @ (8008788 ) - 8008610: fb02 f303 mul.w r3, r2, r3 - 8008614: 647b str r3, [r7, #68] @ 0x44 - } - - /* Calcul of the USB frequency*/ -#if defined(STM32F105xC) || defined(STM32F107xC) - /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ - if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) - 8008616: 4b5a ldr r3, [pc, #360] @ (8008780 ) - 8008618: 685b ldr r3, [r3, #4] - 800861a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 800861e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 8008622: d102 bne.n 800862a - { - /* Prescaler of 2 selected for USB */ - frequency = pllclk; - 8008624: 6c7b ldr r3, [r7, #68] @ 0x44 - 8008626: 643b str r3, [r7, #64] @ 0x40 - /* Prescaler of 1.5 selected for USB */ - frequency = (pllclk * 2) / 3; - } -#endif - } - break; - 8008628: e09a b.n 8008760 - frequency = (2 * pllclk) / 3; - 800862a: 6c7b ldr r3, [r7, #68] @ 0x44 - 800862c: 005b lsls r3, r3, #1 - 800862e: 4a57 ldr r2, [pc, #348] @ (800878c ) - 8008630: fba2 2303 umull r2, r3, r2, r3 - 8008634: 085b lsrs r3, r3, #1 - 8008636: 643b str r3, [r7, #64] @ 0x40 - break; - 8008638: e092 b.n 8008760 - { -#if defined(STM32F103xE) || defined(STM32F103xG) - /* SYSCLK used as source clock for I2S2 */ - frequency = HAL_RCC_GetSysClockFreq(); -#else - if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) - 800863a: 4b51 ldr r3, [pc, #324] @ (8008780 ) - 800863c: 6adb ldr r3, [r3, #44] @ 0x2c - 800863e: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8008642: 2b00 cmp r3, #0 - 8008644: d103 bne.n 800864e - { - /* SYSCLK used as source clock for I2S2 */ - frequency = HAL_RCC_GetSysClockFreq(); - 8008646: f7ff fce3 bl 8008010 - 800864a: 6438 str r0, [r7, #64] @ 0x40 - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - } - } -#endif /* STM32F103xE || STM32F103xG */ - break; - 800864c: e08a b.n 8008764 - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) - 800864e: 4b4c ldr r3, [pc, #304] @ (8008780 ) - 8008650: 681b ldr r3, [r3, #0] - 8008652: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8008656: 2b00 cmp r3, #0 - 8008658: f000 8084 beq.w 8008764 - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - 800865c: 4b48 ldr r3, [pc, #288] @ (8008780 ) - 800865e: 6adb ldr r3, [r3, #44] @ 0x2c - 8008660: 091b lsrs r3, r3, #4 - 8008662: f003 030f and.w r3, r3, #15 - 8008666: 3301 adds r3, #1 - 8008668: 62fb str r3, [r7, #44] @ 0x2c - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - 800866a: 4b45 ldr r3, [pc, #276] @ (8008780 ) - 800866c: 6adb ldr r3, [r3, #44] @ 0x2c - 800866e: 0b1b lsrs r3, r3, #12 - 8008670: f003 030f and.w r3, r3, #15 - 8008674: 3302 adds r3, #2 - 8008676: 633b str r3, [r7, #48] @ 0x30 - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - 8008678: 4a42 ldr r2, [pc, #264] @ (8008784 ) - 800867a: 6afb ldr r3, [r7, #44] @ 0x2c - 800867c: fbb2 f3f3 udiv r3, r2, r3 - 8008680: 6b3a ldr r2, [r7, #48] @ 0x30 - 8008682: fb02 f303 mul.w r3, r2, r3 - 8008686: 005b lsls r3, r3, #1 - 8008688: 643b str r3, [r7, #64] @ 0x40 - break; - 800868a: e06b b.n 8008764 - { -#if defined(STM32F103xE) || defined(STM32F103xG) - /* SYSCLK used as source clock for I2S3 */ - frequency = HAL_RCC_GetSysClockFreq(); -#else - if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) - 800868c: 4b3c ldr r3, [pc, #240] @ (8008780 ) - 800868e: 6adb ldr r3, [r3, #44] @ 0x2c - 8008690: f403 2380 and.w r3, r3, #262144 @ 0x40000 - 8008694: 2b00 cmp r3, #0 - 8008696: d103 bne.n 80086a0 - { - /* SYSCLK used as source clock for I2S3 */ - frequency = HAL_RCC_GetSysClockFreq(); - 8008698: f7ff fcba bl 8008010 - 800869c: 6438 str r0, [r7, #64] @ 0x40 - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - } - } -#endif /* STM32F103xE || STM32F103xG */ - break; - 800869e: e063 b.n 8008768 - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) - 80086a0: 4b37 ldr r3, [pc, #220] @ (8008780 ) - 80086a2: 681b ldr r3, [r3, #0] - 80086a4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80086a8: 2b00 cmp r3, #0 - 80086aa: d05d beq.n 8008768 - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - 80086ac: 4b34 ldr r3, [pc, #208] @ (8008780 ) - 80086ae: 6adb ldr r3, [r3, #44] @ 0x2c - 80086b0: 091b lsrs r3, r3, #4 - 80086b2: f003 030f and.w r3, r3, #15 - 80086b6: 3301 adds r3, #1 - 80086b8: 62fb str r3, [r7, #44] @ 0x2c - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - 80086ba: 4b31 ldr r3, [pc, #196] @ (8008780 ) - 80086bc: 6adb ldr r3, [r3, #44] @ 0x2c - 80086be: 0b1b lsrs r3, r3, #12 - 80086c0: f003 030f and.w r3, r3, #15 - 80086c4: 3302 adds r3, #2 - 80086c6: 633b str r3, [r7, #48] @ 0x30 - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - 80086c8: 4a2e ldr r2, [pc, #184] @ (8008784 ) - 80086ca: 6afb ldr r3, [r7, #44] @ 0x2c - 80086cc: fbb2 f3f3 udiv r3, r2, r3 - 80086d0: 6b3a ldr r2, [r7, #48] @ 0x30 - 80086d2: fb02 f303 mul.w r3, r2, r3 - 80086d6: 005b lsls r3, r3, #1 - 80086d8: 643b str r3, [r7, #64] @ 0x40 - break; - 80086da: e045 b.n 8008768 - } -#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - case RCC_PERIPHCLK_RTC: - { - /* Get RCC BDCR configuration ------------------------------------------------------*/ - temp_reg = RCC->BDCR; - 80086dc: 4b28 ldr r3, [pc, #160] @ (8008780 ) - 80086de: 6a1b ldr r3, [r3, #32] - 80086e0: 62bb str r3, [r7, #40] @ 0x28 - - /* Check if LSE is ready if RTC clock selection is LSE */ - if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) - 80086e2: 6abb ldr r3, [r7, #40] @ 0x28 - 80086e4: f403 7340 and.w r3, r3, #768 @ 0x300 - 80086e8: f5b3 7f80 cmp.w r3, #256 @ 0x100 - 80086ec: d108 bne.n 8008700 - 80086ee: 6abb ldr r3, [r7, #40] @ 0x28 - 80086f0: f003 0302 and.w r3, r3, #2 - 80086f4: 2b00 cmp r3, #0 - 80086f6: d003 beq.n 8008700 - { - frequency = LSE_VALUE; - 80086f8: f44f 4300 mov.w r3, #32768 @ 0x8000 - 80086fc: 643b str r3, [r7, #64] @ 0x40 - 80086fe: e01e b.n 800873e - } - /* Check if LSI is ready if RTC clock selection is LSI */ - else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - 8008700: 6abb ldr r3, [r7, #40] @ 0x28 - 8008702: f403 7340 and.w r3, r3, #768 @ 0x300 - 8008706: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 800870a: d109 bne.n 8008720 - 800870c: 4b1c ldr r3, [pc, #112] @ (8008780 ) - 800870e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8008710: f003 0302 and.w r3, r3, #2 - 8008714: 2b00 cmp r3, #0 - 8008716: d003 beq.n 8008720 - { - frequency = LSI_VALUE; - 8008718: f649 4340 movw r3, #40000 @ 0x9c40 - 800871c: 643b str r3, [r7, #64] @ 0x40 - 800871e: e00e b.n 800873e - } - else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - 8008720: 6abb ldr r3, [r7, #40] @ 0x28 - 8008722: f403 7340 and.w r3, r3, #768 @ 0x300 - 8008726: f5b3 7f40 cmp.w r3, #768 @ 0x300 - 800872a: d11f bne.n 800876c - 800872c: 4b14 ldr r3, [pc, #80] @ (8008780 ) - 800872e: 681b ldr r3, [r3, #0] - 8008730: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8008734: 2b00 cmp r3, #0 - 8008736: d019 beq.n 800876c - { - frequency = HSE_VALUE / 128U; - 8008738: 4b15 ldr r3, [pc, #84] @ (8008790 ) - 800873a: 643b str r3, [r7, #64] @ 0x40 - /* Clock not enabled for RTC*/ - else - { - /* nothing to do: frequency already initialized to 0U */ - } - break; - 800873c: e016 b.n 800876c - 800873e: e015 b.n 800876c - } - case RCC_PERIPHCLK_ADC: - { - frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); - 8008740: f7ff fd62 bl 8008208 - 8008744: 4602 mov r2, r0 - 8008746: 4b0e ldr r3, [pc, #56] @ (8008780 ) - 8008748: 685b ldr r3, [r3, #4] - 800874a: 0b9b lsrs r3, r3, #14 - 800874c: f003 0303 and.w r3, r3, #3 - 8008750: 3301 adds r3, #1 - 8008752: 005b lsls r3, r3, #1 - 8008754: fbb2 f3f3 udiv r3, r2, r3 - 8008758: 643b str r3, [r7, #64] @ 0x40 - break; - 800875a: e008 b.n 800876e - } - default: - { - break; - 800875c: bf00 nop - 800875e: e006 b.n 800876e - break; - 8008760: bf00 nop - 8008762: e004 b.n 800876e - break; - 8008764: bf00 nop - 8008766: e002 b.n 800876e - break; - 8008768: bf00 nop - 800876a: e000 b.n 800876e - break; - 800876c: bf00 nop - } - } - return (frequency); - 800876e: 6c3b ldr r3, [r7, #64] @ 0x40 -} - 8008770: 4618 mov r0, r3 - 8008772: 374c adds r7, #76 @ 0x4c - 8008774: 46bd mov sp, r7 - 8008776: bd90 pop {r4, r7, pc} - 8008778: 0800dfc0 .word 0x0800dfc0 - 800877c: 0800dfd0 .word 0x0800dfd0 - 8008780: 40021000 .word 0x40021000 - 8008784: 017d7840 .word 0x017d7840 - 8008788: 003d0900 .word 0x003d0900 - 800878c: aaaaaaab .word 0xaaaaaaab - 8008790: 0002faf0 .word 0x0002faf0 - -08008794 : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - 8008794: b580 push {r7, lr} - 8008796: b084 sub sp, #16 - 8008798: af00 add r7, sp, #0 - 800879a: 6078 str r0, [r7, #4] - uint32_t prescaler = 0U; - 800879c: 2300 movs r3, #0 - 800879e: 60fb str r3, [r7, #12] - /* Check input parameters */ - if (hrtc == NULL) - 80087a0: 687b ldr r3, [r7, #4] - 80087a2: 2b00 cmp r3, #0 - 80087a4: d101 bne.n 80087aa - { - return HAL_ERROR; - 80087a6: 2301 movs r3, #1 - 80087a8: e084 b.n 80088b4 - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - } -#else - if (hrtc->State == HAL_RTC_STATE_RESET) - 80087aa: 687b ldr r3, [r7, #4] - 80087ac: 7c5b ldrb r3, [r3, #17] - 80087ae: b2db uxtb r3, r3 - 80087b0: 2b00 cmp r3, #0 - 80087b2: d105 bne.n 80087c0 - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - 80087b4: 687b ldr r3, [r7, #4] - 80087b6: 2200 movs r2, #0 - 80087b8: 741a strb r2, [r3, #16] - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - 80087ba: 6878 ldr r0, [r7, #4] - 80087bc: f7fc fc32 bl 8005024 - } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - 80087c0: 687b ldr r3, [r7, #4] - 80087c2: 2202 movs r2, #2 - 80087c4: 745a strb r2, [r3, #17] - - /* Waiting for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - 80087c6: 6878 ldr r0, [r7, #4] - 80087c8: f000 f87a bl 80088c0 - 80087cc: 4603 mov r3, r0 - 80087ce: 2b00 cmp r3, #0 - 80087d0: d004 beq.n 80087dc - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - 80087d2: 687b ldr r3, [r7, #4] - 80087d4: 2204 movs r2, #4 - 80087d6: 745a strb r2, [r3, #17] - - return HAL_ERROR; - 80087d8: 2301 movs r3, #1 - 80087da: e06b b.n 80088b4 - } - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - 80087dc: 6878 ldr r0, [r7, #4] - 80087de: f000 f89c bl 800891a - 80087e2: 4603 mov r3, r0 - 80087e4: 2b00 cmp r3, #0 - 80087e6: d004 beq.n 80087f2 - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - 80087e8: 687b ldr r3, [r7, #4] - 80087ea: 2204 movs r2, #4 - 80087ec: 745a strb r2, [r3, #17] - - return HAL_ERROR; - 80087ee: 2301 movs r3, #1 - 80087f0: e060 b.n 80088b4 - } - else - { - /* Clear Flags Bits */ - CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); - 80087f2: 687b ldr r3, [r7, #4] - 80087f4: 681b ldr r3, [r3, #0] - 80087f6: 685a ldr r2, [r3, #4] - 80087f8: 687b ldr r3, [r7, #4] - 80087fa: 681b ldr r3, [r3, #0] - 80087fc: f022 0207 bic.w r2, r2, #7 - 8008800: 605a str r2, [r3, #4] - - if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) - 8008802: 687b ldr r3, [r7, #4] - 8008804: 689b ldr r3, [r3, #8] - 8008806: 2b00 cmp r3, #0 - 8008808: d005 beq.n 8008816 - { - /* Disable the selected Tamper pin */ - CLEAR_BIT(BKP->CR, BKP_CR_TPE); - 800880a: 4b2c ldr r3, [pc, #176] @ (80088bc ) - 800880c: 6b1b ldr r3, [r3, #48] @ 0x30 - 800880e: 4a2b ldr r2, [pc, #172] @ (80088bc ) - 8008810: f023 0301 bic.w r3, r3, #1 - 8008814: 6313 str r3, [r2, #48] @ 0x30 - } - - /* Set the signal which will be routed to RTC Tamper pin*/ - MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); - 8008816: 4b29 ldr r3, [pc, #164] @ (80088bc ) - 8008818: 6adb ldr r3, [r3, #44] @ 0x2c - 800881a: f423 7260 bic.w r2, r3, #896 @ 0x380 - 800881e: 687b ldr r3, [r7, #4] - 8008820: 689b ldr r3, [r3, #8] - 8008822: 4926 ldr r1, [pc, #152] @ (80088bc ) - 8008824: 4313 orrs r3, r2 - 8008826: 62cb str r3, [r1, #44] @ 0x2c - - if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) - 8008828: 687b ldr r3, [r7, #4] - 800882a: 685b ldr r3, [r3, #4] - 800882c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8008830: d003 beq.n 800883a - { - /* RTC Prescaler provided directly by end-user*/ - prescaler = hrtc->Init.AsynchPrediv; - 8008832: 687b ldr r3, [r7, #4] - 8008834: 685b ldr r3, [r3, #4] - 8008836: 60fb str r3, [r7, #12] - 8008838: e00e b.n 8008858 - } - else - { - /* RTC Prescaler will be automatically calculated to get 1 second timebase */ - /* Get the RTCCLK frequency */ - prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); - 800883a: 2001 movs r0, #1 - 800883c: f7ff fe48 bl 80084d0 - 8008840: 60f8 str r0, [r7, #12] - - /* Check that RTC clock is enabled*/ - if (prescaler == 0U) - 8008842: 68fb ldr r3, [r7, #12] - 8008844: 2b00 cmp r3, #0 - 8008846: d104 bne.n 8008852 - { - /* Should not happen. Frequency is not available*/ - hrtc->State = HAL_RTC_STATE_ERROR; - 8008848: 687b ldr r3, [r7, #4] - 800884a: 2204 movs r2, #4 - 800884c: 745a strb r2, [r3, #17] - return HAL_ERROR; - 800884e: 2301 movs r3, #1 - 8008850: e030 b.n 80088b4 - } - else - { - /* RTC period = RTCCLK/(RTC_PR + 1) */ - prescaler = prescaler - 1U; - 8008852: 68fb ldr r3, [r7, #12] - 8008854: 3b01 subs r3, #1 - 8008856: 60fb str r3, [r7, #12] - } - } - - /* Configure the RTC_PRLH / RTC_PRLL */ - MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); - 8008858: 687b ldr r3, [r7, #4] - 800885a: 681b ldr r3, [r3, #0] - 800885c: 689b ldr r3, [r3, #8] - 800885e: f023 010f bic.w r1, r3, #15 - 8008862: 68fb ldr r3, [r7, #12] - 8008864: 0c1a lsrs r2, r3, #16 - 8008866: 687b ldr r3, [r7, #4] - 8008868: 681b ldr r3, [r3, #0] - 800886a: 430a orrs r2, r1 - 800886c: 609a str r2, [r3, #8] - MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); - 800886e: 687b ldr r3, [r7, #4] - 8008870: 681b ldr r3, [r3, #0] - 8008872: 68db ldr r3, [r3, #12] - 8008874: 0c1b lsrs r3, r3, #16 - 8008876: 041b lsls r3, r3, #16 - 8008878: 68fa ldr r2, [r7, #12] - 800887a: b291 uxth r1, r2 - 800887c: 687a ldr r2, [r7, #4] - 800887e: 6812 ldr r2, [r2, #0] - 8008880: 430b orrs r3, r1 - 8008882: 60d3 str r3, [r2, #12] - - /* Wait for synchro */ - if (RTC_ExitInitMode(hrtc) != HAL_OK) - 8008884: 6878 ldr r0, [r7, #4] - 8008886: f000 f870 bl 800896a - 800888a: 4603 mov r3, r0 - 800888c: 2b00 cmp r3, #0 - 800888e: d004 beq.n 800889a - { - hrtc->State = HAL_RTC_STATE_ERROR; - 8008890: 687b ldr r3, [r7, #4] - 8008892: 2204 movs r2, #4 - 8008894: 745a strb r2, [r3, #17] - - return HAL_ERROR; - 8008896: 2301 movs r3, #1 - 8008898: e00c b.n 80088b4 - } - - /* Initialize date to 1st of January 2000 */ - hrtc->DateToUpdate.Year = 0x00U; - 800889a: 687b ldr r3, [r7, #4] - 800889c: 2200 movs r2, #0 - 800889e: 73da strb r2, [r3, #15] - hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; - 80088a0: 687b ldr r3, [r7, #4] - 80088a2: 2201 movs r2, #1 - 80088a4: 735a strb r2, [r3, #13] - hrtc->DateToUpdate.Date = 0x01U; - 80088a6: 687b ldr r3, [r7, #4] - 80088a8: 2201 movs r2, #1 - 80088aa: 739a strb r2, [r3, #14] - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - 80088ac: 687b ldr r3, [r7, #4] - 80088ae: 2201 movs r2, #1 - 80088b0: 745a strb r2, [r3, #17] - - return HAL_OK; - 80088b2: 2300 movs r3, #0 - } -} - 80088b4: 4618 mov r0, r3 - 80088b6: 3710 adds r7, #16 - 80088b8: 46bd mov sp, r7 - 80088ba: bd80 pop {r7, pc} - 80088bc: 40006c00 .word 0x40006c00 - -080088c0 : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) -{ - 80088c0: b580 push {r7, lr} - 80088c2: b084 sub sp, #16 - 80088c4: af00 add r7, sp, #0 - 80088c6: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 80088c8: 2300 movs r3, #0 - 80088ca: 60fb str r3, [r7, #12] - - /* Check input parameters */ - if (hrtc == NULL) - 80088cc: 687b ldr r3, [r7, #4] - 80088ce: 2b00 cmp r3, #0 - 80088d0: d101 bne.n 80088d6 - { - return HAL_ERROR; - 80088d2: 2301 movs r3, #1 - 80088d4: e01d b.n 8008912 - } - - /* Clear RSF flag */ - CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); - 80088d6: 687b ldr r3, [r7, #4] - 80088d8: 681b ldr r3, [r3, #0] - 80088da: 685a ldr r2, [r3, #4] - 80088dc: 687b ldr r3, [r7, #4] - 80088de: 681b ldr r3, [r3, #0] - 80088e0: f022 0208 bic.w r2, r2, #8 - 80088e4: 605a str r2, [r3, #4] - - tickstart = HAL_GetTick(); - 80088e6: f7fc ffa5 bl 8005834 - 80088ea: 60f8 str r0, [r7, #12] - - /* Wait the registers to be synchronised */ - while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) - 80088ec: e009 b.n 8008902 - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 80088ee: f7fc ffa1 bl 8005834 - 80088f2: 4602 mov r2, r0 - 80088f4: 68fb ldr r3, [r7, #12] - 80088f6: 1ad3 subs r3, r2, r3 - 80088f8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 80088fc: d901 bls.n 8008902 - { - return HAL_TIMEOUT; - 80088fe: 2303 movs r3, #3 - 8008900: e007 b.n 8008912 - while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) - 8008902: 687b ldr r3, [r7, #4] - 8008904: 681b ldr r3, [r3, #0] - 8008906: 685b ldr r3, [r3, #4] - 8008908: f003 0308 and.w r3, r3, #8 - 800890c: 2b00 cmp r3, #0 - 800890e: d0ee beq.n 80088ee - } - } - - return HAL_OK; - 8008910: 2300 movs r3, #0 -} - 8008912: 4618 mov r0, r3 - 8008914: 3710 adds r7, #16 - 8008916: 46bd mov sp, r7 - 8008918: bd80 pop {r7, pc} - -0800891a : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) -{ - 800891a: b580 push {r7, lr} - 800891c: b084 sub sp, #16 - 800891e: af00 add r7, sp, #0 - 8008920: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 8008922: 2300 movs r3, #0 - 8008924: 60fb str r3, [r7, #12] - - tickstart = HAL_GetTick(); - 8008926: f7fc ff85 bl 8005834 - 800892a: 60f8 str r0, [r7, #12] - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 800892c: e009 b.n 8008942 - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 800892e: f7fc ff81 bl 8005834 - 8008932: 4602 mov r2, r0 - 8008934: 68fb ldr r3, [r7, #12] - 8008936: 1ad3 subs r3, r2, r3 - 8008938: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 800893c: d901 bls.n 8008942 - { - return HAL_TIMEOUT; - 800893e: 2303 movs r3, #3 - 8008940: e00f b.n 8008962 - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 8008942: 687b ldr r3, [r7, #4] - 8008944: 681b ldr r3, [r3, #0] - 8008946: 685b ldr r3, [r3, #4] - 8008948: f003 0320 and.w r3, r3, #32 - 800894c: 2b00 cmp r3, #0 - 800894e: d0ee beq.n 800892e - } - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - 8008950: 687b ldr r3, [r7, #4] - 8008952: 681b ldr r3, [r3, #0] - 8008954: 685a ldr r2, [r3, #4] - 8008956: 687b ldr r3, [r7, #4] - 8008958: 681b ldr r3, [r3, #0] - 800895a: f042 0210 orr.w r2, r2, #16 - 800895e: 605a str r2, [r3, #4] - - - return HAL_OK; - 8008960: 2300 movs r3, #0 -} - 8008962: 4618 mov r0, r3 - 8008964: 3710 adds r7, #16 - 8008966: 46bd mov sp, r7 - 8008968: bd80 pop {r7, pc} - -0800896a : - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) -{ - 800896a: b580 push {r7, lr} - 800896c: b084 sub sp, #16 - 800896e: af00 add r7, sp, #0 - 8008970: 6078 str r0, [r7, #4] - uint32_t tickstart = 0U; - 8008972: 2300 movs r3, #0 - 8008974: 60fb str r3, [r7, #12] - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8008976: 687b ldr r3, [r7, #4] - 8008978: 681b ldr r3, [r3, #0] - 800897a: 685a ldr r2, [r3, #4] - 800897c: 687b ldr r3, [r7, #4] - 800897e: 681b ldr r3, [r3, #0] - 8008980: f022 0210 bic.w r2, r2, #16 - 8008984: 605a str r2, [r3, #4] - - tickstart = HAL_GetTick(); - 8008986: f7fc ff55 bl 8005834 - 800898a: 60f8 str r0, [r7, #12] - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 800898c: e009 b.n 80089a2 - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 800898e: f7fc ff51 bl 8005834 - 8008992: 4602 mov r2, r0 - 8008994: 68fb ldr r3, [r7, #12] - 8008996: 1ad3 subs r3, r2, r3 - 8008998: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 - 800899c: d901 bls.n 80089a2 - { - return HAL_TIMEOUT; - 800899e: 2303 movs r3, #3 - 80089a0: e007 b.n 80089b2 - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - 80089a2: 687b ldr r3, [r7, #4] - 80089a4: 681b ldr r3, [r3, #0] - 80089a6: 685b ldr r3, [r3, #4] - 80089a8: f003 0320 and.w r3, r3, #32 - 80089ac: 2b00 cmp r3, #0 - 80089ae: d0ee beq.n 800898e - } - } - - return HAL_OK; - 80089b0: 2300 movs r3, #0 -} - 80089b2: 4618 mov r0, r3 - 80089b4: 3710 adds r7, #16 - 80089b6: 46bd mov sp, r7 - 80089b8: bd80 pop {r7, pc} - -080089ba : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - 80089ba: b580 push {r7, lr} - 80089bc: b082 sub sp, #8 - 80089be: af00 add r7, sp, #0 - 80089c0: 6078 str r0, [r7, #4] - /* Check the UART handle allocation */ - if (huart == NULL) - 80089c2: 687b ldr r3, [r7, #4] - 80089c4: 2b00 cmp r3, #0 - 80089c6: d101 bne.n 80089cc - { - return HAL_ERROR; - 80089c8: 2301 movs r3, #1 - 80089ca: e03f b.n 8008a4c - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); -#if defined(USART_CR1_OVER8) - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#endif /* USART_CR1_OVER8 */ - - if (huart->gState == HAL_UART_STATE_RESET) - 80089cc: 687b ldr r3, [r7, #4] - 80089ce: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 80089d2: b2db uxtb r3, r3 - 80089d4: 2b00 cmp r3, #0 - 80089d6: d106 bne.n 80089e6 - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - 80089d8: 687b ldr r3, [r7, #4] - 80089da: 2200 movs r2, #0 - 80089dc: f883 203c strb.w r2, [r3, #60] @ 0x3c - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - 80089e0: 6878 ldr r0, [r7, #4] - 80089e2: f7fc fe47 bl 8005674 -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - 80089e6: 687b ldr r3, [r7, #4] - 80089e8: 2224 movs r2, #36 @ 0x24 - 80089ea: f883 203d strb.w r2, [r3, #61] @ 0x3d - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - 80089ee: 687b ldr r3, [r7, #4] - 80089f0: 681b ldr r3, [r3, #0] - 80089f2: 68da ldr r2, [r3, #12] - 80089f4: 687b ldr r3, [r7, #4] - 80089f6: 681b ldr r3, [r3, #0] - 80089f8: f422 5200 bic.w r2, r2, #8192 @ 0x2000 - 80089fc: 60da str r2, [r3, #12] - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - 80089fe: 6878 ldr r0, [r7, #4] - 8008a00: f000 fca2 bl 8009348 - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8008a04: 687b ldr r3, [r7, #4] - 8008a06: 681b ldr r3, [r3, #0] - 8008a08: 691a ldr r2, [r3, #16] - 8008a0a: 687b ldr r3, [r7, #4] - 8008a0c: 681b ldr r3, [r3, #0] - 8008a0e: f422 4290 bic.w r2, r2, #18432 @ 0x4800 - 8008a12: 611a str r2, [r3, #16] - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8008a14: 687b ldr r3, [r7, #4] - 8008a16: 681b ldr r3, [r3, #0] - 8008a18: 695a ldr r2, [r3, #20] - 8008a1a: 687b ldr r3, [r7, #4] - 8008a1c: 681b ldr r3, [r3, #0] - 8008a1e: f022 022a bic.w r2, r2, #42 @ 0x2a - 8008a22: 615a str r2, [r3, #20] - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - 8008a24: 687b ldr r3, [r7, #4] - 8008a26: 681b ldr r3, [r3, #0] - 8008a28: 68da ldr r2, [r3, #12] - 8008a2a: 687b ldr r3, [r7, #4] - 8008a2c: 681b ldr r3, [r3, #0] - 8008a2e: f442 5200 orr.w r2, r2, #8192 @ 0x2000 - 8008a32: 60da str r2, [r3, #12] - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - 8008a34: 687b ldr r3, [r7, #4] - 8008a36: 2200 movs r2, #0 - 8008a38: 641a str r2, [r3, #64] @ 0x40 - huart->gState = HAL_UART_STATE_READY; - 8008a3a: 687b ldr r3, [r7, #4] - 8008a3c: 2220 movs r2, #32 - 8008a3e: f883 203d strb.w r2, [r3, #61] @ 0x3d - huart->RxState = HAL_UART_STATE_READY; - 8008a42: 687b ldr r3, [r7, #4] - 8008a44: 2220 movs r2, #32 - 8008a46: f883 203e strb.w r2, [r3, #62] @ 0x3e - - return HAL_OK; - 8008a4a: 2300 movs r3, #0 -} - 8008a4c: 4618 mov r0, r3 - 8008a4e: 3708 adds r7, #8 - 8008a50: 46bd mov sp, r7 - 8008a52: bd80 pop {r7, pc} - -08008a54 : - * @param Size Amount of data elements (u8 or u16) to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - 8008a54: b580 push {r7, lr} - 8008a56: b08a sub sp, #40 @ 0x28 - 8008a58: af02 add r7, sp, #8 - 8008a5a: 60f8 str r0, [r7, #12] - 8008a5c: 60b9 str r1, [r7, #8] - 8008a5e: 603b str r3, [r7, #0] - 8008a60: 4613 mov r3, r2 - 8008a62: 80fb strh r3, [r7, #6] - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint32_t tickstart = 0U; - 8008a64: 2300 movs r3, #0 - 8008a66: 617b str r3, [r7, #20] - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - 8008a68: 68fb ldr r3, [r7, #12] - 8008a6a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 8008a6e: b2db uxtb r3, r3 - 8008a70: 2b20 cmp r3, #32 - 8008a72: d17c bne.n 8008b6e - { - if ((pData == NULL) || (Size == 0U)) - 8008a74: 68bb ldr r3, [r7, #8] - 8008a76: 2b00 cmp r3, #0 - 8008a78: d002 beq.n 8008a80 - 8008a7a: 88fb ldrh r3, [r7, #6] - 8008a7c: 2b00 cmp r3, #0 - 8008a7e: d101 bne.n 8008a84 - { - return HAL_ERROR; - 8008a80: 2301 movs r3, #1 - 8008a82: e075 b.n 8008b70 - } - - /* Process Locked */ - __HAL_LOCK(huart); - 8008a84: 68fb ldr r3, [r7, #12] - 8008a86: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8008a8a: 2b01 cmp r3, #1 - 8008a8c: d101 bne.n 8008a92 - 8008a8e: 2302 movs r3, #2 - 8008a90: e06e b.n 8008b70 - 8008a92: 68fb ldr r3, [r7, #12] - 8008a94: 2201 movs r2, #1 - 8008a96: f883 203c strb.w r2, [r3, #60] @ 0x3c - - huart->ErrorCode = HAL_UART_ERROR_NONE; - 8008a9a: 68fb ldr r3, [r7, #12] - 8008a9c: 2200 movs r2, #0 - 8008a9e: 641a str r2, [r3, #64] @ 0x40 - huart->gState = HAL_UART_STATE_BUSY_TX; - 8008aa0: 68fb ldr r3, [r7, #12] - 8008aa2: 2221 movs r2, #33 @ 0x21 - 8008aa4: f883 203d strb.w r2, [r3, #61] @ 0x3d - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - 8008aa8: f7fc fec4 bl 8005834 - 8008aac: 6178 str r0, [r7, #20] - - huart->TxXferSize = Size; - 8008aae: 68fb ldr r3, [r7, #12] - 8008ab0: 88fa ldrh r2, [r7, #6] - 8008ab2: 849a strh r2, [r3, #36] @ 0x24 - huart->TxXferCount = Size; - 8008ab4: 68fb ldr r3, [r7, #12] - 8008ab6: 88fa ldrh r2, [r7, #6] - 8008ab8: 84da strh r2, [r3, #38] @ 0x26 - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 8008aba: 68fb ldr r3, [r7, #12] - 8008abc: 689b ldr r3, [r3, #8] - 8008abe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8008ac2: d108 bne.n 8008ad6 - 8008ac4: 68fb ldr r3, [r7, #12] - 8008ac6: 691b ldr r3, [r3, #16] - 8008ac8: 2b00 cmp r3, #0 - 8008aca: d104 bne.n 8008ad6 - { - pdata8bits = NULL; - 8008acc: 2300 movs r3, #0 - 8008ace: 61fb str r3, [r7, #28] - pdata16bits = (uint16_t *) pData; - 8008ad0: 68bb ldr r3, [r7, #8] - 8008ad2: 61bb str r3, [r7, #24] - 8008ad4: e003 b.n 8008ade - } - else - { - pdata8bits = pData; - 8008ad6: 68bb ldr r3, [r7, #8] - 8008ad8: 61fb str r3, [r7, #28] - pdata16bits = NULL; - 8008ada: 2300 movs r3, #0 - 8008adc: 61bb str r3, [r7, #24] - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - 8008ade: 68fb ldr r3, [r7, #12] - 8008ae0: 2200 movs r2, #0 - 8008ae2: f883 203c strb.w r2, [r3, #60] @ 0x3c - - while (huart->TxXferCount > 0U) - 8008ae6: e02a b.n 8008b3e - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - 8008ae8: 683b ldr r3, [r7, #0] - 8008aea: 9300 str r3, [sp, #0] - 8008aec: 697b ldr r3, [r7, #20] - 8008aee: 2200 movs r2, #0 - 8008af0: 2180 movs r1, #128 @ 0x80 - 8008af2: 68f8 ldr r0, [r7, #12] - 8008af4: f000 fa55 bl 8008fa2 - 8008af8: 4603 mov r3, r0 - 8008afa: 2b00 cmp r3, #0 - 8008afc: d001 beq.n 8008b02 - { - return HAL_TIMEOUT; - 8008afe: 2303 movs r3, #3 - 8008b00: e036 b.n 8008b70 - } - if (pdata8bits == NULL) - 8008b02: 69fb ldr r3, [r7, #28] - 8008b04: 2b00 cmp r3, #0 - 8008b06: d10b bne.n 8008b20 - { - huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); - 8008b08: 69bb ldr r3, [r7, #24] - 8008b0a: 881b ldrh r3, [r3, #0] - 8008b0c: 461a mov r2, r3 - 8008b0e: 68fb ldr r3, [r7, #12] - 8008b10: 681b ldr r3, [r3, #0] - 8008b12: f3c2 0208 ubfx r2, r2, #0, #9 - 8008b16: 605a str r2, [r3, #4] - pdata16bits++; - 8008b18: 69bb ldr r3, [r7, #24] - 8008b1a: 3302 adds r3, #2 - 8008b1c: 61bb str r3, [r7, #24] - 8008b1e: e007 b.n 8008b30 - } - else - { - huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); - 8008b20: 69fb ldr r3, [r7, #28] - 8008b22: 781a ldrb r2, [r3, #0] - 8008b24: 68fb ldr r3, [r7, #12] - 8008b26: 681b ldr r3, [r3, #0] - 8008b28: 605a str r2, [r3, #4] - pdata8bits++; - 8008b2a: 69fb ldr r3, [r7, #28] - 8008b2c: 3301 adds r3, #1 - 8008b2e: 61fb str r3, [r7, #28] - } - huart->TxXferCount--; - 8008b30: 68fb ldr r3, [r7, #12] - 8008b32: 8cdb ldrh r3, [r3, #38] @ 0x26 - 8008b34: b29b uxth r3, r3 - 8008b36: 3b01 subs r3, #1 - 8008b38: b29a uxth r2, r3 - 8008b3a: 68fb ldr r3, [r7, #12] - 8008b3c: 84da strh r2, [r3, #38] @ 0x26 - while (huart->TxXferCount > 0U) - 8008b3e: 68fb ldr r3, [r7, #12] - 8008b40: 8cdb ldrh r3, [r3, #38] @ 0x26 - 8008b42: b29b uxth r3, r3 - 8008b44: 2b00 cmp r3, #0 - 8008b46: d1cf bne.n 8008ae8 - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - 8008b48: 683b ldr r3, [r7, #0] - 8008b4a: 9300 str r3, [sp, #0] - 8008b4c: 697b ldr r3, [r7, #20] - 8008b4e: 2200 movs r2, #0 - 8008b50: 2140 movs r1, #64 @ 0x40 - 8008b52: 68f8 ldr r0, [r7, #12] - 8008b54: f000 fa25 bl 8008fa2 - 8008b58: 4603 mov r3, r0 - 8008b5a: 2b00 cmp r3, #0 - 8008b5c: d001 beq.n 8008b62 - { - return HAL_TIMEOUT; - 8008b5e: 2303 movs r3, #3 - 8008b60: e006 b.n 8008b70 - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - 8008b62: 68fb ldr r3, [r7, #12] - 8008b64: 2220 movs r2, #32 - 8008b66: f883 203d strb.w r2, [r3, #61] @ 0x3d - - return HAL_OK; - 8008b6a: 2300 movs r3, #0 - 8008b6c: e000 b.n 8008b70 - } - else - { - return HAL_BUSY; - 8008b6e: 2302 movs r3, #2 - } -} - 8008b70: 4618 mov r0, r3 - 8008b72: 3720 adds r7, #32 - 8008b74: 46bd mov sp, r7 - 8008b76: bd80 pop {r7, pc} - -08008b78 : - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - 8008b78: b580 push {r7, lr} - 8008b7a: b086 sub sp, #24 - 8008b7c: af00 add r7, sp, #0 - 8008b7e: 60f8 str r0, [r7, #12] - 8008b80: 60b9 str r1, [r7, #8] - 8008b82: 4613 mov r3, r2 - 8008b84: 80fb strh r3, [r7, #6] - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - 8008b86: 68fb ldr r3, [r7, #12] - 8008b88: f893 303e ldrb.w r3, [r3, #62] @ 0x3e - 8008b8c: b2db uxtb r3, r3 - 8008b8e: 2b20 cmp r3, #32 - 8008b90: d13c bne.n 8008c0c - { - if ((pData == NULL) || (Size == 0U)) - 8008b92: 68bb ldr r3, [r7, #8] - 8008b94: 2b00 cmp r3, #0 - 8008b96: d002 beq.n 8008b9e - 8008b98: 88fb ldrh r3, [r7, #6] - 8008b9a: 2b00 cmp r3, #0 - 8008b9c: d101 bne.n 8008ba2 - { - return HAL_ERROR; - 8008b9e: 2301 movs r3, #1 - 8008ba0: e035 b.n 8008c0e - } - - __HAL_LOCK(huart); - 8008ba2: 68fb ldr r3, [r7, #12] - 8008ba4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8008ba8: 2b01 cmp r3, #1 - 8008baa: d101 bne.n 8008bb0 - 8008bac: 2302 movs r3, #2 - 8008bae: e02e b.n 8008c0e - 8008bb0: 68fb ldr r3, [r7, #12] - 8008bb2: 2201 movs r2, #1 - 8008bb4: f883 203c strb.w r2, [r3, #60] @ 0x3c - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - 8008bb8: 68fb ldr r3, [r7, #12] - 8008bba: 2201 movs r2, #1 - 8008bbc: 631a str r2, [r3, #48] @ 0x30 - - status = UART_Start_Receive_IT(huart, pData, Size); - 8008bbe: 88fb ldrh r3, [r7, #6] - 8008bc0: 461a mov r2, r3 - 8008bc2: 68b9 ldr r1, [r7, #8] - 8008bc4: 68f8 ldr r0, [r7, #12] - 8008bc6: f000 fa36 bl 8009036 - 8008bca: 4603 mov r3, r0 - 8008bcc: 75fb strb r3, [r7, #23] - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - 8008bce: 7dfb ldrb r3, [r7, #23] - 8008bd0: 2b00 cmp r3, #0 - 8008bd2: d119 bne.n 8008c08 - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8008bd4: 68fb ldr r3, [r7, #12] - 8008bd6: 6b1b ldr r3, [r3, #48] @ 0x30 - 8008bd8: 2b01 cmp r3, #1 - 8008bda: d113 bne.n 8008c04 - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - 8008bdc: 2300 movs r3, #0 - 8008bde: 613b str r3, [r7, #16] - 8008be0: 68fb ldr r3, [r7, #12] - 8008be2: 681b ldr r3, [r3, #0] - 8008be4: 681b ldr r3, [r3, #0] - 8008be6: 613b str r3, [r7, #16] - 8008be8: 68fb ldr r3, [r7, #12] - 8008bea: 681b ldr r3, [r3, #0] - 8008bec: 685b ldr r3, [r3, #4] - 8008bee: 613b str r3, [r7, #16] - 8008bf0: 693b ldr r3, [r7, #16] - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8008bf2: 68fb ldr r3, [r7, #12] - 8008bf4: 681b ldr r3, [r3, #0] - 8008bf6: 68da ldr r2, [r3, #12] - 8008bf8: 68fb ldr r3, [r7, #12] - 8008bfa: 681b ldr r3, [r3, #0] - 8008bfc: f042 0210 orr.w r2, r2, #16 - 8008c00: 60da str r2, [r3, #12] - 8008c02: e001 b.n 8008c08 - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - 8008c04: 2301 movs r3, #1 - 8008c06: 75fb strb r3, [r7, #23] - } - } - - return status; - 8008c08: 7dfb ldrb r3, [r7, #23] - 8008c0a: e000 b.n 8008c0e - } - else - { - return HAL_BUSY; - 8008c0c: 2302 movs r3, #2 - } -} - 8008c0e: 4618 mov r0, r3 - 8008c10: 3718 adds r7, #24 - 8008c12: 46bd mov sp, r7 - 8008c14: bd80 pop {r7, pc} - ... - -08008c18 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - 8008c18: b580 push {r7, lr} - 8008c1a: b08a sub sp, #40 @ 0x28 - 8008c1c: af00 add r7, sp, #0 - 8008c1e: 6078 str r0, [r7, #4] - uint32_t isrflags = READ_REG(huart->Instance->SR); - 8008c20: 687b ldr r3, [r7, #4] - 8008c22: 681b ldr r3, [r3, #0] - 8008c24: 681b ldr r3, [r3, #0] - 8008c26: 627b str r3, [r7, #36] @ 0x24 - uint32_t cr1its = READ_REG(huart->Instance->CR1); - 8008c28: 687b ldr r3, [r7, #4] - 8008c2a: 681b ldr r3, [r3, #0] - 8008c2c: 68db ldr r3, [r3, #12] - 8008c2e: 623b str r3, [r7, #32] - uint32_t cr3its = READ_REG(huart->Instance->CR3); - 8008c30: 687b ldr r3, [r7, #4] - 8008c32: 681b ldr r3, [r3, #0] - 8008c34: 695b ldr r3, [r3, #20] - 8008c36: 61fb str r3, [r7, #28] - uint32_t errorflags = 0x00U; - 8008c38: 2300 movs r3, #0 - 8008c3a: 61bb str r3, [r7, #24] - uint32_t dmarequest = 0x00U; - 8008c3c: 2300 movs r3, #0 - 8008c3e: 617b str r3, [r7, #20] - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); - 8008c40: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008c42: f003 030f and.w r3, r3, #15 - 8008c46: 61bb str r3, [r7, #24] - if (errorflags == RESET) - 8008c48: 69bb ldr r3, [r7, #24] - 8008c4a: 2b00 cmp r3, #0 - 8008c4c: d10d bne.n 8008c6a - { - /* UART in mode Receiver -------------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - 8008c4e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008c50: f003 0320 and.w r3, r3, #32 - 8008c54: 2b00 cmp r3, #0 - 8008c56: d008 beq.n 8008c6a - 8008c58: 6a3b ldr r3, [r7, #32] - 8008c5a: f003 0320 and.w r3, r3, #32 - 8008c5e: 2b00 cmp r3, #0 - 8008c60: d003 beq.n 8008c6a - { - UART_Receive_IT(huart); - 8008c62: 6878 ldr r0, [r7, #4] - 8008c64: f000 fac7 bl 80091f6 - return; - 8008c68: e17b b.n 8008f62 - } - } - - /* If some errors occur */ - if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) - 8008c6a: 69bb ldr r3, [r7, #24] - 8008c6c: 2b00 cmp r3, #0 - 8008c6e: f000 80b1 beq.w 8008dd4 - 8008c72: 69fb ldr r3, [r7, #28] - 8008c74: f003 0301 and.w r3, r3, #1 - 8008c78: 2b00 cmp r3, #0 - 8008c7a: d105 bne.n 8008c88 - 8008c7c: 6a3b ldr r3, [r7, #32] - 8008c7e: f403 7390 and.w r3, r3, #288 @ 0x120 - 8008c82: 2b00 cmp r3, #0 - 8008c84: f000 80a6 beq.w 8008dd4 - { - /* UART parity error interrupt occurred ----------------------------------*/ - if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - 8008c88: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008c8a: f003 0301 and.w r3, r3, #1 - 8008c8e: 2b00 cmp r3, #0 - 8008c90: d00a beq.n 8008ca8 - 8008c92: 6a3b ldr r3, [r7, #32] - 8008c94: f403 7380 and.w r3, r3, #256 @ 0x100 - 8008c98: 2b00 cmp r3, #0 - 8008c9a: d005 beq.n 8008ca8 - { - huart->ErrorCode |= HAL_UART_ERROR_PE; - 8008c9c: 687b ldr r3, [r7, #4] - 8008c9e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008ca0: f043 0201 orr.w r2, r3, #1 - 8008ca4: 687b ldr r3, [r7, #4] - 8008ca6: 641a str r2, [r3, #64] @ 0x40 - } - - /* UART noise error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - 8008ca8: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008caa: f003 0304 and.w r3, r3, #4 - 8008cae: 2b00 cmp r3, #0 - 8008cb0: d00a beq.n 8008cc8 - 8008cb2: 69fb ldr r3, [r7, #28] - 8008cb4: f003 0301 and.w r3, r3, #1 - 8008cb8: 2b00 cmp r3, #0 - 8008cba: d005 beq.n 8008cc8 - { - huart->ErrorCode |= HAL_UART_ERROR_NE; - 8008cbc: 687b ldr r3, [r7, #4] - 8008cbe: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008cc0: f043 0202 orr.w r2, r3, #2 - 8008cc4: 687b ldr r3, [r7, #4] - 8008cc6: 641a str r2, [r3, #64] @ 0x40 - } - - /* UART frame error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - 8008cc8: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008cca: f003 0302 and.w r3, r3, #2 - 8008cce: 2b00 cmp r3, #0 - 8008cd0: d00a beq.n 8008ce8 - 8008cd2: 69fb ldr r3, [r7, #28] - 8008cd4: f003 0301 and.w r3, r3, #1 - 8008cd8: 2b00 cmp r3, #0 - 8008cda: d005 beq.n 8008ce8 - { - huart->ErrorCode |= HAL_UART_ERROR_FE; - 8008cdc: 687b ldr r3, [r7, #4] - 8008cde: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008ce0: f043 0204 orr.w r2, r3, #4 - 8008ce4: 687b ldr r3, [r7, #4] - 8008ce6: 641a str r2, [r3, #64] @ 0x40 - } - - /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) - 8008ce8: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008cea: f003 0308 and.w r3, r3, #8 - 8008cee: 2b00 cmp r3, #0 - 8008cf0: d00f beq.n 8008d12 - 8008cf2: 6a3b ldr r3, [r7, #32] - 8008cf4: f003 0320 and.w r3, r3, #32 - 8008cf8: 2b00 cmp r3, #0 - 8008cfa: d104 bne.n 8008d06 - 8008cfc: 69fb ldr r3, [r7, #28] - 8008cfe: f003 0301 and.w r3, r3, #1 - 8008d02: 2b00 cmp r3, #0 - 8008d04: d005 beq.n 8008d12 - { - huart->ErrorCode |= HAL_UART_ERROR_ORE; - 8008d06: 687b ldr r3, [r7, #4] - 8008d08: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008d0a: f043 0208 orr.w r2, r3, #8 - 8008d0e: 687b ldr r3, [r7, #4] - 8008d10: 641a str r2, [r3, #64] @ 0x40 - } - - /* Call UART Error Call back function if need be --------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - 8008d12: 687b ldr r3, [r7, #4] - 8008d14: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008d16: 2b00 cmp r3, #0 - 8008d18: f000 811e beq.w 8008f58 - { - /* UART in mode Receiver -----------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - 8008d1c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008d1e: f003 0320 and.w r3, r3, #32 - 8008d22: 2b00 cmp r3, #0 - 8008d24: d007 beq.n 8008d36 - 8008d26: 6a3b ldr r3, [r7, #32] - 8008d28: f003 0320 and.w r3, r3, #32 - 8008d2c: 2b00 cmp r3, #0 - 8008d2e: d002 beq.n 8008d36 - { - UART_Receive_IT(huart); - 8008d30: 6878 ldr r0, [r7, #4] - 8008d32: f000 fa60 bl 80091f6 - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - 8008d36: 687b ldr r3, [r7, #4] - 8008d38: 681b ldr r3, [r3, #0] - 8008d3a: 695b ldr r3, [r3, #20] - 8008d3c: f003 0340 and.w r3, r3, #64 @ 0x40 - 8008d40: 2b00 cmp r3, #0 - 8008d42: bf14 ite ne - 8008d44: 2301 movne r3, #1 - 8008d46: 2300 moveq r3, #0 - 8008d48: b2db uxtb r3, r3 - 8008d4a: 617b str r3, [r7, #20] - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) - 8008d4c: 687b ldr r3, [r7, #4] - 8008d4e: 6c1b ldr r3, [r3, #64] @ 0x40 - 8008d50: f003 0308 and.w r3, r3, #8 - 8008d54: 2b00 cmp r3, #0 - 8008d56: d102 bne.n 8008d5e - 8008d58: 697b ldr r3, [r7, #20] - 8008d5a: 2b00 cmp r3, #0 - 8008d5c: d031 beq.n 8008dc2 - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - 8008d5e: 6878 ldr r0, [r7, #4] - 8008d60: f000 f9a2 bl 80090a8 - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008d64: 687b ldr r3, [r7, #4] - 8008d66: 681b ldr r3, [r3, #0] - 8008d68: 695b ldr r3, [r3, #20] - 8008d6a: f003 0340 and.w r3, r3, #64 @ 0x40 - 8008d6e: 2b00 cmp r3, #0 - 8008d70: d023 beq.n 8008dba - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 8008d72: 687b ldr r3, [r7, #4] - 8008d74: 681b ldr r3, [r3, #0] - 8008d76: 695a ldr r2, [r3, #20] - 8008d78: 687b ldr r3, [r7, #4] - 8008d7a: 681b ldr r3, [r3, #0] - 8008d7c: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8008d80: 615a str r2, [r3, #20] - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - 8008d82: 687b ldr r3, [r7, #4] - 8008d84: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008d86: 2b00 cmp r3, #0 - 8008d88: d013 beq.n 8008db2 - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - 8008d8a: 687b ldr r3, [r7, #4] - 8008d8c: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008d8e: 4a76 ldr r2, [pc, #472] @ (8008f68 ) - 8008d90: 635a str r2, [r3, #52] @ 0x34 - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - 8008d92: 687b ldr r3, [r7, #4] - 8008d94: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008d96: 4618 mov r0, r3 - 8008d98: f7fe fa72 bl 8007280 - 8008d9c: 4603 mov r3, r0 - 8008d9e: 2b00 cmp r3, #0 - 8008da0: d016 beq.n 8008dd0 - { - /* Call Directly XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - 8008da2: 687b ldr r3, [r7, #4] - 8008da4: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008da6: 6b5b ldr r3, [r3, #52] @ 0x34 - 8008da8: 687a ldr r2, [r7, #4] - 8008daa: 6b92 ldr r2, [r2, #56] @ 0x38 - 8008dac: 4610 mov r0, r2 - 8008dae: 4798 blx r3 - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008db0: e00e b.n 8008dd0 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 8008db2: 6878 ldr r0, [r7, #4] - 8008db4: f000 f8ec bl 8008f90 - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008db8: e00a b.n 8008dd0 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 8008dba: 6878 ldr r0, [r7, #4] - 8008dbc: f000 f8e8 bl 8008f90 - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008dc0: e006 b.n 8008dd0 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 8008dc2: 6878 ldr r0, [r7, #4] - 8008dc4: f000 f8e4 bl 8008f90 -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - 8008dc8: 687b ldr r3, [r7, #4] - 8008dca: 2200 movs r2, #0 - 8008dcc: 641a str r2, [r3, #64] @ 0x40 - } - } - return; - 8008dce: e0c3 b.n 8008f58 - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008dd0: bf00 nop - return; - 8008dd2: e0c1 b.n 8008f58 - } /* End if some error occurs */ - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8008dd4: 687b ldr r3, [r7, #4] - 8008dd6: 6b1b ldr r3, [r3, #48] @ 0x30 - 8008dd8: 2b01 cmp r3, #1 - 8008dda: f040 80a1 bne.w 8008f20 - &&((isrflags & USART_SR_IDLE) != 0U) - 8008dde: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008de0: f003 0310 and.w r3, r3, #16 - 8008de4: 2b00 cmp r3, #0 - 8008de6: f000 809b beq.w 8008f20 - &&((cr1its & USART_SR_IDLE) != 0U)) - 8008dea: 6a3b ldr r3, [r7, #32] - 8008dec: f003 0310 and.w r3, r3, #16 - 8008df0: 2b00 cmp r3, #0 - 8008df2: f000 8095 beq.w 8008f20 - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - 8008df6: 2300 movs r3, #0 - 8008df8: 60fb str r3, [r7, #12] - 8008dfa: 687b ldr r3, [r7, #4] - 8008dfc: 681b ldr r3, [r3, #0] - 8008dfe: 681b ldr r3, [r3, #0] - 8008e00: 60fb str r3, [r7, #12] - 8008e02: 687b ldr r3, [r7, #4] - 8008e04: 681b ldr r3, [r3, #0] - 8008e06: 685b ldr r3, [r3, #4] - 8008e08: 60fb str r3, [r7, #12] - 8008e0a: 68fb ldr r3, [r7, #12] - - /* Check if DMA mode is enabled in UART */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8008e0c: 687b ldr r3, [r7, #4] - 8008e0e: 681b ldr r3, [r3, #0] - 8008e10: 695b ldr r3, [r3, #20] - 8008e12: f003 0340 and.w r3, r3, #64 @ 0x40 - 8008e16: 2b00 cmp r3, #0 - 8008e18: d04e beq.n 8008eb8 - { - /* DMA mode enabled */ - /* Check received length : If all expected data are received, do nothing, - (DMA cplt callback will be called). - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - 8008e1a: 687b ldr r3, [r7, #4] - 8008e1c: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008e1e: 681b ldr r3, [r3, #0] - 8008e20: 685b ldr r3, [r3, #4] - 8008e22: 823b strh r3, [r7, #16] - if ( (nb_remaining_rx_data > 0U) - 8008e24: 8a3b ldrh r3, [r7, #16] - 8008e26: 2b00 cmp r3, #0 - 8008e28: f000 8098 beq.w 8008f5c - &&(nb_remaining_rx_data < huart->RxXferSize)) - 8008e2c: 687b ldr r3, [r7, #4] - 8008e2e: 8d9b ldrh r3, [r3, #44] @ 0x2c - 8008e30: 8a3a ldrh r2, [r7, #16] - 8008e32: 429a cmp r2, r3 - 8008e34: f080 8092 bcs.w 8008f5c - { - /* Reception is not complete */ - huart->RxXferCount = nb_remaining_rx_data; - 8008e38: 687b ldr r3, [r7, #4] - 8008e3a: 8a3a ldrh r2, [r7, #16] - 8008e3c: 85da strh r2, [r3, #46] @ 0x2e - - /* In Normal mode, end DMA xfer and HAL UART Rx process*/ - if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) - 8008e3e: 687b ldr r3, [r7, #4] - 8008e40: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008e42: 699b ldr r3, [r3, #24] - 8008e44: 2b20 cmp r3, #32 - 8008e46: d02b beq.n 8008ea0 - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 8008e48: 687b ldr r3, [r7, #4] - 8008e4a: 681b ldr r3, [r3, #0] - 8008e4c: 68da ldr r2, [r3, #12] - 8008e4e: 687b ldr r3, [r7, #4] - 8008e50: 681b ldr r3, [r3, #0] - 8008e52: f422 7280 bic.w r2, r2, #256 @ 0x100 - 8008e56: 60da str r2, [r3, #12] - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8008e58: 687b ldr r3, [r7, #4] - 8008e5a: 681b ldr r3, [r3, #0] - 8008e5c: 695a ldr r2, [r3, #20] - 8008e5e: 687b ldr r3, [r7, #4] - 8008e60: 681b ldr r3, [r3, #0] - 8008e62: f022 0201 bic.w r2, r2, #1 - 8008e66: 615a str r2, [r3, #20] - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 8008e68: 687b ldr r3, [r7, #4] - 8008e6a: 681b ldr r3, [r3, #0] - 8008e6c: 695a ldr r2, [r3, #20] - 8008e6e: 687b ldr r3, [r7, #4] - 8008e70: 681b ldr r3, [r3, #0] - 8008e72: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8008e76: 615a str r2, [r3, #20] - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - 8008e78: 687b ldr r3, [r7, #4] - 8008e7a: 2220 movs r2, #32 - 8008e7c: f883 203e strb.w r2, [r3, #62] @ 0x3e - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8008e80: 687b ldr r3, [r7, #4] - 8008e82: 2200 movs r2, #0 - 8008e84: 631a str r2, [r3, #48] @ 0x30 - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8008e86: 687b ldr r3, [r7, #4] - 8008e88: 681b ldr r3, [r3, #0] - 8008e8a: 68da ldr r2, [r3, #12] - 8008e8c: 687b ldr r3, [r7, #4] - 8008e8e: 681b ldr r3, [r3, #0] - 8008e90: f022 0210 bic.w r2, r2, #16 - 8008e94: 60da str r2, [r3, #12] - - /* Last bytes received, so no need as the abort is immediate */ - (void)HAL_DMA_Abort(huart->hdmarx); - 8008e96: 687b ldr r3, [r7, #4] - 8008e98: 6b9b ldr r3, [r3, #56] @ 0x38 - 8008e9a: 4618 mov r0, r3 - 8008e9c: f7fe f9b5 bl 800720a -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); - 8008ea0: 687b ldr r3, [r7, #4] - 8008ea2: 8d9a ldrh r2, [r3, #44] @ 0x2c - 8008ea4: 687b ldr r3, [r7, #4] - 8008ea6: 8ddb ldrh r3, [r3, #46] @ 0x2e - 8008ea8: b29b uxth r3, r3 - 8008eaa: 1ad3 subs r3, r2, r3 - 8008eac: b29b uxth r3, r3 - 8008eae: 4619 mov r1, r3 - 8008eb0: 6878 ldr r0, [r7, #4] - 8008eb2: f7f9 ff13 bl 8002cdc -#endif - } - return; - 8008eb6: e051 b.n 8008f5c - else - { - /* DMA mode not enabled */ - /* Check received length : If all expected data are received, do nothing. - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - 8008eb8: 687b ldr r3, [r7, #4] - 8008eba: 8d9a ldrh r2, [r3, #44] @ 0x2c - 8008ebc: 687b ldr r3, [r7, #4] - 8008ebe: 8ddb ldrh r3, [r3, #46] @ 0x2e - 8008ec0: b29b uxth r3, r3 - 8008ec2: 1ad3 subs r3, r2, r3 - 8008ec4: 827b strh r3, [r7, #18] - if ( (huart->RxXferCount > 0U) - 8008ec6: 687b ldr r3, [r7, #4] - 8008ec8: 8ddb ldrh r3, [r3, #46] @ 0x2e - 8008eca: b29b uxth r3, r3 - 8008ecc: 2b00 cmp r3, #0 - 8008ece: d047 beq.n 8008f60 - &&(nb_rx_data > 0U) ) - 8008ed0: 8a7b ldrh r3, [r7, #18] - 8008ed2: 2b00 cmp r3, #0 - 8008ed4: d044 beq.n 8008f60 - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 8008ed6: 687b ldr r3, [r7, #4] - 8008ed8: 681b ldr r3, [r3, #0] - 8008eda: 68da ldr r2, [r3, #12] - 8008edc: 687b ldr r3, [r7, #4] - 8008ede: 681b ldr r3, [r3, #0] - 8008ee0: f422 7290 bic.w r2, r2, #288 @ 0x120 - 8008ee4: 60da str r2, [r3, #12] - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8008ee6: 687b ldr r3, [r7, #4] - 8008ee8: 681b ldr r3, [r3, #0] - 8008eea: 695a ldr r2, [r3, #20] - 8008eec: 687b ldr r3, [r7, #4] - 8008eee: 681b ldr r3, [r3, #0] - 8008ef0: f022 0201 bic.w r2, r2, #1 - 8008ef4: 615a str r2, [r3, #20] - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - 8008ef6: 687b ldr r3, [r7, #4] - 8008ef8: 2220 movs r2, #32 - 8008efa: f883 203e strb.w r2, [r3, #62] @ 0x3e - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8008efe: 687b ldr r3, [r7, #4] - 8008f00: 2200 movs r2, #0 - 8008f02: 631a str r2, [r3, #48] @ 0x30 - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8008f04: 687b ldr r3, [r7, #4] - 8008f06: 681b ldr r3, [r3, #0] - 8008f08: 68da ldr r2, [r3, #12] - 8008f0a: 687b ldr r3, [r7, #4] - 8008f0c: 681b ldr r3, [r3, #0] - 8008f0e: f022 0210 bic.w r2, r2, #16 - 8008f12: 60da str r2, [r3, #12] -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxEventCallback(huart, nb_rx_data); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, nb_rx_data); - 8008f14: 8a7b ldrh r3, [r7, #18] - 8008f16: 4619 mov r1, r3 - 8008f18: 6878 ldr r0, [r7, #4] - 8008f1a: f7f9 fedf bl 8002cdc -#endif - } - return; - 8008f1e: e01f b.n 8008f60 - } - } - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - 8008f20: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008f22: f003 0380 and.w r3, r3, #128 @ 0x80 - 8008f26: 2b00 cmp r3, #0 - 8008f28: d008 beq.n 8008f3c - 8008f2a: 6a3b ldr r3, [r7, #32] - 8008f2c: f003 0380 and.w r3, r3, #128 @ 0x80 - 8008f30: 2b00 cmp r3, #0 - 8008f32: d003 beq.n 8008f3c - { - UART_Transmit_IT(huart); - 8008f34: 6878 ldr r0, [r7, #4] - 8008f36: f000 f8f7 bl 8009128 - return; - 8008f3a: e012 b.n 8008f62 - } - - /* UART in mode Transmitter end --------------------------------------------*/ - if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - 8008f3c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8008f3e: f003 0340 and.w r3, r3, #64 @ 0x40 - 8008f42: 2b00 cmp r3, #0 - 8008f44: d00d beq.n 8008f62 - 8008f46: 6a3b ldr r3, [r7, #32] - 8008f48: f003 0340 and.w r3, r3, #64 @ 0x40 - 8008f4c: 2b00 cmp r3, #0 - 8008f4e: d008 beq.n 8008f62 - { - UART_EndTransmit_IT(huart); - 8008f50: 6878 ldr r0, [r7, #4] - 8008f52: f000 f938 bl 80091c6 - return; - 8008f56: e004 b.n 8008f62 - return; - 8008f58: bf00 nop - 8008f5a: e002 b.n 8008f62 - return; - 8008f5c: bf00 nop - 8008f5e: e000 b.n 8008f62 - return; - 8008f60: bf00 nop - } -} - 8008f62: 3728 adds r7, #40 @ 0x28 - 8008f64: 46bd mov sp, r7 - 8008f66: bd80 pop {r7, pc} - 8008f68: 08009101 .word 0x08009101 - -08008f6c : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - 8008f6c: b480 push {r7} - 8008f6e: b083 sub sp, #12 - 8008f70: af00 add r7, sp, #0 - 8008f72: 6078 str r0, [r7, #4] - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback could be implemented in the user file - */ -} - 8008f74: bf00 nop - 8008f76: 370c adds r7, #12 - 8008f78: 46bd mov sp, r7 - 8008f7a: bc80 pop {r7} - 8008f7c: 4770 bx lr - -08008f7e : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - 8008f7e: b480 push {r7} - 8008f80: b083 sub sp, #12 - 8008f82: af00 add r7, sp, #0 - 8008f84: 6078 str r0, [r7, #4] - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback could be implemented in the user file - */ -} - 8008f86: bf00 nop - 8008f88: 370c adds r7, #12 - 8008f8a: 46bd mov sp, r7 - 8008f8c: bc80 pop {r7} - 8008f8e: 4770 bx lr - -08008f90 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - 8008f90: b480 push {r7} - 8008f92: b083 sub sp, #12 - 8008f94: af00 add r7, sp, #0 - 8008f96: 6078 str r0, [r7, #4] - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file - */ -} - 8008f98: bf00 nop - 8008f9a: 370c adds r7, #12 - 8008f9c: 46bd mov sp, r7 - 8008f9e: bc80 pop {r7} - 8008fa0: 4770 bx lr - -08008fa2 : - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - 8008fa2: b580 push {r7, lr} - 8008fa4: b084 sub sp, #16 - 8008fa6: af00 add r7, sp, #0 - 8008fa8: 60f8 str r0, [r7, #12] - 8008faa: 60b9 str r1, [r7, #8] - 8008fac: 603b str r3, [r7, #0] - 8008fae: 4613 mov r3, r2 - 8008fb0: 71fb strb r3, [r7, #7] - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8008fb2: e02c b.n 800900e - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - 8008fb4: 69bb ldr r3, [r7, #24] - 8008fb6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8008fba: d028 beq.n 800900e - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - 8008fbc: 69bb ldr r3, [r7, #24] - 8008fbe: 2b00 cmp r3, #0 - 8008fc0: d007 beq.n 8008fd2 - 8008fc2: f7fc fc37 bl 8005834 - 8008fc6: 4602 mov r2, r0 - 8008fc8: 683b ldr r3, [r7, #0] - 8008fca: 1ad3 subs r3, r2, r3 - 8008fcc: 69ba ldr r2, [r7, #24] - 8008fce: 429a cmp r2, r3 - 8008fd0: d21d bcs.n 800900e - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 8008fd2: 68fb ldr r3, [r7, #12] - 8008fd4: 681b ldr r3, [r3, #0] - 8008fd6: 68da ldr r2, [r3, #12] - 8008fd8: 68fb ldr r3, [r7, #12] - 8008fda: 681b ldr r3, [r3, #0] - 8008fdc: f422 72d0 bic.w r2, r2, #416 @ 0x1a0 - 8008fe0: 60da str r2, [r3, #12] - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8008fe2: 68fb ldr r3, [r7, #12] - 8008fe4: 681b ldr r3, [r3, #0] - 8008fe6: 695a ldr r2, [r3, #20] - 8008fe8: 68fb ldr r3, [r7, #12] - 8008fea: 681b ldr r3, [r3, #0] - 8008fec: f022 0201 bic.w r2, r2, #1 - 8008ff0: 615a str r2, [r3, #20] - - huart->gState = HAL_UART_STATE_READY; - 8008ff2: 68fb ldr r3, [r7, #12] - 8008ff4: 2220 movs r2, #32 - 8008ff6: f883 203d strb.w r2, [r3, #61] @ 0x3d - huart->RxState = HAL_UART_STATE_READY; - 8008ffa: 68fb ldr r3, [r7, #12] - 8008ffc: 2220 movs r2, #32 - 8008ffe: f883 203e strb.w r2, [r3, #62] @ 0x3e - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - 8009002: 68fb ldr r3, [r7, #12] - 8009004: 2200 movs r2, #0 - 8009006: f883 203c strb.w r2, [r3, #60] @ 0x3c - - return HAL_TIMEOUT; - 800900a: 2303 movs r3, #3 - 800900c: e00f b.n 800902e - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800900e: 68fb ldr r3, [r7, #12] - 8009010: 681b ldr r3, [r3, #0] - 8009012: 681a ldr r2, [r3, #0] - 8009014: 68bb ldr r3, [r7, #8] - 8009016: 4013 ands r3, r2 - 8009018: 68ba ldr r2, [r7, #8] - 800901a: 429a cmp r2, r3 - 800901c: bf0c ite eq - 800901e: 2301 moveq r3, #1 - 8009020: 2300 movne r3, #0 - 8009022: b2db uxtb r3, r3 - 8009024: 461a mov r2, r3 - 8009026: 79fb ldrb r3, [r7, #7] - 8009028: 429a cmp r2, r3 - 800902a: d0c3 beq.n 8008fb4 - } - } - } - return HAL_OK; - 800902c: 2300 movs r3, #0 -} - 800902e: 4618 mov r0, r3 - 8009030: 3710 adds r7, #16 - 8009032: 46bd mov sp, r7 - 8009034: bd80 pop {r7, pc} - -08009036 : - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - 8009036: b480 push {r7} - 8009038: b085 sub sp, #20 - 800903a: af00 add r7, sp, #0 - 800903c: 60f8 str r0, [r7, #12] - 800903e: 60b9 str r1, [r7, #8] - 8009040: 4613 mov r3, r2 - 8009042: 80fb strh r3, [r7, #6] - huart->pRxBuffPtr = pData; - 8009044: 68fb ldr r3, [r7, #12] - 8009046: 68ba ldr r2, [r7, #8] - 8009048: 629a str r2, [r3, #40] @ 0x28 - huart->RxXferSize = Size; - 800904a: 68fb ldr r3, [r7, #12] - 800904c: 88fa ldrh r2, [r7, #6] - 800904e: 859a strh r2, [r3, #44] @ 0x2c - huart->RxXferCount = Size; - 8009050: 68fb ldr r3, [r7, #12] - 8009052: 88fa ldrh r2, [r7, #6] - 8009054: 85da strh r2, [r3, #46] @ 0x2e - - huart->ErrorCode = HAL_UART_ERROR_NONE; - 8009056: 68fb ldr r3, [r7, #12] - 8009058: 2200 movs r2, #0 - 800905a: 641a str r2, [r3, #64] @ 0x40 - huart->RxState = HAL_UART_STATE_BUSY_RX; - 800905c: 68fb ldr r3, [r7, #12] - 800905e: 2222 movs r2, #34 @ 0x22 - 8009060: f883 203e strb.w r2, [r3, #62] @ 0x3e - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - 8009064: 68fb ldr r3, [r7, #12] - 8009066: 2200 movs r2, #0 - 8009068: f883 203c strb.w r2, [r3, #60] @ 0x3c - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - 800906c: 68fb ldr r3, [r7, #12] - 800906e: 681b ldr r3, [r3, #0] - 8009070: 68da ldr r2, [r3, #12] - 8009072: 68fb ldr r3, [r7, #12] - 8009074: 681b ldr r3, [r3, #0] - 8009076: f442 7280 orr.w r2, r2, #256 @ 0x100 - 800907a: 60da str r2, [r3, #12] - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - 800907c: 68fb ldr r3, [r7, #12] - 800907e: 681b ldr r3, [r3, #0] - 8009080: 695a ldr r2, [r3, #20] - 8009082: 68fb ldr r3, [r7, #12] - 8009084: 681b ldr r3, [r3, #0] - 8009086: f042 0201 orr.w r2, r2, #1 - 800908a: 615a str r2, [r3, #20] - - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); - 800908c: 68fb ldr r3, [r7, #12] - 800908e: 681b ldr r3, [r3, #0] - 8009090: 68da ldr r2, [r3, #12] - 8009092: 68fb ldr r3, [r7, #12] - 8009094: 681b ldr r3, [r3, #0] - 8009096: f042 0220 orr.w r2, r2, #32 - 800909a: 60da str r2, [r3, #12] - - return HAL_OK; - 800909c: 2300 movs r3, #0 -} - 800909e: 4618 mov r0, r3 - 80090a0: 3714 adds r7, #20 - 80090a2: 46bd mov sp, r7 - 80090a4: bc80 pop {r7} - 80090a6: 4770 bx lr - -080090a8 : - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - 80090a8: b480 push {r7} - 80090aa: b083 sub sp, #12 - 80090ac: af00 add r7, sp, #0 - 80090ae: 6078 str r0, [r7, #4] - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 80090b0: 687b ldr r3, [r7, #4] - 80090b2: 681b ldr r3, [r3, #0] - 80090b4: 68da ldr r2, [r3, #12] - 80090b6: 687b ldr r3, [r7, #4] - 80090b8: 681b ldr r3, [r3, #0] - 80090ba: f422 7290 bic.w r2, r2, #288 @ 0x120 - 80090be: 60da str r2, [r3, #12] - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 80090c0: 687b ldr r3, [r7, #4] - 80090c2: 681b ldr r3, [r3, #0] - 80090c4: 695a ldr r2, [r3, #20] - 80090c6: 687b ldr r3, [r7, #4] - 80090c8: 681b ldr r3, [r3, #0] - 80090ca: f022 0201 bic.w r2, r2, #1 - 80090ce: 615a str r2, [r3, #20] - - /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80090d0: 687b ldr r3, [r7, #4] - 80090d2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80090d4: 2b01 cmp r3, #1 - 80090d6: d107 bne.n 80090e8 - { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 80090d8: 687b ldr r3, [r7, #4] - 80090da: 681b ldr r3, [r3, #0] - 80090dc: 68da ldr r2, [r3, #12] - 80090de: 687b ldr r3, [r7, #4] - 80090e0: 681b ldr r3, [r3, #0] - 80090e2: f022 0210 bic.w r2, r2, #16 - 80090e6: 60da str r2, [r3, #12] - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - 80090e8: 687b ldr r3, [r7, #4] - 80090ea: 2220 movs r2, #32 - 80090ec: f883 203e strb.w r2, [r3, #62] @ 0x3e - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80090f0: 687b ldr r3, [r7, #4] - 80090f2: 2200 movs r2, #0 - 80090f4: 631a str r2, [r3, #48] @ 0x30 -} - 80090f6: bf00 nop - 80090f8: 370c adds r7, #12 - 80090fa: 46bd mov sp, r7 - 80090fc: bc80 pop {r7} - 80090fe: 4770 bx lr - -08009100 : - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - 8009100: b580 push {r7, lr} - 8009102: b084 sub sp, #16 - 8009104: af00 add r7, sp, #0 - 8009106: 6078 str r0, [r7, #4] - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - 8009108: 687b ldr r3, [r7, #4] - 800910a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800910c: 60fb str r3, [r7, #12] - huart->RxXferCount = 0x00U; - 800910e: 68fb ldr r3, [r7, #12] - 8009110: 2200 movs r2, #0 - 8009112: 85da strh r2, [r3, #46] @ 0x2e - huart->TxXferCount = 0x00U; - 8009114: 68fb ldr r3, [r7, #12] - 8009116: 2200 movs r2, #0 - 8009118: 84da strh r2, [r3, #38] @ 0x26 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 800911a: 68f8 ldr r0, [r7, #12] - 800911c: f7ff ff38 bl 8008f90 -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - 8009120: bf00 nop - 8009122: 3710 adds r7, #16 - 8009124: 46bd mov sp, r7 - 8009126: bd80 pop {r7, pc} - -08009128 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) -{ - 8009128: b480 push {r7} - 800912a: b085 sub sp, #20 - 800912c: af00 add r7, sp, #0 - 800912e: 6078 str r0, [r7, #4] - uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - 8009130: 687b ldr r3, [r7, #4] - 8009132: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 8009136: b2db uxtb r3, r3 - 8009138: 2b21 cmp r3, #33 @ 0x21 - 800913a: d13e bne.n 80091ba - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 800913c: 687b ldr r3, [r7, #4] - 800913e: 689b ldr r3, [r3, #8] - 8009140: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8009144: d114 bne.n 8009170 - 8009146: 687b ldr r3, [r7, #4] - 8009148: 691b ldr r3, [r3, #16] - 800914a: 2b00 cmp r3, #0 - 800914c: d110 bne.n 8009170 - { - tmp = (uint16_t *) huart->pTxBuffPtr; - 800914e: 687b ldr r3, [r7, #4] - 8009150: 6a1b ldr r3, [r3, #32] - 8009152: 60fb str r3, [r7, #12] - huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - 8009154: 68fb ldr r3, [r7, #12] - 8009156: 881b ldrh r3, [r3, #0] - 8009158: 461a mov r2, r3 - 800915a: 687b ldr r3, [r7, #4] - 800915c: 681b ldr r3, [r3, #0] - 800915e: f3c2 0208 ubfx r2, r2, #0, #9 - 8009162: 605a str r2, [r3, #4] - huart->pTxBuffPtr += 2U; - 8009164: 687b ldr r3, [r7, #4] - 8009166: 6a1b ldr r3, [r3, #32] - 8009168: 1c9a adds r2, r3, #2 - 800916a: 687b ldr r3, [r7, #4] - 800916c: 621a str r2, [r3, #32] - 800916e: e008 b.n 8009182 - } - else - { - huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); - 8009170: 687b ldr r3, [r7, #4] - 8009172: 6a1b ldr r3, [r3, #32] - 8009174: 1c59 adds r1, r3, #1 - 8009176: 687a ldr r2, [r7, #4] - 8009178: 6211 str r1, [r2, #32] - 800917a: 781a ldrb r2, [r3, #0] - 800917c: 687b ldr r3, [r7, #4] - 800917e: 681b ldr r3, [r3, #0] - 8009180: 605a str r2, [r3, #4] - } - - if (--huart->TxXferCount == 0U) - 8009182: 687b ldr r3, [r7, #4] - 8009184: 8cdb ldrh r3, [r3, #38] @ 0x26 - 8009186: b29b uxth r3, r3 - 8009188: 3b01 subs r3, #1 - 800918a: b29b uxth r3, r3 - 800918c: 687a ldr r2, [r7, #4] - 800918e: 4619 mov r1, r3 - 8009190: 84d1 strh r1, [r2, #38] @ 0x26 - 8009192: 2b00 cmp r3, #0 - 8009194: d10f bne.n 80091b6 - { - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - 8009196: 687b ldr r3, [r7, #4] - 8009198: 681b ldr r3, [r3, #0] - 800919a: 68da ldr r2, [r3, #12] - 800919c: 687b ldr r3, [r7, #4] - 800919e: 681b ldr r3, [r3, #0] - 80091a0: f022 0280 bic.w r2, r2, #128 @ 0x80 - 80091a4: 60da str r2, [r3, #12] - - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - 80091a6: 687b ldr r3, [r7, #4] - 80091a8: 681b ldr r3, [r3, #0] - 80091aa: 68da ldr r2, [r3, #12] - 80091ac: 687b ldr r3, [r7, #4] - 80091ae: 681b ldr r3, [r3, #0] - 80091b0: f042 0240 orr.w r2, r2, #64 @ 0x40 - 80091b4: 60da str r2, [r3, #12] - } - return HAL_OK; - 80091b6: 2300 movs r3, #0 - 80091b8: e000 b.n 80091bc - } - else - { - return HAL_BUSY; - 80091ba: 2302 movs r3, #2 - } -} - 80091bc: 4618 mov r0, r3 - 80091be: 3714 adds r7, #20 - 80091c0: 46bd mov sp, r7 - 80091c2: bc80 pop {r7} - 80091c4: 4770 bx lr - -080091c6 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - 80091c6: b580 push {r7, lr} - 80091c8: b082 sub sp, #8 - 80091ca: af00 add r7, sp, #0 - 80091cc: 6078 str r0, [r7, #4] - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - 80091ce: 687b ldr r3, [r7, #4] - 80091d0: 681b ldr r3, [r3, #0] - 80091d2: 68da ldr r2, [r3, #12] - 80091d4: 687b ldr r3, [r7, #4] - 80091d6: 681b ldr r3, [r3, #0] - 80091d8: f022 0240 bic.w r2, r2, #64 @ 0x40 - 80091dc: 60da str r2, [r3, #12] - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - 80091de: 687b ldr r3, [r7, #4] - 80091e0: 2220 movs r2, #32 - 80091e2: f883 203d strb.w r2, [r3, #61] @ 0x3d -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); - 80091e6: 6878 ldr r0, [r7, #4] - 80091e8: f7ff fec0 bl 8008f6c -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - return HAL_OK; - 80091ec: 2300 movs r3, #0 -} - 80091ee: 4618 mov r0, r3 - 80091f0: 3708 adds r7, #8 - 80091f2: 46bd mov sp, r7 - 80091f4: bd80 pop {r7, pc} - -080091f6 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - 80091f6: b580 push {r7, lr} - 80091f8: b086 sub sp, #24 - 80091fa: af00 add r7, sp, #0 - 80091fc: 6078 str r0, [r7, #4] - uint8_t *pdata8bits; - uint16_t *pdata16bits; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - 80091fe: 687b ldr r3, [r7, #4] - 8009200: f893 303e ldrb.w r3, [r3, #62] @ 0x3e - 8009204: b2db uxtb r3, r3 - 8009206: 2b22 cmp r3, #34 @ 0x22 - 8009208: f040 8099 bne.w 800933e - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 800920c: 687b ldr r3, [r7, #4] - 800920e: 689b ldr r3, [r3, #8] - 8009210: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8009214: d117 bne.n 8009246 - 8009216: 687b ldr r3, [r7, #4] - 8009218: 691b ldr r3, [r3, #16] - 800921a: 2b00 cmp r3, #0 - 800921c: d113 bne.n 8009246 - { - pdata8bits = NULL; - 800921e: 2300 movs r3, #0 - 8009220: 617b str r3, [r7, #20] - pdata16bits = (uint16_t *) huart->pRxBuffPtr; - 8009222: 687b ldr r3, [r7, #4] - 8009224: 6a9b ldr r3, [r3, #40] @ 0x28 - 8009226: 613b str r3, [r7, #16] - *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - 8009228: 687b ldr r3, [r7, #4] - 800922a: 681b ldr r3, [r3, #0] - 800922c: 685b ldr r3, [r3, #4] - 800922e: b29b uxth r3, r3 - 8009230: f3c3 0308 ubfx r3, r3, #0, #9 - 8009234: b29a uxth r2, r3 - 8009236: 693b ldr r3, [r7, #16] - 8009238: 801a strh r2, [r3, #0] - huart->pRxBuffPtr += 2U; - 800923a: 687b ldr r3, [r7, #4] - 800923c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800923e: 1c9a adds r2, r3, #2 - 8009240: 687b ldr r3, [r7, #4] - 8009242: 629a str r2, [r3, #40] @ 0x28 - 8009244: e026 b.n 8009294 - } - else - { - pdata8bits = (uint8_t *) huart->pRxBuffPtr; - 8009246: 687b ldr r3, [r7, #4] - 8009248: 6a9b ldr r3, [r3, #40] @ 0x28 - 800924a: 617b str r3, [r7, #20] - pdata16bits = NULL; - 800924c: 2300 movs r3, #0 - 800924e: 613b str r3, [r7, #16] - - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - 8009250: 687b ldr r3, [r7, #4] - 8009252: 689b ldr r3, [r3, #8] - 8009254: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8009258: d007 beq.n 800926a - 800925a: 687b ldr r3, [r7, #4] - 800925c: 689b ldr r3, [r3, #8] - 800925e: 2b00 cmp r3, #0 - 8009260: d10a bne.n 8009278 - 8009262: 687b ldr r3, [r7, #4] - 8009264: 691b ldr r3, [r3, #16] - 8009266: 2b00 cmp r3, #0 - 8009268: d106 bne.n 8009278 - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - 800926a: 687b ldr r3, [r7, #4] - 800926c: 681b ldr r3, [r3, #0] - 800926e: 685b ldr r3, [r3, #4] - 8009270: b2da uxtb r2, r3 - 8009272: 697b ldr r3, [r7, #20] - 8009274: 701a strb r2, [r3, #0] - 8009276: e008 b.n 800928a - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - 8009278: 687b ldr r3, [r7, #4] - 800927a: 681b ldr r3, [r3, #0] - 800927c: 685b ldr r3, [r3, #4] - 800927e: b2db uxtb r3, r3 - 8009280: f003 037f and.w r3, r3, #127 @ 0x7f - 8009284: b2da uxtb r2, r3 - 8009286: 697b ldr r3, [r7, #20] - 8009288: 701a strb r2, [r3, #0] - } - huart->pRxBuffPtr += 1U; - 800928a: 687b ldr r3, [r7, #4] - 800928c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800928e: 1c5a adds r2, r3, #1 - 8009290: 687b ldr r3, [r7, #4] - 8009292: 629a str r2, [r3, #40] @ 0x28 - } - - if (--huart->RxXferCount == 0U) - 8009294: 687b ldr r3, [r7, #4] - 8009296: 8ddb ldrh r3, [r3, #46] @ 0x2e - 8009298: b29b uxth r3, r3 - 800929a: 3b01 subs r3, #1 - 800929c: b29b uxth r3, r3 - 800929e: 687a ldr r2, [r7, #4] - 80092a0: 4619 mov r1, r3 - 80092a2: 85d1 strh r1, [r2, #46] @ 0x2e - 80092a4: 2b00 cmp r3, #0 - 80092a6: d148 bne.n 800933a - { - /* Disable the UART Data Register not empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - 80092a8: 687b ldr r3, [r7, #4] - 80092aa: 681b ldr r3, [r3, #0] - 80092ac: 68da ldr r2, [r3, #12] - 80092ae: 687b ldr r3, [r7, #4] - 80092b0: 681b ldr r3, [r3, #0] - 80092b2: f022 0220 bic.w r2, r2, #32 - 80092b6: 60da str r2, [r3, #12] - - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - 80092b8: 687b ldr r3, [r7, #4] - 80092ba: 681b ldr r3, [r3, #0] - 80092bc: 68da ldr r2, [r3, #12] - 80092be: 687b ldr r3, [r7, #4] - 80092c0: 681b ldr r3, [r3, #0] - 80092c2: f422 7280 bic.w r2, r2, #256 @ 0x100 - 80092c6: 60da str r2, [r3, #12] - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - 80092c8: 687b ldr r3, [r7, #4] - 80092ca: 681b ldr r3, [r3, #0] - 80092cc: 695a ldr r2, [r3, #20] - 80092ce: 687b ldr r3, [r7, #4] - 80092d0: 681b ldr r3, [r3, #0] - 80092d2: f022 0201 bic.w r2, r2, #1 - 80092d6: 615a str r2, [r3, #20] - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - 80092d8: 687b ldr r3, [r7, #4] - 80092da: 2220 movs r2, #32 - 80092dc: f883 203e strb.w r2, [r3, #62] @ 0x3e - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80092e0: 687b ldr r3, [r7, #4] - 80092e2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80092e4: 2b01 cmp r3, #1 - 80092e6: d123 bne.n 8009330 - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80092e8: 687b ldr r3, [r7, #4] - 80092ea: 2200 movs r2, #0 - 80092ec: 631a str r2, [r3, #48] @ 0x30 - - /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 80092ee: 687b ldr r3, [r7, #4] - 80092f0: 681b ldr r3, [r3, #0] - 80092f2: 68da ldr r2, [r3, #12] - 80092f4: 687b ldr r3, [r7, #4] - 80092f6: 681b ldr r3, [r3, #0] - 80092f8: f022 0210 bic.w r2, r2, #16 - 80092fc: 60da str r2, [r3, #12] - - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - 80092fe: 687b ldr r3, [r7, #4] - 8009300: 681b ldr r3, [r3, #0] - 8009302: 681b ldr r3, [r3, #0] - 8009304: f003 0310 and.w r3, r3, #16 - 8009308: 2b10 cmp r3, #16 - 800930a: d10a bne.n 8009322 - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_IDLEFLAG(huart); - 800930c: 2300 movs r3, #0 - 800930e: 60fb str r3, [r7, #12] - 8009310: 687b ldr r3, [r7, #4] - 8009312: 681b ldr r3, [r3, #0] - 8009314: 681b ldr r3, [r3, #0] - 8009316: 60fb str r3, [r7, #12] - 8009318: 687b ldr r3, [r7, #4] - 800931a: 681b ldr r3, [r3, #0] - 800931c: 685b ldr r3, [r3, #4] - 800931e: 60fb str r3, [r7, #12] - 8009320: 68fb ldr r3, [r7, #12] -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8009322: 687b ldr r3, [r7, #4] - 8009324: 8d9b ldrh r3, [r3, #44] @ 0x2c - 8009326: 4619 mov r1, r3 - 8009328: 6878 ldr r0, [r7, #4] - 800932a: f7f9 fcd7 bl 8002cdc - 800932e: e002 b.n 8009336 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); - 8009330: 6878 ldr r0, [r7, #4] - 8009332: f7ff fe24 bl 8008f7e -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; - 8009336: 2300 movs r3, #0 - 8009338: e002 b.n 8009340 - } - return HAL_OK; - 800933a: 2300 movs r3, #0 - 800933c: e000 b.n 8009340 - } - else - { - return HAL_BUSY; - 800933e: 2302 movs r3, #2 - } -} - 8009340: 4618 mov r0, r3 - 8009342: 3718 adds r7, #24 - 8009344: 46bd mov sp, r7 - 8009346: bd80 pop {r7, pc} - -08009348 : - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_SetConfig(UART_HandleTypeDef *huart) -{ - 8009348: b580 push {r7, lr} - 800934a: b084 sub sp, #16 - 800934c: af00 add r7, sp, #0 - 800934e: 6078 str r0, [r7, #4] - assert_param(IS_UART_MODE(huart->Init.Mode)); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits - according to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8009350: 687b ldr r3, [r7, #4] - 8009352: 681b ldr r3, [r3, #0] - 8009354: 691b ldr r3, [r3, #16] - 8009356: f423 5140 bic.w r1, r3, #12288 @ 0x3000 - 800935a: 687b ldr r3, [r7, #4] - 800935c: 68da ldr r2, [r3, #12] - 800935e: 687b ldr r3, [r7, #4] - 8009360: 681b ldr r3, [r3, #0] - 8009362: 430a orrs r2, r1 - 8009364: 611a str r2, [r3, #16] - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - MODIFY_REG(huart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - tmpreg); -#else - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; - 8009366: 687b ldr r3, [r7, #4] - 8009368: 689a ldr r2, [r3, #8] - 800936a: 687b ldr r3, [r7, #4] - 800936c: 691b ldr r3, [r3, #16] - 800936e: 431a orrs r2, r3 - 8009370: 687b ldr r3, [r7, #4] - 8009372: 695b ldr r3, [r3, #20] - 8009374: 4313 orrs r3, r2 - 8009376: 60bb str r3, [r7, #8] - MODIFY_REG(huart->Instance->CR1, - 8009378: 687b ldr r3, [r7, #4] - 800937a: 681b ldr r3, [r3, #0] - 800937c: 68db ldr r3, [r3, #12] - 800937e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 - 8009382: f023 030c bic.w r3, r3, #12 - 8009386: 687a ldr r2, [r7, #4] - 8009388: 6812 ldr r2, [r2, #0] - 800938a: 68b9 ldr r1, [r7, #8] - 800938c: 430b orrs r3, r1 - 800938e: 60d3 str r3, [r2, #12] - tmpreg); -#endif /* USART_CR1_OVER8 */ - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - 8009390: 687b ldr r3, [r7, #4] - 8009392: 681b ldr r3, [r3, #0] - 8009394: 695b ldr r3, [r3, #20] - 8009396: f423 7140 bic.w r1, r3, #768 @ 0x300 - 800939a: 687b ldr r3, [r7, #4] - 800939c: 699a ldr r2, [r3, #24] - 800939e: 687b ldr r3, [r7, #4] - 80093a0: 681b ldr r3, [r3, #0] - 80093a2: 430a orrs r2, r1 - 80093a4: 615a str r2, [r3, #20] - - - if(huart->Instance == USART1) - 80093a6: 687b ldr r3, [r7, #4] - 80093a8: 681b ldr r3, [r3, #0] - 80093aa: 4a2c ldr r2, [pc, #176] @ (800945c ) - 80093ac: 4293 cmp r3, r2 - 80093ae: d103 bne.n 80093b8 - { - pclk = HAL_RCC_GetPCLK2Freq(); - 80093b0: f7fe ff2a bl 8008208 - 80093b4: 60f8 str r0, [r7, #12] - 80093b6: e002 b.n 80093be - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - 80093b8: f7fe ff12 bl 80081e0 - 80093bc: 60f8 str r0, [r7, #12] - else - { - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - } -#else - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - 80093be: 68fa ldr r2, [r7, #12] - 80093c0: 4613 mov r3, r2 - 80093c2: 009b lsls r3, r3, #2 - 80093c4: 4413 add r3, r2 - 80093c6: 009a lsls r2, r3, #2 - 80093c8: 441a add r2, r3 - 80093ca: 687b ldr r3, [r7, #4] - 80093cc: 685b ldr r3, [r3, #4] - 80093ce: 009b lsls r3, r3, #2 - 80093d0: fbb2 f3f3 udiv r3, r2, r3 - 80093d4: 4a22 ldr r2, [pc, #136] @ (8009460 ) - 80093d6: fba2 2303 umull r2, r3, r2, r3 - 80093da: 095b lsrs r3, r3, #5 - 80093dc: 0119 lsls r1, r3, #4 - 80093de: 68fa ldr r2, [r7, #12] - 80093e0: 4613 mov r3, r2 - 80093e2: 009b lsls r3, r3, #2 - 80093e4: 4413 add r3, r2 - 80093e6: 009a lsls r2, r3, #2 - 80093e8: 441a add r2, r3 - 80093ea: 687b ldr r3, [r7, #4] - 80093ec: 685b ldr r3, [r3, #4] - 80093ee: 009b lsls r3, r3, #2 - 80093f0: fbb2 f2f3 udiv r2, r2, r3 - 80093f4: 4b1a ldr r3, [pc, #104] @ (8009460 ) - 80093f6: fba3 0302 umull r0, r3, r3, r2 - 80093fa: 095b lsrs r3, r3, #5 - 80093fc: 2064 movs r0, #100 @ 0x64 - 80093fe: fb00 f303 mul.w r3, r0, r3 - 8009402: 1ad3 subs r3, r2, r3 - 8009404: 011b lsls r3, r3, #4 - 8009406: 3332 adds r3, #50 @ 0x32 - 8009408: 4a15 ldr r2, [pc, #84] @ (8009460 ) - 800940a: fba2 2303 umull r2, r3, r2, r3 - 800940e: 095b lsrs r3, r3, #5 - 8009410: f003 03f0 and.w r3, r3, #240 @ 0xf0 - 8009414: 4419 add r1, r3 - 8009416: 68fa ldr r2, [r7, #12] - 8009418: 4613 mov r3, r2 - 800941a: 009b lsls r3, r3, #2 - 800941c: 4413 add r3, r2 - 800941e: 009a lsls r2, r3, #2 - 8009420: 441a add r2, r3 - 8009422: 687b ldr r3, [r7, #4] - 8009424: 685b ldr r3, [r3, #4] - 8009426: 009b lsls r3, r3, #2 - 8009428: fbb2 f2f3 udiv r2, r2, r3 - 800942c: 4b0c ldr r3, [pc, #48] @ (8009460 ) - 800942e: fba3 0302 umull r0, r3, r3, r2 - 8009432: 095b lsrs r3, r3, #5 - 8009434: 2064 movs r0, #100 @ 0x64 - 8009436: fb00 f303 mul.w r3, r0, r3 - 800943a: 1ad3 subs r3, r2, r3 - 800943c: 011b lsls r3, r3, #4 - 800943e: 3332 adds r3, #50 @ 0x32 - 8009440: 4a07 ldr r2, [pc, #28] @ (8009460 ) - 8009442: fba2 2303 umull r2, r3, r2, r3 - 8009446: 095b lsrs r3, r3, #5 - 8009448: f003 020f and.w r2, r3, #15 - 800944c: 687b ldr r3, [r7, #4] - 800944e: 681b ldr r3, [r3, #0] - 8009450: 440a add r2, r1 - 8009452: 609a str r2, [r3, #8] -#endif /* USART_CR1_OVER8 */ -} - 8009454: bf00 nop - 8009456: 3710 adds r7, #16 - 8009458: 46bd mov sp, r7 - 800945a: bd80 pop {r7, pc} - 800945c: 40013800 .word 0x40013800 - 8009460: 51eb851f .word 0x51eb851f - -08009464 <__cvt>: - 8009464: 2b00 cmp r3, #0 - 8009466: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800946a: 461d mov r5, r3 - 800946c: bfbb ittet lt - 800946e: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 - 8009472: 461d movlt r5, r3 - 8009474: 2300 movge r3, #0 - 8009476: 232d movlt r3, #45 @ 0x2d - 8009478: b088 sub sp, #32 - 800947a: 4614 mov r4, r2 - 800947c: bfb8 it lt - 800947e: 4614 movlt r4, r2 - 8009480: 9a12 ldr r2, [sp, #72] @ 0x48 - 8009482: 9e10 ldr r6, [sp, #64] @ 0x40 - 8009484: 7013 strb r3, [r2, #0] - 8009486: 9b14 ldr r3, [sp, #80] @ 0x50 - 8009488: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c - 800948c: f023 0820 bic.w r8, r3, #32 - 8009490: f1b8 0f46 cmp.w r8, #70 @ 0x46 - 8009494: d005 beq.n 80094a2 <__cvt+0x3e> - 8009496: f1b8 0f45 cmp.w r8, #69 @ 0x45 - 800949a: d100 bne.n 800949e <__cvt+0x3a> - 800949c: 3601 adds r6, #1 - 800949e: 2302 movs r3, #2 - 80094a0: e000 b.n 80094a4 <__cvt+0x40> - 80094a2: 2303 movs r3, #3 - 80094a4: aa07 add r2, sp, #28 - 80094a6: 9204 str r2, [sp, #16] - 80094a8: aa06 add r2, sp, #24 - 80094aa: e9cd a202 strd sl, r2, [sp, #8] - 80094ae: e9cd 3600 strd r3, r6, [sp] - 80094b2: 4622 mov r2, r4 - 80094b4: 462b mov r3, r5 - 80094b6: f001 fb9b bl 800abf0 <_dtoa_r> - 80094ba: f1b8 0f47 cmp.w r8, #71 @ 0x47 - 80094be: 4607 mov r7, r0 - 80094c0: d119 bne.n 80094f6 <__cvt+0x92> - 80094c2: 9b11 ldr r3, [sp, #68] @ 0x44 - 80094c4: 07db lsls r3, r3, #31 - 80094c6: d50e bpl.n 80094e6 <__cvt+0x82> - 80094c8: eb00 0906 add.w r9, r0, r6 - 80094cc: 2200 movs r2, #0 - 80094ce: 2300 movs r3, #0 - 80094d0: 4620 mov r0, r4 - 80094d2: 4629 mov r1, r5 - 80094d4: f7f7 fade bl 8000a94 <__aeabi_dcmpeq> - 80094d8: b108 cbz r0, 80094de <__cvt+0x7a> - 80094da: f8cd 901c str.w r9, [sp, #28] - 80094de: 2230 movs r2, #48 @ 0x30 - 80094e0: 9b07 ldr r3, [sp, #28] - 80094e2: 454b cmp r3, r9 - 80094e4: d31e bcc.n 8009524 <__cvt+0xc0> - 80094e6: 4638 mov r0, r7 - 80094e8: 9b07 ldr r3, [sp, #28] - 80094ea: 9a15 ldr r2, [sp, #84] @ 0x54 - 80094ec: 1bdb subs r3, r3, r7 - 80094ee: 6013 str r3, [r2, #0] - 80094f0: b008 add sp, #32 - 80094f2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80094f6: f1b8 0f46 cmp.w r8, #70 @ 0x46 - 80094fa: eb00 0906 add.w r9, r0, r6 - 80094fe: d1e5 bne.n 80094cc <__cvt+0x68> - 8009500: 7803 ldrb r3, [r0, #0] - 8009502: 2b30 cmp r3, #48 @ 0x30 - 8009504: d10a bne.n 800951c <__cvt+0xb8> - 8009506: 2200 movs r2, #0 - 8009508: 2300 movs r3, #0 - 800950a: 4620 mov r0, r4 - 800950c: 4629 mov r1, r5 - 800950e: f7f7 fac1 bl 8000a94 <__aeabi_dcmpeq> - 8009512: b918 cbnz r0, 800951c <__cvt+0xb8> - 8009514: f1c6 0601 rsb r6, r6, #1 - 8009518: f8ca 6000 str.w r6, [sl] - 800951c: f8da 3000 ldr.w r3, [sl] - 8009520: 4499 add r9, r3 - 8009522: e7d3 b.n 80094cc <__cvt+0x68> - 8009524: 1c59 adds r1, r3, #1 - 8009526: 9107 str r1, [sp, #28] - 8009528: 701a strb r2, [r3, #0] - 800952a: e7d9 b.n 80094e0 <__cvt+0x7c> - -0800952c <__exponent>: - 800952c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} - 800952e: 2900 cmp r1, #0 - 8009530: bfb6 itet lt - 8009532: 232d movlt r3, #45 @ 0x2d - 8009534: 232b movge r3, #43 @ 0x2b - 8009536: 4249 neglt r1, r1 - 8009538: 2909 cmp r1, #9 - 800953a: 7002 strb r2, [r0, #0] - 800953c: 7043 strb r3, [r0, #1] - 800953e: dd29 ble.n 8009594 <__exponent+0x68> - 8009540: f10d 0307 add.w r3, sp, #7 - 8009544: 461d mov r5, r3 - 8009546: 270a movs r7, #10 - 8009548: fbb1 f6f7 udiv r6, r1, r7 - 800954c: 461a mov r2, r3 - 800954e: fb07 1416 mls r4, r7, r6, r1 - 8009552: 3430 adds r4, #48 @ 0x30 - 8009554: f802 4c01 strb.w r4, [r2, #-1] - 8009558: 460c mov r4, r1 - 800955a: 2c63 cmp r4, #99 @ 0x63 - 800955c: 4631 mov r1, r6 - 800955e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff - 8009562: dcf1 bgt.n 8009548 <__exponent+0x1c> - 8009564: 3130 adds r1, #48 @ 0x30 - 8009566: 1e94 subs r4, r2, #2 - 8009568: f803 1c01 strb.w r1, [r3, #-1] - 800956c: 4623 mov r3, r4 - 800956e: 1c41 adds r1, r0, #1 - 8009570: 42ab cmp r3, r5 - 8009572: d30a bcc.n 800958a <__exponent+0x5e> - 8009574: f10d 0309 add.w r3, sp, #9 - 8009578: 1a9b subs r3, r3, r2 - 800957a: 42ac cmp r4, r5 - 800957c: bf88 it hi - 800957e: 2300 movhi r3, #0 - 8009580: 3302 adds r3, #2 - 8009582: 4403 add r3, r0 - 8009584: 1a18 subs r0, r3, r0 - 8009586: b003 add sp, #12 - 8009588: bdf0 pop {r4, r5, r6, r7, pc} - 800958a: f813 6b01 ldrb.w r6, [r3], #1 - 800958e: f801 6f01 strb.w r6, [r1, #1]! - 8009592: e7ed b.n 8009570 <__exponent+0x44> - 8009594: 2330 movs r3, #48 @ 0x30 - 8009596: 3130 adds r1, #48 @ 0x30 - 8009598: 7083 strb r3, [r0, #2] - 800959a: 70c1 strb r1, [r0, #3] - 800959c: 1d03 adds r3, r0, #4 - 800959e: e7f1 b.n 8009584 <__exponent+0x58> - -080095a0 <_printf_float>: - 80095a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 80095a4: b091 sub sp, #68 @ 0x44 - 80095a6: 460c mov r4, r1 - 80095a8: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 - 80095ac: 4616 mov r6, r2 - 80095ae: 461f mov r7, r3 - 80095b0: 4605 mov r5, r0 - 80095b2: f001 fa1b bl 800a9ec <_localeconv_r> - 80095b6: 6803 ldr r3, [r0, #0] - 80095b8: 4618 mov r0, r3 - 80095ba: 9308 str r3, [sp, #32] - 80095bc: f7f6 fe34 bl 8000228 - 80095c0: 2300 movs r3, #0 - 80095c2: 930e str r3, [sp, #56] @ 0x38 - 80095c4: f8d8 3000 ldr.w r3, [r8] - 80095c8: 9009 str r0, [sp, #36] @ 0x24 - 80095ca: 3307 adds r3, #7 - 80095cc: f023 0307 bic.w r3, r3, #7 - 80095d0: f103 0208 add.w r2, r3, #8 - 80095d4: f894 a018 ldrb.w sl, [r4, #24] - 80095d8: f8d4 b000 ldr.w fp, [r4] - 80095dc: f8c8 2000 str.w r2, [r8] - 80095e0: e9d3 8900 ldrd r8, r9, [r3] - 80095e4: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 - 80095e8: 930b str r3, [sp, #44] @ 0x2c - 80095ea: f8cd 8028 str.w r8, [sp, #40] @ 0x28 - 80095ee: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 80095f2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 - 80095f6: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 - 80095fa: 4b9c ldr r3, [pc, #624] @ (800986c <_printf_float+0x2cc>) - 80095fc: f7f7 fa7c bl 8000af8 <__aeabi_dcmpun> - 8009600: bb70 cbnz r0, 8009660 <_printf_float+0xc0> - 8009602: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 - 8009606: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800960a: 4b98 ldr r3, [pc, #608] @ (800986c <_printf_float+0x2cc>) - 800960c: f7f7 fa56 bl 8000abc <__aeabi_dcmple> - 8009610: bb30 cbnz r0, 8009660 <_printf_float+0xc0> - 8009612: 2200 movs r2, #0 - 8009614: 2300 movs r3, #0 - 8009616: 4640 mov r0, r8 - 8009618: 4649 mov r1, r9 - 800961a: f7f7 fa45 bl 8000aa8 <__aeabi_dcmplt> - 800961e: b110 cbz r0, 8009626 <_printf_float+0x86> - 8009620: 232d movs r3, #45 @ 0x2d - 8009622: f884 3043 strb.w r3, [r4, #67] @ 0x43 - 8009626: 4a92 ldr r2, [pc, #584] @ (8009870 <_printf_float+0x2d0>) - 8009628: 4b92 ldr r3, [pc, #584] @ (8009874 <_printf_float+0x2d4>) - 800962a: f1ba 0f47 cmp.w sl, #71 @ 0x47 - 800962e: bf94 ite ls - 8009630: 4690 movls r8, r2 - 8009632: 4698 movhi r8, r3 - 8009634: 2303 movs r3, #3 - 8009636: f04f 0900 mov.w r9, #0 - 800963a: 6123 str r3, [r4, #16] - 800963c: f02b 0304 bic.w r3, fp, #4 - 8009640: 6023 str r3, [r4, #0] - 8009642: 4633 mov r3, r6 - 8009644: 4621 mov r1, r4 - 8009646: 4628 mov r0, r5 - 8009648: 9700 str r7, [sp, #0] - 800964a: aa0f add r2, sp, #60 @ 0x3c - 800964c: f000 f9d4 bl 80099f8 <_printf_common> - 8009650: 3001 adds r0, #1 - 8009652: f040 8090 bne.w 8009776 <_printf_float+0x1d6> - 8009656: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800965a: b011 add sp, #68 @ 0x44 - 800965c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8009660: 4642 mov r2, r8 - 8009662: 464b mov r3, r9 - 8009664: 4640 mov r0, r8 - 8009666: 4649 mov r1, r9 - 8009668: f7f7 fa46 bl 8000af8 <__aeabi_dcmpun> - 800966c: b148 cbz r0, 8009682 <_printf_float+0xe2> - 800966e: 464b mov r3, r9 - 8009670: 2b00 cmp r3, #0 - 8009672: bfb8 it lt - 8009674: 232d movlt r3, #45 @ 0x2d - 8009676: 4a80 ldr r2, [pc, #512] @ (8009878 <_printf_float+0x2d8>) - 8009678: bfb8 it lt - 800967a: f884 3043 strblt.w r3, [r4, #67] @ 0x43 - 800967e: 4b7f ldr r3, [pc, #508] @ (800987c <_printf_float+0x2dc>) - 8009680: e7d3 b.n 800962a <_printf_float+0x8a> - 8009682: 6863 ldr r3, [r4, #4] - 8009684: f00a 01df and.w r1, sl, #223 @ 0xdf - 8009688: 1c5a adds r2, r3, #1 - 800968a: d13f bne.n 800970c <_printf_float+0x16c> - 800968c: 2306 movs r3, #6 - 800968e: 6063 str r3, [r4, #4] - 8009690: 2200 movs r2, #0 - 8009692: f44b 6380 orr.w r3, fp, #1024 @ 0x400 - 8009696: 6023 str r3, [r4, #0] - 8009698: 9206 str r2, [sp, #24] - 800969a: aa0e add r2, sp, #56 @ 0x38 - 800969c: e9cd a204 strd sl, r2, [sp, #16] - 80096a0: aa0d add r2, sp, #52 @ 0x34 - 80096a2: 9203 str r2, [sp, #12] - 80096a4: f10d 0233 add.w r2, sp, #51 @ 0x33 - 80096a8: e9cd 3201 strd r3, r2, [sp, #4] - 80096ac: 6863 ldr r3, [r4, #4] - 80096ae: 4642 mov r2, r8 - 80096b0: 9300 str r3, [sp, #0] - 80096b2: 4628 mov r0, r5 - 80096b4: 464b mov r3, r9 - 80096b6: 910a str r1, [sp, #40] @ 0x28 - 80096b8: f7ff fed4 bl 8009464 <__cvt> - 80096bc: 990a ldr r1, [sp, #40] @ 0x28 - 80096be: 4680 mov r8, r0 - 80096c0: 2947 cmp r1, #71 @ 0x47 - 80096c2: 990d ldr r1, [sp, #52] @ 0x34 - 80096c4: d128 bne.n 8009718 <_printf_float+0x178> - 80096c6: 1cc8 adds r0, r1, #3 - 80096c8: db02 blt.n 80096d0 <_printf_float+0x130> - 80096ca: 6863 ldr r3, [r4, #4] - 80096cc: 4299 cmp r1, r3 - 80096ce: dd40 ble.n 8009752 <_printf_float+0x1b2> - 80096d0: f1aa 0a02 sub.w sl, sl, #2 - 80096d4: fa5f fa8a uxtb.w sl, sl - 80096d8: 4652 mov r2, sl - 80096da: 3901 subs r1, #1 - 80096dc: f104 0050 add.w r0, r4, #80 @ 0x50 - 80096e0: 910d str r1, [sp, #52] @ 0x34 - 80096e2: f7ff ff23 bl 800952c <__exponent> - 80096e6: 9a0e ldr r2, [sp, #56] @ 0x38 - 80096e8: 4681 mov r9, r0 - 80096ea: 1813 adds r3, r2, r0 - 80096ec: 2a01 cmp r2, #1 - 80096ee: 6123 str r3, [r4, #16] - 80096f0: dc02 bgt.n 80096f8 <_printf_float+0x158> - 80096f2: 6822 ldr r2, [r4, #0] - 80096f4: 07d2 lsls r2, r2, #31 - 80096f6: d501 bpl.n 80096fc <_printf_float+0x15c> - 80096f8: 3301 adds r3, #1 - 80096fa: 6123 str r3, [r4, #16] - 80096fc: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 - 8009700: 2b00 cmp r3, #0 - 8009702: d09e beq.n 8009642 <_printf_float+0xa2> - 8009704: 232d movs r3, #45 @ 0x2d - 8009706: f884 3043 strb.w r3, [r4, #67] @ 0x43 - 800970a: e79a b.n 8009642 <_printf_float+0xa2> - 800970c: 2947 cmp r1, #71 @ 0x47 - 800970e: d1bf bne.n 8009690 <_printf_float+0xf0> - 8009710: 2b00 cmp r3, #0 - 8009712: d1bd bne.n 8009690 <_printf_float+0xf0> - 8009714: 2301 movs r3, #1 - 8009716: e7ba b.n 800968e <_printf_float+0xee> - 8009718: f1ba 0f65 cmp.w sl, #101 @ 0x65 - 800971c: d9dc bls.n 80096d8 <_printf_float+0x138> - 800971e: f1ba 0f66 cmp.w sl, #102 @ 0x66 - 8009722: d118 bne.n 8009756 <_printf_float+0x1b6> - 8009724: 2900 cmp r1, #0 - 8009726: 6863 ldr r3, [r4, #4] - 8009728: dd0b ble.n 8009742 <_printf_float+0x1a2> - 800972a: 6121 str r1, [r4, #16] - 800972c: b913 cbnz r3, 8009734 <_printf_float+0x194> - 800972e: 6822 ldr r2, [r4, #0] - 8009730: 07d0 lsls r0, r2, #31 - 8009732: d502 bpl.n 800973a <_printf_float+0x19a> - 8009734: 3301 adds r3, #1 - 8009736: 440b add r3, r1 - 8009738: 6123 str r3, [r4, #16] - 800973a: f04f 0900 mov.w r9, #0 - 800973e: 65a1 str r1, [r4, #88] @ 0x58 - 8009740: e7dc b.n 80096fc <_printf_float+0x15c> - 8009742: b913 cbnz r3, 800974a <_printf_float+0x1aa> - 8009744: 6822 ldr r2, [r4, #0] - 8009746: 07d2 lsls r2, r2, #31 - 8009748: d501 bpl.n 800974e <_printf_float+0x1ae> - 800974a: 3302 adds r3, #2 - 800974c: e7f4 b.n 8009738 <_printf_float+0x198> - 800974e: 2301 movs r3, #1 - 8009750: e7f2 b.n 8009738 <_printf_float+0x198> - 8009752: f04f 0a67 mov.w sl, #103 @ 0x67 - 8009756: 9b0e ldr r3, [sp, #56] @ 0x38 - 8009758: 4299 cmp r1, r3 - 800975a: db05 blt.n 8009768 <_printf_float+0x1c8> - 800975c: 6823 ldr r3, [r4, #0] - 800975e: 6121 str r1, [r4, #16] - 8009760: 07d8 lsls r0, r3, #31 - 8009762: d5ea bpl.n 800973a <_printf_float+0x19a> - 8009764: 1c4b adds r3, r1, #1 - 8009766: e7e7 b.n 8009738 <_printf_float+0x198> - 8009768: 2900 cmp r1, #0 - 800976a: bfcc ite gt - 800976c: 2201 movgt r2, #1 - 800976e: f1c1 0202 rsble r2, r1, #2 - 8009772: 4413 add r3, r2 - 8009774: e7e0 b.n 8009738 <_printf_float+0x198> - 8009776: 6823 ldr r3, [r4, #0] - 8009778: 055a lsls r2, r3, #21 - 800977a: d407 bmi.n 800978c <_printf_float+0x1ec> - 800977c: 6923 ldr r3, [r4, #16] - 800977e: 4642 mov r2, r8 - 8009780: 4631 mov r1, r6 - 8009782: 4628 mov r0, r5 - 8009784: 47b8 blx r7 - 8009786: 3001 adds r0, #1 - 8009788: d12b bne.n 80097e2 <_printf_float+0x242> - 800978a: e764 b.n 8009656 <_printf_float+0xb6> - 800978c: f1ba 0f65 cmp.w sl, #101 @ 0x65 - 8009790: f240 80dc bls.w 800994c <_printf_float+0x3ac> - 8009794: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 - 8009798: 2200 movs r2, #0 - 800979a: 2300 movs r3, #0 - 800979c: f7f7 f97a bl 8000a94 <__aeabi_dcmpeq> - 80097a0: 2800 cmp r0, #0 - 80097a2: d033 beq.n 800980c <_printf_float+0x26c> - 80097a4: 2301 movs r3, #1 - 80097a6: 4631 mov r1, r6 - 80097a8: 4628 mov r0, r5 - 80097aa: 4a35 ldr r2, [pc, #212] @ (8009880 <_printf_float+0x2e0>) - 80097ac: 47b8 blx r7 - 80097ae: 3001 adds r0, #1 - 80097b0: f43f af51 beq.w 8009656 <_printf_float+0xb6> - 80097b4: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 - 80097b8: 4543 cmp r3, r8 - 80097ba: db02 blt.n 80097c2 <_printf_float+0x222> - 80097bc: 6823 ldr r3, [r4, #0] - 80097be: 07d8 lsls r0, r3, #31 - 80097c0: d50f bpl.n 80097e2 <_printf_float+0x242> - 80097c2: e9dd 2308 ldrd r2, r3, [sp, #32] - 80097c6: 4631 mov r1, r6 - 80097c8: 4628 mov r0, r5 - 80097ca: 47b8 blx r7 - 80097cc: 3001 adds r0, #1 - 80097ce: f43f af42 beq.w 8009656 <_printf_float+0xb6> - 80097d2: f04f 0900 mov.w r9, #0 - 80097d6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff - 80097da: f104 0a1a add.w sl, r4, #26 - 80097de: 45c8 cmp r8, r9 - 80097e0: dc09 bgt.n 80097f6 <_printf_float+0x256> - 80097e2: 6823 ldr r3, [r4, #0] - 80097e4: 079b lsls r3, r3, #30 - 80097e6: f100 8102 bmi.w 80099ee <_printf_float+0x44e> - 80097ea: 68e0 ldr r0, [r4, #12] - 80097ec: 9b0f ldr r3, [sp, #60] @ 0x3c - 80097ee: 4298 cmp r0, r3 - 80097f0: bfb8 it lt - 80097f2: 4618 movlt r0, r3 - 80097f4: e731 b.n 800965a <_printf_float+0xba> - 80097f6: 2301 movs r3, #1 - 80097f8: 4652 mov r2, sl - 80097fa: 4631 mov r1, r6 - 80097fc: 4628 mov r0, r5 - 80097fe: 47b8 blx r7 - 8009800: 3001 adds r0, #1 - 8009802: f43f af28 beq.w 8009656 <_printf_float+0xb6> - 8009806: f109 0901 add.w r9, r9, #1 - 800980a: e7e8 b.n 80097de <_printf_float+0x23e> - 800980c: 9b0d ldr r3, [sp, #52] @ 0x34 - 800980e: 2b00 cmp r3, #0 - 8009810: dc38 bgt.n 8009884 <_printf_float+0x2e4> - 8009812: 2301 movs r3, #1 - 8009814: 4631 mov r1, r6 - 8009816: 4628 mov r0, r5 - 8009818: 4a19 ldr r2, [pc, #100] @ (8009880 <_printf_float+0x2e0>) - 800981a: 47b8 blx r7 - 800981c: 3001 adds r0, #1 - 800981e: f43f af1a beq.w 8009656 <_printf_float+0xb6> - 8009822: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 - 8009826: ea59 0303 orrs.w r3, r9, r3 - 800982a: d102 bne.n 8009832 <_printf_float+0x292> - 800982c: 6823 ldr r3, [r4, #0] - 800982e: 07d9 lsls r1, r3, #31 - 8009830: d5d7 bpl.n 80097e2 <_printf_float+0x242> - 8009832: e9dd 2308 ldrd r2, r3, [sp, #32] - 8009836: 4631 mov r1, r6 - 8009838: 4628 mov r0, r5 - 800983a: 47b8 blx r7 - 800983c: 3001 adds r0, #1 - 800983e: f43f af0a beq.w 8009656 <_printf_float+0xb6> - 8009842: f04f 0a00 mov.w sl, #0 - 8009846: f104 0b1a add.w fp, r4, #26 - 800984a: 9b0d ldr r3, [sp, #52] @ 0x34 - 800984c: 425b negs r3, r3 - 800984e: 4553 cmp r3, sl - 8009850: dc01 bgt.n 8009856 <_printf_float+0x2b6> - 8009852: 464b mov r3, r9 - 8009854: e793 b.n 800977e <_printf_float+0x1de> - 8009856: 2301 movs r3, #1 - 8009858: 465a mov r2, fp - 800985a: 4631 mov r1, r6 - 800985c: 4628 mov r0, r5 - 800985e: 47b8 blx r7 - 8009860: 3001 adds r0, #1 - 8009862: f43f aef8 beq.w 8009656 <_printf_float+0xb6> - 8009866: f10a 0a01 add.w sl, sl, #1 - 800986a: e7ee b.n 800984a <_printf_float+0x2aa> - 800986c: 7fefffff .word 0x7fefffff - 8009870: 0800e004 .word 0x0800e004 - 8009874: 0800e008 .word 0x0800e008 - 8009878: 0800e00c .word 0x0800e00c - 800987c: 0800e010 .word 0x0800e010 - 8009880: 0800e4e9 .word 0x0800e4e9 - 8009884: 6da3 ldr r3, [r4, #88] @ 0x58 - 8009886: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 - 800988a: 4553 cmp r3, sl - 800988c: bfa8 it ge - 800988e: 4653 movge r3, sl - 8009890: 2b00 cmp r3, #0 - 8009892: 4699 mov r9, r3 - 8009894: dc36 bgt.n 8009904 <_printf_float+0x364> - 8009896: f04f 0b00 mov.w fp, #0 - 800989a: ea29 79e9 bic.w r9, r9, r9, asr #31 - 800989e: f104 021a add.w r2, r4, #26 - 80098a2: 6da3 ldr r3, [r4, #88] @ 0x58 - 80098a4: 930a str r3, [sp, #40] @ 0x28 - 80098a6: eba3 0309 sub.w r3, r3, r9 - 80098aa: 455b cmp r3, fp - 80098ac: dc31 bgt.n 8009912 <_printf_float+0x372> - 80098ae: 9b0d ldr r3, [sp, #52] @ 0x34 - 80098b0: 459a cmp sl, r3 - 80098b2: dc3a bgt.n 800992a <_printf_float+0x38a> - 80098b4: 6823 ldr r3, [r4, #0] - 80098b6: 07da lsls r2, r3, #31 - 80098b8: d437 bmi.n 800992a <_printf_float+0x38a> - 80098ba: 9b0d ldr r3, [sp, #52] @ 0x34 - 80098bc: ebaa 0903 sub.w r9, sl, r3 - 80098c0: 9b0a ldr r3, [sp, #40] @ 0x28 - 80098c2: ebaa 0303 sub.w r3, sl, r3 - 80098c6: 4599 cmp r9, r3 - 80098c8: bfa8 it ge - 80098ca: 4699 movge r9, r3 - 80098cc: f1b9 0f00 cmp.w r9, #0 - 80098d0: dc33 bgt.n 800993a <_printf_float+0x39a> - 80098d2: f04f 0800 mov.w r8, #0 - 80098d6: ea29 79e9 bic.w r9, r9, r9, asr #31 - 80098da: f104 0b1a add.w fp, r4, #26 - 80098de: 9b0d ldr r3, [sp, #52] @ 0x34 - 80098e0: ebaa 0303 sub.w r3, sl, r3 - 80098e4: eba3 0309 sub.w r3, r3, r9 - 80098e8: 4543 cmp r3, r8 - 80098ea: f77f af7a ble.w 80097e2 <_printf_float+0x242> - 80098ee: 2301 movs r3, #1 - 80098f0: 465a mov r2, fp - 80098f2: 4631 mov r1, r6 - 80098f4: 4628 mov r0, r5 - 80098f6: 47b8 blx r7 - 80098f8: 3001 adds r0, #1 - 80098fa: f43f aeac beq.w 8009656 <_printf_float+0xb6> - 80098fe: f108 0801 add.w r8, r8, #1 - 8009902: e7ec b.n 80098de <_printf_float+0x33e> - 8009904: 4642 mov r2, r8 - 8009906: 4631 mov r1, r6 - 8009908: 4628 mov r0, r5 - 800990a: 47b8 blx r7 - 800990c: 3001 adds r0, #1 - 800990e: d1c2 bne.n 8009896 <_printf_float+0x2f6> - 8009910: e6a1 b.n 8009656 <_printf_float+0xb6> - 8009912: 2301 movs r3, #1 - 8009914: 4631 mov r1, r6 - 8009916: 4628 mov r0, r5 - 8009918: 920a str r2, [sp, #40] @ 0x28 - 800991a: 47b8 blx r7 - 800991c: 3001 adds r0, #1 - 800991e: f43f ae9a beq.w 8009656 <_printf_float+0xb6> - 8009922: 9a0a ldr r2, [sp, #40] @ 0x28 - 8009924: f10b 0b01 add.w fp, fp, #1 - 8009928: e7bb b.n 80098a2 <_printf_float+0x302> - 800992a: 4631 mov r1, r6 - 800992c: e9dd 2308 ldrd r2, r3, [sp, #32] - 8009930: 4628 mov r0, r5 - 8009932: 47b8 blx r7 - 8009934: 3001 adds r0, #1 - 8009936: d1c0 bne.n 80098ba <_printf_float+0x31a> - 8009938: e68d b.n 8009656 <_printf_float+0xb6> - 800993a: 9a0a ldr r2, [sp, #40] @ 0x28 - 800993c: 464b mov r3, r9 - 800993e: 4631 mov r1, r6 - 8009940: 4628 mov r0, r5 - 8009942: 4442 add r2, r8 - 8009944: 47b8 blx r7 - 8009946: 3001 adds r0, #1 - 8009948: d1c3 bne.n 80098d2 <_printf_float+0x332> - 800994a: e684 b.n 8009656 <_printf_float+0xb6> - 800994c: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 - 8009950: f1ba 0f01 cmp.w sl, #1 - 8009954: dc01 bgt.n 800995a <_printf_float+0x3ba> - 8009956: 07db lsls r3, r3, #31 - 8009958: d536 bpl.n 80099c8 <_printf_float+0x428> - 800995a: 2301 movs r3, #1 - 800995c: 4642 mov r2, r8 - 800995e: 4631 mov r1, r6 - 8009960: 4628 mov r0, r5 - 8009962: 47b8 blx r7 - 8009964: 3001 adds r0, #1 - 8009966: f43f ae76 beq.w 8009656 <_printf_float+0xb6> - 800996a: e9dd 2308 ldrd r2, r3, [sp, #32] - 800996e: 4631 mov r1, r6 - 8009970: 4628 mov r0, r5 - 8009972: 47b8 blx r7 - 8009974: 3001 adds r0, #1 - 8009976: f43f ae6e beq.w 8009656 <_printf_float+0xb6> - 800997a: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 - 800997e: 2200 movs r2, #0 - 8009980: 2300 movs r3, #0 - 8009982: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff - 8009986: f7f7 f885 bl 8000a94 <__aeabi_dcmpeq> - 800998a: b9c0 cbnz r0, 80099be <_printf_float+0x41e> - 800998c: 4653 mov r3, sl - 800998e: f108 0201 add.w r2, r8, #1 - 8009992: 4631 mov r1, r6 - 8009994: 4628 mov r0, r5 - 8009996: 47b8 blx r7 - 8009998: 3001 adds r0, #1 - 800999a: d10c bne.n 80099b6 <_printf_float+0x416> - 800999c: e65b b.n 8009656 <_printf_float+0xb6> - 800999e: 2301 movs r3, #1 - 80099a0: 465a mov r2, fp - 80099a2: 4631 mov r1, r6 - 80099a4: 4628 mov r0, r5 - 80099a6: 47b8 blx r7 - 80099a8: 3001 adds r0, #1 - 80099aa: f43f ae54 beq.w 8009656 <_printf_float+0xb6> - 80099ae: f108 0801 add.w r8, r8, #1 - 80099b2: 45d0 cmp r8, sl - 80099b4: dbf3 blt.n 800999e <_printf_float+0x3fe> - 80099b6: 464b mov r3, r9 - 80099b8: f104 0250 add.w r2, r4, #80 @ 0x50 - 80099bc: e6e0 b.n 8009780 <_printf_float+0x1e0> - 80099be: f04f 0800 mov.w r8, #0 - 80099c2: f104 0b1a add.w fp, r4, #26 - 80099c6: e7f4 b.n 80099b2 <_printf_float+0x412> - 80099c8: 2301 movs r3, #1 - 80099ca: 4642 mov r2, r8 - 80099cc: e7e1 b.n 8009992 <_printf_float+0x3f2> - 80099ce: 2301 movs r3, #1 - 80099d0: 464a mov r2, r9 - 80099d2: 4631 mov r1, r6 - 80099d4: 4628 mov r0, r5 - 80099d6: 47b8 blx r7 - 80099d8: 3001 adds r0, #1 - 80099da: f43f ae3c beq.w 8009656 <_printf_float+0xb6> - 80099de: f108 0801 add.w r8, r8, #1 - 80099e2: 68e3 ldr r3, [r4, #12] - 80099e4: 990f ldr r1, [sp, #60] @ 0x3c - 80099e6: 1a5b subs r3, r3, r1 - 80099e8: 4543 cmp r3, r8 - 80099ea: dcf0 bgt.n 80099ce <_printf_float+0x42e> - 80099ec: e6fd b.n 80097ea <_printf_float+0x24a> - 80099ee: f04f 0800 mov.w r8, #0 - 80099f2: f104 0919 add.w r9, r4, #25 - 80099f6: e7f4 b.n 80099e2 <_printf_float+0x442> - -080099f8 <_printf_common>: - 80099f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 80099fc: 4616 mov r6, r2 - 80099fe: 4698 mov r8, r3 - 8009a00: 688a ldr r2, [r1, #8] - 8009a02: 690b ldr r3, [r1, #16] - 8009a04: 4607 mov r7, r0 - 8009a06: 4293 cmp r3, r2 - 8009a08: bfb8 it lt - 8009a0a: 4613 movlt r3, r2 - 8009a0c: 6033 str r3, [r6, #0] - 8009a0e: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 - 8009a12: 460c mov r4, r1 - 8009a14: f8dd 9020 ldr.w r9, [sp, #32] - 8009a18: b10a cbz r2, 8009a1e <_printf_common+0x26> - 8009a1a: 3301 adds r3, #1 - 8009a1c: 6033 str r3, [r6, #0] - 8009a1e: 6823 ldr r3, [r4, #0] - 8009a20: 0699 lsls r1, r3, #26 - 8009a22: bf42 ittt mi - 8009a24: 6833 ldrmi r3, [r6, #0] - 8009a26: 3302 addmi r3, #2 - 8009a28: 6033 strmi r3, [r6, #0] - 8009a2a: 6825 ldr r5, [r4, #0] - 8009a2c: f015 0506 ands.w r5, r5, #6 - 8009a30: d106 bne.n 8009a40 <_printf_common+0x48> - 8009a32: f104 0a19 add.w sl, r4, #25 - 8009a36: 68e3 ldr r3, [r4, #12] - 8009a38: 6832 ldr r2, [r6, #0] - 8009a3a: 1a9b subs r3, r3, r2 - 8009a3c: 42ab cmp r3, r5 - 8009a3e: dc2b bgt.n 8009a98 <_printf_common+0xa0> - 8009a40: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 - 8009a44: 6822 ldr r2, [r4, #0] - 8009a46: 3b00 subs r3, #0 - 8009a48: bf18 it ne - 8009a4a: 2301 movne r3, #1 - 8009a4c: 0692 lsls r2, r2, #26 - 8009a4e: d430 bmi.n 8009ab2 <_printf_common+0xba> - 8009a50: 4641 mov r1, r8 - 8009a52: 4638 mov r0, r7 - 8009a54: f104 0243 add.w r2, r4, #67 @ 0x43 - 8009a58: 47c8 blx r9 - 8009a5a: 3001 adds r0, #1 - 8009a5c: d023 beq.n 8009aa6 <_printf_common+0xae> - 8009a5e: 6823 ldr r3, [r4, #0] - 8009a60: 6922 ldr r2, [r4, #16] - 8009a62: f003 0306 and.w r3, r3, #6 - 8009a66: 2b04 cmp r3, #4 - 8009a68: bf14 ite ne - 8009a6a: 2500 movne r5, #0 - 8009a6c: 6833 ldreq r3, [r6, #0] - 8009a6e: f04f 0600 mov.w r6, #0 - 8009a72: bf08 it eq - 8009a74: 68e5 ldreq r5, [r4, #12] - 8009a76: f104 041a add.w r4, r4, #26 - 8009a7a: bf08 it eq - 8009a7c: 1aed subeq r5, r5, r3 - 8009a7e: f854 3c12 ldr.w r3, [r4, #-18] - 8009a82: bf08 it eq - 8009a84: ea25 75e5 biceq.w r5, r5, r5, asr #31 - 8009a88: 4293 cmp r3, r2 - 8009a8a: bfc4 itt gt - 8009a8c: 1a9b subgt r3, r3, r2 - 8009a8e: 18ed addgt r5, r5, r3 - 8009a90: 42b5 cmp r5, r6 - 8009a92: d11a bne.n 8009aca <_printf_common+0xd2> - 8009a94: 2000 movs r0, #0 - 8009a96: e008 b.n 8009aaa <_printf_common+0xb2> - 8009a98: 2301 movs r3, #1 - 8009a9a: 4652 mov r2, sl - 8009a9c: 4641 mov r1, r8 - 8009a9e: 4638 mov r0, r7 - 8009aa0: 47c8 blx r9 - 8009aa2: 3001 adds r0, #1 - 8009aa4: d103 bne.n 8009aae <_printf_common+0xb6> - 8009aa6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8009aaa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8009aae: 3501 adds r5, #1 - 8009ab0: e7c1 b.n 8009a36 <_printf_common+0x3e> - 8009ab2: 2030 movs r0, #48 @ 0x30 - 8009ab4: 18e1 adds r1, r4, r3 - 8009ab6: f881 0043 strb.w r0, [r1, #67] @ 0x43 - 8009aba: 1c5a adds r2, r3, #1 - 8009abc: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 - 8009ac0: 4422 add r2, r4 - 8009ac2: 3302 adds r3, #2 - 8009ac4: f882 1043 strb.w r1, [r2, #67] @ 0x43 - 8009ac8: e7c2 b.n 8009a50 <_printf_common+0x58> - 8009aca: 2301 movs r3, #1 - 8009acc: 4622 mov r2, r4 - 8009ace: 4641 mov r1, r8 - 8009ad0: 4638 mov r0, r7 - 8009ad2: 47c8 blx r9 - 8009ad4: 3001 adds r0, #1 - 8009ad6: d0e6 beq.n 8009aa6 <_printf_common+0xae> - 8009ad8: 3601 adds r6, #1 - 8009ada: e7d9 b.n 8009a90 <_printf_common+0x98> - -08009adc <_printf_i>: - 8009adc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 8009ae0: 7e0f ldrb r7, [r1, #24] - 8009ae2: 4691 mov r9, r2 - 8009ae4: 2f78 cmp r7, #120 @ 0x78 - 8009ae6: 4680 mov r8, r0 - 8009ae8: 460c mov r4, r1 - 8009aea: 469a mov sl, r3 - 8009aec: 9e0c ldr r6, [sp, #48] @ 0x30 - 8009aee: f101 0243 add.w r2, r1, #67 @ 0x43 - 8009af2: d807 bhi.n 8009b04 <_printf_i+0x28> - 8009af4: 2f62 cmp r7, #98 @ 0x62 - 8009af6: d80a bhi.n 8009b0e <_printf_i+0x32> - 8009af8: 2f00 cmp r7, #0 - 8009afa: f000 80d3 beq.w 8009ca4 <_printf_i+0x1c8> - 8009afe: 2f58 cmp r7, #88 @ 0x58 - 8009b00: f000 80ba beq.w 8009c78 <_printf_i+0x19c> - 8009b04: f104 0642 add.w r6, r4, #66 @ 0x42 - 8009b08: f884 7042 strb.w r7, [r4, #66] @ 0x42 - 8009b0c: e03a b.n 8009b84 <_printf_i+0xa8> - 8009b0e: f1a7 0363 sub.w r3, r7, #99 @ 0x63 - 8009b12: 2b15 cmp r3, #21 - 8009b14: d8f6 bhi.n 8009b04 <_printf_i+0x28> - 8009b16: a101 add r1, pc, #4 @ (adr r1, 8009b1c <_printf_i+0x40>) - 8009b18: f851 f023 ldr.w pc, [r1, r3, lsl #2] - 8009b1c: 08009b75 .word 0x08009b75 - 8009b20: 08009b89 .word 0x08009b89 - 8009b24: 08009b05 .word 0x08009b05 - 8009b28: 08009b05 .word 0x08009b05 - 8009b2c: 08009b05 .word 0x08009b05 - 8009b30: 08009b05 .word 0x08009b05 - 8009b34: 08009b89 .word 0x08009b89 - 8009b38: 08009b05 .word 0x08009b05 - 8009b3c: 08009b05 .word 0x08009b05 - 8009b40: 08009b05 .word 0x08009b05 - 8009b44: 08009b05 .word 0x08009b05 - 8009b48: 08009c8b .word 0x08009c8b - 8009b4c: 08009bb3 .word 0x08009bb3 - 8009b50: 08009c45 .word 0x08009c45 - 8009b54: 08009b05 .word 0x08009b05 - 8009b58: 08009b05 .word 0x08009b05 - 8009b5c: 08009cad .word 0x08009cad - 8009b60: 08009b05 .word 0x08009b05 - 8009b64: 08009bb3 .word 0x08009bb3 - 8009b68: 08009b05 .word 0x08009b05 - 8009b6c: 08009b05 .word 0x08009b05 - 8009b70: 08009c4d .word 0x08009c4d - 8009b74: 6833 ldr r3, [r6, #0] - 8009b76: 1d1a adds r2, r3, #4 - 8009b78: 681b ldr r3, [r3, #0] - 8009b7a: 6032 str r2, [r6, #0] - 8009b7c: f104 0642 add.w r6, r4, #66 @ 0x42 - 8009b80: f884 3042 strb.w r3, [r4, #66] @ 0x42 - 8009b84: 2301 movs r3, #1 - 8009b86: e09e b.n 8009cc6 <_printf_i+0x1ea> - 8009b88: 6833 ldr r3, [r6, #0] - 8009b8a: 6820 ldr r0, [r4, #0] - 8009b8c: 1d19 adds r1, r3, #4 - 8009b8e: 6031 str r1, [r6, #0] - 8009b90: 0606 lsls r6, r0, #24 - 8009b92: d501 bpl.n 8009b98 <_printf_i+0xbc> - 8009b94: 681d ldr r5, [r3, #0] - 8009b96: e003 b.n 8009ba0 <_printf_i+0xc4> - 8009b98: 0645 lsls r5, r0, #25 - 8009b9a: d5fb bpl.n 8009b94 <_printf_i+0xb8> - 8009b9c: f9b3 5000 ldrsh.w r5, [r3] - 8009ba0: 2d00 cmp r5, #0 - 8009ba2: da03 bge.n 8009bac <_printf_i+0xd0> - 8009ba4: 232d movs r3, #45 @ 0x2d - 8009ba6: 426d negs r5, r5 - 8009ba8: f884 3043 strb.w r3, [r4, #67] @ 0x43 - 8009bac: 230a movs r3, #10 - 8009bae: 4859 ldr r0, [pc, #356] @ (8009d14 <_printf_i+0x238>) - 8009bb0: e011 b.n 8009bd6 <_printf_i+0xfa> - 8009bb2: 6821 ldr r1, [r4, #0] - 8009bb4: 6833 ldr r3, [r6, #0] - 8009bb6: 0608 lsls r0, r1, #24 - 8009bb8: f853 5b04 ldr.w r5, [r3], #4 - 8009bbc: d402 bmi.n 8009bc4 <_printf_i+0xe8> - 8009bbe: 0649 lsls r1, r1, #25 - 8009bc0: bf48 it mi - 8009bc2: b2ad uxthmi r5, r5 - 8009bc4: 2f6f cmp r7, #111 @ 0x6f - 8009bc6: 6033 str r3, [r6, #0] - 8009bc8: bf14 ite ne - 8009bca: 230a movne r3, #10 - 8009bcc: 2308 moveq r3, #8 - 8009bce: 4851 ldr r0, [pc, #324] @ (8009d14 <_printf_i+0x238>) - 8009bd0: 2100 movs r1, #0 - 8009bd2: f884 1043 strb.w r1, [r4, #67] @ 0x43 - 8009bd6: 6866 ldr r6, [r4, #4] - 8009bd8: 2e00 cmp r6, #0 - 8009bda: bfa8 it ge - 8009bdc: 6821 ldrge r1, [r4, #0] - 8009bde: 60a6 str r6, [r4, #8] - 8009be0: bfa4 itt ge - 8009be2: f021 0104 bicge.w r1, r1, #4 - 8009be6: 6021 strge r1, [r4, #0] - 8009be8: b90d cbnz r5, 8009bee <_printf_i+0x112> - 8009bea: 2e00 cmp r6, #0 - 8009bec: d04b beq.n 8009c86 <_printf_i+0x1aa> - 8009bee: 4616 mov r6, r2 - 8009bf0: fbb5 f1f3 udiv r1, r5, r3 - 8009bf4: fb03 5711 mls r7, r3, r1, r5 - 8009bf8: 5dc7 ldrb r7, [r0, r7] - 8009bfa: f806 7d01 strb.w r7, [r6, #-1]! - 8009bfe: 462f mov r7, r5 - 8009c00: 42bb cmp r3, r7 - 8009c02: 460d mov r5, r1 - 8009c04: d9f4 bls.n 8009bf0 <_printf_i+0x114> - 8009c06: 2b08 cmp r3, #8 - 8009c08: d10b bne.n 8009c22 <_printf_i+0x146> - 8009c0a: 6823 ldr r3, [r4, #0] - 8009c0c: 07df lsls r7, r3, #31 - 8009c0e: d508 bpl.n 8009c22 <_printf_i+0x146> - 8009c10: 6923 ldr r3, [r4, #16] - 8009c12: 6861 ldr r1, [r4, #4] - 8009c14: 4299 cmp r1, r3 - 8009c16: bfde ittt le - 8009c18: 2330 movle r3, #48 @ 0x30 - 8009c1a: f806 3c01 strble.w r3, [r6, #-1] - 8009c1e: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff - 8009c22: 1b92 subs r2, r2, r6 - 8009c24: 6122 str r2, [r4, #16] - 8009c26: 464b mov r3, r9 - 8009c28: 4621 mov r1, r4 - 8009c2a: 4640 mov r0, r8 - 8009c2c: f8cd a000 str.w sl, [sp] - 8009c30: aa03 add r2, sp, #12 - 8009c32: f7ff fee1 bl 80099f8 <_printf_common> - 8009c36: 3001 adds r0, #1 - 8009c38: d14a bne.n 8009cd0 <_printf_i+0x1f4> - 8009c3a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8009c3e: b004 add sp, #16 - 8009c40: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8009c44: 6823 ldr r3, [r4, #0] - 8009c46: f043 0320 orr.w r3, r3, #32 - 8009c4a: 6023 str r3, [r4, #0] - 8009c4c: 2778 movs r7, #120 @ 0x78 - 8009c4e: 4832 ldr r0, [pc, #200] @ (8009d18 <_printf_i+0x23c>) - 8009c50: f884 7045 strb.w r7, [r4, #69] @ 0x45 - 8009c54: 6823 ldr r3, [r4, #0] - 8009c56: 6831 ldr r1, [r6, #0] - 8009c58: 061f lsls r7, r3, #24 - 8009c5a: f851 5b04 ldr.w r5, [r1], #4 - 8009c5e: d402 bmi.n 8009c66 <_printf_i+0x18a> - 8009c60: 065f lsls r7, r3, #25 - 8009c62: bf48 it mi - 8009c64: b2ad uxthmi r5, r5 - 8009c66: 6031 str r1, [r6, #0] - 8009c68: 07d9 lsls r1, r3, #31 - 8009c6a: bf44 itt mi - 8009c6c: f043 0320 orrmi.w r3, r3, #32 - 8009c70: 6023 strmi r3, [r4, #0] - 8009c72: b11d cbz r5, 8009c7c <_printf_i+0x1a0> - 8009c74: 2310 movs r3, #16 - 8009c76: e7ab b.n 8009bd0 <_printf_i+0xf4> - 8009c78: 4826 ldr r0, [pc, #152] @ (8009d14 <_printf_i+0x238>) - 8009c7a: e7e9 b.n 8009c50 <_printf_i+0x174> - 8009c7c: 6823 ldr r3, [r4, #0] - 8009c7e: f023 0320 bic.w r3, r3, #32 - 8009c82: 6023 str r3, [r4, #0] - 8009c84: e7f6 b.n 8009c74 <_printf_i+0x198> - 8009c86: 4616 mov r6, r2 - 8009c88: e7bd b.n 8009c06 <_printf_i+0x12a> - 8009c8a: 6833 ldr r3, [r6, #0] - 8009c8c: 6825 ldr r5, [r4, #0] - 8009c8e: 1d18 adds r0, r3, #4 - 8009c90: 6961 ldr r1, [r4, #20] - 8009c92: 6030 str r0, [r6, #0] - 8009c94: 062e lsls r6, r5, #24 - 8009c96: 681b ldr r3, [r3, #0] - 8009c98: d501 bpl.n 8009c9e <_printf_i+0x1c2> - 8009c9a: 6019 str r1, [r3, #0] - 8009c9c: e002 b.n 8009ca4 <_printf_i+0x1c8> - 8009c9e: 0668 lsls r0, r5, #25 - 8009ca0: d5fb bpl.n 8009c9a <_printf_i+0x1be> - 8009ca2: 8019 strh r1, [r3, #0] - 8009ca4: 2300 movs r3, #0 - 8009ca6: 4616 mov r6, r2 - 8009ca8: 6123 str r3, [r4, #16] - 8009caa: e7bc b.n 8009c26 <_printf_i+0x14a> - 8009cac: 6833 ldr r3, [r6, #0] - 8009cae: 2100 movs r1, #0 - 8009cb0: 1d1a adds r2, r3, #4 - 8009cb2: 6032 str r2, [r6, #0] - 8009cb4: 681e ldr r6, [r3, #0] - 8009cb6: 6862 ldr r2, [r4, #4] - 8009cb8: 4630 mov r0, r6 - 8009cba: f000 fece bl 800aa5a - 8009cbe: b108 cbz r0, 8009cc4 <_printf_i+0x1e8> - 8009cc0: 1b80 subs r0, r0, r6 - 8009cc2: 6060 str r0, [r4, #4] - 8009cc4: 6863 ldr r3, [r4, #4] - 8009cc6: 6123 str r3, [r4, #16] - 8009cc8: 2300 movs r3, #0 - 8009cca: f884 3043 strb.w r3, [r4, #67] @ 0x43 - 8009cce: e7aa b.n 8009c26 <_printf_i+0x14a> - 8009cd0: 4632 mov r2, r6 - 8009cd2: 4649 mov r1, r9 - 8009cd4: 4640 mov r0, r8 - 8009cd6: 6923 ldr r3, [r4, #16] - 8009cd8: 47d0 blx sl - 8009cda: 3001 adds r0, #1 - 8009cdc: d0ad beq.n 8009c3a <_printf_i+0x15e> - 8009cde: 6823 ldr r3, [r4, #0] - 8009ce0: 079b lsls r3, r3, #30 - 8009ce2: d413 bmi.n 8009d0c <_printf_i+0x230> - 8009ce4: 68e0 ldr r0, [r4, #12] - 8009ce6: 9b03 ldr r3, [sp, #12] - 8009ce8: 4298 cmp r0, r3 - 8009cea: bfb8 it lt - 8009cec: 4618 movlt r0, r3 - 8009cee: e7a6 b.n 8009c3e <_printf_i+0x162> - 8009cf0: 2301 movs r3, #1 - 8009cf2: 4632 mov r2, r6 - 8009cf4: 4649 mov r1, r9 - 8009cf6: 4640 mov r0, r8 - 8009cf8: 47d0 blx sl - 8009cfa: 3001 adds r0, #1 - 8009cfc: d09d beq.n 8009c3a <_printf_i+0x15e> - 8009cfe: 3501 adds r5, #1 - 8009d00: 68e3 ldr r3, [r4, #12] - 8009d02: 9903 ldr r1, [sp, #12] - 8009d04: 1a5b subs r3, r3, r1 - 8009d06: 42ab cmp r3, r5 - 8009d08: dcf2 bgt.n 8009cf0 <_printf_i+0x214> - 8009d0a: e7eb b.n 8009ce4 <_printf_i+0x208> - 8009d0c: 2500 movs r5, #0 - 8009d0e: f104 0619 add.w r6, r4, #25 - 8009d12: e7f5 b.n 8009d00 <_printf_i+0x224> - 8009d14: 0800e014 .word 0x0800e014 - 8009d18: 0800e025 .word 0x0800e025 - -08009d1c : - 8009d1c: b40c push {r2, r3} - 8009d1e: b530 push {r4, r5, lr} - 8009d20: 4b17 ldr r3, [pc, #92] @ (8009d80 ) - 8009d22: 1e0c subs r4, r1, #0 - 8009d24: 681d ldr r5, [r3, #0] - 8009d26: b09d sub sp, #116 @ 0x74 - 8009d28: da08 bge.n 8009d3c - 8009d2a: 238b movs r3, #139 @ 0x8b - 8009d2c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8009d30: 602b str r3, [r5, #0] - 8009d32: b01d add sp, #116 @ 0x74 - 8009d34: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8009d38: b002 add sp, #8 - 8009d3a: 4770 bx lr - 8009d3c: f44f 7302 mov.w r3, #520 @ 0x208 - 8009d40: f8ad 3014 strh.w r3, [sp, #20] - 8009d44: bf0c ite eq - 8009d46: 4623 moveq r3, r4 - 8009d48: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff - 8009d4c: 9304 str r3, [sp, #16] - 8009d4e: 9307 str r3, [sp, #28] - 8009d50: f64f 73ff movw r3, #65535 @ 0xffff - 8009d54: 9002 str r0, [sp, #8] - 8009d56: 9006 str r0, [sp, #24] - 8009d58: f8ad 3016 strh.w r3, [sp, #22] - 8009d5c: 4628 mov r0, r5 - 8009d5e: ab21 add r3, sp, #132 @ 0x84 - 8009d60: 9a20 ldr r2, [sp, #128] @ 0x80 - 8009d62: a902 add r1, sp, #8 - 8009d64: 9301 str r3, [sp, #4] - 8009d66: f001 fda9 bl 800b8bc <_svfiprintf_r> - 8009d6a: 1c43 adds r3, r0, #1 - 8009d6c: bfbc itt lt - 8009d6e: 238b movlt r3, #139 @ 0x8b - 8009d70: 602b strlt r3, [r5, #0] - 8009d72: 2c00 cmp r4, #0 - 8009d74: d0dd beq.n 8009d32 - 8009d76: 2200 movs r2, #0 - 8009d78: 9b02 ldr r3, [sp, #8] - 8009d7a: 701a strb r2, [r3, #0] - 8009d7c: e7d9 b.n 8009d32 - 8009d7e: bf00 nop - 8009d80: 20000028 .word 0x20000028 - -08009d84 : - 8009d84: 2300 movs r3, #0 - 8009d86: b510 push {r4, lr} - 8009d88: 4604 mov r4, r0 - 8009d8a: e9c0 3300 strd r3, r3, [r0] - 8009d8e: e9c0 3304 strd r3, r3, [r0, #16] - 8009d92: 6083 str r3, [r0, #8] - 8009d94: 8181 strh r1, [r0, #12] - 8009d96: 6643 str r3, [r0, #100] @ 0x64 - 8009d98: 81c2 strh r2, [r0, #14] - 8009d9a: 6183 str r3, [r0, #24] - 8009d9c: 4619 mov r1, r3 - 8009d9e: 2208 movs r2, #8 - 8009da0: 305c adds r0, #92 @ 0x5c - 8009da2: f000 f96d bl 800a080 - 8009da6: 4b0d ldr r3, [pc, #52] @ (8009ddc ) - 8009da8: 6224 str r4, [r4, #32] - 8009daa: 6263 str r3, [r4, #36] @ 0x24 - 8009dac: 4b0c ldr r3, [pc, #48] @ (8009de0 ) - 8009dae: 62a3 str r3, [r4, #40] @ 0x28 - 8009db0: 4b0c ldr r3, [pc, #48] @ (8009de4 ) - 8009db2: 62e3 str r3, [r4, #44] @ 0x2c - 8009db4: 4b0c ldr r3, [pc, #48] @ (8009de8 ) - 8009db6: 6323 str r3, [r4, #48] @ 0x30 - 8009db8: 4b0c ldr r3, [pc, #48] @ (8009dec ) - 8009dba: 429c cmp r4, r3 - 8009dbc: d006 beq.n 8009dcc - 8009dbe: f103 0268 add.w r2, r3, #104 @ 0x68 - 8009dc2: 4294 cmp r4, r2 - 8009dc4: d002 beq.n 8009dcc - 8009dc6: 33d0 adds r3, #208 @ 0xd0 - 8009dc8: 429c cmp r4, r3 - 8009dca: d105 bne.n 8009dd8 - 8009dcc: f104 0058 add.w r0, r4, #88 @ 0x58 - 8009dd0: e8bd 4010 ldmia.w sp!, {r4, lr} - 8009dd4: f000 be3c b.w 800aa50 <__retarget_lock_init_recursive> - 8009dd8: bd10 pop {r4, pc} - 8009dda: bf00 nop - 8009ddc: 0800c755 .word 0x0800c755 - 8009de0: 0800c77b .word 0x0800c77b - 8009de4: 0800c7b3 .word 0x0800c7b3 - 8009de8: 0800c7d7 .word 0x0800c7d7 - 8009dec: 2000339c .word 0x2000339c - -08009df0 : - 8009df0: 4a02 ldr r2, [pc, #8] @ (8009dfc ) - 8009df2: 4903 ldr r1, [pc, #12] @ (8009e00 ) - 8009df4: 4803 ldr r0, [pc, #12] @ (8009e04 ) - 8009df6: f000 b869 b.w 8009ecc <_fwalk_sglue> - 8009dfa: bf00 nop - 8009dfc: 20000014 .word 0x20000014 - 8009e00: 0800bf99 .word 0x0800bf99 - 8009e04: 2000002c .word 0x2000002c - -08009e08 : - 8009e08: 6841 ldr r1, [r0, #4] - 8009e0a: 4b0c ldr r3, [pc, #48] @ (8009e3c ) - 8009e0c: b510 push {r4, lr} - 8009e0e: 4299 cmp r1, r3 - 8009e10: 4604 mov r4, r0 - 8009e12: d001 beq.n 8009e18 - 8009e14: f002 f8c0 bl 800bf98 <_fflush_r> - 8009e18: 68a1 ldr r1, [r4, #8] - 8009e1a: 4b09 ldr r3, [pc, #36] @ (8009e40 ) - 8009e1c: 4299 cmp r1, r3 - 8009e1e: d002 beq.n 8009e26 - 8009e20: 4620 mov r0, r4 - 8009e22: f002 f8b9 bl 800bf98 <_fflush_r> - 8009e26: 68e1 ldr r1, [r4, #12] - 8009e28: 4b06 ldr r3, [pc, #24] @ (8009e44 ) - 8009e2a: 4299 cmp r1, r3 - 8009e2c: d004 beq.n 8009e38 - 8009e2e: 4620 mov r0, r4 - 8009e30: e8bd 4010 ldmia.w sp!, {r4, lr} - 8009e34: f002 b8b0 b.w 800bf98 <_fflush_r> - 8009e38: bd10 pop {r4, pc} - 8009e3a: bf00 nop - 8009e3c: 2000339c .word 0x2000339c - 8009e40: 20003404 .word 0x20003404 - 8009e44: 2000346c .word 0x2000346c - -08009e48 : - 8009e48: b510 push {r4, lr} - 8009e4a: 4b0b ldr r3, [pc, #44] @ (8009e78 ) - 8009e4c: 4c0b ldr r4, [pc, #44] @ (8009e7c ) - 8009e4e: 4a0c ldr r2, [pc, #48] @ (8009e80 ) - 8009e50: 4620 mov r0, r4 - 8009e52: 601a str r2, [r3, #0] - 8009e54: 2104 movs r1, #4 - 8009e56: 2200 movs r2, #0 - 8009e58: f7ff ff94 bl 8009d84 - 8009e5c: f104 0068 add.w r0, r4, #104 @ 0x68 - 8009e60: 2201 movs r2, #1 - 8009e62: 2109 movs r1, #9 - 8009e64: f7ff ff8e bl 8009d84 - 8009e68: f104 00d0 add.w r0, r4, #208 @ 0xd0 - 8009e6c: 2202 movs r2, #2 - 8009e6e: e8bd 4010 ldmia.w sp!, {r4, lr} - 8009e72: 2112 movs r1, #18 - 8009e74: f7ff bf86 b.w 8009d84 - 8009e78: 200034d4 .word 0x200034d4 - 8009e7c: 2000339c .word 0x2000339c - 8009e80: 08009df1 .word 0x08009df1 - -08009e84 <__sfp_lock_acquire>: - 8009e84: 4801 ldr r0, [pc, #4] @ (8009e8c <__sfp_lock_acquire+0x8>) - 8009e86: f000 bde5 b.w 800aa54 <__retarget_lock_acquire_recursive> - 8009e8a: bf00 nop - 8009e8c: 200034ff .word 0x200034ff - -08009e90 <__sfp_lock_release>: - 8009e90: 4801 ldr r0, [pc, #4] @ (8009e98 <__sfp_lock_release+0x8>) - 8009e92: f000 bde1 b.w 800aa58 <__retarget_lock_release_recursive> - 8009e96: bf00 nop - 8009e98: 200034ff .word 0x200034ff - -08009e9c <__sinit>: - 8009e9c: b510 push {r4, lr} - 8009e9e: 4604 mov r4, r0 - 8009ea0: f7ff fff0 bl 8009e84 <__sfp_lock_acquire> - 8009ea4: 6a23 ldr r3, [r4, #32] - 8009ea6: b11b cbz r3, 8009eb0 <__sinit+0x14> - 8009ea8: e8bd 4010 ldmia.w sp!, {r4, lr} - 8009eac: f7ff bff0 b.w 8009e90 <__sfp_lock_release> - 8009eb0: 4b04 ldr r3, [pc, #16] @ (8009ec4 <__sinit+0x28>) - 8009eb2: 6223 str r3, [r4, #32] - 8009eb4: 4b04 ldr r3, [pc, #16] @ (8009ec8 <__sinit+0x2c>) - 8009eb6: 681b ldr r3, [r3, #0] - 8009eb8: 2b00 cmp r3, #0 - 8009eba: d1f5 bne.n 8009ea8 <__sinit+0xc> - 8009ebc: f7ff ffc4 bl 8009e48 - 8009ec0: e7f2 b.n 8009ea8 <__sinit+0xc> - 8009ec2: bf00 nop - 8009ec4: 08009e09 .word 0x08009e09 - 8009ec8: 200034d4 .word 0x200034d4 - -08009ecc <_fwalk_sglue>: - 8009ecc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 8009ed0: 4607 mov r7, r0 - 8009ed2: 4688 mov r8, r1 - 8009ed4: 4614 mov r4, r2 - 8009ed6: 2600 movs r6, #0 - 8009ed8: e9d4 9501 ldrd r9, r5, [r4, #4] - 8009edc: f1b9 0901 subs.w r9, r9, #1 - 8009ee0: d505 bpl.n 8009eee <_fwalk_sglue+0x22> - 8009ee2: 6824 ldr r4, [r4, #0] - 8009ee4: 2c00 cmp r4, #0 - 8009ee6: d1f7 bne.n 8009ed8 <_fwalk_sglue+0xc> - 8009ee8: 4630 mov r0, r6 - 8009eea: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8009eee: 89ab ldrh r3, [r5, #12] - 8009ef0: 2b01 cmp r3, #1 - 8009ef2: d907 bls.n 8009f04 <_fwalk_sglue+0x38> - 8009ef4: f9b5 300e ldrsh.w r3, [r5, #14] - 8009ef8: 3301 adds r3, #1 - 8009efa: d003 beq.n 8009f04 <_fwalk_sglue+0x38> - 8009efc: 4629 mov r1, r5 - 8009efe: 4638 mov r0, r7 - 8009f00: 47c0 blx r8 - 8009f02: 4306 orrs r6, r0 - 8009f04: 3568 adds r5, #104 @ 0x68 - 8009f06: e7e9 b.n 8009edc <_fwalk_sglue+0x10> - -08009f08 <_vsniprintf_r>: - 8009f08: b530 push {r4, r5, lr} - 8009f0a: 4614 mov r4, r2 - 8009f0c: 2c00 cmp r4, #0 - 8009f0e: 4605 mov r5, r0 - 8009f10: 461a mov r2, r3 - 8009f12: b09b sub sp, #108 @ 0x6c - 8009f14: da05 bge.n 8009f22 <_vsniprintf_r+0x1a> - 8009f16: 238b movs r3, #139 @ 0x8b - 8009f18: 6003 str r3, [r0, #0] - 8009f1a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8009f1e: b01b add sp, #108 @ 0x6c - 8009f20: bd30 pop {r4, r5, pc} - 8009f22: f44f 7302 mov.w r3, #520 @ 0x208 - 8009f26: f8ad 300c strh.w r3, [sp, #12] - 8009f2a: bf0c ite eq - 8009f2c: 4623 moveq r3, r4 - 8009f2e: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff - 8009f32: 9302 str r3, [sp, #8] - 8009f34: 9305 str r3, [sp, #20] - 8009f36: f64f 73ff movw r3, #65535 @ 0xffff - 8009f3a: 9100 str r1, [sp, #0] - 8009f3c: 9104 str r1, [sp, #16] - 8009f3e: f8ad 300e strh.w r3, [sp, #14] - 8009f42: 4669 mov r1, sp - 8009f44: 9b1e ldr r3, [sp, #120] @ 0x78 - 8009f46: f001 fcb9 bl 800b8bc <_svfiprintf_r> - 8009f4a: 1c43 adds r3, r0, #1 - 8009f4c: bfbc itt lt - 8009f4e: 238b movlt r3, #139 @ 0x8b - 8009f50: 602b strlt r3, [r5, #0] - 8009f52: 2c00 cmp r4, #0 - 8009f54: d0e3 beq.n 8009f1e <_vsniprintf_r+0x16> - 8009f56: 2200 movs r2, #0 - 8009f58: 9b00 ldr r3, [sp, #0] - 8009f5a: 701a strb r2, [r3, #0] - 8009f5c: e7df b.n 8009f1e <_vsniprintf_r+0x16> - ... - -08009f60 : - 8009f60: b507 push {r0, r1, r2, lr} - 8009f62: 9300 str r3, [sp, #0] - 8009f64: 4613 mov r3, r2 - 8009f66: 460a mov r2, r1 - 8009f68: 4601 mov r1, r0 - 8009f6a: 4803 ldr r0, [pc, #12] @ (8009f78 ) - 8009f6c: 6800 ldr r0, [r0, #0] - 8009f6e: f7ff ffcb bl 8009f08 <_vsniprintf_r> - 8009f72: b003 add sp, #12 - 8009f74: f85d fb04 ldr.w pc, [sp], #4 - 8009f78: 20000028 .word 0x20000028 - -08009f7c : - 8009f7c: b40f push {r0, r1, r2, r3} - 8009f7e: b507 push {r0, r1, r2, lr} - 8009f80: 4906 ldr r1, [pc, #24] @ (8009f9c ) - 8009f82: ab04 add r3, sp, #16 - 8009f84: 6808 ldr r0, [r1, #0] - 8009f86: f853 2b04 ldr.w r2, [r3], #4 - 8009f8a: 6881 ldr r1, [r0, #8] - 8009f8c: 9301 str r3, [sp, #4] - 8009f8e: f001 fdb9 bl 800bb04 <_vfiprintf_r> - 8009f92: b003 add sp, #12 - 8009f94: f85d eb04 ldr.w lr, [sp], #4 - 8009f98: b004 add sp, #16 - 8009f9a: 4770 bx lr - 8009f9c: 20000028 .word 0x20000028 - -08009fa0 <_puts_r>: - 8009fa0: 6a03 ldr r3, [r0, #32] - 8009fa2: b570 push {r4, r5, r6, lr} - 8009fa4: 4605 mov r5, r0 - 8009fa6: 460e mov r6, r1 - 8009fa8: 6884 ldr r4, [r0, #8] - 8009faa: b90b cbnz r3, 8009fb0 <_puts_r+0x10> - 8009fac: f7ff ff76 bl 8009e9c <__sinit> - 8009fb0: 6e63 ldr r3, [r4, #100] @ 0x64 - 8009fb2: 07db lsls r3, r3, #31 - 8009fb4: d405 bmi.n 8009fc2 <_puts_r+0x22> - 8009fb6: 89a3 ldrh r3, [r4, #12] - 8009fb8: 0598 lsls r0, r3, #22 - 8009fba: d402 bmi.n 8009fc2 <_puts_r+0x22> - 8009fbc: 6da0 ldr r0, [r4, #88] @ 0x58 - 8009fbe: f000 fd49 bl 800aa54 <__retarget_lock_acquire_recursive> - 8009fc2: 89a3 ldrh r3, [r4, #12] - 8009fc4: 0719 lsls r1, r3, #28 - 8009fc6: d502 bpl.n 8009fce <_puts_r+0x2e> - 8009fc8: 6923 ldr r3, [r4, #16] - 8009fca: 2b00 cmp r3, #0 - 8009fcc: d135 bne.n 800a03a <_puts_r+0x9a> - 8009fce: 4621 mov r1, r4 - 8009fd0: 4628 mov r0, r5 - 8009fd2: f002 fcfd bl 800c9d0 <__swsetup_r> - 8009fd6: b380 cbz r0, 800a03a <_puts_r+0x9a> - 8009fd8: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff - 8009fdc: 6e63 ldr r3, [r4, #100] @ 0x64 - 8009fde: 07da lsls r2, r3, #31 - 8009fe0: d405 bmi.n 8009fee <_puts_r+0x4e> - 8009fe2: 89a3 ldrh r3, [r4, #12] - 8009fe4: 059b lsls r3, r3, #22 - 8009fe6: d402 bmi.n 8009fee <_puts_r+0x4e> - 8009fe8: 6da0 ldr r0, [r4, #88] @ 0x58 - 8009fea: f000 fd35 bl 800aa58 <__retarget_lock_release_recursive> - 8009fee: 4628 mov r0, r5 - 8009ff0: bd70 pop {r4, r5, r6, pc} - 8009ff2: 2b00 cmp r3, #0 - 8009ff4: da04 bge.n 800a000 <_puts_r+0x60> - 8009ff6: 69a2 ldr r2, [r4, #24] - 8009ff8: 429a cmp r2, r3 - 8009ffa: dc17 bgt.n 800a02c <_puts_r+0x8c> - 8009ffc: 290a cmp r1, #10 - 8009ffe: d015 beq.n 800a02c <_puts_r+0x8c> - 800a000: 6823 ldr r3, [r4, #0] - 800a002: 1c5a adds r2, r3, #1 - 800a004: 6022 str r2, [r4, #0] - 800a006: 7019 strb r1, [r3, #0] - 800a008: 68a3 ldr r3, [r4, #8] - 800a00a: f816 1f01 ldrb.w r1, [r6, #1]! - 800a00e: 3b01 subs r3, #1 - 800a010: 60a3 str r3, [r4, #8] - 800a012: 2900 cmp r1, #0 - 800a014: d1ed bne.n 8009ff2 <_puts_r+0x52> - 800a016: 2b00 cmp r3, #0 - 800a018: da11 bge.n 800a03e <_puts_r+0x9e> - 800a01a: 4622 mov r2, r4 - 800a01c: 210a movs r1, #10 - 800a01e: 4628 mov r0, r5 - 800a020: f002 fc98 bl 800c954 <__swbuf_r> - 800a024: 3001 adds r0, #1 - 800a026: d0d7 beq.n 8009fd8 <_puts_r+0x38> - 800a028: 250a movs r5, #10 - 800a02a: e7d7 b.n 8009fdc <_puts_r+0x3c> - 800a02c: 4622 mov r2, r4 - 800a02e: 4628 mov r0, r5 - 800a030: f002 fc90 bl 800c954 <__swbuf_r> - 800a034: 3001 adds r0, #1 - 800a036: d1e7 bne.n 800a008 <_puts_r+0x68> - 800a038: e7ce b.n 8009fd8 <_puts_r+0x38> - 800a03a: 3e01 subs r6, #1 - 800a03c: e7e4 b.n 800a008 <_puts_r+0x68> - 800a03e: 6823 ldr r3, [r4, #0] - 800a040: 1c5a adds r2, r3, #1 - 800a042: 6022 str r2, [r4, #0] - 800a044: 220a movs r2, #10 - 800a046: 701a strb r2, [r3, #0] - 800a048: e7ee b.n 800a028 <_puts_r+0x88> - ... - -0800a04c : - 800a04c: 4b02 ldr r3, [pc, #8] @ (800a058 ) - 800a04e: 4601 mov r1, r0 - 800a050: 6818 ldr r0, [r3, #0] - 800a052: f7ff bfa5 b.w 8009fa0 <_puts_r> - 800a056: bf00 nop - 800a058: 20000028 .word 0x20000028 - -0800a05c : - 800a05c: b510 push {r4, lr} - 800a05e: b16a cbz r2, 800a07c - 800a060: 3901 subs r1, #1 - 800a062: 1884 adds r4, r0, r2 - 800a064: f810 2b01 ldrb.w r2, [r0], #1 - 800a068: f811 3f01 ldrb.w r3, [r1, #1]! - 800a06c: 429a cmp r2, r3 - 800a06e: d103 bne.n 800a078 - 800a070: 42a0 cmp r0, r4 - 800a072: d001 beq.n 800a078 - 800a074: 2a00 cmp r2, #0 - 800a076: d1f5 bne.n 800a064 - 800a078: 1ad0 subs r0, r2, r3 - 800a07a: bd10 pop {r4, pc} - 800a07c: 4610 mov r0, r2 - 800a07e: e7fc b.n 800a07a - -0800a080 : - 800a080: 4603 mov r3, r0 - 800a082: 4402 add r2, r0 - 800a084: 4293 cmp r3, r2 - 800a086: d100 bne.n 800a08a - 800a088: 4770 bx lr - 800a08a: f803 1b01 strb.w r1, [r3], #1 - 800a08e: e7f9 b.n 800a084 - -0800a090 : - 800a090: b538 push {r3, r4, r5, lr} - 800a092: 4b0b ldr r3, [pc, #44] @ (800a0c0 ) - 800a094: 4604 mov r4, r0 - 800a096: 681d ldr r5, [r3, #0] - 800a098: 6b6b ldr r3, [r5, #52] @ 0x34 - 800a09a: b953 cbnz r3, 800a0b2 - 800a09c: 2024 movs r0, #36 @ 0x24 - 800a09e: f001 fe49 bl 800bd34 - 800a0a2: 4602 mov r2, r0 - 800a0a4: 6368 str r0, [r5, #52] @ 0x34 - 800a0a6: b920 cbnz r0, 800a0b2 - 800a0a8: 213d movs r1, #61 @ 0x3d - 800a0aa: 4b06 ldr r3, [pc, #24] @ (800a0c4 ) - 800a0ac: 4806 ldr r0, [pc, #24] @ (800a0c8 ) - 800a0ae: f000 fcf9 bl 800aaa4 <__assert_func> - 800a0b2: 4620 mov r0, r4 - 800a0b4: 6b69 ldr r1, [r5, #52] @ 0x34 - 800a0b6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 800a0ba: f000 b807 b.w 800a0cc - 800a0be: bf00 nop - 800a0c0: 20000028 .word 0x20000028 - 800a0c4: 0800e036 .word 0x0800e036 - 800a0c8: 0800e04d .word 0x0800e04d - -0800a0cc : - 800a0cc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800a0d0: 2300 movs r3, #0 - 800a0d2: 460c mov r4, r1 - 800a0d4: e9d0 0100 ldrd r0, r1, [r0] - 800a0d8: 4a4b ldr r2, [pc, #300] @ (800a208 ) - 800a0da: f7f7 f895 bl 8001208 <__aeabi_ldivmod> - 800a0de: f44f 6161 mov.w r1, #3600 @ 0xe10 - 800a0e2: 2a00 cmp r2, #0 - 800a0e4: bfbc itt lt - 800a0e6: f502 32a8 addlt.w r2, r2, #86016 @ 0x15000 - 800a0ea: f502 72c0 addlt.w r2, r2, #384 @ 0x180 - 800a0ee: fbb2 f3f1 udiv r3, r2, r1 - 800a0f2: fb01 2213 mls r2, r1, r3, r2 - 800a0f6: f04f 013c mov.w r1, #60 @ 0x3c - 800a0fa: 60a3 str r3, [r4, #8] - 800a0fc: fbb2 f3f1 udiv r3, r2, r1 - 800a100: fb01 2213 mls r2, r1, r3, r2 - 800a104: 6022 str r2, [r4, #0] - 800a106: f04f 0207 mov.w r2, #7 - 800a10a: f500 202f add.w r0, r0, #716800 @ 0xaf000 - 800a10e: bfac ite ge - 800a110: f600 206c addwge r0, r0, #2668 @ 0xa6c - 800a114: f600 206b addwlt r0, r0, #2667 @ 0xa6b - 800a118: 6063 str r3, [r4, #4] - 800a11a: 1cc3 adds r3, r0, #3 - 800a11c: fb93 f2f2 sdiv r2, r3, r2 - 800a120: ebc2 02c2 rsb r2, r2, r2, lsl #3 - 800a124: 1a9b subs r3, r3, r2 - 800a126: bf48 it mi - 800a128: 3307 addmi r3, #7 - 800a12a: 2800 cmp r0, #0 - 800a12c: 4937 ldr r1, [pc, #220] @ (800a20c ) - 800a12e: 61a3 str r3, [r4, #24] - 800a130: bfbd ittte lt - 800a132: f5a0 330e sublt.w r3, r0, #145408 @ 0x23800 - 800a136: f5a3 732c sublt.w r3, r3, #688 @ 0x2b0 - 800a13a: fb93 f1f1 sdivlt r1, r3, r1 - 800a13e: fb90 f1f1 sdivge r1, r0, r1 - 800a142: 4b33 ldr r3, [pc, #204] @ (800a210 ) - 800a144: f240 5cb4 movw ip, #1460 @ 0x5b4 - 800a148: fb03 0001 mla r0, r3, r1, r0 - 800a14c: f648 63ac movw r3, #36524 @ 0x8eac - 800a150: fbb0 f3f3 udiv r3, r0, r3 - 800a154: fbb0 f2fc udiv r2, r0, ip - 800a158: 4403 add r3, r0 - 800a15a: 1a9b subs r3, r3, r2 - 800a15c: 4a2d ldr r2, [pc, #180] @ (800a214 ) - 800a15e: f240 176d movw r7, #365 @ 0x16d - 800a162: fbb0 f2f2 udiv r2, r0, r2 - 800a166: 1a9b subs r3, r3, r2 - 800a168: fbb3 f2f7 udiv r2, r3, r7 - 800a16c: 2664 movs r6, #100 @ 0x64 - 800a16e: fbb3 f3fc udiv r3, r3, ip - 800a172: fbb2 f5f6 udiv r5, r2, r6 - 800a176: 1aeb subs r3, r5, r3 - 800a178: 4403 add r3, r0 - 800a17a: 2099 movs r0, #153 @ 0x99 - 800a17c: fb07 3312 mls r3, r7, r2, r3 - 800a180: eb03 0783 add.w r7, r3, r3, lsl #2 - 800a184: 3702 adds r7, #2 - 800a186: fbb7 fcf0 udiv ip, r7, r0 - 800a18a: f04f 0805 mov.w r8, #5 - 800a18e: fb00 f00c mul.w r0, r0, ip - 800a192: 3002 adds r0, #2 - 800a194: fbb0 f0f8 udiv r0, r0, r8 - 800a198: f103 0e01 add.w lr, r3, #1 - 800a19c: ebae 0000 sub.w r0, lr, r0 - 800a1a0: f240 5ef9 movw lr, #1529 @ 0x5f9 - 800a1a4: 4577 cmp r7, lr - 800a1a6: bf8c ite hi - 800a1a8: f06f 0709 mvnhi.w r7, #9 - 800a1ac: 2702 movls r7, #2 - 800a1ae: 4467 add r7, ip - 800a1b0: f44f 7cc8 mov.w ip, #400 @ 0x190 - 800a1b4: fb0c 2101 mla r1, ip, r1, r2 - 800a1b8: 2f01 cmp r7, #1 - 800a1ba: bf98 it ls - 800a1bc: 3101 addls r1, #1 - 800a1be: f5b3 7f99 cmp.w r3, #306 @ 0x132 - 800a1c2: d30c bcc.n 800a1de - 800a1c4: f5a3 7399 sub.w r3, r3, #306 @ 0x132 - 800a1c8: 61e3 str r3, [r4, #28] - 800a1ca: 2300 movs r3, #0 - 800a1cc: f2a1 716c subw r1, r1, #1900 @ 0x76c - 800a1d0: 60e0 str r0, [r4, #12] - 800a1d2: e9c4 7104 strd r7, r1, [r4, #16] - 800a1d6: 4620 mov r0, r4 - 800a1d8: 6223 str r3, [r4, #32] - 800a1da: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 800a1de: f012 0f03 tst.w r2, #3 - 800a1e2: d102 bne.n 800a1ea - 800a1e4: fb06 2515 mls r5, r6, r5, r2 - 800a1e8: b95d cbnz r5, 800a202 - 800a1ea: f44f 75c8 mov.w r5, #400 @ 0x190 - 800a1ee: fbb2 f6f5 udiv r6, r2, r5 - 800a1f2: fb05 2216 mls r2, r5, r6, r2 - 800a1f6: fab2 f282 clz r2, r2 - 800a1fa: 0952 lsrs r2, r2, #5 - 800a1fc: 333b adds r3, #59 @ 0x3b - 800a1fe: 4413 add r3, r2 - 800a200: e7e2 b.n 800a1c8 - 800a202: 2201 movs r2, #1 - 800a204: e7fa b.n 800a1fc - 800a206: bf00 nop - 800a208: 00015180 .word 0x00015180 - 800a20c: 00023ab1 .word 0x00023ab1 - 800a210: fffdc54f .word 0xfffdc54f - 800a214: 00023ab0 .word 0x00023ab0 - -0800a218 : - 800a218: b538 push {r3, r4, r5, lr} - 800a21a: 4b0b ldr r3, [pc, #44] @ (800a248 ) - 800a21c: 4604 mov r4, r0 - 800a21e: 681d ldr r5, [r3, #0] - 800a220: 6b6b ldr r3, [r5, #52] @ 0x34 - 800a222: b953 cbnz r3, 800a23a - 800a224: 2024 movs r0, #36 @ 0x24 - 800a226: f001 fd85 bl 800bd34 - 800a22a: 4602 mov r2, r0 - 800a22c: 6368 str r0, [r5, #52] @ 0x34 - 800a22e: b920 cbnz r0, 800a23a - 800a230: 2132 movs r1, #50 @ 0x32 - 800a232: 4b06 ldr r3, [pc, #24] @ (800a24c ) - 800a234: 4806 ldr r0, [pc, #24] @ (800a250 ) - 800a236: f000 fc35 bl 800aaa4 <__assert_func> - 800a23a: 4620 mov r0, r4 - 800a23c: 6b69 ldr r1, [r5, #52] @ 0x34 - 800a23e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 800a242: f000 b807 b.w 800a254 - 800a246: bf00 nop - 800a248: 20000028 .word 0x20000028 - 800a24c: 0800e036 .word 0x0800e036 - 800a250: 0800e0a5 .word 0x0800e0a5 - -0800a254 : - 800a254: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800a258: 460c mov r4, r1 - 800a25a: 4680 mov r8, r0 - 800a25c: f000 fbca bl 800a9f4 <__gettzinfo> - 800a260: 4621 mov r1, r4 - 800a262: 4605 mov r5, r0 - 800a264: 4640 mov r0, r8 - 800a266: f7ff ff31 bl 800a0cc - 800a26a: 6943 ldr r3, [r0, #20] - 800a26c: 4604 mov r4, r0 - 800a26e: 0799 lsls r1, r3, #30 - 800a270: f203 776c addw r7, r3, #1900 @ 0x76c - 800a274: d106 bne.n 800a284 - 800a276: 2264 movs r2, #100 @ 0x64 - 800a278: fb97 f3f2 sdiv r3, r7, r2 - 800a27c: fb02 7313 mls r3, r2, r3, r7 - 800a280: 2b00 cmp r3, #0 - 800a282: d170 bne.n 800a366 - 800a284: f44f 72c8 mov.w r2, #400 @ 0x190 - 800a288: fb97 f3f2 sdiv r3, r7, r2 - 800a28c: fb02 7313 mls r3, r2, r3, r7 - 800a290: fab3 f383 clz r3, r3 - 800a294: 095b lsrs r3, r3, #5 - 800a296: 2230 movs r2, #48 @ 0x30 - 800a298: 4e63 ldr r6, [pc, #396] @ (800a428 ) - 800a29a: fb02 6603 mla r6, r2, r3, r6 - 800a29e: f000 f96f bl 800a580 <__tz_lock> - 800a2a2: f000 f979 bl 800a598 <_tzset_unlocked> - 800a2a6: 4b61 ldr r3, [pc, #388] @ (800a42c ) - 800a2a8: 681b ldr r3, [r3, #0] - 800a2aa: 2b00 cmp r3, #0 - 800a2ac: d06a beq.n 800a384 - 800a2ae: 686b ldr r3, [r5, #4] - 800a2b0: 42bb cmp r3, r7 - 800a2b2: d15a bne.n 800a36a - 800a2b4: e9d8 2300 ldrd r2, r3, [r8] - 800a2b8: e9d5 0108 ldrd r0, r1, [r5, #32] - 800a2bc: 682f ldr r7, [r5, #0] - 800a2be: 2f00 cmp r7, #0 - 800a2c0: d15b bne.n 800a37a - 800a2c2: 4282 cmp r2, r0 - 800a2c4: eb73 0101 sbcs.w r1, r3, r1 - 800a2c8: db5e blt.n 800a388 - 800a2ca: 2301 movs r3, #1 - 800a2cc: 6223 str r3, [r4, #32] - 800a2ce: 6d2b ldr r3, [r5, #80] @ 0x50 - 800a2d0: f44f 6261 mov.w r2, #3600 @ 0xe10 - 800a2d4: fb93 f0f2 sdiv r0, r3, r2 - 800a2d8: fb02 3310 mls r3, r2, r0, r3 - 800a2dc: 223c movs r2, #60 @ 0x3c - 800a2de: fb93 f5f2 sdiv r5, r3, r2 - 800a2e2: fb02 3215 mls r2, r2, r5, r3 - 800a2e6: 6823 ldr r3, [r4, #0] - 800a2e8: 6861 ldr r1, [r4, #4] - 800a2ea: 1a9b subs r3, r3, r2 - 800a2ec: 68a2 ldr r2, [r4, #8] - 800a2ee: 1b49 subs r1, r1, r5 - 800a2f0: 1a12 subs r2, r2, r0 - 800a2f2: 2b3b cmp r3, #59 @ 0x3b - 800a2f4: 6023 str r3, [r4, #0] - 800a2f6: 6061 str r1, [r4, #4] - 800a2f8: 60a2 str r2, [r4, #8] - 800a2fa: dd51 ble.n 800a3a0 - 800a2fc: 3101 adds r1, #1 - 800a2fe: 6061 str r1, [r4, #4] - 800a300: 3b3c subs r3, #60 @ 0x3c - 800a302: 6023 str r3, [r4, #0] - 800a304: 6863 ldr r3, [r4, #4] - 800a306: 2b3b cmp r3, #59 @ 0x3b - 800a308: dd50 ble.n 800a3ac - 800a30a: 3201 adds r2, #1 - 800a30c: 60a2 str r2, [r4, #8] - 800a30e: 3b3c subs r3, #60 @ 0x3c - 800a310: 6063 str r3, [r4, #4] - 800a312: 68a3 ldr r3, [r4, #8] - 800a314: 2b17 cmp r3, #23 - 800a316: dd4f ble.n 800a3b8 - 800a318: 69e2 ldr r2, [r4, #28] - 800a31a: 3b18 subs r3, #24 - 800a31c: 3201 adds r2, #1 - 800a31e: 61e2 str r2, [r4, #28] - 800a320: 69a2 ldr r2, [r4, #24] - 800a322: 60a3 str r3, [r4, #8] - 800a324: 3201 adds r2, #1 - 800a326: 2a07 cmp r2, #7 - 800a328: bfa8 it ge - 800a32a: 2200 movge r2, #0 - 800a32c: 61a2 str r2, [r4, #24] - 800a32e: 68e2 ldr r2, [r4, #12] - 800a330: 6923 ldr r3, [r4, #16] - 800a332: 3201 adds r2, #1 - 800a334: 60e2 str r2, [r4, #12] - 800a336: f856 1023 ldr.w r1, [r6, r3, lsl #2] - 800a33a: 428a cmp r2, r1 - 800a33c: dd0e ble.n 800a35c - 800a33e: 2b0b cmp r3, #11 - 800a340: eba2 0201 sub.w r2, r2, r1 - 800a344: 60e2 str r2, [r4, #12] - 800a346: f103 0201 add.w r2, r3, #1 - 800a34a: bf05 ittet eq - 800a34c: 2200 moveq r2, #0 - 800a34e: 6963 ldreq r3, [r4, #20] - 800a350: 6122 strne r2, [r4, #16] - 800a352: 3301 addeq r3, #1 - 800a354: bf02 ittt eq - 800a356: 6122 streq r2, [r4, #16] - 800a358: 6163 streq r3, [r4, #20] - 800a35a: 61e2 streq r2, [r4, #28] - 800a35c: f000 f916 bl 800a58c <__tz_unlock> - 800a360: 4620 mov r0, r4 - 800a362: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 800a366: 2301 movs r3, #1 - 800a368: e795 b.n 800a296 - 800a36a: 4638 mov r0, r7 - 800a36c: f000 f860 bl 800a430 <__tzcalc_limits> - 800a370: 2800 cmp r0, #0 - 800a372: d19f bne.n 800a2b4 - 800a374: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 800a378: e004 b.n 800a384 - 800a37a: 4282 cmp r2, r0 - 800a37c: eb73 0101 sbcs.w r1, r3, r1 - 800a380: da02 bge.n 800a388 - 800a382: 2300 movs r3, #0 - 800a384: 6223 str r3, [r4, #32] - 800a386: e009 b.n 800a39c - 800a388: e9d5 0112 ldrd r0, r1, [r5, #72] @ 0x48 - 800a38c: 4282 cmp r2, r0 - 800a38e: 418b sbcs r3, r1 - 800a390: bfb4 ite lt - 800a392: 2301 movlt r3, #1 - 800a394: 2300 movge r3, #0 - 800a396: 6223 str r3, [r4, #32] - 800a398: 2b00 cmp r3, #0 - 800a39a: d198 bne.n 800a2ce - 800a39c: 6aab ldr r3, [r5, #40] @ 0x28 - 800a39e: e797 b.n 800a2d0 - 800a3a0: 2b00 cmp r3, #0 - 800a3a2: daaf bge.n 800a304 - 800a3a4: 3901 subs r1, #1 - 800a3a6: 6061 str r1, [r4, #4] - 800a3a8: 333c adds r3, #60 @ 0x3c - 800a3aa: e7aa b.n 800a302 - 800a3ac: 2b00 cmp r3, #0 - 800a3ae: dab0 bge.n 800a312 - 800a3b0: 3a01 subs r2, #1 - 800a3b2: 60a2 str r2, [r4, #8] - 800a3b4: 333c adds r3, #60 @ 0x3c - 800a3b6: e7ab b.n 800a310 - 800a3b8: 2b00 cmp r3, #0 - 800a3ba: dacf bge.n 800a35c - 800a3bc: 69e2 ldr r2, [r4, #28] - 800a3be: 3318 adds r3, #24 - 800a3c0: 3a01 subs r2, #1 - 800a3c2: 61e2 str r2, [r4, #28] - 800a3c4: 69a2 ldr r2, [r4, #24] - 800a3c6: 60a3 str r3, [r4, #8] - 800a3c8: 3a01 subs r2, #1 - 800a3ca: bf48 it mi - 800a3cc: 2206 movmi r2, #6 - 800a3ce: 61a2 str r2, [r4, #24] - 800a3d0: 68e2 ldr r2, [r4, #12] - 800a3d2: 3a01 subs r2, #1 - 800a3d4: 60e2 str r2, [r4, #12] - 800a3d6: 2a00 cmp r2, #0 - 800a3d8: d1c0 bne.n 800a35c - 800a3da: 6923 ldr r3, [r4, #16] - 800a3dc: 3b01 subs r3, #1 - 800a3de: d405 bmi.n 800a3ec - 800a3e0: 6123 str r3, [r4, #16] - 800a3e2: 6923 ldr r3, [r4, #16] - 800a3e4: f856 3023 ldr.w r3, [r6, r3, lsl #2] - 800a3e8: 60e3 str r3, [r4, #12] - 800a3ea: e7b7 b.n 800a35c - 800a3ec: 230b movs r3, #11 - 800a3ee: 6123 str r3, [r4, #16] - 800a3f0: 6963 ldr r3, [r4, #20] - 800a3f2: 1e5a subs r2, r3, #1 - 800a3f4: 6162 str r2, [r4, #20] - 800a3f6: 0792 lsls r2, r2, #30 - 800a3f8: f203 736b addw r3, r3, #1899 @ 0x76b - 800a3fc: d105 bne.n 800a40a - 800a3fe: 2164 movs r1, #100 @ 0x64 - 800a400: fb93 f2f1 sdiv r2, r3, r1 - 800a404: fb01 3212 mls r2, r1, r2, r3 - 800a408: b962 cbnz r2, 800a424 - 800a40a: f44f 72c8 mov.w r2, #400 @ 0x190 - 800a40e: fb93 f1f2 sdiv r1, r3, r2 - 800a412: fb02 3311 mls r3, r2, r1, r3 - 800a416: fab3 f383 clz r3, r3 - 800a41a: 095b lsrs r3, r3, #5 - 800a41c: f503 73b6 add.w r3, r3, #364 @ 0x16c - 800a420: 61e3 str r3, [r4, #28] - 800a422: e7de b.n 800a3e2 - 800a424: 2301 movs r3, #1 - 800a426: e7f9 b.n 800a41c - 800a428: 0800e100 .word 0x0800e100 - 800a42c: 200034f8 .word 0x200034f8 - -0800a430 <__tzcalc_limits>: - 800a430: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800a434: 4604 mov r4, r0 - 800a436: f000 fadd bl 800a9f4 <__gettzinfo> - 800a43a: f240 73b1 movw r3, #1969 @ 0x7b1 - 800a43e: 429c cmp r4, r3 - 800a440: f340 8098 ble.w 800a574 <__tzcalc_limits+0x144> - 800a444: f46f 67f6 mvn.w r7, #1968 @ 0x7b0 - 800a448: f240 126d movw r2, #365 @ 0x16d - 800a44c: 19e5 adds r5, r4, r7 - 800a44e: f2a4 73b2 subw r3, r4, #1970 @ 0x7b2 - 800a452: 10ad asrs r5, r5, #2 - 800a454: fb02 5503 mla r5, r2, r3, r5 - 800a458: f06f 0263 mvn.w r2, #99 @ 0x63 - 800a45c: f2a4 736d subw r3, r4, #1901 @ 0x76d - 800a460: fb93 f3f2 sdiv r3, r3, r2 - 800a464: f46f 6cc8 mvn.w ip, #1600 @ 0x640 - 800a468: f44f 72c8 mov.w r2, #400 @ 0x190 - 800a46c: 441d add r5, r3 - 800a46e: eb04 030c add.w r3, r4, ip - 800a472: fbb3 f3f2 udiv r3, r3, r2 - 800a476: 4601 mov r1, r0 - 800a478: 4f3f ldr r7, [pc, #252] @ (800a578 <__tzcalc_limits+0x148>) - 800a47a: 6044 str r4, [r0, #4] - 800a47c: 441d add r5, r3 - 800a47e: f100 0c50 add.w ip, r0, #80 @ 0x50 - 800a482: 7a0b ldrb r3, [r1, #8] - 800a484: 694a ldr r2, [r1, #20] - 800a486: 2b4a cmp r3, #74 @ 0x4a - 800a488: d133 bne.n 800a4f2 <__tzcalc_limits+0xc2> - 800a48a: 07a6 lsls r6, r4, #30 - 800a48c: eb05 0302 add.w r3, r5, r2 - 800a490: d106 bne.n 800a4a0 <__tzcalc_limits+0x70> - 800a492: f04f 0e64 mov.w lr, #100 @ 0x64 - 800a496: fb94 f6fe sdiv r6, r4, lr - 800a49a: fb0e 4616 mls r6, lr, r6, r4 - 800a49e: b936 cbnz r6, 800a4ae <__tzcalc_limits+0x7e> - 800a4a0: f44f 7ec8 mov.w lr, #400 @ 0x190 - 800a4a4: fb94 f6fe sdiv r6, r4, lr - 800a4a8: fb0e 4616 mls r6, lr, r6, r4 - 800a4ac: b9fe cbnz r6, 800a4ee <__tzcalc_limits+0xbe> - 800a4ae: 2a3b cmp r2, #59 @ 0x3b - 800a4b0: bfd4 ite le - 800a4b2: 2200 movle r2, #0 - 800a4b4: 2201 movgt r2, #1 - 800a4b6: 4413 add r3, r2 - 800a4b8: 3b01 subs r3, #1 - 800a4ba: 698a ldr r2, [r1, #24] - 800a4bc: 17d6 asrs r6, r2, #31 - 800a4be: fbc3 2607 smlal r2, r6, r3, r7 - 800a4c2: 6a8b ldr r3, [r1, #40] @ 0x28 - 800a4c4: 18d2 adds r2, r2, r3 - 800a4c6: eb46 73e3 adc.w r3, r6, r3, asr #31 - 800a4ca: e9c1 2308 strd r2, r3, [r1, #32] - 800a4ce: 3128 adds r1, #40 @ 0x28 - 800a4d0: 458c cmp ip, r1 - 800a4d2: d1d6 bne.n 800a482 <__tzcalc_limits+0x52> - 800a4d4: e9d0 4308 ldrd r4, r3, [r0, #32] - 800a4d8: e9d0 1212 ldrd r1, r2, [r0, #72] @ 0x48 - 800a4dc: 428c cmp r4, r1 - 800a4de: 4193 sbcs r3, r2 - 800a4e0: bfb4 ite lt - 800a4e2: 2301 movlt r3, #1 - 800a4e4: 2300 movge r3, #0 - 800a4e6: 6003 str r3, [r0, #0] - 800a4e8: 2001 movs r0, #1 - 800a4ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800a4ee: 2200 movs r2, #0 - 800a4f0: e7e1 b.n 800a4b6 <__tzcalc_limits+0x86> - 800a4f2: 2b44 cmp r3, #68 @ 0x44 - 800a4f4: d101 bne.n 800a4fa <__tzcalc_limits+0xca> - 800a4f6: 18ab adds r3, r5, r2 - 800a4f8: e7df b.n 800a4ba <__tzcalc_limits+0x8a> - 800a4fa: 07a3 lsls r3, r4, #30 - 800a4fc: d105 bne.n 800a50a <__tzcalc_limits+0xda> - 800a4fe: 2664 movs r6, #100 @ 0x64 - 800a500: fb94 f3f6 sdiv r3, r4, r6 - 800a504: fb06 4313 mls r3, r6, r3, r4 - 800a508: bb73 cbnz r3, 800a568 <__tzcalc_limits+0x138> - 800a50a: f44f 73c8 mov.w r3, #400 @ 0x190 - 800a50e: fb94 f6f3 sdiv r6, r4, r3 - 800a512: fb03 4616 mls r6, r3, r6, r4 - 800a516: fab6 f686 clz r6, r6 - 800a51a: 0976 lsrs r6, r6, #5 - 800a51c: f04f 0a30 mov.w sl, #48 @ 0x30 - 800a520: 462b mov r3, r5 - 800a522: f04f 0800 mov.w r8, #0 - 800a526: f8df e054 ldr.w lr, [pc, #84] @ 800a57c <__tzcalc_limits+0x14c> - 800a52a: f8d1 900c ldr.w r9, [r1, #12] - 800a52e: fb0a e606 mla r6, sl, r6, lr - 800a532: f108 0801 add.w r8, r8, #1 - 800a536: 45c1 cmp r9, r8 - 800a538: f856 e028 ldr.w lr, [r6, r8, lsl #2] - 800a53c: dc16 bgt.n 800a56c <__tzcalc_limits+0x13c> - 800a53e: 2607 movs r6, #7 - 800a540: f103 0804 add.w r8, r3, #4 - 800a544: fb98 f6f6 sdiv r6, r8, r6 - 800a548: ebc6 06c6 rsb r6, r6, r6, lsl #3 - 800a54c: eba8 0606 sub.w r6, r8, r6 - 800a550: 1b92 subs r2, r2, r6 - 800a552: 690e ldr r6, [r1, #16] - 800a554: bf48 it mi - 800a556: 3207 addmi r2, #7 - 800a558: 3e01 subs r6, #1 - 800a55a: ebc6 06c6 rsb r6, r6, r6, lsl #3 - 800a55e: 4432 add r2, r6 - 800a560: 4572 cmp r2, lr - 800a562: da05 bge.n 800a570 <__tzcalc_limits+0x140> - 800a564: 4413 add r3, r2 - 800a566: e7a8 b.n 800a4ba <__tzcalc_limits+0x8a> - 800a568: 2601 movs r6, #1 - 800a56a: e7d7 b.n 800a51c <__tzcalc_limits+0xec> - 800a56c: 4473 add r3, lr - 800a56e: e7e0 b.n 800a532 <__tzcalc_limits+0x102> - 800a570: 3a07 subs r2, #7 - 800a572: e7f5 b.n 800a560 <__tzcalc_limits+0x130> - 800a574: 2000 movs r0, #0 - 800a576: e7b8 b.n 800a4ea <__tzcalc_limits+0xba> - 800a578: 00015180 .word 0x00015180 - 800a57c: 0800e0fc .word 0x0800e0fc - -0800a580 <__tz_lock>: - 800a580: 4801 ldr r0, [pc, #4] @ (800a588 <__tz_lock+0x8>) - 800a582: f000 ba66 b.w 800aa52 <__retarget_lock_acquire> - 800a586: bf00 nop - 800a588: 200034fc .word 0x200034fc - -0800a58c <__tz_unlock>: - 800a58c: 4801 ldr r0, [pc, #4] @ (800a594 <__tz_unlock+0x8>) - 800a58e: f000 ba62 b.w 800aa56 <__retarget_lock_release> - 800a592: bf00 nop - 800a594: 200034fc .word 0x200034fc - -0800a598 <_tzset_unlocked>: - 800a598: 4b01 ldr r3, [pc, #4] @ (800a5a0 <_tzset_unlocked+0x8>) - 800a59a: 6818 ldr r0, [r3, #0] - 800a59c: f000 b802 b.w 800a5a4 <_tzset_unlocked_r> - 800a5a0: 20000028 .word 0x20000028 - -0800a5a4 <_tzset_unlocked_r>: - 800a5a4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800a5a8: b08d sub sp, #52 @ 0x34 - 800a5aa: 4607 mov r7, r0 - 800a5ac: f000 fa22 bl 800a9f4 <__gettzinfo> - 800a5b0: 496d ldr r1, [pc, #436] @ (800a768 <_tzset_unlocked_r+0x1c4>) - 800a5b2: 4604 mov r4, r0 - 800a5b4: 4638 mov r0, r7 - 800a5b6: f001 f91f bl 800b7f8 <_getenv_r> - 800a5ba: 4d6c ldr r5, [pc, #432] @ (800a76c <_tzset_unlocked_r+0x1c8>) - 800a5bc: 4606 mov r6, r0 - 800a5be: bb10 cbnz r0, 800a606 <_tzset_unlocked_r+0x62> - 800a5c0: 4b6b ldr r3, [pc, #428] @ (800a770 <_tzset_unlocked_r+0x1cc>) - 800a5c2: 4a6c ldr r2, [pc, #432] @ (800a774 <_tzset_unlocked_r+0x1d0>) - 800a5c4: 6018 str r0, [r3, #0] - 800a5c6: 4b6c ldr r3, [pc, #432] @ (800a778 <_tzset_unlocked_r+0x1d4>) - 800a5c8: 214a movs r1, #74 @ 0x4a - 800a5ca: 6018 str r0, [r3, #0] - 800a5cc: 4b6b ldr r3, [pc, #428] @ (800a77c <_tzset_unlocked_r+0x1d8>) - 800a5ce: e9c4 0003 strd r0, r0, [r4, #12] - 800a5d2: e9c3 2200 strd r2, r2, [r3] - 800a5d6: 2200 movs r2, #0 - 800a5d8: 2300 movs r3, #0 - 800a5da: e9c4 0005 strd r0, r0, [r4, #20] - 800a5de: e9c4 000d strd r0, r0, [r4, #52] @ 0x34 - 800a5e2: e9c4 000f strd r0, r0, [r4, #60] @ 0x3c - 800a5e6: 62a0 str r0, [r4, #40] @ 0x28 - 800a5e8: 6520 str r0, [r4, #80] @ 0x50 - 800a5ea: e9c4 2308 strd r2, r3, [r4, #32] - 800a5ee: e9c4 2312 strd r2, r3, [r4, #72] @ 0x48 - 800a5f2: 6828 ldr r0, [r5, #0] - 800a5f4: 7221 strb r1, [r4, #8] - 800a5f6: f884 1030 strb.w r1, [r4, #48] @ 0x30 - 800a5fa: f001 fba3 bl 800bd44 - 800a5fe: 602e str r6, [r5, #0] - 800a600: b00d add sp, #52 @ 0x34 - 800a602: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800a606: 6829 ldr r1, [r5, #0] - 800a608: 2900 cmp r1, #0 - 800a60a: f040 808e bne.w 800a72a <_tzset_unlocked_r+0x186> - 800a60e: 6828 ldr r0, [r5, #0] - 800a610: f001 fb98 bl 800bd44 - 800a614: 4630 mov r0, r6 - 800a616: f7f5 fe07 bl 8000228 - 800a61a: 1c41 adds r1, r0, #1 - 800a61c: 4638 mov r0, r7 - 800a61e: f001 fbbb bl 800bd98 <_malloc_r> - 800a622: 6028 str r0, [r5, #0] - 800a624: 2800 cmp r0, #0 - 800a626: f040 8086 bne.w 800a736 <_tzset_unlocked_r+0x192> - 800a62a: 2300 movs r3, #0 - 800a62c: 4a52 ldr r2, [pc, #328] @ (800a778 <_tzset_unlocked_r+0x1d4>) - 800a62e: 2000 movs r0, #0 - 800a630: 6013 str r3, [r2, #0] - 800a632: 2100 movs r1, #0 - 800a634: 4a52 ldr r2, [pc, #328] @ (800a780 <_tzset_unlocked_r+0x1dc>) - 800a636: f8df 8144 ldr.w r8, [pc, #324] @ 800a77c <_tzset_unlocked_r+0x1d8> - 800a63a: e9c4 3303 strd r3, r3, [r4, #12] - 800a63e: e9c8 2200 strd r2, r2, [r8] - 800a642: 224a movs r2, #74 @ 0x4a - 800a644: e9c4 3305 strd r3, r3, [r4, #20] - 800a648: e9c4 0108 strd r0, r1, [r4, #32] - 800a64c: e9c4 330d strd r3, r3, [r4, #52] @ 0x34 - 800a650: e9c4 330f strd r3, r3, [r4, #60] @ 0x3c - 800a654: e9c4 0112 strd r0, r1, [r4, #72] @ 0x48 - 800a658: f8df a114 ldr.w sl, [pc, #276] @ 800a770 <_tzset_unlocked_r+0x1cc> - 800a65c: 7222 strb r2, [r4, #8] - 800a65e: f8ca 3000 str.w r3, [sl] - 800a662: 62a3 str r3, [r4, #40] @ 0x28 - 800a664: f884 2030 strb.w r2, [r4, #48] @ 0x30 - 800a668: 6523 str r3, [r4, #80] @ 0x50 - 800a66a: 7833 ldrb r3, [r6, #0] - 800a66c: 2b3a cmp r3, #58 @ 0x3a - 800a66e: bf08 it eq - 800a670: 3601 addeq r6, #1 - 800a672: 7833 ldrb r3, [r6, #0] - 800a674: 2b3c cmp r3, #60 @ 0x3c - 800a676: d162 bne.n 800a73e <_tzset_unlocked_r+0x19a> - 800a678: 1c75 adds r5, r6, #1 - 800a67a: 4628 mov r0, r5 - 800a67c: 4a41 ldr r2, [pc, #260] @ (800a784 <_tzset_unlocked_r+0x1e0>) - 800a67e: 4942 ldr r1, [pc, #264] @ (800a788 <_tzset_unlocked_r+0x1e4>) - 800a680: ab0a add r3, sp, #40 @ 0x28 - 800a682: f002 f83d bl 800c700 - 800a686: 2800 cmp r0, #0 - 800a688: ddba ble.n 800a600 <_tzset_unlocked_r+0x5c> - 800a68a: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a68c: 1eda subs r2, r3, #3 - 800a68e: 2a07 cmp r2, #7 - 800a690: d8b6 bhi.n 800a600 <_tzset_unlocked_r+0x5c> - 800a692: 5ceb ldrb r3, [r5, r3] - 800a694: 2b3e cmp r3, #62 @ 0x3e - 800a696: d1b3 bne.n 800a600 <_tzset_unlocked_r+0x5c> - 800a698: 3602 adds r6, #2 - 800a69a: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a69c: 18f5 adds r5, r6, r3 - 800a69e: 5cf3 ldrb r3, [r6, r3] - 800a6a0: 2b2d cmp r3, #45 @ 0x2d - 800a6a2: d15a bne.n 800a75a <_tzset_unlocked_r+0x1b6> - 800a6a4: f04f 39ff mov.w r9, #4294967295 @ 0xffffffff - 800a6a8: 3501 adds r5, #1 - 800a6aa: 2300 movs r3, #0 - 800a6ac: af08 add r7, sp, #32 - 800a6ae: f8ad 301e strh.w r3, [sp, #30] - 800a6b2: f8ad 3020 strh.w r3, [sp, #32] - 800a6b6: ab0a add r3, sp, #40 @ 0x28 - 800a6b8: e9cd 3701 strd r3, r7, [sp, #4] - 800a6bc: 9303 str r3, [sp, #12] - 800a6be: f10d 031e add.w r3, sp, #30 - 800a6c2: 9300 str r3, [sp, #0] - 800a6c4: 4628 mov r0, r5 - 800a6c6: 4931 ldr r1, [pc, #196] @ (800a78c <_tzset_unlocked_r+0x1e8>) - 800a6c8: ab0a add r3, sp, #40 @ 0x28 - 800a6ca: aa07 add r2, sp, #28 - 800a6cc: f002 f818 bl 800c700 - 800a6d0: 2800 cmp r0, #0 - 800a6d2: dd95 ble.n 800a600 <_tzset_unlocked_r+0x5c> - 800a6d4: 223c movs r2, #60 @ 0x3c - 800a6d6: f8bd 301e ldrh.w r3, [sp, #30] - 800a6da: f8bd 6020 ldrh.w r6, [sp, #32] - 800a6de: fb02 6603 mla r6, r2, r3, r6 - 800a6e2: f44f 6261 mov.w r2, #3600 @ 0xe10 - 800a6e6: f8bd 301c ldrh.w r3, [sp, #28] - 800a6ea: fb02 6603 mla r6, r2, r3, r6 - 800a6ee: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a6f0: fb09 f606 mul.w r6, r9, r6 - 800a6f4: eb05 0903 add.w r9, r5, r3 - 800a6f8: 5ceb ldrb r3, [r5, r3] - 800a6fa: 2b3c cmp r3, #60 @ 0x3c - 800a6fc: f040 80e8 bne.w 800a8d0 <_tzset_unlocked_r+0x32c> - 800a700: f109 0501 add.w r5, r9, #1 - 800a704: 4628 mov r0, r5 - 800a706: 4a22 ldr r2, [pc, #136] @ (800a790 <_tzset_unlocked_r+0x1ec>) - 800a708: 491f ldr r1, [pc, #124] @ (800a788 <_tzset_unlocked_r+0x1e4>) - 800a70a: ab0a add r3, sp, #40 @ 0x28 - 800a70c: f001 fff8 bl 800c700 - 800a710: 2800 cmp r0, #0 - 800a712: dc41 bgt.n 800a798 <_tzset_unlocked_r+0x1f4> - 800a714: f899 3001 ldrb.w r3, [r9, #1] - 800a718: 2b3e cmp r3, #62 @ 0x3e - 800a71a: d13d bne.n 800a798 <_tzset_unlocked_r+0x1f4> - 800a71c: 4b19 ldr r3, [pc, #100] @ (800a784 <_tzset_unlocked_r+0x1e0>) - 800a71e: 62a6 str r6, [r4, #40] @ 0x28 - 800a720: e9c8 3300 strd r3, r3, [r8] - 800a724: f8ca 6000 str.w r6, [sl] - 800a728: e76a b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a72a: f7f5 fd85 bl 8000238 - 800a72e: 2800 cmp r0, #0 - 800a730: f47f af6d bne.w 800a60e <_tzset_unlocked_r+0x6a> - 800a734: e764 b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a736: 4631 mov r1, r6 - 800a738: f000 f9ab bl 800aa92 - 800a73c: e775 b.n 800a62a <_tzset_unlocked_r+0x86> - 800a73e: 4630 mov r0, r6 - 800a740: 4a10 ldr r2, [pc, #64] @ (800a784 <_tzset_unlocked_r+0x1e0>) - 800a742: 4914 ldr r1, [pc, #80] @ (800a794 <_tzset_unlocked_r+0x1f0>) - 800a744: ab0a add r3, sp, #40 @ 0x28 - 800a746: f001 ffdb bl 800c700 - 800a74a: 2800 cmp r0, #0 - 800a74c: f77f af58 ble.w 800a600 <_tzset_unlocked_r+0x5c> - 800a750: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a752: 3b03 subs r3, #3 - 800a754: 2b07 cmp r3, #7 - 800a756: d9a0 bls.n 800a69a <_tzset_unlocked_r+0xf6> - 800a758: e752 b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a75a: 2b2b cmp r3, #43 @ 0x2b - 800a75c: f04f 0901 mov.w r9, #1 - 800a760: bf08 it eq - 800a762: 3501 addeq r5, #1 - 800a764: e7a1 b.n 800a6aa <_tzset_unlocked_r+0x106> - 800a766: bf00 nop - 800a768: 0800e160 .word 0x0800e160 - 800a76c: 200034d8 .word 0x200034d8 - 800a770: 200034f4 .word 0x200034f4 - 800a774: 0800e163 .word 0x0800e163 - 800a778: 200034f8 .word 0x200034f8 - 800a77c: 20000020 .word 0x20000020 - 800a780: 0800e1e9 .word 0x0800e1e9 - 800a784: 200034e8 .word 0x200034e8 - 800a788: 0800e167 .word 0x0800e167 - 800a78c: 0800e19c .word 0x0800e19c - 800a790: 200034dc .word 0x200034dc - 800a794: 0800e17a .word 0x0800e17a - 800a798: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a79a: 1eda subs r2, r3, #3 - 800a79c: 2a07 cmp r2, #7 - 800a79e: f63f af2f bhi.w 800a600 <_tzset_unlocked_r+0x5c> - 800a7a2: 5ceb ldrb r3, [r5, r3] - 800a7a4: 2b3e cmp r3, #62 @ 0x3e - 800a7a6: f47f af2b bne.w 800a600 <_tzset_unlocked_r+0x5c> - 800a7aa: f109 0902 add.w r9, r9, #2 - 800a7ae: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a7b0: eb09 0503 add.w r5, r9, r3 - 800a7b4: f819 3003 ldrb.w r3, [r9, r3] - 800a7b8: 2b2d cmp r3, #45 @ 0x2d - 800a7ba: f040 8098 bne.w 800a8ee <_tzset_unlocked_r+0x34a> - 800a7be: f04f 39ff mov.w r9, #4294967295 @ 0xffffffff - 800a7c2: 3501 adds r5, #1 - 800a7c4: 2300 movs r3, #0 - 800a7c6: f8ad 301c strh.w r3, [sp, #28] - 800a7ca: f8ad 301e strh.w r3, [sp, #30] - 800a7ce: f8ad 3020 strh.w r3, [sp, #32] - 800a7d2: 930a str r3, [sp, #40] @ 0x28 - 800a7d4: ab0a add r3, sp, #40 @ 0x28 - 800a7d6: e9cd 7302 strd r7, r3, [sp, #8] - 800a7da: 9301 str r3, [sp, #4] - 800a7dc: f10d 031e add.w r3, sp, #30 - 800a7e0: 9300 str r3, [sp, #0] - 800a7e2: 4628 mov r0, r5 - 800a7e4: 497a ldr r1, [pc, #488] @ (800a9d0 <_tzset_unlocked_r+0x42c>) - 800a7e6: ab0a add r3, sp, #40 @ 0x28 - 800a7e8: aa07 add r2, sp, #28 - 800a7ea: f001 ff89 bl 800c700 - 800a7ee: 2800 cmp r0, #0 - 800a7f0: f300 8083 bgt.w 800a8fa <_tzset_unlocked_r+0x356> - 800a7f4: f5a6 6361 sub.w r3, r6, #3600 @ 0xe10 - 800a7f8: 4627 mov r7, r4 - 800a7fa: f04f 0b00 mov.w fp, #0 - 800a7fe: 9304 str r3, [sp, #16] - 800a800: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a802: 441d add r5, r3 - 800a804: 782b ldrb r3, [r5, #0] - 800a806: 2b2c cmp r3, #44 @ 0x2c - 800a808: bf08 it eq - 800a80a: 3501 addeq r5, #1 - 800a80c: f895 9000 ldrb.w r9, [r5] - 800a810: f1b9 0f4d cmp.w r9, #77 @ 0x4d - 800a814: f040 8084 bne.w 800a920 <_tzset_unlocked_r+0x37c> - 800a818: ab0a add r3, sp, #40 @ 0x28 - 800a81a: f10d 0226 add.w r2, sp, #38 @ 0x26 - 800a81e: e9cd 3201 strd r3, r2, [sp, #4] - 800a822: aa09 add r2, sp, #36 @ 0x24 - 800a824: 9200 str r2, [sp, #0] - 800a826: 4628 mov r0, r5 - 800a828: 496a ldr r1, [pc, #424] @ (800a9d4 <_tzset_unlocked_r+0x430>) - 800a82a: 9303 str r3, [sp, #12] - 800a82c: f10d 0222 add.w r2, sp, #34 @ 0x22 - 800a830: f001 ff66 bl 800c700 - 800a834: 2803 cmp r0, #3 - 800a836: f47f aee3 bne.w 800a600 <_tzset_unlocked_r+0x5c> - 800a83a: f8bd 1022 ldrh.w r1, [sp, #34] @ 0x22 - 800a83e: 1e4b subs r3, r1, #1 - 800a840: 2b0b cmp r3, #11 - 800a842: f63f aedd bhi.w 800a600 <_tzset_unlocked_r+0x5c> - 800a846: f8bd 2024 ldrh.w r2, [sp, #36] @ 0x24 - 800a84a: 1e53 subs r3, r2, #1 - 800a84c: 2b04 cmp r3, #4 - 800a84e: f63f aed7 bhi.w 800a600 <_tzset_unlocked_r+0x5c> - 800a852: f8bd 3026 ldrh.w r3, [sp, #38] @ 0x26 - 800a856: 2b06 cmp r3, #6 - 800a858: f63f aed2 bhi.w 800a600 <_tzset_unlocked_r+0x5c> - 800a85c: e9c7 1203 strd r1, r2, [r7, #12] - 800a860: f887 9008 strb.w r9, [r7, #8] - 800a864: 617b str r3, [r7, #20] - 800a866: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a868: eb05 0903 add.w r9, r5, r3 - 800a86c: 2500 movs r5, #0 - 800a86e: f04f 0302 mov.w r3, #2 - 800a872: f8ad 501e strh.w r5, [sp, #30] - 800a876: f8ad 301c strh.w r3, [sp, #28] - 800a87a: f8ad 5020 strh.w r5, [sp, #32] - 800a87e: 950a str r5, [sp, #40] @ 0x28 - 800a880: f899 3000 ldrb.w r3, [r9] - 800a884: 2b2f cmp r3, #47 @ 0x2f - 800a886: d177 bne.n 800a978 <_tzset_unlocked_r+0x3d4> - 800a888: ab0a add r3, sp, #40 @ 0x28 - 800a88a: aa08 add r2, sp, #32 - 800a88c: e9cd 3201 strd r3, r2, [sp, #4] - 800a890: f10d 021e add.w r2, sp, #30 - 800a894: 9200 str r2, [sp, #0] - 800a896: 4648 mov r0, r9 - 800a898: 494f ldr r1, [pc, #316] @ (800a9d8 <_tzset_unlocked_r+0x434>) - 800a89a: 9303 str r3, [sp, #12] - 800a89c: aa07 add r2, sp, #28 - 800a89e: f001 ff2f bl 800c700 - 800a8a2: 42a8 cmp r0, r5 - 800a8a4: dc68 bgt.n 800a978 <_tzset_unlocked_r+0x3d4> - 800a8a6: 214a movs r1, #74 @ 0x4a - 800a8a8: 2200 movs r2, #0 - 800a8aa: 2300 movs r3, #0 - 800a8ac: e9c4 5503 strd r5, r5, [r4, #12] - 800a8b0: e9c4 5505 strd r5, r5, [r4, #20] - 800a8b4: e9c4 2308 strd r2, r3, [r4, #32] - 800a8b8: e9c4 550d strd r5, r5, [r4, #52] @ 0x34 - 800a8bc: e9c4 550f strd r5, r5, [r4, #60] @ 0x3c - 800a8c0: e9c4 2312 strd r2, r3, [r4, #72] @ 0x48 - 800a8c4: 7221 strb r1, [r4, #8] - 800a8c6: 62a5 str r5, [r4, #40] @ 0x28 - 800a8c8: f884 1030 strb.w r1, [r4, #48] @ 0x30 - 800a8cc: 6525 str r5, [r4, #80] @ 0x50 - 800a8ce: e697 b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a8d0: 4648 mov r0, r9 - 800a8d2: 4a42 ldr r2, [pc, #264] @ (800a9dc <_tzset_unlocked_r+0x438>) - 800a8d4: 4942 ldr r1, [pc, #264] @ (800a9e0 <_tzset_unlocked_r+0x43c>) - 800a8d6: ab0a add r3, sp, #40 @ 0x28 - 800a8d8: f001 ff12 bl 800c700 - 800a8dc: 2800 cmp r0, #0 - 800a8de: f77f af1d ble.w 800a71c <_tzset_unlocked_r+0x178> - 800a8e2: 9b0a ldr r3, [sp, #40] @ 0x28 - 800a8e4: 3b03 subs r3, #3 - 800a8e6: 2b07 cmp r3, #7 - 800a8e8: f67f af61 bls.w 800a7ae <_tzset_unlocked_r+0x20a> - 800a8ec: e688 b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a8ee: 2b2b cmp r3, #43 @ 0x2b - 800a8f0: f04f 0901 mov.w r9, #1 - 800a8f4: bf08 it eq - 800a8f6: 3501 addeq r5, #1 - 800a8f8: e764 b.n 800a7c4 <_tzset_unlocked_r+0x220> - 800a8fa: 213c movs r1, #60 @ 0x3c - 800a8fc: f8bd 201e ldrh.w r2, [sp, #30] - 800a900: f8bd 3020 ldrh.w r3, [sp, #32] - 800a904: fb01 3302 mla r3, r1, r2, r3 - 800a908: f44f 6161 mov.w r1, #3600 @ 0xe10 - 800a90c: f8bd 201c ldrh.w r2, [sp, #28] - 800a910: fb01 3302 mla r3, r1, r2, r3 - 800a914: fb09 f303 mul.w r3, r9, r3 - 800a918: e76e b.n 800a7f8 <_tzset_unlocked_r+0x254> - 800a91a: f04f 0b01 mov.w fp, #1 - 800a91e: e771 b.n 800a804 <_tzset_unlocked_r+0x260> - 800a920: f1b9 0f4a cmp.w r9, #74 @ 0x4a - 800a924: bf0a itet eq - 800a926: 464b moveq r3, r9 - 800a928: 2344 movne r3, #68 @ 0x44 - 800a92a: 3501 addeq r5, #1 - 800a92c: 220a movs r2, #10 - 800a92e: 4628 mov r0, r5 - 800a930: a90b add r1, sp, #44 @ 0x2c - 800a932: 9305 str r3, [sp, #20] - 800a934: f002 f804 bl 800c940 - 800a938: f8dd 902c ldr.w r9, [sp, #44] @ 0x2c - 800a93c: 9b05 ldr r3, [sp, #20] - 800a93e: 45a9 cmp r9, r5 - 800a940: f8ad 0026 strh.w r0, [sp, #38] @ 0x26 - 800a944: d114 bne.n 800a970 <_tzset_unlocked_r+0x3cc> - 800a946: 234d movs r3, #77 @ 0x4d - 800a948: f1bb 0f00 cmp.w fp, #0 - 800a94c: d107 bne.n 800a95e <_tzset_unlocked_r+0x3ba> - 800a94e: 2103 movs r1, #3 - 800a950: 7223 strb r3, [r4, #8] - 800a952: 2302 movs r3, #2 - 800a954: f8c4 b014 str.w fp, [r4, #20] - 800a958: e9c4 1303 strd r1, r3, [r4, #12] - 800a95c: e786 b.n 800a86c <_tzset_unlocked_r+0x2c8> - 800a95e: 220b movs r2, #11 - 800a960: f884 3030 strb.w r3, [r4, #48] @ 0x30 - 800a964: 2301 movs r3, #1 - 800a966: e9c4 230d strd r2, r3, [r4, #52] @ 0x34 - 800a96a: 2300 movs r3, #0 - 800a96c: 63e3 str r3, [r4, #60] @ 0x3c - 800a96e: e77d b.n 800a86c <_tzset_unlocked_r+0x2c8> - 800a970: b280 uxth r0, r0 - 800a972: 723b strb r3, [r7, #8] - 800a974: 6178 str r0, [r7, #20] - 800a976: e779 b.n 800a86c <_tzset_unlocked_r+0x2c8> - 800a978: 213c movs r1, #60 @ 0x3c - 800a97a: f8bd 201e ldrh.w r2, [sp, #30] - 800a97e: f8bd 3020 ldrh.w r3, [sp, #32] - 800a982: 3728 adds r7, #40 @ 0x28 - 800a984: fb01 3302 mla r3, r1, r2, r3 - 800a988: f44f 6161 mov.w r1, #3600 @ 0xe10 - 800a98c: f8bd 201c ldrh.w r2, [sp, #28] - 800a990: fb01 3302 mla r3, r1, r2, r3 - 800a994: f847 3c10 str.w r3, [r7, #-16] - 800a998: 9d0a ldr r5, [sp, #40] @ 0x28 - 800a99a: 444d add r5, r9 - 800a99c: f1bb 0f00 cmp.w fp, #0 - 800a9a0: d0bb beq.n 800a91a <_tzset_unlocked_r+0x376> - 800a9a2: 9b04 ldr r3, [sp, #16] - 800a9a4: 6860 ldr r0, [r4, #4] - 800a9a6: 6523 str r3, [r4, #80] @ 0x50 - 800a9a8: 4b0e ldr r3, [pc, #56] @ (800a9e4 <_tzset_unlocked_r+0x440>) - 800a9aa: 62a6 str r6, [r4, #40] @ 0x28 - 800a9ac: f8c8 3000 str.w r3, [r8] - 800a9b0: 4b0a ldr r3, [pc, #40] @ (800a9dc <_tzset_unlocked_r+0x438>) - 800a9b2: f8c8 3004 str.w r3, [r8, #4] - 800a9b6: f7ff fd3b bl 800a430 <__tzcalc_limits> - 800a9ba: 6aa2 ldr r2, [r4, #40] @ 0x28 - 800a9bc: 6d23 ldr r3, [r4, #80] @ 0x50 - 800a9be: f8ca 2000 str.w r2, [sl] - 800a9c2: 1a9b subs r3, r3, r2 - 800a9c4: bf18 it ne - 800a9c6: 2301 movne r3, #1 - 800a9c8: 4a07 ldr r2, [pc, #28] @ (800a9e8 <_tzset_unlocked_r+0x444>) - 800a9ca: 6013 str r3, [r2, #0] - 800a9cc: e618 b.n 800a600 <_tzset_unlocked_r+0x5c> - 800a9ce: bf00 nop - 800a9d0: 0800e19c .word 0x0800e19c - 800a9d4: 0800e188 .word 0x0800e188 - 800a9d8: 0800e19b .word 0x0800e19b - 800a9dc: 200034dc .word 0x200034dc - 800a9e0: 0800e17a .word 0x0800e17a - 800a9e4: 200034e8 .word 0x200034e8 - 800a9e8: 200034f8 .word 0x200034f8 - -0800a9ec <_localeconv_r>: - 800a9ec: 4800 ldr r0, [pc, #0] @ (800a9f0 <_localeconv_r+0x4>) - 800a9ee: 4770 bx lr - 800a9f0: 200001c0 .word 0x200001c0 - -0800a9f4 <__gettzinfo>: - 800a9f4: 4800 ldr r0, [pc, #0] @ (800a9f8 <__gettzinfo+0x4>) - 800a9f6: 4770 bx lr - 800a9f8: 20000078 .word 0x20000078 - -0800a9fc <__errno>: - 800a9fc: 4b01 ldr r3, [pc, #4] @ (800aa04 <__errno+0x8>) - 800a9fe: 6818 ldr r0, [r3, #0] - 800aa00: 4770 bx lr - 800aa02: bf00 nop - 800aa04: 20000028 .word 0x20000028 - -0800aa08 <__libc_init_array>: - 800aa08: b570 push {r4, r5, r6, lr} - 800aa0a: 2600 movs r6, #0 - 800aa0c: 4d0c ldr r5, [pc, #48] @ (800aa40 <__libc_init_array+0x38>) - 800aa0e: 4c0d ldr r4, [pc, #52] @ (800aa44 <__libc_init_array+0x3c>) - 800aa10: 1b64 subs r4, r4, r5 - 800aa12: 10a4 asrs r4, r4, #2 - 800aa14: 42a6 cmp r6, r4 - 800aa16: d109 bne.n 800aa2c <__libc_init_array+0x24> - 800aa18: f002 fe04 bl 800d624 <_init> - 800aa1c: 2600 movs r6, #0 - 800aa1e: 4d0a ldr r5, [pc, #40] @ (800aa48 <__libc_init_array+0x40>) - 800aa20: 4c0a ldr r4, [pc, #40] @ (800aa4c <__libc_init_array+0x44>) - 800aa22: 1b64 subs r4, r4, r5 - 800aa24: 10a4 asrs r4, r4, #2 - 800aa26: 42a6 cmp r6, r4 - 800aa28: d105 bne.n 800aa36 <__libc_init_array+0x2e> - 800aa2a: bd70 pop {r4, r5, r6, pc} - 800aa2c: f855 3b04 ldr.w r3, [r5], #4 - 800aa30: 4798 blx r3 - 800aa32: 3601 adds r6, #1 - 800aa34: e7ee b.n 800aa14 <__libc_init_array+0xc> - 800aa36: f855 3b04 ldr.w r3, [r5], #4 - 800aa3a: 4798 blx r3 - 800aa3c: 3601 adds r6, #1 - 800aa3e: e7f2 b.n 800aa26 <__libc_init_array+0x1e> - 800aa40: 0800e4f8 .word 0x0800e4f8 - 800aa44: 0800e4f8 .word 0x0800e4f8 - 800aa48: 0800e4f8 .word 0x0800e4f8 - 800aa4c: 0800e4fc .word 0x0800e4fc - -0800aa50 <__retarget_lock_init_recursive>: - 800aa50: 4770 bx lr - -0800aa52 <__retarget_lock_acquire>: - 800aa52: 4770 bx lr - -0800aa54 <__retarget_lock_acquire_recursive>: - 800aa54: 4770 bx lr - -0800aa56 <__retarget_lock_release>: - 800aa56: 4770 bx lr - -0800aa58 <__retarget_lock_release_recursive>: - 800aa58: 4770 bx lr - -0800aa5a : - 800aa5a: 4603 mov r3, r0 - 800aa5c: b510 push {r4, lr} - 800aa5e: b2c9 uxtb r1, r1 - 800aa60: 4402 add r2, r0 - 800aa62: 4293 cmp r3, r2 - 800aa64: 4618 mov r0, r3 - 800aa66: d101 bne.n 800aa6c - 800aa68: 2000 movs r0, #0 - 800aa6a: e003 b.n 800aa74 - 800aa6c: 7804 ldrb r4, [r0, #0] - 800aa6e: 3301 adds r3, #1 - 800aa70: 428c cmp r4, r1 - 800aa72: d1f6 bne.n 800aa62 - 800aa74: bd10 pop {r4, pc} - -0800aa76 : - 800aa76: 440a add r2, r1 - 800aa78: 4291 cmp r1, r2 - 800aa7a: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff - 800aa7e: d100 bne.n 800aa82 - 800aa80: 4770 bx lr - 800aa82: b510 push {r4, lr} - 800aa84: f811 4b01 ldrb.w r4, [r1], #1 - 800aa88: 4291 cmp r1, r2 - 800aa8a: f803 4f01 strb.w r4, [r3, #1]! - 800aa8e: d1f9 bne.n 800aa84 - 800aa90: bd10 pop {r4, pc} - -0800aa92 : - 800aa92: 4603 mov r3, r0 - 800aa94: f811 2b01 ldrb.w r2, [r1], #1 - 800aa98: f803 2b01 strb.w r2, [r3], #1 - 800aa9c: 2a00 cmp r2, #0 - 800aa9e: d1f9 bne.n 800aa94 - 800aaa0: 4770 bx lr - ... - -0800aaa4 <__assert_func>: - 800aaa4: b51f push {r0, r1, r2, r3, r4, lr} - 800aaa6: 4614 mov r4, r2 - 800aaa8: 461a mov r2, r3 - 800aaaa: 4b09 ldr r3, [pc, #36] @ (800aad0 <__assert_func+0x2c>) - 800aaac: 4605 mov r5, r0 - 800aaae: 681b ldr r3, [r3, #0] - 800aab0: 68d8 ldr r0, [r3, #12] - 800aab2: b954 cbnz r4, 800aaca <__assert_func+0x26> - 800aab4: 4b07 ldr r3, [pc, #28] @ (800aad4 <__assert_func+0x30>) - 800aab6: 461c mov r4, r3 - 800aab8: e9cd 3401 strd r3, r4, [sp, #4] - 800aabc: 9100 str r1, [sp, #0] - 800aabe: 462b mov r3, r5 - 800aac0: 4905 ldr r1, [pc, #20] @ (800aad8 <__assert_func+0x34>) - 800aac2: f001 fe8d bl 800c7e0 - 800aac6: f002 f8cd bl 800cc64 - 800aaca: 4b04 ldr r3, [pc, #16] @ (800aadc <__assert_func+0x38>) - 800aacc: e7f4 b.n 800aab8 <__assert_func+0x14> - 800aace: bf00 nop - 800aad0: 20000028 .word 0x20000028 - 800aad4: 0800e1e9 .word 0x0800e1e9 - 800aad8: 0800e1bb .word 0x0800e1bb - 800aadc: 0800e1ae .word 0x0800e1ae - -0800aae0 : - 800aae0: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800aae4: 6903 ldr r3, [r0, #16] - 800aae6: 690c ldr r4, [r1, #16] - 800aae8: 4607 mov r7, r0 - 800aaea: 42a3 cmp r3, r4 - 800aaec: db7e blt.n 800abec - 800aaee: 3c01 subs r4, #1 - 800aaf0: 00a3 lsls r3, r4, #2 - 800aaf2: f100 0514 add.w r5, r0, #20 - 800aaf6: f101 0814 add.w r8, r1, #20 - 800aafa: 9300 str r3, [sp, #0] - 800aafc: eb05 0384 add.w r3, r5, r4, lsl #2 - 800ab00: 9301 str r3, [sp, #4] - 800ab02: f858 3024 ldr.w r3, [r8, r4, lsl #2] - 800ab06: f855 2024 ldr.w r2, [r5, r4, lsl #2] - 800ab0a: 3301 adds r3, #1 - 800ab0c: 429a cmp r2, r3 - 800ab0e: fbb2 f6f3 udiv r6, r2, r3 - 800ab12: eb08 0984 add.w r9, r8, r4, lsl #2 - 800ab16: d32e bcc.n 800ab76 - 800ab18: f04f 0a00 mov.w sl, #0 - 800ab1c: 46c4 mov ip, r8 - 800ab1e: 46ae mov lr, r5 - 800ab20: 46d3 mov fp, sl - 800ab22: f85c 3b04 ldr.w r3, [ip], #4 - 800ab26: b298 uxth r0, r3 - 800ab28: fb06 a000 mla r0, r6, r0, sl - 800ab2c: 0c1b lsrs r3, r3, #16 - 800ab2e: 0c02 lsrs r2, r0, #16 - 800ab30: fb06 2303 mla r3, r6, r3, r2 - 800ab34: f8de 2000 ldr.w r2, [lr] - 800ab38: b280 uxth r0, r0 - 800ab3a: b292 uxth r2, r2 - 800ab3c: 1a12 subs r2, r2, r0 - 800ab3e: 445a add r2, fp - 800ab40: f8de 0000 ldr.w r0, [lr] - 800ab44: ea4f 4a13 mov.w sl, r3, lsr #16 - 800ab48: b29b uxth r3, r3 - 800ab4a: ebc3 4322 rsb r3, r3, r2, asr #16 - 800ab4e: eb03 4310 add.w r3, r3, r0, lsr #16 - 800ab52: b292 uxth r2, r2 - 800ab54: ea42 4203 orr.w r2, r2, r3, lsl #16 - 800ab58: 45e1 cmp r9, ip - 800ab5a: ea4f 4b23 mov.w fp, r3, asr #16 - 800ab5e: f84e 2b04 str.w r2, [lr], #4 - 800ab62: d2de bcs.n 800ab22 - 800ab64: 9b00 ldr r3, [sp, #0] - 800ab66: 58eb ldr r3, [r5, r3] - 800ab68: b92b cbnz r3, 800ab76 - 800ab6a: 9b01 ldr r3, [sp, #4] - 800ab6c: 3b04 subs r3, #4 - 800ab6e: 429d cmp r5, r3 - 800ab70: 461a mov r2, r3 - 800ab72: d32f bcc.n 800abd4 - 800ab74: 613c str r4, [r7, #16] - 800ab76: 4638 mov r0, r7 - 800ab78: f001 fcba bl 800c4f0 <__mcmp> - 800ab7c: 2800 cmp r0, #0 - 800ab7e: db25 blt.n 800abcc - 800ab80: 4629 mov r1, r5 - 800ab82: 2000 movs r0, #0 - 800ab84: f858 2b04 ldr.w r2, [r8], #4 - 800ab88: f8d1 c000 ldr.w ip, [r1] - 800ab8c: fa1f fe82 uxth.w lr, r2 - 800ab90: fa1f f38c uxth.w r3, ip - 800ab94: eba3 030e sub.w r3, r3, lr - 800ab98: 4403 add r3, r0 - 800ab9a: 0c12 lsrs r2, r2, #16 - 800ab9c: ebc2 4223 rsb r2, r2, r3, asr #16 - 800aba0: eb02 421c add.w r2, r2, ip, lsr #16 - 800aba4: b29b uxth r3, r3 - 800aba6: ea43 4302 orr.w r3, r3, r2, lsl #16 - 800abaa: 45c1 cmp r9, r8 - 800abac: ea4f 4022 mov.w r0, r2, asr #16 - 800abb0: f841 3b04 str.w r3, [r1], #4 - 800abb4: d2e6 bcs.n 800ab84 - 800abb6: f855 2024 ldr.w r2, [r5, r4, lsl #2] - 800abba: eb05 0384 add.w r3, r5, r4, lsl #2 - 800abbe: b922 cbnz r2, 800abca - 800abc0: 3b04 subs r3, #4 - 800abc2: 429d cmp r5, r3 - 800abc4: 461a mov r2, r3 - 800abc6: d30b bcc.n 800abe0 - 800abc8: 613c str r4, [r7, #16] - 800abca: 3601 adds r6, #1 - 800abcc: 4630 mov r0, r6 - 800abce: b003 add sp, #12 - 800abd0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800abd4: 6812 ldr r2, [r2, #0] - 800abd6: 3b04 subs r3, #4 - 800abd8: 2a00 cmp r2, #0 - 800abda: d1cb bne.n 800ab74 - 800abdc: 3c01 subs r4, #1 - 800abde: e7c6 b.n 800ab6e - 800abe0: 6812 ldr r2, [r2, #0] - 800abe2: 3b04 subs r3, #4 - 800abe4: 2a00 cmp r2, #0 - 800abe6: d1ef bne.n 800abc8 - 800abe8: 3c01 subs r4, #1 - 800abea: e7ea b.n 800abc2 - 800abec: 2000 movs r0, #0 - 800abee: e7ee b.n 800abce - -0800abf0 <_dtoa_r>: - 800abf0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800abf4: 4614 mov r4, r2 - 800abf6: 461d mov r5, r3 - 800abf8: 69c7 ldr r7, [r0, #28] - 800abfa: b097 sub sp, #92 @ 0x5c - 800abfc: 4683 mov fp, r0 - 800abfe: e9cd 4502 strd r4, r5, [sp, #8] - 800ac02: 9e23 ldr r6, [sp, #140] @ 0x8c - 800ac04: b97f cbnz r7, 800ac26 <_dtoa_r+0x36> - 800ac06: 2010 movs r0, #16 - 800ac08: f001 f894 bl 800bd34 - 800ac0c: 4602 mov r2, r0 - 800ac0e: f8cb 001c str.w r0, [fp, #28] - 800ac12: b920 cbnz r0, 800ac1e <_dtoa_r+0x2e> - 800ac14: 21ef movs r1, #239 @ 0xef - 800ac16: 4ba8 ldr r3, [pc, #672] @ (800aeb8 <_dtoa_r+0x2c8>) - 800ac18: 48a8 ldr r0, [pc, #672] @ (800aebc <_dtoa_r+0x2cc>) - 800ac1a: f7ff ff43 bl 800aaa4 <__assert_func> - 800ac1e: e9c0 7701 strd r7, r7, [r0, #4] - 800ac22: 6007 str r7, [r0, #0] - 800ac24: 60c7 str r7, [r0, #12] - 800ac26: f8db 301c ldr.w r3, [fp, #28] - 800ac2a: 6819 ldr r1, [r3, #0] - 800ac2c: b159 cbz r1, 800ac46 <_dtoa_r+0x56> - 800ac2e: 685a ldr r2, [r3, #4] - 800ac30: 2301 movs r3, #1 - 800ac32: 4093 lsls r3, r2 - 800ac34: 604a str r2, [r1, #4] - 800ac36: 608b str r3, [r1, #8] - 800ac38: 4658 mov r0, fp - 800ac3a: f001 fa21 bl 800c080 <_Bfree> - 800ac3e: 2200 movs r2, #0 - 800ac40: f8db 301c ldr.w r3, [fp, #28] - 800ac44: 601a str r2, [r3, #0] - 800ac46: 1e2b subs r3, r5, #0 - 800ac48: bfaf iteee ge - 800ac4a: 2300 movge r3, #0 - 800ac4c: 2201 movlt r2, #1 - 800ac4e: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 - 800ac52: 9303 strlt r3, [sp, #12] - 800ac54: bfa8 it ge - 800ac56: 6033 strge r3, [r6, #0] - 800ac58: f8dd 800c ldr.w r8, [sp, #12] - 800ac5c: 4b98 ldr r3, [pc, #608] @ (800aec0 <_dtoa_r+0x2d0>) - 800ac5e: bfb8 it lt - 800ac60: 6032 strlt r2, [r6, #0] - 800ac62: ea33 0308 bics.w r3, r3, r8 - 800ac66: d112 bne.n 800ac8e <_dtoa_r+0x9e> - 800ac68: f242 730f movw r3, #9999 @ 0x270f - 800ac6c: 9a22 ldr r2, [sp, #136] @ 0x88 - 800ac6e: 6013 str r3, [r2, #0] - 800ac70: f3c8 0313 ubfx r3, r8, #0, #20 - 800ac74: 4323 orrs r3, r4 - 800ac76: f000 8550 beq.w 800b71a <_dtoa_r+0xb2a> - 800ac7a: 9b24 ldr r3, [sp, #144] @ 0x90 - 800ac7c: f8df a244 ldr.w sl, [pc, #580] @ 800aec4 <_dtoa_r+0x2d4> - 800ac80: 2b00 cmp r3, #0 - 800ac82: f000 8552 beq.w 800b72a <_dtoa_r+0xb3a> - 800ac86: f10a 0303 add.w r3, sl, #3 - 800ac8a: f000 bd4c b.w 800b726 <_dtoa_r+0xb36> - 800ac8e: e9dd 2302 ldrd r2, r3, [sp, #8] - 800ac92: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 - 800ac96: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 - 800ac9a: 2200 movs r2, #0 - 800ac9c: 2300 movs r3, #0 - 800ac9e: f7f5 fef9 bl 8000a94 <__aeabi_dcmpeq> - 800aca2: 4607 mov r7, r0 - 800aca4: b158 cbz r0, 800acbe <_dtoa_r+0xce> - 800aca6: 2301 movs r3, #1 - 800aca8: 9a22 ldr r2, [sp, #136] @ 0x88 - 800acaa: 6013 str r3, [r2, #0] - 800acac: 9b24 ldr r3, [sp, #144] @ 0x90 - 800acae: b113 cbz r3, 800acb6 <_dtoa_r+0xc6> - 800acb0: 4b85 ldr r3, [pc, #532] @ (800aec8 <_dtoa_r+0x2d8>) - 800acb2: 9a24 ldr r2, [sp, #144] @ 0x90 - 800acb4: 6013 str r3, [r2, #0] - 800acb6: f8df a214 ldr.w sl, [pc, #532] @ 800aecc <_dtoa_r+0x2dc> - 800acba: f000 bd36 b.w 800b72a <_dtoa_r+0xb3a> - 800acbe: ab14 add r3, sp, #80 @ 0x50 - 800acc0: 9301 str r3, [sp, #4] - 800acc2: ab15 add r3, sp, #84 @ 0x54 - 800acc4: 9300 str r3, [sp, #0] - 800acc6: 4658 mov r0, fp - 800acc8: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 - 800accc: f001 fcc0 bl 800c650 <__d2b> - 800acd0: f3c8 560a ubfx r6, r8, #20, #11 - 800acd4: 4681 mov r9, r0 - 800acd6: 2e00 cmp r6, #0 - 800acd8: d077 beq.n 800adca <_dtoa_r+0x1da> - 800acda: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 - 800acde: 9b0d ldr r3, [sp, #52] @ 0x34 - 800ace0: f2a6 36ff subw r6, r6, #1023 @ 0x3ff - 800ace4: f3c3 0313 ubfx r3, r3, #0, #20 - 800ace8: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 - 800acec: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 - 800acf0: 9712 str r7, [sp, #72] @ 0x48 - 800acf2: 4619 mov r1, r3 - 800acf4: 2200 movs r2, #0 - 800acf6: 4b76 ldr r3, [pc, #472] @ (800aed0 <_dtoa_r+0x2e0>) - 800acf8: f7f5 faac bl 8000254 <__aeabi_dsub> - 800acfc: a368 add r3, pc, #416 @ (adr r3, 800aea0 <_dtoa_r+0x2b0>) - 800acfe: e9d3 2300 ldrd r2, r3, [r3] - 800ad02: f7f5 fc5f bl 80005c4 <__aeabi_dmul> - 800ad06: a368 add r3, pc, #416 @ (adr r3, 800aea8 <_dtoa_r+0x2b8>) - 800ad08: e9d3 2300 ldrd r2, r3, [r3] - 800ad0c: f7f5 faa4 bl 8000258 <__adddf3> - 800ad10: 4604 mov r4, r0 - 800ad12: 4630 mov r0, r6 - 800ad14: 460d mov r5, r1 - 800ad16: f7f5 fbeb bl 80004f0 <__aeabi_i2d> - 800ad1a: a365 add r3, pc, #404 @ (adr r3, 800aeb0 <_dtoa_r+0x2c0>) - 800ad1c: e9d3 2300 ldrd r2, r3, [r3] - 800ad20: f7f5 fc50 bl 80005c4 <__aeabi_dmul> - 800ad24: 4602 mov r2, r0 - 800ad26: 460b mov r3, r1 - 800ad28: 4620 mov r0, r4 - 800ad2a: 4629 mov r1, r5 - 800ad2c: f7f5 fa94 bl 8000258 <__adddf3> - 800ad30: 4604 mov r4, r0 - 800ad32: 460d mov r5, r1 - 800ad34: f7f5 fef6 bl 8000b24 <__aeabi_d2iz> - 800ad38: 2200 movs r2, #0 - 800ad3a: 4607 mov r7, r0 - 800ad3c: 2300 movs r3, #0 - 800ad3e: 4620 mov r0, r4 - 800ad40: 4629 mov r1, r5 - 800ad42: f7f5 feb1 bl 8000aa8 <__aeabi_dcmplt> - 800ad46: b140 cbz r0, 800ad5a <_dtoa_r+0x16a> - 800ad48: 4638 mov r0, r7 - 800ad4a: f7f5 fbd1 bl 80004f0 <__aeabi_i2d> - 800ad4e: 4622 mov r2, r4 - 800ad50: 462b mov r3, r5 - 800ad52: f7f5 fe9f bl 8000a94 <__aeabi_dcmpeq> - 800ad56: b900 cbnz r0, 800ad5a <_dtoa_r+0x16a> - 800ad58: 3f01 subs r7, #1 - 800ad5a: 2f16 cmp r7, #22 - 800ad5c: d853 bhi.n 800ae06 <_dtoa_r+0x216> - 800ad5e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 - 800ad62: 4b5c ldr r3, [pc, #368] @ (800aed4 <_dtoa_r+0x2e4>) - 800ad64: eb03 03c7 add.w r3, r3, r7, lsl #3 - 800ad68: e9d3 2300 ldrd r2, r3, [r3] - 800ad6c: f7f5 fe9c bl 8000aa8 <__aeabi_dcmplt> - 800ad70: 2800 cmp r0, #0 - 800ad72: d04a beq.n 800ae0a <_dtoa_r+0x21a> - 800ad74: 2300 movs r3, #0 - 800ad76: 3f01 subs r7, #1 - 800ad78: 930f str r3, [sp, #60] @ 0x3c - 800ad7a: 9b14 ldr r3, [sp, #80] @ 0x50 - 800ad7c: 1b9b subs r3, r3, r6 - 800ad7e: 1e5a subs r2, r3, #1 - 800ad80: bf46 itte mi - 800ad82: f1c3 0801 rsbmi r8, r3, #1 - 800ad86: 2300 movmi r3, #0 - 800ad88: f04f 0800 movpl.w r8, #0 - 800ad8c: 9209 str r2, [sp, #36] @ 0x24 - 800ad8e: bf48 it mi - 800ad90: 9309 strmi r3, [sp, #36] @ 0x24 - 800ad92: 2f00 cmp r7, #0 - 800ad94: db3b blt.n 800ae0e <_dtoa_r+0x21e> - 800ad96: 9b09 ldr r3, [sp, #36] @ 0x24 - 800ad98: 970e str r7, [sp, #56] @ 0x38 - 800ad9a: 443b add r3, r7 - 800ad9c: 9309 str r3, [sp, #36] @ 0x24 - 800ad9e: 2300 movs r3, #0 - 800ada0: 930a str r3, [sp, #40] @ 0x28 - 800ada2: 9b20 ldr r3, [sp, #128] @ 0x80 - 800ada4: 2b09 cmp r3, #9 - 800ada6: d866 bhi.n 800ae76 <_dtoa_r+0x286> - 800ada8: 2b05 cmp r3, #5 - 800adaa: bfc4 itt gt - 800adac: 3b04 subgt r3, #4 - 800adae: 9320 strgt r3, [sp, #128] @ 0x80 - 800adb0: 9b20 ldr r3, [sp, #128] @ 0x80 - 800adb2: bfc8 it gt - 800adb4: 2400 movgt r4, #0 - 800adb6: f1a3 0302 sub.w r3, r3, #2 - 800adba: bfd8 it le - 800adbc: 2401 movle r4, #1 - 800adbe: 2b03 cmp r3, #3 - 800adc0: d864 bhi.n 800ae8c <_dtoa_r+0x29c> - 800adc2: e8df f003 tbb [pc, r3] - 800adc6: 382b .short 0x382b - 800adc8: 5636 .short 0x5636 - 800adca: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 - 800adce: 441e add r6, r3 - 800add0: f206 4332 addw r3, r6, #1074 @ 0x432 - 800add4: 2b20 cmp r3, #32 - 800add6: bfc1 itttt gt - 800add8: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 - 800addc: fa08 f803 lslgt.w r8, r8, r3 - 800ade0: f206 4312 addwgt r3, r6, #1042 @ 0x412 - 800ade4: fa24 f303 lsrgt.w r3, r4, r3 - 800ade8: bfd6 itet le - 800adea: f1c3 0320 rsble r3, r3, #32 - 800adee: ea48 0003 orrgt.w r0, r8, r3 - 800adf2: fa04 f003 lslle.w r0, r4, r3 - 800adf6: f7f5 fb6b bl 80004d0 <__aeabi_ui2d> - 800adfa: 2201 movs r2, #1 - 800adfc: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 - 800ae00: 3e01 subs r6, #1 - 800ae02: 9212 str r2, [sp, #72] @ 0x48 - 800ae04: e775 b.n 800acf2 <_dtoa_r+0x102> - 800ae06: 2301 movs r3, #1 - 800ae08: e7b6 b.n 800ad78 <_dtoa_r+0x188> - 800ae0a: 900f str r0, [sp, #60] @ 0x3c - 800ae0c: e7b5 b.n 800ad7a <_dtoa_r+0x18a> - 800ae0e: 427b negs r3, r7 - 800ae10: 930a str r3, [sp, #40] @ 0x28 - 800ae12: 2300 movs r3, #0 - 800ae14: eba8 0807 sub.w r8, r8, r7 - 800ae18: 930e str r3, [sp, #56] @ 0x38 - 800ae1a: e7c2 b.n 800ada2 <_dtoa_r+0x1b2> - 800ae1c: 2300 movs r3, #0 - 800ae1e: 930b str r3, [sp, #44] @ 0x2c - 800ae20: 9b21 ldr r3, [sp, #132] @ 0x84 - 800ae22: 2b00 cmp r3, #0 - 800ae24: dc35 bgt.n 800ae92 <_dtoa_r+0x2a2> - 800ae26: 2301 movs r3, #1 - 800ae28: 461a mov r2, r3 - 800ae2a: e9cd 3307 strd r3, r3, [sp, #28] - 800ae2e: 9221 str r2, [sp, #132] @ 0x84 - 800ae30: e00b b.n 800ae4a <_dtoa_r+0x25a> - 800ae32: 2301 movs r3, #1 - 800ae34: e7f3 b.n 800ae1e <_dtoa_r+0x22e> - 800ae36: 2300 movs r3, #0 - 800ae38: 930b str r3, [sp, #44] @ 0x2c - 800ae3a: 9b21 ldr r3, [sp, #132] @ 0x84 - 800ae3c: 18fb adds r3, r7, r3 - 800ae3e: 9308 str r3, [sp, #32] - 800ae40: 3301 adds r3, #1 - 800ae42: 2b01 cmp r3, #1 - 800ae44: 9307 str r3, [sp, #28] - 800ae46: bfb8 it lt - 800ae48: 2301 movlt r3, #1 - 800ae4a: 2100 movs r1, #0 - 800ae4c: 2204 movs r2, #4 - 800ae4e: f8db 001c ldr.w r0, [fp, #28] - 800ae52: f102 0514 add.w r5, r2, #20 - 800ae56: 429d cmp r5, r3 - 800ae58: d91f bls.n 800ae9a <_dtoa_r+0x2aa> - 800ae5a: 6041 str r1, [r0, #4] - 800ae5c: 4658 mov r0, fp - 800ae5e: f001 f8cf bl 800c000 <_Balloc> - 800ae62: 4682 mov sl, r0 - 800ae64: 2800 cmp r0, #0 - 800ae66: d139 bne.n 800aedc <_dtoa_r+0x2ec> - 800ae68: 4602 mov r2, r0 - 800ae6a: f240 11af movw r1, #431 @ 0x1af - 800ae6e: 4b1a ldr r3, [pc, #104] @ (800aed8 <_dtoa_r+0x2e8>) - 800ae70: e6d2 b.n 800ac18 <_dtoa_r+0x28> - 800ae72: 2301 movs r3, #1 - 800ae74: e7e0 b.n 800ae38 <_dtoa_r+0x248> - 800ae76: 2401 movs r4, #1 - 800ae78: 2300 movs r3, #0 - 800ae7a: 940b str r4, [sp, #44] @ 0x2c - 800ae7c: 9320 str r3, [sp, #128] @ 0x80 - 800ae7e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff - 800ae82: 2200 movs r2, #0 - 800ae84: e9cd 3307 strd r3, r3, [sp, #28] - 800ae88: 2312 movs r3, #18 - 800ae8a: e7d0 b.n 800ae2e <_dtoa_r+0x23e> - 800ae8c: 2301 movs r3, #1 - 800ae8e: 930b str r3, [sp, #44] @ 0x2c - 800ae90: e7f5 b.n 800ae7e <_dtoa_r+0x28e> - 800ae92: 9b21 ldr r3, [sp, #132] @ 0x84 - 800ae94: e9cd 3307 strd r3, r3, [sp, #28] - 800ae98: e7d7 b.n 800ae4a <_dtoa_r+0x25a> - 800ae9a: 3101 adds r1, #1 - 800ae9c: 0052 lsls r2, r2, #1 - 800ae9e: e7d8 b.n 800ae52 <_dtoa_r+0x262> - 800aea0: 636f4361 .word 0x636f4361 - 800aea4: 3fd287a7 .word 0x3fd287a7 - 800aea8: 8b60c8b3 .word 0x8b60c8b3 - 800aeac: 3fc68a28 .word 0x3fc68a28 - 800aeb0: 509f79fb .word 0x509f79fb - 800aeb4: 3fd34413 .word 0x3fd34413 - 800aeb8: 0800e036 .word 0x0800e036 - 800aebc: 0800e1f7 .word 0x0800e1f7 - 800aec0: 7ff00000 .word 0x7ff00000 - 800aec4: 0800e1f3 .word 0x0800e1f3 - 800aec8: 0800e4ea .word 0x0800e4ea - 800aecc: 0800e4e9 .word 0x0800e4e9 - 800aed0: 3ff80000 .word 0x3ff80000 - 800aed4: 0800e300 .word 0x0800e300 - 800aed8: 0800e24f .word 0x0800e24f - 800aedc: f8db 301c ldr.w r3, [fp, #28] - 800aee0: 6018 str r0, [r3, #0] - 800aee2: 9b07 ldr r3, [sp, #28] - 800aee4: 2b0e cmp r3, #14 - 800aee6: f200 80a4 bhi.w 800b032 <_dtoa_r+0x442> - 800aeea: 2c00 cmp r4, #0 - 800aeec: f000 80a1 beq.w 800b032 <_dtoa_r+0x442> - 800aef0: 2f00 cmp r7, #0 - 800aef2: dd33 ble.n 800af5c <_dtoa_r+0x36c> - 800aef4: 4b86 ldr r3, [pc, #536] @ (800b110 <_dtoa_r+0x520>) - 800aef6: f007 020f and.w r2, r7, #15 - 800aefa: eb03 03c2 add.w r3, r3, r2, lsl #3 - 800aefe: 05f8 lsls r0, r7, #23 - 800af00: e9d3 3400 ldrd r3, r4, [r3] - 800af04: e9cd 3404 strd r3, r4, [sp, #16] - 800af08: ea4f 1427 mov.w r4, r7, asr #4 - 800af0c: d516 bpl.n 800af3c <_dtoa_r+0x34c> - 800af0e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 - 800af12: 4b80 ldr r3, [pc, #512] @ (800b114 <_dtoa_r+0x524>) - 800af14: 2603 movs r6, #3 - 800af16: e9d3 2308 ldrd r2, r3, [r3, #32] - 800af1a: f7f5 fc7d bl 8000818 <__aeabi_ddiv> - 800af1e: e9cd 0102 strd r0, r1, [sp, #8] - 800af22: f004 040f and.w r4, r4, #15 - 800af26: 4d7b ldr r5, [pc, #492] @ (800b114 <_dtoa_r+0x524>) - 800af28: b954 cbnz r4, 800af40 <_dtoa_r+0x350> - 800af2a: e9dd 2304 ldrd r2, r3, [sp, #16] - 800af2e: e9dd 0102 ldrd r0, r1, [sp, #8] - 800af32: f7f5 fc71 bl 8000818 <__aeabi_ddiv> - 800af36: e9cd 0102 strd r0, r1, [sp, #8] - 800af3a: e028 b.n 800af8e <_dtoa_r+0x39e> - 800af3c: 2602 movs r6, #2 - 800af3e: e7f2 b.n 800af26 <_dtoa_r+0x336> - 800af40: 07e1 lsls r1, r4, #31 - 800af42: d508 bpl.n 800af56 <_dtoa_r+0x366> - 800af44: e9dd 0104 ldrd r0, r1, [sp, #16] - 800af48: e9d5 2300 ldrd r2, r3, [r5] - 800af4c: f7f5 fb3a bl 80005c4 <__aeabi_dmul> - 800af50: e9cd 0104 strd r0, r1, [sp, #16] - 800af54: 3601 adds r6, #1 - 800af56: 1064 asrs r4, r4, #1 - 800af58: 3508 adds r5, #8 - 800af5a: e7e5 b.n 800af28 <_dtoa_r+0x338> - 800af5c: f000 80d2 beq.w 800b104 <_dtoa_r+0x514> - 800af60: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 - 800af64: 427c negs r4, r7 - 800af66: 4b6a ldr r3, [pc, #424] @ (800b110 <_dtoa_r+0x520>) - 800af68: f004 020f and.w r2, r4, #15 - 800af6c: eb03 03c2 add.w r3, r3, r2, lsl #3 - 800af70: e9d3 2300 ldrd r2, r3, [r3] - 800af74: f7f5 fb26 bl 80005c4 <__aeabi_dmul> - 800af78: 2602 movs r6, #2 - 800af7a: 2300 movs r3, #0 - 800af7c: e9cd 0102 strd r0, r1, [sp, #8] - 800af80: 4d64 ldr r5, [pc, #400] @ (800b114 <_dtoa_r+0x524>) - 800af82: 1124 asrs r4, r4, #4 - 800af84: 2c00 cmp r4, #0 - 800af86: f040 80b2 bne.w 800b0ee <_dtoa_r+0x4fe> - 800af8a: 2b00 cmp r3, #0 - 800af8c: d1d3 bne.n 800af36 <_dtoa_r+0x346> - 800af8e: e9dd 4502 ldrd r4, r5, [sp, #8] - 800af92: 9b0f ldr r3, [sp, #60] @ 0x3c - 800af94: 2b00 cmp r3, #0 - 800af96: f000 80b7 beq.w 800b108 <_dtoa_r+0x518> - 800af9a: 2200 movs r2, #0 - 800af9c: 4620 mov r0, r4 - 800af9e: 4629 mov r1, r5 - 800afa0: 4b5d ldr r3, [pc, #372] @ (800b118 <_dtoa_r+0x528>) - 800afa2: f7f5 fd81 bl 8000aa8 <__aeabi_dcmplt> - 800afa6: 2800 cmp r0, #0 - 800afa8: f000 80ae beq.w 800b108 <_dtoa_r+0x518> - 800afac: 9b07 ldr r3, [sp, #28] - 800afae: 2b00 cmp r3, #0 - 800afb0: f000 80aa beq.w 800b108 <_dtoa_r+0x518> - 800afb4: 9b08 ldr r3, [sp, #32] - 800afb6: 2b00 cmp r3, #0 - 800afb8: dd37 ble.n 800b02a <_dtoa_r+0x43a> - 800afba: 1e7b subs r3, r7, #1 - 800afbc: 4620 mov r0, r4 - 800afbe: 9304 str r3, [sp, #16] - 800afc0: 2200 movs r2, #0 - 800afc2: 4629 mov r1, r5 - 800afc4: 4b55 ldr r3, [pc, #340] @ (800b11c <_dtoa_r+0x52c>) - 800afc6: f7f5 fafd bl 80005c4 <__aeabi_dmul> - 800afca: e9cd 0102 strd r0, r1, [sp, #8] - 800afce: 9c08 ldr r4, [sp, #32] - 800afd0: 3601 adds r6, #1 - 800afd2: 4630 mov r0, r6 - 800afd4: f7f5 fa8c bl 80004f0 <__aeabi_i2d> - 800afd8: e9dd 2302 ldrd r2, r3, [sp, #8] - 800afdc: f7f5 faf2 bl 80005c4 <__aeabi_dmul> - 800afe0: 2200 movs r2, #0 - 800afe2: 4b4f ldr r3, [pc, #316] @ (800b120 <_dtoa_r+0x530>) - 800afe4: f7f5 f938 bl 8000258 <__adddf3> - 800afe8: 4605 mov r5, r0 - 800afea: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 - 800afee: 2c00 cmp r4, #0 - 800aff0: f040 809a bne.w 800b128 <_dtoa_r+0x538> - 800aff4: e9dd 0102 ldrd r0, r1, [sp, #8] - 800aff8: 2200 movs r2, #0 - 800affa: 4b4a ldr r3, [pc, #296] @ (800b124 <_dtoa_r+0x534>) - 800affc: f7f5 f92a bl 8000254 <__aeabi_dsub> - 800b000: 4602 mov r2, r0 - 800b002: 460b mov r3, r1 - 800b004: e9cd 2302 strd r2, r3, [sp, #8] - 800b008: 462a mov r2, r5 - 800b00a: 4633 mov r3, r6 - 800b00c: f7f5 fd6a bl 8000ae4 <__aeabi_dcmpgt> - 800b010: 2800 cmp r0, #0 - 800b012: f040 828e bne.w 800b532 <_dtoa_r+0x942> - 800b016: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b01a: 462a mov r2, r5 - 800b01c: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 - 800b020: f7f5 fd42 bl 8000aa8 <__aeabi_dcmplt> - 800b024: 2800 cmp r0, #0 - 800b026: f040 8127 bne.w 800b278 <_dtoa_r+0x688> - 800b02a: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 - 800b02e: e9cd 3402 strd r3, r4, [sp, #8] - 800b032: 9b15 ldr r3, [sp, #84] @ 0x54 - 800b034: 2b00 cmp r3, #0 - 800b036: f2c0 8163 blt.w 800b300 <_dtoa_r+0x710> - 800b03a: 2f0e cmp r7, #14 - 800b03c: f300 8160 bgt.w 800b300 <_dtoa_r+0x710> - 800b040: 4b33 ldr r3, [pc, #204] @ (800b110 <_dtoa_r+0x520>) - 800b042: eb03 03c7 add.w r3, r3, r7, lsl #3 - 800b046: e9d3 3400 ldrd r3, r4, [r3] - 800b04a: e9cd 3404 strd r3, r4, [sp, #16] - 800b04e: 9b21 ldr r3, [sp, #132] @ 0x84 - 800b050: 2b00 cmp r3, #0 - 800b052: da03 bge.n 800b05c <_dtoa_r+0x46c> - 800b054: 9b07 ldr r3, [sp, #28] - 800b056: 2b00 cmp r3, #0 - 800b058: f340 8100 ble.w 800b25c <_dtoa_r+0x66c> - 800b05c: e9dd 4502 ldrd r4, r5, [sp, #8] - 800b060: 4656 mov r6, sl - 800b062: e9dd 2304 ldrd r2, r3, [sp, #16] - 800b066: 4620 mov r0, r4 - 800b068: 4629 mov r1, r5 - 800b06a: f7f5 fbd5 bl 8000818 <__aeabi_ddiv> - 800b06e: f7f5 fd59 bl 8000b24 <__aeabi_d2iz> - 800b072: 4680 mov r8, r0 - 800b074: f7f5 fa3c bl 80004f0 <__aeabi_i2d> - 800b078: e9dd 2304 ldrd r2, r3, [sp, #16] - 800b07c: f7f5 faa2 bl 80005c4 <__aeabi_dmul> - 800b080: 4602 mov r2, r0 - 800b082: 460b mov r3, r1 - 800b084: 4620 mov r0, r4 - 800b086: 4629 mov r1, r5 - 800b088: f7f5 f8e4 bl 8000254 <__aeabi_dsub> - 800b08c: f108 0430 add.w r4, r8, #48 @ 0x30 - 800b090: 9d07 ldr r5, [sp, #28] - 800b092: f806 4b01 strb.w r4, [r6], #1 - 800b096: eba6 040a sub.w r4, r6, sl - 800b09a: 42a5 cmp r5, r4 - 800b09c: 4602 mov r2, r0 - 800b09e: 460b mov r3, r1 - 800b0a0: f040 8116 bne.w 800b2d0 <_dtoa_r+0x6e0> - 800b0a4: f7f5 f8d8 bl 8000258 <__adddf3> - 800b0a8: e9dd 2304 ldrd r2, r3, [sp, #16] - 800b0ac: 4604 mov r4, r0 - 800b0ae: 460d mov r5, r1 - 800b0b0: f7f5 fd18 bl 8000ae4 <__aeabi_dcmpgt> - 800b0b4: 2800 cmp r0, #0 - 800b0b6: f040 80f8 bne.w 800b2aa <_dtoa_r+0x6ba> - 800b0ba: e9dd 2304 ldrd r2, r3, [sp, #16] - 800b0be: 4620 mov r0, r4 - 800b0c0: 4629 mov r1, r5 - 800b0c2: f7f5 fce7 bl 8000a94 <__aeabi_dcmpeq> - 800b0c6: b118 cbz r0, 800b0d0 <_dtoa_r+0x4e0> - 800b0c8: f018 0f01 tst.w r8, #1 - 800b0cc: f040 80ed bne.w 800b2aa <_dtoa_r+0x6ba> - 800b0d0: 4649 mov r1, r9 - 800b0d2: 4658 mov r0, fp - 800b0d4: f000 ffd4 bl 800c080 <_Bfree> - 800b0d8: 2300 movs r3, #0 - 800b0da: 7033 strb r3, [r6, #0] - 800b0dc: 9b22 ldr r3, [sp, #136] @ 0x88 - 800b0de: 3701 adds r7, #1 - 800b0e0: 601f str r7, [r3, #0] - 800b0e2: 9b24 ldr r3, [sp, #144] @ 0x90 - 800b0e4: 2b00 cmp r3, #0 - 800b0e6: f000 8320 beq.w 800b72a <_dtoa_r+0xb3a> - 800b0ea: 601e str r6, [r3, #0] - 800b0ec: e31d b.n 800b72a <_dtoa_r+0xb3a> - 800b0ee: 07e2 lsls r2, r4, #31 - 800b0f0: d505 bpl.n 800b0fe <_dtoa_r+0x50e> - 800b0f2: e9d5 2300 ldrd r2, r3, [r5] - 800b0f6: f7f5 fa65 bl 80005c4 <__aeabi_dmul> - 800b0fa: 2301 movs r3, #1 - 800b0fc: 3601 adds r6, #1 - 800b0fe: 1064 asrs r4, r4, #1 - 800b100: 3508 adds r5, #8 - 800b102: e73f b.n 800af84 <_dtoa_r+0x394> - 800b104: 2602 movs r6, #2 - 800b106: e742 b.n 800af8e <_dtoa_r+0x39e> - 800b108: 9c07 ldr r4, [sp, #28] - 800b10a: 9704 str r7, [sp, #16] - 800b10c: e761 b.n 800afd2 <_dtoa_r+0x3e2> - 800b10e: bf00 nop - 800b110: 0800e300 .word 0x0800e300 - 800b114: 0800e2d8 .word 0x0800e2d8 - 800b118: 3ff00000 .word 0x3ff00000 - 800b11c: 40240000 .word 0x40240000 - 800b120: 401c0000 .word 0x401c0000 - 800b124: 40140000 .word 0x40140000 - 800b128: 4b70 ldr r3, [pc, #448] @ (800b2ec <_dtoa_r+0x6fc>) - 800b12a: 990b ldr r1, [sp, #44] @ 0x2c - 800b12c: eb03 03c4 add.w r3, r3, r4, lsl #3 - 800b130: e953 2302 ldrd r2, r3, [r3, #-8] - 800b134: 4454 add r4, sl - 800b136: 2900 cmp r1, #0 - 800b138: d045 beq.n 800b1c6 <_dtoa_r+0x5d6> - 800b13a: 2000 movs r0, #0 - 800b13c: 496c ldr r1, [pc, #432] @ (800b2f0 <_dtoa_r+0x700>) - 800b13e: f7f5 fb6b bl 8000818 <__aeabi_ddiv> - 800b142: 4633 mov r3, r6 - 800b144: 462a mov r2, r5 - 800b146: f7f5 f885 bl 8000254 <__aeabi_dsub> - 800b14a: 4656 mov r6, sl - 800b14c: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 - 800b150: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b154: f7f5 fce6 bl 8000b24 <__aeabi_d2iz> - 800b158: 4605 mov r5, r0 - 800b15a: f7f5 f9c9 bl 80004f0 <__aeabi_i2d> - 800b15e: 4602 mov r2, r0 - 800b160: 460b mov r3, r1 - 800b162: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b166: f7f5 f875 bl 8000254 <__aeabi_dsub> - 800b16a: 4602 mov r2, r0 - 800b16c: 460b mov r3, r1 - 800b16e: 3530 adds r5, #48 @ 0x30 - 800b170: e9cd 2302 strd r2, r3, [sp, #8] - 800b174: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 - 800b178: f806 5b01 strb.w r5, [r6], #1 - 800b17c: f7f5 fc94 bl 8000aa8 <__aeabi_dcmplt> - 800b180: 2800 cmp r0, #0 - 800b182: d163 bne.n 800b24c <_dtoa_r+0x65c> - 800b184: e9dd 2302 ldrd r2, r3, [sp, #8] - 800b188: 2000 movs r0, #0 - 800b18a: 495a ldr r1, [pc, #360] @ (800b2f4 <_dtoa_r+0x704>) - 800b18c: f7f5 f862 bl 8000254 <__aeabi_dsub> - 800b190: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 - 800b194: f7f5 fc88 bl 8000aa8 <__aeabi_dcmplt> - 800b198: 2800 cmp r0, #0 - 800b19a: f040 8087 bne.w 800b2ac <_dtoa_r+0x6bc> - 800b19e: 42a6 cmp r6, r4 - 800b1a0: f43f af43 beq.w 800b02a <_dtoa_r+0x43a> - 800b1a4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 - 800b1a8: 2200 movs r2, #0 - 800b1aa: 4b53 ldr r3, [pc, #332] @ (800b2f8 <_dtoa_r+0x708>) - 800b1ac: f7f5 fa0a bl 80005c4 <__aeabi_dmul> - 800b1b0: 2200 movs r2, #0 - 800b1b2: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 - 800b1b6: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b1ba: 4b4f ldr r3, [pc, #316] @ (800b2f8 <_dtoa_r+0x708>) - 800b1bc: f7f5 fa02 bl 80005c4 <__aeabi_dmul> - 800b1c0: e9cd 0102 strd r0, r1, [sp, #8] - 800b1c4: e7c4 b.n 800b150 <_dtoa_r+0x560> - 800b1c6: 4631 mov r1, r6 - 800b1c8: 4628 mov r0, r5 - 800b1ca: f7f5 f9fb bl 80005c4 <__aeabi_dmul> - 800b1ce: 4656 mov r6, sl - 800b1d0: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 - 800b1d4: 9413 str r4, [sp, #76] @ 0x4c - 800b1d6: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b1da: f7f5 fca3 bl 8000b24 <__aeabi_d2iz> - 800b1de: 4605 mov r5, r0 - 800b1e0: f7f5 f986 bl 80004f0 <__aeabi_i2d> - 800b1e4: 4602 mov r2, r0 - 800b1e6: 460b mov r3, r1 - 800b1e8: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b1ec: f7f5 f832 bl 8000254 <__aeabi_dsub> - 800b1f0: 4602 mov r2, r0 - 800b1f2: 460b mov r3, r1 - 800b1f4: 3530 adds r5, #48 @ 0x30 - 800b1f6: f806 5b01 strb.w r5, [r6], #1 - 800b1fa: 42a6 cmp r6, r4 - 800b1fc: e9cd 2302 strd r2, r3, [sp, #8] - 800b200: f04f 0200 mov.w r2, #0 - 800b204: d124 bne.n 800b250 <_dtoa_r+0x660> - 800b206: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 - 800b20a: 4b39 ldr r3, [pc, #228] @ (800b2f0 <_dtoa_r+0x700>) - 800b20c: f7f5 f824 bl 8000258 <__adddf3> - 800b210: 4602 mov r2, r0 - 800b212: 460b mov r3, r1 - 800b214: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b218: f7f5 fc64 bl 8000ae4 <__aeabi_dcmpgt> - 800b21c: 2800 cmp r0, #0 - 800b21e: d145 bne.n 800b2ac <_dtoa_r+0x6bc> - 800b220: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 - 800b224: 2000 movs r0, #0 - 800b226: 4932 ldr r1, [pc, #200] @ (800b2f0 <_dtoa_r+0x700>) - 800b228: f7f5 f814 bl 8000254 <__aeabi_dsub> - 800b22c: 4602 mov r2, r0 - 800b22e: 460b mov r3, r1 - 800b230: e9dd 0102 ldrd r0, r1, [sp, #8] - 800b234: f7f5 fc38 bl 8000aa8 <__aeabi_dcmplt> - 800b238: 2800 cmp r0, #0 - 800b23a: f43f aef6 beq.w 800b02a <_dtoa_r+0x43a> - 800b23e: 9e13 ldr r6, [sp, #76] @ 0x4c - 800b240: 1e73 subs r3, r6, #1 - 800b242: 9313 str r3, [sp, #76] @ 0x4c - 800b244: f816 3c01 ldrb.w r3, [r6, #-1] - 800b248: 2b30 cmp r3, #48 @ 0x30 - 800b24a: d0f8 beq.n 800b23e <_dtoa_r+0x64e> - 800b24c: 9f04 ldr r7, [sp, #16] - 800b24e: e73f b.n 800b0d0 <_dtoa_r+0x4e0> - 800b250: 4b29 ldr r3, [pc, #164] @ (800b2f8 <_dtoa_r+0x708>) - 800b252: f7f5 f9b7 bl 80005c4 <__aeabi_dmul> - 800b256: e9cd 0102 strd r0, r1, [sp, #8] - 800b25a: e7bc b.n 800b1d6 <_dtoa_r+0x5e6> - 800b25c: d10c bne.n 800b278 <_dtoa_r+0x688> - 800b25e: e9dd 0104 ldrd r0, r1, [sp, #16] - 800b262: 2200 movs r2, #0 - 800b264: 4b25 ldr r3, [pc, #148] @ (800b2fc <_dtoa_r+0x70c>) - 800b266: f7f5 f9ad bl 80005c4 <__aeabi_dmul> - 800b26a: e9dd 2302 ldrd r2, r3, [sp, #8] - 800b26e: f7f5 fc2f bl 8000ad0 <__aeabi_dcmpge> - 800b272: 2800 cmp r0, #0 - 800b274: f000 815b beq.w 800b52e <_dtoa_r+0x93e> - 800b278: 2400 movs r4, #0 - 800b27a: 4625 mov r5, r4 - 800b27c: 9b21 ldr r3, [sp, #132] @ 0x84 - 800b27e: 4656 mov r6, sl - 800b280: 43db mvns r3, r3 - 800b282: 9304 str r3, [sp, #16] - 800b284: 2700 movs r7, #0 - 800b286: 4621 mov r1, r4 - 800b288: 4658 mov r0, fp - 800b28a: f000 fef9 bl 800c080 <_Bfree> - 800b28e: 2d00 cmp r5, #0 - 800b290: d0dc beq.n 800b24c <_dtoa_r+0x65c> - 800b292: b12f cbz r7, 800b2a0 <_dtoa_r+0x6b0> - 800b294: 42af cmp r7, r5 - 800b296: d003 beq.n 800b2a0 <_dtoa_r+0x6b0> - 800b298: 4639 mov r1, r7 - 800b29a: 4658 mov r0, fp - 800b29c: f000 fef0 bl 800c080 <_Bfree> - 800b2a0: 4629 mov r1, r5 - 800b2a2: 4658 mov r0, fp - 800b2a4: f000 feec bl 800c080 <_Bfree> - 800b2a8: e7d0 b.n 800b24c <_dtoa_r+0x65c> - 800b2aa: 9704 str r7, [sp, #16] - 800b2ac: 4633 mov r3, r6 - 800b2ae: 461e mov r6, r3 - 800b2b0: f813 2d01 ldrb.w r2, [r3, #-1]! - 800b2b4: 2a39 cmp r2, #57 @ 0x39 - 800b2b6: d107 bne.n 800b2c8 <_dtoa_r+0x6d8> - 800b2b8: 459a cmp sl, r3 - 800b2ba: d1f8 bne.n 800b2ae <_dtoa_r+0x6be> - 800b2bc: 9a04 ldr r2, [sp, #16] - 800b2be: 3201 adds r2, #1 - 800b2c0: 9204 str r2, [sp, #16] - 800b2c2: 2230 movs r2, #48 @ 0x30 - 800b2c4: f88a 2000 strb.w r2, [sl] - 800b2c8: 781a ldrb r2, [r3, #0] - 800b2ca: 3201 adds r2, #1 - 800b2cc: 701a strb r2, [r3, #0] - 800b2ce: e7bd b.n 800b24c <_dtoa_r+0x65c> - 800b2d0: 2200 movs r2, #0 - 800b2d2: 4b09 ldr r3, [pc, #36] @ (800b2f8 <_dtoa_r+0x708>) - 800b2d4: f7f5 f976 bl 80005c4 <__aeabi_dmul> - 800b2d8: 2200 movs r2, #0 - 800b2da: 2300 movs r3, #0 - 800b2dc: 4604 mov r4, r0 - 800b2de: 460d mov r5, r1 - 800b2e0: f7f5 fbd8 bl 8000a94 <__aeabi_dcmpeq> - 800b2e4: 2800 cmp r0, #0 - 800b2e6: f43f aebc beq.w 800b062 <_dtoa_r+0x472> - 800b2ea: e6f1 b.n 800b0d0 <_dtoa_r+0x4e0> - 800b2ec: 0800e300 .word 0x0800e300 - 800b2f0: 3fe00000 .word 0x3fe00000 - 800b2f4: 3ff00000 .word 0x3ff00000 - 800b2f8: 40240000 .word 0x40240000 - 800b2fc: 40140000 .word 0x40140000 - 800b300: 9a0b ldr r2, [sp, #44] @ 0x2c - 800b302: 2a00 cmp r2, #0 - 800b304: f000 80db beq.w 800b4be <_dtoa_r+0x8ce> - 800b308: 9a20 ldr r2, [sp, #128] @ 0x80 - 800b30a: 2a01 cmp r2, #1 - 800b30c: f300 80bf bgt.w 800b48e <_dtoa_r+0x89e> - 800b310: 9a12 ldr r2, [sp, #72] @ 0x48 - 800b312: 2a00 cmp r2, #0 - 800b314: f000 80b7 beq.w 800b486 <_dtoa_r+0x896> - 800b318: f203 4333 addw r3, r3, #1075 @ 0x433 - 800b31c: 4646 mov r6, r8 - 800b31e: 9c0a ldr r4, [sp, #40] @ 0x28 - 800b320: 9a09 ldr r2, [sp, #36] @ 0x24 - 800b322: 2101 movs r1, #1 - 800b324: 441a add r2, r3 - 800b326: 4658 mov r0, fp - 800b328: 4498 add r8, r3 - 800b32a: 9209 str r2, [sp, #36] @ 0x24 - 800b32c: f000 ff5c bl 800c1e8 <__i2b> - 800b330: 4605 mov r5, r0 - 800b332: b15e cbz r6, 800b34c <_dtoa_r+0x75c> - 800b334: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b336: 2b00 cmp r3, #0 - 800b338: dd08 ble.n 800b34c <_dtoa_r+0x75c> - 800b33a: 42b3 cmp r3, r6 - 800b33c: bfa8 it ge - 800b33e: 4633 movge r3, r6 - 800b340: 9a09 ldr r2, [sp, #36] @ 0x24 - 800b342: eba8 0803 sub.w r8, r8, r3 - 800b346: 1af6 subs r6, r6, r3 - 800b348: 1ad3 subs r3, r2, r3 - 800b34a: 9309 str r3, [sp, #36] @ 0x24 - 800b34c: 9b0a ldr r3, [sp, #40] @ 0x28 - 800b34e: b1f3 cbz r3, 800b38e <_dtoa_r+0x79e> - 800b350: 9b0b ldr r3, [sp, #44] @ 0x2c - 800b352: 2b00 cmp r3, #0 - 800b354: f000 80b7 beq.w 800b4c6 <_dtoa_r+0x8d6> - 800b358: b18c cbz r4, 800b37e <_dtoa_r+0x78e> - 800b35a: 4629 mov r1, r5 - 800b35c: 4622 mov r2, r4 - 800b35e: 4658 mov r0, fp - 800b360: f001 f800 bl 800c364 <__pow5mult> - 800b364: 464a mov r2, r9 - 800b366: 4601 mov r1, r0 - 800b368: 4605 mov r5, r0 - 800b36a: 4658 mov r0, fp - 800b36c: f000 ff52 bl 800c214 <__multiply> - 800b370: 4649 mov r1, r9 - 800b372: 9004 str r0, [sp, #16] - 800b374: 4658 mov r0, fp - 800b376: f000 fe83 bl 800c080 <_Bfree> - 800b37a: 9b04 ldr r3, [sp, #16] - 800b37c: 4699 mov r9, r3 - 800b37e: 9b0a ldr r3, [sp, #40] @ 0x28 - 800b380: 1b1a subs r2, r3, r4 - 800b382: d004 beq.n 800b38e <_dtoa_r+0x79e> - 800b384: 4649 mov r1, r9 - 800b386: 4658 mov r0, fp - 800b388: f000 ffec bl 800c364 <__pow5mult> - 800b38c: 4681 mov r9, r0 - 800b38e: 2101 movs r1, #1 - 800b390: 4658 mov r0, fp - 800b392: f000 ff29 bl 800c1e8 <__i2b> - 800b396: 9b0e ldr r3, [sp, #56] @ 0x38 - 800b398: 4604 mov r4, r0 - 800b39a: 2b00 cmp r3, #0 - 800b39c: f000 81c9 beq.w 800b732 <_dtoa_r+0xb42> - 800b3a0: 461a mov r2, r3 - 800b3a2: 4601 mov r1, r0 - 800b3a4: 4658 mov r0, fp - 800b3a6: f000 ffdd bl 800c364 <__pow5mult> - 800b3aa: 9b20 ldr r3, [sp, #128] @ 0x80 - 800b3ac: 4604 mov r4, r0 - 800b3ae: 2b01 cmp r3, #1 - 800b3b0: f300 808f bgt.w 800b4d2 <_dtoa_r+0x8e2> - 800b3b4: 9b02 ldr r3, [sp, #8] - 800b3b6: 2b00 cmp r3, #0 - 800b3b8: f040 8087 bne.w 800b4ca <_dtoa_r+0x8da> - 800b3bc: 9b03 ldr r3, [sp, #12] - 800b3be: f3c3 0313 ubfx r3, r3, #0, #20 - 800b3c2: 2b00 cmp r3, #0 - 800b3c4: f040 8083 bne.w 800b4ce <_dtoa_r+0x8de> - 800b3c8: 9b03 ldr r3, [sp, #12] - 800b3ca: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 800b3ce: 0d1b lsrs r3, r3, #20 - 800b3d0: 051b lsls r3, r3, #20 - 800b3d2: b12b cbz r3, 800b3e0 <_dtoa_r+0x7f0> - 800b3d4: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b3d6: f108 0801 add.w r8, r8, #1 - 800b3da: 3301 adds r3, #1 - 800b3dc: 9309 str r3, [sp, #36] @ 0x24 - 800b3de: 2301 movs r3, #1 - 800b3e0: 930a str r3, [sp, #40] @ 0x28 - 800b3e2: 9b0e ldr r3, [sp, #56] @ 0x38 - 800b3e4: 2b00 cmp r3, #0 - 800b3e6: f000 81aa beq.w 800b73e <_dtoa_r+0xb4e> - 800b3ea: 6923 ldr r3, [r4, #16] - 800b3ec: eb04 0383 add.w r3, r4, r3, lsl #2 - 800b3f0: 6918 ldr r0, [r3, #16] - 800b3f2: f000 fead bl 800c150 <__hi0bits> - 800b3f6: f1c0 0020 rsb r0, r0, #32 - 800b3fa: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b3fc: 4418 add r0, r3 - 800b3fe: f010 001f ands.w r0, r0, #31 - 800b402: d071 beq.n 800b4e8 <_dtoa_r+0x8f8> - 800b404: f1c0 0320 rsb r3, r0, #32 - 800b408: 2b04 cmp r3, #4 - 800b40a: dd65 ble.n 800b4d8 <_dtoa_r+0x8e8> - 800b40c: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b40e: f1c0 001c rsb r0, r0, #28 - 800b412: 4403 add r3, r0 - 800b414: 4480 add r8, r0 - 800b416: 4406 add r6, r0 - 800b418: 9309 str r3, [sp, #36] @ 0x24 - 800b41a: f1b8 0f00 cmp.w r8, #0 - 800b41e: dd05 ble.n 800b42c <_dtoa_r+0x83c> - 800b420: 4649 mov r1, r9 - 800b422: 4642 mov r2, r8 - 800b424: 4658 mov r0, fp - 800b426: f000 fff7 bl 800c418 <__lshift> - 800b42a: 4681 mov r9, r0 - 800b42c: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b42e: 2b00 cmp r3, #0 - 800b430: dd05 ble.n 800b43e <_dtoa_r+0x84e> - 800b432: 4621 mov r1, r4 - 800b434: 461a mov r2, r3 - 800b436: 4658 mov r0, fp - 800b438: f000 ffee bl 800c418 <__lshift> - 800b43c: 4604 mov r4, r0 - 800b43e: 9b0f ldr r3, [sp, #60] @ 0x3c - 800b440: 2b00 cmp r3, #0 - 800b442: d053 beq.n 800b4ec <_dtoa_r+0x8fc> - 800b444: 4621 mov r1, r4 - 800b446: 4648 mov r0, r9 - 800b448: f001 f852 bl 800c4f0 <__mcmp> - 800b44c: 2800 cmp r0, #0 - 800b44e: da4d bge.n 800b4ec <_dtoa_r+0x8fc> - 800b450: 1e7b subs r3, r7, #1 - 800b452: 4649 mov r1, r9 - 800b454: 9304 str r3, [sp, #16] - 800b456: 220a movs r2, #10 - 800b458: 2300 movs r3, #0 - 800b45a: 4658 mov r0, fp - 800b45c: f000 fe32 bl 800c0c4 <__multadd> - 800b460: 9b0b ldr r3, [sp, #44] @ 0x2c - 800b462: 4681 mov r9, r0 - 800b464: 2b00 cmp r3, #0 - 800b466: f000 816c beq.w 800b742 <_dtoa_r+0xb52> - 800b46a: 2300 movs r3, #0 - 800b46c: 4629 mov r1, r5 - 800b46e: 220a movs r2, #10 - 800b470: 4658 mov r0, fp - 800b472: f000 fe27 bl 800c0c4 <__multadd> - 800b476: 9b08 ldr r3, [sp, #32] - 800b478: 4605 mov r5, r0 - 800b47a: 2b00 cmp r3, #0 - 800b47c: dc61 bgt.n 800b542 <_dtoa_r+0x952> - 800b47e: 9b20 ldr r3, [sp, #128] @ 0x80 - 800b480: 2b02 cmp r3, #2 - 800b482: dc3b bgt.n 800b4fc <_dtoa_r+0x90c> - 800b484: e05d b.n 800b542 <_dtoa_r+0x952> - 800b486: 9b14 ldr r3, [sp, #80] @ 0x50 - 800b488: f1c3 0336 rsb r3, r3, #54 @ 0x36 - 800b48c: e746 b.n 800b31c <_dtoa_r+0x72c> - 800b48e: 9b07 ldr r3, [sp, #28] - 800b490: 1e5c subs r4, r3, #1 - 800b492: 9b0a ldr r3, [sp, #40] @ 0x28 - 800b494: 42a3 cmp r3, r4 - 800b496: bfbf itttt lt - 800b498: 9b0a ldrlt r3, [sp, #40] @ 0x28 - 800b49a: 9a0e ldrlt r2, [sp, #56] @ 0x38 - 800b49c: 1ae3 sublt r3, r4, r3 - 800b49e: 18d2 addlt r2, r2, r3 - 800b4a0: bfa8 it ge - 800b4a2: 1b1c subge r4, r3, r4 - 800b4a4: 9b07 ldr r3, [sp, #28] - 800b4a6: bfbe ittt lt - 800b4a8: 940a strlt r4, [sp, #40] @ 0x28 - 800b4aa: 920e strlt r2, [sp, #56] @ 0x38 - 800b4ac: 2400 movlt r4, #0 - 800b4ae: 2b00 cmp r3, #0 - 800b4b0: bfb5 itete lt - 800b4b2: eba8 0603 sublt.w r6, r8, r3 - 800b4b6: 4646 movge r6, r8 - 800b4b8: 2300 movlt r3, #0 - 800b4ba: 9b07 ldrge r3, [sp, #28] - 800b4bc: e730 b.n 800b320 <_dtoa_r+0x730> - 800b4be: 4646 mov r6, r8 - 800b4c0: 9c0a ldr r4, [sp, #40] @ 0x28 - 800b4c2: 9d0b ldr r5, [sp, #44] @ 0x2c - 800b4c4: e735 b.n 800b332 <_dtoa_r+0x742> - 800b4c6: 9a0a ldr r2, [sp, #40] @ 0x28 - 800b4c8: e75c b.n 800b384 <_dtoa_r+0x794> - 800b4ca: 2300 movs r3, #0 - 800b4cc: e788 b.n 800b3e0 <_dtoa_r+0x7f0> - 800b4ce: 9b02 ldr r3, [sp, #8] - 800b4d0: e786 b.n 800b3e0 <_dtoa_r+0x7f0> - 800b4d2: 2300 movs r3, #0 - 800b4d4: 930a str r3, [sp, #40] @ 0x28 - 800b4d6: e788 b.n 800b3ea <_dtoa_r+0x7fa> - 800b4d8: d09f beq.n 800b41a <_dtoa_r+0x82a> - 800b4da: 9a09 ldr r2, [sp, #36] @ 0x24 - 800b4dc: 331c adds r3, #28 - 800b4de: 441a add r2, r3 - 800b4e0: 4498 add r8, r3 - 800b4e2: 441e add r6, r3 - 800b4e4: 9209 str r2, [sp, #36] @ 0x24 - 800b4e6: e798 b.n 800b41a <_dtoa_r+0x82a> - 800b4e8: 4603 mov r3, r0 - 800b4ea: e7f6 b.n 800b4da <_dtoa_r+0x8ea> - 800b4ec: 9b07 ldr r3, [sp, #28] - 800b4ee: 9704 str r7, [sp, #16] - 800b4f0: 2b00 cmp r3, #0 - 800b4f2: dc20 bgt.n 800b536 <_dtoa_r+0x946> - 800b4f4: 9308 str r3, [sp, #32] - 800b4f6: 9b20 ldr r3, [sp, #128] @ 0x80 - 800b4f8: 2b02 cmp r3, #2 - 800b4fa: dd1e ble.n 800b53a <_dtoa_r+0x94a> - 800b4fc: 9b08 ldr r3, [sp, #32] - 800b4fe: 2b00 cmp r3, #0 - 800b500: f47f aebc bne.w 800b27c <_dtoa_r+0x68c> - 800b504: 4621 mov r1, r4 - 800b506: 2205 movs r2, #5 - 800b508: 4658 mov r0, fp - 800b50a: f000 fddb bl 800c0c4 <__multadd> - 800b50e: 4601 mov r1, r0 - 800b510: 4604 mov r4, r0 - 800b512: 4648 mov r0, r9 - 800b514: f000 ffec bl 800c4f0 <__mcmp> - 800b518: 2800 cmp r0, #0 - 800b51a: f77f aeaf ble.w 800b27c <_dtoa_r+0x68c> - 800b51e: 2331 movs r3, #49 @ 0x31 - 800b520: 4656 mov r6, sl - 800b522: f806 3b01 strb.w r3, [r6], #1 - 800b526: 9b04 ldr r3, [sp, #16] - 800b528: 3301 adds r3, #1 - 800b52a: 9304 str r3, [sp, #16] - 800b52c: e6aa b.n 800b284 <_dtoa_r+0x694> - 800b52e: 9c07 ldr r4, [sp, #28] - 800b530: 9704 str r7, [sp, #16] - 800b532: 4625 mov r5, r4 - 800b534: e7f3 b.n 800b51e <_dtoa_r+0x92e> - 800b536: 9b07 ldr r3, [sp, #28] - 800b538: 9308 str r3, [sp, #32] - 800b53a: 9b0b ldr r3, [sp, #44] @ 0x2c - 800b53c: 2b00 cmp r3, #0 - 800b53e: f000 8104 beq.w 800b74a <_dtoa_r+0xb5a> - 800b542: 2e00 cmp r6, #0 - 800b544: dd05 ble.n 800b552 <_dtoa_r+0x962> - 800b546: 4629 mov r1, r5 - 800b548: 4632 mov r2, r6 - 800b54a: 4658 mov r0, fp - 800b54c: f000 ff64 bl 800c418 <__lshift> - 800b550: 4605 mov r5, r0 - 800b552: 9b0a ldr r3, [sp, #40] @ 0x28 - 800b554: 2b00 cmp r3, #0 - 800b556: d05a beq.n 800b60e <_dtoa_r+0xa1e> - 800b558: 4658 mov r0, fp - 800b55a: 6869 ldr r1, [r5, #4] - 800b55c: f000 fd50 bl 800c000 <_Balloc> - 800b560: 4606 mov r6, r0 - 800b562: b928 cbnz r0, 800b570 <_dtoa_r+0x980> - 800b564: 4602 mov r2, r0 - 800b566: f240 21ef movw r1, #751 @ 0x2ef - 800b56a: 4b83 ldr r3, [pc, #524] @ (800b778 <_dtoa_r+0xb88>) - 800b56c: f7ff bb54 b.w 800ac18 <_dtoa_r+0x28> - 800b570: 692a ldr r2, [r5, #16] - 800b572: f105 010c add.w r1, r5, #12 - 800b576: 3202 adds r2, #2 - 800b578: 0092 lsls r2, r2, #2 - 800b57a: 300c adds r0, #12 - 800b57c: f7ff fa7b bl 800aa76 - 800b580: 2201 movs r2, #1 - 800b582: 4631 mov r1, r6 - 800b584: 4658 mov r0, fp - 800b586: f000 ff47 bl 800c418 <__lshift> - 800b58a: 462f mov r7, r5 - 800b58c: 4605 mov r5, r0 - 800b58e: f10a 0301 add.w r3, sl, #1 - 800b592: 9307 str r3, [sp, #28] - 800b594: 9b08 ldr r3, [sp, #32] - 800b596: 4453 add r3, sl - 800b598: 930b str r3, [sp, #44] @ 0x2c - 800b59a: 9b02 ldr r3, [sp, #8] - 800b59c: f003 0301 and.w r3, r3, #1 - 800b5a0: 930a str r3, [sp, #40] @ 0x28 - 800b5a2: 9b07 ldr r3, [sp, #28] - 800b5a4: 4621 mov r1, r4 - 800b5a6: 3b01 subs r3, #1 - 800b5a8: 4648 mov r0, r9 - 800b5aa: 9302 str r3, [sp, #8] - 800b5ac: f7ff fa98 bl 800aae0 - 800b5b0: 4639 mov r1, r7 - 800b5b2: 9008 str r0, [sp, #32] - 800b5b4: f100 0830 add.w r8, r0, #48 @ 0x30 - 800b5b8: 4648 mov r0, r9 - 800b5ba: f000 ff99 bl 800c4f0 <__mcmp> - 800b5be: 462a mov r2, r5 - 800b5c0: 9009 str r0, [sp, #36] @ 0x24 - 800b5c2: 4621 mov r1, r4 - 800b5c4: 4658 mov r0, fp - 800b5c6: f000 ffaf bl 800c528 <__mdiff> - 800b5ca: 68c2 ldr r2, [r0, #12] - 800b5cc: 4606 mov r6, r0 - 800b5ce: bb02 cbnz r2, 800b612 <_dtoa_r+0xa22> - 800b5d0: 4601 mov r1, r0 - 800b5d2: 4648 mov r0, r9 - 800b5d4: f000 ff8c bl 800c4f0 <__mcmp> - 800b5d8: 4602 mov r2, r0 - 800b5da: 4631 mov r1, r6 - 800b5dc: 4658 mov r0, fp - 800b5de: 920c str r2, [sp, #48] @ 0x30 - 800b5e0: f000 fd4e bl 800c080 <_Bfree> - 800b5e4: 9b20 ldr r3, [sp, #128] @ 0x80 - 800b5e6: 9a0c ldr r2, [sp, #48] @ 0x30 - 800b5e8: 9e07 ldr r6, [sp, #28] - 800b5ea: ea43 0102 orr.w r1, r3, r2 - 800b5ee: 9b0a ldr r3, [sp, #40] @ 0x28 - 800b5f0: 4319 orrs r1, r3 - 800b5f2: d110 bne.n 800b616 <_dtoa_r+0xa26> - 800b5f4: f1b8 0f39 cmp.w r8, #57 @ 0x39 - 800b5f8: d029 beq.n 800b64e <_dtoa_r+0xa5e> - 800b5fa: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b5fc: 2b00 cmp r3, #0 - 800b5fe: dd02 ble.n 800b606 <_dtoa_r+0xa16> - 800b600: 9b08 ldr r3, [sp, #32] - 800b602: f103 0831 add.w r8, r3, #49 @ 0x31 - 800b606: 9b02 ldr r3, [sp, #8] - 800b608: f883 8000 strb.w r8, [r3] - 800b60c: e63b b.n 800b286 <_dtoa_r+0x696> - 800b60e: 4628 mov r0, r5 - 800b610: e7bb b.n 800b58a <_dtoa_r+0x99a> - 800b612: 2201 movs r2, #1 - 800b614: e7e1 b.n 800b5da <_dtoa_r+0x9ea> - 800b616: 9b09 ldr r3, [sp, #36] @ 0x24 - 800b618: 2b00 cmp r3, #0 - 800b61a: db04 blt.n 800b626 <_dtoa_r+0xa36> - 800b61c: 9920 ldr r1, [sp, #128] @ 0x80 - 800b61e: 430b orrs r3, r1 - 800b620: 990a ldr r1, [sp, #40] @ 0x28 - 800b622: 430b orrs r3, r1 - 800b624: d120 bne.n 800b668 <_dtoa_r+0xa78> - 800b626: 2a00 cmp r2, #0 - 800b628: dded ble.n 800b606 <_dtoa_r+0xa16> - 800b62a: 4649 mov r1, r9 - 800b62c: 2201 movs r2, #1 - 800b62e: 4658 mov r0, fp - 800b630: f000 fef2 bl 800c418 <__lshift> - 800b634: 4621 mov r1, r4 - 800b636: 4681 mov r9, r0 - 800b638: f000 ff5a bl 800c4f0 <__mcmp> - 800b63c: 2800 cmp r0, #0 - 800b63e: dc03 bgt.n 800b648 <_dtoa_r+0xa58> - 800b640: d1e1 bne.n 800b606 <_dtoa_r+0xa16> - 800b642: f018 0f01 tst.w r8, #1 - 800b646: d0de beq.n 800b606 <_dtoa_r+0xa16> - 800b648: f1b8 0f39 cmp.w r8, #57 @ 0x39 - 800b64c: d1d8 bne.n 800b600 <_dtoa_r+0xa10> - 800b64e: 2339 movs r3, #57 @ 0x39 - 800b650: 9a02 ldr r2, [sp, #8] - 800b652: 7013 strb r3, [r2, #0] - 800b654: 4633 mov r3, r6 - 800b656: 461e mov r6, r3 - 800b658: f816 2c01 ldrb.w r2, [r6, #-1] - 800b65c: 3b01 subs r3, #1 - 800b65e: 2a39 cmp r2, #57 @ 0x39 - 800b660: d052 beq.n 800b708 <_dtoa_r+0xb18> - 800b662: 3201 adds r2, #1 - 800b664: 701a strb r2, [r3, #0] - 800b666: e60e b.n 800b286 <_dtoa_r+0x696> - 800b668: 2a00 cmp r2, #0 - 800b66a: dd07 ble.n 800b67c <_dtoa_r+0xa8c> - 800b66c: f1b8 0f39 cmp.w r8, #57 @ 0x39 - 800b670: d0ed beq.n 800b64e <_dtoa_r+0xa5e> - 800b672: 9a02 ldr r2, [sp, #8] - 800b674: f108 0301 add.w r3, r8, #1 - 800b678: 7013 strb r3, [r2, #0] - 800b67a: e604 b.n 800b286 <_dtoa_r+0x696> - 800b67c: 9b07 ldr r3, [sp, #28] - 800b67e: 9a07 ldr r2, [sp, #28] - 800b680: f803 8c01 strb.w r8, [r3, #-1] - 800b684: 9b0b ldr r3, [sp, #44] @ 0x2c - 800b686: 4293 cmp r3, r2 - 800b688: d028 beq.n 800b6dc <_dtoa_r+0xaec> - 800b68a: 4649 mov r1, r9 - 800b68c: 2300 movs r3, #0 - 800b68e: 220a movs r2, #10 - 800b690: 4658 mov r0, fp - 800b692: f000 fd17 bl 800c0c4 <__multadd> - 800b696: 42af cmp r7, r5 - 800b698: 4681 mov r9, r0 - 800b69a: f04f 0300 mov.w r3, #0 - 800b69e: f04f 020a mov.w r2, #10 - 800b6a2: 4639 mov r1, r7 - 800b6a4: 4658 mov r0, fp - 800b6a6: d107 bne.n 800b6b8 <_dtoa_r+0xac8> - 800b6a8: f000 fd0c bl 800c0c4 <__multadd> - 800b6ac: 4607 mov r7, r0 - 800b6ae: 4605 mov r5, r0 - 800b6b0: 9b07 ldr r3, [sp, #28] - 800b6b2: 3301 adds r3, #1 - 800b6b4: 9307 str r3, [sp, #28] - 800b6b6: e774 b.n 800b5a2 <_dtoa_r+0x9b2> - 800b6b8: f000 fd04 bl 800c0c4 <__multadd> - 800b6bc: 4629 mov r1, r5 - 800b6be: 4607 mov r7, r0 - 800b6c0: 2300 movs r3, #0 - 800b6c2: 220a movs r2, #10 - 800b6c4: 4658 mov r0, fp - 800b6c6: f000 fcfd bl 800c0c4 <__multadd> - 800b6ca: 4605 mov r5, r0 - 800b6cc: e7f0 b.n 800b6b0 <_dtoa_r+0xac0> - 800b6ce: 9b08 ldr r3, [sp, #32] - 800b6d0: 2700 movs r7, #0 - 800b6d2: 2b00 cmp r3, #0 - 800b6d4: bfcc ite gt - 800b6d6: 461e movgt r6, r3 - 800b6d8: 2601 movle r6, #1 - 800b6da: 4456 add r6, sl - 800b6dc: 4649 mov r1, r9 - 800b6de: 2201 movs r2, #1 - 800b6e0: 4658 mov r0, fp - 800b6e2: f000 fe99 bl 800c418 <__lshift> - 800b6e6: 4621 mov r1, r4 - 800b6e8: 4681 mov r9, r0 - 800b6ea: f000 ff01 bl 800c4f0 <__mcmp> - 800b6ee: 2800 cmp r0, #0 - 800b6f0: dcb0 bgt.n 800b654 <_dtoa_r+0xa64> - 800b6f2: d102 bne.n 800b6fa <_dtoa_r+0xb0a> - 800b6f4: f018 0f01 tst.w r8, #1 - 800b6f8: d1ac bne.n 800b654 <_dtoa_r+0xa64> - 800b6fa: 4633 mov r3, r6 - 800b6fc: 461e mov r6, r3 - 800b6fe: f813 2d01 ldrb.w r2, [r3, #-1]! - 800b702: 2a30 cmp r2, #48 @ 0x30 - 800b704: d0fa beq.n 800b6fc <_dtoa_r+0xb0c> - 800b706: e5be b.n 800b286 <_dtoa_r+0x696> - 800b708: 459a cmp sl, r3 - 800b70a: d1a4 bne.n 800b656 <_dtoa_r+0xa66> - 800b70c: 9b04 ldr r3, [sp, #16] - 800b70e: 3301 adds r3, #1 - 800b710: 9304 str r3, [sp, #16] - 800b712: 2331 movs r3, #49 @ 0x31 - 800b714: f88a 3000 strb.w r3, [sl] - 800b718: e5b5 b.n 800b286 <_dtoa_r+0x696> - 800b71a: 9b24 ldr r3, [sp, #144] @ 0x90 - 800b71c: f8df a05c ldr.w sl, [pc, #92] @ 800b77c <_dtoa_r+0xb8c> - 800b720: b11b cbz r3, 800b72a <_dtoa_r+0xb3a> - 800b722: f10a 0308 add.w r3, sl, #8 - 800b726: 9a24 ldr r2, [sp, #144] @ 0x90 - 800b728: 6013 str r3, [r2, #0] - 800b72a: 4650 mov r0, sl - 800b72c: b017 add sp, #92 @ 0x5c - 800b72e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800b732: 9b20 ldr r3, [sp, #128] @ 0x80 - 800b734: 2b01 cmp r3, #1 - 800b736: f77f ae3d ble.w 800b3b4 <_dtoa_r+0x7c4> - 800b73a: 9b0e ldr r3, [sp, #56] @ 0x38 - 800b73c: 930a str r3, [sp, #40] @ 0x28 - 800b73e: 2001 movs r0, #1 - 800b740: e65b b.n 800b3fa <_dtoa_r+0x80a> - 800b742: 9b08 ldr r3, [sp, #32] - 800b744: 2b00 cmp r3, #0 - 800b746: f77f aed6 ble.w 800b4f6 <_dtoa_r+0x906> - 800b74a: 4656 mov r6, sl - 800b74c: 4621 mov r1, r4 - 800b74e: 4648 mov r0, r9 - 800b750: f7ff f9c6 bl 800aae0 - 800b754: f100 0830 add.w r8, r0, #48 @ 0x30 - 800b758: 9b08 ldr r3, [sp, #32] - 800b75a: f806 8b01 strb.w r8, [r6], #1 - 800b75e: eba6 020a sub.w r2, r6, sl - 800b762: 4293 cmp r3, r2 - 800b764: ddb3 ble.n 800b6ce <_dtoa_r+0xade> - 800b766: 4649 mov r1, r9 - 800b768: 2300 movs r3, #0 - 800b76a: 220a movs r2, #10 - 800b76c: 4658 mov r0, fp - 800b76e: f000 fca9 bl 800c0c4 <__multadd> - 800b772: 4681 mov r9, r0 - 800b774: e7ea b.n 800b74c <_dtoa_r+0xb5c> - 800b776: bf00 nop - 800b778: 0800e24f .word 0x0800e24f - 800b77c: 0800e1ea .word 0x0800e1ea - -0800b780 <_findenv_r>: - 800b780: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800b784: f8df a06c ldr.w sl, [pc, #108] @ 800b7f4 <_findenv_r+0x74> - 800b788: 4606 mov r6, r0 - 800b78a: 4689 mov r9, r1 - 800b78c: 4617 mov r7, r2 - 800b78e: f001 fa85 bl 800cc9c <__env_lock> - 800b792: f8da 4000 ldr.w r4, [sl] - 800b796: b134 cbz r4, 800b7a6 <_findenv_r+0x26> - 800b798: 464b mov r3, r9 - 800b79a: 4698 mov r8, r3 - 800b79c: f813 2b01 ldrb.w r2, [r3], #1 - 800b7a0: b13a cbz r2, 800b7b2 <_findenv_r+0x32> - 800b7a2: 2a3d cmp r2, #61 @ 0x3d - 800b7a4: d1f9 bne.n 800b79a <_findenv_r+0x1a> - 800b7a6: 4630 mov r0, r6 - 800b7a8: f001 fa7e bl 800cca8 <__env_unlock> - 800b7ac: 2000 movs r0, #0 - 800b7ae: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800b7b2: eba8 0809 sub.w r8, r8, r9 - 800b7b6: 46a3 mov fp, r4 - 800b7b8: f854 0b04 ldr.w r0, [r4], #4 - 800b7bc: 2800 cmp r0, #0 - 800b7be: d0f2 beq.n 800b7a6 <_findenv_r+0x26> - 800b7c0: 4642 mov r2, r8 - 800b7c2: 4649 mov r1, r9 - 800b7c4: f7fe fc4a bl 800a05c - 800b7c8: 2800 cmp r0, #0 - 800b7ca: d1f4 bne.n 800b7b6 <_findenv_r+0x36> - 800b7cc: f854 3c04 ldr.w r3, [r4, #-4] - 800b7d0: eb03 0508 add.w r5, r3, r8 - 800b7d4: f813 3008 ldrb.w r3, [r3, r8] - 800b7d8: 2b3d cmp r3, #61 @ 0x3d - 800b7da: d1ec bne.n 800b7b6 <_findenv_r+0x36> - 800b7dc: f8da 3000 ldr.w r3, [sl] - 800b7e0: 4630 mov r0, r6 - 800b7e2: ebab 0303 sub.w r3, fp, r3 - 800b7e6: 109b asrs r3, r3, #2 - 800b7e8: 603b str r3, [r7, #0] - 800b7ea: f001 fa5d bl 800cca8 <__env_unlock> - 800b7ee: 1c68 adds r0, r5, #1 - 800b7f0: e7dd b.n 800b7ae <_findenv_r+0x2e> - 800b7f2: bf00 nop - 800b7f4: 20000004 .word 0x20000004 - -0800b7f8 <_getenv_r>: - 800b7f8: b507 push {r0, r1, r2, lr} - 800b7fa: aa01 add r2, sp, #4 - 800b7fc: f7ff ffc0 bl 800b780 <_findenv_r> - 800b800: b003 add sp, #12 - 800b802: f85d fb04 ldr.w pc, [sp], #4 - -0800b806 <__ssputs_r>: - 800b806: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800b80a: 461f mov r7, r3 - 800b80c: 688e ldr r6, [r1, #8] - 800b80e: 4682 mov sl, r0 - 800b810: 42be cmp r6, r7 - 800b812: 460c mov r4, r1 - 800b814: 4690 mov r8, r2 - 800b816: 680b ldr r3, [r1, #0] - 800b818: d82d bhi.n 800b876 <__ssputs_r+0x70> - 800b81a: f9b1 200c ldrsh.w r2, [r1, #12] - 800b81e: f412 6f90 tst.w r2, #1152 @ 0x480 - 800b822: d026 beq.n 800b872 <__ssputs_r+0x6c> - 800b824: 6965 ldr r5, [r4, #20] - 800b826: 6909 ldr r1, [r1, #16] - 800b828: eb05 0545 add.w r5, r5, r5, lsl #1 - 800b82c: eba3 0901 sub.w r9, r3, r1 - 800b830: eb05 75d5 add.w r5, r5, r5, lsr #31 - 800b834: 1c7b adds r3, r7, #1 - 800b836: 444b add r3, r9 - 800b838: 106d asrs r5, r5, #1 - 800b83a: 429d cmp r5, r3 - 800b83c: bf38 it cc - 800b83e: 461d movcc r5, r3 - 800b840: 0553 lsls r3, r2, #21 - 800b842: d527 bpl.n 800b894 <__ssputs_r+0x8e> - 800b844: 4629 mov r1, r5 - 800b846: f000 faa7 bl 800bd98 <_malloc_r> - 800b84a: 4606 mov r6, r0 - 800b84c: b360 cbz r0, 800b8a8 <__ssputs_r+0xa2> - 800b84e: 464a mov r2, r9 - 800b850: 6921 ldr r1, [r4, #16] - 800b852: f7ff f910 bl 800aa76 - 800b856: 89a3 ldrh r3, [r4, #12] - 800b858: f423 6390 bic.w r3, r3, #1152 @ 0x480 - 800b85c: f043 0380 orr.w r3, r3, #128 @ 0x80 - 800b860: 81a3 strh r3, [r4, #12] - 800b862: 6126 str r6, [r4, #16] - 800b864: 444e add r6, r9 - 800b866: 6026 str r6, [r4, #0] - 800b868: 463e mov r6, r7 - 800b86a: 6165 str r5, [r4, #20] - 800b86c: eba5 0509 sub.w r5, r5, r9 - 800b870: 60a5 str r5, [r4, #8] - 800b872: 42be cmp r6, r7 - 800b874: d900 bls.n 800b878 <__ssputs_r+0x72> - 800b876: 463e mov r6, r7 - 800b878: 4632 mov r2, r6 - 800b87a: 4641 mov r1, r8 - 800b87c: 6820 ldr r0, [r4, #0] - 800b87e: f001 f95e bl 800cb3e - 800b882: 2000 movs r0, #0 - 800b884: 68a3 ldr r3, [r4, #8] - 800b886: 1b9b subs r3, r3, r6 - 800b888: 60a3 str r3, [r4, #8] - 800b88a: 6823 ldr r3, [r4, #0] - 800b88c: 4433 add r3, r6 - 800b88e: 6023 str r3, [r4, #0] - 800b890: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800b894: 462a mov r2, r5 - 800b896: f000 ffb5 bl 800c804 <_realloc_r> - 800b89a: 4606 mov r6, r0 - 800b89c: 2800 cmp r0, #0 - 800b89e: d1e0 bne.n 800b862 <__ssputs_r+0x5c> - 800b8a0: 4650 mov r0, sl - 800b8a2: 6921 ldr r1, [r4, #16] - 800b8a4: f001 fa06 bl 800ccb4 <_free_r> - 800b8a8: 230c movs r3, #12 - 800b8aa: f8ca 3000 str.w r3, [sl] - 800b8ae: 89a3 ldrh r3, [r4, #12] - 800b8b0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800b8b4: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800b8b8: 81a3 strh r3, [r4, #12] - 800b8ba: e7e9 b.n 800b890 <__ssputs_r+0x8a> - -0800b8bc <_svfiprintf_r>: - 800b8bc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800b8c0: 4698 mov r8, r3 - 800b8c2: 898b ldrh r3, [r1, #12] - 800b8c4: 4607 mov r7, r0 - 800b8c6: 061b lsls r3, r3, #24 - 800b8c8: 460d mov r5, r1 - 800b8ca: 4614 mov r4, r2 - 800b8cc: b09d sub sp, #116 @ 0x74 - 800b8ce: d510 bpl.n 800b8f2 <_svfiprintf_r+0x36> - 800b8d0: 690b ldr r3, [r1, #16] - 800b8d2: b973 cbnz r3, 800b8f2 <_svfiprintf_r+0x36> - 800b8d4: 2140 movs r1, #64 @ 0x40 - 800b8d6: f000 fa5f bl 800bd98 <_malloc_r> - 800b8da: 6028 str r0, [r5, #0] - 800b8dc: 6128 str r0, [r5, #16] - 800b8de: b930 cbnz r0, 800b8ee <_svfiprintf_r+0x32> - 800b8e0: 230c movs r3, #12 - 800b8e2: 603b str r3, [r7, #0] - 800b8e4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800b8e8: b01d add sp, #116 @ 0x74 - 800b8ea: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800b8ee: 2340 movs r3, #64 @ 0x40 - 800b8f0: 616b str r3, [r5, #20] - 800b8f2: 2300 movs r3, #0 - 800b8f4: 9309 str r3, [sp, #36] @ 0x24 - 800b8f6: 2320 movs r3, #32 - 800b8f8: f88d 3029 strb.w r3, [sp, #41] @ 0x29 - 800b8fc: 2330 movs r3, #48 @ 0x30 - 800b8fe: f04f 0901 mov.w r9, #1 - 800b902: f8cd 800c str.w r8, [sp, #12] - 800b906: f8df 8198 ldr.w r8, [pc, #408] @ 800baa0 <_svfiprintf_r+0x1e4> - 800b90a: f88d 302a strb.w r3, [sp, #42] @ 0x2a - 800b90e: 4623 mov r3, r4 - 800b910: 469a mov sl, r3 - 800b912: f813 2b01 ldrb.w r2, [r3], #1 - 800b916: b10a cbz r2, 800b91c <_svfiprintf_r+0x60> - 800b918: 2a25 cmp r2, #37 @ 0x25 - 800b91a: d1f9 bne.n 800b910 <_svfiprintf_r+0x54> - 800b91c: ebba 0b04 subs.w fp, sl, r4 - 800b920: d00b beq.n 800b93a <_svfiprintf_r+0x7e> - 800b922: 465b mov r3, fp - 800b924: 4622 mov r2, r4 - 800b926: 4629 mov r1, r5 - 800b928: 4638 mov r0, r7 - 800b92a: f7ff ff6c bl 800b806 <__ssputs_r> - 800b92e: 3001 adds r0, #1 - 800b930: f000 80a7 beq.w 800ba82 <_svfiprintf_r+0x1c6> - 800b934: 9a09 ldr r2, [sp, #36] @ 0x24 - 800b936: 445a add r2, fp - 800b938: 9209 str r2, [sp, #36] @ 0x24 - 800b93a: f89a 3000 ldrb.w r3, [sl] - 800b93e: 2b00 cmp r3, #0 - 800b940: f000 809f beq.w 800ba82 <_svfiprintf_r+0x1c6> - 800b944: 2300 movs r3, #0 - 800b946: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800b94a: e9cd 2305 strd r2, r3, [sp, #20] - 800b94e: f10a 0a01 add.w sl, sl, #1 - 800b952: 9304 str r3, [sp, #16] - 800b954: 9307 str r3, [sp, #28] - 800b956: f88d 3053 strb.w r3, [sp, #83] @ 0x53 - 800b95a: 931a str r3, [sp, #104] @ 0x68 - 800b95c: 4654 mov r4, sl - 800b95e: 2205 movs r2, #5 - 800b960: f814 1b01 ldrb.w r1, [r4], #1 - 800b964: 484e ldr r0, [pc, #312] @ (800baa0 <_svfiprintf_r+0x1e4>) - 800b966: f7ff f878 bl 800aa5a - 800b96a: 9a04 ldr r2, [sp, #16] - 800b96c: b9d8 cbnz r0, 800b9a6 <_svfiprintf_r+0xea> - 800b96e: 06d0 lsls r0, r2, #27 - 800b970: bf44 itt mi - 800b972: 2320 movmi r3, #32 - 800b974: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 - 800b978: 0711 lsls r1, r2, #28 - 800b97a: bf44 itt mi - 800b97c: 232b movmi r3, #43 @ 0x2b - 800b97e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 - 800b982: f89a 3000 ldrb.w r3, [sl] - 800b986: 2b2a cmp r3, #42 @ 0x2a - 800b988: d015 beq.n 800b9b6 <_svfiprintf_r+0xfa> - 800b98a: 4654 mov r4, sl - 800b98c: 2000 movs r0, #0 - 800b98e: f04f 0c0a mov.w ip, #10 - 800b992: 9a07 ldr r2, [sp, #28] - 800b994: 4621 mov r1, r4 - 800b996: f811 3b01 ldrb.w r3, [r1], #1 - 800b99a: 3b30 subs r3, #48 @ 0x30 - 800b99c: 2b09 cmp r3, #9 - 800b99e: d94b bls.n 800ba38 <_svfiprintf_r+0x17c> - 800b9a0: b1b0 cbz r0, 800b9d0 <_svfiprintf_r+0x114> - 800b9a2: 9207 str r2, [sp, #28] - 800b9a4: e014 b.n 800b9d0 <_svfiprintf_r+0x114> - 800b9a6: eba0 0308 sub.w r3, r0, r8 - 800b9aa: fa09 f303 lsl.w r3, r9, r3 - 800b9ae: 4313 orrs r3, r2 - 800b9b0: 46a2 mov sl, r4 - 800b9b2: 9304 str r3, [sp, #16] - 800b9b4: e7d2 b.n 800b95c <_svfiprintf_r+0xa0> - 800b9b6: 9b03 ldr r3, [sp, #12] - 800b9b8: 1d19 adds r1, r3, #4 - 800b9ba: 681b ldr r3, [r3, #0] - 800b9bc: 9103 str r1, [sp, #12] - 800b9be: 2b00 cmp r3, #0 - 800b9c0: bfbb ittet lt - 800b9c2: 425b neglt r3, r3 - 800b9c4: f042 0202 orrlt.w r2, r2, #2 - 800b9c8: 9307 strge r3, [sp, #28] - 800b9ca: 9307 strlt r3, [sp, #28] - 800b9cc: bfb8 it lt - 800b9ce: 9204 strlt r2, [sp, #16] - 800b9d0: 7823 ldrb r3, [r4, #0] - 800b9d2: 2b2e cmp r3, #46 @ 0x2e - 800b9d4: d10a bne.n 800b9ec <_svfiprintf_r+0x130> - 800b9d6: 7863 ldrb r3, [r4, #1] - 800b9d8: 2b2a cmp r3, #42 @ 0x2a - 800b9da: d132 bne.n 800ba42 <_svfiprintf_r+0x186> - 800b9dc: 9b03 ldr r3, [sp, #12] - 800b9de: 3402 adds r4, #2 - 800b9e0: 1d1a adds r2, r3, #4 - 800b9e2: 681b ldr r3, [r3, #0] - 800b9e4: 9203 str r2, [sp, #12] - 800b9e6: ea43 73e3 orr.w r3, r3, r3, asr #31 - 800b9ea: 9305 str r3, [sp, #20] - 800b9ec: f8df a0b4 ldr.w sl, [pc, #180] @ 800baa4 <_svfiprintf_r+0x1e8> - 800b9f0: 2203 movs r2, #3 - 800b9f2: 4650 mov r0, sl - 800b9f4: 7821 ldrb r1, [r4, #0] - 800b9f6: f7ff f830 bl 800aa5a - 800b9fa: b138 cbz r0, 800ba0c <_svfiprintf_r+0x150> - 800b9fc: 2240 movs r2, #64 @ 0x40 - 800b9fe: 9b04 ldr r3, [sp, #16] - 800ba00: eba0 000a sub.w r0, r0, sl - 800ba04: 4082 lsls r2, r0 - 800ba06: 4313 orrs r3, r2 - 800ba08: 3401 adds r4, #1 - 800ba0a: 9304 str r3, [sp, #16] - 800ba0c: f814 1b01 ldrb.w r1, [r4], #1 - 800ba10: 2206 movs r2, #6 - 800ba12: 4825 ldr r0, [pc, #148] @ (800baa8 <_svfiprintf_r+0x1ec>) - 800ba14: f88d 1028 strb.w r1, [sp, #40] @ 0x28 - 800ba18: f7ff f81f bl 800aa5a - 800ba1c: 2800 cmp r0, #0 - 800ba1e: d036 beq.n 800ba8e <_svfiprintf_r+0x1d2> - 800ba20: 4b22 ldr r3, [pc, #136] @ (800baac <_svfiprintf_r+0x1f0>) - 800ba22: bb1b cbnz r3, 800ba6c <_svfiprintf_r+0x1b0> - 800ba24: 9b03 ldr r3, [sp, #12] - 800ba26: 3307 adds r3, #7 - 800ba28: f023 0307 bic.w r3, r3, #7 - 800ba2c: 3308 adds r3, #8 - 800ba2e: 9303 str r3, [sp, #12] - 800ba30: 9b09 ldr r3, [sp, #36] @ 0x24 - 800ba32: 4433 add r3, r6 - 800ba34: 9309 str r3, [sp, #36] @ 0x24 - 800ba36: e76a b.n 800b90e <_svfiprintf_r+0x52> - 800ba38: 460c mov r4, r1 - 800ba3a: 2001 movs r0, #1 - 800ba3c: fb0c 3202 mla r2, ip, r2, r3 - 800ba40: e7a8 b.n 800b994 <_svfiprintf_r+0xd8> - 800ba42: 2300 movs r3, #0 - 800ba44: f04f 0c0a mov.w ip, #10 - 800ba48: 4619 mov r1, r3 - 800ba4a: 3401 adds r4, #1 - 800ba4c: 9305 str r3, [sp, #20] - 800ba4e: 4620 mov r0, r4 - 800ba50: f810 2b01 ldrb.w r2, [r0], #1 - 800ba54: 3a30 subs r2, #48 @ 0x30 - 800ba56: 2a09 cmp r2, #9 - 800ba58: d903 bls.n 800ba62 <_svfiprintf_r+0x1a6> - 800ba5a: 2b00 cmp r3, #0 - 800ba5c: d0c6 beq.n 800b9ec <_svfiprintf_r+0x130> - 800ba5e: 9105 str r1, [sp, #20] - 800ba60: e7c4 b.n 800b9ec <_svfiprintf_r+0x130> - 800ba62: 4604 mov r4, r0 - 800ba64: 2301 movs r3, #1 - 800ba66: fb0c 2101 mla r1, ip, r1, r2 - 800ba6a: e7f0 b.n 800ba4e <_svfiprintf_r+0x192> - 800ba6c: ab03 add r3, sp, #12 - 800ba6e: 9300 str r3, [sp, #0] - 800ba70: 462a mov r2, r5 - 800ba72: 4638 mov r0, r7 - 800ba74: 4b0e ldr r3, [pc, #56] @ (800bab0 <_svfiprintf_r+0x1f4>) - 800ba76: a904 add r1, sp, #16 - 800ba78: f7fd fd92 bl 80095a0 <_printf_float> - 800ba7c: 1c42 adds r2, r0, #1 - 800ba7e: 4606 mov r6, r0 - 800ba80: d1d6 bne.n 800ba30 <_svfiprintf_r+0x174> - 800ba82: 89ab ldrh r3, [r5, #12] - 800ba84: 065b lsls r3, r3, #25 - 800ba86: f53f af2d bmi.w 800b8e4 <_svfiprintf_r+0x28> - 800ba8a: 9809 ldr r0, [sp, #36] @ 0x24 - 800ba8c: e72c b.n 800b8e8 <_svfiprintf_r+0x2c> - 800ba8e: ab03 add r3, sp, #12 - 800ba90: 9300 str r3, [sp, #0] - 800ba92: 462a mov r2, r5 - 800ba94: 4638 mov r0, r7 - 800ba96: 4b06 ldr r3, [pc, #24] @ (800bab0 <_svfiprintf_r+0x1f4>) - 800ba98: a904 add r1, sp, #16 - 800ba9a: f7fe f81f bl 8009adc <_printf_i> - 800ba9e: e7ed b.n 800ba7c <_svfiprintf_r+0x1c0> - 800baa0: 0800e260 .word 0x0800e260 - 800baa4: 0800e266 .word 0x0800e266 - 800baa8: 0800e26a .word 0x0800e26a - 800baac: 080095a1 .word 0x080095a1 - 800bab0: 0800b807 .word 0x0800b807 - -0800bab4 <__sfputc_r>: - 800bab4: 6893 ldr r3, [r2, #8] - 800bab6: b410 push {r4} - 800bab8: 3b01 subs r3, #1 - 800baba: 2b00 cmp r3, #0 - 800babc: 6093 str r3, [r2, #8] - 800babe: da07 bge.n 800bad0 <__sfputc_r+0x1c> - 800bac0: 6994 ldr r4, [r2, #24] - 800bac2: 42a3 cmp r3, r4 - 800bac4: db01 blt.n 800baca <__sfputc_r+0x16> - 800bac6: 290a cmp r1, #10 - 800bac8: d102 bne.n 800bad0 <__sfputc_r+0x1c> - 800baca: bc10 pop {r4} - 800bacc: f000 bf42 b.w 800c954 <__swbuf_r> - 800bad0: 6813 ldr r3, [r2, #0] - 800bad2: 1c58 adds r0, r3, #1 - 800bad4: 6010 str r0, [r2, #0] - 800bad6: 7019 strb r1, [r3, #0] - 800bad8: 4608 mov r0, r1 - 800bada: bc10 pop {r4} - 800badc: 4770 bx lr - -0800bade <__sfputs_r>: - 800bade: b5f8 push {r3, r4, r5, r6, r7, lr} - 800bae0: 4606 mov r6, r0 - 800bae2: 460f mov r7, r1 - 800bae4: 4614 mov r4, r2 - 800bae6: 18d5 adds r5, r2, r3 - 800bae8: 42ac cmp r4, r5 - 800baea: d101 bne.n 800baf0 <__sfputs_r+0x12> - 800baec: 2000 movs r0, #0 - 800baee: e007 b.n 800bb00 <__sfputs_r+0x22> - 800baf0: 463a mov r2, r7 - 800baf2: 4630 mov r0, r6 - 800baf4: f814 1b01 ldrb.w r1, [r4], #1 - 800baf8: f7ff ffdc bl 800bab4 <__sfputc_r> - 800bafc: 1c43 adds r3, r0, #1 - 800bafe: d1f3 bne.n 800bae8 <__sfputs_r+0xa> - 800bb00: bdf8 pop {r3, r4, r5, r6, r7, pc} - ... - -0800bb04 <_vfiprintf_r>: - 800bb04: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800bb08: 460d mov r5, r1 - 800bb0a: 4614 mov r4, r2 - 800bb0c: 4698 mov r8, r3 - 800bb0e: 4606 mov r6, r0 - 800bb10: b09d sub sp, #116 @ 0x74 - 800bb12: b118 cbz r0, 800bb1c <_vfiprintf_r+0x18> - 800bb14: 6a03 ldr r3, [r0, #32] - 800bb16: b90b cbnz r3, 800bb1c <_vfiprintf_r+0x18> - 800bb18: f7fe f9c0 bl 8009e9c <__sinit> - 800bb1c: 6e6b ldr r3, [r5, #100] @ 0x64 - 800bb1e: 07d9 lsls r1, r3, #31 - 800bb20: d405 bmi.n 800bb2e <_vfiprintf_r+0x2a> - 800bb22: 89ab ldrh r3, [r5, #12] - 800bb24: 059a lsls r2, r3, #22 - 800bb26: d402 bmi.n 800bb2e <_vfiprintf_r+0x2a> - 800bb28: 6da8 ldr r0, [r5, #88] @ 0x58 - 800bb2a: f7fe ff93 bl 800aa54 <__retarget_lock_acquire_recursive> - 800bb2e: 89ab ldrh r3, [r5, #12] - 800bb30: 071b lsls r3, r3, #28 - 800bb32: d501 bpl.n 800bb38 <_vfiprintf_r+0x34> - 800bb34: 692b ldr r3, [r5, #16] - 800bb36: b99b cbnz r3, 800bb60 <_vfiprintf_r+0x5c> - 800bb38: 4629 mov r1, r5 - 800bb3a: 4630 mov r0, r6 - 800bb3c: f000 ff48 bl 800c9d0 <__swsetup_r> - 800bb40: b170 cbz r0, 800bb60 <_vfiprintf_r+0x5c> - 800bb42: 6e6b ldr r3, [r5, #100] @ 0x64 - 800bb44: 07dc lsls r4, r3, #31 - 800bb46: d504 bpl.n 800bb52 <_vfiprintf_r+0x4e> - 800bb48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800bb4c: b01d add sp, #116 @ 0x74 - 800bb4e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800bb52: 89ab ldrh r3, [r5, #12] - 800bb54: 0598 lsls r0, r3, #22 - 800bb56: d4f7 bmi.n 800bb48 <_vfiprintf_r+0x44> - 800bb58: 6da8 ldr r0, [r5, #88] @ 0x58 - 800bb5a: f7fe ff7d bl 800aa58 <__retarget_lock_release_recursive> - 800bb5e: e7f3 b.n 800bb48 <_vfiprintf_r+0x44> - 800bb60: 2300 movs r3, #0 - 800bb62: 9309 str r3, [sp, #36] @ 0x24 - 800bb64: 2320 movs r3, #32 - 800bb66: f88d 3029 strb.w r3, [sp, #41] @ 0x29 - 800bb6a: 2330 movs r3, #48 @ 0x30 - 800bb6c: f04f 0901 mov.w r9, #1 - 800bb70: f8cd 800c str.w r8, [sp, #12] - 800bb74: f8df 81a8 ldr.w r8, [pc, #424] @ 800bd20 <_vfiprintf_r+0x21c> - 800bb78: f88d 302a strb.w r3, [sp, #42] @ 0x2a - 800bb7c: 4623 mov r3, r4 - 800bb7e: 469a mov sl, r3 - 800bb80: f813 2b01 ldrb.w r2, [r3], #1 - 800bb84: b10a cbz r2, 800bb8a <_vfiprintf_r+0x86> - 800bb86: 2a25 cmp r2, #37 @ 0x25 - 800bb88: d1f9 bne.n 800bb7e <_vfiprintf_r+0x7a> - 800bb8a: ebba 0b04 subs.w fp, sl, r4 - 800bb8e: d00b beq.n 800bba8 <_vfiprintf_r+0xa4> - 800bb90: 465b mov r3, fp - 800bb92: 4622 mov r2, r4 - 800bb94: 4629 mov r1, r5 - 800bb96: 4630 mov r0, r6 - 800bb98: f7ff ffa1 bl 800bade <__sfputs_r> - 800bb9c: 3001 adds r0, #1 - 800bb9e: f000 80a7 beq.w 800bcf0 <_vfiprintf_r+0x1ec> - 800bba2: 9a09 ldr r2, [sp, #36] @ 0x24 - 800bba4: 445a add r2, fp - 800bba6: 9209 str r2, [sp, #36] @ 0x24 - 800bba8: f89a 3000 ldrb.w r3, [sl] - 800bbac: 2b00 cmp r3, #0 - 800bbae: f000 809f beq.w 800bcf0 <_vfiprintf_r+0x1ec> - 800bbb2: 2300 movs r3, #0 - 800bbb4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800bbb8: e9cd 2305 strd r2, r3, [sp, #20] - 800bbbc: f10a 0a01 add.w sl, sl, #1 - 800bbc0: 9304 str r3, [sp, #16] - 800bbc2: 9307 str r3, [sp, #28] - 800bbc4: f88d 3053 strb.w r3, [sp, #83] @ 0x53 - 800bbc8: 931a str r3, [sp, #104] @ 0x68 - 800bbca: 4654 mov r4, sl - 800bbcc: 2205 movs r2, #5 - 800bbce: f814 1b01 ldrb.w r1, [r4], #1 - 800bbd2: 4853 ldr r0, [pc, #332] @ (800bd20 <_vfiprintf_r+0x21c>) - 800bbd4: f7fe ff41 bl 800aa5a - 800bbd8: 9a04 ldr r2, [sp, #16] - 800bbda: b9d8 cbnz r0, 800bc14 <_vfiprintf_r+0x110> - 800bbdc: 06d1 lsls r1, r2, #27 - 800bbde: bf44 itt mi - 800bbe0: 2320 movmi r3, #32 - 800bbe2: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 - 800bbe6: 0713 lsls r3, r2, #28 - 800bbe8: bf44 itt mi - 800bbea: 232b movmi r3, #43 @ 0x2b - 800bbec: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 - 800bbf0: f89a 3000 ldrb.w r3, [sl] - 800bbf4: 2b2a cmp r3, #42 @ 0x2a - 800bbf6: d015 beq.n 800bc24 <_vfiprintf_r+0x120> - 800bbf8: 4654 mov r4, sl - 800bbfa: 2000 movs r0, #0 - 800bbfc: f04f 0c0a mov.w ip, #10 - 800bc00: 9a07 ldr r2, [sp, #28] - 800bc02: 4621 mov r1, r4 - 800bc04: f811 3b01 ldrb.w r3, [r1], #1 - 800bc08: 3b30 subs r3, #48 @ 0x30 - 800bc0a: 2b09 cmp r3, #9 - 800bc0c: d94b bls.n 800bca6 <_vfiprintf_r+0x1a2> - 800bc0e: b1b0 cbz r0, 800bc3e <_vfiprintf_r+0x13a> - 800bc10: 9207 str r2, [sp, #28] - 800bc12: e014 b.n 800bc3e <_vfiprintf_r+0x13a> - 800bc14: eba0 0308 sub.w r3, r0, r8 - 800bc18: fa09 f303 lsl.w r3, r9, r3 - 800bc1c: 4313 orrs r3, r2 - 800bc1e: 46a2 mov sl, r4 - 800bc20: 9304 str r3, [sp, #16] - 800bc22: e7d2 b.n 800bbca <_vfiprintf_r+0xc6> - 800bc24: 9b03 ldr r3, [sp, #12] - 800bc26: 1d19 adds r1, r3, #4 - 800bc28: 681b ldr r3, [r3, #0] - 800bc2a: 9103 str r1, [sp, #12] - 800bc2c: 2b00 cmp r3, #0 - 800bc2e: bfbb ittet lt - 800bc30: 425b neglt r3, r3 - 800bc32: f042 0202 orrlt.w r2, r2, #2 - 800bc36: 9307 strge r3, [sp, #28] - 800bc38: 9307 strlt r3, [sp, #28] - 800bc3a: bfb8 it lt - 800bc3c: 9204 strlt r2, [sp, #16] - 800bc3e: 7823 ldrb r3, [r4, #0] - 800bc40: 2b2e cmp r3, #46 @ 0x2e - 800bc42: d10a bne.n 800bc5a <_vfiprintf_r+0x156> - 800bc44: 7863 ldrb r3, [r4, #1] - 800bc46: 2b2a cmp r3, #42 @ 0x2a - 800bc48: d132 bne.n 800bcb0 <_vfiprintf_r+0x1ac> - 800bc4a: 9b03 ldr r3, [sp, #12] - 800bc4c: 3402 adds r4, #2 - 800bc4e: 1d1a adds r2, r3, #4 - 800bc50: 681b ldr r3, [r3, #0] - 800bc52: 9203 str r2, [sp, #12] - 800bc54: ea43 73e3 orr.w r3, r3, r3, asr #31 - 800bc58: 9305 str r3, [sp, #20] - 800bc5a: f8df a0c8 ldr.w sl, [pc, #200] @ 800bd24 <_vfiprintf_r+0x220> - 800bc5e: 2203 movs r2, #3 - 800bc60: 4650 mov r0, sl - 800bc62: 7821 ldrb r1, [r4, #0] - 800bc64: f7fe fef9 bl 800aa5a - 800bc68: b138 cbz r0, 800bc7a <_vfiprintf_r+0x176> - 800bc6a: 2240 movs r2, #64 @ 0x40 - 800bc6c: 9b04 ldr r3, [sp, #16] - 800bc6e: eba0 000a sub.w r0, r0, sl - 800bc72: 4082 lsls r2, r0 - 800bc74: 4313 orrs r3, r2 - 800bc76: 3401 adds r4, #1 - 800bc78: 9304 str r3, [sp, #16] - 800bc7a: f814 1b01 ldrb.w r1, [r4], #1 - 800bc7e: 2206 movs r2, #6 - 800bc80: 4829 ldr r0, [pc, #164] @ (800bd28 <_vfiprintf_r+0x224>) - 800bc82: f88d 1028 strb.w r1, [sp, #40] @ 0x28 - 800bc86: f7fe fee8 bl 800aa5a - 800bc8a: 2800 cmp r0, #0 - 800bc8c: d03f beq.n 800bd0e <_vfiprintf_r+0x20a> - 800bc8e: 4b27 ldr r3, [pc, #156] @ (800bd2c <_vfiprintf_r+0x228>) - 800bc90: bb1b cbnz r3, 800bcda <_vfiprintf_r+0x1d6> - 800bc92: 9b03 ldr r3, [sp, #12] - 800bc94: 3307 adds r3, #7 - 800bc96: f023 0307 bic.w r3, r3, #7 - 800bc9a: 3308 adds r3, #8 - 800bc9c: 9303 str r3, [sp, #12] - 800bc9e: 9b09 ldr r3, [sp, #36] @ 0x24 - 800bca0: 443b add r3, r7 - 800bca2: 9309 str r3, [sp, #36] @ 0x24 - 800bca4: e76a b.n 800bb7c <_vfiprintf_r+0x78> - 800bca6: 460c mov r4, r1 - 800bca8: 2001 movs r0, #1 - 800bcaa: fb0c 3202 mla r2, ip, r2, r3 - 800bcae: e7a8 b.n 800bc02 <_vfiprintf_r+0xfe> - 800bcb0: 2300 movs r3, #0 - 800bcb2: f04f 0c0a mov.w ip, #10 - 800bcb6: 4619 mov r1, r3 - 800bcb8: 3401 adds r4, #1 - 800bcba: 9305 str r3, [sp, #20] - 800bcbc: 4620 mov r0, r4 - 800bcbe: f810 2b01 ldrb.w r2, [r0], #1 - 800bcc2: 3a30 subs r2, #48 @ 0x30 - 800bcc4: 2a09 cmp r2, #9 - 800bcc6: d903 bls.n 800bcd0 <_vfiprintf_r+0x1cc> - 800bcc8: 2b00 cmp r3, #0 - 800bcca: d0c6 beq.n 800bc5a <_vfiprintf_r+0x156> - 800bccc: 9105 str r1, [sp, #20] - 800bcce: e7c4 b.n 800bc5a <_vfiprintf_r+0x156> - 800bcd0: 4604 mov r4, r0 - 800bcd2: 2301 movs r3, #1 - 800bcd4: fb0c 2101 mla r1, ip, r1, r2 - 800bcd8: e7f0 b.n 800bcbc <_vfiprintf_r+0x1b8> - 800bcda: ab03 add r3, sp, #12 - 800bcdc: 9300 str r3, [sp, #0] - 800bcde: 462a mov r2, r5 - 800bce0: 4630 mov r0, r6 - 800bce2: 4b13 ldr r3, [pc, #76] @ (800bd30 <_vfiprintf_r+0x22c>) - 800bce4: a904 add r1, sp, #16 - 800bce6: f7fd fc5b bl 80095a0 <_printf_float> - 800bcea: 4607 mov r7, r0 - 800bcec: 1c78 adds r0, r7, #1 - 800bcee: d1d6 bne.n 800bc9e <_vfiprintf_r+0x19a> - 800bcf0: 6e6b ldr r3, [r5, #100] @ 0x64 - 800bcf2: 07d9 lsls r1, r3, #31 - 800bcf4: d405 bmi.n 800bd02 <_vfiprintf_r+0x1fe> - 800bcf6: 89ab ldrh r3, [r5, #12] - 800bcf8: 059a lsls r2, r3, #22 - 800bcfa: d402 bmi.n 800bd02 <_vfiprintf_r+0x1fe> - 800bcfc: 6da8 ldr r0, [r5, #88] @ 0x58 - 800bcfe: f7fe feab bl 800aa58 <__retarget_lock_release_recursive> - 800bd02: 89ab ldrh r3, [r5, #12] - 800bd04: 065b lsls r3, r3, #25 - 800bd06: f53f af1f bmi.w 800bb48 <_vfiprintf_r+0x44> - 800bd0a: 9809 ldr r0, [sp, #36] @ 0x24 - 800bd0c: e71e b.n 800bb4c <_vfiprintf_r+0x48> - 800bd0e: ab03 add r3, sp, #12 - 800bd10: 9300 str r3, [sp, #0] - 800bd12: 462a mov r2, r5 - 800bd14: 4630 mov r0, r6 - 800bd16: 4b06 ldr r3, [pc, #24] @ (800bd30 <_vfiprintf_r+0x22c>) - 800bd18: a904 add r1, sp, #16 - 800bd1a: f7fd fedf bl 8009adc <_printf_i> - 800bd1e: e7e4 b.n 800bcea <_vfiprintf_r+0x1e6> - 800bd20: 0800e260 .word 0x0800e260 - 800bd24: 0800e266 .word 0x0800e266 - 800bd28: 0800e26a .word 0x0800e26a - 800bd2c: 080095a1 .word 0x080095a1 - 800bd30: 0800badf .word 0x0800badf - -0800bd34 : - 800bd34: 4b02 ldr r3, [pc, #8] @ (800bd40 ) - 800bd36: 4601 mov r1, r0 - 800bd38: 6818 ldr r0, [r3, #0] - 800bd3a: f000 b82d b.w 800bd98 <_malloc_r> - 800bd3e: bf00 nop - 800bd40: 20000028 .word 0x20000028 - -0800bd44 : - 800bd44: 4b02 ldr r3, [pc, #8] @ (800bd50 ) - 800bd46: 4601 mov r1, r0 - 800bd48: 6818 ldr r0, [r3, #0] - 800bd4a: f000 bfb3 b.w 800ccb4 <_free_r> - 800bd4e: bf00 nop - 800bd50: 20000028 .word 0x20000028 - -0800bd54 : - 800bd54: b570 push {r4, r5, r6, lr} - 800bd56: 4e0f ldr r6, [pc, #60] @ (800bd94 ) - 800bd58: 460c mov r4, r1 - 800bd5a: 6831 ldr r1, [r6, #0] - 800bd5c: 4605 mov r5, r0 - 800bd5e: b911 cbnz r1, 800bd66 - 800bd60: f000 ff5e bl 800cc20 <_sbrk_r> - 800bd64: 6030 str r0, [r6, #0] - 800bd66: 4621 mov r1, r4 - 800bd68: 4628 mov r0, r5 - 800bd6a: f000 ff59 bl 800cc20 <_sbrk_r> - 800bd6e: 1c43 adds r3, r0, #1 - 800bd70: d103 bne.n 800bd7a - 800bd72: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff - 800bd76: 4620 mov r0, r4 - 800bd78: bd70 pop {r4, r5, r6, pc} - 800bd7a: 1cc4 adds r4, r0, #3 - 800bd7c: f024 0403 bic.w r4, r4, #3 - 800bd80: 42a0 cmp r0, r4 - 800bd82: d0f8 beq.n 800bd76 - 800bd84: 1a21 subs r1, r4, r0 - 800bd86: 4628 mov r0, r5 - 800bd88: f000 ff4a bl 800cc20 <_sbrk_r> - 800bd8c: 3001 adds r0, #1 - 800bd8e: d1f2 bne.n 800bd76 - 800bd90: e7ef b.n 800bd72 - 800bd92: bf00 nop - 800bd94: 20003500 .word 0x20003500 - -0800bd98 <_malloc_r>: - 800bd98: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 800bd9c: 1ccd adds r5, r1, #3 - 800bd9e: f025 0503 bic.w r5, r5, #3 - 800bda2: 3508 adds r5, #8 - 800bda4: 2d0c cmp r5, #12 - 800bda6: bf38 it cc - 800bda8: 250c movcc r5, #12 - 800bdaa: 2d00 cmp r5, #0 - 800bdac: 4606 mov r6, r0 - 800bdae: db01 blt.n 800bdb4 <_malloc_r+0x1c> - 800bdb0: 42a9 cmp r1, r5 - 800bdb2: d904 bls.n 800bdbe <_malloc_r+0x26> - 800bdb4: 230c movs r3, #12 - 800bdb6: 6033 str r3, [r6, #0] - 800bdb8: 2000 movs r0, #0 - 800bdba: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 800bdbe: f8df 80d4 ldr.w r8, [pc, #212] @ 800be94 <_malloc_r+0xfc> - 800bdc2: f000 f911 bl 800bfe8 <__malloc_lock> - 800bdc6: f8d8 3000 ldr.w r3, [r8] - 800bdca: 461c mov r4, r3 - 800bdcc: bb44 cbnz r4, 800be20 <_malloc_r+0x88> - 800bdce: 4629 mov r1, r5 - 800bdd0: 4630 mov r0, r6 - 800bdd2: f7ff ffbf bl 800bd54 - 800bdd6: 1c43 adds r3, r0, #1 - 800bdd8: 4604 mov r4, r0 - 800bdda: d158 bne.n 800be8e <_malloc_r+0xf6> - 800bddc: f8d8 4000 ldr.w r4, [r8] - 800bde0: 4627 mov r7, r4 - 800bde2: 2f00 cmp r7, #0 - 800bde4: d143 bne.n 800be6e <_malloc_r+0xd6> - 800bde6: 2c00 cmp r4, #0 - 800bde8: d04b beq.n 800be82 <_malloc_r+0xea> - 800bdea: 6823 ldr r3, [r4, #0] - 800bdec: 4639 mov r1, r7 - 800bdee: 4630 mov r0, r6 - 800bdf0: eb04 0903 add.w r9, r4, r3 - 800bdf4: f000 ff14 bl 800cc20 <_sbrk_r> - 800bdf8: 4581 cmp r9, r0 - 800bdfa: d142 bne.n 800be82 <_malloc_r+0xea> - 800bdfc: 6821 ldr r1, [r4, #0] - 800bdfe: 4630 mov r0, r6 - 800be00: 1a6d subs r5, r5, r1 - 800be02: 4629 mov r1, r5 - 800be04: f7ff ffa6 bl 800bd54 - 800be08: 3001 adds r0, #1 - 800be0a: d03a beq.n 800be82 <_malloc_r+0xea> - 800be0c: 6823 ldr r3, [r4, #0] - 800be0e: 442b add r3, r5 - 800be10: 6023 str r3, [r4, #0] - 800be12: f8d8 3000 ldr.w r3, [r8] - 800be16: 685a ldr r2, [r3, #4] - 800be18: bb62 cbnz r2, 800be74 <_malloc_r+0xdc> - 800be1a: f8c8 7000 str.w r7, [r8] - 800be1e: e00f b.n 800be40 <_malloc_r+0xa8> - 800be20: 6822 ldr r2, [r4, #0] - 800be22: 1b52 subs r2, r2, r5 - 800be24: d420 bmi.n 800be68 <_malloc_r+0xd0> - 800be26: 2a0b cmp r2, #11 - 800be28: d917 bls.n 800be5a <_malloc_r+0xc2> - 800be2a: 1961 adds r1, r4, r5 - 800be2c: 42a3 cmp r3, r4 - 800be2e: 6025 str r5, [r4, #0] - 800be30: bf18 it ne - 800be32: 6059 strne r1, [r3, #4] - 800be34: 6863 ldr r3, [r4, #4] - 800be36: bf08 it eq - 800be38: f8c8 1000 streq.w r1, [r8] - 800be3c: 5162 str r2, [r4, r5] - 800be3e: 604b str r3, [r1, #4] - 800be40: 4630 mov r0, r6 - 800be42: f000 f8d7 bl 800bff4 <__malloc_unlock> - 800be46: f104 000b add.w r0, r4, #11 - 800be4a: 1d23 adds r3, r4, #4 - 800be4c: f020 0007 bic.w r0, r0, #7 - 800be50: 1ac2 subs r2, r0, r3 - 800be52: bf1c itt ne - 800be54: 1a1b subne r3, r3, r0 - 800be56: 50a3 strne r3, [r4, r2] - 800be58: e7af b.n 800bdba <_malloc_r+0x22> - 800be5a: 6862 ldr r2, [r4, #4] - 800be5c: 42a3 cmp r3, r4 - 800be5e: bf0c ite eq - 800be60: f8c8 2000 streq.w r2, [r8] - 800be64: 605a strne r2, [r3, #4] - 800be66: e7eb b.n 800be40 <_malloc_r+0xa8> - 800be68: 4623 mov r3, r4 - 800be6a: 6864 ldr r4, [r4, #4] - 800be6c: e7ae b.n 800bdcc <_malloc_r+0x34> - 800be6e: 463c mov r4, r7 - 800be70: 687f ldr r7, [r7, #4] - 800be72: e7b6 b.n 800bde2 <_malloc_r+0x4a> - 800be74: 461a mov r2, r3 - 800be76: 685b ldr r3, [r3, #4] - 800be78: 42a3 cmp r3, r4 - 800be7a: d1fb bne.n 800be74 <_malloc_r+0xdc> - 800be7c: 2300 movs r3, #0 - 800be7e: 6053 str r3, [r2, #4] - 800be80: e7de b.n 800be40 <_malloc_r+0xa8> - 800be82: 230c movs r3, #12 - 800be84: 4630 mov r0, r6 - 800be86: 6033 str r3, [r6, #0] - 800be88: f000 f8b4 bl 800bff4 <__malloc_unlock> - 800be8c: e794 b.n 800bdb8 <_malloc_r+0x20> - 800be8e: 6005 str r5, [r0, #0] - 800be90: e7d6 b.n 800be40 <_malloc_r+0xa8> - 800be92: bf00 nop - 800be94: 20003504 .word 0x20003504 - -0800be98 <__sflush_r>: - 800be98: f9b1 200c ldrsh.w r2, [r1, #12] - 800be9c: b5f8 push {r3, r4, r5, r6, r7, lr} - 800be9e: 0716 lsls r6, r2, #28 - 800bea0: 4605 mov r5, r0 - 800bea2: 460c mov r4, r1 - 800bea4: d454 bmi.n 800bf50 <__sflush_r+0xb8> - 800bea6: 684b ldr r3, [r1, #4] - 800bea8: 2b00 cmp r3, #0 - 800beaa: dc02 bgt.n 800beb2 <__sflush_r+0x1a> - 800beac: 6c0b ldr r3, [r1, #64] @ 0x40 - 800beae: 2b00 cmp r3, #0 - 800beb0: dd48 ble.n 800bf44 <__sflush_r+0xac> - 800beb2: 6ae6 ldr r6, [r4, #44] @ 0x2c - 800beb4: 2e00 cmp r6, #0 - 800beb6: d045 beq.n 800bf44 <__sflush_r+0xac> - 800beb8: 2300 movs r3, #0 - 800beba: f412 5280 ands.w r2, r2, #4096 @ 0x1000 - 800bebe: 682f ldr r7, [r5, #0] - 800bec0: 6a21 ldr r1, [r4, #32] - 800bec2: 602b str r3, [r5, #0] - 800bec4: d030 beq.n 800bf28 <__sflush_r+0x90> - 800bec6: 6d62 ldr r2, [r4, #84] @ 0x54 - 800bec8: 89a3 ldrh r3, [r4, #12] - 800beca: 0759 lsls r1, r3, #29 - 800becc: d505 bpl.n 800beda <__sflush_r+0x42> - 800bece: 6863 ldr r3, [r4, #4] - 800bed0: 1ad2 subs r2, r2, r3 - 800bed2: 6b63 ldr r3, [r4, #52] @ 0x34 - 800bed4: b10b cbz r3, 800beda <__sflush_r+0x42> - 800bed6: 6c23 ldr r3, [r4, #64] @ 0x40 - 800bed8: 1ad2 subs r2, r2, r3 - 800beda: 2300 movs r3, #0 - 800bedc: 4628 mov r0, r5 - 800bede: 6ae6 ldr r6, [r4, #44] @ 0x2c - 800bee0: 6a21 ldr r1, [r4, #32] - 800bee2: 47b0 blx r6 - 800bee4: 1c43 adds r3, r0, #1 - 800bee6: 89a3 ldrh r3, [r4, #12] - 800bee8: d106 bne.n 800bef8 <__sflush_r+0x60> - 800beea: 6829 ldr r1, [r5, #0] - 800beec: 291d cmp r1, #29 - 800beee: d82b bhi.n 800bf48 <__sflush_r+0xb0> - 800bef0: 4a28 ldr r2, [pc, #160] @ (800bf94 <__sflush_r+0xfc>) - 800bef2: 410a asrs r2, r1 - 800bef4: 07d6 lsls r6, r2, #31 - 800bef6: d427 bmi.n 800bf48 <__sflush_r+0xb0> - 800bef8: 2200 movs r2, #0 - 800befa: 6062 str r2, [r4, #4] - 800befc: 6922 ldr r2, [r4, #16] - 800befe: 04d9 lsls r1, r3, #19 - 800bf00: 6022 str r2, [r4, #0] - 800bf02: d504 bpl.n 800bf0e <__sflush_r+0x76> - 800bf04: 1c42 adds r2, r0, #1 - 800bf06: d101 bne.n 800bf0c <__sflush_r+0x74> - 800bf08: 682b ldr r3, [r5, #0] - 800bf0a: b903 cbnz r3, 800bf0e <__sflush_r+0x76> - 800bf0c: 6560 str r0, [r4, #84] @ 0x54 - 800bf0e: 6b61 ldr r1, [r4, #52] @ 0x34 - 800bf10: 602f str r7, [r5, #0] - 800bf12: b1b9 cbz r1, 800bf44 <__sflush_r+0xac> - 800bf14: f104 0344 add.w r3, r4, #68 @ 0x44 - 800bf18: 4299 cmp r1, r3 - 800bf1a: d002 beq.n 800bf22 <__sflush_r+0x8a> - 800bf1c: 4628 mov r0, r5 - 800bf1e: f000 fec9 bl 800ccb4 <_free_r> - 800bf22: 2300 movs r3, #0 - 800bf24: 6363 str r3, [r4, #52] @ 0x34 - 800bf26: e00d b.n 800bf44 <__sflush_r+0xac> - 800bf28: 2301 movs r3, #1 - 800bf2a: 4628 mov r0, r5 - 800bf2c: 47b0 blx r6 - 800bf2e: 4602 mov r2, r0 - 800bf30: 1c50 adds r0, r2, #1 - 800bf32: d1c9 bne.n 800bec8 <__sflush_r+0x30> - 800bf34: 682b ldr r3, [r5, #0] - 800bf36: 2b00 cmp r3, #0 - 800bf38: d0c6 beq.n 800bec8 <__sflush_r+0x30> - 800bf3a: 2b1d cmp r3, #29 - 800bf3c: d001 beq.n 800bf42 <__sflush_r+0xaa> - 800bf3e: 2b16 cmp r3, #22 - 800bf40: d11d bne.n 800bf7e <__sflush_r+0xe6> - 800bf42: 602f str r7, [r5, #0] - 800bf44: 2000 movs r0, #0 - 800bf46: e021 b.n 800bf8c <__sflush_r+0xf4> - 800bf48: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800bf4c: b21b sxth r3, r3 - 800bf4e: e01a b.n 800bf86 <__sflush_r+0xee> - 800bf50: 690f ldr r7, [r1, #16] - 800bf52: 2f00 cmp r7, #0 - 800bf54: d0f6 beq.n 800bf44 <__sflush_r+0xac> - 800bf56: 0793 lsls r3, r2, #30 - 800bf58: bf18 it ne - 800bf5a: 2300 movne r3, #0 - 800bf5c: 680e ldr r6, [r1, #0] - 800bf5e: bf08 it eq - 800bf60: 694b ldreq r3, [r1, #20] - 800bf62: 1bf6 subs r6, r6, r7 - 800bf64: 600f str r7, [r1, #0] - 800bf66: 608b str r3, [r1, #8] - 800bf68: 2e00 cmp r6, #0 - 800bf6a: ddeb ble.n 800bf44 <__sflush_r+0xac> - 800bf6c: 4633 mov r3, r6 - 800bf6e: 463a mov r2, r7 - 800bf70: 4628 mov r0, r5 - 800bf72: 6a21 ldr r1, [r4, #32] - 800bf74: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 - 800bf78: 47e0 blx ip - 800bf7a: 2800 cmp r0, #0 - 800bf7c: dc07 bgt.n 800bf8e <__sflush_r+0xf6> - 800bf7e: f9b4 300c ldrsh.w r3, [r4, #12] - 800bf82: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800bf86: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800bf8a: 81a3 strh r3, [r4, #12] - 800bf8c: bdf8 pop {r3, r4, r5, r6, r7, pc} - 800bf8e: 4407 add r7, r0 - 800bf90: 1a36 subs r6, r6, r0 - 800bf92: e7e9 b.n 800bf68 <__sflush_r+0xd0> - 800bf94: dfbffffe .word 0xdfbffffe - -0800bf98 <_fflush_r>: - 800bf98: b538 push {r3, r4, r5, lr} - 800bf9a: 690b ldr r3, [r1, #16] - 800bf9c: 4605 mov r5, r0 - 800bf9e: 460c mov r4, r1 - 800bfa0: b913 cbnz r3, 800bfa8 <_fflush_r+0x10> - 800bfa2: 2500 movs r5, #0 - 800bfa4: 4628 mov r0, r5 - 800bfa6: bd38 pop {r3, r4, r5, pc} - 800bfa8: b118 cbz r0, 800bfb2 <_fflush_r+0x1a> - 800bfaa: 6a03 ldr r3, [r0, #32] - 800bfac: b90b cbnz r3, 800bfb2 <_fflush_r+0x1a> - 800bfae: f7fd ff75 bl 8009e9c <__sinit> - 800bfb2: f9b4 300c ldrsh.w r3, [r4, #12] - 800bfb6: 2b00 cmp r3, #0 - 800bfb8: d0f3 beq.n 800bfa2 <_fflush_r+0xa> - 800bfba: 6e62 ldr r2, [r4, #100] @ 0x64 - 800bfbc: 07d0 lsls r0, r2, #31 - 800bfbe: d404 bmi.n 800bfca <_fflush_r+0x32> - 800bfc0: 0599 lsls r1, r3, #22 - 800bfc2: d402 bmi.n 800bfca <_fflush_r+0x32> - 800bfc4: 6da0 ldr r0, [r4, #88] @ 0x58 - 800bfc6: f7fe fd45 bl 800aa54 <__retarget_lock_acquire_recursive> - 800bfca: 4628 mov r0, r5 - 800bfcc: 4621 mov r1, r4 - 800bfce: f7ff ff63 bl 800be98 <__sflush_r> - 800bfd2: 6e63 ldr r3, [r4, #100] @ 0x64 - 800bfd4: 4605 mov r5, r0 - 800bfd6: 07da lsls r2, r3, #31 - 800bfd8: d4e4 bmi.n 800bfa4 <_fflush_r+0xc> - 800bfda: 89a3 ldrh r3, [r4, #12] - 800bfdc: 059b lsls r3, r3, #22 - 800bfde: d4e1 bmi.n 800bfa4 <_fflush_r+0xc> - 800bfe0: 6da0 ldr r0, [r4, #88] @ 0x58 - 800bfe2: f7fe fd39 bl 800aa58 <__retarget_lock_release_recursive> - 800bfe6: e7dd b.n 800bfa4 <_fflush_r+0xc> - -0800bfe8 <__malloc_lock>: - 800bfe8: 4801 ldr r0, [pc, #4] @ (800bff0 <__malloc_lock+0x8>) - 800bfea: f7fe bd33 b.w 800aa54 <__retarget_lock_acquire_recursive> - 800bfee: bf00 nop - 800bff0: 200034fe .word 0x200034fe - -0800bff4 <__malloc_unlock>: - 800bff4: 4801 ldr r0, [pc, #4] @ (800bffc <__malloc_unlock+0x8>) - 800bff6: f7fe bd2f b.w 800aa58 <__retarget_lock_release_recursive> - 800bffa: bf00 nop - 800bffc: 200034fe .word 0x200034fe - -0800c000 <_Balloc>: - 800c000: b570 push {r4, r5, r6, lr} - 800c002: 69c6 ldr r6, [r0, #28] - 800c004: 4604 mov r4, r0 - 800c006: 460d mov r5, r1 - 800c008: b976 cbnz r6, 800c028 <_Balloc+0x28> - 800c00a: 2010 movs r0, #16 - 800c00c: f7ff fe92 bl 800bd34 - 800c010: 4602 mov r2, r0 - 800c012: 61e0 str r0, [r4, #28] - 800c014: b920 cbnz r0, 800c020 <_Balloc+0x20> - 800c016: 216b movs r1, #107 @ 0x6b - 800c018: 4b17 ldr r3, [pc, #92] @ (800c078 <_Balloc+0x78>) - 800c01a: 4818 ldr r0, [pc, #96] @ (800c07c <_Balloc+0x7c>) - 800c01c: f7fe fd42 bl 800aaa4 <__assert_func> - 800c020: e9c0 6601 strd r6, r6, [r0, #4] - 800c024: 6006 str r6, [r0, #0] - 800c026: 60c6 str r6, [r0, #12] - 800c028: 69e6 ldr r6, [r4, #28] - 800c02a: 68f3 ldr r3, [r6, #12] - 800c02c: b183 cbz r3, 800c050 <_Balloc+0x50> - 800c02e: 69e3 ldr r3, [r4, #28] - 800c030: 68db ldr r3, [r3, #12] - 800c032: f853 0025 ldr.w r0, [r3, r5, lsl #2] - 800c036: b9b8 cbnz r0, 800c068 <_Balloc+0x68> - 800c038: 2101 movs r1, #1 - 800c03a: fa01 f605 lsl.w r6, r1, r5 - 800c03e: 1d72 adds r2, r6, #5 - 800c040: 4620 mov r0, r4 - 800c042: 0092 lsls r2, r2, #2 - 800c044: f000 fe15 bl 800cc72 <_calloc_r> - 800c048: b160 cbz r0, 800c064 <_Balloc+0x64> - 800c04a: e9c0 5601 strd r5, r6, [r0, #4] - 800c04e: e00e b.n 800c06e <_Balloc+0x6e> - 800c050: 2221 movs r2, #33 @ 0x21 - 800c052: 2104 movs r1, #4 - 800c054: 4620 mov r0, r4 - 800c056: f000 fe0c bl 800cc72 <_calloc_r> - 800c05a: 69e3 ldr r3, [r4, #28] - 800c05c: 60f0 str r0, [r6, #12] - 800c05e: 68db ldr r3, [r3, #12] - 800c060: 2b00 cmp r3, #0 - 800c062: d1e4 bne.n 800c02e <_Balloc+0x2e> - 800c064: 2000 movs r0, #0 - 800c066: bd70 pop {r4, r5, r6, pc} - 800c068: 6802 ldr r2, [r0, #0] - 800c06a: f843 2025 str.w r2, [r3, r5, lsl #2] - 800c06e: 2300 movs r3, #0 - 800c070: e9c0 3303 strd r3, r3, [r0, #12] - 800c074: e7f7 b.n 800c066 <_Balloc+0x66> - 800c076: bf00 nop - 800c078: 0800e036 .word 0x0800e036 - 800c07c: 0800e271 .word 0x0800e271 - -0800c080 <_Bfree>: - 800c080: b570 push {r4, r5, r6, lr} - 800c082: 69c6 ldr r6, [r0, #28] - 800c084: 4605 mov r5, r0 - 800c086: 460c mov r4, r1 - 800c088: b976 cbnz r6, 800c0a8 <_Bfree+0x28> - 800c08a: 2010 movs r0, #16 - 800c08c: f7ff fe52 bl 800bd34 - 800c090: 4602 mov r2, r0 - 800c092: 61e8 str r0, [r5, #28] - 800c094: b920 cbnz r0, 800c0a0 <_Bfree+0x20> - 800c096: 218f movs r1, #143 @ 0x8f - 800c098: 4b08 ldr r3, [pc, #32] @ (800c0bc <_Bfree+0x3c>) - 800c09a: 4809 ldr r0, [pc, #36] @ (800c0c0 <_Bfree+0x40>) - 800c09c: f7fe fd02 bl 800aaa4 <__assert_func> - 800c0a0: e9c0 6601 strd r6, r6, [r0, #4] - 800c0a4: 6006 str r6, [r0, #0] - 800c0a6: 60c6 str r6, [r0, #12] - 800c0a8: b13c cbz r4, 800c0ba <_Bfree+0x3a> - 800c0aa: 69eb ldr r3, [r5, #28] - 800c0ac: 6862 ldr r2, [r4, #4] - 800c0ae: 68db ldr r3, [r3, #12] - 800c0b0: f853 1022 ldr.w r1, [r3, r2, lsl #2] - 800c0b4: 6021 str r1, [r4, #0] - 800c0b6: f843 4022 str.w r4, [r3, r2, lsl #2] - 800c0ba: bd70 pop {r4, r5, r6, pc} - 800c0bc: 0800e036 .word 0x0800e036 - 800c0c0: 0800e271 .word 0x0800e271 - -0800c0c4 <__multadd>: - 800c0c4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800c0c8: 4607 mov r7, r0 - 800c0ca: 460c mov r4, r1 - 800c0cc: 461e mov r6, r3 - 800c0ce: 2000 movs r0, #0 - 800c0d0: 690d ldr r5, [r1, #16] - 800c0d2: f101 0c14 add.w ip, r1, #20 - 800c0d6: f8dc 3000 ldr.w r3, [ip] - 800c0da: 3001 adds r0, #1 - 800c0dc: b299 uxth r1, r3 - 800c0de: fb02 6101 mla r1, r2, r1, r6 - 800c0e2: 0c1e lsrs r6, r3, #16 - 800c0e4: 0c0b lsrs r3, r1, #16 - 800c0e6: fb02 3306 mla r3, r2, r6, r3 - 800c0ea: b289 uxth r1, r1 - 800c0ec: eb01 4103 add.w r1, r1, r3, lsl #16 - 800c0f0: 4285 cmp r5, r0 - 800c0f2: ea4f 4613 mov.w r6, r3, lsr #16 - 800c0f6: f84c 1b04 str.w r1, [ip], #4 - 800c0fa: dcec bgt.n 800c0d6 <__multadd+0x12> - 800c0fc: b30e cbz r6, 800c142 <__multadd+0x7e> - 800c0fe: 68a3 ldr r3, [r4, #8] - 800c100: 42ab cmp r3, r5 - 800c102: dc19 bgt.n 800c138 <__multadd+0x74> - 800c104: 6861 ldr r1, [r4, #4] - 800c106: 4638 mov r0, r7 - 800c108: 3101 adds r1, #1 - 800c10a: f7ff ff79 bl 800c000 <_Balloc> - 800c10e: 4680 mov r8, r0 - 800c110: b928 cbnz r0, 800c11e <__multadd+0x5a> - 800c112: 4602 mov r2, r0 - 800c114: 21ba movs r1, #186 @ 0xba - 800c116: 4b0c ldr r3, [pc, #48] @ (800c148 <__multadd+0x84>) - 800c118: 480c ldr r0, [pc, #48] @ (800c14c <__multadd+0x88>) - 800c11a: f7fe fcc3 bl 800aaa4 <__assert_func> - 800c11e: 6922 ldr r2, [r4, #16] - 800c120: f104 010c add.w r1, r4, #12 - 800c124: 3202 adds r2, #2 - 800c126: 0092 lsls r2, r2, #2 - 800c128: 300c adds r0, #12 - 800c12a: f7fe fca4 bl 800aa76 - 800c12e: 4621 mov r1, r4 - 800c130: 4638 mov r0, r7 - 800c132: f7ff ffa5 bl 800c080 <_Bfree> - 800c136: 4644 mov r4, r8 - 800c138: eb04 0385 add.w r3, r4, r5, lsl #2 - 800c13c: 3501 adds r5, #1 - 800c13e: 615e str r6, [r3, #20] - 800c140: 6125 str r5, [r4, #16] - 800c142: 4620 mov r0, r4 - 800c144: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 800c148: 0800e24f .word 0x0800e24f - 800c14c: 0800e271 .word 0x0800e271 - -0800c150 <__hi0bits>: - 800c150: 4603 mov r3, r0 - 800c152: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 - 800c156: bf3a itte cc - 800c158: 0403 lslcc r3, r0, #16 - 800c15a: 2010 movcc r0, #16 - 800c15c: 2000 movcs r0, #0 - 800c15e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 800c162: bf3c itt cc - 800c164: 021b lslcc r3, r3, #8 - 800c166: 3008 addcc r0, #8 - 800c168: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 - 800c16c: bf3c itt cc - 800c16e: 011b lslcc r3, r3, #4 - 800c170: 3004 addcc r0, #4 - 800c172: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 800c176: bf3c itt cc - 800c178: 009b lslcc r3, r3, #2 - 800c17a: 3002 addcc r0, #2 - 800c17c: 2b00 cmp r3, #0 - 800c17e: db05 blt.n 800c18c <__hi0bits+0x3c> - 800c180: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 - 800c184: f100 0001 add.w r0, r0, #1 - 800c188: bf08 it eq - 800c18a: 2020 moveq r0, #32 - 800c18c: 4770 bx lr - -0800c18e <__lo0bits>: - 800c18e: 6803 ldr r3, [r0, #0] - 800c190: 4602 mov r2, r0 - 800c192: f013 0007 ands.w r0, r3, #7 - 800c196: d00b beq.n 800c1b0 <__lo0bits+0x22> - 800c198: 07d9 lsls r1, r3, #31 - 800c19a: d421 bmi.n 800c1e0 <__lo0bits+0x52> - 800c19c: 0798 lsls r0, r3, #30 - 800c19e: bf49 itett mi - 800c1a0: 085b lsrmi r3, r3, #1 - 800c1a2: 089b lsrpl r3, r3, #2 - 800c1a4: 2001 movmi r0, #1 - 800c1a6: 6013 strmi r3, [r2, #0] - 800c1a8: bf5c itt pl - 800c1aa: 2002 movpl r0, #2 - 800c1ac: 6013 strpl r3, [r2, #0] - 800c1ae: 4770 bx lr - 800c1b0: b299 uxth r1, r3 - 800c1b2: b909 cbnz r1, 800c1b8 <__lo0bits+0x2a> - 800c1b4: 2010 movs r0, #16 - 800c1b6: 0c1b lsrs r3, r3, #16 - 800c1b8: b2d9 uxtb r1, r3 - 800c1ba: b909 cbnz r1, 800c1c0 <__lo0bits+0x32> - 800c1bc: 3008 adds r0, #8 - 800c1be: 0a1b lsrs r3, r3, #8 - 800c1c0: 0719 lsls r1, r3, #28 - 800c1c2: bf04 itt eq - 800c1c4: 091b lsreq r3, r3, #4 - 800c1c6: 3004 addeq r0, #4 - 800c1c8: 0799 lsls r1, r3, #30 - 800c1ca: bf04 itt eq - 800c1cc: 089b lsreq r3, r3, #2 - 800c1ce: 3002 addeq r0, #2 - 800c1d0: 07d9 lsls r1, r3, #31 - 800c1d2: d403 bmi.n 800c1dc <__lo0bits+0x4e> - 800c1d4: 085b lsrs r3, r3, #1 - 800c1d6: f100 0001 add.w r0, r0, #1 - 800c1da: d003 beq.n 800c1e4 <__lo0bits+0x56> - 800c1dc: 6013 str r3, [r2, #0] - 800c1de: 4770 bx lr - 800c1e0: 2000 movs r0, #0 - 800c1e2: 4770 bx lr - 800c1e4: 2020 movs r0, #32 - 800c1e6: 4770 bx lr - -0800c1e8 <__i2b>: - 800c1e8: b510 push {r4, lr} - 800c1ea: 460c mov r4, r1 - 800c1ec: 2101 movs r1, #1 - 800c1ee: f7ff ff07 bl 800c000 <_Balloc> - 800c1f2: 4602 mov r2, r0 - 800c1f4: b928 cbnz r0, 800c202 <__i2b+0x1a> - 800c1f6: f240 1145 movw r1, #325 @ 0x145 - 800c1fa: 4b04 ldr r3, [pc, #16] @ (800c20c <__i2b+0x24>) - 800c1fc: 4804 ldr r0, [pc, #16] @ (800c210 <__i2b+0x28>) - 800c1fe: f7fe fc51 bl 800aaa4 <__assert_func> - 800c202: 2301 movs r3, #1 - 800c204: 6144 str r4, [r0, #20] - 800c206: 6103 str r3, [r0, #16] - 800c208: bd10 pop {r4, pc} - 800c20a: bf00 nop - 800c20c: 0800e24f .word 0x0800e24f - 800c210: 0800e271 .word 0x0800e271 - -0800c214 <__multiply>: - 800c214: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800c218: 4614 mov r4, r2 - 800c21a: 690a ldr r2, [r1, #16] - 800c21c: 6923 ldr r3, [r4, #16] - 800c21e: 460f mov r7, r1 - 800c220: 429a cmp r2, r3 - 800c222: bfa2 ittt ge - 800c224: 4623 movge r3, r4 - 800c226: 460c movge r4, r1 - 800c228: 461f movge r7, r3 - 800c22a: f8d4 a010 ldr.w sl, [r4, #16] - 800c22e: f8d7 9010 ldr.w r9, [r7, #16] - 800c232: 68a3 ldr r3, [r4, #8] - 800c234: 6861 ldr r1, [r4, #4] - 800c236: eb0a 0609 add.w r6, sl, r9 - 800c23a: 42b3 cmp r3, r6 - 800c23c: b085 sub sp, #20 - 800c23e: bfb8 it lt - 800c240: 3101 addlt r1, #1 - 800c242: f7ff fedd bl 800c000 <_Balloc> - 800c246: b930 cbnz r0, 800c256 <__multiply+0x42> - 800c248: 4602 mov r2, r0 - 800c24a: f44f 71b1 mov.w r1, #354 @ 0x162 - 800c24e: 4b43 ldr r3, [pc, #268] @ (800c35c <__multiply+0x148>) - 800c250: 4843 ldr r0, [pc, #268] @ (800c360 <__multiply+0x14c>) - 800c252: f7fe fc27 bl 800aaa4 <__assert_func> - 800c256: f100 0514 add.w r5, r0, #20 - 800c25a: 462b mov r3, r5 - 800c25c: 2200 movs r2, #0 - 800c25e: eb05 0886 add.w r8, r5, r6, lsl #2 - 800c262: 4543 cmp r3, r8 - 800c264: d321 bcc.n 800c2aa <__multiply+0x96> - 800c266: f107 0114 add.w r1, r7, #20 - 800c26a: f104 0214 add.w r2, r4, #20 - 800c26e: eb02 028a add.w r2, r2, sl, lsl #2 - 800c272: eb01 0389 add.w r3, r1, r9, lsl #2 - 800c276: 9302 str r3, [sp, #8] - 800c278: 1b13 subs r3, r2, r4 - 800c27a: 3b15 subs r3, #21 - 800c27c: f023 0303 bic.w r3, r3, #3 - 800c280: 3304 adds r3, #4 - 800c282: f104 0715 add.w r7, r4, #21 - 800c286: 42ba cmp r2, r7 - 800c288: bf38 it cc - 800c28a: 2304 movcc r3, #4 - 800c28c: 9301 str r3, [sp, #4] - 800c28e: 9b02 ldr r3, [sp, #8] - 800c290: 9103 str r1, [sp, #12] - 800c292: 428b cmp r3, r1 - 800c294: d80c bhi.n 800c2b0 <__multiply+0x9c> - 800c296: 2e00 cmp r6, #0 - 800c298: dd03 ble.n 800c2a2 <__multiply+0x8e> - 800c29a: f858 3d04 ldr.w r3, [r8, #-4]! - 800c29e: 2b00 cmp r3, #0 - 800c2a0: d05a beq.n 800c358 <__multiply+0x144> - 800c2a2: 6106 str r6, [r0, #16] - 800c2a4: b005 add sp, #20 - 800c2a6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800c2aa: f843 2b04 str.w r2, [r3], #4 - 800c2ae: e7d8 b.n 800c262 <__multiply+0x4e> - 800c2b0: f8b1 a000 ldrh.w sl, [r1] - 800c2b4: f1ba 0f00 cmp.w sl, #0 - 800c2b8: d023 beq.n 800c302 <__multiply+0xee> - 800c2ba: 46a9 mov r9, r5 - 800c2bc: f04f 0c00 mov.w ip, #0 - 800c2c0: f104 0e14 add.w lr, r4, #20 - 800c2c4: f85e 7b04 ldr.w r7, [lr], #4 - 800c2c8: f8d9 3000 ldr.w r3, [r9] - 800c2cc: fa1f fb87 uxth.w fp, r7 - 800c2d0: b29b uxth r3, r3 - 800c2d2: fb0a 330b mla r3, sl, fp, r3 - 800c2d6: 4463 add r3, ip - 800c2d8: f8d9 c000 ldr.w ip, [r9] - 800c2dc: 0c3f lsrs r7, r7, #16 - 800c2de: ea4f 4c1c mov.w ip, ip, lsr #16 - 800c2e2: fb0a c707 mla r7, sl, r7, ip - 800c2e6: eb07 4713 add.w r7, r7, r3, lsr #16 - 800c2ea: b29b uxth r3, r3 - 800c2ec: ea43 4307 orr.w r3, r3, r7, lsl #16 - 800c2f0: 4572 cmp r2, lr - 800c2f2: ea4f 4c17 mov.w ip, r7, lsr #16 - 800c2f6: f849 3b04 str.w r3, [r9], #4 - 800c2fa: d8e3 bhi.n 800c2c4 <__multiply+0xb0> - 800c2fc: 9b01 ldr r3, [sp, #4] - 800c2fe: f845 c003 str.w ip, [r5, r3] - 800c302: 9b03 ldr r3, [sp, #12] - 800c304: 3104 adds r1, #4 - 800c306: f8b3 9002 ldrh.w r9, [r3, #2] - 800c30a: f1b9 0f00 cmp.w r9, #0 - 800c30e: d021 beq.n 800c354 <__multiply+0x140> - 800c310: 46ae mov lr, r5 - 800c312: f04f 0a00 mov.w sl, #0 - 800c316: 682b ldr r3, [r5, #0] - 800c318: f104 0c14 add.w ip, r4, #20 - 800c31c: f8bc b000 ldrh.w fp, [ip] - 800c320: f8be 7002 ldrh.w r7, [lr, #2] - 800c324: b29b uxth r3, r3 - 800c326: fb09 770b mla r7, r9, fp, r7 - 800c32a: 4457 add r7, sl - 800c32c: ea43 4307 orr.w r3, r3, r7, lsl #16 - 800c330: f84e 3b04 str.w r3, [lr], #4 - 800c334: f85c 3b04 ldr.w r3, [ip], #4 - 800c338: ea4f 4a13 mov.w sl, r3, lsr #16 - 800c33c: f8be 3000 ldrh.w r3, [lr] - 800c340: 4562 cmp r2, ip - 800c342: fb09 330a mla r3, r9, sl, r3 - 800c346: eb03 4317 add.w r3, r3, r7, lsr #16 - 800c34a: ea4f 4a13 mov.w sl, r3, lsr #16 - 800c34e: d8e5 bhi.n 800c31c <__multiply+0x108> - 800c350: 9f01 ldr r7, [sp, #4] - 800c352: 51eb str r3, [r5, r7] - 800c354: 3504 adds r5, #4 - 800c356: e79a b.n 800c28e <__multiply+0x7a> - 800c358: 3e01 subs r6, #1 - 800c35a: e79c b.n 800c296 <__multiply+0x82> - 800c35c: 0800e24f .word 0x0800e24f - 800c360: 0800e271 .word 0x0800e271 - -0800c364 <__pow5mult>: - 800c364: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 800c368: 4615 mov r5, r2 - 800c36a: f012 0203 ands.w r2, r2, #3 - 800c36e: 4607 mov r7, r0 - 800c370: 460e mov r6, r1 - 800c372: d007 beq.n 800c384 <__pow5mult+0x20> - 800c374: 4c25 ldr r4, [pc, #148] @ (800c40c <__pow5mult+0xa8>) - 800c376: 3a01 subs r2, #1 - 800c378: 2300 movs r3, #0 - 800c37a: f854 2022 ldr.w r2, [r4, r2, lsl #2] - 800c37e: f7ff fea1 bl 800c0c4 <__multadd> - 800c382: 4606 mov r6, r0 - 800c384: 10ad asrs r5, r5, #2 - 800c386: d03d beq.n 800c404 <__pow5mult+0xa0> - 800c388: 69fc ldr r4, [r7, #28] - 800c38a: b97c cbnz r4, 800c3ac <__pow5mult+0x48> - 800c38c: 2010 movs r0, #16 - 800c38e: f7ff fcd1 bl 800bd34 - 800c392: 4602 mov r2, r0 - 800c394: 61f8 str r0, [r7, #28] - 800c396: b928 cbnz r0, 800c3a4 <__pow5mult+0x40> - 800c398: f240 11b3 movw r1, #435 @ 0x1b3 - 800c39c: 4b1c ldr r3, [pc, #112] @ (800c410 <__pow5mult+0xac>) - 800c39e: 481d ldr r0, [pc, #116] @ (800c414 <__pow5mult+0xb0>) - 800c3a0: f7fe fb80 bl 800aaa4 <__assert_func> - 800c3a4: e9c0 4401 strd r4, r4, [r0, #4] - 800c3a8: 6004 str r4, [r0, #0] - 800c3aa: 60c4 str r4, [r0, #12] - 800c3ac: f8d7 801c ldr.w r8, [r7, #28] - 800c3b0: f8d8 4008 ldr.w r4, [r8, #8] - 800c3b4: b94c cbnz r4, 800c3ca <__pow5mult+0x66> - 800c3b6: f240 2171 movw r1, #625 @ 0x271 - 800c3ba: 4638 mov r0, r7 - 800c3bc: f7ff ff14 bl 800c1e8 <__i2b> - 800c3c0: 2300 movs r3, #0 - 800c3c2: 4604 mov r4, r0 - 800c3c4: f8c8 0008 str.w r0, [r8, #8] - 800c3c8: 6003 str r3, [r0, #0] - 800c3ca: f04f 0900 mov.w r9, #0 - 800c3ce: 07eb lsls r3, r5, #31 - 800c3d0: d50a bpl.n 800c3e8 <__pow5mult+0x84> - 800c3d2: 4631 mov r1, r6 - 800c3d4: 4622 mov r2, r4 - 800c3d6: 4638 mov r0, r7 - 800c3d8: f7ff ff1c bl 800c214 <__multiply> - 800c3dc: 4680 mov r8, r0 - 800c3de: 4631 mov r1, r6 - 800c3e0: 4638 mov r0, r7 - 800c3e2: f7ff fe4d bl 800c080 <_Bfree> - 800c3e6: 4646 mov r6, r8 - 800c3e8: 106d asrs r5, r5, #1 - 800c3ea: d00b beq.n 800c404 <__pow5mult+0xa0> - 800c3ec: 6820 ldr r0, [r4, #0] - 800c3ee: b938 cbnz r0, 800c400 <__pow5mult+0x9c> - 800c3f0: 4622 mov r2, r4 - 800c3f2: 4621 mov r1, r4 - 800c3f4: 4638 mov r0, r7 - 800c3f6: f7ff ff0d bl 800c214 <__multiply> - 800c3fa: 6020 str r0, [r4, #0] - 800c3fc: f8c0 9000 str.w r9, [r0] - 800c400: 4604 mov r4, r0 - 800c402: e7e4 b.n 800c3ce <__pow5mult+0x6a> - 800c404: 4630 mov r0, r6 - 800c406: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 800c40a: bf00 nop - 800c40c: 0800e2cc .word 0x0800e2cc - 800c410: 0800e036 .word 0x0800e036 - 800c414: 0800e271 .word 0x0800e271 - -0800c418 <__lshift>: - 800c418: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800c41c: 460c mov r4, r1 - 800c41e: 4607 mov r7, r0 - 800c420: 4691 mov r9, r2 - 800c422: 6923 ldr r3, [r4, #16] - 800c424: 6849 ldr r1, [r1, #4] - 800c426: eb03 1862 add.w r8, r3, r2, asr #5 - 800c42a: 68a3 ldr r3, [r4, #8] - 800c42c: ea4f 1a62 mov.w sl, r2, asr #5 - 800c430: f108 0601 add.w r6, r8, #1 - 800c434: 42b3 cmp r3, r6 - 800c436: db0b blt.n 800c450 <__lshift+0x38> - 800c438: 4638 mov r0, r7 - 800c43a: f7ff fde1 bl 800c000 <_Balloc> - 800c43e: 4605 mov r5, r0 - 800c440: b948 cbnz r0, 800c456 <__lshift+0x3e> - 800c442: 4602 mov r2, r0 - 800c444: f44f 71ef mov.w r1, #478 @ 0x1de - 800c448: 4b27 ldr r3, [pc, #156] @ (800c4e8 <__lshift+0xd0>) - 800c44a: 4828 ldr r0, [pc, #160] @ (800c4ec <__lshift+0xd4>) - 800c44c: f7fe fb2a bl 800aaa4 <__assert_func> - 800c450: 3101 adds r1, #1 - 800c452: 005b lsls r3, r3, #1 - 800c454: e7ee b.n 800c434 <__lshift+0x1c> - 800c456: 2300 movs r3, #0 - 800c458: f100 0114 add.w r1, r0, #20 - 800c45c: f100 0210 add.w r2, r0, #16 - 800c460: 4618 mov r0, r3 - 800c462: 4553 cmp r3, sl - 800c464: db33 blt.n 800c4ce <__lshift+0xb6> - 800c466: 6920 ldr r0, [r4, #16] - 800c468: ea2a 7aea bic.w sl, sl, sl, asr #31 - 800c46c: f104 0314 add.w r3, r4, #20 - 800c470: f019 091f ands.w r9, r9, #31 - 800c474: eb01 018a add.w r1, r1, sl, lsl #2 - 800c478: eb03 0c80 add.w ip, r3, r0, lsl #2 - 800c47c: d02b beq.n 800c4d6 <__lshift+0xbe> - 800c47e: 468a mov sl, r1 - 800c480: 2200 movs r2, #0 - 800c482: f1c9 0e20 rsb lr, r9, #32 - 800c486: 6818 ldr r0, [r3, #0] - 800c488: fa00 f009 lsl.w r0, r0, r9 - 800c48c: 4310 orrs r0, r2 - 800c48e: f84a 0b04 str.w r0, [sl], #4 - 800c492: f853 2b04 ldr.w r2, [r3], #4 - 800c496: 459c cmp ip, r3 - 800c498: fa22 f20e lsr.w r2, r2, lr - 800c49c: d8f3 bhi.n 800c486 <__lshift+0x6e> - 800c49e: ebac 0304 sub.w r3, ip, r4 - 800c4a2: 3b15 subs r3, #21 - 800c4a4: f023 0303 bic.w r3, r3, #3 - 800c4a8: 3304 adds r3, #4 - 800c4aa: f104 0015 add.w r0, r4, #21 - 800c4ae: 4584 cmp ip, r0 - 800c4b0: bf38 it cc - 800c4b2: 2304 movcc r3, #4 - 800c4b4: 50ca str r2, [r1, r3] - 800c4b6: b10a cbz r2, 800c4bc <__lshift+0xa4> - 800c4b8: f108 0602 add.w r6, r8, #2 - 800c4bc: 3e01 subs r6, #1 - 800c4be: 4638 mov r0, r7 - 800c4c0: 4621 mov r1, r4 - 800c4c2: 612e str r6, [r5, #16] - 800c4c4: f7ff fddc bl 800c080 <_Bfree> - 800c4c8: 4628 mov r0, r5 - 800c4ca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800c4ce: f842 0f04 str.w r0, [r2, #4]! - 800c4d2: 3301 adds r3, #1 - 800c4d4: e7c5 b.n 800c462 <__lshift+0x4a> - 800c4d6: 3904 subs r1, #4 - 800c4d8: f853 2b04 ldr.w r2, [r3], #4 - 800c4dc: 459c cmp ip, r3 - 800c4de: f841 2f04 str.w r2, [r1, #4]! - 800c4e2: d8f9 bhi.n 800c4d8 <__lshift+0xc0> - 800c4e4: e7ea b.n 800c4bc <__lshift+0xa4> - 800c4e6: bf00 nop - 800c4e8: 0800e24f .word 0x0800e24f - 800c4ec: 0800e271 .word 0x0800e271 - -0800c4f0 <__mcmp>: - 800c4f0: 4603 mov r3, r0 - 800c4f2: 690a ldr r2, [r1, #16] - 800c4f4: 6900 ldr r0, [r0, #16] - 800c4f6: b530 push {r4, r5, lr} - 800c4f8: 1a80 subs r0, r0, r2 - 800c4fa: d10e bne.n 800c51a <__mcmp+0x2a> - 800c4fc: 3314 adds r3, #20 - 800c4fe: 3114 adds r1, #20 - 800c500: eb03 0482 add.w r4, r3, r2, lsl #2 - 800c504: eb01 0182 add.w r1, r1, r2, lsl #2 - 800c508: f854 5d04 ldr.w r5, [r4, #-4]! - 800c50c: f851 2d04 ldr.w r2, [r1, #-4]! - 800c510: 4295 cmp r5, r2 - 800c512: d003 beq.n 800c51c <__mcmp+0x2c> - 800c514: d205 bcs.n 800c522 <__mcmp+0x32> - 800c516: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800c51a: bd30 pop {r4, r5, pc} - 800c51c: 42a3 cmp r3, r4 - 800c51e: d3f3 bcc.n 800c508 <__mcmp+0x18> - 800c520: e7fb b.n 800c51a <__mcmp+0x2a> - 800c522: 2001 movs r0, #1 - 800c524: e7f9 b.n 800c51a <__mcmp+0x2a> - ... - -0800c528 <__mdiff>: - 800c528: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800c52c: 4689 mov r9, r1 - 800c52e: 4606 mov r6, r0 - 800c530: 4611 mov r1, r2 - 800c532: 4648 mov r0, r9 - 800c534: 4614 mov r4, r2 - 800c536: f7ff ffdb bl 800c4f0 <__mcmp> - 800c53a: 1e05 subs r5, r0, #0 - 800c53c: d112 bne.n 800c564 <__mdiff+0x3c> - 800c53e: 4629 mov r1, r5 - 800c540: 4630 mov r0, r6 - 800c542: f7ff fd5d bl 800c000 <_Balloc> - 800c546: 4602 mov r2, r0 - 800c548: b928 cbnz r0, 800c556 <__mdiff+0x2e> - 800c54a: f240 2137 movw r1, #567 @ 0x237 - 800c54e: 4b3e ldr r3, [pc, #248] @ (800c648 <__mdiff+0x120>) - 800c550: 483e ldr r0, [pc, #248] @ (800c64c <__mdiff+0x124>) - 800c552: f7fe faa7 bl 800aaa4 <__assert_func> - 800c556: 2301 movs r3, #1 - 800c558: e9c0 3504 strd r3, r5, [r0, #16] - 800c55c: 4610 mov r0, r2 - 800c55e: b003 add sp, #12 - 800c560: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800c564: bfbc itt lt - 800c566: 464b movlt r3, r9 - 800c568: 46a1 movlt r9, r4 - 800c56a: 4630 mov r0, r6 - 800c56c: f8d9 1004 ldr.w r1, [r9, #4] - 800c570: bfba itte lt - 800c572: 461c movlt r4, r3 - 800c574: 2501 movlt r5, #1 - 800c576: 2500 movge r5, #0 - 800c578: f7ff fd42 bl 800c000 <_Balloc> - 800c57c: 4602 mov r2, r0 - 800c57e: b918 cbnz r0, 800c588 <__mdiff+0x60> - 800c580: f240 2145 movw r1, #581 @ 0x245 - 800c584: 4b30 ldr r3, [pc, #192] @ (800c648 <__mdiff+0x120>) - 800c586: e7e3 b.n 800c550 <__mdiff+0x28> - 800c588: f100 0b14 add.w fp, r0, #20 - 800c58c: f8d9 7010 ldr.w r7, [r9, #16] - 800c590: f109 0310 add.w r3, r9, #16 - 800c594: 60c5 str r5, [r0, #12] - 800c596: f04f 0c00 mov.w ip, #0 - 800c59a: f109 0514 add.w r5, r9, #20 - 800c59e: 46d9 mov r9, fp - 800c5a0: 6926 ldr r6, [r4, #16] - 800c5a2: f104 0e14 add.w lr, r4, #20 - 800c5a6: eb05 0887 add.w r8, r5, r7, lsl #2 - 800c5aa: eb0e 0686 add.w r6, lr, r6, lsl #2 - 800c5ae: 9301 str r3, [sp, #4] - 800c5b0: 9b01 ldr r3, [sp, #4] - 800c5b2: f85e 0b04 ldr.w r0, [lr], #4 - 800c5b6: f853 af04 ldr.w sl, [r3, #4]! - 800c5ba: b281 uxth r1, r0 - 800c5bc: 9301 str r3, [sp, #4] - 800c5be: fa1f f38a uxth.w r3, sl - 800c5c2: 1a5b subs r3, r3, r1 - 800c5c4: 0c00 lsrs r0, r0, #16 - 800c5c6: 4463 add r3, ip - 800c5c8: ebc0 401a rsb r0, r0, sl, lsr #16 - 800c5cc: eb00 4023 add.w r0, r0, r3, asr #16 - 800c5d0: b29b uxth r3, r3 - 800c5d2: ea43 4300 orr.w r3, r3, r0, lsl #16 - 800c5d6: 4576 cmp r6, lr - 800c5d8: ea4f 4c20 mov.w ip, r0, asr #16 - 800c5dc: f849 3b04 str.w r3, [r9], #4 - 800c5e0: d8e6 bhi.n 800c5b0 <__mdiff+0x88> - 800c5e2: 1b33 subs r3, r6, r4 - 800c5e4: 3b15 subs r3, #21 - 800c5e6: f023 0303 bic.w r3, r3, #3 - 800c5ea: 3415 adds r4, #21 - 800c5ec: 3304 adds r3, #4 - 800c5ee: 42a6 cmp r6, r4 - 800c5f0: bf38 it cc - 800c5f2: 2304 movcc r3, #4 - 800c5f4: 441d add r5, r3 - 800c5f6: 445b add r3, fp - 800c5f8: 461e mov r6, r3 - 800c5fa: 462c mov r4, r5 - 800c5fc: 4544 cmp r4, r8 - 800c5fe: d30e bcc.n 800c61e <__mdiff+0xf6> - 800c600: f108 0103 add.w r1, r8, #3 - 800c604: 1b49 subs r1, r1, r5 - 800c606: f021 0103 bic.w r1, r1, #3 - 800c60a: 3d03 subs r5, #3 - 800c60c: 45a8 cmp r8, r5 - 800c60e: bf38 it cc - 800c610: 2100 movcc r1, #0 - 800c612: 440b add r3, r1 - 800c614: f853 1d04 ldr.w r1, [r3, #-4]! - 800c618: b199 cbz r1, 800c642 <__mdiff+0x11a> - 800c61a: 6117 str r7, [r2, #16] - 800c61c: e79e b.n 800c55c <__mdiff+0x34> - 800c61e: 46e6 mov lr, ip - 800c620: f854 1b04 ldr.w r1, [r4], #4 - 800c624: fa1f fc81 uxth.w ip, r1 - 800c628: 44f4 add ip, lr - 800c62a: 0c08 lsrs r0, r1, #16 - 800c62c: 4471 add r1, lr - 800c62e: eb00 402c add.w r0, r0, ip, asr #16 - 800c632: b289 uxth r1, r1 - 800c634: ea41 4100 orr.w r1, r1, r0, lsl #16 - 800c638: ea4f 4c20 mov.w ip, r0, asr #16 - 800c63c: f846 1b04 str.w r1, [r6], #4 - 800c640: e7dc b.n 800c5fc <__mdiff+0xd4> - 800c642: 3f01 subs r7, #1 - 800c644: e7e6 b.n 800c614 <__mdiff+0xec> - 800c646: bf00 nop - 800c648: 0800e24f .word 0x0800e24f - 800c64c: 0800e271 .word 0x0800e271 - -0800c650 <__d2b>: - 800c650: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} - 800c654: 2101 movs r1, #1 - 800c656: 4690 mov r8, r2 - 800c658: 4699 mov r9, r3 - 800c65a: 9e08 ldr r6, [sp, #32] - 800c65c: f7ff fcd0 bl 800c000 <_Balloc> - 800c660: 4604 mov r4, r0 - 800c662: b930 cbnz r0, 800c672 <__d2b+0x22> - 800c664: 4602 mov r2, r0 - 800c666: f240 310f movw r1, #783 @ 0x30f - 800c66a: 4b23 ldr r3, [pc, #140] @ (800c6f8 <__d2b+0xa8>) - 800c66c: 4823 ldr r0, [pc, #140] @ (800c6fc <__d2b+0xac>) - 800c66e: f7fe fa19 bl 800aaa4 <__assert_func> - 800c672: f3c9 550a ubfx r5, r9, #20, #11 - 800c676: f3c9 0313 ubfx r3, r9, #0, #20 - 800c67a: b10d cbz r5, 800c680 <__d2b+0x30> - 800c67c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 800c680: 9301 str r3, [sp, #4] - 800c682: f1b8 0300 subs.w r3, r8, #0 - 800c686: d024 beq.n 800c6d2 <__d2b+0x82> - 800c688: 4668 mov r0, sp - 800c68a: 9300 str r3, [sp, #0] - 800c68c: f7ff fd7f bl 800c18e <__lo0bits> - 800c690: e9dd 1200 ldrd r1, r2, [sp] - 800c694: b1d8 cbz r0, 800c6ce <__d2b+0x7e> - 800c696: f1c0 0320 rsb r3, r0, #32 - 800c69a: fa02 f303 lsl.w r3, r2, r3 - 800c69e: 430b orrs r3, r1 - 800c6a0: 40c2 lsrs r2, r0 - 800c6a2: 6163 str r3, [r4, #20] - 800c6a4: 9201 str r2, [sp, #4] - 800c6a6: 9b01 ldr r3, [sp, #4] - 800c6a8: 2b00 cmp r3, #0 - 800c6aa: bf0c ite eq - 800c6ac: 2201 moveq r2, #1 - 800c6ae: 2202 movne r2, #2 - 800c6b0: 61a3 str r3, [r4, #24] - 800c6b2: 6122 str r2, [r4, #16] - 800c6b4: b1ad cbz r5, 800c6e2 <__d2b+0x92> - 800c6b6: f2a5 4533 subw r5, r5, #1075 @ 0x433 - 800c6ba: 4405 add r5, r0 - 800c6bc: 6035 str r5, [r6, #0] - 800c6be: f1c0 0035 rsb r0, r0, #53 @ 0x35 - 800c6c2: 9b09 ldr r3, [sp, #36] @ 0x24 - 800c6c4: 6018 str r0, [r3, #0] - 800c6c6: 4620 mov r0, r4 - 800c6c8: b002 add sp, #8 - 800c6ca: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} - 800c6ce: 6161 str r1, [r4, #20] - 800c6d0: e7e9 b.n 800c6a6 <__d2b+0x56> - 800c6d2: a801 add r0, sp, #4 - 800c6d4: f7ff fd5b bl 800c18e <__lo0bits> - 800c6d8: 9b01 ldr r3, [sp, #4] - 800c6da: 2201 movs r2, #1 - 800c6dc: 6163 str r3, [r4, #20] - 800c6de: 3020 adds r0, #32 - 800c6e0: e7e7 b.n 800c6b2 <__d2b+0x62> - 800c6e2: f2a0 4032 subw r0, r0, #1074 @ 0x432 - 800c6e6: eb04 0382 add.w r3, r4, r2, lsl #2 - 800c6ea: 6030 str r0, [r6, #0] - 800c6ec: 6918 ldr r0, [r3, #16] - 800c6ee: f7ff fd2f bl 800c150 <__hi0bits> - 800c6f2: ebc0 1042 rsb r0, r0, r2, lsl #5 - 800c6f6: e7e4 b.n 800c6c2 <__d2b+0x72> - 800c6f8: 0800e24f .word 0x0800e24f - 800c6fc: 0800e271 .word 0x0800e271 - -0800c700 : - 800c700: b40e push {r1, r2, r3} - 800c702: f44f 7201 mov.w r2, #516 @ 0x204 - 800c706: b530 push {r4, r5, lr} - 800c708: b09c sub sp, #112 @ 0x70 - 800c70a: ac1f add r4, sp, #124 @ 0x7c - 800c70c: f854 5b04 ldr.w r5, [r4], #4 - 800c710: f8ad 2014 strh.w r2, [sp, #20] - 800c714: 9002 str r0, [sp, #8] - 800c716: 9006 str r0, [sp, #24] - 800c718: f7f3 fd86 bl 8000228 - 800c71c: 4b0b ldr r3, [pc, #44] @ (800c74c ) - 800c71e: 9003 str r0, [sp, #12] - 800c720: 930b str r3, [sp, #44] @ 0x2c - 800c722: 2300 movs r3, #0 - 800c724: 930f str r3, [sp, #60] @ 0x3c - 800c726: 9314 str r3, [sp, #80] @ 0x50 - 800c728: f64f 73ff movw r3, #65535 @ 0xffff - 800c72c: 9007 str r0, [sp, #28] - 800c72e: 4808 ldr r0, [pc, #32] @ (800c750 ) - 800c730: f8ad 3016 strh.w r3, [sp, #22] - 800c734: 462a mov r2, r5 - 800c736: 4623 mov r3, r4 - 800c738: a902 add r1, sp, #8 - 800c73a: 6800 ldr r0, [r0, #0] - 800c73c: 9401 str r4, [sp, #4] - 800c73e: f000 fb59 bl 800cdf4 <__ssvfiscanf_r> - 800c742: b01c add sp, #112 @ 0x70 - 800c744: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 800c748: b003 add sp, #12 - 800c74a: 4770 bx lr - 800c74c: 0800c777 .word 0x0800c777 - 800c750: 20000028 .word 0x20000028 - -0800c754 <__sread>: - 800c754: b510 push {r4, lr} - 800c756: 460c mov r4, r1 - 800c758: f9b1 100e ldrsh.w r1, [r1, #14] - 800c75c: f000 fa4e bl 800cbfc <_read_r> - 800c760: 2800 cmp r0, #0 - 800c762: bfab itete ge - 800c764: 6d63 ldrge r3, [r4, #84] @ 0x54 - 800c766: 89a3 ldrhlt r3, [r4, #12] - 800c768: 181b addge r3, r3, r0 - 800c76a: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 - 800c76e: bfac ite ge - 800c770: 6563 strge r3, [r4, #84] @ 0x54 - 800c772: 81a3 strhlt r3, [r4, #12] - 800c774: bd10 pop {r4, pc} - -0800c776 <__seofread>: - 800c776: 2000 movs r0, #0 - 800c778: 4770 bx lr - -0800c77a <__swrite>: - 800c77a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800c77e: 461f mov r7, r3 - 800c780: 898b ldrh r3, [r1, #12] - 800c782: 4605 mov r5, r0 - 800c784: 05db lsls r3, r3, #23 - 800c786: 460c mov r4, r1 - 800c788: 4616 mov r6, r2 - 800c78a: d505 bpl.n 800c798 <__swrite+0x1e> - 800c78c: 2302 movs r3, #2 - 800c78e: 2200 movs r2, #0 - 800c790: f9b1 100e ldrsh.w r1, [r1, #14] - 800c794: f000 fa20 bl 800cbd8 <_lseek_r> - 800c798: 89a3 ldrh r3, [r4, #12] - 800c79a: 4632 mov r2, r6 - 800c79c: f423 5380 bic.w r3, r3, #4096 @ 0x1000 - 800c7a0: 81a3 strh r3, [r4, #12] - 800c7a2: 4628 mov r0, r5 - 800c7a4: 463b mov r3, r7 - 800c7a6: f9b4 100e ldrsh.w r1, [r4, #14] - 800c7aa: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 800c7ae: f000 ba47 b.w 800cc40 <_write_r> - -0800c7b2 <__sseek>: - 800c7b2: b510 push {r4, lr} - 800c7b4: 460c mov r4, r1 - 800c7b6: f9b1 100e ldrsh.w r1, [r1, #14] - 800c7ba: f000 fa0d bl 800cbd8 <_lseek_r> - 800c7be: 1c43 adds r3, r0, #1 - 800c7c0: 89a3 ldrh r3, [r4, #12] - 800c7c2: bf15 itete ne - 800c7c4: 6560 strne r0, [r4, #84] @ 0x54 - 800c7c6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 - 800c7ca: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 - 800c7ce: 81a3 strheq r3, [r4, #12] - 800c7d0: bf18 it ne - 800c7d2: 81a3 strhne r3, [r4, #12] - 800c7d4: bd10 pop {r4, pc} - -0800c7d6 <__sclose>: - 800c7d6: f9b1 100e ldrsh.w r1, [r1, #14] - 800c7da: f000 b9cb b.w 800cb74 <_close_r> - ... - -0800c7e0 : - 800c7e0: b40e push {r1, r2, r3} - 800c7e2: b503 push {r0, r1, lr} - 800c7e4: 4601 mov r1, r0 - 800c7e6: ab03 add r3, sp, #12 - 800c7e8: 4805 ldr r0, [pc, #20] @ (800c800 ) - 800c7ea: f853 2b04 ldr.w r2, [r3], #4 - 800c7ee: 6800 ldr r0, [r0, #0] - 800c7f0: 9301 str r3, [sp, #4] - 800c7f2: f7ff f987 bl 800bb04 <_vfiprintf_r> - 800c7f6: b002 add sp, #8 - 800c7f8: f85d eb04 ldr.w lr, [sp], #4 - 800c7fc: b003 add sp, #12 - 800c7fe: 4770 bx lr - 800c800: 20000028 .word 0x20000028 - -0800c804 <_realloc_r>: - 800c804: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800c808: 4680 mov r8, r0 - 800c80a: 4615 mov r5, r2 - 800c80c: 460c mov r4, r1 - 800c80e: b921 cbnz r1, 800c81a <_realloc_r+0x16> - 800c810: 4611 mov r1, r2 - 800c812: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 800c816: f7ff babf b.w 800bd98 <_malloc_r> - 800c81a: b92a cbnz r2, 800c828 <_realloc_r+0x24> - 800c81c: f000 fa4a bl 800ccb4 <_free_r> - 800c820: 2400 movs r4, #0 - 800c822: 4620 mov r0, r4 - 800c824: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 800c828: f000 fded bl 800d406 <_malloc_usable_size_r> - 800c82c: 4285 cmp r5, r0 - 800c82e: 4606 mov r6, r0 - 800c830: d802 bhi.n 800c838 <_realloc_r+0x34> - 800c832: ebb5 0f50 cmp.w r5, r0, lsr #1 - 800c836: d8f4 bhi.n 800c822 <_realloc_r+0x1e> - 800c838: 4629 mov r1, r5 - 800c83a: 4640 mov r0, r8 - 800c83c: f7ff faac bl 800bd98 <_malloc_r> - 800c840: 4607 mov r7, r0 - 800c842: 2800 cmp r0, #0 - 800c844: d0ec beq.n 800c820 <_realloc_r+0x1c> - 800c846: 42b5 cmp r5, r6 - 800c848: 462a mov r2, r5 - 800c84a: 4621 mov r1, r4 - 800c84c: bf28 it cs - 800c84e: 4632 movcs r2, r6 - 800c850: f7fe f911 bl 800aa76 - 800c854: 4621 mov r1, r4 - 800c856: 4640 mov r0, r8 - 800c858: f000 fa2c bl 800ccb4 <_free_r> - 800c85c: 463c mov r4, r7 - 800c85e: e7e0 b.n 800c822 <_realloc_r+0x1e> - -0800c860 <_strtoul_l.constprop.0>: - 800c860: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} - 800c864: 4686 mov lr, r0 - 800c866: 460d mov r5, r1 - 800c868: 4e33 ldr r6, [pc, #204] @ (800c938 <_strtoul_l.constprop.0+0xd8>) - 800c86a: 4628 mov r0, r5 - 800c86c: f815 4b01 ldrb.w r4, [r5], #1 - 800c870: 5d37 ldrb r7, [r6, r4] - 800c872: f017 0708 ands.w r7, r7, #8 - 800c876: d1f8 bne.n 800c86a <_strtoul_l.constprop.0+0xa> - 800c878: 2c2d cmp r4, #45 @ 0x2d - 800c87a: d12f bne.n 800c8dc <_strtoul_l.constprop.0+0x7c> - 800c87c: 2701 movs r7, #1 - 800c87e: 782c ldrb r4, [r5, #0] - 800c880: 1c85 adds r5, r0, #2 - 800c882: f033 0010 bics.w r0, r3, #16 - 800c886: d109 bne.n 800c89c <_strtoul_l.constprop.0+0x3c> - 800c888: 2c30 cmp r4, #48 @ 0x30 - 800c88a: d12c bne.n 800c8e6 <_strtoul_l.constprop.0+0x86> - 800c88c: 7828 ldrb r0, [r5, #0] - 800c88e: f000 00df and.w r0, r0, #223 @ 0xdf - 800c892: 2858 cmp r0, #88 @ 0x58 - 800c894: d127 bne.n 800c8e6 <_strtoul_l.constprop.0+0x86> - 800c896: 2310 movs r3, #16 - 800c898: 786c ldrb r4, [r5, #1] - 800c89a: 3502 adds r5, #2 - 800c89c: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff - 800c8a0: fbb8 f8f3 udiv r8, r8, r3 - 800c8a4: 2600 movs r6, #0 - 800c8a6: fb03 f908 mul.w r9, r3, r8 - 800c8aa: 4630 mov r0, r6 - 800c8ac: ea6f 0909 mvn.w r9, r9 - 800c8b0: f1a4 0c30 sub.w ip, r4, #48 @ 0x30 - 800c8b4: f1bc 0f09 cmp.w ip, #9 - 800c8b8: d81c bhi.n 800c8f4 <_strtoul_l.constprop.0+0x94> - 800c8ba: 4664 mov r4, ip - 800c8bc: 42a3 cmp r3, r4 - 800c8be: dd2a ble.n 800c916 <_strtoul_l.constprop.0+0xb6> - 800c8c0: f1b6 3fff cmp.w r6, #4294967295 @ 0xffffffff - 800c8c4: d007 beq.n 800c8d6 <_strtoul_l.constprop.0+0x76> - 800c8c6: 4580 cmp r8, r0 - 800c8c8: d322 bcc.n 800c910 <_strtoul_l.constprop.0+0xb0> - 800c8ca: d101 bne.n 800c8d0 <_strtoul_l.constprop.0+0x70> - 800c8cc: 45a1 cmp r9, r4 - 800c8ce: db1f blt.n 800c910 <_strtoul_l.constprop.0+0xb0> - 800c8d0: 2601 movs r6, #1 - 800c8d2: fb00 4003 mla r0, r0, r3, r4 - 800c8d6: f815 4b01 ldrb.w r4, [r5], #1 - 800c8da: e7e9 b.n 800c8b0 <_strtoul_l.constprop.0+0x50> - 800c8dc: 2c2b cmp r4, #43 @ 0x2b - 800c8de: bf04 itt eq - 800c8e0: 782c ldrbeq r4, [r5, #0] - 800c8e2: 1c85 addeq r5, r0, #2 - 800c8e4: e7cd b.n 800c882 <_strtoul_l.constprop.0+0x22> - 800c8e6: 2b00 cmp r3, #0 - 800c8e8: d1d8 bne.n 800c89c <_strtoul_l.constprop.0+0x3c> - 800c8ea: 2c30 cmp r4, #48 @ 0x30 - 800c8ec: bf0c ite eq - 800c8ee: 2308 moveq r3, #8 - 800c8f0: 230a movne r3, #10 - 800c8f2: e7d3 b.n 800c89c <_strtoul_l.constprop.0+0x3c> - 800c8f4: f1a4 0c41 sub.w ip, r4, #65 @ 0x41 - 800c8f8: f1bc 0f19 cmp.w ip, #25 - 800c8fc: d801 bhi.n 800c902 <_strtoul_l.constprop.0+0xa2> - 800c8fe: 3c37 subs r4, #55 @ 0x37 - 800c900: e7dc b.n 800c8bc <_strtoul_l.constprop.0+0x5c> - 800c902: f1a4 0c61 sub.w ip, r4, #97 @ 0x61 - 800c906: f1bc 0f19 cmp.w ip, #25 - 800c90a: d804 bhi.n 800c916 <_strtoul_l.constprop.0+0xb6> - 800c90c: 3c57 subs r4, #87 @ 0x57 - 800c90e: e7d5 b.n 800c8bc <_strtoul_l.constprop.0+0x5c> - 800c910: f04f 36ff mov.w r6, #4294967295 @ 0xffffffff - 800c914: e7df b.n 800c8d6 <_strtoul_l.constprop.0+0x76> - 800c916: 1c73 adds r3, r6, #1 - 800c918: d106 bne.n 800c928 <_strtoul_l.constprop.0+0xc8> - 800c91a: 2322 movs r3, #34 @ 0x22 - 800c91c: 4630 mov r0, r6 - 800c91e: f8ce 3000 str.w r3, [lr] - 800c922: b932 cbnz r2, 800c932 <_strtoul_l.constprop.0+0xd2> - 800c924: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} - 800c928: b107 cbz r7, 800c92c <_strtoul_l.constprop.0+0xcc> - 800c92a: 4240 negs r0, r0 - 800c92c: 2a00 cmp r2, #0 - 800c92e: d0f9 beq.n 800c924 <_strtoul_l.constprop.0+0xc4> - 800c930: b106 cbz r6, 800c934 <_strtoul_l.constprop.0+0xd4> - 800c932: 1e69 subs r1, r5, #1 - 800c934: 6011 str r1, [r2, #0] - 800c936: e7f5 b.n 800c924 <_strtoul_l.constprop.0+0xc4> - 800c938: 0800e3d3 .word 0x0800e3d3 - -0800c93c <_strtoul_r>: - 800c93c: f7ff bf90 b.w 800c860 <_strtoul_l.constprop.0> - -0800c940 : - 800c940: 4613 mov r3, r2 - 800c942: 460a mov r2, r1 - 800c944: 4601 mov r1, r0 - 800c946: 4802 ldr r0, [pc, #8] @ (800c950 ) - 800c948: 6800 ldr r0, [r0, #0] - 800c94a: f7ff bf89 b.w 800c860 <_strtoul_l.constprop.0> - 800c94e: bf00 nop - 800c950: 20000028 .word 0x20000028 - -0800c954 <__swbuf_r>: - 800c954: b5f8 push {r3, r4, r5, r6, r7, lr} - 800c956: 460e mov r6, r1 - 800c958: 4614 mov r4, r2 - 800c95a: 4605 mov r5, r0 - 800c95c: b118 cbz r0, 800c966 <__swbuf_r+0x12> - 800c95e: 6a03 ldr r3, [r0, #32] - 800c960: b90b cbnz r3, 800c966 <__swbuf_r+0x12> - 800c962: f7fd fa9b bl 8009e9c <__sinit> - 800c966: 69a3 ldr r3, [r4, #24] - 800c968: 60a3 str r3, [r4, #8] - 800c96a: 89a3 ldrh r3, [r4, #12] - 800c96c: 071a lsls r2, r3, #28 - 800c96e: d501 bpl.n 800c974 <__swbuf_r+0x20> - 800c970: 6923 ldr r3, [r4, #16] - 800c972: b943 cbnz r3, 800c986 <__swbuf_r+0x32> - 800c974: 4621 mov r1, r4 - 800c976: 4628 mov r0, r5 - 800c978: f000 f82a bl 800c9d0 <__swsetup_r> - 800c97c: b118 cbz r0, 800c986 <__swbuf_r+0x32> - 800c97e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff - 800c982: 4638 mov r0, r7 - 800c984: bdf8 pop {r3, r4, r5, r6, r7, pc} - 800c986: 6823 ldr r3, [r4, #0] - 800c988: 6922 ldr r2, [r4, #16] - 800c98a: b2f6 uxtb r6, r6 - 800c98c: 1a98 subs r0, r3, r2 - 800c98e: 6963 ldr r3, [r4, #20] - 800c990: 4637 mov r7, r6 - 800c992: 4283 cmp r3, r0 - 800c994: dc05 bgt.n 800c9a2 <__swbuf_r+0x4e> - 800c996: 4621 mov r1, r4 - 800c998: 4628 mov r0, r5 - 800c99a: f7ff fafd bl 800bf98 <_fflush_r> - 800c99e: 2800 cmp r0, #0 - 800c9a0: d1ed bne.n 800c97e <__swbuf_r+0x2a> - 800c9a2: 68a3 ldr r3, [r4, #8] - 800c9a4: 3b01 subs r3, #1 - 800c9a6: 60a3 str r3, [r4, #8] - 800c9a8: 6823 ldr r3, [r4, #0] - 800c9aa: 1c5a adds r2, r3, #1 - 800c9ac: 6022 str r2, [r4, #0] - 800c9ae: 701e strb r6, [r3, #0] - 800c9b0: 6962 ldr r2, [r4, #20] - 800c9b2: 1c43 adds r3, r0, #1 - 800c9b4: 429a cmp r2, r3 - 800c9b6: d004 beq.n 800c9c2 <__swbuf_r+0x6e> - 800c9b8: 89a3 ldrh r3, [r4, #12] - 800c9ba: 07db lsls r3, r3, #31 - 800c9bc: d5e1 bpl.n 800c982 <__swbuf_r+0x2e> - 800c9be: 2e0a cmp r6, #10 - 800c9c0: d1df bne.n 800c982 <__swbuf_r+0x2e> - 800c9c2: 4621 mov r1, r4 - 800c9c4: 4628 mov r0, r5 - 800c9c6: f7ff fae7 bl 800bf98 <_fflush_r> - 800c9ca: 2800 cmp r0, #0 - 800c9cc: d0d9 beq.n 800c982 <__swbuf_r+0x2e> - 800c9ce: e7d6 b.n 800c97e <__swbuf_r+0x2a> - -0800c9d0 <__swsetup_r>: - 800c9d0: b538 push {r3, r4, r5, lr} - 800c9d2: 4b29 ldr r3, [pc, #164] @ (800ca78 <__swsetup_r+0xa8>) - 800c9d4: 4605 mov r5, r0 - 800c9d6: 6818 ldr r0, [r3, #0] - 800c9d8: 460c mov r4, r1 - 800c9da: b118 cbz r0, 800c9e4 <__swsetup_r+0x14> - 800c9dc: 6a03 ldr r3, [r0, #32] - 800c9de: b90b cbnz r3, 800c9e4 <__swsetup_r+0x14> - 800c9e0: f7fd fa5c bl 8009e9c <__sinit> - 800c9e4: f9b4 300c ldrsh.w r3, [r4, #12] - 800c9e8: 0719 lsls r1, r3, #28 - 800c9ea: d422 bmi.n 800ca32 <__swsetup_r+0x62> - 800c9ec: 06da lsls r2, r3, #27 - 800c9ee: d407 bmi.n 800ca00 <__swsetup_r+0x30> - 800c9f0: 2209 movs r2, #9 - 800c9f2: 602a str r2, [r5, #0] - 800c9f4: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800c9f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800c9fc: 81a3 strh r3, [r4, #12] - 800c9fe: e033 b.n 800ca68 <__swsetup_r+0x98> - 800ca00: 0758 lsls r0, r3, #29 - 800ca02: d512 bpl.n 800ca2a <__swsetup_r+0x5a> - 800ca04: 6b61 ldr r1, [r4, #52] @ 0x34 - 800ca06: b141 cbz r1, 800ca1a <__swsetup_r+0x4a> - 800ca08: f104 0344 add.w r3, r4, #68 @ 0x44 - 800ca0c: 4299 cmp r1, r3 - 800ca0e: d002 beq.n 800ca16 <__swsetup_r+0x46> - 800ca10: 4628 mov r0, r5 - 800ca12: f000 f94f bl 800ccb4 <_free_r> - 800ca16: 2300 movs r3, #0 - 800ca18: 6363 str r3, [r4, #52] @ 0x34 - 800ca1a: 89a3 ldrh r3, [r4, #12] - 800ca1c: f023 0324 bic.w r3, r3, #36 @ 0x24 - 800ca20: 81a3 strh r3, [r4, #12] - 800ca22: 2300 movs r3, #0 - 800ca24: 6063 str r3, [r4, #4] - 800ca26: 6923 ldr r3, [r4, #16] - 800ca28: 6023 str r3, [r4, #0] - 800ca2a: 89a3 ldrh r3, [r4, #12] - 800ca2c: f043 0308 orr.w r3, r3, #8 - 800ca30: 81a3 strh r3, [r4, #12] - 800ca32: 6923 ldr r3, [r4, #16] - 800ca34: b94b cbnz r3, 800ca4a <__swsetup_r+0x7a> - 800ca36: 89a3 ldrh r3, [r4, #12] - 800ca38: f403 7320 and.w r3, r3, #640 @ 0x280 - 800ca3c: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 800ca40: d003 beq.n 800ca4a <__swsetup_r+0x7a> - 800ca42: 4621 mov r1, r4 - 800ca44: 4628 mov r0, r5 - 800ca46: f000 f83e bl 800cac6 <__smakebuf_r> - 800ca4a: f9b4 300c ldrsh.w r3, [r4, #12] - 800ca4e: f013 0201 ands.w r2, r3, #1 - 800ca52: d00a beq.n 800ca6a <__swsetup_r+0x9a> - 800ca54: 2200 movs r2, #0 - 800ca56: 60a2 str r2, [r4, #8] - 800ca58: 6962 ldr r2, [r4, #20] - 800ca5a: 4252 negs r2, r2 - 800ca5c: 61a2 str r2, [r4, #24] - 800ca5e: 6922 ldr r2, [r4, #16] - 800ca60: b942 cbnz r2, 800ca74 <__swsetup_r+0xa4> - 800ca62: f013 0080 ands.w r0, r3, #128 @ 0x80 - 800ca66: d1c5 bne.n 800c9f4 <__swsetup_r+0x24> - 800ca68: bd38 pop {r3, r4, r5, pc} - 800ca6a: 0799 lsls r1, r3, #30 - 800ca6c: bf58 it pl - 800ca6e: 6962 ldrpl r2, [r4, #20] - 800ca70: 60a2 str r2, [r4, #8] - 800ca72: e7f4 b.n 800ca5e <__swsetup_r+0x8e> - 800ca74: 2000 movs r0, #0 - 800ca76: e7f7 b.n 800ca68 <__swsetup_r+0x98> - 800ca78: 20000028 .word 0x20000028 - -0800ca7c <__swhatbuf_r>: - 800ca7c: b570 push {r4, r5, r6, lr} - 800ca7e: 460c mov r4, r1 - 800ca80: f9b1 100e ldrsh.w r1, [r1, #14] - 800ca84: 4615 mov r5, r2 - 800ca86: 2900 cmp r1, #0 - 800ca88: 461e mov r6, r3 - 800ca8a: b096 sub sp, #88 @ 0x58 - 800ca8c: da0c bge.n 800caa8 <__swhatbuf_r+0x2c> - 800ca8e: 89a3 ldrh r3, [r4, #12] - 800ca90: 2100 movs r1, #0 - 800ca92: f013 0f80 tst.w r3, #128 @ 0x80 - 800ca96: bf14 ite ne - 800ca98: 2340 movne r3, #64 @ 0x40 - 800ca9a: f44f 6380 moveq.w r3, #1024 @ 0x400 - 800ca9e: 2000 movs r0, #0 - 800caa0: 6031 str r1, [r6, #0] - 800caa2: 602b str r3, [r5, #0] - 800caa4: b016 add sp, #88 @ 0x58 - 800caa6: bd70 pop {r4, r5, r6, pc} - 800caa8: 466a mov r2, sp - 800caaa: f000 f873 bl 800cb94 <_fstat_r> - 800caae: 2800 cmp r0, #0 - 800cab0: dbed blt.n 800ca8e <__swhatbuf_r+0x12> - 800cab2: 9901 ldr r1, [sp, #4] - 800cab4: f401 4170 and.w r1, r1, #61440 @ 0xf000 - 800cab8: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 - 800cabc: 4259 negs r1, r3 - 800cabe: 4159 adcs r1, r3 - 800cac0: f44f 6380 mov.w r3, #1024 @ 0x400 - 800cac4: e7eb b.n 800ca9e <__swhatbuf_r+0x22> - -0800cac6 <__smakebuf_r>: - 800cac6: 898b ldrh r3, [r1, #12] - 800cac8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} - 800caca: 079d lsls r5, r3, #30 - 800cacc: 4606 mov r6, r0 - 800cace: 460c mov r4, r1 - 800cad0: d507 bpl.n 800cae2 <__smakebuf_r+0x1c> - 800cad2: f104 0347 add.w r3, r4, #71 @ 0x47 - 800cad6: 6023 str r3, [r4, #0] - 800cad8: 6123 str r3, [r4, #16] - 800cada: 2301 movs r3, #1 - 800cadc: 6163 str r3, [r4, #20] - 800cade: b003 add sp, #12 - 800cae0: bdf0 pop {r4, r5, r6, r7, pc} - 800cae2: 466a mov r2, sp - 800cae4: ab01 add r3, sp, #4 - 800cae6: f7ff ffc9 bl 800ca7c <__swhatbuf_r> - 800caea: 9f00 ldr r7, [sp, #0] - 800caec: 4605 mov r5, r0 - 800caee: 4639 mov r1, r7 - 800caf0: 4630 mov r0, r6 - 800caf2: f7ff f951 bl 800bd98 <_malloc_r> - 800caf6: b948 cbnz r0, 800cb0c <__smakebuf_r+0x46> - 800caf8: f9b4 300c ldrsh.w r3, [r4, #12] - 800cafc: 059a lsls r2, r3, #22 - 800cafe: d4ee bmi.n 800cade <__smakebuf_r+0x18> - 800cb00: f023 0303 bic.w r3, r3, #3 - 800cb04: f043 0302 orr.w r3, r3, #2 - 800cb08: 81a3 strh r3, [r4, #12] - 800cb0a: e7e2 b.n 800cad2 <__smakebuf_r+0xc> - 800cb0c: 89a3 ldrh r3, [r4, #12] - 800cb0e: e9c4 0704 strd r0, r7, [r4, #16] - 800cb12: f043 0380 orr.w r3, r3, #128 @ 0x80 - 800cb16: 81a3 strh r3, [r4, #12] - 800cb18: 9b01 ldr r3, [sp, #4] - 800cb1a: 6020 str r0, [r4, #0] - 800cb1c: b15b cbz r3, 800cb36 <__smakebuf_r+0x70> - 800cb1e: 4630 mov r0, r6 - 800cb20: f9b4 100e ldrsh.w r1, [r4, #14] - 800cb24: f000 f848 bl 800cbb8 <_isatty_r> - 800cb28: b128 cbz r0, 800cb36 <__smakebuf_r+0x70> - 800cb2a: 89a3 ldrh r3, [r4, #12] - 800cb2c: f023 0303 bic.w r3, r3, #3 - 800cb30: f043 0301 orr.w r3, r3, #1 - 800cb34: 81a3 strh r3, [r4, #12] - 800cb36: 89a3 ldrh r3, [r4, #12] - 800cb38: 431d orrs r5, r3 - 800cb3a: 81a5 strh r5, [r4, #12] - 800cb3c: e7cf b.n 800cade <__smakebuf_r+0x18> - -0800cb3e : - 800cb3e: 4288 cmp r0, r1 - 800cb40: b510 push {r4, lr} - 800cb42: eb01 0402 add.w r4, r1, r2 - 800cb46: d902 bls.n 800cb4e - 800cb48: 4284 cmp r4, r0 - 800cb4a: 4623 mov r3, r4 - 800cb4c: d807 bhi.n 800cb5e - 800cb4e: 1e43 subs r3, r0, #1 - 800cb50: 42a1 cmp r1, r4 - 800cb52: d008 beq.n 800cb66 - 800cb54: f811 2b01 ldrb.w r2, [r1], #1 - 800cb58: f803 2f01 strb.w r2, [r3, #1]! - 800cb5c: e7f8 b.n 800cb50 - 800cb5e: 4601 mov r1, r0 - 800cb60: 4402 add r2, r0 - 800cb62: 428a cmp r2, r1 - 800cb64: d100 bne.n 800cb68 - 800cb66: bd10 pop {r4, pc} - 800cb68: f813 4d01 ldrb.w r4, [r3, #-1]! - 800cb6c: f802 4d01 strb.w r4, [r2, #-1]! - 800cb70: e7f7 b.n 800cb62 - ... - -0800cb74 <_close_r>: - 800cb74: b538 push {r3, r4, r5, lr} - 800cb76: 2300 movs r3, #0 - 800cb78: 4d05 ldr r5, [pc, #20] @ (800cb90 <_close_r+0x1c>) - 800cb7a: 4604 mov r4, r0 - 800cb7c: 4608 mov r0, r1 - 800cb7e: 602b str r3, [r5, #0] - 800cb80: f7f8 fce1 bl 8005546 <_close> - 800cb84: 1c43 adds r3, r0, #1 - 800cb86: d102 bne.n 800cb8e <_close_r+0x1a> - 800cb88: 682b ldr r3, [r5, #0] - 800cb8a: b103 cbz r3, 800cb8e <_close_r+0x1a> - 800cb8c: 6023 str r3, [r4, #0] - 800cb8e: bd38 pop {r3, r4, r5, pc} - 800cb90: 20003508 .word 0x20003508 - -0800cb94 <_fstat_r>: - 800cb94: b538 push {r3, r4, r5, lr} - 800cb96: 2300 movs r3, #0 - 800cb98: 4d06 ldr r5, [pc, #24] @ (800cbb4 <_fstat_r+0x20>) - 800cb9a: 4604 mov r4, r0 - 800cb9c: 4608 mov r0, r1 - 800cb9e: 4611 mov r1, r2 - 800cba0: 602b str r3, [r5, #0] - 800cba2: f7f8 fcdb bl 800555c <_fstat> - 800cba6: 1c43 adds r3, r0, #1 - 800cba8: d102 bne.n 800cbb0 <_fstat_r+0x1c> - 800cbaa: 682b ldr r3, [r5, #0] - 800cbac: b103 cbz r3, 800cbb0 <_fstat_r+0x1c> - 800cbae: 6023 str r3, [r4, #0] - 800cbb0: bd38 pop {r3, r4, r5, pc} - 800cbb2: bf00 nop - 800cbb4: 20003508 .word 0x20003508 - -0800cbb8 <_isatty_r>: - 800cbb8: b538 push {r3, r4, r5, lr} - 800cbba: 2300 movs r3, #0 - 800cbbc: 4d05 ldr r5, [pc, #20] @ (800cbd4 <_isatty_r+0x1c>) - 800cbbe: 4604 mov r4, r0 - 800cbc0: 4608 mov r0, r1 - 800cbc2: 602b str r3, [r5, #0] - 800cbc4: f7f8 fcd9 bl 800557a <_isatty> - 800cbc8: 1c43 adds r3, r0, #1 - 800cbca: d102 bne.n 800cbd2 <_isatty_r+0x1a> - 800cbcc: 682b ldr r3, [r5, #0] - 800cbce: b103 cbz r3, 800cbd2 <_isatty_r+0x1a> - 800cbd0: 6023 str r3, [r4, #0] - 800cbd2: bd38 pop {r3, r4, r5, pc} - 800cbd4: 20003508 .word 0x20003508 - -0800cbd8 <_lseek_r>: - 800cbd8: b538 push {r3, r4, r5, lr} - 800cbda: 4604 mov r4, r0 - 800cbdc: 4608 mov r0, r1 - 800cbde: 4611 mov r1, r2 - 800cbe0: 2200 movs r2, #0 - 800cbe2: 4d05 ldr r5, [pc, #20] @ (800cbf8 <_lseek_r+0x20>) - 800cbe4: 602a str r2, [r5, #0] - 800cbe6: 461a mov r2, r3 - 800cbe8: f7f8 fcd1 bl 800558e <_lseek> - 800cbec: 1c43 adds r3, r0, #1 - 800cbee: d102 bne.n 800cbf6 <_lseek_r+0x1e> - 800cbf0: 682b ldr r3, [r5, #0] - 800cbf2: b103 cbz r3, 800cbf6 <_lseek_r+0x1e> - 800cbf4: 6023 str r3, [r4, #0] - 800cbf6: bd38 pop {r3, r4, r5, pc} - 800cbf8: 20003508 .word 0x20003508 - -0800cbfc <_read_r>: - 800cbfc: b538 push {r3, r4, r5, lr} - 800cbfe: 4604 mov r4, r0 - 800cc00: 4608 mov r0, r1 - 800cc02: 4611 mov r1, r2 - 800cc04: 2200 movs r2, #0 - 800cc06: 4d05 ldr r5, [pc, #20] @ (800cc1c <_read_r+0x20>) - 800cc08: 602a str r2, [r5, #0] - 800cc0a: 461a mov r2, r3 - 800cc0c: f7f8 fc7e bl 800550c <_read> - 800cc10: 1c43 adds r3, r0, #1 - 800cc12: d102 bne.n 800cc1a <_read_r+0x1e> - 800cc14: 682b ldr r3, [r5, #0] - 800cc16: b103 cbz r3, 800cc1a <_read_r+0x1e> - 800cc18: 6023 str r3, [r4, #0] - 800cc1a: bd38 pop {r3, r4, r5, pc} - 800cc1c: 20003508 .word 0x20003508 - -0800cc20 <_sbrk_r>: - 800cc20: b538 push {r3, r4, r5, lr} - 800cc22: 2300 movs r3, #0 - 800cc24: 4d05 ldr r5, [pc, #20] @ (800cc3c <_sbrk_r+0x1c>) - 800cc26: 4604 mov r4, r0 - 800cc28: 4608 mov r0, r1 - 800cc2a: 602b str r3, [r5, #0] - 800cc2c: f7f8 fcbc bl 80055a8 <_sbrk> - 800cc30: 1c43 adds r3, r0, #1 - 800cc32: d102 bne.n 800cc3a <_sbrk_r+0x1a> - 800cc34: 682b ldr r3, [r5, #0] - 800cc36: b103 cbz r3, 800cc3a <_sbrk_r+0x1a> - 800cc38: 6023 str r3, [r4, #0] - 800cc3a: bd38 pop {r3, r4, r5, pc} - 800cc3c: 20003508 .word 0x20003508 - -0800cc40 <_write_r>: - 800cc40: b538 push {r3, r4, r5, lr} - 800cc42: 4604 mov r4, r0 - 800cc44: 4608 mov r0, r1 - 800cc46: 4611 mov r1, r2 - 800cc48: 2200 movs r2, #0 - 800cc4a: 4d05 ldr r5, [pc, #20] @ (800cc60 <_write_r+0x20>) - 800cc4c: 602a str r2, [r5, #0] - 800cc4e: 461a mov r2, r3 - 800cc50: f7f6 f822 bl 8002c98 <_write> - 800cc54: 1c43 adds r3, r0, #1 - 800cc56: d102 bne.n 800cc5e <_write_r+0x1e> - 800cc58: 682b ldr r3, [r5, #0] - 800cc5a: b103 cbz r3, 800cc5e <_write_r+0x1e> - 800cc5c: 6023 str r3, [r4, #0] - 800cc5e: bd38 pop {r3, r4, r5, pc} - 800cc60: 20003508 .word 0x20003508 - -0800cc64 : - 800cc64: 2006 movs r0, #6 - 800cc66: b508 push {r3, lr} - 800cc68: f000 fcc0 bl 800d5ec - 800cc6c: 2001 movs r0, #1 - 800cc6e: f7f8 fc42 bl 80054f6 <_exit> - -0800cc72 <_calloc_r>: - 800cc72: b570 push {r4, r5, r6, lr} - 800cc74: fba1 5402 umull r5, r4, r1, r2 - 800cc78: b93c cbnz r4, 800cc8a <_calloc_r+0x18> - 800cc7a: 4629 mov r1, r5 - 800cc7c: f7ff f88c bl 800bd98 <_malloc_r> - 800cc80: 4606 mov r6, r0 - 800cc82: b928 cbnz r0, 800cc90 <_calloc_r+0x1e> - 800cc84: 2600 movs r6, #0 - 800cc86: 4630 mov r0, r6 - 800cc88: bd70 pop {r4, r5, r6, pc} - 800cc8a: 220c movs r2, #12 - 800cc8c: 6002 str r2, [r0, #0] - 800cc8e: e7f9 b.n 800cc84 <_calloc_r+0x12> - 800cc90: 462a mov r2, r5 - 800cc92: 4621 mov r1, r4 - 800cc94: f7fd f9f4 bl 800a080 - 800cc98: e7f5 b.n 800cc86 <_calloc_r+0x14> - ... - -0800cc9c <__env_lock>: - 800cc9c: 4801 ldr r0, [pc, #4] @ (800cca4 <__env_lock+0x8>) - 800cc9e: f7fd bed9 b.w 800aa54 <__retarget_lock_acquire_recursive> - 800cca2: bf00 nop - 800cca4: 200034fd .word 0x200034fd - -0800cca8 <__env_unlock>: - 800cca8: 4801 ldr r0, [pc, #4] @ (800ccb0 <__env_unlock+0x8>) - 800ccaa: f7fd bed5 b.w 800aa58 <__retarget_lock_release_recursive> - 800ccae: bf00 nop - 800ccb0: 200034fd .word 0x200034fd - -0800ccb4 <_free_r>: - 800ccb4: b538 push {r3, r4, r5, lr} - 800ccb6: 4605 mov r5, r0 - 800ccb8: 2900 cmp r1, #0 - 800ccba: d040 beq.n 800cd3e <_free_r+0x8a> - 800ccbc: f851 3c04 ldr.w r3, [r1, #-4] - 800ccc0: 1f0c subs r4, r1, #4 - 800ccc2: 2b00 cmp r3, #0 - 800ccc4: bfb8 it lt - 800ccc6: 18e4 addlt r4, r4, r3 - 800ccc8: f7ff f98e bl 800bfe8 <__malloc_lock> - 800cccc: 4a1c ldr r2, [pc, #112] @ (800cd40 <_free_r+0x8c>) - 800ccce: 6813 ldr r3, [r2, #0] - 800ccd0: b933 cbnz r3, 800cce0 <_free_r+0x2c> - 800ccd2: 6063 str r3, [r4, #4] - 800ccd4: 6014 str r4, [r2, #0] - 800ccd6: 4628 mov r0, r5 - 800ccd8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 800ccdc: f7ff b98a b.w 800bff4 <__malloc_unlock> - 800cce0: 42a3 cmp r3, r4 - 800cce2: d908 bls.n 800ccf6 <_free_r+0x42> - 800cce4: 6820 ldr r0, [r4, #0] - 800cce6: 1821 adds r1, r4, r0 - 800cce8: 428b cmp r3, r1 - 800ccea: bf01 itttt eq - 800ccec: 6819 ldreq r1, [r3, #0] - 800ccee: 685b ldreq r3, [r3, #4] - 800ccf0: 1809 addeq r1, r1, r0 - 800ccf2: 6021 streq r1, [r4, #0] - 800ccf4: e7ed b.n 800ccd2 <_free_r+0x1e> - 800ccf6: 461a mov r2, r3 - 800ccf8: 685b ldr r3, [r3, #4] - 800ccfa: b10b cbz r3, 800cd00 <_free_r+0x4c> - 800ccfc: 42a3 cmp r3, r4 - 800ccfe: d9fa bls.n 800ccf6 <_free_r+0x42> - 800cd00: 6811 ldr r1, [r2, #0] - 800cd02: 1850 adds r0, r2, r1 - 800cd04: 42a0 cmp r0, r4 - 800cd06: d10b bne.n 800cd20 <_free_r+0x6c> - 800cd08: 6820 ldr r0, [r4, #0] - 800cd0a: 4401 add r1, r0 - 800cd0c: 1850 adds r0, r2, r1 - 800cd0e: 4283 cmp r3, r0 - 800cd10: 6011 str r1, [r2, #0] - 800cd12: d1e0 bne.n 800ccd6 <_free_r+0x22> - 800cd14: 6818 ldr r0, [r3, #0] - 800cd16: 685b ldr r3, [r3, #4] - 800cd18: 4408 add r0, r1 - 800cd1a: 6010 str r0, [r2, #0] - 800cd1c: 6053 str r3, [r2, #4] - 800cd1e: e7da b.n 800ccd6 <_free_r+0x22> - 800cd20: d902 bls.n 800cd28 <_free_r+0x74> - 800cd22: 230c movs r3, #12 - 800cd24: 602b str r3, [r5, #0] - 800cd26: e7d6 b.n 800ccd6 <_free_r+0x22> - 800cd28: 6820 ldr r0, [r4, #0] - 800cd2a: 1821 adds r1, r4, r0 - 800cd2c: 428b cmp r3, r1 - 800cd2e: bf01 itttt eq - 800cd30: 6819 ldreq r1, [r3, #0] - 800cd32: 685b ldreq r3, [r3, #4] - 800cd34: 1809 addeq r1, r1, r0 - 800cd36: 6021 streq r1, [r4, #0] - 800cd38: 6063 str r3, [r4, #4] - 800cd3a: 6054 str r4, [r2, #4] - 800cd3c: e7cb b.n 800ccd6 <_free_r+0x22> - 800cd3e: bd38 pop {r3, r4, r5, pc} - 800cd40: 20003504 .word 0x20003504 - -0800cd44 <_sungetc_r>: - 800cd44: b538 push {r3, r4, r5, lr} - 800cd46: 1c4b adds r3, r1, #1 - 800cd48: 4614 mov r4, r2 - 800cd4a: d103 bne.n 800cd54 <_sungetc_r+0x10> - 800cd4c: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff - 800cd50: 4628 mov r0, r5 - 800cd52: bd38 pop {r3, r4, r5, pc} - 800cd54: 8993 ldrh r3, [r2, #12] - 800cd56: b2cd uxtb r5, r1 - 800cd58: f023 0320 bic.w r3, r3, #32 - 800cd5c: 8193 strh r3, [r2, #12] - 800cd5e: 6853 ldr r3, [r2, #4] - 800cd60: 6b52 ldr r2, [r2, #52] @ 0x34 - 800cd62: b18a cbz r2, 800cd88 <_sungetc_r+0x44> - 800cd64: 6ba2 ldr r2, [r4, #56] @ 0x38 - 800cd66: 429a cmp r2, r3 - 800cd68: dd08 ble.n 800cd7c <_sungetc_r+0x38> - 800cd6a: 6823 ldr r3, [r4, #0] - 800cd6c: 1e5a subs r2, r3, #1 - 800cd6e: 6022 str r2, [r4, #0] - 800cd70: f803 5c01 strb.w r5, [r3, #-1] - 800cd74: 6863 ldr r3, [r4, #4] - 800cd76: 3301 adds r3, #1 - 800cd78: 6063 str r3, [r4, #4] - 800cd7a: e7e9 b.n 800cd50 <_sungetc_r+0xc> - 800cd7c: 4621 mov r1, r4 - 800cd7e: f000 fb4a bl 800d416 <__submore> - 800cd82: 2800 cmp r0, #0 - 800cd84: d0f1 beq.n 800cd6a <_sungetc_r+0x26> - 800cd86: e7e1 b.n 800cd4c <_sungetc_r+0x8> - 800cd88: 6921 ldr r1, [r4, #16] - 800cd8a: 6822 ldr r2, [r4, #0] - 800cd8c: b141 cbz r1, 800cda0 <_sungetc_r+0x5c> - 800cd8e: 4291 cmp r1, r2 - 800cd90: d206 bcs.n 800cda0 <_sungetc_r+0x5c> - 800cd92: f812 1c01 ldrb.w r1, [r2, #-1] - 800cd96: 42a9 cmp r1, r5 - 800cd98: d102 bne.n 800cda0 <_sungetc_r+0x5c> - 800cd9a: 3a01 subs r2, #1 - 800cd9c: 6022 str r2, [r4, #0] - 800cd9e: e7ea b.n 800cd76 <_sungetc_r+0x32> - 800cda0: e9c4 230f strd r2, r3, [r4, #60] @ 0x3c - 800cda4: f104 0344 add.w r3, r4, #68 @ 0x44 - 800cda8: 6363 str r3, [r4, #52] @ 0x34 - 800cdaa: 2303 movs r3, #3 - 800cdac: 63a3 str r3, [r4, #56] @ 0x38 - 800cdae: 4623 mov r3, r4 - 800cdb0: f803 5f46 strb.w r5, [r3, #70]! - 800cdb4: 6023 str r3, [r4, #0] - 800cdb6: 2301 movs r3, #1 - 800cdb8: e7de b.n 800cd78 <_sungetc_r+0x34> - -0800cdba <__ssrefill_r>: - 800cdba: b510 push {r4, lr} - 800cdbc: 460c mov r4, r1 - 800cdbe: 6b49 ldr r1, [r1, #52] @ 0x34 - 800cdc0: b169 cbz r1, 800cdde <__ssrefill_r+0x24> - 800cdc2: f104 0344 add.w r3, r4, #68 @ 0x44 - 800cdc6: 4299 cmp r1, r3 - 800cdc8: d001 beq.n 800cdce <__ssrefill_r+0x14> - 800cdca: f7ff ff73 bl 800ccb4 <_free_r> - 800cdce: 2000 movs r0, #0 - 800cdd0: 6c23 ldr r3, [r4, #64] @ 0x40 - 800cdd2: 6360 str r0, [r4, #52] @ 0x34 - 800cdd4: 6063 str r3, [r4, #4] - 800cdd6: b113 cbz r3, 800cdde <__ssrefill_r+0x24> - 800cdd8: 6be3 ldr r3, [r4, #60] @ 0x3c - 800cdda: 6023 str r3, [r4, #0] - 800cddc: bd10 pop {r4, pc} - 800cdde: 6923 ldr r3, [r4, #16] - 800cde0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800cde4: 6023 str r3, [r4, #0] - 800cde6: 2300 movs r3, #0 - 800cde8: 6063 str r3, [r4, #4] - 800cdea: 89a3 ldrh r3, [r4, #12] - 800cdec: f043 0320 orr.w r3, r3, #32 - 800cdf0: 81a3 strh r3, [r4, #12] - 800cdf2: e7f3 b.n 800cddc <__ssrefill_r+0x22> - -0800cdf4 <__ssvfiscanf_r>: - 800cdf4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800cdf8: 460c mov r4, r1 - 800cdfa: 2100 movs r1, #0 - 800cdfc: 4606 mov r6, r0 - 800cdfe: f5ad 7d22 sub.w sp, sp, #648 @ 0x288 - 800ce02: e9cd 1144 strd r1, r1, [sp, #272] @ 0x110 - 800ce06: 49aa ldr r1, [pc, #680] @ (800d0b0 <__ssvfiscanf_r+0x2bc>) - 800ce08: f10d 0804 add.w r8, sp, #4 - 800ce0c: 91a0 str r1, [sp, #640] @ 0x280 - 800ce0e: 49a9 ldr r1, [pc, #676] @ (800d0b4 <__ssvfiscanf_r+0x2c0>) - 800ce10: 4fa9 ldr r7, [pc, #676] @ (800d0b8 <__ssvfiscanf_r+0x2c4>) - 800ce12: f8cd 8118 str.w r8, [sp, #280] @ 0x118 - 800ce16: 91a1 str r1, [sp, #644] @ 0x284 - 800ce18: 9300 str r3, [sp, #0] - 800ce1a: 7813 ldrb r3, [r2, #0] - 800ce1c: 2b00 cmp r3, #0 - 800ce1e: f000 8159 beq.w 800d0d4 <__ssvfiscanf_r+0x2e0> - 800ce22: 5cf9 ldrb r1, [r7, r3] - 800ce24: 1c55 adds r5, r2, #1 - 800ce26: f011 0108 ands.w r1, r1, #8 - 800ce2a: d019 beq.n 800ce60 <__ssvfiscanf_r+0x6c> - 800ce2c: 6863 ldr r3, [r4, #4] - 800ce2e: 2b00 cmp r3, #0 - 800ce30: dd0f ble.n 800ce52 <__ssvfiscanf_r+0x5e> - 800ce32: 6823 ldr r3, [r4, #0] - 800ce34: 781a ldrb r2, [r3, #0] - 800ce36: 5cba ldrb r2, [r7, r2] - 800ce38: 0712 lsls r2, r2, #28 - 800ce3a: d401 bmi.n 800ce40 <__ssvfiscanf_r+0x4c> - 800ce3c: 462a mov r2, r5 - 800ce3e: e7ec b.n 800ce1a <__ssvfiscanf_r+0x26> - 800ce40: 9a45 ldr r2, [sp, #276] @ 0x114 - 800ce42: 3301 adds r3, #1 - 800ce44: 3201 adds r2, #1 - 800ce46: 9245 str r2, [sp, #276] @ 0x114 - 800ce48: 6862 ldr r2, [r4, #4] - 800ce4a: 6023 str r3, [r4, #0] - 800ce4c: 3a01 subs r2, #1 - 800ce4e: 6062 str r2, [r4, #4] - 800ce50: e7ec b.n 800ce2c <__ssvfiscanf_r+0x38> - 800ce52: 4621 mov r1, r4 - 800ce54: 4630 mov r0, r6 - 800ce56: 9ba1 ldr r3, [sp, #644] @ 0x284 - 800ce58: 4798 blx r3 - 800ce5a: 2800 cmp r0, #0 - 800ce5c: d0e9 beq.n 800ce32 <__ssvfiscanf_r+0x3e> - 800ce5e: e7ed b.n 800ce3c <__ssvfiscanf_r+0x48> - 800ce60: 2b25 cmp r3, #37 @ 0x25 - 800ce62: d012 beq.n 800ce8a <__ssvfiscanf_r+0x96> - 800ce64: 4699 mov r9, r3 - 800ce66: 6863 ldr r3, [r4, #4] - 800ce68: 2b00 cmp r3, #0 - 800ce6a: f340 8094 ble.w 800cf96 <__ssvfiscanf_r+0x1a2> - 800ce6e: 6822 ldr r2, [r4, #0] - 800ce70: 7813 ldrb r3, [r2, #0] - 800ce72: 454b cmp r3, r9 - 800ce74: f040 812e bne.w 800d0d4 <__ssvfiscanf_r+0x2e0> - 800ce78: 6863 ldr r3, [r4, #4] - 800ce7a: 3201 adds r2, #1 - 800ce7c: 3b01 subs r3, #1 - 800ce7e: 6063 str r3, [r4, #4] - 800ce80: 9b45 ldr r3, [sp, #276] @ 0x114 - 800ce82: 6022 str r2, [r4, #0] - 800ce84: 3301 adds r3, #1 - 800ce86: 9345 str r3, [sp, #276] @ 0x114 - 800ce88: e7d8 b.n 800ce3c <__ssvfiscanf_r+0x48> - 800ce8a: 9141 str r1, [sp, #260] @ 0x104 - 800ce8c: 9143 str r1, [sp, #268] @ 0x10c - 800ce8e: 7853 ldrb r3, [r2, #1] - 800ce90: 2b2a cmp r3, #42 @ 0x2a - 800ce92: bf04 itt eq - 800ce94: 2310 moveq r3, #16 - 800ce96: 1c95 addeq r5, r2, #2 - 800ce98: f04f 020a mov.w r2, #10 - 800ce9c: bf08 it eq - 800ce9e: 9341 streq r3, [sp, #260] @ 0x104 - 800cea0: 46a9 mov r9, r5 - 800cea2: f819 1b01 ldrb.w r1, [r9], #1 - 800cea6: f1a1 0330 sub.w r3, r1, #48 @ 0x30 - 800ceaa: 2b09 cmp r3, #9 - 800ceac: d91e bls.n 800ceec <__ssvfiscanf_r+0xf8> - 800ceae: f8df a20c ldr.w sl, [pc, #524] @ 800d0bc <__ssvfiscanf_r+0x2c8> - 800ceb2: 2203 movs r2, #3 - 800ceb4: 4650 mov r0, sl - 800ceb6: f7fd fdd0 bl 800aa5a - 800ceba: b138 cbz r0, 800cecc <__ssvfiscanf_r+0xd8> - 800cebc: 2301 movs r3, #1 - 800cebe: 464d mov r5, r9 - 800cec0: 9a41 ldr r2, [sp, #260] @ 0x104 - 800cec2: eba0 000a sub.w r0, r0, sl - 800cec6: 4083 lsls r3, r0 - 800cec8: 4313 orrs r3, r2 - 800ceca: 9341 str r3, [sp, #260] @ 0x104 - 800cecc: f815 3b01 ldrb.w r3, [r5], #1 - 800ced0: 2b78 cmp r3, #120 @ 0x78 - 800ced2: d806 bhi.n 800cee2 <__ssvfiscanf_r+0xee> - 800ced4: 2b57 cmp r3, #87 @ 0x57 - 800ced6: d810 bhi.n 800cefa <__ssvfiscanf_r+0x106> - 800ced8: 2b25 cmp r3, #37 @ 0x25 - 800ceda: d0c3 beq.n 800ce64 <__ssvfiscanf_r+0x70> - 800cedc: d856 bhi.n 800cf8c <__ssvfiscanf_r+0x198> - 800cede: 2b00 cmp r3, #0 - 800cee0: d064 beq.n 800cfac <__ssvfiscanf_r+0x1b8> - 800cee2: 2303 movs r3, #3 - 800cee4: 9347 str r3, [sp, #284] @ 0x11c - 800cee6: 230a movs r3, #10 - 800cee8: 9342 str r3, [sp, #264] @ 0x108 - 800ceea: e077 b.n 800cfdc <__ssvfiscanf_r+0x1e8> - 800ceec: 9b43 ldr r3, [sp, #268] @ 0x10c - 800ceee: 464d mov r5, r9 - 800cef0: fb02 1103 mla r1, r2, r3, r1 - 800cef4: 3930 subs r1, #48 @ 0x30 - 800cef6: 9143 str r1, [sp, #268] @ 0x10c - 800cef8: e7d2 b.n 800cea0 <__ssvfiscanf_r+0xac> - 800cefa: f1a3 0258 sub.w r2, r3, #88 @ 0x58 - 800cefe: 2a20 cmp r2, #32 - 800cf00: d8ef bhi.n 800cee2 <__ssvfiscanf_r+0xee> - 800cf02: a101 add r1, pc, #4 @ (adr r1, 800cf08 <__ssvfiscanf_r+0x114>) - 800cf04: f851 f022 ldr.w pc, [r1, r2, lsl #2] - 800cf08: 0800cfbb .word 0x0800cfbb - 800cf0c: 0800cee3 .word 0x0800cee3 - 800cf10: 0800cee3 .word 0x0800cee3 - 800cf14: 0800d015 .word 0x0800d015 - 800cf18: 0800cee3 .word 0x0800cee3 - 800cf1c: 0800cee3 .word 0x0800cee3 - 800cf20: 0800cee3 .word 0x0800cee3 - 800cf24: 0800cee3 .word 0x0800cee3 - 800cf28: 0800cee3 .word 0x0800cee3 - 800cf2c: 0800cee3 .word 0x0800cee3 - 800cf30: 0800cee3 .word 0x0800cee3 - 800cf34: 0800d02b .word 0x0800d02b - 800cf38: 0800d011 .word 0x0800d011 - 800cf3c: 0800cf93 .word 0x0800cf93 - 800cf40: 0800cf93 .word 0x0800cf93 - 800cf44: 0800cf93 .word 0x0800cf93 - 800cf48: 0800cee3 .word 0x0800cee3 - 800cf4c: 0800cfcd .word 0x0800cfcd - 800cf50: 0800cee3 .word 0x0800cee3 - 800cf54: 0800cee3 .word 0x0800cee3 - 800cf58: 0800cee3 .word 0x0800cee3 - 800cf5c: 0800cee3 .word 0x0800cee3 - 800cf60: 0800d03b .word 0x0800d03b - 800cf64: 0800cfd5 .word 0x0800cfd5 - 800cf68: 0800cfb3 .word 0x0800cfb3 - 800cf6c: 0800cee3 .word 0x0800cee3 - 800cf70: 0800cee3 .word 0x0800cee3 - 800cf74: 0800d037 .word 0x0800d037 - 800cf78: 0800cee3 .word 0x0800cee3 - 800cf7c: 0800d011 .word 0x0800d011 - 800cf80: 0800cee3 .word 0x0800cee3 - 800cf84: 0800cee3 .word 0x0800cee3 - 800cf88: 0800cfbb .word 0x0800cfbb - 800cf8c: 3b45 subs r3, #69 @ 0x45 - 800cf8e: 2b02 cmp r3, #2 - 800cf90: d8a7 bhi.n 800cee2 <__ssvfiscanf_r+0xee> - 800cf92: 2305 movs r3, #5 - 800cf94: e021 b.n 800cfda <__ssvfiscanf_r+0x1e6> - 800cf96: 4621 mov r1, r4 - 800cf98: 4630 mov r0, r6 - 800cf9a: 9ba1 ldr r3, [sp, #644] @ 0x284 - 800cf9c: 4798 blx r3 - 800cf9e: 2800 cmp r0, #0 - 800cfa0: f43f af65 beq.w 800ce6e <__ssvfiscanf_r+0x7a> - 800cfa4: 9844 ldr r0, [sp, #272] @ 0x110 - 800cfa6: 2800 cmp r0, #0 - 800cfa8: f040 808c bne.w 800d0c4 <__ssvfiscanf_r+0x2d0> - 800cfac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800cfb0: e08c b.n 800d0cc <__ssvfiscanf_r+0x2d8> - 800cfb2: 9a41 ldr r2, [sp, #260] @ 0x104 - 800cfb4: f042 0220 orr.w r2, r2, #32 - 800cfb8: 9241 str r2, [sp, #260] @ 0x104 - 800cfba: 9a41 ldr r2, [sp, #260] @ 0x104 - 800cfbc: f442 7200 orr.w r2, r2, #512 @ 0x200 - 800cfc0: 9241 str r2, [sp, #260] @ 0x104 - 800cfc2: 2210 movs r2, #16 - 800cfc4: 2b6e cmp r3, #110 @ 0x6e - 800cfc6: 9242 str r2, [sp, #264] @ 0x108 - 800cfc8: d902 bls.n 800cfd0 <__ssvfiscanf_r+0x1dc> - 800cfca: e005 b.n 800cfd8 <__ssvfiscanf_r+0x1e4> - 800cfcc: 2300 movs r3, #0 - 800cfce: 9342 str r3, [sp, #264] @ 0x108 - 800cfd0: 2303 movs r3, #3 - 800cfd2: e002 b.n 800cfda <__ssvfiscanf_r+0x1e6> - 800cfd4: 2308 movs r3, #8 - 800cfd6: 9342 str r3, [sp, #264] @ 0x108 - 800cfd8: 2304 movs r3, #4 - 800cfda: 9347 str r3, [sp, #284] @ 0x11c - 800cfdc: 6863 ldr r3, [r4, #4] - 800cfde: 2b00 cmp r3, #0 - 800cfe0: dd39 ble.n 800d056 <__ssvfiscanf_r+0x262> - 800cfe2: 9b41 ldr r3, [sp, #260] @ 0x104 - 800cfe4: 0659 lsls r1, r3, #25 - 800cfe6: d404 bmi.n 800cff2 <__ssvfiscanf_r+0x1fe> - 800cfe8: 6823 ldr r3, [r4, #0] - 800cfea: 781a ldrb r2, [r3, #0] - 800cfec: 5cba ldrb r2, [r7, r2] - 800cfee: 0712 lsls r2, r2, #28 - 800cff0: d438 bmi.n 800d064 <__ssvfiscanf_r+0x270> - 800cff2: 9b47 ldr r3, [sp, #284] @ 0x11c - 800cff4: 2b02 cmp r3, #2 - 800cff6: dc47 bgt.n 800d088 <__ssvfiscanf_r+0x294> - 800cff8: 466b mov r3, sp - 800cffa: 4622 mov r2, r4 - 800cffc: 4630 mov r0, r6 - 800cffe: a941 add r1, sp, #260 @ 0x104 - 800d000: f000 f87c bl 800d0fc <_scanf_chars> - 800d004: 2801 cmp r0, #1 - 800d006: d065 beq.n 800d0d4 <__ssvfiscanf_r+0x2e0> - 800d008: 2802 cmp r0, #2 - 800d00a: f47f af17 bne.w 800ce3c <__ssvfiscanf_r+0x48> - 800d00e: e7c9 b.n 800cfa4 <__ssvfiscanf_r+0x1b0> - 800d010: 220a movs r2, #10 - 800d012: e7d7 b.n 800cfc4 <__ssvfiscanf_r+0x1d0> - 800d014: 4629 mov r1, r5 - 800d016: 4640 mov r0, r8 - 800d018: f000 f9bc bl 800d394 <__sccl> - 800d01c: 9b41 ldr r3, [sp, #260] @ 0x104 - 800d01e: 4605 mov r5, r0 - 800d020: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800d024: 9341 str r3, [sp, #260] @ 0x104 - 800d026: 2301 movs r3, #1 - 800d028: e7d7 b.n 800cfda <__ssvfiscanf_r+0x1e6> - 800d02a: 9b41 ldr r3, [sp, #260] @ 0x104 - 800d02c: f043 0340 orr.w r3, r3, #64 @ 0x40 - 800d030: 9341 str r3, [sp, #260] @ 0x104 - 800d032: 2300 movs r3, #0 - 800d034: e7d1 b.n 800cfda <__ssvfiscanf_r+0x1e6> - 800d036: 2302 movs r3, #2 - 800d038: e7cf b.n 800cfda <__ssvfiscanf_r+0x1e6> - 800d03a: 9841 ldr r0, [sp, #260] @ 0x104 - 800d03c: 06c3 lsls r3, r0, #27 - 800d03e: f53f aefd bmi.w 800ce3c <__ssvfiscanf_r+0x48> - 800d042: 9b00 ldr r3, [sp, #0] - 800d044: 9a45 ldr r2, [sp, #276] @ 0x114 - 800d046: 1d19 adds r1, r3, #4 - 800d048: 9100 str r1, [sp, #0] - 800d04a: 681b ldr r3, [r3, #0] - 800d04c: 07c0 lsls r0, r0, #31 - 800d04e: bf4c ite mi - 800d050: 801a strhmi r2, [r3, #0] - 800d052: 601a strpl r2, [r3, #0] - 800d054: e6f2 b.n 800ce3c <__ssvfiscanf_r+0x48> - 800d056: 4621 mov r1, r4 - 800d058: 4630 mov r0, r6 - 800d05a: 9ba1 ldr r3, [sp, #644] @ 0x284 - 800d05c: 4798 blx r3 - 800d05e: 2800 cmp r0, #0 - 800d060: d0bf beq.n 800cfe2 <__ssvfiscanf_r+0x1ee> - 800d062: e79f b.n 800cfa4 <__ssvfiscanf_r+0x1b0> - 800d064: 9a45 ldr r2, [sp, #276] @ 0x114 - 800d066: 3201 adds r2, #1 - 800d068: 9245 str r2, [sp, #276] @ 0x114 - 800d06a: 6862 ldr r2, [r4, #4] - 800d06c: 3a01 subs r2, #1 - 800d06e: 2a00 cmp r2, #0 - 800d070: 6062 str r2, [r4, #4] - 800d072: dd02 ble.n 800d07a <__ssvfiscanf_r+0x286> - 800d074: 3301 adds r3, #1 - 800d076: 6023 str r3, [r4, #0] - 800d078: e7b6 b.n 800cfe8 <__ssvfiscanf_r+0x1f4> - 800d07a: 4621 mov r1, r4 - 800d07c: 4630 mov r0, r6 - 800d07e: 9ba1 ldr r3, [sp, #644] @ 0x284 - 800d080: 4798 blx r3 - 800d082: 2800 cmp r0, #0 - 800d084: d0b0 beq.n 800cfe8 <__ssvfiscanf_r+0x1f4> - 800d086: e78d b.n 800cfa4 <__ssvfiscanf_r+0x1b0> - 800d088: 2b04 cmp r3, #4 - 800d08a: dc06 bgt.n 800d09a <__ssvfiscanf_r+0x2a6> - 800d08c: 466b mov r3, sp - 800d08e: 4622 mov r2, r4 - 800d090: 4630 mov r0, r6 - 800d092: a941 add r1, sp, #260 @ 0x104 - 800d094: f000 f88c bl 800d1b0 <_scanf_i> - 800d098: e7b4 b.n 800d004 <__ssvfiscanf_r+0x210> - 800d09a: 4b09 ldr r3, [pc, #36] @ (800d0c0 <__ssvfiscanf_r+0x2cc>) - 800d09c: 2b00 cmp r3, #0 - 800d09e: f43f aecd beq.w 800ce3c <__ssvfiscanf_r+0x48> - 800d0a2: 466b mov r3, sp - 800d0a4: 4622 mov r2, r4 - 800d0a6: 4630 mov r0, r6 - 800d0a8: a941 add r1, sp, #260 @ 0x104 - 800d0aa: f3af 8000 nop.w - 800d0ae: e7a9 b.n 800d004 <__ssvfiscanf_r+0x210> - 800d0b0: 0800cd45 .word 0x0800cd45 - 800d0b4: 0800cdbb .word 0x0800cdbb - 800d0b8: 0800e3d3 .word 0x0800e3d3 - 800d0bc: 0800e266 .word 0x0800e266 - 800d0c0: 00000000 .word 0x00000000 - 800d0c4: 89a3 ldrh r3, [r4, #12] - 800d0c6: 065b lsls r3, r3, #25 - 800d0c8: f53f af70 bmi.w 800cfac <__ssvfiscanf_r+0x1b8> - 800d0cc: f50d 7d22 add.w sp, sp, #648 @ 0x288 - 800d0d0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800d0d4: 9844 ldr r0, [sp, #272] @ 0x110 - 800d0d6: e7f9 b.n 800d0cc <__ssvfiscanf_r+0x2d8> - -0800d0d8 <__ascii_mbtowc>: - 800d0d8: b082 sub sp, #8 - 800d0da: b901 cbnz r1, 800d0de <__ascii_mbtowc+0x6> - 800d0dc: a901 add r1, sp, #4 - 800d0de: b142 cbz r2, 800d0f2 <__ascii_mbtowc+0x1a> - 800d0e0: b14b cbz r3, 800d0f6 <__ascii_mbtowc+0x1e> - 800d0e2: 7813 ldrb r3, [r2, #0] - 800d0e4: 600b str r3, [r1, #0] - 800d0e6: 7812 ldrb r2, [r2, #0] - 800d0e8: 1e10 subs r0, r2, #0 - 800d0ea: bf18 it ne - 800d0ec: 2001 movne r0, #1 - 800d0ee: b002 add sp, #8 - 800d0f0: 4770 bx lr - 800d0f2: 4610 mov r0, r2 - 800d0f4: e7fb b.n 800d0ee <__ascii_mbtowc+0x16> - 800d0f6: f06f 0001 mvn.w r0, #1 - 800d0fa: e7f8 b.n 800d0ee <__ascii_mbtowc+0x16> - -0800d0fc <_scanf_chars>: - 800d0fc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 800d100: 4615 mov r5, r2 - 800d102: 688a ldr r2, [r1, #8] - 800d104: 4680 mov r8, r0 - 800d106: 460c mov r4, r1 - 800d108: b932 cbnz r2, 800d118 <_scanf_chars+0x1c> - 800d10a: 698a ldr r2, [r1, #24] - 800d10c: 2a00 cmp r2, #0 - 800d10e: bf14 ite ne - 800d110: f04f 32ff movne.w r2, #4294967295 @ 0xffffffff - 800d114: 2201 moveq r2, #1 - 800d116: 608a str r2, [r1, #8] - 800d118: 2700 movs r7, #0 - 800d11a: 6822 ldr r2, [r4, #0] - 800d11c: f8df 908c ldr.w r9, [pc, #140] @ 800d1ac <_scanf_chars+0xb0> - 800d120: 06d1 lsls r1, r2, #27 - 800d122: bf5f itttt pl - 800d124: 681a ldrpl r2, [r3, #0] - 800d126: 1d11 addpl r1, r2, #4 - 800d128: 6019 strpl r1, [r3, #0] - 800d12a: 6816 ldrpl r6, [r2, #0] - 800d12c: 69a0 ldr r0, [r4, #24] - 800d12e: b188 cbz r0, 800d154 <_scanf_chars+0x58> - 800d130: 2801 cmp r0, #1 - 800d132: d107 bne.n 800d144 <_scanf_chars+0x48> - 800d134: 682b ldr r3, [r5, #0] - 800d136: 781a ldrb r2, [r3, #0] - 800d138: 6963 ldr r3, [r4, #20] - 800d13a: 5c9b ldrb r3, [r3, r2] - 800d13c: b953 cbnz r3, 800d154 <_scanf_chars+0x58> - 800d13e: 2f00 cmp r7, #0 - 800d140: d031 beq.n 800d1a6 <_scanf_chars+0xaa> - 800d142: e022 b.n 800d18a <_scanf_chars+0x8e> - 800d144: 2802 cmp r0, #2 - 800d146: d120 bne.n 800d18a <_scanf_chars+0x8e> - 800d148: 682b ldr r3, [r5, #0] - 800d14a: 781b ldrb r3, [r3, #0] - 800d14c: f819 3003 ldrb.w r3, [r9, r3] - 800d150: 071b lsls r3, r3, #28 - 800d152: d41a bmi.n 800d18a <_scanf_chars+0x8e> - 800d154: 6823 ldr r3, [r4, #0] - 800d156: 3701 adds r7, #1 - 800d158: 06da lsls r2, r3, #27 - 800d15a: bf5e ittt pl - 800d15c: 682b ldrpl r3, [r5, #0] - 800d15e: 781b ldrbpl r3, [r3, #0] - 800d160: f806 3b01 strbpl.w r3, [r6], #1 - 800d164: 682a ldr r2, [r5, #0] - 800d166: 686b ldr r3, [r5, #4] - 800d168: 3201 adds r2, #1 - 800d16a: 602a str r2, [r5, #0] - 800d16c: 68a2 ldr r2, [r4, #8] - 800d16e: 3b01 subs r3, #1 - 800d170: 3a01 subs r2, #1 - 800d172: 606b str r3, [r5, #4] - 800d174: 60a2 str r2, [r4, #8] - 800d176: b142 cbz r2, 800d18a <_scanf_chars+0x8e> - 800d178: 2b00 cmp r3, #0 - 800d17a: dcd7 bgt.n 800d12c <_scanf_chars+0x30> - 800d17c: 4629 mov r1, r5 - 800d17e: 4640 mov r0, r8 - 800d180: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 - 800d184: 4798 blx r3 - 800d186: 2800 cmp r0, #0 - 800d188: d0d0 beq.n 800d12c <_scanf_chars+0x30> - 800d18a: 6823 ldr r3, [r4, #0] - 800d18c: f013 0310 ands.w r3, r3, #16 - 800d190: d105 bne.n 800d19e <_scanf_chars+0xa2> - 800d192: 68e2 ldr r2, [r4, #12] - 800d194: 3201 adds r2, #1 - 800d196: 60e2 str r2, [r4, #12] - 800d198: 69a2 ldr r2, [r4, #24] - 800d19a: b102 cbz r2, 800d19e <_scanf_chars+0xa2> - 800d19c: 7033 strb r3, [r6, #0] - 800d19e: 2000 movs r0, #0 - 800d1a0: 6923 ldr r3, [r4, #16] - 800d1a2: 443b add r3, r7 - 800d1a4: 6123 str r3, [r4, #16] - 800d1a6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 800d1aa: bf00 nop - 800d1ac: 0800e3d3 .word 0x0800e3d3 - -0800d1b0 <_scanf_i>: - 800d1b0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 800d1b4: 460c mov r4, r1 - 800d1b6: 4698 mov r8, r3 - 800d1b8: 4b72 ldr r3, [pc, #456] @ (800d384 <_scanf_i+0x1d4>) - 800d1ba: b087 sub sp, #28 - 800d1bc: 4682 mov sl, r0 - 800d1be: 4616 mov r6, r2 - 800d1c0: e893 0007 ldmia.w r3, {r0, r1, r2} - 800d1c4: ab03 add r3, sp, #12 - 800d1c6: e883 0007 stmia.w r3, {r0, r1, r2} - 800d1ca: 4b6f ldr r3, [pc, #444] @ (800d388 <_scanf_i+0x1d8>) - 800d1cc: 69a1 ldr r1, [r4, #24] - 800d1ce: 4a6f ldr r2, [pc, #444] @ (800d38c <_scanf_i+0x1dc>) - 800d1d0: 4627 mov r7, r4 - 800d1d2: 2903 cmp r1, #3 - 800d1d4: bf08 it eq - 800d1d6: 461a moveq r2, r3 - 800d1d8: 68a3 ldr r3, [r4, #8] - 800d1da: 9201 str r2, [sp, #4] - 800d1dc: 1e5a subs r2, r3, #1 - 800d1de: f5b2 7fae cmp.w r2, #348 @ 0x15c - 800d1e2: bf81 itttt hi - 800d1e4: f46f 75ae mvnhi.w r5, #348 @ 0x15c - 800d1e8: eb03 0905 addhi.w r9, r3, r5 - 800d1ec: f240 135d movwhi r3, #349 @ 0x15d - 800d1f0: 60a3 strhi r3, [r4, #8] - 800d1f2: f857 3b1c ldr.w r3, [r7], #28 - 800d1f6: bf98 it ls - 800d1f8: f04f 0900 movls.w r9, #0 - 800d1fc: 463d mov r5, r7 - 800d1fe: f04f 0b00 mov.w fp, #0 - 800d202: f443 6350 orr.w r3, r3, #3328 @ 0xd00 - 800d206: 6023 str r3, [r4, #0] - 800d208: 6831 ldr r1, [r6, #0] - 800d20a: ab03 add r3, sp, #12 - 800d20c: 2202 movs r2, #2 - 800d20e: 7809 ldrb r1, [r1, #0] - 800d210: f853 002b ldr.w r0, [r3, fp, lsl #2] - 800d214: f7fd fc21 bl 800aa5a - 800d218: b328 cbz r0, 800d266 <_scanf_i+0xb6> - 800d21a: f1bb 0f01 cmp.w fp, #1 - 800d21e: d159 bne.n 800d2d4 <_scanf_i+0x124> - 800d220: 6862 ldr r2, [r4, #4] - 800d222: b92a cbnz r2, 800d230 <_scanf_i+0x80> - 800d224: 2108 movs r1, #8 - 800d226: 6822 ldr r2, [r4, #0] - 800d228: 6061 str r1, [r4, #4] - 800d22a: f442 7200 orr.w r2, r2, #512 @ 0x200 - 800d22e: 6022 str r2, [r4, #0] - 800d230: 6822 ldr r2, [r4, #0] - 800d232: f422 62a0 bic.w r2, r2, #1280 @ 0x500 - 800d236: 6022 str r2, [r4, #0] - 800d238: 68a2 ldr r2, [r4, #8] - 800d23a: 1e51 subs r1, r2, #1 - 800d23c: 60a1 str r1, [r4, #8] - 800d23e: b192 cbz r2, 800d266 <_scanf_i+0xb6> - 800d240: 6832 ldr r2, [r6, #0] - 800d242: 1c51 adds r1, r2, #1 - 800d244: 6031 str r1, [r6, #0] - 800d246: 7812 ldrb r2, [r2, #0] - 800d248: f805 2b01 strb.w r2, [r5], #1 - 800d24c: 6872 ldr r2, [r6, #4] - 800d24e: 3a01 subs r2, #1 - 800d250: 2a00 cmp r2, #0 - 800d252: 6072 str r2, [r6, #4] - 800d254: dc07 bgt.n 800d266 <_scanf_i+0xb6> - 800d256: 4631 mov r1, r6 - 800d258: 4650 mov r0, sl - 800d25a: f8d4 2180 ldr.w r2, [r4, #384] @ 0x180 - 800d25e: 4790 blx r2 - 800d260: 2800 cmp r0, #0 - 800d262: f040 8085 bne.w 800d370 <_scanf_i+0x1c0> - 800d266: f10b 0b01 add.w fp, fp, #1 - 800d26a: f1bb 0f03 cmp.w fp, #3 - 800d26e: d1cb bne.n 800d208 <_scanf_i+0x58> - 800d270: 6863 ldr r3, [r4, #4] - 800d272: b90b cbnz r3, 800d278 <_scanf_i+0xc8> - 800d274: 230a movs r3, #10 - 800d276: 6063 str r3, [r4, #4] - 800d278: 6863 ldr r3, [r4, #4] - 800d27a: 4945 ldr r1, [pc, #276] @ (800d390 <_scanf_i+0x1e0>) - 800d27c: 6960 ldr r0, [r4, #20] - 800d27e: 1ac9 subs r1, r1, r3 - 800d280: f000 f888 bl 800d394 <__sccl> - 800d284: f04f 0b00 mov.w fp, #0 - 800d288: 68a3 ldr r3, [r4, #8] - 800d28a: 6822 ldr r2, [r4, #0] - 800d28c: 2b00 cmp r3, #0 - 800d28e: d03d beq.n 800d30c <_scanf_i+0x15c> - 800d290: 6831 ldr r1, [r6, #0] - 800d292: 6960 ldr r0, [r4, #20] - 800d294: f891 c000 ldrb.w ip, [r1] - 800d298: f810 000c ldrb.w r0, [r0, ip] - 800d29c: 2800 cmp r0, #0 - 800d29e: d035 beq.n 800d30c <_scanf_i+0x15c> - 800d2a0: f1bc 0f30 cmp.w ip, #48 @ 0x30 - 800d2a4: d124 bne.n 800d2f0 <_scanf_i+0x140> - 800d2a6: 0510 lsls r0, r2, #20 - 800d2a8: d522 bpl.n 800d2f0 <_scanf_i+0x140> - 800d2aa: f10b 0b01 add.w fp, fp, #1 - 800d2ae: f1b9 0f00 cmp.w r9, #0 - 800d2b2: d003 beq.n 800d2bc <_scanf_i+0x10c> - 800d2b4: 3301 adds r3, #1 - 800d2b6: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff - 800d2ba: 60a3 str r3, [r4, #8] - 800d2bc: 6873 ldr r3, [r6, #4] - 800d2be: 3b01 subs r3, #1 - 800d2c0: 2b00 cmp r3, #0 - 800d2c2: 6073 str r3, [r6, #4] - 800d2c4: dd1b ble.n 800d2fe <_scanf_i+0x14e> - 800d2c6: 6833 ldr r3, [r6, #0] - 800d2c8: 3301 adds r3, #1 - 800d2ca: 6033 str r3, [r6, #0] - 800d2cc: 68a3 ldr r3, [r4, #8] - 800d2ce: 3b01 subs r3, #1 - 800d2d0: 60a3 str r3, [r4, #8] - 800d2d2: e7d9 b.n 800d288 <_scanf_i+0xd8> - 800d2d4: f1bb 0f02 cmp.w fp, #2 - 800d2d8: d1ae bne.n 800d238 <_scanf_i+0x88> - 800d2da: 6822 ldr r2, [r4, #0] - 800d2dc: f402 61c0 and.w r1, r2, #1536 @ 0x600 - 800d2e0: f5b1 7f00 cmp.w r1, #512 @ 0x200 - 800d2e4: d1bf bne.n 800d266 <_scanf_i+0xb6> - 800d2e6: 2110 movs r1, #16 - 800d2e8: f442 7280 orr.w r2, r2, #256 @ 0x100 - 800d2ec: 6061 str r1, [r4, #4] - 800d2ee: e7a2 b.n 800d236 <_scanf_i+0x86> - 800d2f0: f422 6210 bic.w r2, r2, #2304 @ 0x900 - 800d2f4: 6022 str r2, [r4, #0] - 800d2f6: 780b ldrb r3, [r1, #0] - 800d2f8: f805 3b01 strb.w r3, [r5], #1 - 800d2fc: e7de b.n 800d2bc <_scanf_i+0x10c> - 800d2fe: 4631 mov r1, r6 - 800d300: 4650 mov r0, sl - 800d302: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 - 800d306: 4798 blx r3 - 800d308: 2800 cmp r0, #0 - 800d30a: d0df beq.n 800d2cc <_scanf_i+0x11c> - 800d30c: 6823 ldr r3, [r4, #0] - 800d30e: 05d9 lsls r1, r3, #23 - 800d310: d50d bpl.n 800d32e <_scanf_i+0x17e> - 800d312: 42bd cmp r5, r7 - 800d314: d909 bls.n 800d32a <_scanf_i+0x17a> - 800d316: f815 1c01 ldrb.w r1, [r5, #-1] - 800d31a: 4632 mov r2, r6 - 800d31c: 4650 mov r0, sl - 800d31e: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c - 800d322: f105 39ff add.w r9, r5, #4294967295 @ 0xffffffff - 800d326: 4798 blx r3 - 800d328: 464d mov r5, r9 - 800d32a: 42bd cmp r5, r7 - 800d32c: d028 beq.n 800d380 <_scanf_i+0x1d0> - 800d32e: 6822 ldr r2, [r4, #0] - 800d330: f012 0210 ands.w r2, r2, #16 - 800d334: d113 bne.n 800d35e <_scanf_i+0x1ae> - 800d336: 702a strb r2, [r5, #0] - 800d338: 4639 mov r1, r7 - 800d33a: 6863 ldr r3, [r4, #4] - 800d33c: 4650 mov r0, sl - 800d33e: 9e01 ldr r6, [sp, #4] - 800d340: 47b0 blx r6 - 800d342: f8d8 3000 ldr.w r3, [r8] - 800d346: 6821 ldr r1, [r4, #0] - 800d348: 1d1a adds r2, r3, #4 - 800d34a: f8c8 2000 str.w r2, [r8] - 800d34e: f011 0f20 tst.w r1, #32 - 800d352: 681b ldr r3, [r3, #0] - 800d354: d00f beq.n 800d376 <_scanf_i+0x1c6> - 800d356: 6018 str r0, [r3, #0] - 800d358: 68e3 ldr r3, [r4, #12] - 800d35a: 3301 adds r3, #1 - 800d35c: 60e3 str r3, [r4, #12] - 800d35e: 2000 movs r0, #0 - 800d360: 6923 ldr r3, [r4, #16] - 800d362: 1bed subs r5, r5, r7 - 800d364: 445d add r5, fp - 800d366: 442b add r3, r5 - 800d368: 6123 str r3, [r4, #16] - 800d36a: b007 add sp, #28 - 800d36c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 800d370: f04f 0b00 mov.w fp, #0 - 800d374: e7ca b.n 800d30c <_scanf_i+0x15c> - 800d376: 07ca lsls r2, r1, #31 - 800d378: bf4c ite mi - 800d37a: 8018 strhmi r0, [r3, #0] - 800d37c: 6018 strpl r0, [r3, #0] - 800d37e: e7eb b.n 800d358 <_scanf_i+0x1a8> - 800d380: 2001 movs r0, #1 - 800d382: e7f2 b.n 800d36a <_scanf_i+0x1ba> - 800d384: 0800dfe0 .word 0x0800dfe0 - 800d388: 0800d57d .word 0x0800d57d - 800d38c: 0800c93d .word 0x0800c93d - 800d390: 0800e4e3 .word 0x0800e4e3 - -0800d394 <__sccl>: - 800d394: b570 push {r4, r5, r6, lr} - 800d396: 780b ldrb r3, [r1, #0] - 800d398: 4604 mov r4, r0 - 800d39a: 2b5e cmp r3, #94 @ 0x5e - 800d39c: bf0b itete eq - 800d39e: 784b ldrbeq r3, [r1, #1] - 800d3a0: 1c4a addne r2, r1, #1 - 800d3a2: 1c8a addeq r2, r1, #2 - 800d3a4: 2100 movne r1, #0 - 800d3a6: bf08 it eq - 800d3a8: 2101 moveq r1, #1 - 800d3aa: 3801 subs r0, #1 - 800d3ac: f104 05ff add.w r5, r4, #255 @ 0xff - 800d3b0: f800 1f01 strb.w r1, [r0, #1]! - 800d3b4: 42a8 cmp r0, r5 - 800d3b6: d1fb bne.n 800d3b0 <__sccl+0x1c> - 800d3b8: b90b cbnz r3, 800d3be <__sccl+0x2a> - 800d3ba: 1e50 subs r0, r2, #1 - 800d3bc: bd70 pop {r4, r5, r6, pc} - 800d3be: f081 0101 eor.w r1, r1, #1 - 800d3c2: 4610 mov r0, r2 - 800d3c4: 54e1 strb r1, [r4, r3] - 800d3c6: 4602 mov r2, r0 - 800d3c8: f812 5b01 ldrb.w r5, [r2], #1 - 800d3cc: 2d2d cmp r5, #45 @ 0x2d - 800d3ce: d005 beq.n 800d3dc <__sccl+0x48> - 800d3d0: 2d5d cmp r5, #93 @ 0x5d - 800d3d2: d016 beq.n 800d402 <__sccl+0x6e> - 800d3d4: 2d00 cmp r5, #0 - 800d3d6: d0f1 beq.n 800d3bc <__sccl+0x28> - 800d3d8: 462b mov r3, r5 - 800d3da: e7f2 b.n 800d3c2 <__sccl+0x2e> - 800d3dc: 7846 ldrb r6, [r0, #1] - 800d3de: 2e5d cmp r6, #93 @ 0x5d - 800d3e0: d0fa beq.n 800d3d8 <__sccl+0x44> - 800d3e2: 42b3 cmp r3, r6 - 800d3e4: dcf8 bgt.n 800d3d8 <__sccl+0x44> - 800d3e6: 461a mov r2, r3 - 800d3e8: 3002 adds r0, #2 - 800d3ea: 3201 adds r2, #1 - 800d3ec: 4296 cmp r6, r2 - 800d3ee: 54a1 strb r1, [r4, r2] - 800d3f0: dcfb bgt.n 800d3ea <__sccl+0x56> - 800d3f2: 1af2 subs r2, r6, r3 - 800d3f4: 3a01 subs r2, #1 - 800d3f6: 42b3 cmp r3, r6 - 800d3f8: bfa8 it ge - 800d3fa: 2200 movge r2, #0 - 800d3fc: 1c5d adds r5, r3, #1 - 800d3fe: 18ab adds r3, r5, r2 - 800d400: e7e1 b.n 800d3c6 <__sccl+0x32> - 800d402: 4610 mov r0, r2 - 800d404: e7da b.n 800d3bc <__sccl+0x28> - -0800d406 <_malloc_usable_size_r>: - 800d406: f851 3c04 ldr.w r3, [r1, #-4] - 800d40a: 1f18 subs r0, r3, #4 - 800d40c: 2b00 cmp r3, #0 - 800d40e: bfbc itt lt - 800d410: 580b ldrlt r3, [r1, r0] - 800d412: 18c0 addlt r0, r0, r3 - 800d414: 4770 bx lr - -0800d416 <__submore>: - 800d416: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800d41a: 460c mov r4, r1 - 800d41c: 6b49 ldr r1, [r1, #52] @ 0x34 - 800d41e: f104 0344 add.w r3, r4, #68 @ 0x44 - 800d422: 4299 cmp r1, r3 - 800d424: d11b bne.n 800d45e <__submore+0x48> - 800d426: f44f 6180 mov.w r1, #1024 @ 0x400 - 800d42a: f7fe fcb5 bl 800bd98 <_malloc_r> - 800d42e: b918 cbnz r0, 800d438 <__submore+0x22> - 800d430: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800d434: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 800d438: f44f 6380 mov.w r3, #1024 @ 0x400 - 800d43c: 63a3 str r3, [r4, #56] @ 0x38 - 800d43e: f894 3046 ldrb.w r3, [r4, #70] @ 0x46 - 800d442: 6360 str r0, [r4, #52] @ 0x34 - 800d444: f880 33ff strb.w r3, [r0, #1023] @ 0x3ff - 800d448: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 - 800d44c: f200 30fd addw r0, r0, #1021 @ 0x3fd - 800d450: 7043 strb r3, [r0, #1] - 800d452: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 - 800d456: 7003 strb r3, [r0, #0] - 800d458: 6020 str r0, [r4, #0] - 800d45a: 2000 movs r0, #0 - 800d45c: e7ea b.n 800d434 <__submore+0x1e> - 800d45e: 6ba6 ldr r6, [r4, #56] @ 0x38 - 800d460: 0077 lsls r7, r6, #1 - 800d462: 463a mov r2, r7 - 800d464: f7ff f9ce bl 800c804 <_realloc_r> - 800d468: 4605 mov r5, r0 - 800d46a: 2800 cmp r0, #0 - 800d46c: d0e0 beq.n 800d430 <__submore+0x1a> - 800d46e: eb00 0806 add.w r8, r0, r6 - 800d472: 4601 mov r1, r0 - 800d474: 4632 mov r2, r6 - 800d476: 4640 mov r0, r8 - 800d478: f7fd fafd bl 800aa76 - 800d47c: e9c4 570d strd r5, r7, [r4, #52] @ 0x34 - 800d480: f8c4 8000 str.w r8, [r4] - 800d484: e7e9 b.n 800d45a <__submore+0x44> - ... - -0800d488 <_strtol_l.constprop.0>: - 800d488: 2b24 cmp r3, #36 @ 0x24 - 800d48a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 800d48e: 4686 mov lr, r0 - 800d490: 4690 mov r8, r2 - 800d492: d801 bhi.n 800d498 <_strtol_l.constprop.0+0x10> - 800d494: 2b01 cmp r3, #1 - 800d496: d106 bne.n 800d4a6 <_strtol_l.constprop.0+0x1e> - 800d498: f7fd fab0 bl 800a9fc <__errno> - 800d49c: 2316 movs r3, #22 - 800d49e: 6003 str r3, [r0, #0] - 800d4a0: 2000 movs r0, #0 - 800d4a2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800d4a6: 460d mov r5, r1 - 800d4a8: 4833 ldr r0, [pc, #204] @ (800d578 <_strtol_l.constprop.0+0xf0>) - 800d4aa: 462a mov r2, r5 - 800d4ac: f815 4b01 ldrb.w r4, [r5], #1 - 800d4b0: 5d06 ldrb r6, [r0, r4] - 800d4b2: f016 0608 ands.w r6, r6, #8 - 800d4b6: d1f8 bne.n 800d4aa <_strtol_l.constprop.0+0x22> - 800d4b8: 2c2d cmp r4, #45 @ 0x2d - 800d4ba: d12d bne.n 800d518 <_strtol_l.constprop.0+0x90> - 800d4bc: 2601 movs r6, #1 - 800d4be: 782c ldrb r4, [r5, #0] - 800d4c0: 1c95 adds r5, r2, #2 - 800d4c2: f033 0210 bics.w r2, r3, #16 - 800d4c6: d109 bne.n 800d4dc <_strtol_l.constprop.0+0x54> - 800d4c8: 2c30 cmp r4, #48 @ 0x30 - 800d4ca: d12a bne.n 800d522 <_strtol_l.constprop.0+0x9a> - 800d4cc: 782a ldrb r2, [r5, #0] - 800d4ce: f002 02df and.w r2, r2, #223 @ 0xdf - 800d4d2: 2a58 cmp r2, #88 @ 0x58 - 800d4d4: d125 bne.n 800d522 <_strtol_l.constprop.0+0x9a> - 800d4d6: 2310 movs r3, #16 - 800d4d8: 786c ldrb r4, [r5, #1] - 800d4da: 3502 adds r5, #2 - 800d4dc: 2200 movs r2, #0 - 800d4de: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 - 800d4e2: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff - 800d4e6: fbbc f9f3 udiv r9, ip, r3 - 800d4ea: 4610 mov r0, r2 - 800d4ec: fb03 ca19 mls sl, r3, r9, ip - 800d4f0: f1a4 0730 sub.w r7, r4, #48 @ 0x30 - 800d4f4: 2f09 cmp r7, #9 - 800d4f6: d81b bhi.n 800d530 <_strtol_l.constprop.0+0xa8> - 800d4f8: 463c mov r4, r7 - 800d4fa: 42a3 cmp r3, r4 - 800d4fc: dd27 ble.n 800d54e <_strtol_l.constprop.0+0xc6> - 800d4fe: 1c57 adds r7, r2, #1 - 800d500: d007 beq.n 800d512 <_strtol_l.constprop.0+0x8a> - 800d502: 4581 cmp r9, r0 - 800d504: d320 bcc.n 800d548 <_strtol_l.constprop.0+0xc0> - 800d506: d101 bne.n 800d50c <_strtol_l.constprop.0+0x84> - 800d508: 45a2 cmp sl, r4 - 800d50a: db1d blt.n 800d548 <_strtol_l.constprop.0+0xc0> - 800d50c: 2201 movs r2, #1 - 800d50e: fb00 4003 mla r0, r0, r3, r4 - 800d512: f815 4b01 ldrb.w r4, [r5], #1 - 800d516: e7eb b.n 800d4f0 <_strtol_l.constprop.0+0x68> - 800d518: 2c2b cmp r4, #43 @ 0x2b - 800d51a: bf04 itt eq - 800d51c: 782c ldrbeq r4, [r5, #0] - 800d51e: 1c95 addeq r5, r2, #2 - 800d520: e7cf b.n 800d4c2 <_strtol_l.constprop.0+0x3a> - 800d522: 2b00 cmp r3, #0 - 800d524: d1da bne.n 800d4dc <_strtol_l.constprop.0+0x54> - 800d526: 2c30 cmp r4, #48 @ 0x30 - 800d528: bf0c ite eq - 800d52a: 2308 moveq r3, #8 - 800d52c: 230a movne r3, #10 - 800d52e: e7d5 b.n 800d4dc <_strtol_l.constprop.0+0x54> - 800d530: f1a4 0741 sub.w r7, r4, #65 @ 0x41 - 800d534: 2f19 cmp r7, #25 - 800d536: d801 bhi.n 800d53c <_strtol_l.constprop.0+0xb4> - 800d538: 3c37 subs r4, #55 @ 0x37 - 800d53a: e7de b.n 800d4fa <_strtol_l.constprop.0+0x72> - 800d53c: f1a4 0761 sub.w r7, r4, #97 @ 0x61 - 800d540: 2f19 cmp r7, #25 - 800d542: d804 bhi.n 800d54e <_strtol_l.constprop.0+0xc6> - 800d544: 3c57 subs r4, #87 @ 0x57 - 800d546: e7d8 b.n 800d4fa <_strtol_l.constprop.0+0x72> - 800d548: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 800d54c: e7e1 b.n 800d512 <_strtol_l.constprop.0+0x8a> - 800d54e: 1c53 adds r3, r2, #1 - 800d550: d108 bne.n 800d564 <_strtol_l.constprop.0+0xdc> - 800d552: 2322 movs r3, #34 @ 0x22 - 800d554: 4660 mov r0, ip - 800d556: f8ce 3000 str.w r3, [lr] - 800d55a: f1b8 0f00 cmp.w r8, #0 - 800d55e: d0a0 beq.n 800d4a2 <_strtol_l.constprop.0+0x1a> - 800d560: 1e69 subs r1, r5, #1 - 800d562: e006 b.n 800d572 <_strtol_l.constprop.0+0xea> - 800d564: b106 cbz r6, 800d568 <_strtol_l.constprop.0+0xe0> - 800d566: 4240 negs r0, r0 - 800d568: f1b8 0f00 cmp.w r8, #0 - 800d56c: d099 beq.n 800d4a2 <_strtol_l.constprop.0+0x1a> - 800d56e: 2a00 cmp r2, #0 - 800d570: d1f6 bne.n 800d560 <_strtol_l.constprop.0+0xd8> - 800d572: f8c8 1000 str.w r1, [r8] - 800d576: e794 b.n 800d4a2 <_strtol_l.constprop.0+0x1a> - 800d578: 0800e3d3 .word 0x0800e3d3 - -0800d57c <_strtol_r>: - 800d57c: f7ff bf84 b.w 800d488 <_strtol_l.constprop.0> - -0800d580 <__ascii_wctomb>: - 800d580: 4603 mov r3, r0 - 800d582: 4608 mov r0, r1 - 800d584: b141 cbz r1, 800d598 <__ascii_wctomb+0x18> - 800d586: 2aff cmp r2, #255 @ 0xff - 800d588: d904 bls.n 800d594 <__ascii_wctomb+0x14> - 800d58a: 228a movs r2, #138 @ 0x8a - 800d58c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800d590: 601a str r2, [r3, #0] - 800d592: 4770 bx lr - 800d594: 2001 movs r0, #1 - 800d596: 700a strb r2, [r1, #0] - 800d598: 4770 bx lr - -0800d59a <_raise_r>: - 800d59a: 291f cmp r1, #31 - 800d59c: b538 push {r3, r4, r5, lr} - 800d59e: 4605 mov r5, r0 - 800d5a0: 460c mov r4, r1 - 800d5a2: d904 bls.n 800d5ae <_raise_r+0x14> - 800d5a4: 2316 movs r3, #22 - 800d5a6: 6003 str r3, [r0, #0] - 800d5a8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800d5ac: bd38 pop {r3, r4, r5, pc} - 800d5ae: 6bc2 ldr r2, [r0, #60] @ 0x3c - 800d5b0: b112 cbz r2, 800d5b8 <_raise_r+0x1e> - 800d5b2: f852 3021 ldr.w r3, [r2, r1, lsl #2] - 800d5b6: b94b cbnz r3, 800d5cc <_raise_r+0x32> - 800d5b8: 4628 mov r0, r5 - 800d5ba: f000 f831 bl 800d620 <_getpid_r> - 800d5be: 4622 mov r2, r4 - 800d5c0: 4601 mov r1, r0 - 800d5c2: 4628 mov r0, r5 - 800d5c4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 800d5c8: f000 b818 b.w 800d5fc <_kill_r> - 800d5cc: 2b01 cmp r3, #1 - 800d5ce: d00a beq.n 800d5e6 <_raise_r+0x4c> - 800d5d0: 1c59 adds r1, r3, #1 - 800d5d2: d103 bne.n 800d5dc <_raise_r+0x42> - 800d5d4: 2316 movs r3, #22 - 800d5d6: 6003 str r3, [r0, #0] - 800d5d8: 2001 movs r0, #1 - 800d5da: e7e7 b.n 800d5ac <_raise_r+0x12> - 800d5dc: 2100 movs r1, #0 - 800d5de: 4620 mov r0, r4 - 800d5e0: f842 1024 str.w r1, [r2, r4, lsl #2] - 800d5e4: 4798 blx r3 - 800d5e6: 2000 movs r0, #0 - 800d5e8: e7e0 b.n 800d5ac <_raise_r+0x12> - ... - -0800d5ec : - 800d5ec: 4b02 ldr r3, [pc, #8] @ (800d5f8 ) - 800d5ee: 4601 mov r1, r0 - 800d5f0: 6818 ldr r0, [r3, #0] - 800d5f2: f7ff bfd2 b.w 800d59a <_raise_r> - 800d5f6: bf00 nop - 800d5f8: 20000028 .word 0x20000028 - -0800d5fc <_kill_r>: - 800d5fc: b538 push {r3, r4, r5, lr} - 800d5fe: 2300 movs r3, #0 - 800d600: 4d06 ldr r5, [pc, #24] @ (800d61c <_kill_r+0x20>) - 800d602: 4604 mov r4, r0 - 800d604: 4608 mov r0, r1 - 800d606: 4611 mov r1, r2 - 800d608: 602b str r3, [r5, #0] - 800d60a: f7f7 ff64 bl 80054d6 <_kill> - 800d60e: 1c43 adds r3, r0, #1 - 800d610: d102 bne.n 800d618 <_kill_r+0x1c> - 800d612: 682b ldr r3, [r5, #0] - 800d614: b103 cbz r3, 800d618 <_kill_r+0x1c> - 800d616: 6023 str r3, [r4, #0] - 800d618: bd38 pop {r3, r4, r5, pc} - 800d61a: bf00 nop - 800d61c: 20003508 .word 0x20003508 - -0800d620 <_getpid_r>: - 800d620: f7f7 bf52 b.w 80054c8 <_getpid> - -0800d624 <_init>: - 800d624: b5f8 push {r3, r4, r5, r6, r7, lr} - 800d626: bf00 nop - 800d628: bcf8 pop {r3, r4, r5, r6, r7} - 800d62a: bc08 pop {r3} - 800d62c: 469e mov lr, r3 - 800d62e: 4770 bx lr - -0800d630 <_fini>: - 800d630: b5f8 push {r3, r4, r5, r6, r7, lr} - 800d632: bf00 nop - 800d634: bcf8 pop {r3, r4, r5, r6, r7} - 800d636: bc08 pop {r3} - 800d638: 469e mov lr, r3 - 800d63a: 4770 bx lr diff --git a/Debug/GbTModuleSW30Web.bin b/Debug/GbTModuleSW30Web.bin new file mode 100755 index 0000000..4eee680 Binary files /dev/null and b/Debug/GbTModuleSW30Web.bin differ diff --git a/Debug/GbTModuleSW30Web.list b/Debug/GbTModuleSW30Web.list new file mode 100644 index 0000000..a1a5078 --- /dev/null +++ b/Debug/GbTModuleSW30Web.list @@ -0,0 +1,33746 @@ + +GbTModuleSW30Web.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000e288 080081e8 080081e8 000011e8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000b84 08016470 08016470 0000f470 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08016ff4 08016ff4 00011240 2**0 + CONTENTS + 4 .ARM 00000008 08016ff4 08016ff4 0000fff4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08016ffc 08016ffc 00011240 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08016ffc 08016ffc 0000fffc 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08017000 08017000 00010000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000240 20000000 08017004 00011000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000d70 20000240 08017244 00011240 2**3 + ALLOC + 10 ._user_heap_stack 00000600 20000fb0 08017244 00011fb0 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 00011240 2**0 + CONTENTS, READONLY + 12 .debug_info 0001c185 00000000 00000000 00011269 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 0000586d 00000000 00000000 0002d3ee 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00001768 00000000 00000000 00032c60 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 000011db 00000000 00000000 000343c8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 00026df6 00000000 00000000 000355a3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0001e8a1 00000000 00000000 0005c399 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000c96c1 00000000 00000000 0007ac3a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 001442fb 2**0 + CONTENTS, READONLY + 20 .debug_frame 00006fb8 00000000 00000000 00144340 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 0000006e 00000000 00000000 0014b2f8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080081e8 <__do_global_dtors_aux>: + 80081e8: b510 push {r4, lr} + 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) + 80081ec: 7823 ldrb r3, [r4, #0] + 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> + 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) + 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> + 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) + 80081f6: f3af 8000 nop.w + 80081fa: 2301 movs r3, #1 + 80081fc: 7023 strb r3, [r4, #0] + 80081fe: bd10 pop {r4, pc} + 8008200: 20000240 .word 0x20000240 + 8008204: 00000000 .word 0x00000000 + 8008208: 08016458 .word 0x08016458 + +0800820c : + 800820c: b508 push {r3, lr} + 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) + 8008210: b11b cbz r3, 800821a + 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) + 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) + 8008216: f3af 8000 nop.w + 800821a: bd08 pop {r3, pc} + 800821c: 00000000 .word 0x00000000 + 8008220: 20000244 .word 0x20000244 + 8008224: 08016458 .word 0x08016458 + +08008228 : + 8008228: 4603 mov r3, r0 + 800822a: f813 2b01 ldrb.w r2, [r3], #1 + 800822e: 2a00 cmp r2, #0 + 8008230: d1fb bne.n 800822a + 8008232: 1a18 subs r0, r3, r0 + 8008234: 3801 subs r0, #1 + 8008236: 4770 bx lr + +08008238 <__aeabi_drsub>: + 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 + 800823c: e002 b.n 8008244 <__adddf3> + 800823e: bf00 nop + +08008240 <__aeabi_dsub>: + 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 + +08008244 <__adddf3>: + 8008244: b530 push {r4, r5, lr} + 8008246: ea4f 0441 mov.w r4, r1, lsl #1 + 800824a: ea4f 0543 mov.w r5, r3, lsl #1 + 800824e: ea94 0f05 teq r4, r5 + 8008252: bf08 it eq + 8008254: ea90 0f02 teqeq r0, r2 + 8008258: bf1f itttt ne + 800825a: ea54 0c00 orrsne.w ip, r4, r0 + 800825e: ea55 0c02 orrsne.w ip, r5, r2 + 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> + 800826e: ea4f 5454 mov.w r4, r4, lsr #21 + 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 8008276: bfb8 it lt + 8008278: 426d neglt r5, r5 + 800827a: dd0c ble.n 8008296 <__adddf3+0x52> + 800827c: 442c add r4, r5 + 800827e: ea80 0202 eor.w r2, r0, r2 + 8008282: ea81 0303 eor.w r3, r1, r3 + 8008286: ea82 0000 eor.w r0, r2, r0 + 800828a: ea83 0101 eor.w r1, r3, r1 + 800828e: ea80 0202 eor.w r2, r0, r2 + 8008292: ea81 0303 eor.w r3, r1, r3 + 8008296: 2d36 cmp r5, #54 @ 0x36 + 8008298: bf88 it hi + 800829a: bd30 pophi {r4, r5, pc} + 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 + 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 + 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 + 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> + 80082ae: 4240 negs r0, r0 + 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 + 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 + 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> + 80082c2: 4252 negs r2, r2 + 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 80082c8: ea94 0f05 teq r4, r5 + 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> + 80082d0: f1a4 0401 sub.w r4, r4, #1 + 80082d4: f1d5 0e20 rsbs lr, r5, #32 + 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> + 80082da: fa02 fc0e lsl.w ip, r2, lr + 80082de: fa22 f205 lsr.w r2, r2, r5 + 80082e2: 1880 adds r0, r0, r2 + 80082e4: f141 0100 adc.w r1, r1, #0 + 80082e8: fa03 f20e lsl.w r2, r3, lr + 80082ec: 1880 adds r0, r0, r2 + 80082ee: fa43 f305 asr.w r3, r3, r5 + 80082f2: 4159 adcs r1, r3 + 80082f4: e00e b.n 8008314 <__adddf3+0xd0> + 80082f6: f1a5 0520 sub.w r5, r5, #32 + 80082fa: f10e 0e20 add.w lr, lr, #32 + 80082fe: 2a01 cmp r2, #1 + 8008300: fa03 fc0e lsl.w ip, r3, lr + 8008304: bf28 it cs + 8008306: f04c 0c02 orrcs.w ip, ip, #2 + 800830a: fa43 f305 asr.w r3, r3, r5 + 800830e: 18c0 adds r0, r0, r3 + 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 8008318: d507 bpl.n 800832a <__adddf3+0xe6> + 800831a: f04f 0e00 mov.w lr, #0 + 800831e: f1dc 0c00 rsbs ip, ip, #0 + 8008322: eb7e 0000 sbcs.w r0, lr, r0 + 8008326: eb6e 0101 sbc.w r1, lr, r1 + 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 + 800832e: d31b bcc.n 8008368 <__adddf3+0x124> + 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 + 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> + 8008336: 0849 lsrs r1, r1, #1 + 8008338: ea5f 0030 movs.w r0, r0, rrx + 800833c: ea4f 0c3c mov.w ip, ip, rrx + 8008340: f104 0401 add.w r4, r4, #1 + 8008344: ea4f 5244 mov.w r2, r4, lsl #21 + 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 + 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> + 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 + 8008354: bf08 it eq + 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 + 800835a: f150 0000 adcs.w r0, r0, #0 + 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8008362: ea41 0105 orr.w r1, r1, r5 + 8008366: bd30 pop {r4, r5, pc} + 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 + 800836c: 4140 adcs r0, r0 + 800836e: eb41 0101 adc.w r1, r1, r1 + 8008372: 3c01 subs r4, #1 + 8008374: bf28 it cs + 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 + 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> + 800837c: f091 0f00 teq r1, #0 + 8008380: bf04 itt eq + 8008382: 4601 moveq r1, r0 + 8008384: 2000 moveq r0, #0 + 8008386: fab1 f381 clz r3, r1 + 800838a: bf08 it eq + 800838c: 3320 addeq r3, #32 + 800838e: f1a3 030b sub.w r3, r3, #11 + 8008392: f1b3 0220 subs.w r2, r3, #32 + 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> + 8008398: 320c adds r2, #12 + 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> + 800839c: f102 0c14 add.w ip, r2, #20 + 80083a0: f1c2 020c rsb r2, r2, #12 + 80083a4: fa01 f00c lsl.w r0, r1, ip + 80083a8: fa21 f102 lsr.w r1, r1, r2 + 80083ac: e00c b.n 80083c8 <__adddf3+0x184> + 80083ae: f102 0214 add.w r2, r2, #20 + 80083b2: bfd8 it le + 80083b4: f1c2 0c20 rsble ip, r2, #32 + 80083b8: fa01 f102 lsl.w r1, r1, r2 + 80083bc: fa20 fc0c lsr.w ip, r0, ip + 80083c0: bfdc itt le + 80083c2: ea41 010c orrle.w r1, r1, ip + 80083c6: 4090 lslle r0, r2 + 80083c8: 1ae4 subs r4, r4, r3 + 80083ca: bfa2 ittt ge + 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 + 80083d0: 4329 orrge r1, r5 + 80083d2: bd30 popge {r4, r5, pc} + 80083d4: ea6f 0404 mvn.w r4, r4 + 80083d8: 3c1f subs r4, #31 + 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> + 80083dc: 340c adds r4, #12 + 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> + 80083e0: f104 0414 add.w r4, r4, #20 + 80083e4: f1c4 0220 rsb r2, r4, #32 + 80083e8: fa20 f004 lsr.w r0, r0, r4 + 80083ec: fa01 f302 lsl.w r3, r1, r2 + 80083f0: ea40 0003 orr.w r0, r0, r3 + 80083f4: fa21 f304 lsr.w r3, r1, r4 + 80083f8: ea45 0103 orr.w r1, r5, r3 + 80083fc: bd30 pop {r4, r5, pc} + 80083fe: f1c4 040c rsb r4, r4, #12 + 8008402: f1c4 0220 rsb r2, r4, #32 + 8008406: fa20 f002 lsr.w r0, r0, r2 + 800840a: fa01 f304 lsl.w r3, r1, r4 + 800840e: ea40 0003 orr.w r0, r0, r3 + 8008412: 4629 mov r1, r5 + 8008414: bd30 pop {r4, r5, pc} + 8008416: fa21 f004 lsr.w r0, r1, r4 + 800841a: 4629 mov r1, r5 + 800841c: bd30 pop {r4, r5, pc} + 800841e: f094 0f00 teq r4, #0 + 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 + 8008426: bf06 itte eq + 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 + 800842c: 3401 addeq r4, #1 + 800842e: 3d01 subne r5, #1 + 8008430: e74e b.n 80082d0 <__adddf3+0x8c> + 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 + 8008436: bf18 it ne + 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 800843c: d029 beq.n 8008492 <__adddf3+0x24e> + 800843e: ea94 0f05 teq r4, r5 + 8008442: bf08 it eq + 8008444: ea90 0f02 teqeq r0, r2 + 8008448: d005 beq.n 8008456 <__adddf3+0x212> + 800844a: ea54 0c00 orrs.w ip, r4, r0 + 800844e: bf04 itt eq + 8008450: 4619 moveq r1, r3 + 8008452: 4610 moveq r0, r2 + 8008454: bd30 pop {r4, r5, pc} + 8008456: ea91 0f03 teq r1, r3 + 800845a: bf1e ittt ne + 800845c: 2100 movne r1, #0 + 800845e: 2000 movne r0, #0 + 8008460: bd30 popne {r4, r5, pc} + 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 + 8008466: d105 bne.n 8008474 <__adddf3+0x230> + 8008468: 0040 lsls r0, r0, #1 + 800846a: 4149 adcs r1, r1 + 800846c: bf28 it cs + 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 + 8008472: bd30 pop {r4, r5, pc} + 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 + 8008478: bf3c itt cc + 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 + 800847e: bd30 popcc {r4, r5, pc} + 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 + 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 800848c: f04f 0000 mov.w r0, #0 + 8008490: bd30 pop {r4, r5, pc} + 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 + 8008496: bf1a itte ne + 8008498: 4619 movne r1, r3 + 800849a: 4610 movne r0, r2 + 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80084a0: bf1c itt ne + 80084a2: 460b movne r3, r1 + 80084a4: 4602 movne r2, r0 + 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80084aa: bf06 itte eq + 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 80084b0: ea91 0f03 teqeq r1, r3 + 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 + 80084b8: bd30 pop {r4, r5, pc} + 80084ba: bf00 nop + +080084bc <__aeabi_ui2d>: + 80084bc: f090 0f00 teq r0, #0 + 80084c0: bf04 itt eq + 80084c2: 2100 moveq r1, #0 + 80084c4: 4770 bxeq lr + 80084c6: b530 push {r4, r5, lr} + 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 + 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 + 80084d0: f04f 0500 mov.w r5, #0 + 80084d4: f04f 0100 mov.w r1, #0 + 80084d8: e750 b.n 800837c <__adddf3+0x138> + 80084da: bf00 nop + +080084dc <__aeabi_i2d>: + 80084dc: f090 0f00 teq r0, #0 + 80084e0: bf04 itt eq + 80084e2: 2100 moveq r1, #0 + 80084e4: 4770 bxeq lr + 80084e6: b530 push {r4, r5, lr} + 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 + 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 + 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 + 80084f4: bf48 it mi + 80084f6: 4240 negmi r0, r0 + 80084f8: f04f 0100 mov.w r1, #0 + 80084fc: e73e b.n 800837c <__adddf3+0x138> + 80084fe: bf00 nop + +08008500 <__aeabi_f2d>: + 8008500: 0042 lsls r2, r0, #1 + 8008502: ea4f 01e2 mov.w r1, r2, asr #3 + 8008506: ea4f 0131 mov.w r1, r1, rrx + 800850a: ea4f 7002 mov.w r0, r2, lsl #28 + 800850e: bf1f itttt ne + 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 + 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 + 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 + 800851c: 4770 bxne lr + 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 + 8008522: bf08 it eq + 8008524: 4770 bxeq lr + 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 + 800852a: bf04 itt eq + 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 + 8008530: 4770 bxeq lr + 8008532: b530 push {r4, r5, lr} + 8008534: f44f 7460 mov.w r4, #896 @ 0x380 + 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 + 8008540: e71c b.n 800837c <__adddf3+0x138> + 8008542: bf00 nop + +08008544 <__aeabi_ul2d>: + 8008544: ea50 0201 orrs.w r2, r0, r1 + 8008548: bf08 it eq + 800854a: 4770 bxeq lr + 800854c: b530 push {r4, r5, lr} + 800854e: f04f 0500 mov.w r5, #0 + 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> + +08008554 <__aeabi_l2d>: + 8008554: ea50 0201 orrs.w r2, r0, r1 + 8008558: bf08 it eq + 800855a: 4770 bxeq lr + 800855c: b530 push {r4, r5, lr} + 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 + 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> + 8008564: 4240 negs r0, r0 + 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 + 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 + 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 + 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> + 800857a: f04f 0203 mov.w r2, #3 + 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 + 8008582: bf18 it ne + 8008584: 3203 addne r2, #3 + 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 + 800858a: bf18 it ne + 800858c: 3203 addne r2, #3 + 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 + 8008592: f1c2 0320 rsb r3, r2, #32 + 8008596: fa00 fc03 lsl.w ip, r0, r3 + 800859a: fa20 f002 lsr.w r0, r0, r2 + 800859e: fa01 fe03 lsl.w lr, r1, r3 + 80085a2: ea40 000e orr.w r0, r0, lr + 80085a6: fa21 f102 lsr.w r1, r1, r2 + 80085aa: 4414 add r4, r2 + 80085ac: e6bd b.n 800832a <__adddf3+0xe6> + 80085ae: bf00 nop + +080085b0 <__aeabi_dmul>: + 80085b0: b570 push {r4, r5, r6, lr} + 80085b2: f04f 0cff mov.w ip, #255 @ 0xff + 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 + 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 80085be: bf1d ittte ne + 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80085c4: ea94 0f0c teqne r4, ip + 80085c8: ea95 0f0c teqne r5, ip + 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> + 80085d0: 442c add r4, r5 + 80085d2: ea81 0603 eor.w r6, r1, r3 + 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 + 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 + 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 80085e2: bf18 it ne + 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> + 80085f2: fba0 ce02 umull ip, lr, r0, r2 + 80085f6: f04f 0500 mov.w r5, #0 + 80085fa: fbe1 e502 umlal lr, r5, r1, r2 + 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 + 8008602: fbe0 e503 umlal lr, r5, r0, r3 + 8008606: f04f 0600 mov.w r6, #0 + 800860a: fbe1 5603 umlal r5, r6, r1, r3 + 800860e: f09c 0f00 teq ip, #0 + 8008612: bf18 it ne + 8008614: f04e 0e01 orrne.w lr, lr, #1 + 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff + 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 + 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 + 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> + 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 + 800862a: 416d adcs r5, r5 + 800862c: eb46 0606 adc.w r6, r6, r6 + 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 + 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 + 8008640: ea4f 2ece mov.w lr, lr, lsl #11 + 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd + 8008648: bf88 it hi + 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 + 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> + 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 + 8008654: bf08 it eq + 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 + 800865a: f150 0000 adcs.w r0, r0, #0 + 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8008662: bd70 pop {r4, r5, r6, pc} + 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 + 8008668: ea46 0101 orr.w r1, r6, r1 + 800866c: ea40 0002 orr.w r0, r0, r2 + 8008670: ea81 0103 eor.w r1, r1, r3 + 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8008678: bfc2 ittt gt + 800867a: ebd4 050c rsbsgt r5, r4, ip + 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8008682: bd70 popgt {r4, r5, r6, pc} + 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 8008688: f04f 0e00 mov.w lr, #0 + 800868c: 3c01 subs r4, #1 + 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> + 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 + 8008696: bfde ittt le + 8008698: 2000 movle r0, #0 + 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 + 800869e: bd70 pople {r4, r5, r6, pc} + 80086a0: f1c4 0400 rsb r4, r4, #0 + 80086a4: 3c20 subs r4, #32 + 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> + 80086a8: 340c adds r4, #12 + 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> + 80086ac: f104 0414 add.w r4, r4, #20 + 80086b0: f1c4 0520 rsb r5, r4, #32 + 80086b4: fa00 f305 lsl.w r3, r0, r5 + 80086b8: fa20 f004 lsr.w r0, r0, r4 + 80086bc: fa01 f205 lsl.w r2, r1, r5 + 80086c0: ea40 0002 orr.w r0, r0, r2 + 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 + 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 + 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80086d0: fa21 f604 lsr.w r6, r1, r4 + 80086d4: eb42 0106 adc.w r1, r2, r6 + 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80086dc: bf08 it eq + 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80086e2: bd70 pop {r4, r5, r6, pc} + 80086e4: f1c4 040c rsb r4, r4, #12 + 80086e8: f1c4 0520 rsb r5, r4, #32 + 80086ec: fa00 f304 lsl.w r3, r0, r4 + 80086f0: fa20 f005 lsr.w r0, r0, r5 + 80086f4: fa01 f204 lsl.w r2, r1, r4 + 80086f8: ea40 0002 orr.w r0, r0, r2 + 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8008704: f141 0100 adc.w r1, r1, #0 + 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800870c: bf08 it eq + 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 8008712: bd70 pop {r4, r5, r6, pc} + 8008714: f1c4 0520 rsb r5, r4, #32 + 8008718: fa00 f205 lsl.w r2, r0, r5 + 800871c: ea4e 0e02 orr.w lr, lr, r2 + 8008720: fa20 f304 lsr.w r3, r0, r4 + 8008724: fa01 f205 lsl.w r2, r1, r5 + 8008728: ea43 0302 orr.w r3, r3, r2 + 800872c: fa21 f004 lsr.w r0, r1, r4 + 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 8008734: fa21 f204 lsr.w r2, r1, r4 + 8008738: ea20 0002 bic.w r0, r0, r2 + 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8008744: bf08 it eq + 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800874a: bd70 pop {r4, r5, r6, pc} + 800874c: f094 0f00 teq r4, #0 + 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> + 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 + 8008756: 0040 lsls r0, r0, #1 + 8008758: eb41 0101 adc.w r1, r1, r1 + 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 + 8008760: bf08 it eq + 8008762: 3c01 subeq r4, #1 + 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> + 8008766: ea41 0106 orr.w r1, r1, r6 + 800876a: f095 0f00 teq r5, #0 + 800876e: bf18 it ne + 8008770: 4770 bxne lr + 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 + 8008776: 0052 lsls r2, r2, #1 + 8008778: eb43 0303 adc.w r3, r3, r3 + 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 + 8008780: bf08 it eq + 8008782: 3d01 subeq r5, #1 + 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> + 8008786: ea43 0306 orr.w r3, r3, r6 + 800878a: 4770 bx lr + 800878c: ea94 0f0c teq r4, ip + 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8008794: bf18 it ne + 8008796: ea95 0f0c teqne r5, ip + 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> + 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80087a0: bf18 it ne + 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> + 80087a8: ea81 0103 eor.w r1, r1, r3 + 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 80087b0: f04f 0000 mov.w r0, #0 + 80087b4: bd70 pop {r4, r5, r6, pc} + 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80087ba: bf06 itte eq + 80087bc: 4610 moveq r0, r2 + 80087be: 4619 moveq r1, r3 + 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> + 80087c6: ea94 0f0c teq r4, ip + 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> + 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> + 80087d2: ea95 0f0c teq r5, ip + 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> + 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 80087dc: bf1c itt ne + 80087de: 4610 movne r0, r2 + 80087e0: 4619 movne r1, r3 + 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> + 80087e4: ea81 0103 eor.w r1, r1, r3 + 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 + 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 80087f4: f04f 0000 mov.w r0, #0 + 80087f8: bd70 pop {r4, r5, r6, pc} + 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 + 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 + 8008802: bd70 pop {r4, r5, r6, pc} + +08008804 <__aeabi_ddiv>: + 8008804: b570 push {r4, r5, r6, lr} + 8008806: f04f 0cff mov.w ip, #255 @ 0xff + 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 + 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 8008812: bf1d ittte ne + 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8008818: ea94 0f0c teqne r4, ip + 800881c: ea95 0f0c teqne r5, ip + 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> + 8008824: eba4 0405 sub.w r4, r4, r5 + 8008828: ea81 0e03 eor.w lr, r1, r3 + 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8008830: ea4f 3101 mov.w r1, r1, lsl #12 + 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> + 8008838: ea4f 3303 mov.w r3, r3, lsl #12 + 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 + 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 + 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 + 8008848: ea4f 2202 mov.w r2, r2, lsl #8 + 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 + 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 + 8008854: ea4f 2600 mov.w r6, r0, lsl #8 + 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 + 800885c: 429d cmp r5, r3 + 800885e: bf08 it eq + 8008860: 4296 cmpeq r6, r2 + 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd + 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 + 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> + 800886c: 085b lsrs r3, r3, #1 + 800886e: ea4f 0232 mov.w r2, r2, rrx + 8008872: 1ab6 subs r6, r6, r2 + 8008874: eb65 0503 sbc.w r5, r5, r3 + 8008878: 085b lsrs r3, r3, #1 + 800887a: ea4f 0232 mov.w r2, r2, rrx + 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 + 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 + 8008886: ebb6 0e02 subs.w lr, r6, r2 + 800888a: eb75 0e03 sbcs.w lr, r5, r3 + 800888e: bf22 ittt cs + 8008890: 1ab6 subcs r6, r6, r2 + 8008892: 4675 movcs r5, lr + 8008894: ea40 000c orrcs.w r0, r0, ip + 8008898: 085b lsrs r3, r3, #1 + 800889a: ea4f 0232 mov.w r2, r2, rrx + 800889e: ebb6 0e02 subs.w lr, r6, r2 + 80088a2: eb75 0e03 sbcs.w lr, r5, r3 + 80088a6: bf22 ittt cs + 80088a8: 1ab6 subcs r6, r6, r2 + 80088aa: 4675 movcs r5, lr + 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 80088b0: 085b lsrs r3, r3, #1 + 80088b2: ea4f 0232 mov.w r2, r2, rrx + 80088b6: ebb6 0e02 subs.w lr, r6, r2 + 80088ba: eb75 0e03 sbcs.w lr, r5, r3 + 80088be: bf22 ittt cs + 80088c0: 1ab6 subcs r6, r6, r2 + 80088c2: 4675 movcs r5, lr + 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 80088c8: 085b lsrs r3, r3, #1 + 80088ca: ea4f 0232 mov.w r2, r2, rrx + 80088ce: ebb6 0e02 subs.w lr, r6, r2 + 80088d2: eb75 0e03 sbcs.w lr, r5, r3 + 80088d6: bf22 ittt cs + 80088d8: 1ab6 subcs r6, r6, r2 + 80088da: 4675 movcs r5, lr + 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 80088e0: ea55 0e06 orrs.w lr, r5, r6 + 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> + 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 + 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 + 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 + 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 + 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 + 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 + 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 + 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> + 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 + 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> + 800890a: ea41 0100 orr.w r1, r1, r0 + 800890e: f04f 0000 mov.w r0, #0 + 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 + 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> + 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 + 800891c: bf04 itt eq + 800891e: 4301 orreq r1, r0 + 8008920: 2000 moveq r0, #0 + 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd + 8008926: bf88 it hi + 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 + 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> + 8008930: ebb5 0c03 subs.w ip, r5, r3 + 8008934: bf04 itt eq + 8008936: ebb6 0c02 subseq.w ip, r6, r2 + 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 + 800893e: f150 0000 adcs.w r0, r0, #0 + 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8008946: bd70 pop {r4, r5, r6, pc} + 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 + 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 + 8008954: bfc2 ittt gt + 8008956: ebd4 050c rsbsgt r5, r4, ip + 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 800895e: bd70 popgt {r4, r5, r6, pc} + 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 8008964: f04f 0e00 mov.w lr, #0 + 8008968: 3c01 subs r4, #1 + 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> + 800896c: ea45 0e06 orr.w lr, r5, r6 + 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> + 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8008976: ea94 0f0c teq r4, ip + 800897a: bf08 it eq + 800897c: ea95 0f0c teqeq r5, ip + 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> + 8008984: ea94 0f0c teq r4, ip + 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> + 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> + 8008992: ea95 0f0c teq r5, ip + 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> + 800899a: 4610 mov r0, r2 + 800899c: 4619 mov r1, r3 + 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> + 80089a0: ea95 0f0c teq r5, ip + 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> + 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> + 80089ae: 4610 mov r0, r2 + 80089b0: 4619 mov r1, r3 + 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> + 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80089b8: bf18 it ne + 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> + 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> + 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> + 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> + +080089d4 <__gedf2>: + 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff + 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> + 80089da: bf00 nop + +080089dc <__ledf2>: + 80089dc: f04f 0c01 mov.w ip, #1 + 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> + 80089e2: bf00 nop + +080089e4 <__cmpdf2>: + 80089e4: f04f 0c01 mov.w ip, #1 + 80089e8: f84d cd04 str.w ip, [sp, #-4]! + 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 + 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 + 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 + 80089f8: bf18 it ne + 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> + 8008a00: b001 add sp, #4 + 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 8008a06: bf0c ite eq + 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8008a0c: ea91 0f03 teqne r1, r3 + 8008a10: bf02 ittt eq + 8008a12: ea90 0f02 teqeq r0, r2 + 8008a16: 2000 moveq r0, #0 + 8008a18: 4770 bxeq lr + 8008a1a: f110 0f00 cmn.w r0, #0 + 8008a1e: ea91 0f03 teq r1, r3 + 8008a22: bf58 it pl + 8008a24: 4299 cmppl r1, r3 + 8008a26: bf08 it eq + 8008a28: 4290 cmpeq r0, r2 + 8008a2a: bf2c ite cs + 8008a2c: 17d8 asrcs r0, r3, #31 + 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 + 8008a32: f040 0001 orr.w r0, r0, #1 + 8008a36: 4770 bx lr + 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 + 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 + 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> + 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> + 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 + 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 + 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> + 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> + 8008a58: f85d 0b04 ldr.w r0, [sp], #4 + 8008a5c: 4770 bx lr + 8008a5e: bf00 nop + +08008a60 <__aeabi_cdrcmple>: + 8008a60: 4684 mov ip, r0 + 8008a62: 4610 mov r0, r2 + 8008a64: 4662 mov r2, ip + 8008a66: 468c mov ip, r1 + 8008a68: 4619 mov r1, r3 + 8008a6a: 4663 mov r3, ip + 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> + 8008a6e: bf00 nop + +08008a70 <__aeabi_cdcmpeq>: + 8008a70: b501 push {r0, lr} + 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> + 8008a76: 2800 cmp r0, #0 + 8008a78: bf48 it mi + 8008a7a: f110 0f00 cmnmi.w r0, #0 + 8008a7e: bd01 pop {r0, pc} + +08008a80 <__aeabi_dcmpeq>: + 8008a80: f84d ed08 str.w lr, [sp, #-8]! + 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> + 8008a88: bf0c ite eq + 8008a8a: 2001 moveq r0, #1 + 8008a8c: 2000 movne r0, #0 + 8008a8e: f85d fb08 ldr.w pc, [sp], #8 + 8008a92: bf00 nop + +08008a94 <__aeabi_dcmplt>: + 8008a94: f84d ed08 str.w lr, [sp, #-8]! + 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> + 8008a9c: bf34 ite cc + 8008a9e: 2001 movcc r0, #1 + 8008aa0: 2000 movcs r0, #0 + 8008aa2: f85d fb08 ldr.w pc, [sp], #8 + 8008aa6: bf00 nop + +08008aa8 <__aeabi_dcmple>: + 8008aa8: f84d ed08 str.w lr, [sp, #-8]! + 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> + 8008ab0: bf94 ite ls + 8008ab2: 2001 movls r0, #1 + 8008ab4: 2000 movhi r0, #0 + 8008ab6: f85d fb08 ldr.w pc, [sp], #8 + 8008aba: bf00 nop + +08008abc <__aeabi_dcmpge>: + 8008abc: f84d ed08 str.w lr, [sp, #-8]! + 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> + 8008ac4: bf94 ite ls + 8008ac6: 2001 movls r0, #1 + 8008ac8: 2000 movhi r0, #0 + 8008aca: f85d fb08 ldr.w pc, [sp], #8 + 8008ace: bf00 nop + +08008ad0 <__aeabi_dcmpgt>: + 8008ad0: f84d ed08 str.w lr, [sp, #-8]! + 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> + 8008ad8: bf34 ite cc + 8008ada: 2001 movcc r0, #1 + 8008adc: 2000 movcs r0, #0 + 8008ade: f85d fb08 ldr.w pc, [sp], #8 + 8008ae2: bf00 nop + +08008ae4 <__aeabi_dcmpun>: + 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 + 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 + 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> + 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> + 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 + 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 + 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> + 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> + 8008b04: f04f 0000 mov.w r0, #0 + 8008b08: 4770 bx lr + 8008b0a: f04f 0001 mov.w r0, #1 + 8008b0e: 4770 bx lr + +08008b10 <__aeabi_d2iz>: + 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 + 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 + 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> + 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> + 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 + 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> + 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 + 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 + 8008b36: fa23 f002 lsr.w r0, r3, r2 + 8008b3a: bf18 it ne + 8008b3c: 4240 negne r0, r0 + 8008b3e: 4770 bx lr + 8008b40: f04f 0000 mov.w r0, #0 + 8008b44: 4770 bx lr + 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> + 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 + 8008b50: bf08 it eq + 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 + 8008b56: 4770 bx lr + 8008b58: f04f 0000 mov.w r0, #0 + 8008b5c: 4770 bx lr + 8008b5e: bf00 nop + +08008b60 <__aeabi_d2f>: + 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 + 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 + 8008b68: bf24 itt cs + 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 + 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 + 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> + 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 + 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 + 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 + 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 + 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 + 8008b88: bf08 it eq + 8008b8a: f020 0001 biceq.w r0, r0, #1 + 8008b8e: 4770 bx lr + 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 + 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> + 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 + 8008b9a: bfbc itt lt + 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 + 8008ba0: 4770 bxlt lr + 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 + 8008baa: f1c2 0218 rsb r2, r2, #24 + 8008bae: f1c2 0c20 rsb ip, r2, #32 + 8008bb2: fa10 f30c lsls.w r3, r0, ip + 8008bb6: fa20 f002 lsr.w r0, r0, r2 + 8008bba: bf18 it ne + 8008bbc: f040 0001 orrne.w r0, r0, #1 + 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 + 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 + 8008bc8: fa03 fc0c lsl.w ip, r3, ip + 8008bcc: ea40 000c orr.w r0, r0, ip + 8008bd0: fa23 f302 lsr.w r3, r3, r2 + 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 + 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> + 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 + 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> + 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 + 8008be4: bf1e ittt ne + 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 + 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 + 8008bee: 4770 bxne lr + 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 + 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 + 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8008bfc: 4770 bx lr + 8008bfe: bf00 nop + +08008c00 <__aeabi_frsub>: + 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 + 8008c04: e002 b.n 8008c0c <__addsf3> + 8008c06: bf00 nop + +08008c08 <__aeabi_fsub>: + 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 + +08008c0c <__addsf3>: + 8008c0c: 0042 lsls r2, r0, #1 + 8008c0e: bf1f itttt ne + 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 + 8008c14: ea92 0f03 teqne r2, r3 + 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 + 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> + 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 + 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 + 8008c2a: bfc1 itttt gt + 8008c2c: 18d2 addgt r2, r2, r3 + 8008c2e: 4041 eorgt r1, r0 + 8008c30: 4048 eorgt r0, r1 + 8008c32: 4041 eorgt r1, r0 + 8008c34: bfb8 it lt + 8008c36: 425b neglt r3, r3 + 8008c38: 2b19 cmp r3, #25 + 8008c3a: bf88 it hi + 8008c3c: 4770 bxhi lr + 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 + 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 + 8008c4a: bf18 it ne + 8008c4c: 4240 negne r0, r0 + 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 + 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 + 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 + 8008c5a: bf18 it ne + 8008c5c: 4249 negne r1, r1 + 8008c5e: ea92 0f03 teq r2, r3 + 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> + 8008c64: f1a2 0201 sub.w r2, r2, #1 + 8008c68: fa41 fc03 asr.w ip, r1, r3 + 8008c6c: eb10 000c adds.w r0, r0, ip + 8008c70: f1c3 0320 rsb r3, r3, #32 + 8008c74: fa01 f103 lsl.w r1, r1, r3 + 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 + 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> + 8008c7e: 4249 negs r1, r1 + 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 + 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 + 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> + 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 + 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> + 8008c90: 0840 lsrs r0, r0, #1 + 8008c92: ea4f 0131 mov.w r1, r1, rrx + 8008c96: f102 0201 add.w r2, r2, #1 + 8008c9a: 2afe cmp r2, #254 @ 0xfe + 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> + 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 + 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8008ca6: bf08 it eq + 8008ca8: f020 0001 biceq.w r0, r0, #1 + 8008cac: ea40 0003 orr.w r0, r0, r3 + 8008cb0: 4770 bx lr + 8008cb2: 0049 lsls r1, r1, #1 + 8008cb4: eb40 0000 adc.w r0, r0, r0 + 8008cb8: 3a01 subs r2, #1 + 8008cba: bf28 it cs + 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 + 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> + 8008cc2: fab0 fc80 clz ip, r0 + 8008cc6: f1ac 0c08 sub.w ip, ip, #8 + 8008cca: ebb2 020c subs.w r2, r2, ip + 8008cce: fa00 f00c lsl.w r0, r0, ip + 8008cd2: bfaa itet ge + 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 + 8008cd8: 4252 neglt r2, r2 + 8008cda: 4318 orrge r0, r3 + 8008cdc: bfbc itt lt + 8008cde: 40d0 lsrlt r0, r2 + 8008ce0: 4318 orrlt r0, r3 + 8008ce2: 4770 bx lr + 8008ce4: f092 0f00 teq r2, #0 + 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 + 8008cec: bf06 itte eq + 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 + 8008cf2: 3201 addeq r2, #1 + 8008cf4: 3b01 subne r3, #1 + 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> + 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 + 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 + 8008d00: bf18 it ne + 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> + 8008d08: ea92 0f03 teq r2, r3 + 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> + 8008d0e: f092 0f00 teq r2, #0 + 8008d12: bf08 it eq + 8008d14: 4608 moveq r0, r1 + 8008d16: 4770 bx lr + 8008d18: ea90 0f01 teq r0, r1 + 8008d1c: bf1c itt ne + 8008d1e: 2000 movne r0, #0 + 8008d20: 4770 bxne lr + 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 + 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> + 8008d28: 0040 lsls r0, r0, #1 + 8008d2a: bf28 it cs + 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 + 8008d30: 4770 bx lr + 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 + 8008d36: bf3c itt cc + 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 + 8008d3c: 4770 bxcc lr + 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 + 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 + 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8008d4a: 4770 bx lr + 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 + 8008d50: bf16 itet ne + 8008d52: 4608 movne r0, r1 + 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 + 8008d58: 4601 movne r1, r0 + 8008d5a: 0242 lsls r2, r0, #9 + 8008d5c: bf06 itte eq + 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 + 8008d62: ea90 0f01 teqeq r0, r1 + 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 + 8008d6a: 4770 bx lr + +08008d6c <__aeabi_ui2f>: + 8008d6c: f04f 0300 mov.w r3, #0 + 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> + 8008d72: bf00 nop + +08008d74 <__aeabi_i2f>: + 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 + 8008d78: bf48 it mi + 8008d7a: 4240 negmi r0, r0 + 8008d7c: ea5f 0c00 movs.w ip, r0 + 8008d80: bf08 it eq + 8008d82: 4770 bxeq lr + 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 + 8008d88: 4601 mov r1, r0 + 8008d8a: f04f 0000 mov.w r0, #0 + 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> + +08008d90 <__aeabi_ul2f>: + 8008d90: ea50 0201 orrs.w r2, r0, r1 + 8008d94: bf08 it eq + 8008d96: 4770 bxeq lr + 8008d98: f04f 0300 mov.w r3, #0 + 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> + 8008d9e: bf00 nop + +08008da0 <__aeabi_l2f>: + 8008da0: ea50 0201 orrs.w r2, r0, r1 + 8008da4: bf08 it eq + 8008da6: 4770 bxeq lr + 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 + 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> + 8008dae: 4240 negs r0, r0 + 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8008db4: ea5f 0c01 movs.w ip, r1 + 8008db8: bf02 ittt eq + 8008dba: 4684 moveq ip, r0 + 8008dbc: 4601 moveq r1, r0 + 8008dbe: 2000 moveq r0, #0 + 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 + 8008dc4: bf08 it eq + 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 + 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 + 8008dce: fabc f28c clz r2, ip + 8008dd2: 3a08 subs r2, #8 + 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 + 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> + 8008dda: fa01 fc02 lsl.w ip, r1, r2 + 8008dde: 4463 add r3, ip + 8008de0: fa00 fc02 lsl.w ip, r0, r2 + 8008de4: f1c2 0220 rsb r2, r2, #32 + 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 + 8008dec: fa20 f202 lsr.w r2, r0, r2 + 8008df0: eb43 0002 adc.w r0, r3, r2 + 8008df4: bf08 it eq + 8008df6: f020 0001 biceq.w r0, r0, #1 + 8008dfa: 4770 bx lr + 8008dfc: f102 0220 add.w r2, r2, #32 + 8008e00: fa01 fc02 lsl.w ip, r1, r2 + 8008e04: f1c2 0220 rsb r2, r2, #32 + 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 + 8008e0c: fa21 f202 lsr.w r2, r1, r2 + 8008e10: eb43 0002 adc.w r0, r3, r2 + 8008e14: bf08 it eq + 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8008e1a: 4770 bx lr + +08008e1c <__aeabi_fmul>: + 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff + 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8008e24: bf1e ittt ne + 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8008e2a: ea92 0f0c teqne r2, ip + 8008e2e: ea93 0f0c teqne r3, ip + 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> + 8008e34: 441a add r2, r3 + 8008e36: ea80 0c01 eor.w ip, r0, r1 + 8008e3a: 0240 lsls r0, r0, #9 + 8008e3c: bf18 it ne + 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 + 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> + 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 + 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 + 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 + 8008e50: fba0 3101 umull r3, r1, r0, r1 + 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 + 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 + 8008e5c: bf3e ittt cc + 8008e5e: 0049 lslcc r1, r1, #1 + 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 + 8008e64: 005b lslcc r3, r3, #1 + 8008e66: ea40 0001 orr.w r0, r0, r1 + 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f + 8008e6e: 2afd cmp r2, #253 @ 0xfd + 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> + 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8008e7a: bf08 it eq + 8008e7c: f020 0001 biceq.w r0, r0, #1 + 8008e80: 4770 bx lr + 8008e82: f090 0f00 teq r0, #0 + 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 + 8008e8a: bf08 it eq + 8008e8c: 0249 lsleq r1, r1, #9 + 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 + 8008e96: 3a7f subs r2, #127 @ 0x7f + 8008e98: bfc2 ittt gt + 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff + 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8008ea2: 4770 bxgt lr + 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8008ea8: f04f 0300 mov.w r3, #0 + 8008eac: 3a01 subs r2, #1 + 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> + 8008eb0: f112 0f19 cmn.w r2, #25 + 8008eb4: bfdc itt le + 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 + 8008eba: 4770 bxle lr + 8008ebc: f1c2 0200 rsb r2, r2, #0 + 8008ec0: 0041 lsls r1, r0, #1 + 8008ec2: fa21 f102 lsr.w r1, r1, r2 + 8008ec6: f1c2 0220 rsb r2, r2, #32 + 8008eca: fa00 fc02 lsl.w ip, r0, r2 + 8008ece: ea5f 0031 movs.w r0, r1, rrx + 8008ed2: f140 0000 adc.w r0, r0, #0 + 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 + 8008eda: bf08 it eq + 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8008ee0: 4770 bx lr + 8008ee2: f092 0f00 teq r2, #0 + 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 + 8008eea: bf02 ittt eq + 8008eec: 0040 lsleq r0, r0, #1 + 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 + 8008ef2: 3a01 subeq r2, #1 + 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> + 8008ef6: ea40 000c orr.w r0, r0, ip + 8008efa: f093 0f00 teq r3, #0 + 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 + 8008f02: bf02 ittt eq + 8008f04: 0049 lsleq r1, r1, #1 + 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 + 8008f0a: 3b01 subeq r3, #1 + 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> + 8008f0e: ea41 010c orr.w r1, r1, ip + 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> + 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8008f18: ea92 0f0c teq r2, ip + 8008f1c: bf18 it ne + 8008f1e: ea93 0f0c teqne r3, ip + 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> + 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 + 8008f28: bf18 it ne + 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 + 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> + 8008f30: ea80 0001 eor.w r0, r0, r1 + 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 + 8008f38: 4770 bx lr + 8008f3a: f090 0f00 teq r0, #0 + 8008f3e: bf17 itett ne + 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 + 8008f44: 4608 moveq r0, r1 + 8008f46: f091 0f00 teqne r1, #0 + 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 + 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> + 8008f50: ea92 0f0c teq r2, ip + 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> + 8008f56: 0242 lsls r2, r0, #9 + 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> + 8008f5a: ea93 0f0c teq r3, ip + 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> + 8008f60: 024b lsls r3, r1, #9 + 8008f62: bf18 it ne + 8008f64: 4608 movne r0, r1 + 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> + 8008f68: ea80 0001 eor.w r0, r0, r1 + 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 + 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 + 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8008f78: 4770 bx lr + 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 + 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 + 8008f82: 4770 bx lr + +08008f84 <__aeabi_fdiv>: + 8008f84: f04f 0cff mov.w ip, #255 @ 0xff + 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8008f8c: bf1e ittt ne + 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8008f92: ea92 0f0c teqne r2, ip + 8008f96: ea93 0f0c teqne r3, ip + 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> + 8008f9c: eba2 0203 sub.w r2, r2, r3 + 8008fa0: ea80 0c01 eor.w ip, r0, r1 + 8008fa4: 0249 lsls r1, r1, #9 + 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 + 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> + 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 + 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 + 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 + 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 + 8008fbc: 428b cmp r3, r1 + 8008fbe: bf38 it cc + 8008fc0: 005b lslcc r3, r3, #1 + 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d + 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 + 8008fca: 428b cmp r3, r1 + 8008fcc: bf24 itt cs + 8008fce: 1a5b subcs r3, r3, r1 + 8008fd0: ea40 000c orrcs.w r0, r0, ip + 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 + 8008fd8: bf24 itt cs + 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 + 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 + 8008fe6: bf24 itt cs + 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 + 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 + 8008ff4: bf24 itt cs + 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 + 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8008ffe: 011b lsls r3, r3, #4 + 8009000: bf18 it ne + 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 + 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> + 8009008: 2afd cmp r2, #253 @ 0xfd + 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> + 800900e: 428b cmp r3, r1 + 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8009014: bf08 it eq + 8009016: f020 0001 biceq.w r0, r0, #1 + 800901a: 4770 bx lr + 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 + 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8009024: 327f adds r2, #127 @ 0x7f + 8009026: bfc2 ittt gt + 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff + 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8009030: 4770 bxgt lr + 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 + 8009036: f04f 0300 mov.w r3, #0 + 800903a: 3a01 subs r2, #1 + 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> + 800903e: f092 0f00 teq r2, #0 + 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 + 8009046: bf02 ittt eq + 8009048: 0040 lsleq r0, r0, #1 + 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 + 800904e: 3a01 subeq r2, #1 + 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> + 8009052: ea40 000c orr.w r0, r0, ip + 8009056: f093 0f00 teq r3, #0 + 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 + 800905e: bf02 ittt eq + 8009060: 0049 lsleq r1, r1, #1 + 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 + 8009066: 3b01 subeq r3, #1 + 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> + 800906a: ea41 010c orr.w r1, r1, ip + 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> + 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8009074: ea92 0f0c teq r2, ip + 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> + 800907a: 0242 lsls r2, r0, #9 + 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> + 8009080: ea93 0f0c teq r3, ip + 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> + 8009088: 4608 mov r0, r1 + 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> + 800908c: ea93 0f0c teq r3, ip + 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> + 8009092: 024b lsls r3, r1, #9 + 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> + 8009098: 4608 mov r0, r1 + 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> + 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 + 80090a0: bf18 it ne + 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 + 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> + 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 + 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> + 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 + 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> + 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> + 80090ba: bf00 nop + +080090bc <__gesf2>: + 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff + 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> + 80090c2: bf00 nop + +080090c4 <__lesf2>: + 80090c4: f04f 0c01 mov.w ip, #1 + 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> + 80090ca: bf00 nop + +080090cc <__cmpsf2>: + 80090cc: f04f 0c01 mov.w ip, #1 + 80090d0: f84d cd04 str.w ip, [sp, #-4]! + 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 + 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 + 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 + 80090e0: bf18 it ne + 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> + 80090e8: b001 add sp, #4 + 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 + 80090ee: bf18 it ne + 80090f0: ea90 0f01 teqne r0, r1 + 80090f4: bf58 it pl + 80090f6: ebb2 0003 subspl.w r0, r2, r3 + 80090fa: bf88 it hi + 80090fc: 17c8 asrhi r0, r1, #31 + 80090fe: bf38 it cc + 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 + 8009104: bf18 it ne + 8009106: f040 0001 orrne.w r0, r0, #1 + 800910a: 4770 bx lr + 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 + 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> + 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 + 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> + 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 + 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> + 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 + 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> + 8009124: f85d 0b04 ldr.w r0, [sp], #4 + 8009128: 4770 bx lr + 800912a: bf00 nop + +0800912c <__aeabi_cfrcmple>: + 800912c: 4684 mov ip, r0 + 800912e: 4608 mov r0, r1 + 8009130: 4661 mov r1, ip + 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> + +08009134 <__aeabi_cfcmpeq>: + 8009134: b50f push {r0, r1, r2, r3, lr} + 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> + 800913a: 2800 cmp r0, #0 + 800913c: bf48 it mi + 800913e: f110 0f00 cmnmi.w r0, #0 + 8009142: bd0f pop {r0, r1, r2, r3, pc} + +08009144 <__aeabi_fcmpeq>: + 8009144: f84d ed08 str.w lr, [sp, #-8]! + 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> + 800914c: bf0c ite eq + 800914e: 2001 moveq r0, #1 + 8009150: 2000 movne r0, #0 + 8009152: f85d fb08 ldr.w pc, [sp], #8 + 8009156: bf00 nop + +08009158 <__aeabi_fcmplt>: + 8009158: f84d ed08 str.w lr, [sp, #-8]! + 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> + 8009160: bf34 ite cc + 8009162: 2001 movcc r0, #1 + 8009164: 2000 movcs r0, #0 + 8009166: f85d fb08 ldr.w pc, [sp], #8 + 800916a: bf00 nop + +0800916c <__aeabi_fcmple>: + 800916c: f84d ed08 str.w lr, [sp, #-8]! + 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> + 8009174: bf94 ite ls + 8009176: 2001 movls r0, #1 + 8009178: 2000 movhi r0, #0 + 800917a: f85d fb08 ldr.w pc, [sp], #8 + 800917e: bf00 nop + +08009180 <__aeabi_fcmpge>: + 8009180: f84d ed08 str.w lr, [sp, #-8]! + 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> + 8009188: bf94 ite ls + 800918a: 2001 movls r0, #1 + 800918c: 2000 movhi r0, #0 + 800918e: f85d fb08 ldr.w pc, [sp], #8 + 8009192: bf00 nop + +08009194 <__aeabi_fcmpgt>: + 8009194: f84d ed08 str.w lr, [sp, #-8]! + 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> + 800919c: bf34 ite cc + 800919e: 2001 movcc r0, #1 + 80091a0: 2000 movcs r0, #0 + 80091a2: f85d fb08 ldr.w pc, [sp], #8 + 80091a6: bf00 nop + +080091a8 <__aeabi_f2iz>: + 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 + 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 + 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> + 80091b2: f04f 039e mov.w r3, #158 @ 0x9e + 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 + 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> + 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 + 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 + 80091c8: fa23 f002 lsr.w r0, r3, r2 + 80091cc: bf18 it ne + 80091ce: 4240 negne r0, r0 + 80091d0: 4770 bx lr + 80091d2: f04f 0000 mov.w r0, #0 + 80091d6: 4770 bx lr + 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 + 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> + 80091de: 0242 lsls r2, r0, #9 + 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> + 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 + 80091e6: bf08 it eq + 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 + 80091ec: 4770 bx lr + 80091ee: f04f 0000 mov.w r0, #0 + 80091f2: 4770 bx lr + +080091f4 <__aeabi_ldivmod>: + 80091f4: b97b cbnz r3, 8009216 <__aeabi_ldivmod+0x22> + 80091f6: b972 cbnz r2, 8009216 <__aeabi_ldivmod+0x22> + 80091f8: 2900 cmp r1, #0 + 80091fa: bfbe ittt lt + 80091fc: 2000 movlt r0, #0 + 80091fe: f04f 4100 movlt.w r1, #2147483648 @ 0x80000000 + 8009202: e006 blt.n 8009212 <__aeabi_ldivmod+0x1e> + 8009204: bf08 it eq + 8009206: 2800 cmpeq r0, #0 + 8009208: bf1c itt ne + 800920a: f06f 4100 mvnne.w r1, #2147483648 @ 0x80000000 + 800920e: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8009212: f000 b9d7 b.w 80095c4 <__aeabi_idiv0> + 8009216: f1ad 0c08 sub.w ip, sp, #8 + 800921a: e96d ce04 strd ip, lr, [sp, #-16]! + 800921e: 2900 cmp r1, #0 + 8009220: db09 blt.n 8009236 <__aeabi_ldivmod+0x42> + 8009222: 2b00 cmp r3, #0 + 8009224: db1a blt.n 800925c <__aeabi_ldivmod+0x68> + 8009226: f000 f84d bl 80092c4 <__udivmoddi4> + 800922a: f8dd e004 ldr.w lr, [sp, #4] + 800922e: e9dd 2302 ldrd r2, r3, [sp, #8] + 8009232: b004 add sp, #16 + 8009234: 4770 bx lr + 8009236: 4240 negs r0, r0 + 8009238: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800923c: 2b00 cmp r3, #0 + 800923e: db1b blt.n 8009278 <__aeabi_ldivmod+0x84> + 8009240: f000 f840 bl 80092c4 <__udivmoddi4> + 8009244: f8dd e004 ldr.w lr, [sp, #4] + 8009248: e9dd 2302 ldrd r2, r3, [sp, #8] + 800924c: b004 add sp, #16 + 800924e: 4240 negs r0, r0 + 8009250: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8009254: 4252 negs r2, r2 + 8009256: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 800925a: 4770 bx lr + 800925c: 4252 negs r2, r2 + 800925e: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8009262: f000 f82f bl 80092c4 <__udivmoddi4> + 8009266: f8dd e004 ldr.w lr, [sp, #4] + 800926a: e9dd 2302 ldrd r2, r3, [sp, #8] + 800926e: b004 add sp, #16 + 8009270: 4240 negs r0, r0 + 8009272: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8009276: 4770 bx lr + 8009278: 4252 negs r2, r2 + 800927a: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 800927e: f000 f821 bl 80092c4 <__udivmoddi4> + 8009282: f8dd e004 ldr.w lr, [sp, #4] + 8009286: e9dd 2302 ldrd r2, r3, [sp, #8] + 800928a: b004 add sp, #16 + 800928c: 4252 negs r2, r2 + 800928e: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8009292: 4770 bx lr + +08009294 <__aeabi_uldivmod>: + 8009294: b953 cbnz r3, 80092ac <__aeabi_uldivmod+0x18> + 8009296: b94a cbnz r2, 80092ac <__aeabi_uldivmod+0x18> + 8009298: 2900 cmp r1, #0 + 800929a: bf08 it eq + 800929c: 2800 cmpeq r0, #0 + 800929e: bf1c itt ne + 80092a0: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 80092a4: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 80092a8: f000 b98c b.w 80095c4 <__aeabi_idiv0> + 80092ac: f1ad 0c08 sub.w ip, sp, #8 + 80092b0: e96d ce04 strd ip, lr, [sp, #-16]! + 80092b4: f000 f806 bl 80092c4 <__udivmoddi4> + 80092b8: f8dd e004 ldr.w lr, [sp, #4] + 80092bc: e9dd 2302 ldrd r2, r3, [sp, #8] + 80092c0: b004 add sp, #16 + 80092c2: 4770 bx lr + +080092c4 <__udivmoddi4>: + 80092c4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80092c8: 9d08 ldr r5, [sp, #32] + 80092ca: 468e mov lr, r1 + 80092cc: 4604 mov r4, r0 + 80092ce: 4688 mov r8, r1 + 80092d0: 2b00 cmp r3, #0 + 80092d2: d14a bne.n 800936a <__udivmoddi4+0xa6> + 80092d4: 428a cmp r2, r1 + 80092d6: 4617 mov r7, r2 + 80092d8: d962 bls.n 80093a0 <__udivmoddi4+0xdc> + 80092da: fab2 f682 clz r6, r2 + 80092de: b14e cbz r6, 80092f4 <__udivmoddi4+0x30> + 80092e0: f1c6 0320 rsb r3, r6, #32 + 80092e4: fa01 f806 lsl.w r8, r1, r6 + 80092e8: fa20 f303 lsr.w r3, r0, r3 + 80092ec: 40b7 lsls r7, r6 + 80092ee: ea43 0808 orr.w r8, r3, r8 + 80092f2: 40b4 lsls r4, r6 + 80092f4: ea4f 4e17 mov.w lr, r7, lsr #16 + 80092f8: fbb8 f1fe udiv r1, r8, lr + 80092fc: fa1f fc87 uxth.w ip, r7 + 8009300: fb0e 8811 mls r8, lr, r1, r8 + 8009304: fb01 f20c mul.w r2, r1, ip + 8009308: 0c23 lsrs r3, r4, #16 + 800930a: ea43 4308 orr.w r3, r3, r8, lsl #16 + 800930e: 429a cmp r2, r3 + 8009310: d909 bls.n 8009326 <__udivmoddi4+0x62> + 8009312: 18fb adds r3, r7, r3 + 8009314: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8009318: f080 80eb bcs.w 80094f2 <__udivmoddi4+0x22e> + 800931c: 429a cmp r2, r3 + 800931e: f240 80e8 bls.w 80094f2 <__udivmoddi4+0x22e> + 8009322: 3902 subs r1, #2 + 8009324: 443b add r3, r7 + 8009326: 1a9a subs r2, r3, r2 + 8009328: fbb2 f0fe udiv r0, r2, lr + 800932c: fb0e 2210 mls r2, lr, r0, r2 + 8009330: fb00 fc0c mul.w ip, r0, ip + 8009334: b2a3 uxth r3, r4 + 8009336: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800933a: 459c cmp ip, r3 + 800933c: d909 bls.n 8009352 <__udivmoddi4+0x8e> + 800933e: 18fb adds r3, r7, r3 + 8009340: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 8009344: f080 80d7 bcs.w 80094f6 <__udivmoddi4+0x232> + 8009348: 459c cmp ip, r3 + 800934a: f240 80d4 bls.w 80094f6 <__udivmoddi4+0x232> + 800934e: 443b add r3, r7 + 8009350: 3802 subs r0, #2 + 8009352: ea40 4001 orr.w r0, r0, r1, lsl #16 + 8009356: 2100 movs r1, #0 + 8009358: eba3 030c sub.w r3, r3, ip + 800935c: b11d cbz r5, 8009366 <__udivmoddi4+0xa2> + 800935e: 2200 movs r2, #0 + 8009360: 40f3 lsrs r3, r6 + 8009362: e9c5 3200 strd r3, r2, [r5] + 8009366: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800936a: 428b cmp r3, r1 + 800936c: d905 bls.n 800937a <__udivmoddi4+0xb6> + 800936e: b10d cbz r5, 8009374 <__udivmoddi4+0xb0> + 8009370: e9c5 0100 strd r0, r1, [r5] + 8009374: 2100 movs r1, #0 + 8009376: 4608 mov r0, r1 + 8009378: e7f5 b.n 8009366 <__udivmoddi4+0xa2> + 800937a: fab3 f183 clz r1, r3 + 800937e: 2900 cmp r1, #0 + 8009380: d146 bne.n 8009410 <__udivmoddi4+0x14c> + 8009382: 4573 cmp r3, lr + 8009384: d302 bcc.n 800938c <__udivmoddi4+0xc8> + 8009386: 4282 cmp r2, r0 + 8009388: f200 8108 bhi.w 800959c <__udivmoddi4+0x2d8> + 800938c: 1a84 subs r4, r0, r2 + 800938e: eb6e 0203 sbc.w r2, lr, r3 + 8009392: 2001 movs r0, #1 + 8009394: 4690 mov r8, r2 + 8009396: 2d00 cmp r5, #0 + 8009398: d0e5 beq.n 8009366 <__udivmoddi4+0xa2> + 800939a: e9c5 4800 strd r4, r8, [r5] + 800939e: e7e2 b.n 8009366 <__udivmoddi4+0xa2> + 80093a0: 2a00 cmp r2, #0 + 80093a2: f000 8091 beq.w 80094c8 <__udivmoddi4+0x204> + 80093a6: fab2 f682 clz r6, r2 + 80093aa: 2e00 cmp r6, #0 + 80093ac: f040 80a5 bne.w 80094fa <__udivmoddi4+0x236> + 80093b0: 1a8a subs r2, r1, r2 + 80093b2: 2101 movs r1, #1 + 80093b4: 0c03 lsrs r3, r0, #16 + 80093b6: ea4f 4e17 mov.w lr, r7, lsr #16 + 80093ba: b280 uxth r0, r0 + 80093bc: b2bc uxth r4, r7 + 80093be: fbb2 fcfe udiv ip, r2, lr + 80093c2: fb0e 221c mls r2, lr, ip, r2 + 80093c6: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80093ca: fb04 f20c mul.w r2, r4, ip + 80093ce: 429a cmp r2, r3 + 80093d0: d907 bls.n 80093e2 <__udivmoddi4+0x11e> + 80093d2: 18fb adds r3, r7, r3 + 80093d4: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80093d8: d202 bcs.n 80093e0 <__udivmoddi4+0x11c> + 80093da: 429a cmp r2, r3 + 80093dc: f200 80e3 bhi.w 80095a6 <__udivmoddi4+0x2e2> + 80093e0: 46c4 mov ip, r8 + 80093e2: 1a9b subs r3, r3, r2 + 80093e4: fbb3 f2fe udiv r2, r3, lr + 80093e8: fb0e 3312 mls r3, lr, r2, r3 + 80093ec: fb02 f404 mul.w r4, r2, r4 + 80093f0: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80093f4: 429c cmp r4, r3 + 80093f6: d907 bls.n 8009408 <__udivmoddi4+0x144> + 80093f8: 18fb adds r3, r7, r3 + 80093fa: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80093fe: d202 bcs.n 8009406 <__udivmoddi4+0x142> + 8009400: 429c cmp r4, r3 + 8009402: f200 80cd bhi.w 80095a0 <__udivmoddi4+0x2dc> + 8009406: 4602 mov r2, r0 + 8009408: 1b1b subs r3, r3, r4 + 800940a: ea42 400c orr.w r0, r2, ip, lsl #16 + 800940e: e7a5 b.n 800935c <__udivmoddi4+0x98> + 8009410: f1c1 0620 rsb r6, r1, #32 + 8009414: 408b lsls r3, r1 + 8009416: fa22 f706 lsr.w r7, r2, r6 + 800941a: 431f orrs r7, r3 + 800941c: fa2e fa06 lsr.w sl, lr, r6 + 8009420: ea4f 4917 mov.w r9, r7, lsr #16 + 8009424: fbba f8f9 udiv r8, sl, r9 + 8009428: fa0e fe01 lsl.w lr, lr, r1 + 800942c: fa20 f306 lsr.w r3, r0, r6 + 8009430: fb09 aa18 mls sl, r9, r8, sl + 8009434: fa1f fc87 uxth.w ip, r7 + 8009438: ea43 030e orr.w r3, r3, lr + 800943c: fa00 fe01 lsl.w lr, r0, r1 + 8009440: fb08 f00c mul.w r0, r8, ip + 8009444: 0c1c lsrs r4, r3, #16 + 8009446: ea44 440a orr.w r4, r4, sl, lsl #16 + 800944a: 42a0 cmp r0, r4 + 800944c: fa02 f201 lsl.w r2, r2, r1 + 8009450: d90a bls.n 8009468 <__udivmoddi4+0x1a4> + 8009452: 193c adds r4, r7, r4 + 8009454: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8009458: f080 809e bcs.w 8009598 <__udivmoddi4+0x2d4> + 800945c: 42a0 cmp r0, r4 + 800945e: f240 809b bls.w 8009598 <__udivmoddi4+0x2d4> + 8009462: f1a8 0802 sub.w r8, r8, #2 + 8009466: 443c add r4, r7 + 8009468: 1a24 subs r4, r4, r0 + 800946a: b298 uxth r0, r3 + 800946c: fbb4 f3f9 udiv r3, r4, r9 + 8009470: fb09 4413 mls r4, r9, r3, r4 + 8009474: fb03 fc0c mul.w ip, r3, ip + 8009478: ea40 4404 orr.w r4, r0, r4, lsl #16 + 800947c: 45a4 cmp ip, r4 + 800947e: d909 bls.n 8009494 <__udivmoddi4+0x1d0> + 8009480: 193c adds r4, r7, r4 + 8009482: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 8009486: f080 8085 bcs.w 8009594 <__udivmoddi4+0x2d0> + 800948a: 45a4 cmp ip, r4 + 800948c: f240 8082 bls.w 8009594 <__udivmoddi4+0x2d0> + 8009490: 3b02 subs r3, #2 + 8009492: 443c add r4, r7 + 8009494: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8009498: eba4 040c sub.w r4, r4, ip + 800949c: fba0 8c02 umull r8, ip, r0, r2 + 80094a0: 4564 cmp r4, ip + 80094a2: 4643 mov r3, r8 + 80094a4: 46e1 mov r9, ip + 80094a6: d364 bcc.n 8009572 <__udivmoddi4+0x2ae> + 80094a8: d061 beq.n 800956e <__udivmoddi4+0x2aa> + 80094aa: b15d cbz r5, 80094c4 <__udivmoddi4+0x200> + 80094ac: ebbe 0203 subs.w r2, lr, r3 + 80094b0: eb64 0409 sbc.w r4, r4, r9 + 80094b4: fa04 f606 lsl.w r6, r4, r6 + 80094b8: fa22 f301 lsr.w r3, r2, r1 + 80094bc: 431e orrs r6, r3 + 80094be: 40cc lsrs r4, r1 + 80094c0: e9c5 6400 strd r6, r4, [r5] + 80094c4: 2100 movs r1, #0 + 80094c6: e74e b.n 8009366 <__udivmoddi4+0xa2> + 80094c8: fbb1 fcf2 udiv ip, r1, r2 + 80094cc: 0c01 lsrs r1, r0, #16 + 80094ce: ea41 410e orr.w r1, r1, lr, lsl #16 + 80094d2: b280 uxth r0, r0 + 80094d4: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80094d8: 463b mov r3, r7 + 80094da: fbb1 f1f7 udiv r1, r1, r7 + 80094de: 4638 mov r0, r7 + 80094e0: 463c mov r4, r7 + 80094e2: 46b8 mov r8, r7 + 80094e4: 46be mov lr, r7 + 80094e6: 2620 movs r6, #32 + 80094e8: eba2 0208 sub.w r2, r2, r8 + 80094ec: ea41 410c orr.w r1, r1, ip, lsl #16 + 80094f0: e765 b.n 80093be <__udivmoddi4+0xfa> + 80094f2: 4601 mov r1, r0 + 80094f4: e717 b.n 8009326 <__udivmoddi4+0x62> + 80094f6: 4610 mov r0, r2 + 80094f8: e72b b.n 8009352 <__udivmoddi4+0x8e> + 80094fa: f1c6 0120 rsb r1, r6, #32 + 80094fe: fa2e fc01 lsr.w ip, lr, r1 + 8009502: 40b7 lsls r7, r6 + 8009504: fa0e fe06 lsl.w lr, lr, r6 + 8009508: fa20 f101 lsr.w r1, r0, r1 + 800950c: ea41 010e orr.w r1, r1, lr + 8009510: ea4f 4e17 mov.w lr, r7, lsr #16 + 8009514: fbbc f8fe udiv r8, ip, lr + 8009518: b2bc uxth r4, r7 + 800951a: fb0e cc18 mls ip, lr, r8, ip + 800951e: fb08 f904 mul.w r9, r8, r4 + 8009522: 0c0a lsrs r2, r1, #16 + 8009524: ea42 420c orr.w r2, r2, ip, lsl #16 + 8009528: 40b0 lsls r0, r6 + 800952a: 4591 cmp r9, r2 + 800952c: ea4f 4310 mov.w r3, r0, lsr #16 + 8009530: b280 uxth r0, r0 + 8009532: d93e bls.n 80095b2 <__udivmoddi4+0x2ee> + 8009534: 18ba adds r2, r7, r2 + 8009536: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 800953a: d201 bcs.n 8009540 <__udivmoddi4+0x27c> + 800953c: 4591 cmp r9, r2 + 800953e: d81f bhi.n 8009580 <__udivmoddi4+0x2bc> + 8009540: eba2 0209 sub.w r2, r2, r9 + 8009544: fbb2 f9fe udiv r9, r2, lr + 8009548: fb09 f804 mul.w r8, r9, r4 + 800954c: fb0e 2a19 mls sl, lr, r9, r2 + 8009550: b28a uxth r2, r1 + 8009552: ea42 420a orr.w r2, r2, sl, lsl #16 + 8009556: 4542 cmp r2, r8 + 8009558: d229 bcs.n 80095ae <__udivmoddi4+0x2ea> + 800955a: 18ba adds r2, r7, r2 + 800955c: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8009560: d2c2 bcs.n 80094e8 <__udivmoddi4+0x224> + 8009562: 4542 cmp r2, r8 + 8009564: d2c0 bcs.n 80094e8 <__udivmoddi4+0x224> + 8009566: f1a9 0102 sub.w r1, r9, #2 + 800956a: 443a add r2, r7 + 800956c: e7bc b.n 80094e8 <__udivmoddi4+0x224> + 800956e: 45c6 cmp lr, r8 + 8009570: d29b bcs.n 80094aa <__udivmoddi4+0x1e6> + 8009572: ebb8 0302 subs.w r3, r8, r2 + 8009576: eb6c 0c07 sbc.w ip, ip, r7 + 800957a: 3801 subs r0, #1 + 800957c: 46e1 mov r9, ip + 800957e: e794 b.n 80094aa <__udivmoddi4+0x1e6> + 8009580: eba7 0909 sub.w r9, r7, r9 + 8009584: 444a add r2, r9 + 8009586: fbb2 f9fe udiv r9, r2, lr + 800958a: f1a8 0c02 sub.w ip, r8, #2 + 800958e: fb09 f804 mul.w r8, r9, r4 + 8009592: e7db b.n 800954c <__udivmoddi4+0x288> + 8009594: 4603 mov r3, r0 + 8009596: e77d b.n 8009494 <__udivmoddi4+0x1d0> + 8009598: 46d0 mov r8, sl + 800959a: e765 b.n 8009468 <__udivmoddi4+0x1a4> + 800959c: 4608 mov r0, r1 + 800959e: e6fa b.n 8009396 <__udivmoddi4+0xd2> + 80095a0: 443b add r3, r7 + 80095a2: 3a02 subs r2, #2 + 80095a4: e730 b.n 8009408 <__udivmoddi4+0x144> + 80095a6: f1ac 0c02 sub.w ip, ip, #2 + 80095aa: 443b add r3, r7 + 80095ac: e719 b.n 80093e2 <__udivmoddi4+0x11e> + 80095ae: 4649 mov r1, r9 + 80095b0: e79a b.n 80094e8 <__udivmoddi4+0x224> + 80095b2: eba2 0209 sub.w r2, r2, r9 + 80095b6: fbb2 f9fe udiv r9, r2, lr + 80095ba: 46c4 mov ip, r8 + 80095bc: fb09 f804 mul.w r8, r9, r4 + 80095c0: e7c4 b.n 800954c <__udivmoddi4+0x288> + 80095c2: bf00 nop + +080095c4 <__aeabi_idiv0>: + 80095c4: 4770 bx lr + 80095c6: bf00 nop + +080095c8 : + +ADC_HandleTypeDef hadc1; + +/* ADC1 init function */ +void MX_ADC1_Init(void) +{ + 80095c8: b580 push {r7, lr} + 80095ca: b084 sub sp, #16 + 80095cc: af00 add r7, sp, #0 + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + 80095ce: 1d3b adds r3, r7, #4 + 80095d0: 2200 movs r2, #0 + 80095d2: 601a str r2, [r3, #0] + 80095d4: 605a str r2, [r3, #4] + 80095d6: 609a str r2, [r3, #8] + + /* USER CODE END ADC1_Init 1 */ + + /** Common config + */ + hadc1.Instance = ADC1; + 80095d8: 4b18 ldr r3, [pc, #96] @ (800963c ) + 80095da: 4a19 ldr r2, [pc, #100] @ (8009640 ) + 80095dc: 601a str r2, [r3, #0] + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + 80095de: 4b17 ldr r3, [pc, #92] @ (800963c ) + 80095e0: 2200 movs r2, #0 + 80095e2: 609a str r2, [r3, #8] + hadc1.Init.ContinuousConvMode = DISABLE; + 80095e4: 4b15 ldr r3, [pc, #84] @ (800963c ) + 80095e6: 2200 movs r2, #0 + 80095e8: 731a strb r2, [r3, #12] + hadc1.Init.DiscontinuousConvMode = DISABLE; + 80095ea: 4b14 ldr r3, [pc, #80] @ (800963c ) + 80095ec: 2200 movs r2, #0 + 80095ee: 751a strb r2, [r3, #20] + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 80095f0: 4b12 ldr r3, [pc, #72] @ (800963c ) + 80095f2: f44f 2260 mov.w r2, #917504 @ 0xe0000 + 80095f6: 61da str r2, [r3, #28] + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 80095f8: 4b10 ldr r3, [pc, #64] @ (800963c ) + 80095fa: 2200 movs r2, #0 + 80095fc: 605a str r2, [r3, #4] + hadc1.Init.NbrOfConversion = 1; + 80095fe: 4b0f ldr r3, [pc, #60] @ (800963c ) + 8009600: 2201 movs r2, #1 + 8009602: 611a str r2, [r3, #16] + if (HAL_ADC_Init(&hadc1) != HAL_OK) + 8009604: 480d ldr r0, [pc, #52] @ (800963c ) + 8009606: f005 f911 bl 800e82c + 800960a: 4603 mov r3, r0 + 800960c: 2b00 cmp r3, #0 + 800960e: d001 beq.n 8009614 + { + Error_Handler(); + 8009610: f002 fe6a bl 800c2e8 + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_8; + 8009614: 2308 movs r3, #8 + 8009616: 607b str r3, [r7, #4] + sConfig.Rank = ADC_REGULAR_RANK_1; + 8009618: 2301 movs r3, #1 + 800961a: 60bb str r3, [r7, #8] + sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; + 800961c: 2300 movs r3, #0 + 800961e: 60fb str r3, [r7, #12] + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 8009620: 1d3b adds r3, r7, #4 + 8009622: 4619 mov r1, r3 + 8009624: 4805 ldr r0, [pc, #20] @ (800963c ) + 8009626: f005 fbc5 bl 800edb4 + 800962a: 4603 mov r3, r0 + 800962c: 2b00 cmp r3, #0 + 800962e: d001 beq.n 8009634 + { + Error_Handler(); + 8009630: f002 fe5a bl 800c2e8 + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + 8009634: bf00 nop + 8009636: 3710 adds r7, #16 + 8009638: 46bd mov sp, r7 + 800963a: bd80 pop {r7, pc} + 800963c: 2000025c .word 0x2000025c + 8009640: 40012400 .word 0x40012400 + +08009644 : + +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + 8009644: b580 push {r7, lr} + 8009646: b08a sub sp, #40 @ 0x28 + 8009648: af00 add r7, sp, #0 + 800964a: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800964c: f107 0318 add.w r3, r7, #24 + 8009650: 2200 movs r2, #0 + 8009652: 601a str r2, [r3, #0] + 8009654: 605a str r2, [r3, #4] + 8009656: 609a str r2, [r3, #8] + 8009658: 60da str r2, [r3, #12] + if(adcHandle->Instance==ADC1) + 800965a: 687b ldr r3, [r7, #4] + 800965c: 681b ldr r3, [r3, #0] + 800965e: 4a1f ldr r2, [pc, #124] @ (80096dc ) + 8009660: 4293 cmp r3, r2 + 8009662: d137 bne.n 80096d4 + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* ADC1 clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + 8009664: 4b1e ldr r3, [pc, #120] @ (80096e0 ) + 8009666: 699b ldr r3, [r3, #24] + 8009668: 4a1d ldr r2, [pc, #116] @ (80096e0 ) + 800966a: f443 7300 orr.w r3, r3, #512 @ 0x200 + 800966e: 6193 str r3, [r2, #24] + 8009670: 4b1b ldr r3, [pc, #108] @ (80096e0 ) + 8009672: 699b ldr r3, [r3, #24] + 8009674: f403 7300 and.w r3, r3, #512 @ 0x200 + 8009678: 617b str r3, [r7, #20] + 800967a: 697b ldr r3, [r7, #20] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800967c: 4b18 ldr r3, [pc, #96] @ (80096e0 ) + 800967e: 699b ldr r3, [r3, #24] + 8009680: 4a17 ldr r2, [pc, #92] @ (80096e0 ) + 8009682: f043 0304 orr.w r3, r3, #4 + 8009686: 6193 str r3, [r2, #24] + 8009688: 4b15 ldr r3, [pc, #84] @ (80096e0 ) + 800968a: 699b ldr r3, [r3, #24] + 800968c: f003 0304 and.w r3, r3, #4 + 8009690: 613b str r3, [r7, #16] + 8009692: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8009694: 4b12 ldr r3, [pc, #72] @ (80096e0 ) + 8009696: 699b ldr r3, [r3, #24] + 8009698: 4a11 ldr r2, [pc, #68] @ (80096e0 ) + 800969a: f043 0308 orr.w r3, r3, #8 + 800969e: 6193 str r3, [r2, #24] + 80096a0: 4b0f ldr r3, [pc, #60] @ (80096e0 ) + 80096a2: 699b ldr r3, [r3, #24] + 80096a4: f003 0308 and.w r3, r3, #8 + 80096a8: 60fb str r3, [r7, #12] + 80096aa: 68fb ldr r3, [r7, #12] + /**ADC1 GPIO Configuration + PA3 ------> ADC1_IN3 + PB0 ------> ADC1_IN8 + PB1 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + 80096ac: 2308 movs r3, #8 + 80096ae: 61bb str r3, [r7, #24] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80096b0: 2303 movs r3, #3 + 80096b2: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80096b4: f107 0318 add.w r3, r7, #24 + 80096b8: 4619 mov r1, r3 + 80096ba: 480a ldr r0, [pc, #40] @ (80096e4 ) + 80096bc: f006 fef4 bl 80104a8 + + GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; + 80096c0: 2303 movs r3, #3 + 80096c2: 61bb str r3, [r7, #24] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80096c4: 2303 movs r3, #3 + 80096c6: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80096c8: f107 0318 add.w r3, r7, #24 + 80096cc: 4619 mov r1, r3 + 80096ce: 4806 ldr r0, [pc, #24] @ (80096e8 ) + 80096d0: f006 feea bl 80104a8 + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } +} + 80096d4: bf00 nop + 80096d6: 3728 adds r7, #40 @ 0x28 + 80096d8: 46bd mov sp, r7 + 80096da: bd80 pop {r7, pc} + 80096dc: 40012400 .word 0x40012400 + 80096e0: 40021000 .word 0x40021000 + 80096e4: 40010800 .word 0x40010800 + 80096e8: 40010c00 .word 0x40010c00 + +080096ec : + +InfoBlock_t *InfoBlock = (InfoBlock_t *)(VERSION_OFFSET); + +uint8_t RELAY_State[RELAY_COUNT]; + +void RELAY_Write(relay_t num, uint8_t state){ + 80096ec: b580 push {r7, lr} + 80096ee: b082 sub sp, #8 + 80096f0: af00 add r7, sp, #0 + 80096f2: 4603 mov r3, r0 + 80096f4: 460a mov r2, r1 + 80096f6: 71fb strb r3, [r7, #7] + 80096f8: 4613 mov r3, r2 + 80096fa: 71bb strb r3, [r7, #6] + switch (num) { + 80096fc: 79fb ldrb r3, [r7, #7] + 80096fe: 2b06 cmp r3, #6 + 8009700: d847 bhi.n 8009792 + 8009702: a201 add r2, pc, #4 @ (adr r2, 8009708 ) + 8009704: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009708: 08009725 .word 0x08009725 + 800970c: 08009735 .word 0x08009735 + 8009710: 08009745 .word 0x08009745 + 8009714: 08009755 .word 0x08009755 + 8009718: 08009765 .word 0x08009765 + 800971c: 08009775 .word 0x08009775 + 8009720: 08009785 .word 0x08009785 + case RELAY_AUX0: + HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); + 8009724: 79bb ldrb r3, [r7, #6] + 8009726: 461a mov r2, r3 + 8009728: f44f 7180 mov.w r1, #256 @ 0x100 + 800972c: 481d ldr r0, [pc, #116] @ (80097a4 ) + 800972e: f007 f856 bl 80107de + break; + 8009732: e02f b.n 8009794 + case RELAY_AUX1: + HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); + 8009734: 79bb ldrb r3, [r7, #6] + 8009736: 461a mov r2, r3 + 8009738: f44f 7100 mov.w r1, #512 @ 0x200 + 800973c: 4819 ldr r0, [pc, #100] @ (80097a4 ) + 800973e: f007 f84e bl 80107de + break; + 8009742: e027 b.n 8009794 + case RELAY3: + HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); + 8009744: 79bb ldrb r3, [r7, #6] + 8009746: 461a mov r2, r3 + 8009748: f44f 6180 mov.w r1, #1024 @ 0x400 + 800974c: 4815 ldr r0, [pc, #84] @ (80097a4 ) + 800974e: f007 f846 bl 80107de + break; + 8009752: e01f b.n 8009794 + case RELAY_DC: + HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); + 8009754: 79bb ldrb r3, [r7, #6] + 8009756: 461a mov r2, r3 + 8009758: f44f 6100 mov.w r1, #2048 @ 0x800 + 800975c: 4811 ldr r0, [pc, #68] @ (80097a4 ) + 800975e: f007 f83e bl 80107de + break; + 8009762: e017 b.n 8009794 + case RELAY_AC: + HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); + 8009764: 79bb ldrb r3, [r7, #6] + 8009766: 461a mov r2, r3 + 8009768: f44f 5180 mov.w r1, #4096 @ 0x1000 + 800976c: 480d ldr r0, [pc, #52] @ (80097a4 ) + 800976e: f007 f836 bl 80107de + break; + 8009772: e00f b.n 8009794 + case RELAY_CC: + HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); + 8009774: 79bb ldrb r3, [r7, #6] + 8009776: 461a mov r2, r3 + 8009778: f44f 4100 mov.w r1, #32768 @ 0x8000 + 800977c: 480a ldr r0, [pc, #40] @ (80097a8 ) + 800977e: f007 f82e bl 80107de + break; + 8009782: e007 b.n 8009794 + case RELAY_DC1: + HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); + 8009784: 79bb ldrb r3, [r7, #6] + 8009786: 461a mov r2, r3 + 8009788: 2108 movs r1, #8 + 800978a: 4808 ldr r0, [pc, #32] @ (80097ac ) + 800978c: f007 f827 bl 80107de + break; + 8009790: e000 b.n 8009794 + default: + break; + 8009792: bf00 nop + } + + RELAY_State[num] = state; + 8009794: 79fb ldrb r3, [r7, #7] + 8009796: 4906 ldr r1, [pc, #24] @ (80097b0 ) + 8009798: 79ba ldrb r2, [r7, #6] + 800979a: 54ca strb r2, [r1, r3] +} + 800979c: bf00 nop + 800979e: 3708 adds r7, #8 + 80097a0: 46bd mov sp, r7 + 80097a2: bd80 pop {r7, pc} + 80097a4: 40011800 .word 0x40011800 + 80097a8: 40010800 .word 0x40010800 + 80097ac: 40011400 .word 0x40011400 + 80097b0: 2000028c .word 0x2000028c + +080097b4 : + +uint8_t RELAY_Read(relay_t num){ + 80097b4: b480 push {r7} + 80097b6: b083 sub sp, #12 + 80097b8: af00 add r7, sp, #0 + 80097ba: 4603 mov r3, r0 + 80097bc: 71fb strb r3, [r7, #7] + return RELAY_State[num]; + 80097be: 79fb ldrb r3, [r7, #7] + 80097c0: 4a03 ldr r2, [pc, #12] @ (80097d0 ) + 80097c2: 5cd3 ldrb r3, [r2, r3] +} + 80097c4: 4618 mov r0, r3 + 80097c6: 370c adds r7, #12 + 80097c8: 46bd mov sp, r7 + 80097ca: bc80 pop {r7} + 80097cc: 4770 bx lr + 80097ce: bf00 nop + 80097d0: 2000028c .word 0x2000028c + +080097d4 : + + +uint8_t IN_ReadInput(inputNum_t input_n){ + 80097d4: b580 push {r7, lr} + 80097d6: b082 sub sp, #8 + 80097d8: af00 add r7, sp, #0 + 80097da: 4603 mov r3, r0 + 80097dc: 71fb strb r3, [r7, #7] + switch(input_n){ + 80097de: 79fb ldrb r3, [r7, #7] + 80097e0: 2b06 cmp r3, #6 + 80097e2: d83b bhi.n 800985c + 80097e4: a201 add r2, pc, #4 @ (adr r2, 80097ec ) + 80097e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80097ea: bf00 nop + 80097ec: 08009809 .word 0x08009809 + 80097f0: 08009815 .word 0x08009815 + 80097f4: 08009821 .word 0x08009821 + 80097f8: 0800982d .word 0x0800982d + 80097fc: 08009839 .word 0x08009839 + 8009800: 08009845 .word 0x08009845 + 8009804: 08009851 .word 0x08009851 + case IN_SW0: + return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); + 8009808: 2102 movs r1, #2 + 800980a: 4817 ldr r0, [pc, #92] @ (8009868 ) + 800980c: f006 ffd0 bl 80107b0 + 8009810: 4603 mov r3, r0 + 8009812: e024 b.n 800985e + case IN_SW1: + return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); + 8009814: 2104 movs r1, #4 + 8009816: 4814 ldr r0, [pc, #80] @ (8009868 ) + 8009818: f006 ffca bl 80107b0 + 800981c: 4603 mov r3, r0 + 800981e: e01e b.n 800985e + case IN0: + return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); + 8009820: 2180 movs r1, #128 @ 0x80 + 8009822: 4812 ldr r0, [pc, #72] @ (800986c ) + 8009824: f006 ffc4 bl 80107b0 + 8009828: 4603 mov r3, r0 + 800982a: e018 b.n 800985e + case IN_ESTOP: + return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); + 800982c: 2180 movs r1, #128 @ 0x80 + 800982e: 4810 ldr r0, [pc, #64] @ (8009870 ) + 8009830: f006 ffbe bl 80107b0 + 8009834: 4603 mov r3, r0 + 8009836: e012 b.n 800985e + case IN_FB1: + return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); + 8009838: 2110 movs r1, #16 + 800983a: 480e ldr r0, [pc, #56] @ (8009874 ) + 800983c: f006 ffb8 bl 80107b0 + 8009840: 4603 mov r3, r0 + 8009842: e00c b.n 800985e + case IN_CONT_FB_DC: + return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); + 8009844: 2108 movs r1, #8 + 8009846: 480b ldr r0, [pc, #44] @ (8009874 ) + 8009848: f006 ffb2 bl 80107b0 + 800984c: 4603 mov r3, r0 + 800984e: e006 b.n 800985e + case ISO_IN: + return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); + 8009850: 2102 movs r1, #2 + 8009852: 4806 ldr r0, [pc, #24] @ (800986c ) + 8009854: f006 ffac bl 80107b0 + 8009858: 4603 mov r3, r0 + 800985a: e000 b.n 800985e + default: + return 0; + 800985c: 2300 movs r3, #0 + } +} + 800985e: 4618 mov r0, r3 + 8009860: 3708 adds r7, #8 + 8009862: 46bd mov sp, r7 + 8009864: bd80 pop {r7, pc} + 8009866: bf00 nop + 8009868: 40010800 .word 0x40010800 + 800986c: 40011800 .word 0x40011800 + 8009870: 40011400 .word 0x40011400 + 8009874: 40010c00 .word 0x40010c00 + +08009878 : +// +// HAL_ADC_Stop(&hadc1); // stop adc + return 0; +} + +void Init_Peripheral(){ + 8009878: b580 push {r7, lr} + 800987a: af00 add r7, sp, #0 + HAL_ADCEx_Calibration_Start(&hadc1); + 800987c: 4810 ldr r0, [pc, #64] @ (80098c0 ) + 800987e: f005 fc2d bl 800f0dc + + RELAY_Write(RELAY_AUX0, 0); + 8009882: 2100 movs r1, #0 + 8009884: 2000 movs r0, #0 + 8009886: f7ff ff31 bl 80096ec + RELAY_Write(RELAY_AUX1, 0); + 800988a: 2100 movs r1, #0 + 800988c: 2001 movs r0, #1 + 800988e: f7ff ff2d bl 80096ec + RELAY_Write(RELAY3, 0); + 8009892: 2100 movs r1, #0 + 8009894: 2002 movs r0, #2 + 8009896: f7ff ff29 bl 80096ec + RELAY_Write(RELAY_DC, 0); + 800989a: 2100 movs r1, #0 + 800989c: 2003 movs r0, #3 + 800989e: f7ff ff25 bl 80096ec + RELAY_Write(RELAY_AC, 0); + 80098a2: 2100 movs r1, #0 + 80098a4: 2004 movs r0, #4 + 80098a6: f7ff ff21 bl 80096ec + RELAY_Write(RELAY_CC, 1); + 80098aa: 2101 movs r1, #1 + 80098ac: 2005 movs r0, #5 + 80098ae: f7ff ff1d bl 80096ec + RELAY_Write(RELAY_DC1, 0); + 80098b2: 2100 movs r1, #0 + 80098b4: 2006 movs r0, #6 + 80098b6: f7ff ff19 bl 80096ec +} + 80098ba: bf00 nop + 80098bc: bd80 pop {r7, pc} + 80098be: bf00 nop + 80098c0: 2000025c .word 0x2000025c + +080098c4 : + +float pt1000_to_temperature(float resistance) { + 80098c4: b590 push {r4, r7, lr} + 80098c6: b087 sub sp, #28 + 80098c8: af00 add r7, sp, #0 + 80098ca: 6078 str r0, [r7, #4] + // Константы для PT1000 + const float R0 = 1000.0; // Сопротивление при 0 °C + 80098cc: 4b0c ldr r3, [pc, #48] @ (8009900 ) + 80098ce: 617b str r3, [r7, #20] + const float C_A = 3.9083E-3f; + 80098d0: 4b0c ldr r3, [pc, #48] @ (8009904 ) + 80098d2: 613b str r3, [r7, #16] + + float temperature = (resistance-R0) / ( R0 * C_A); + 80098d4: 6979 ldr r1, [r7, #20] + 80098d6: 6878 ldr r0, [r7, #4] + 80098d8: f7ff f996 bl 8008c08 <__aeabi_fsub> + 80098dc: 4603 mov r3, r0 + 80098de: 461c mov r4, r3 + 80098e0: 6939 ldr r1, [r7, #16] + 80098e2: 6978 ldr r0, [r7, #20] + 80098e4: f7ff fa9a bl 8008e1c <__aeabi_fmul> + 80098e8: 4603 mov r3, r0 + 80098ea: 4619 mov r1, r3 + 80098ec: 4620 mov r0, r4 + 80098ee: f7ff fb49 bl 8008f84 <__aeabi_fdiv> + 80098f2: 4603 mov r3, r0 + 80098f4: 60fb str r3, [r7, #12] + + return temperature; + 80098f6: 68fb ldr r3, [r7, #12] +} + 80098f8: 4618 mov r0, r3 + 80098fa: 371c adds r7, #28 + 80098fc: 46bd mov sp, r7 + 80098fe: bd90 pop {r4, r7, pc} + 8009900: 447a0000 .word 0x447a0000 + 8009904: 3b801132 .word 0x3b801132 + +08009908 : + + +float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { + 8009908: b5b0 push {r4, r5, r7, lr} + 800990a: b086 sub sp, #24 + 800990c: af00 add r7, sp, #0 + 800990e: 60f8 str r0, [r7, #12] + 8009910: 60b9 str r1, [r7, #8] + 8009912: 607a str r2, [r7, #4] + 8009914: 603b str r3, [r7, #0] + // Преобразуем значение АЦП в выходное напряжение + float Vout = (adc_value / 4095.0) * Vref; + 8009916: 68f8 ldr r0, [r7, #12] + 8009918: f7fe fde0 bl 80084dc <__aeabi_i2d> + 800991c: a31c add r3, pc, #112 @ (adr r3, 8009990 ) + 800991e: e9d3 2300 ldrd r2, r3, [r3] + 8009922: f7fe ff6f bl 8008804 <__aeabi_ddiv> + 8009926: 4602 mov r2, r0 + 8009928: 460b mov r3, r1 + 800992a: 4614 mov r4, r2 + 800992c: 461d mov r5, r3 + 800992e: 68b8 ldr r0, [r7, #8] + 8009930: f7fe fde6 bl 8008500 <__aeabi_f2d> + 8009934: 4602 mov r2, r0 + 8009936: 460b mov r3, r1 + 8009938: 4620 mov r0, r4 + 800993a: 4629 mov r1, r5 + 800993c: f7fe fe38 bl 80085b0 <__aeabi_dmul> + 8009940: 4602 mov r2, r0 + 8009942: 460b mov r3, r1 + 8009944: 4610 mov r0, r2 + 8009946: 4619 mov r1, r3 + 8009948: f7ff f90a bl 8008b60 <__aeabi_d2f> + 800994c: 4603 mov r3, r0 + 800994e: 617b str r3, [r7, #20] + + // Проверяем, чтобы Vout не было равно Vin + if (Vout >= Vin) { + 8009950: 6879 ldr r1, [r7, #4] + 8009952: 6978 ldr r0, [r7, #20] + 8009954: f7ff fc14 bl 8009180 <__aeabi_fcmpge> + 8009958: 4603 mov r3, r0 + 800995a: 2b00 cmp r3, #0 + 800995c: d001 beq.n 8009962 + return -1; // Ошибка: Vout не может быть больше или равно Vin + 800995e: 4b0e ldr r3, [pc, #56] @ (8009998 ) + 8009960: e010 b.n 8009984 + } + + // Вычисляем сопротивление термистора + float R_NTC = R * (Vout / (Vin - Vout)); + 8009962: 6979 ldr r1, [r7, #20] + 8009964: 6878 ldr r0, [r7, #4] + 8009966: f7ff f94f bl 8008c08 <__aeabi_fsub> + 800996a: 4603 mov r3, r0 + 800996c: 4619 mov r1, r3 + 800996e: 6978 ldr r0, [r7, #20] + 8009970: f7ff fb08 bl 8008f84 <__aeabi_fdiv> + 8009974: 4603 mov r3, r0 + 8009976: 4619 mov r1, r3 + 8009978: 6838 ldr r0, [r7, #0] + 800997a: f7ff fa4f bl 8008e1c <__aeabi_fmul> + 800997e: 4603 mov r3, r0 + 8009980: 613b str r3, [r7, #16] + + return R_NTC; + 8009982: 693b ldr r3, [r7, #16] +} + 8009984: 4618 mov r0, r3 + 8009986: 3718 adds r7, #24 + 8009988: 46bd mov sp, r7 + 800998a: bdb0 pop {r4, r5, r7, pc} + 800998c: f3af 8000 nop.w + 8009990: 00000000 .word 0x00000000 + 8009994: 40affe00 .word 0x40affe00 + 8009998: bf800000 .word 0xbf800000 + +0800999c : + +int16_t GBT_ReadTemp(uint8_t ch){ + 800999c: b580 push {r7, lr} + 800999e: b088 sub sp, #32 + 80099a0: af00 add r7, sp, #0 + 80099a2: 4603 mov r3, r0 + 80099a4: 71fb strb r3, [r7, #7] + //TODO + if(ch)ADC_Select_Channel(ADC_CHANNEL_8); + 80099a6: 79fb ldrb r3, [r7, #7] + 80099a8: 2b00 cmp r3, #0 + 80099aa: d003 beq.n 80099b4 + 80099ac: 2008 movs r0, #8 + 80099ae: f000 f83b bl 8009a28 + 80099b2: e002 b.n 80099ba + else ADC_Select_Channel(ADC_CHANNEL_9); + 80099b4: 2009 movs r0, #9 + 80099b6: f000 f837 bl 8009a28 + // Начало конверсии + HAL_ADC_Start(&hadc1); + 80099ba: 4817 ldr r0, [pc, #92] @ (8009a18 ) + 80099bc: f005 f80e bl 800e9dc + + + // Ожидание окончания конверсии + HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); + 80099c0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 80099c4: 4814 ldr r0, [pc, #80] @ (8009a18 ) + 80099c6: f005 f8e3 bl 800eb90 + + // Получение значения + uint32_t adcValue = HAL_ADC_GetValue(&hadc1); + 80099ca: 4813 ldr r0, [pc, #76] @ (8009a18 ) + 80099cc: f005 f9e6 bl 800ed9c + 80099d0: 61f8 str r0, [r7, #28] + + // Остановка АЦП (по желанию) + HAL_ADC_Stop(&hadc1); + 80099d2: 4811 ldr r0, [pc, #68] @ (8009a18 ) + 80099d4: f005 f8b0 bl 800eb38 + + if(adcValue>4000) return 20; //Термодатчик не подключен + 80099d8: 69fb ldr r3, [r7, #28] + 80099da: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 + 80099de: d901 bls.n 80099e4 + 80099e0: 2314 movs r3, #20 + 80099e2: e015 b.n 8009a10 + +// int adc_value = 2048; // Пример значения АЦП + float Vref = 3.3; // Напряжение опорное + 80099e4: 4b0d ldr r3, [pc, #52] @ (8009a1c ) + 80099e6: 61bb str r3, [r7, #24] + float Vin = 5.0; // Входное напряжение + 80099e8: 4b0d ldr r3, [pc, #52] @ (8009a20 ) + 80099ea: 617b str r3, [r7, #20] + float R = 1000; // Сопротивление резистора в Омах + 80099ec: 4b0d ldr r3, [pc, #52] @ (8009a24 ) + 80099ee: 613b str r3, [r7, #16] + + float temp = pt1000_to_temperature(calculate_NTC_resistance(adcValue, Vref, Vin, R)); + 80099f0: 69f8 ldr r0, [r7, #28] + 80099f2: 693b ldr r3, [r7, #16] + 80099f4: 697a ldr r2, [r7, #20] + 80099f6: 69b9 ldr r1, [r7, #24] + 80099f8: f7ff ff86 bl 8009908 + 80099fc: 4603 mov r3, r0 + 80099fe: 4618 mov r0, r3 + 8009a00: f7ff ff60 bl 80098c4 + 8009a04: 60f8 str r0, [r7, #12] + + return (int16_t)temp; + 8009a06: 68f8 ldr r0, [r7, #12] + 8009a08: f7ff fbce bl 80091a8 <__aeabi_f2iz> + 8009a0c: 4603 mov r3, r0 + 8009a0e: b21b sxth r3, r3 + +} + 8009a10: 4618 mov r0, r3 + 8009a12: 3720 adds r7, #32 + 8009a14: 46bd mov sp, r7 + 8009a16: bd80 pop {r7, pc} + 8009a18: 2000025c .word 0x2000025c + 8009a1c: 40533333 .word 0x40533333 + 8009a20: 40a00000 .word 0x40a00000 + 8009a24: 447a0000 .word 0x447a0000 + +08009a28 : + +void ADC_Select_Channel(uint32_t ch) { + 8009a28: b580 push {r7, lr} + 8009a2a: b086 sub sp, #24 + 8009a2c: af00 add r7, sp, #0 + 8009a2e: 6078 str r0, [r7, #4] + ADC_ChannelConfTypeDef conf = { + 8009a30: 687b ldr r3, [r7, #4] + 8009a32: 60fb str r3, [r7, #12] + 8009a34: 2301 movs r3, #1 + 8009a36: 613b str r3, [r7, #16] + 8009a38: 2303 movs r3, #3 + 8009a3a: 617b str r3, [r7, #20] + .Channel = ch, + .Rank = 1, + .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, + }; + if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { + 8009a3c: f107 030c add.w r3, r7, #12 + 8009a40: 4619 mov r1, r3 + 8009a42: 4806 ldr r0, [pc, #24] @ (8009a5c ) + 8009a44: f005 f9b6 bl 800edb4 + 8009a48: 4603 mov r3, r0 + 8009a4a: 2b00 cmp r3, #0 + 8009a4c: d001 beq.n 8009a52 + Error_Handler(); + 8009a4e: f002 fc4b bl 800c2e8 + } +} + 8009a52: bf00 nop + 8009a54: 3718 adds r7, #24 + 8009a56: 46bd mov sp, r7 + 8009a58: bd80 pop {r7, pc} + 8009a5a: bf00 nop + 8009a5c: 2000025c .word 0x2000025c + +08009a60 : +CAN_HandleTypeDef hcan1; +CAN_HandleTypeDef hcan2; + +/* CAN1 init function */ +void MX_CAN1_Init(void) +{ + 8009a60: b580 push {r7, lr} + 8009a62: af00 add r7, sp, #0 + /* USER CODE END CAN1_Init 0 */ + + /* USER CODE BEGIN CAN1_Init 1 */ + + /* USER CODE END CAN1_Init 1 */ + hcan1.Instance = CAN1; + 8009a64: 4b17 ldr r3, [pc, #92] @ (8009ac4 ) + 8009a66: 4a18 ldr r2, [pc, #96] @ (8009ac8 ) + 8009a68: 601a str r2, [r3, #0] + hcan1.Init.Prescaler = 8; + 8009a6a: 4b16 ldr r3, [pc, #88] @ (8009ac4 ) + 8009a6c: 2208 movs r2, #8 + 8009a6e: 605a str r2, [r3, #4] + hcan1.Init.Mode = CAN_MODE_NORMAL; + 8009a70: 4b14 ldr r3, [pc, #80] @ (8009ac4 ) + 8009a72: 2200 movs r2, #0 + 8009a74: 609a str r2, [r3, #8] + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + 8009a76: 4b13 ldr r3, [pc, #76] @ (8009ac4 ) + 8009a78: 2200 movs r2, #0 + 8009a7a: 60da str r2, [r3, #12] + hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; + 8009a7c: 4b11 ldr r3, [pc, #68] @ (8009ac4 ) + 8009a7e: f44f 2260 mov.w r2, #917504 @ 0xe0000 + 8009a82: 611a str r2, [r3, #16] + hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; + 8009a84: 4b0f ldr r3, [pc, #60] @ (8009ac4 ) + 8009a86: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8009a8a: 615a str r2, [r3, #20] + hcan1.Init.TimeTriggeredMode = DISABLE; + 8009a8c: 4b0d ldr r3, [pc, #52] @ (8009ac4 ) + 8009a8e: 2200 movs r2, #0 + 8009a90: 761a strb r2, [r3, #24] + hcan1.Init.AutoBusOff = ENABLE; + 8009a92: 4b0c ldr r3, [pc, #48] @ (8009ac4 ) + 8009a94: 2201 movs r2, #1 + 8009a96: 765a strb r2, [r3, #25] + hcan1.Init.AutoWakeUp = ENABLE; + 8009a98: 4b0a ldr r3, [pc, #40] @ (8009ac4 ) + 8009a9a: 2201 movs r2, #1 + 8009a9c: 769a strb r2, [r3, #26] + hcan1.Init.AutoRetransmission = ENABLE; + 8009a9e: 4b09 ldr r3, [pc, #36] @ (8009ac4 ) + 8009aa0: 2201 movs r2, #1 + 8009aa2: 76da strb r2, [r3, #27] + hcan1.Init.ReceiveFifoLocked = DISABLE; + 8009aa4: 4b07 ldr r3, [pc, #28] @ (8009ac4 ) + 8009aa6: 2200 movs r2, #0 + 8009aa8: 771a strb r2, [r3, #28] + hcan1.Init.TransmitFifoPriority = ENABLE; + 8009aaa: 4b06 ldr r3, [pc, #24] @ (8009ac4 ) + 8009aac: 2201 movs r2, #1 + 8009aae: 775a strb r2, [r3, #29] + if (HAL_CAN_Init(&hcan1) != HAL_OK) + 8009ab0: 4804 ldr r0, [pc, #16] @ (8009ac4 ) + 8009ab2: f005 fbc1 bl 800f238 + 8009ab6: 4603 mov r3, r0 + 8009ab8: 2b00 cmp r3, #0 + 8009aba: d001 beq.n 8009ac0 + { + Error_Handler(); + 8009abc: f002 fc14 bl 800c2e8 + } + /* USER CODE BEGIN CAN1_Init 2 */ + + /* USER CODE END CAN1_Init 2 */ + +} + 8009ac0: bf00 nop + 8009ac2: bd80 pop {r7, pc} + 8009ac4: 20000294 .word 0x20000294 + 8009ac8: 40006400 .word 0x40006400 + +08009acc : +/* CAN2 init function */ +void MX_CAN2_Init(void) +{ + 8009acc: b580 push {r7, lr} + 8009ace: af00 add r7, sp, #0 + /* USER CODE END CAN2_Init 0 */ + + /* USER CODE BEGIN CAN2_Init 1 */ + + /* USER CODE END CAN2_Init 1 */ + hcan2.Instance = CAN2; + 8009ad0: 4b17 ldr r3, [pc, #92] @ (8009b30 ) + 8009ad2: 4a18 ldr r2, [pc, #96] @ (8009b34 ) + 8009ad4: 601a str r2, [r3, #0] + hcan2.Init.Prescaler = 16; + 8009ad6: 4b16 ldr r3, [pc, #88] @ (8009b30 ) + 8009ad8: 2210 movs r2, #16 + 8009ada: 605a str r2, [r3, #4] + hcan2.Init.Mode = CAN_MODE_NORMAL; + 8009adc: 4b14 ldr r3, [pc, #80] @ (8009b30 ) + 8009ade: 2200 movs r2, #0 + 8009ae0: 609a str r2, [r3, #8] + hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; + 8009ae2: 4b13 ldr r3, [pc, #76] @ (8009b30 ) + 8009ae4: 2200 movs r2, #0 + 8009ae6: 60da str r2, [r3, #12] + hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; + 8009ae8: 4b11 ldr r3, [pc, #68] @ (8009b30 ) + 8009aea: f44f 2260 mov.w r2, #917504 @ 0xe0000 + 8009aee: 611a str r2, [r3, #16] + hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; + 8009af0: 4b0f ldr r3, [pc, #60] @ (8009b30 ) + 8009af2: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8009af6: 615a str r2, [r3, #20] + hcan2.Init.TimeTriggeredMode = DISABLE; + 8009af8: 4b0d ldr r3, [pc, #52] @ (8009b30 ) + 8009afa: 2200 movs r2, #0 + 8009afc: 761a strb r2, [r3, #24] + hcan2.Init.AutoBusOff = ENABLE; + 8009afe: 4b0c ldr r3, [pc, #48] @ (8009b30 ) + 8009b00: 2201 movs r2, #1 + 8009b02: 765a strb r2, [r3, #25] + hcan2.Init.AutoWakeUp = ENABLE; + 8009b04: 4b0a ldr r3, [pc, #40] @ (8009b30 ) + 8009b06: 2201 movs r2, #1 + 8009b08: 769a strb r2, [r3, #26] + hcan2.Init.AutoRetransmission = ENABLE; + 8009b0a: 4b09 ldr r3, [pc, #36] @ (8009b30 ) + 8009b0c: 2201 movs r2, #1 + 8009b0e: 76da strb r2, [r3, #27] + hcan2.Init.ReceiveFifoLocked = DISABLE; + 8009b10: 4b07 ldr r3, [pc, #28] @ (8009b30 ) + 8009b12: 2200 movs r2, #0 + 8009b14: 771a strb r2, [r3, #28] + hcan2.Init.TransmitFifoPriority = ENABLE; + 8009b16: 4b06 ldr r3, [pc, #24] @ (8009b30 ) + 8009b18: 2201 movs r2, #1 + 8009b1a: 775a strb r2, [r3, #29] + if (HAL_CAN_Init(&hcan2) != HAL_OK) + 8009b1c: 4804 ldr r0, [pc, #16] @ (8009b30 ) + 8009b1e: f005 fb8b bl 800f238 + 8009b22: 4603 mov r3, r0 + 8009b24: 2b00 cmp r3, #0 + 8009b26: d001 beq.n 8009b2c + { + Error_Handler(); + 8009b28: f002 fbde bl 800c2e8 + } + /* USER CODE BEGIN CAN2_Init 2 */ + + /* USER CODE END CAN2_Init 2 */ + +} + 8009b2c: bf00 nop + 8009b2e: bd80 pop {r7, pc} + 8009b30: 200002bc .word 0x200002bc + 8009b34: 40006800 .word 0x40006800 + +08009b38 : + +static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; + +void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) +{ + 8009b38: b580 push {r7, lr} + 8009b3a: b08e sub sp, #56 @ 0x38 + 8009b3c: af00 add r7, sp, #0 + 8009b3e: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8009b40: f107 0320 add.w r3, r7, #32 + 8009b44: 2200 movs r2, #0 + 8009b46: 601a str r2, [r3, #0] + 8009b48: 605a str r2, [r3, #4] + 8009b4a: 609a str r2, [r3, #8] + 8009b4c: 60da str r2, [r3, #12] + if(canHandle->Instance==CAN1) + 8009b4e: 687b ldr r3, [r7, #4] + 8009b50: 681b ldr r3, [r3, #0] + 8009b52: 4a61 ldr r2, [pc, #388] @ (8009cd8 ) + 8009b54: 4293 cmp r3, r2 + 8009b56: d153 bne.n 8009c00 + { + /* USER CODE BEGIN CAN1_MspInit 0 */ + + /* USER CODE END CAN1_MspInit 0 */ + /* CAN1 clock enable */ + HAL_RCC_CAN1_CLK_ENABLED++; + 8009b58: 4b60 ldr r3, [pc, #384] @ (8009cdc ) + 8009b5a: 681b ldr r3, [r3, #0] + 8009b5c: 3301 adds r3, #1 + 8009b5e: 4a5f ldr r2, [pc, #380] @ (8009cdc ) + 8009b60: 6013 str r3, [r2, #0] + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + 8009b62: 4b5e ldr r3, [pc, #376] @ (8009cdc ) + 8009b64: 681b ldr r3, [r3, #0] + 8009b66: 2b01 cmp r3, #1 + 8009b68: d10b bne.n 8009b82 + __HAL_RCC_CAN1_CLK_ENABLE(); + 8009b6a: 4b5d ldr r3, [pc, #372] @ (8009ce0 ) + 8009b6c: 69db ldr r3, [r3, #28] + 8009b6e: 4a5c ldr r2, [pc, #368] @ (8009ce0 ) + 8009b70: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8009b74: 61d3 str r3, [r2, #28] + 8009b76: 4b5a ldr r3, [pc, #360] @ (8009ce0 ) + 8009b78: 69db ldr r3, [r3, #28] + 8009b7a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8009b7e: 61fb str r3, [r7, #28] + 8009b80: 69fb ldr r3, [r7, #28] + } + + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8009b82: 4b57 ldr r3, [pc, #348] @ (8009ce0 ) + 8009b84: 699b ldr r3, [r3, #24] + 8009b86: 4a56 ldr r2, [pc, #344] @ (8009ce0 ) + 8009b88: f043 0320 orr.w r3, r3, #32 + 8009b8c: 6193 str r3, [r2, #24] + 8009b8e: 4b54 ldr r3, [pc, #336] @ (8009ce0 ) + 8009b90: 699b ldr r3, [r3, #24] + 8009b92: f003 0320 and.w r3, r3, #32 + 8009b96: 61bb str r3, [r7, #24] + 8009b98: 69bb ldr r3, [r7, #24] + /**CAN1 GPIO Configuration + PD0 ------> CAN1_RX + PD1 ------> CAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8009b9a: 2301 movs r3, #1 + 8009b9c: 623b str r3, [r7, #32] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8009b9e: 2300 movs r3, #0 + 8009ba0: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8009ba2: 2300 movs r3, #0 + 8009ba4: 62bb str r3, [r7, #40] @ 0x28 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8009ba6: f107 0320 add.w r3, r7, #32 + 8009baa: 4619 mov r1, r3 + 8009bac: 484d ldr r0, [pc, #308] @ (8009ce4 ) + 8009bae: f006 fc7b bl 80104a8 + + GPIO_InitStruct.Pin = GPIO_PIN_1; + 8009bb2: 2302 movs r3, #2 + 8009bb4: 623b str r3, [r7, #32] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8009bb6: 2302 movs r3, #2 + 8009bb8: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8009bba: 2303 movs r3, #3 + 8009bbc: 62fb str r3, [r7, #44] @ 0x2c + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8009bbe: f107 0320 add.w r3, r7, #32 + 8009bc2: 4619 mov r1, r3 + 8009bc4: 4847 ldr r0, [pc, #284] @ (8009ce4 ) + 8009bc6: f006 fc6f bl 80104a8 + + __HAL_AFIO_REMAP_CAN1_3(); + 8009bca: 4b47 ldr r3, [pc, #284] @ (8009ce8 ) + 8009bcc: 685b ldr r3, [r3, #4] + 8009bce: 633b str r3, [r7, #48] @ 0x30 + 8009bd0: 6b3b ldr r3, [r7, #48] @ 0x30 + 8009bd2: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 + 8009bd6: 633b str r3, [r7, #48] @ 0x30 + 8009bd8: 6b3b ldr r3, [r7, #48] @ 0x30 + 8009bda: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 8009bde: 633b str r3, [r7, #48] @ 0x30 + 8009be0: 6b3b ldr r3, [r7, #48] @ 0x30 + 8009be2: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 + 8009be6: 633b str r3, [r7, #48] @ 0x30 + 8009be8: 4a3f ldr r2, [pc, #252] @ (8009ce8 ) + 8009bea: 6b3b ldr r3, [r7, #48] @ 0x30 + 8009bec: 6053 str r3, [r2, #4] + + /* CAN1 interrupt Init */ + HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); + 8009bee: 2200 movs r2, #0 + 8009bf0: 2100 movs r1, #0 + 8009bf2: 2014 movs r0, #20 + 8009bf4: f006 fac3 bl 801017e + HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); + 8009bf8: 2014 movs r0, #20 + 8009bfa: f006 fadc bl 80101b6 + HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); + /* USER CODE BEGIN CAN2_MspInit 1 */ + + /* USER CODE END CAN2_MspInit 1 */ + } +} + 8009bfe: e067 b.n 8009cd0 + else if(canHandle->Instance==CAN2) + 8009c00: 687b ldr r3, [r7, #4] + 8009c02: 681b ldr r3, [r3, #0] + 8009c04: 4a39 ldr r2, [pc, #228] @ (8009cec ) + 8009c06: 4293 cmp r3, r2 + 8009c08: d162 bne.n 8009cd0 + __HAL_RCC_CAN2_CLK_ENABLE(); + 8009c0a: 4b35 ldr r3, [pc, #212] @ (8009ce0 ) + 8009c0c: 69db ldr r3, [r3, #28] + 8009c0e: 4a34 ldr r2, [pc, #208] @ (8009ce0 ) + 8009c10: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 8009c14: 61d3 str r3, [r2, #28] + 8009c16: 4b32 ldr r3, [pc, #200] @ (8009ce0 ) + 8009c18: 69db ldr r3, [r3, #28] + 8009c1a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 8009c1e: 617b str r3, [r7, #20] + 8009c20: 697b ldr r3, [r7, #20] + HAL_RCC_CAN1_CLK_ENABLED++; + 8009c22: 4b2e ldr r3, [pc, #184] @ (8009cdc ) + 8009c24: 681b ldr r3, [r3, #0] + 8009c26: 3301 adds r3, #1 + 8009c28: 4a2c ldr r2, [pc, #176] @ (8009cdc ) + 8009c2a: 6013 str r3, [r2, #0] + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + 8009c2c: 4b2b ldr r3, [pc, #172] @ (8009cdc ) + 8009c2e: 681b ldr r3, [r3, #0] + 8009c30: 2b01 cmp r3, #1 + 8009c32: d10b bne.n 8009c4c + __HAL_RCC_CAN1_CLK_ENABLE(); + 8009c34: 4b2a ldr r3, [pc, #168] @ (8009ce0 ) + 8009c36: 69db ldr r3, [r3, #28] + 8009c38: 4a29 ldr r2, [pc, #164] @ (8009ce0 ) + 8009c3a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8009c3e: 61d3 str r3, [r2, #28] + 8009c40: 4b27 ldr r3, [pc, #156] @ (8009ce0 ) + 8009c42: 69db ldr r3, [r3, #28] + 8009c44: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8009c48: 613b str r3, [r7, #16] + 8009c4a: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8009c4c: 4b24 ldr r3, [pc, #144] @ (8009ce0 ) + 8009c4e: 699b ldr r3, [r3, #24] + 8009c50: 4a23 ldr r2, [pc, #140] @ (8009ce0 ) + 8009c52: f043 0308 orr.w r3, r3, #8 + 8009c56: 6193 str r3, [r2, #24] + 8009c58: 4b21 ldr r3, [pc, #132] @ (8009ce0 ) + 8009c5a: 699b ldr r3, [r3, #24] + 8009c5c: f003 0308 and.w r3, r3, #8 + 8009c60: 60fb str r3, [r7, #12] + 8009c62: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_5; + 8009c64: 2320 movs r3, #32 + 8009c66: 623b str r3, [r7, #32] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8009c68: 2300 movs r3, #0 + 8009c6a: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8009c6c: 2300 movs r3, #0 + 8009c6e: 62bb str r3, [r7, #40] @ 0x28 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8009c70: f107 0320 add.w r3, r7, #32 + 8009c74: 4619 mov r1, r3 + 8009c76: 481e ldr r0, [pc, #120] @ (8009cf0 ) + 8009c78: f006 fc16 bl 80104a8 + GPIO_InitStruct.Pin = GPIO_PIN_6; + 8009c7c: 2340 movs r3, #64 @ 0x40 + 8009c7e: 623b str r3, [r7, #32] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8009c80: 2302 movs r3, #2 + 8009c82: 627b str r3, [r7, #36] @ 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8009c84: 2303 movs r3, #3 + 8009c86: 62fb str r3, [r7, #44] @ 0x2c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8009c88: f107 0320 add.w r3, r7, #32 + 8009c8c: 4619 mov r1, r3 + 8009c8e: 4818 ldr r0, [pc, #96] @ (8009cf0 ) + 8009c90: f006 fc0a bl 80104a8 + __HAL_AFIO_REMAP_CAN2_ENABLE(); + 8009c94: 4b14 ldr r3, [pc, #80] @ (8009ce8 ) + 8009c96: 685b ldr r3, [r3, #4] + 8009c98: 637b str r3, [r7, #52] @ 0x34 + 8009c9a: 6b7b ldr r3, [r7, #52] @ 0x34 + 8009c9c: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 8009ca0: 637b str r3, [r7, #52] @ 0x34 + 8009ca2: 6b7b ldr r3, [r7, #52] @ 0x34 + 8009ca4: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8009ca8: 637b str r3, [r7, #52] @ 0x34 + 8009caa: 4a0f ldr r2, [pc, #60] @ (8009ce8 ) + 8009cac: 6b7b ldr r3, [r7, #52] @ 0x34 + 8009cae: 6053 str r3, [r2, #4] + HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); + 8009cb0: 2200 movs r2, #0 + 8009cb2: 2100 movs r1, #0 + 8009cb4: 203f movs r0, #63 @ 0x3f + 8009cb6: f006 fa62 bl 801017e + HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); + 8009cba: 203f movs r0, #63 @ 0x3f + 8009cbc: f006 fa7b bl 80101b6 + HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); + 8009cc0: 2200 movs r2, #0 + 8009cc2: 2100 movs r1, #0 + 8009cc4: 2041 movs r0, #65 @ 0x41 + 8009cc6: f006 fa5a bl 801017e + HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); + 8009cca: 2041 movs r0, #65 @ 0x41 + 8009ccc: f006 fa73 bl 80101b6 +} + 8009cd0: bf00 nop + 8009cd2: 3738 adds r7, #56 @ 0x38 + 8009cd4: 46bd mov sp, r7 + 8009cd6: bd80 pop {r7, pc} + 8009cd8: 40006400 .word 0x40006400 + 8009cdc: 200002e4 .word 0x200002e4 + 8009ce0: 40021000 .word 0x40021000 + 8009ce4: 40011400 .word 0x40011400 + 8009ce8: 40010000 .word 0x40010000 + 8009cec: 40006800 .word 0x40006800 + 8009cf0: 40010c00 .word 0x40010c00 + +08009cf4 : +#include "lock.h" +#include "psu_control.h" + +ChargingConnector_t CONN; + +void CONN_Init(){ + 8009cf4: b480 push {r7} + 8009cf6: af00 add r7, sp, #0 + + CONN.connControl = CMD_NONE; + 8009cf8: 4b08 ldr r3, [pc, #32] @ (8009d1c ) + 8009cfa: 2200 movs r2, #0 + 8009cfc: 701a strb r2, [r3, #0] + CONN.connState = Unknown; + 8009cfe: 4b07 ldr r3, [pc, #28] @ (8009d1c ) + 8009d00: 2200 movs r2, #0 + 8009d02: 705a strb r2, [r3, #1] + CONN.RequestedVoltage = PSU_MIN_VOLTAGE; + 8009d04: 4b05 ldr r3, [pc, #20] @ (8009d1c ) + 8009d06: 2200 movs r2, #0 + 8009d08: f062 0269 orn r2, r2, #105 @ 0x69 + 8009d0c: 73da strb r2, [r3, #15] + 8009d0e: 2200 movs r2, #0 + 8009d10: 741a strb r2, [r3, #16] + +} + 8009d12: bf00 nop + 8009d14: 46bd mov sp, r7 + 8009d16: bc80 pop {r7} + 8009d18: 4770 bx lr + 8009d1a: bf00 nop + 8009d1c: 200002e8 .word 0x200002e8 + +08009d20 : + +void CONN_Loop(){ + 8009d20: b580 push {r7, lr} + 8009d22: af00 add r7, sp, #0 + static CONN_State_t last_connState = Unknown; + if(last_connState != CONN.connState){ + 8009d24: 4b1e ldr r3, [pc, #120] @ (8009da0 ) + 8009d26: 785a ldrb r2, [r3, #1] + 8009d28: 4b1e ldr r3, [pc, #120] @ (8009da4 ) + 8009d2a: 781b ldrb r3, [r3, #0] + 8009d2c: 429a cmp r2, r3 + 8009d2e: d006 beq.n 8009d3e + last_connState = CONN.connState; + 8009d30: 4b1b ldr r3, [pc, #108] @ (8009da0 ) + 8009d32: 785a ldrb r2, [r3, #1] + 8009d34: 4b1b ldr r3, [pc, #108] @ (8009da4 ) + 8009d36: 701a strb r2, [r3, #0] + CONN.connControl = CMD_NONE; + 8009d38: 4b19 ldr r3, [pc, #100] @ (8009da0 ) + 8009d3a: 2200 movs r2, #0 + 8009d3c: 701a strb r2, [r3, #0] + } + + if(GBT_LockState.error){ + 8009d3e: 4b1a ldr r3, [pc, #104] @ (8009da8 ) + 8009d40: 785b ldrb r3, [r3, #1] + 8009d42: 2b00 cmp r3, #0 + 8009d44: d003 beq.n 8009d4e + CONN.chargingError = CONN_ERR_LOCK; + 8009d46: 4b16 ldr r3, [pc, #88] @ (8009da0 ) + 8009d48: 2204 movs r2, #4 + 8009d4a: 775a strb r2, [r3, #29] + 8009d4c: e016 b.n 8009d7c + } else if(PSU0.cont_fault){ + 8009d4e: 4b17 ldr r3, [pc, #92] @ (8009dac ) + 8009d50: 7b1b ldrb r3, [r3, #12] + 8009d52: 2b00 cmp r3, #0 + 8009d54: d003 beq.n 8009d5e + CONN.chargingError = CONN_ERR_CONTACTOR; + 8009d56: 4b12 ldr r3, [pc, #72] @ (8009da0 ) + 8009d58: 2207 movs r2, #7 + 8009d5a: 775a strb r2, [r3, #29] + 8009d5c: e00e b.n 8009d7c + } else if(PSU0.psu_fault){ + 8009d5e: 4b13 ldr r3, [pc, #76] @ (8009dac ) + 8009d60: 7b5b ldrb r3, [r3, #13] + 8009d62: 2b00 cmp r3, #0 + 8009d64: d003 beq.n 8009d6e + CONN.chargingError = CONN_ERR_PSU_FAULT; + 8009d66: 4b0e ldr r3, [pc, #56] @ (8009da0 ) + 8009d68: 220a movs r2, #10 + 8009d6a: 775a strb r2, [r3, #29] + 8009d6c: e006 b.n 8009d7c + // } else if(!CTRL.ac_ok) { + // CONN.chargingError = CONN_ERR_AC_FAULT; + // } else + }else if (CONN.EvConnected == 0){ + 8009d6e: 4b0c ldr r3, [pc, #48] @ (8009da0 ) + 8009d70: 7f9b ldrb r3, [r3, #30] + 8009d72: 2b00 cmp r3, #0 + 8009d74: d102 bne.n 8009d7c + CONN.chargingError = CONN_NO_ERROR; + 8009d76: 4b0a ldr r3, [pc, #40] @ (8009da0 ) + 8009d78: 2200 movs r2, #0 + 8009d7a: 775a strb r2, [r3, #29] + } + + if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); + 8009d7c: 4b08 ldr r3, [pc, #32] @ (8009da0 ) + 8009d7e: 7f5b ldrb r3, [r3, #29] + 8009d80: 2100 movs r1, #0 + 8009d82: 4618 mov r0, r3 + 8009d84: f002 f95e bl 800c044 + 8009d88: 4603 mov r3, r0 + 8009d8a: 2b00 cmp r3, #0 + 8009d8c: d006 beq.n 8009d9c + 8009d8e: 4b04 ldr r3, [pc, #16] @ (8009da0 ) + 8009d90: 7f5b ldrb r3, [r3, #29] + 8009d92: 461a mov r2, r3 + 8009d94: 2100 movs r1, #0 + 8009d96: 4806 ldr r0, [pc, #24] @ (8009db0 ) + 8009d98: f00a f968 bl 801406c + +} + 8009d9c: bf00 nop + 8009d9e: bd80 pop {r7, pc} + 8009da0: 200002e8 .word 0x200002e8 + 8009da4: 20000307 .word 0x20000307 + 8009da8: 20000008 .word 0x20000008 + 8009dac: 200009fc .word 0x200009fc + 8009db0: 08016470 .word 0x08016470 + +08009db4 : + +GBT_StopSource_t GBT_StopSource; + +extern ConfigBlock_t config; + +void GBT_Init(){ + 8009db4: b580 push {r7, lr} + 8009db6: af00 add r7, sp, #0 + GBT_State = GBT_DISABLED; + 8009db8: 4b0b ldr r3, [pc, #44] @ (8009de8 ) + 8009dba: 2210 movs r2, #16 + 8009dbc: 701a strb r2, [r3, #0] + GBT_Reset(); + 8009dbe: f000 ff1f bl 800ac00 + + GBT_MaxLoad.maxOutputVoltage = PSU_MAX_VOLTAGE*10; // 1000V + 8009dc2: 4b0a ldr r3, [pc, #40] @ (8009dec ) + 8009dc4: f242 7210 movw r2, #10000 @ 0x2710 + 8009dc8: 801a strh r2, [r3, #0] + GBT_MaxLoad.minOutputVoltage = PSU_MIN_VOLTAGE*10; //150V + 8009dca: 4b08 ldr r3, [pc, #32] @ (8009dec ) + 8009dcc: f240 52dc movw r2, #1500 @ 0x5dc + 8009dd0: 805a strh r2, [r3, #2] + GBT_MaxLoad.maxOutputCurrent = 4000 - (PSU_MAX_CURRENT*10); //100A + 8009dd2: 4b06 ldr r3, [pc, #24] @ (8009dec ) + 8009dd4: f640 32b8 movw r2, #3000 @ 0xbb8 + 8009dd8: 809a strh r2, [r3, #4] + GBT_MaxLoad.minOutputCurrent = 4000 - (PSU_MIN_CURRENT*10); //1A + 8009dda: 4b04 ldr r3, [pc, #16] @ (8009dec ) + 8009ddc: f640 7296 movw r2, #3990 @ 0xf96 + 8009de0: 80da strh r2, [r3, #6] + +} + 8009de2: bf00 nop + 8009de4: bd80 pop {r7, pc} + 8009de6: bf00 nop + 8009de8: 20000308 .word 0x20000308 + 8009dec: 20000320 .word 0x20000320 + +08009df0 : + +void GBT_SetConfig(){ + 8009df0: b580 push {r7, lr} + 8009df2: af00 add r7, sp, #0 + set_Time(config.unixTime); + 8009df4: 4b0c ldr r3, [pc, #48] @ (8009e28 ) + 8009df6: f8d3 3007 ldr.w r3, [r3, #7] + 8009dfa: 4618 mov r0, r3 + 8009dfc: f003 ff00 bl 800dc00 + GBT_ChargerInfo.chargerLocation[0] = config.location[0]; + 8009e00: 4b09 ldr r3, [pc, #36] @ (8009e28 ) + 8009e02: 781a ldrb r2, [r3, #0] + 8009e04: 4b09 ldr r3, [pc, #36] @ (8009e2c ) + 8009e06: 715a strb r2, [r3, #5] + GBT_ChargerInfo.chargerLocation[1] = config.location[1]; + 8009e08: 4b07 ldr r3, [pc, #28] @ (8009e28 ) + 8009e0a: 785a ldrb r2, [r3, #1] + 8009e0c: 4b07 ldr r3, [pc, #28] @ (8009e2c ) + 8009e0e: 719a strb r2, [r3, #6] + GBT_ChargerInfo.chargerLocation[2] = config.location[2]; + 8009e10: 4b05 ldr r3, [pc, #20] @ (8009e28 ) + 8009e12: 789a ldrb r2, [r3, #2] + 8009e14: 4b05 ldr r3, [pc, #20] @ (8009e2c ) + 8009e16: 71da strb r2, [r3, #7] + GBT_ChargerInfo.chargerNumber = config.chargerNumber; + 8009e18: 4b03 ldr r3, [pc, #12] @ (8009e28 ) + 8009e1a: f8d3 3003 ldr.w r3, [r3, #3] + 8009e1e: 4a03 ldr r2, [pc, #12] @ (8009e2c ) + 8009e20: f8c2 3001 str.w r3, [r2, #1] +} + 8009e24: bf00 nop + 8009e26: bd80 pop {r7, pc} + 8009e28: 20000060 .word 0x20000060 + 8009e2c: 20000328 .word 0x20000328 + +08009e30 : + + +void GBT_ChargerTask(){ + 8009e30: b5b0 push {r4, r5, r7, lr} + 8009e32: b084 sub sp, #16 + 8009e34: af02 add r7, sp, #8 + + //GBT_LockTask(); + if(j_rx.state == 2){ + 8009e36: 4bab ldr r3, [pc, #684] @ (800a0e4 ) + 8009e38: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 8009e3c: 2b02 cmp r3, #2 + 8009e3e: f040 80d1 bne.w 8009fe4 + switch (j_rx.PGN){ + 8009e42: 4ba8 ldr r3, [pc, #672] @ (800a0e4 ) + 8009e44: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100 + 8009e48: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 + 8009e4c: d047 beq.n 8009ede + 8009e4e: f5b3 5f1c cmp.w r3, #9984 @ 0x2700 + 8009e52: f200 80c3 bhi.w 8009fdc + 8009e56: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 8009e5a: f000 80b6 beq.w 8009fca + 8009e5e: f5b3 5fe0 cmp.w r3, #7168 @ 0x1c00 + 8009e62: f200 80bb bhi.w 8009fdc + 8009e66: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 + 8009e6a: f000 80b2 beq.w 8009fd2 + 8009e6e: f5b3 5fb8 cmp.w r3, #5888 @ 0x1700 + 8009e72: f200 80b3 bhi.w 8009fdc + 8009e76: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 + 8009e7a: f000 80ac beq.w 8009fd6 + 8009e7e: f5b3 5fb0 cmp.w r3, #5632 @ 0x1600 + 8009e82: f200 80ab bhi.w 8009fdc + 8009e86: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 + 8009e8a: f000 80a6 beq.w 8009fda + 8009e8e: f5b3 5fa8 cmp.w r3, #5376 @ 0x1500 + 8009e92: f200 80a3 bhi.w 8009fdc + 8009e96: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 + 8009e9a: f000 8086 beq.w 8009faa + 8009e9e: f5b3 5f98 cmp.w r3, #4864 @ 0x1300 + 8009ea2: f200 809b bhi.w 8009fdc + 8009ea6: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 + 8009eaa: d06f beq.n 8009f8c + 8009eac: f5b3 5f88 cmp.w r3, #4352 @ 0x1100 + 8009eb0: f200 8094 bhi.w 8009fdc + 8009eb4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8009eb8: d046 beq.n 8009f48 + 8009eba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8009ebe: f200 808d bhi.w 8009fdc + 8009ec2: f5b3 6f10 cmp.w r3, #2304 @ 0x900 + 8009ec6: d02c beq.n 8009f22 + 8009ec8: f5b3 6f10 cmp.w r3, #2304 @ 0x900 + 8009ecc: f200 8086 bhi.w 8009fdc + 8009ed0: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8009ed4: d00b beq.n 8009eee + 8009ed6: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 + 8009eda: d018 beq.n 8009f0e + 8009edc: e07e b.n 8009fdc + case 0x2700: //PGN BHM + GBT_BHM_recv = 1; + 8009ede: 4b82 ldr r3, [pc, #520] @ (800a0e8 ) + 8009ee0: 2201 movs r2, #1 + 8009ee2: 701a strb r2, [r3, #0] + memcpy (&GBT_MaxVoltage, j_rx.data, sizeof(GBT_MaxVoltage)); + 8009ee4: 4b7f ldr r3, [pc, #508] @ (800a0e4 ) + 8009ee6: 881a ldrh r2, [r3, #0] + 8009ee8: 4b80 ldr r3, [pc, #512] @ (800a0ec ) + 8009eea: 801a strh r2, [r3, #0] + + break; + 8009eec: e076 b.n 8009fdc + + case 0x0200: //PGN BRM LONG + GBT_BAT_INFO_recv = 1; + 8009eee: 4b80 ldr r3, [pc, #512] @ (800a0f0 ) + 8009ef0: 2201 movs r2, #1 + 8009ef2: 701a strb r2, [r3, #0] + memcpy (&GBT_EVInfo, j_rx.data, sizeof(GBT_EVInfo)); + 8009ef4: 4a7f ldr r2, [pc, #508] @ (800a0f4 ) + 8009ef6: 4b7b ldr r3, [pc, #492] @ (800a0e4 ) + 8009ef8: 4614 mov r4, r2 + 8009efa: 461d mov r5, r3 + 8009efc: cd0f ldmia r5!, {r0, r1, r2, r3} + 8009efe: c40f stmia r4!, {r0, r1, r2, r3} + 8009f00: cd0f ldmia r5!, {r0, r1, r2, r3} + 8009f02: c40f stmia r4!, {r0, r1, r2, r3} + 8009f04: cd0f ldmia r5!, {r0, r1, r2, r3} + 8009f06: c40f stmia r4!, {r0, r1, r2, r3} + 8009f08: 682b ldr r3, [r5, #0] + 8009f0a: 7023 strb r3, [r4, #0] + + break; + 8009f0c: e066 b.n 8009fdc + + case 0x0600: //PGN BCP LONG + GBT_BAT_STAT_recv = 1; + 8009f0e: 4b7a ldr r3, [pc, #488] @ (800a0f8 ) + 8009f10: 2201 movs r2, #1 + 8009f12: 701a strb r2, [r3, #0] + memcpy (&GBT_BATStat, j_rx.data, sizeof(GBT_BATStat)); + 8009f14: 4a79 ldr r2, [pc, #484] @ (800a0fc ) + 8009f16: 4b73 ldr r3, [pc, #460] @ (800a0e4 ) + 8009f18: 4614 mov r4, r2 + 8009f1a: cb0f ldmia r3, {r0, r1, r2, r3} + 8009f1c: c407 stmia r4!, {r0, r1, r2} + 8009f1e: 7023 strb r3, [r4, #0] + break; + 8009f20: e05c b.n 8009fdc + + case 0x0900: //PGN BRO + GBT_BRO_recv = 1; + 8009f22: 4b77 ldr r3, [pc, #476] @ (800a100 ) + 8009f24: 2201 movs r2, #1 + 8009f26: 701a strb r2, [r3, #0] + if(j_rx.data[0] == 0xAA) EV_ready = 1; + 8009f28: 4b6e ldr r3, [pc, #440] @ (800a0e4 ) + 8009f2a: 781b ldrb r3, [r3, #0] + 8009f2c: 2baa cmp r3, #170 @ 0xaa + 8009f2e: d103 bne.n 8009f38 + 8009f30: 4b74 ldr r3, [pc, #464] @ (800a104 ) + 8009f32: 2201 movs r2, #1 + 8009f34: 701a strb r2, [r3, #0] + 8009f36: e002 b.n 8009f3e + else EV_ready = 0; + 8009f38: 4b72 ldr r3, [pc, #456] @ (800a104 ) + 8009f3a: 2200 movs r2, #0 + 8009f3c: 701a strb r2, [r3, #0] + GBT_BRO = j_rx.data[0]; + 8009f3e: 4b69 ldr r3, [pc, #420] @ (800a0e4 ) + 8009f40: 781a ldrb r2, [r3, #0] + 8009f42: 4b71 ldr r3, [pc, #452] @ (800a108 ) + 8009f44: 701a strb r2, [r3, #0] + break; + 8009f46: e049 b.n 8009fdc + + case 0x1000: //PGN BCL + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + 8009f48: f004 fc42 bl 800e7d0 + 8009f4c: 4603 mov r3, r0 + 8009f4e: 4a6f ldr r2, [pc, #444] @ (800a10c ) + 8009f50: 6013 str r3, [r2, #0] + //TODO: power block + memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); + 8009f52: 4b6f ldr r3, [pc, #444] @ (800a110 ) + 8009f54: 4a63 ldr r2, [pc, #396] @ (800a0e4 ) + 8009f56: e892 0003 ldmia.w r2, {r0, r1} + 8009f5a: 6018 str r0, [r3, #0] + 8009f5c: 3304 adds r3, #4 + 8009f5e: 7019 strb r1, [r3, #0] + + uint16_t volt = GBT_ReqPower.requestedVoltage; // 0.1V/bit + 8009f60: 4b6b ldr r3, [pc, #428] @ (800a110 ) + 8009f62: 881b ldrh r3, [r3, #0] + 8009f64: 80fb strh r3, [r7, #6] + uint16_t curr = 4000 - GBT_ReqPower.requestedCurrent; // 0.1A/bit + 8009f66: 4b6a ldr r3, [pc, #424] @ (800a110 ) + 8009f68: 885b ldrh r3, [r3, #2] + 8009f6a: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 + 8009f6e: 80bb strh r3, [r7, #4] + CONN.RequestedVoltage = volt / 10; // В + 8009f70: 88fb ldrh r3, [r7, #6] + 8009f72: 4a68 ldr r2, [pc, #416] @ (800a114 ) + 8009f74: fba2 2303 umull r2, r3, r2, r3 + 8009f78: 08db lsrs r3, r3, #3 + 8009f7a: b29a uxth r2, r3 + 8009f7c: 4b66 ldr r3, [pc, #408] @ (800a118 ) + 8009f7e: f8a3 200f strh.w r2, [r3, #15] + CONN.WantedCurrent = curr; // 0.1A + 8009f82: 4b65 ldr r3, [pc, #404] @ (800a118 ) + 8009f84: 88ba ldrh r2, [r7, #4] + 8009f86: f8a3 201b strh.w r2, [r3, #27] + + break; + 8009f8a: e027 b.n 8009fdc + + case 0x1100: //PGN BCS + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + 8009f8c: f004 fc20 bl 800e7d0 + 8009f90: 4603 mov r3, r0 + 8009f92: 4a5e ldr r2, [pc, #376] @ (800a10c ) + 8009f94: 6013 str r3, [r2, #0] + //TODO + memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); + 8009f96: 4b61 ldr r3, [pc, #388] @ (800a11c ) + 8009f98: 4a52 ldr r2, [pc, #328] @ (800a0e4 ) + 8009f9a: ca07 ldmia r2, {r0, r1, r2} + 8009f9c: c303 stmia r3!, {r0, r1} + 8009f9e: 701a strb r2, [r3, #0] + CONN.SOC = GBT_ChargingStatus.currentChargeState; + 8009fa0: 4b5e ldr r3, [pc, #376] @ (800a11c ) + 8009fa2: 799a ldrb r2, [r3, #6] + 8009fa4: 4b5c ldr r3, [pc, #368] @ (800a118 ) + 8009fa6: 709a strb r2, [r3, #2] + break; + 8009fa8: e018 b.n 8009fdc + + case 0x1300: //PGN BSM + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + 8009faa: f004 fc11 bl 800e7d0 + 8009fae: 4603 mov r3, r0 + 8009fb0: 4a56 ldr r2, [pc, #344] @ (800a10c ) + 8009fb2: 6013 str r3, [r2, #0] + //TODO + memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); + 8009fb4: 4b5a ldr r3, [pc, #360] @ (800a120 ) + 8009fb6: 4a4b ldr r2, [pc, #300] @ (800a0e4 ) + 8009fb8: e892 0003 ldmia.w r2, {r0, r1} + 8009fbc: 6018 str r0, [r3, #0] + 8009fbe: 3304 adds r3, #4 + 8009fc0: 8019 strh r1, [r3, #0] + 8009fc2: 3302 adds r3, #2 + 8009fc4: 0c0a lsrs r2, r1, #16 + 8009fc6: 701a strb r2, [r3, #0] + break; + 8009fc8: e008 b.n 8009fdc +// case 0x1900: //PGN BST +// break; + + case 0x1C00: //PGN BSD + //TODO SOC Voltage Temp + GBT_BSD_recv = 1; + 8009fca: 4b56 ldr r3, [pc, #344] @ (800a124 ) + 8009fcc: 2201 movs r2, #1 + 8009fce: 701a strb r2, [r3, #0] + break; + 8009fd0: e004 b.n 8009fdc + break; + 8009fd2: bf00 nop + 8009fd4: e002 b.n 8009fdc + break; + 8009fd6: bf00 nop + 8009fd8: e000 b.n 8009fdc + break; + 8009fda: bf00 nop +// break; + + //BSM BMV BMT BSP BST BSD BEM + + } + j_rx.state = 0; + 8009fdc: 4b41 ldr r3, [pc, #260] @ (800a0e4 ) + 8009fde: 2200 movs r2, #0 + 8009fe0: f883 210a strb.w r2, [r3, #266] @ 0x10a + } + + if((HAL_GetTick() - GBT_delay_start) < GBT_delay){ + 8009fe4: f004 fbf4 bl 800e7d0 + 8009fe8: 4602 mov r2, r0 + 8009fea: 4b4f ldr r3, [pc, #316] @ (800a128 ) + 8009fec: 681b ldr r3, [r3, #0] + 8009fee: 1ad2 subs r2, r2, r3 + 8009ff0: 4b4e ldr r3, [pc, #312] @ (800a12c ) + 8009ff2: 681b ldr r3, [r3, #0] + 8009ff4: 429a cmp r2, r3 + 8009ff6: f0c0 8474 bcc.w 800a8e2 + //waiting + }else switch (GBT_State){ + 8009ffa: 4b4d ldr r3, [pc, #308] @ (800a130 ) + 8009ffc: 781b ldrb r3, [r3, #0] + 8009ffe: 3b10 subs r3, #16 + 800a000: 2b12 cmp r3, #18 + 800a002: f200 844f bhi.w 800a8a4 + 800a006: a201 add r2, pc, #4 @ (adr r2, 800a00c ) + 800a008: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a00c: 0800a059 .word 0x0800a059 + 800a010: 0800a8a5 .word 0x0800a8a5 + 800a014: 0800a8a5 .word 0x0800a8a5 + 800a018: 0800a07f .word 0x0800a07f + 800a01c: 0800a091 .word 0x0800a091 + 800a020: 0800a141 .word 0x0800a141 + 800a024: 0800a18b .word 0x0800a18b + 800a028: 0800a1fd .word 0x0800a1fd + 800a02c: 0800a239 .word 0x0800a239 + 800a030: 0800a28b .word 0x0800a28b + 800a034: 0800a409 .word 0x0800a409 + 800a038: 0800a50d .word 0x0800a50d + 800a03c: 0800a59f .word 0x0800a59f + 800a040: 0800a5f5 .word 0x0800a5f5 + 800a044: 0800a667 .word 0x0800a667 + 800a048: 0800a81d .word 0x0800a81d + 800a04c: 0800a85f .word 0x0800a85f + 800a050: 0800a87f .word 0x0800a87f + 800a054: 0800a891 .word 0x0800a891 + case GBT_DISABLED: + RELAY_Write(RELAY_AUX0, 0); + 800a058: 2100 movs r1, #0 + 800a05a: 2000 movs r0, #0 + 800a05c: f7ff fb46 bl 80096ec + RELAY_Write(RELAY_AUX1, 0); + 800a060: 2100 movs r1, #0 + 800a062: 2001 movs r0, #1 + 800a064: f7ff fb42 bl 80096ec + if(connectorState == Preparing){ + 800a068: 4b32 ldr r3, [pc, #200] @ (800a134 ) + 800a06a: 781b ldrb r3, [r3, #0] + 800a06c: 2b03 cmp r3, #3 + 800a06e: f040 841d bne.w 800a8ac + GBT_Reset(); + 800a072: f000 fdc5 bl 800ac00 + GBT_Start();//TODO IF protections (maybe not needed) + 800a076: f000 fe51 bl 800ad1c + } + break; + 800a07a: f000 bc17 b.w 800a8ac + + case GBT_S3_STARTED: + GBT_SwitchState(GBT_S31_WAIT_BHM); + 800a07e: 2014 movs r0, #20 + 800a080: f000 fc5c bl 800a93c + GBT_Delay(500); + 800a084: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800a088: f000 fd10 bl 800aaac + break; + 800a08c: f000 bc29 b.w 800a8e2 + + case GBT_S31_WAIT_BHM: + if(j_rx.state == 0) GBT_SendCHM(); + 800a090: 4b14 ldr r3, [pc, #80] @ (800a0e4 ) + 800a092: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a096: 2b00 cmp r3, #0 + 800a098: d101 bne.n 800a09e + 800a09a: f001 fa3d bl 800b518 + GBT_Delay(250); + 800a09e: 20fa movs r0, #250 @ 0xfa + 800a0a0: f000 fd04 bl 800aaac + + if(GBT_BHM_recv) { + 800a0a4: 4b10 ldr r3, [pc, #64] @ (800a0e8 ) + 800a0a6: 781b ldrb r3, [r3, #0] + 800a0a8: 2b00 cmp r3, #0 + 800a0aa: d002 beq.n 800a0b2 + GBT_SwitchState(GBT_S4_WAIT_PSU_READY); + 800a0ac: 2015 movs r0, #21 + 800a0ae: f000 fc45 bl 800a93c + } + + //Timeout 10S + if((GBT_BHM_recv == 0) && (GBT_StateTick()>10000)) { //BHM Timeout + 800a0b2: 4b0d ldr r3, [pc, #52] @ (800a0e8 ) + 800a0b4: 781b ldrb r3, [r3, #0] + 800a0b6: 2b00 cmp r3, #0 + 800a0b8: f040 83fa bne.w 800a8b0 + 800a0bc: f000 fcea bl 800aa94 + 800a0c0: 4603 mov r3, r0 + 800a0c2: f242 7210 movw r2, #10000 @ 0x2710 + 800a0c6: 4293 cmp r3, r2 + 800a0c8: f240 83f2 bls.w 800a8b0 + GBT_Error(0xFCF0C0FC); + 800a0cc: 481a ldr r0, [pc, #104] @ (800a138 ) + 800a0ce: f000 fd7b bl 800abc8 + CONN.chargingError = CONN_ERR_EV_COMM; + 800a0d2: 4b11 ldr r3, [pc, #68] @ (800a118 ) + 800a0d4: 2209 movs r2, #9 + 800a0d6: 775a strb r2, [r3, #29] + log_printf(LOG_ERR, "BHM Timeout\n"); + 800a0d8: 4918 ldr r1, [pc, #96] @ (800a13c ) + 800a0da: 2004 movs r0, #4 + 800a0dc: f001 f9c2 bl 800b464 + } + break; + 800a0e0: e3e6 b.n 800a8b0 + 800a0e2: bf00 nop + 800a0e4: 20000860 .word 0x20000860 + 800a0e8: 2000031b .word 0x2000031b + 800a0ec: 20000330 .word 0x20000330 + 800a0f0: 20000318 .word 0x20000318 + 800a0f4: 20000334 .word 0x20000334 + 800a0f8: 20000319 .word 0x20000319 + 800a0fc: 20000368 .word 0x20000368 + 800a100: 2000031a .word 0x2000031a + 800a104: 2000031d .word 0x2000031d + 800a108: 200003ac .word 0x200003ac + 800a10c: 200003b4 .word 0x200003b4 + 800a110: 20000378 .word 0x20000378 + 800a114: cccccccd .word 0xcccccccd + 800a118: 200002e8 .word 0x200002e8 + 800a11c: 20000388 .word 0x20000388 + 800a120: 20000394 .word 0x20000394 + 800a124: 2000031c .word 0x2000031c + 800a128: 20000310 .word 0x20000310 + 800a12c: 20000314 .word 0x20000314 + 800a130: 20000308 .word 0x20000308 + 800a134: 200003c1 .word 0x200003c1 + 800a138: fcf0c0fc .word 0xfcf0c0fc + 800a13c: 080164b8 .word 0x080164b8 + case GBT_S4_WAIT_PSU_READY: + if(j_rx.state == 0) GBT_SendCHM(); + 800a140: 4b96 ldr r3, [pc, #600] @ (800a39c ) + 800a142: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a146: 2b00 cmp r3, #0 + 800a148: d101 bne.n 800a14e + 800a14a: f001 f9e5 bl 800b518 + GBT_Delay(250); + 800a14e: 20fa movs r0, #250 @ 0xfa + 800a150: f000 fcac bl 800aaac + if(PSU0.ready){ + 800a154: 4b92 ldr r3, [pc, #584] @ (800a3a0 ) + 800a156: 7a5b ldrb r3, [r3, #9] + 800a158: 2b00 cmp r3, #0 + 800a15a: d002 beq.n 800a162 + GBT_SwitchState(GBT_S4_WAIT_PSU_ON); + 800a15c: 2016 movs r0, #22 + 800a15e: f000 fbed bl 800a93c + } + if(GBT_StateTick()>10000){ + 800a162: f000 fc97 bl 800aa94 + 800a166: 4603 mov r3, r0 + 800a168: f242 7210 movw r2, #10000 @ 0x2710 + 800a16c: 4293 cmp r3, r2 + 800a16e: f240 83a1 bls.w 800a8b4 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a172: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a176: f000 fcd3 bl 800ab20 + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800a17a: 4b8a ldr r3, [pc, #552] @ (800a3a4 ) + 800a17c: 220a movs r2, #10 + 800a17e: 775a strb r2, [r3, #29] + log_printf(LOG_ERR, "PSU ready timeout, stopping...\n"); + 800a180: 4989 ldr r1, [pc, #548] @ (800a3a8 ) + 800a182: 2004 movs r0, #4 + 800a184: f001 f96e bl 800b464 + break; + 800a188: e3ab b.n 800a8e2 + } + break; + + case GBT_S4_WAIT_PSU_ON: + if(j_rx.state == 0) GBT_SendCHM(); + 800a18a: 4b84 ldr r3, [pc, #528] @ (800a39c ) + 800a18c: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a190: 2b00 cmp r3, #0 + 800a192: d101 bne.n 800a198 + 800a194: f001 f9c0 bl 800b518 + GBT_Delay(250); + 800a198: 20fa movs r0, #250 @ 0xfa + 800a19a: f000 fc87 bl 800aaac + CONN.RequestedVoltage = GBT_MaxVoltage.maxOutputVoltage / 10; // 0.1V -> V + 800a19e: 4b83 ldr r3, [pc, #524] @ (800a3ac ) + 800a1a0: 881b ldrh r3, [r3, #0] + 800a1a2: 4a83 ldr r2, [pc, #524] @ (800a3b0 ) + 800a1a4: fba2 2303 umull r2, r3, r2, r3 + 800a1a8: 08db lsrs r3, r3, #3 + 800a1aa: b29a uxth r2, r3 + 800a1ac: 4b7d ldr r3, [pc, #500] @ (800a3a4 ) + 800a1ae: f8a3 200f strh.w r2, [r3, #15] + CONN.WantedCurrent = 10; // 1A max (0.1A units) + 800a1b2: 4b7c ldr r3, [pc, #496] @ (800a3a4 ) + 800a1b4: 2200 movs r2, #0 + 800a1b6: f042 020a orr.w r2, r2, #10 + 800a1ba: 76da strb r2, [r3, #27] + 800a1bc: 2200 movs r2, #0 + 800a1be: 771a strb r2, [r3, #28] + CONN.EnableOutput = 1; + 800a1c0: 4b78 ldr r3, [pc, #480] @ (800a3a4 ) + 800a1c2: 2201 movs r2, #1 + 800a1c4: 75da strb r2, [r3, #23] + if(PSU0.state == PSU_CONNECTED){ + 800a1c6: 4b76 ldr r3, [pc, #472] @ (800a3a0 ) + 800a1c8: 79db ldrb r3, [r3, #7] + 800a1ca: 2b05 cmp r3, #5 + 800a1cc: d102 bne.n 800a1d4 + GBT_SwitchState(GBT_S4_ISOTEST); + 800a1ce: 2017 movs r0, #23 + 800a1d0: f000 fbb4 bl 800a93c + } + if(GBT_StateTick()>10000){ + 800a1d4: f000 fc5e bl 800aa94 + 800a1d8: 4603 mov r3, r0 + 800a1da: f242 7210 movw r2, #10000 @ 0x2710 + 800a1de: 4293 cmp r3, r2 + 800a1e0: f240 836a bls.w 800a8b8 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a1e4: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a1e8: f000 fc9a bl 800ab20 + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800a1ec: 4b6d ldr r3, [pc, #436] @ (800a3a4 ) + 800a1ee: 220a movs r2, #10 + 800a1f0: 775a strb r2, [r3, #29] + log_printf(LOG_ERR, "PSU on timeout, stopping...\n"); + 800a1f2: 4970 ldr r1, [pc, #448] @ (800a3b4 ) + 800a1f4: 2004 movs r0, #4 + 800a1f6: f001 f935 bl 800b464 + break; + 800a1fa: e372 b.n 800a8e2 + } + break; + + case GBT_S4_ISOTEST: + if(j_rx.state == 0) GBT_SendCHM(); + 800a1fc: 4b67 ldr r3, [pc, #412] @ (800a39c ) + 800a1fe: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a202: 2b00 cmp r3, #0 + 800a204: d101 bne.n 800a20a + 800a206: f001 f987 bl 800b518 + GBT_Delay(250); + 800a20a: 20fa movs r0, #250 @ 0xfa + 800a20c: f000 fc4e bl 800aaac + //TODO: Isolation test trigger + if(CONN.chargingError != CONN_NO_ERROR){ + 800a210: 4b64 ldr r3, [pc, #400] @ (800a3a4 ) + 800a212: 7f5b ldrb r3, [r3, #29] + 800a214: 2b00 cmp r3, #0 + 800a216: d003 beq.n 800a220 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a218: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a21c: f000 fc80 bl 800ab20 + } + if(GBT_StateTick()>5000){ + 800a220: f000 fc38 bl 800aa94 + 800a224: 4603 mov r3, r0 + 800a226: f241 3288 movw r2, #5000 @ 0x1388 + 800a22a: 4293 cmp r3, r2 + 800a22c: f240 8346 bls.w 800a8bc + GBT_SwitchState(GBT_S4_WAIT_PSU_OFF); + 800a230: 2018 movs r0, #24 + 800a232: f000 fb83 bl 800a93c + } + break; + 800a236: e341 b.n 800a8bc + + case GBT_S4_WAIT_PSU_OFF: + CONN.RequestedVoltage = 0; + 800a238: 4b5a ldr r3, [pc, #360] @ (800a3a4 ) + 800a23a: 2200 movs r2, #0 + 800a23c: 73da strb r2, [r3, #15] + 800a23e: 2200 movs r2, #0 + 800a240: 741a strb r2, [r3, #16] + CONN.WantedCurrent = 0; + 800a242: 4b58 ldr r3, [pc, #352] @ (800a3a4 ) + 800a244: 2200 movs r2, #0 + 800a246: 76da strb r2, [r3, #27] + 800a248: 2200 movs r2, #0 + 800a24a: 771a strb r2, [r3, #28] + CONN.EnableOutput = 0; + 800a24c: 4b55 ldr r3, [pc, #340] @ (800a3a4 ) + 800a24e: 2200 movs r2, #0 + 800a250: 75da strb r2, [r3, #23] + if(GBT_StateTick()>5000){ + 800a252: f000 fc1f bl 800aa94 + 800a256: 4603 mov r3, r0 + 800a258: f241 3288 movw r2, #5000 @ 0x1388 + 800a25c: 4293 cmp r3, r2 + 800a25e: d90b bls.n 800a278 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a260: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a264: f000 fc5c bl 800ab20 + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800a268: 4b4e ldr r3, [pc, #312] @ (800a3a4 ) + 800a26a: 220a movs r2, #10 + 800a26c: 775a strb r2, [r3, #29] + log_printf(LOG_ERR, "PSU off timeout, stopping...\n"); + 800a26e: 4952 ldr r1, [pc, #328] @ (800a3b8 ) + 800a270: 2004 movs r0, #4 + 800a272: f001 f8f7 bl 800b464 + break; + 800a276: e334 b.n 800a8e2 + } + if(PSU0.PSU_enabled == 0){ + 800a278: 4b49 ldr r3, [pc, #292] @ (800a3a0 ) + 800a27a: 7a9b ldrb r3, [r3, #10] + 800a27c: 2b00 cmp r3, #0 + 800a27e: f040 831f bne.w 800a8c0 + GBT_SwitchState(GBT_S5_BAT_INFO); + 800a282: 2019 movs r0, #25 + 800a284: f000 fb5a bl 800a93c + } + break; + 800a288: e31a b.n 800a8c0 + + case GBT_S5_BAT_INFO: + if(j_rx.state == 0) GBT_SendCRM(0x00); + 800a28a: 4b44 ldr r3, [pc, #272] @ (800a39c ) + 800a28c: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a290: 2b00 cmp r3, #0 + 800a292: d102 bne.n 800a29a + 800a294: 2000 movs r0, #0 + 800a296: f001 f953 bl 800b540 + GBT_Delay(250); + 800a29a: 20fa movs r0, #250 @ 0xfa + 800a29c: f000 fc06 bl 800aaac + if(GBT_BAT_INFO_recv){ //BRM + 800a2a0: 4b46 ldr r3, [pc, #280] @ (800a3bc ) + 800a2a2: 781b ldrb r3, [r3, #0] + 800a2a4: 2b00 cmp r3, #0 + 800a2a6: d060 beq.n 800a36a + //Got battery info + GBT_SwitchState(GBT_S6_BAT_STAT); + 800a2a8: 201a movs r0, #26 + 800a2aa: f000 fb47 bl 800a93c + log_printf(LOG_INFO, "EV info:\n"); + 800a2ae: 4944 ldr r1, [pc, #272] @ (800a3c0 ) + 800a2b0: 2007 movs r0, #7 + 800a2b2: f001 f8d7 bl 800b464 + log_printf(LOG_INFO, "GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); + 800a2b6: 4b43 ldr r3, [pc, #268] @ (800a3c4 ) + 800a2b8: 781b ldrb r3, [r3, #0] + 800a2ba: 461a mov r2, r3 + 800a2bc: 4b41 ldr r3, [pc, #260] @ (800a3c4 ) + 800a2be: 785b ldrb r3, [r3, #1] + 800a2c0: 4619 mov r1, r3 + 800a2c2: 4b40 ldr r3, [pc, #256] @ (800a3c4 ) + 800a2c4: 789b ldrb r3, [r3, #2] + 800a2c6: 9300 str r3, [sp, #0] + 800a2c8: 460b mov r3, r1 + 800a2ca: 493f ldr r1, [pc, #252] @ (800a3c8 ) + 800a2cc: 2007 movs r0, #7 + 800a2ce: f001 f8c9 bl 800b464 + log_printf(LOG_INFO, "Battery type: %d\n",GBT_EVInfo.batteryType); + 800a2d2: 4b3c ldr r3, [pc, #240] @ (800a3c4 ) + 800a2d4: 78db ldrb r3, [r3, #3] + 800a2d6: 461a mov r2, r3 + 800a2d8: 493c ldr r1, [pc, #240] @ (800a3cc ) + 800a2da: 2007 movs r0, #7 + 800a2dc: f001 f8c2 bl 800b464 + log_printf(LOG_INFO, "Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit + 800a2e0: 4b38 ldr r3, [pc, #224] @ (800a3c4 ) + 800a2e2: 889b ldrh r3, [r3, #4] + 800a2e4: 461a mov r2, r3 + 800a2e6: 493a ldr r1, [pc, #232] @ (800a3d0 ) + 800a2e8: 2007 movs r0, #7 + 800a2ea: f001 f8bb bl 800b464 + log_printf(LOG_INFO, "Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit + 800a2ee: 4b35 ldr r3, [pc, #212] @ (800a3c4 ) + 800a2f0: 88db ldrh r3, [r3, #6] + 800a2f2: 461a mov r2, r3 + 800a2f4: 4937 ldr r1, [pc, #220] @ (800a3d4 ) + 800a2f6: 2007 movs r0, #7 + 800a2f8: f001 f8b4 bl 800b464 + log_printf(LOG_INFO, "Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) + 800a2fc: 4a36 ldr r2, [pc, #216] @ (800a3d8 ) + 800a2fe: 4937 ldr r1, [pc, #220] @ (800a3dc ) + 800a300: 2007 movs r0, #7 + 800a302: f001 f8af bl 800b464 + log_printf(LOG_INFO, "Battery SN: %lu\n", GBT_EVInfo.batterySN); // int + 800a306: 4b2f ldr r3, [pc, #188] @ (800a3c4 ) + 800a308: 68db ldr r3, [r3, #12] + 800a30a: 461a mov r2, r3 + 800a30c: 4934 ldr r1, [pc, #208] @ (800a3e0 ) + 800a30e: 2007 movs r0, #7 + 800a310: f001 f8a8 bl 800b464 + log_printf(LOG_INFO, "Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) + 800a314: 4b2b ldr r3, [pc, #172] @ (800a3c4 ) + 800a316: 7c9b ldrb r3, [r3, #18] + 800a318: 461a mov r2, r3 + 800a31a: 4b2a ldr r3, [pc, #168] @ (800a3c4 ) + 800a31c: 7c5b ldrb r3, [r3, #17] + 800a31e: 4619 mov r1, r3 + 800a320: 4b28 ldr r3, [pc, #160] @ (800a3c4 ) + 800a322: 7c1b ldrb r3, [r3, #16] + 800a324: f203 73c1 addw r3, r3, #1985 @ 0x7c1 + 800a328: 9300 str r3, [sp, #0] + 800a32a: 460b mov r3, r1 + 800a32c: 492d ldr r1, [pc, #180] @ (800a3e4 ) + 800a32e: 2007 movs r0, #7 + 800a330: f001 f898 bl 800b464 + log_printf(LOG_INFO, "Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t + 800a334: 4b23 ldr r3, [pc, #140] @ (800a3c4 ) + 800a336: 7cda ldrb r2, [r3, #19] + 800a338: 8a9b ldrh r3, [r3, #20] + 800a33a: 021b lsls r3, r3, #8 + 800a33c: 4313 orrs r3, r2 + 800a33e: 461a mov r2, r3 + 800a340: 4929 ldr r1, [pc, #164] @ (800a3e8 ) + 800a342: 2007 movs r0, #7 + 800a344: f001 f88e bl 800b464 + log_printf(LOG_INFO, "Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto + 800a348: 4b1e ldr r3, [pc, #120] @ (800a3c4 ) + 800a34a: 7d9b ldrb r3, [r3, #22] + 800a34c: 461a mov r2, r3 + 800a34e: 4927 ldr r1, [pc, #156] @ (800a3ec ) + 800a350: 2007 movs r0, #7 + 800a352: f001 f887 bl 800b464 + log_printf(LOG_INFO, "EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN + 800a356: 4a26 ldr r2, [pc, #152] @ (800a3f0 ) + 800a358: 4926 ldr r1, [pc, #152] @ (800a3f4 ) + 800a35a: 2007 movs r0, #7 + 800a35c: f001 f882 bl 800b464 + log_printf(LOG_INFO, "EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); + 800a360: 4a25 ldr r2, [pc, #148] @ (800a3f8 ) + 800a362: 4926 ldr r1, [pc, #152] @ (800a3fc ) + 800a364: 2007 movs r0, #7 + 800a366: f001 f87d bl 800b464 + + } + //Timeout + if((GBT_StateTick()>5000) && (GBT_BAT_INFO_recv == 0)){ + 800a36a: f000 fb93 bl 800aa94 + 800a36e: 4603 mov r3, r0 + 800a370: f241 3288 movw r2, #5000 @ 0x1388 + 800a374: 4293 cmp r3, r2 + 800a376: f240 82a5 bls.w 800a8c4 + 800a37a: 4b10 ldr r3, [pc, #64] @ (800a3bc ) + 800a37c: 781b ldrb r3, [r3, #0] + 800a37e: 2b00 cmp r3, #0 + 800a380: f040 82a0 bne.w 800a8c4 + CONN.chargingError = CONN_ERR_EV_COMM; + 800a384: 4b07 ldr r3, [pc, #28] @ (800a3a4 ) + 800a386: 2209 movs r2, #9 + 800a388: 775a strb r2, [r3, #29] + GBT_Error(0xFDF0C0FC); //BRM Timeout + 800a38a: 481d ldr r0, [pc, #116] @ (800a400 ) + 800a38c: f000 fc1c bl 800abc8 + log_printf(LOG_ERR, "BRM Timeout\n"); + 800a390: 491c ldr r1, [pc, #112] @ (800a404 ) + 800a392: 2004 movs r0, #4 + 800a394: f001 f866 bl 800b464 + } + break; + 800a398: e294 b.n 800a8c4 + 800a39a: bf00 nop + 800a39c: 20000860 .word 0x20000860 + 800a3a0: 200009fc .word 0x200009fc + 800a3a4: 200002e8 .word 0x200002e8 + 800a3a8: 080164c8 .word 0x080164c8 + 800a3ac: 20000330 .word 0x20000330 + 800a3b0: cccccccd .word 0xcccccccd + 800a3b4: 080164e8 .word 0x080164e8 + 800a3b8: 08016508 .word 0x08016508 + 800a3bc: 20000318 .word 0x20000318 + 800a3c0: 08016528 .word 0x08016528 + 800a3c4: 20000334 .word 0x20000334 + 800a3c8: 08016534 .word 0x08016534 + 800a3cc: 08016548 .word 0x08016548 + 800a3d0: 0801655c .word 0x0801655c + 800a3d4: 08016574 .word 0x08016574 + 800a3d8: 2000033c .word 0x2000033c + 800a3dc: 0801658c .word 0x0801658c + 800a3e0: 080165a4 .word 0x080165a4 + 800a3e4: 080165b8 .word 0x080165b8 + 800a3e8: 080165e4 .word 0x080165e4 + 800a3ec: 080165f8 .word 0x080165f8 + 800a3f0: 2000034c .word 0x2000034c + 800a3f4: 08016608 .word 0x08016608 + 800a3f8: 2000035d .word 0x2000035d + 800a3fc: 08016618 .word 0x08016618 + 800a400: fdf0c0fc .word 0xfdf0c0fc + 800a404: 0801662c .word 0x0801662c + + case GBT_S6_BAT_STAT: + if(j_rx.state == 0) GBT_SendCRM(0xAA); + 800a408: 4bb0 ldr r3, [pc, #704] @ (800a6cc ) + 800a40a: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a40e: 2b00 cmp r3, #0 + 800a410: d102 bne.n 800a418 + 800a412: 20aa movs r0, #170 @ 0xaa + 800a414: f001 f894 bl 800b540 + GBT_Delay(250); + 800a418: 20fa movs r0, #250 @ 0xfa + 800a41a: f000 fb47 bl 800aaac + if(GBT_BAT_STAT_recv){ + 800a41e: 4bac ldr r3, [pc, #688] @ (800a6d0 ) + 800a420: 781b ldrb r3, [r3, #0] + 800a422: 2b00 cmp r3, #0 + 800a424: d05a beq.n 800a4dc + //Got battery status + GBT_SwitchState(GBT_S7_BMS_WAIT); + 800a426: 201b movs r0, #27 + 800a428: f000 fa88 bl 800a93c + log_printf(LOG_INFO, "Battery info:\n"); + 800a42c: 49a9 ldr r1, [pc, #676] @ (800a6d4 ) + 800a42e: 2007 movs r0, #7 + 800a430: f001 f818 bl 800b464 + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit + 800a434: 4ba8 ldr r3, [pc, #672] @ (800a6d8 ) + 800a436: 881b ldrh r3, [r3, #0] + 800a438: 4aa8 ldr r2, [pc, #672] @ (800a6dc ) + 800a43a: fba2 2303 umull r2, r3, r2, r3 + 800a43e: 095b lsrs r3, r3, #5 + 800a440: b29b uxth r3, r3 + 800a442: 461a mov r2, r3 + 800a444: 49a6 ldr r1, [pc, #664] @ (800a6e0 ) + 800a446: 2007 movs r0, #7 + 800a448: f001 f80c bl 800b464 + log_printf(LOG_INFO, "maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit + 800a44c: 4ba2 ldr r3, [pc, #648] @ (800a6d8 ) + 800a44e: 885b ldrh r3, [r3, #2] + 800a450: 4aa4 ldr r2, [pc, #656] @ (800a6e4 ) + 800a452: fba2 2303 umull r2, r3, r2, r3 + 800a456: 08db lsrs r3, r3, #3 + 800a458: b29b uxth r3, r3 + 800a45a: 461a mov r2, r3 + 800a45c: 49a2 ldr r1, [pc, #648] @ (800a6e8 ) + 800a45e: 2007 movs r0, #7 + 800a460: f001 f800 bl 800b464 + log_printf(LOG_INFO, "totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh + 800a464: 4b9c ldr r3, [pc, #624] @ (800a6d8 ) + 800a466: 889b ldrh r3, [r3, #4] + 800a468: 4a9e ldr r2, [pc, #632] @ (800a6e4 ) + 800a46a: fba2 2303 umull r2, r3, r2, r3 + 800a46e: 08db lsrs r3, r3, #3 + 800a470: b29b uxth r3, r3 + 800a472: 461a mov r2, r3 + 800a474: 499d ldr r1, [pc, #628] @ (800a6ec ) + 800a476: 2007 movs r0, #7 + 800a478: f000 fff4 bl 800b464 + log_printf(LOG_INFO, "maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit + 800a47c: 4b96 ldr r3, [pc, #600] @ (800a6d8 ) + 800a47e: 88db ldrh r3, [r3, #6] + 800a480: 4a98 ldr r2, [pc, #608] @ (800a6e4 ) + 800a482: fba2 2303 umull r2, r3, r2, r3 + 800a486: 08db lsrs r3, r3, #3 + 800a488: b29b uxth r3, r3 + 800a48a: 461a mov r2, r3 + 800a48c: 4994 ldr r1, [pc, #592] @ (800a6e0 ) + 800a48e: 2007 movs r0, #7 + 800a490: f000 ffe8 bl 800b464 + log_printf(LOG_INFO, "maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset + 800a494: 4b90 ldr r3, [pc, #576] @ (800a6d8 ) + 800a496: 7a1b ldrb r3, [r3, #8] + 800a498: 3b32 subs r3, #50 @ 0x32 + 800a49a: 461a mov r2, r3 + 800a49c: 4994 ldr r1, [pc, #592] @ (800a6f0 ) + 800a49e: 2007 movs r0, #7 + 800a4a0: f000 ffe0 bl 800b464 + log_printf(LOG_INFO, "SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% + 800a4a4: 4b8c ldr r3, [pc, #560] @ (800a6d8 ) + 800a4a6: f8b3 3009 ldrh.w r3, [r3, #9] + 800a4aa: b29b uxth r3, r3 + 800a4ac: 4a8d ldr r2, [pc, #564] @ (800a6e4 ) + 800a4ae: fba2 2303 umull r2, r3, r2, r3 + 800a4b2: 08db lsrs r3, r3, #3 + 800a4b4: b29b uxth r3, r3 + 800a4b6: 461a mov r2, r3 + 800a4b8: 498e ldr r1, [pc, #568] @ (800a6f4 ) + 800a4ba: 2007 movs r0, #7 + 800a4bc: f000 ffd2 bl 800b464 + log_printf(LOG_INFO, "Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit + 800a4c0: 4b85 ldr r3, [pc, #532] @ (800a6d8 ) + 800a4c2: f8b3 300b ldrh.w r3, [r3, #11] + 800a4c6: b29b uxth r3, r3 + 800a4c8: 4a86 ldr r2, [pc, #536] @ (800a6e4 ) + 800a4ca: fba2 2303 umull r2, r3, r2, r3 + 800a4ce: 08db lsrs r3, r3, #3 + 800a4d0: b29b uxth r3, r3 + 800a4d2: 461a mov r2, r3 + 800a4d4: 4988 ldr r1, [pc, #544] @ (800a6f8 ) + 800a4d6: 2007 movs r0, #7 + 800a4d8: f000 ffc4 bl 800b464 + + } + if((GBT_StateTick()>5000) && (GBT_BAT_STAT_recv == 0)){ + 800a4dc: f000 fada bl 800aa94 + 800a4e0: 4603 mov r3, r0 + 800a4e2: f241 3288 movw r2, #5000 @ 0x1388 + 800a4e6: 4293 cmp r3, r2 + 800a4e8: f240 81ee bls.w 800a8c8 + 800a4ec: 4b78 ldr r3, [pc, #480] @ (800a6d0 ) + 800a4ee: 781b ldrb r3, [r3, #0] + 800a4f0: 2b00 cmp r3, #0 + 800a4f2: f040 81e9 bne.w 800a8c8 + CONN.chargingError = CONN_ERR_EV_COMM; + 800a4f6: 4b81 ldr r3, [pc, #516] @ (800a6fc ) + 800a4f8: 2209 movs r2, #9 + 800a4fa: 775a strb r2, [r3, #29] + GBT_Error(0xFCF1C0FC); //BCP Timeout + 800a4fc: 4880 ldr r0, [pc, #512] @ (800a700 ) + 800a4fe: f000 fb63 bl 800abc8 + log_printf(LOG_ERR, "BCP Timeout\n"); + 800a502: 4980 ldr r1, [pc, #512] @ (800a704 ) + 800a504: 2004 movs r0, #4 + 800a506: f000 ffad bl 800b464 + } + break; + 800a50a: e1dd b.n 800a8c8 + + case GBT_S7_BMS_WAIT: + if(j_rx.state == 0) GBT_SendCTS(); + 800a50c: 4b6f ldr r3, [pc, #444] @ (800a6cc ) + 800a50e: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a512: 2b00 cmp r3, #0 + 800a514: d101 bne.n 800a51a + 800a516: f000 ffdb bl 800b4d0 + HAL_Delay(2); + 800a51a: 2002 movs r0, #2 + 800a51c: f004 f962 bl 800e7e4 + if(j_rx.state == 0) GBT_SendCML(); + 800a520: 4b6a ldr r3, [pc, #424] @ (800a6cc ) + 800a522: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a526: 2b00 cmp r3, #0 + 800a528: d101 bne.n 800a52e + 800a52a: f000 ffe7 bl 800b4fc + GBT_Delay(250); + 800a52e: 20fa movs r0, #250 @ 0xfa + 800a530: f000 fabc bl 800aaac + if((GBT_StateTick()>5000) && (GBT_BRO_recv == 0)){ + 800a534: f000 faae bl 800aa94 + 800a538: 4603 mov r3, r0 + 800a53a: f241 3288 movw r2, #5000 @ 0x1388 + 800a53e: 4293 cmp r3, r2 + 800a540: d90d bls.n 800a55e + 800a542: 4b71 ldr r3, [pc, #452] @ (800a708 ) + 800a544: 781b ldrb r3, [r3, #0] + 800a546: 2b00 cmp r3, #0 + 800a548: d109 bne.n 800a55e + CONN.chargingError = CONN_ERR_EV_COMM; + 800a54a: 4b6c ldr r3, [pc, #432] @ (800a6fc ) + 800a54c: 2209 movs r2, #9 + 800a54e: 775a strb r2, [r3, #29] + GBT_Error(0xFCF4C0FC); //BRO Timeout + 800a550: 486e ldr r0, [pc, #440] @ (800a70c ) + 800a552: f000 fb39 bl 800abc8 + log_printf(LOG_ERR, "BRO Timeout\n"); + 800a556: 496e ldr r1, [pc, #440] @ (800a710 ) + 800a558: 2004 movs r0, #4 + 800a55a: f000 ff83 bl 800b464 + } + if(EV_ready){ + 800a55e: 4b6d ldr r3, [pc, #436] @ (800a714 ) + 800a560: 781b ldrb r3, [r3, #0] + 800a562: 2b00 cmp r3, #0 + 800a564: d003 beq.n 800a56e + //EV ready (AA) + GBT_SwitchState(GBT_S8_INIT_CHARGER); + 800a566: 201c movs r0, #28 + 800a568: f000 f9e8 bl 800a93c + CONN.chargingError = CONN_ERR_EV_COMM; + GBT_Error(0xFCF4C0FC); //BRO Timeout + log_printf(LOG_ERR, "EV not ready for a 60s\n"); + } + } + break; + 800a56c: e1ae b.n 800a8cc + if((GBT_StateTick()>60000) && (GBT_BRO_recv == 1)){ + 800a56e: f000 fa91 bl 800aa94 + 800a572: 4603 mov r3, r0 + 800a574: f64e 2260 movw r2, #60000 @ 0xea60 + 800a578: 4293 cmp r3, r2 + 800a57a: f240 81a7 bls.w 800a8cc + 800a57e: 4b62 ldr r3, [pc, #392] @ (800a708 ) + 800a580: 781b ldrb r3, [r3, #0] + 800a582: 2b01 cmp r3, #1 + 800a584: f040 81a2 bne.w 800a8cc + CONN.chargingError = CONN_ERR_EV_COMM; + 800a588: 4b5c ldr r3, [pc, #368] @ (800a6fc ) + 800a58a: 2209 movs r2, #9 + 800a58c: 775a strb r2, [r3, #29] + GBT_Error(0xFCF4C0FC); //BRO Timeout + 800a58e: 485f ldr r0, [pc, #380] @ (800a70c ) + 800a590: f000 fb1a bl 800abc8 + log_printf(LOG_ERR, "EV not ready for a 60s\n"); + 800a594: 4960 ldr r1, [pc, #384] @ (800a718 ) + 800a596: 2004 movs r0, #4 + 800a598: f000 ff64 bl 800b464 + break; + 800a59c: e196 b.n 800a8cc + + case GBT_S8_INIT_CHARGER: + if(j_rx.state == 0) GBT_SendCRO(0x00); + 800a59e: 4b4b ldr r3, [pc, #300] @ (800a6cc ) + 800a5a0: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a5a4: 2b00 cmp r3, #0 + 800a5a6: d102 bne.n 800a5ae + 800a5a8: 2000 movs r0, #0 + 800a5aa: f000 ffdf bl 800b56c + //TODO + GBT_Delay(250); + 800a5ae: 20fa movs r0, #250 @ 0xfa + 800a5b0: f000 fa7c bl 800aaac + // if(GBT_StateTick()>1500){ + if(PSU0.ready){ + 800a5b4: 4b59 ldr r3, [pc, #356] @ (800a71c ) + 800a5b6: 7a5b ldrb r3, [r3, #9] + 800a5b8: 2b00 cmp r3, #0 + 800a5ba: d002 beq.n 800a5c2 + //Power Modules initiated + GBT_SwitchState(GBT_S9_WAIT_BCL); + 800a5bc: 201d movs r0, #29 + 800a5be: f000 f9bd bl 800a93c + } + if((GBT_StateTick()>6000) && (PSU0.ready == 0)){ + 800a5c2: f000 fa67 bl 800aa94 + 800a5c6: 4603 mov r3, r0 + 800a5c8: f241 7270 movw r2, #6000 @ 0x1770 + 800a5cc: 4293 cmp r3, r2 + 800a5ce: f240 817f bls.w 800a8d0 + 800a5d2: 4b52 ldr r3, [pc, #328] @ (800a71c ) + 800a5d4: 7a5b ldrb r3, [r3, #9] + 800a5d6: 2b00 cmp r3, #0 + 800a5d8: f040 817a bne.w 800a8d0 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a5dc: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a5e0: f000 fa9e bl 800ab20 + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800a5e4: 4b45 ldr r3, [pc, #276] @ (800a6fc ) + 800a5e6: 220a movs r2, #10 + 800a5e8: 775a strb r2, [r3, #29] + log_printf(LOG_ERR, "PSU not ready, stopping...\n"); + 800a5ea: 494d ldr r1, [pc, #308] @ (800a720 ) + 800a5ec: 2004 movs r0, #4 + 800a5ee: f000 ff39 bl 800b464 + } + break; + 800a5f2: e16d b.n 800a8d0 + + case GBT_S9_WAIT_BCL: + if(j_rx.state == 0) GBT_SendCRO(0xAA); + 800a5f4: 4b35 ldr r3, [pc, #212] @ (800a6cc ) + 800a5f6: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a5fa: 2b00 cmp r3, #0 + 800a5fc: d102 bne.n 800a604 + 800a5fe: 20aa movs r0, #170 @ 0xaa + 800a600: f000 ffb4 bl 800b56c + GBT_Delay(250); + 800a604: 20fa movs r0, #250 @ 0xfa + 800a606: f000 fa51 bl 800aaac + if(GBT_ReqPower.chargingMode != 0){ //REFACTORING + 800a60a: 4b46 ldr r3, [pc, #280] @ (800a724 ) + 800a60c: 791b ldrb r3, [r3, #4] + 800a60e: 2b00 cmp r3, #0 + 800a610: f000 8160 beq.w 800a8d4 + //BCL power requirements received + + GBT_SwitchState(GBT_S10_CHARGING); + 800a614: 201e movs r0, #30 + 800a616: f000 f991 bl 800a93c + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + 800a61a: f004 f8d9 bl 800e7d0 + 800a61e: 4603 mov r3, r0 + 800a620: 4a41 ldr r2, [pc, #260] @ (800a728 ) + 800a622: 6013 str r3, [r2, #0] + CONN_SetState(Charging); + 800a624: 2008 movs r0, #8 + 800a626: f000 fca1 bl 800af6c + + uint16_t curr = 4000 - GBT_ReqPower.requestedCurrent; + 800a62a: 4b3e ldr r3, [pc, #248] @ (800a724 ) + 800a62c: 885b ldrh r3, [r3, #2] + 800a62e: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 + 800a632: 807b strh r3, [r7, #2] + uint16_t volt = GBT_ReqPower.requestedVoltage; + 800a634: 4b3b ldr r3, [pc, #236] @ (800a724 ) + 800a636: 881b ldrh r3, [r3, #0] + 800a638: 803b strh r3, [r7, #0] + //TODO Limits + CONN.RequestedVoltage = volt / 10; // В + 800a63a: 883b ldrh r3, [r7, #0] + 800a63c: 4a29 ldr r2, [pc, #164] @ (800a6e4 ) + 800a63e: fba2 2303 umull r2, r3, r2, r3 + 800a642: 08db lsrs r3, r3, #3 + 800a644: b29a uxth r2, r3 + 800a646: 4b2d ldr r3, [pc, #180] @ (800a6fc ) + 800a648: f8a3 200f strh.w r2, [r3, #15] + CONN.WantedCurrent = curr; // 0.1A + 800a64c: 4b2b ldr r3, [pc, #172] @ (800a6fc ) + 800a64e: 887a ldrh r2, [r7, #2] + 800a650: f8a3 201b strh.w r2, [r3, #27] + CONN.EnableOutput = 1; + 800a654: 4b29 ldr r3, [pc, #164] @ (800a6fc ) + 800a656: 2201 movs r2, #1 + 800a658: 75da strb r2, [r3, #23] + GBT_TimeChargingStarted = get_Current_Time(); + 800a65a: f003 fac7 bl 800dbec + 800a65e: 4603 mov r3, r0 + 800a660: 4a32 ldr r2, [pc, #200] @ (800a72c ) + 800a662: 6013 str r3, [r2, #0] + + } + break; + 800a664: e136 b.n 800a8d4 + + case GBT_S10_CHARGING: + //CHARGING + if((HAL_GetTick() - GBT_last_BCL_BCS_BSM_tick) > GBT_BCL_BCS_BSM_TIMEOUT_MS){ + 800a666: f004 f8b3 bl 800e7d0 + 800a66a: 4602 mov r2, r0 + 800a66c: 4b2e ldr r3, [pc, #184] @ (800a728 ) + 800a66e: 681b ldr r3, [r3, #0] + 800a670: 1ad3 subs r3, r2, r3 + 800a672: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 + 800a676: d90b bls.n 800a690 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a678: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a67c: f000 fa50 bl 800ab20 + CONN.chargingError = CONN_ERR_EV_COMM; + 800a680: 4b1e ldr r3, [pc, #120] @ (800a6fc ) + 800a682: 2209 movs r2, #9 + 800a684: 775a strb r2, [r3, #29] + log_printf(LOG_WARN, "BCL/BCS/BSM timeout, stopping...\n"); + 800a686: 492a ldr r1, [pc, #168] @ (800a730 ) + 800a688: 2005 movs r0, #5 + 800a68a: f000 feeb bl 800b464 + break; + 800a68e: e128 b.n 800a8e2 + } + if(CONN.connControl == CMD_STOP) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); + 800a690: 4b1a ldr r3, [pc, #104] @ (800a6fc ) + 800a692: 781b ldrb r3, [r3, #0] + 800a694: 2b01 cmp r3, #1 + 800a696: d102 bne.n 800a69e + 800a698: 4826 ldr r0, [pc, #152] @ (800a734 ) + 800a69a: f000 fa5d bl 800ab58 + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_StopOCPP(GBT_CST_SUSPENDS_ARTIFICIALLY); // --> Finished + 800a69e: 4b17 ldr r3, [pc, #92] @ (800a6fc ) + 800a6a0: 781b ldrb r3, [r3, #0] + 800a6a2: 2b03 cmp r3, #3 + 800a6a4: d102 bne.n 800a6ac + 800a6a6: 4823 ldr r0, [pc, #140] @ (800a734 ) + 800a6a8: f000 fa56 bl 800ab58 + if(GBT_LockState.error) { + 800a6ac: 4b22 ldr r3, [pc, #136] @ (800a738 ) + 800a6ae: 785b ldrb r3, [r3, #1] + 800a6b0: 2b00 cmp r3, #0 + 800a6b2: d045 beq.n 800a740 + GBT_StopEVSE(GBT_CST_OTHERFALUT); // --> Suspend EVSE + 800a6b4: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a6b8: f000 fa32 bl 800ab20 + CONN.chargingError = CONN_ERR_LOCK; + 800a6bc: 4b0f ldr r3, [pc, #60] @ (800a6fc ) + 800a6be: 2204 movs r2, #4 + 800a6c0: 775a strb r2, [r3, #29] + log_printf(LOG_WARN, "Lock error, stopping...\n"); + 800a6c2: 491e ldr r1, [pc, #120] @ (800a73c ) + 800a6c4: 2005 movs r0, #5 + 800a6c6: f000 fecd bl 800b464 + break; + 800a6ca: e10a b.n 800a8e2 + 800a6cc: 20000860 .word 0x20000860 + 800a6d0: 20000319 .word 0x20000319 + 800a6d4: 0801663c .word 0x0801663c + 800a6d8: 20000368 .word 0x20000368 + 800a6dc: 51eb851f .word 0x51eb851f + 800a6e0: 0801664c .word 0x0801664c + 800a6e4: cccccccd .word 0xcccccccd + 800a6e8: 08016658 .word 0x08016658 + 800a6ec: 08016664 .word 0x08016664 + 800a6f0: 08016670 .word 0x08016670 + 800a6f4: 0801667c .word 0x0801667c + 800a6f8: 08016688 .word 0x08016688 + 800a6fc: 200002e8 .word 0x200002e8 + 800a700: fcf1c0fc .word 0xfcf1c0fc + 800a704: 08016694 .word 0x08016694 + 800a708: 2000031a .word 0x2000031a + 800a70c: fcf4c0fc .word 0xfcf4c0fc + 800a710: 080166a4 .word 0x080166a4 + 800a714: 2000031d .word 0x2000031d + 800a718: 080166b4 .word 0x080166b4 + 800a71c: 200009fc .word 0x200009fc + 800a720: 080166cc .word 0x080166cc + 800a724: 20000378 .word 0x20000378 + 800a728: 200003b4 .word 0x200003b4 + 800a72c: 200003b0 .word 0x200003b0 + 800a730: 080166e8 .word 0x080166e8 + 800a734: 0400f0f0 .word 0x0400f0f0 + 800a738: 20000008 .word 0x20000008 + 800a73c: 0801670c .word 0x0801670c + } + if(CONN_CC_GetState()!=GBT_CC_4V){ + 800a740: f000 fcf0 bl 800b124 + 800a744: 4603 mov r3, r0 + 800a746: 2b03 cmp r3, #3 + 800a748: d00b beq.n 800a762 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a74a: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a74e: f000 f9e7 bl 800ab20 + CONN.chargingError = CONN_ERR_HOTPLUG; + 800a752: 4b6c ldr r3, [pc, #432] @ (800a904 ) + 800a754: 2208 movs r2, #8 + 800a756: 775a strb r2, [r3, #29] + log_printf(LOG_WARN, "Hotplug detected, stopping...\n"); + 800a758: 496b ldr r1, [pc, #428] @ (800a908 ) + 800a75a: 2005 movs r0, #5 + 800a75c: f000 fe82 bl 800b464 + break; + 800a760: e0bf b.n 800a8e2 + } + if((GBT_ReadTemp(0) > 90) || (GBT_ReadTemp(1) > 90)) { + 800a762: 2000 movs r0, #0 + 800a764: f7ff f91a bl 800999c + 800a768: 4603 mov r3, r0 + 800a76a: 2b5a cmp r3, #90 @ 0x5a + 800a76c: dc05 bgt.n 800a77a + 800a76e: 2001 movs r0, #1 + 800a770: f7ff f914 bl 800999c + 800a774: 4603 mov r3, r0 + 800a776: 2b5a cmp r3, #90 @ 0x5a + 800a778: dd14 ble.n 800a7a4 + GBT_StopEVSE(GBT_CST_CONNECTOR_OVER_TEMP); + 800a77a: 4864 ldr r0, [pc, #400] @ (800a90c ) + 800a77c: f000 f9d0 bl 800ab20 + CONN.chargingError = CONN_ERR_CONN_TEMP; + 800a780: 4b60 ldr r3, [pc, #384] @ (800a904 ) + 800a782: 2205 movs r2, #5 + 800a784: 775a strb r2, [r3, #29] + log_printf(LOG_WARN, "Connector overheat %d %d, stopping...\n", GBT_ReadTemp(0), GBT_ReadTemp(1)); + 800a786: 2000 movs r0, #0 + 800a788: f7ff f908 bl 800999c + 800a78c: 4603 mov r3, r0 + 800a78e: 461c mov r4, r3 + 800a790: 2001 movs r0, #1 + 800a792: f7ff f903 bl 800999c + 800a796: 4603 mov r3, r0 + 800a798: 4622 mov r2, r4 + 800a79a: 495d ldr r1, [pc, #372] @ (800a910 ) + 800a79c: 2005 movs r0, #5 + 800a79e: f000 fe61 bl 800b464 + break; + 800a7a2: e09e b.n 800a8e2 + } + if(CONN.chargingError != CONN_NO_ERROR){ // --> Suspend EVSE + 800a7a4: 4b57 ldr r3, [pc, #348] @ (800a904 ) + 800a7a6: 7f5b ldrb r3, [r3, #29] + 800a7a8: 2b00 cmp r3, #0 + 800a7aa: d003 beq.n 800a7b4 + GBT_StopEVSE(GBT_CST_OTHERFALUT); + 800a7ac: f24f 40f0 movw r0, #62704 @ 0xf4f0 + 800a7b0: f000 f9b6 bl 800ab20 +// log_printf(LOG_WARN, "Isolation error\n"); + } + + //GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111100;//NOT PERMITTED + GBT_ChargerCurrentStatus.chargingPermissible = 0b1111111111111101; + 800a7b4: 4b57 ldr r3, [pc, #348] @ (800a914 ) + 800a7b6: f64f 72fd movw r2, #65533 @ 0xfffd + 800a7ba: 80da strh r2, [r3, #6] + GBT_ChargerCurrentStatus.chargingTime = (get_Current_Time() - GBT_TimeChargingStarted)/60; + 800a7bc: f003 fa16 bl 800dbec + 800a7c0: 4602 mov r2, r0 + 800a7c2: 4b55 ldr r3, [pc, #340] @ (800a918 ) + 800a7c4: 681b ldr r3, [r3, #0] + 800a7c6: 1ad3 subs r3, r2, r3 + 800a7c8: 4a54 ldr r2, [pc, #336] @ (800a91c ) + 800a7ca: fba2 2303 umull r2, r3, r2, r3 + 800a7ce: 095b lsrs r3, r3, #5 + 800a7d0: b29a uxth r2, r3 + 800a7d2: 4b50 ldr r3, [pc, #320] @ (800a914 ) + 800a7d4: 809a strh r2, [r3, #4] + GBT_ChargerCurrentStatus.outputCurrent = 4000 - CONN.MeasuredCurrent; // 0.1A + 800a7d6: 4b4b ldr r3, [pc, #300] @ (800a904 ) + 800a7d8: f8b3 3015 ldrh.w r3, [r3, #21] + 800a7dc: b29b uxth r3, r3 + 800a7de: f5c3 637a rsb r3, r3, #4000 @ 0xfa0 + 800a7e2: b29a uxth r2, r3 + 800a7e4: 4b4b ldr r3, [pc, #300] @ (800a914 ) + 800a7e6: 805a strh r2, [r3, #2] + GBT_ChargerCurrentStatus.outputVoltage = CONN.MeasuredVoltage * 10; // V -> 0.1V + 800a7e8: 4b46 ldr r3, [pc, #280] @ (800a904 ) + 800a7ea: f8b3 3013 ldrh.w r3, [r3, #19] + 800a7ee: b29b uxth r3, r3 + 800a7f0: 461a mov r2, r3 + 800a7f2: 0092 lsls r2, r2, #2 + 800a7f4: 4413 add r3, r2 + 800a7f6: 005b lsls r3, r3, #1 + 800a7f8: b29a uxth r2, r3 + 800a7fa: 4b46 ldr r3, [pc, #280] @ (800a914 ) + 800a7fc: 801a strh r2, [r3, #0] + + if(j_rx.state == 0) { + 800a7fe: 4b48 ldr r3, [pc, #288] @ (800a920 ) + 800a800: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800a804: 2b00 cmp r3, #0 + 800a806: d105 bne.n 800a814 + GBT_SendCCS(); + 800a808: f000 fec4 bl 800b594 + GBT_Delay(49); + 800a80c: 2031 movs r0, #49 @ 0x31 + 800a80e: f000 f94d bl 800aaac + } + + + //TODO: снижение тока если перегрев контактов + + break; + 800a812: e066 b.n 800a8e2 + GBT_Delay(10); // Resend packet if not sent + 800a814: 200a movs r0, #10 + 800a816: f000 f949 bl 800aaac + break; + 800a81a: e062 b.n 800a8e2 + + case GBT_STOP: + GBT_Delay(10); + 800a81c: 200a movs r0, #10 + 800a81e: f000 f945 bl 800aaac + CONN.EnableOutput = 0; + 800a822: 4b38 ldr r3, [pc, #224] @ (800a904 ) + 800a824: 2200 movs r2, #0 + 800a826: 75da strb r2, [r3, #23] + GBT_SendCST(GBT_StopCauseCode); + 800a828: 4b3e ldr r3, [pc, #248] @ (800a924 ) + 800a82a: 681b ldr r3, [r3, #0] + 800a82c: 4618 mov r0, r3 + 800a82e: f000 febf bl 800b5b0 + //RELAY_Write(RELAY_OUTPUT, 0); + //GBT_SwitchState(GBT_DISABLED); + if(GBT_StateTick()>10000){ + 800a832: f000 f92f bl 800aa94 + 800a836: 4603 mov r3, r0 + 800a838: f242 7210 movw r2, #10000 @ 0x2710 + 800a83c: 4293 cmp r3, r2 + 800a83e: d906 bls.n 800a84e + log_printf(LOG_ERR, "BSD Timeout\n"); + 800a840: 4939 ldr r1, [pc, #228] @ (800a928 ) + 800a842: 2004 movs r0, #4 + 800a844: f000 fe0e bl 800b464 + GBT_Error(0xFCF0C0FD); //BSD Timeout + 800a848: 4838 ldr r0, [pc, #224] @ (800a92c ) + 800a84a: f000 f9bd bl 800abc8 + } + + if(GBT_BSD_recv != 0){ + 800a84e: 4b38 ldr r3, [pc, #224] @ (800a930 ) + 800a850: 781b ldrb r3, [r3, #0] + 800a852: 2b00 cmp r3, #0 + 800a854: d040 beq.n 800a8d8 + GBT_SwitchState(GBT_STOP_CSD); + 800a856: 2020 movs r0, #32 + 800a858: f000 f870 bl 800a93c + } + + break; + 800a85c: e03c b.n 800a8d8 + case GBT_STOP_CSD: + GBT_Delay(250); + 800a85e: 20fa movs r0, #250 @ 0xfa + 800a860: f000 f924 bl 800aaac + GBT_SendCSD(); + 800a864: f000 fec4 bl 800b5f0 + if(GBT_StateTick()>2500){ //2.5S + 800a868: f000 f914 bl 800aa94 + 800a86c: 4603 mov r3, r0 + 800a86e: f640 12c4 movw r2, #2500 @ 0x9c4 + 800a872: 4293 cmp r3, r2 + 800a874: d932 bls.n 800a8dc + GBT_SwitchState(GBT_COMPLETE); + 800a876: 2022 movs r0, #34 @ 0x22 + 800a878: f000 f860 bl 800a93c + + } + break; + 800a87c: e02e b.n 800a8dc + + + case GBT_ERROR: + GBT_SendCEM(GBT_ErrorCode); //2.5S + 800a87e: 4b2d ldr r3, [pc, #180] @ (800a934 ) + 800a880: 681b ldr r3, [r3, #0] + 800a882: 4618 mov r0, r3 + 800a884: f000 fed4 bl 800b630 + GBT_SwitchState(GBT_COMPLETE); + 800a888: 2022 movs r0, #34 @ 0x22 + 800a88a: f000 f857 bl 800a93c + + break; + 800a88e: e028 b.n 800a8e2 + + case GBT_COMPLETE: + if(connectorState != Finished) { + 800a890: 4b29 ldr r3, [pc, #164] @ (800a938 ) + 800a892: 781b ldrb r3, [r3, #0] + 800a894: 2b0a cmp r3, #10 + 800a896: d023 beq.n 800a8e0 + GBT_SwitchState(GBT_DISABLED); + 800a898: 2010 movs r0, #16 + 800a89a: f000 f84f bl 800a93c + GBT_Reset();//CHECK + 800a89e: f000 f9af bl 800ac00 + } + break; + 800a8a2: e01d b.n 800a8e0 + + default: + GBT_SwitchState(GBT_DISABLED); + 800a8a4: 2010 movs r0, #16 + 800a8a6: f000 f849 bl 800a93c + 800a8aa: e01a b.n 800a8e2 + break; + 800a8ac: bf00 nop + 800a8ae: e018 b.n 800a8e2 + break; + 800a8b0: bf00 nop + 800a8b2: e016 b.n 800a8e2 + break; + 800a8b4: bf00 nop + 800a8b6: e014 b.n 800a8e2 + break; + 800a8b8: bf00 nop + 800a8ba: e012 b.n 800a8e2 + break; + 800a8bc: bf00 nop + 800a8be: e010 b.n 800a8e2 + break; + 800a8c0: bf00 nop + 800a8c2: e00e b.n 800a8e2 + break; + 800a8c4: bf00 nop + 800a8c6: e00c b.n 800a8e2 + break; + 800a8c8: bf00 nop + 800a8ca: e00a b.n 800a8e2 + break; + 800a8cc: bf00 nop + 800a8ce: e008 b.n 800a8e2 + break; + 800a8d0: bf00 nop + 800a8d2: e006 b.n 800a8e2 + break; + 800a8d4: bf00 nop + 800a8d6: e004 b.n 800a8e2 + break; + 800a8d8: bf00 nop + 800a8da: e002 b.n 800a8e2 + break; + 800a8dc: bf00 nop + 800a8de: e000 b.n 800a8e2 + break; + 800a8e0: bf00 nop + } + if (CONN_CC_GetState()==GBT_CC_4V) CONN.EvConnected = 1; + 800a8e2: f000 fc1f bl 800b124 + 800a8e6: 4603 mov r3, r0 + 800a8e8: 2b03 cmp r3, #3 + 800a8ea: d103 bne.n 800a8f4 + 800a8ec: 4b05 ldr r3, [pc, #20] @ (800a904 ) + 800a8ee: 2201 movs r2, #1 + 800a8f0: 779a strb r2, [r3, #30] + else CONN.EvConnected = 0; +} + 800a8f2: e002 b.n 800a8fa + else CONN.EvConnected = 0; + 800a8f4: 4b03 ldr r3, [pc, #12] @ (800a904 ) + 800a8f6: 2200 movs r2, #0 + 800a8f8: 779a strb r2, [r3, #30] +} + 800a8fa: bf00 nop + 800a8fc: 3708 adds r7, #8 + 800a8fe: 46bd mov sp, r7 + 800a900: bdb0 pop {r4, r5, r7, pc} + 800a902: bf00 nop + 800a904: 200002e8 .word 0x200002e8 + 800a908: 08016728 .word 0x08016728 + 800a90c: 0001f0f0 .word 0x0001f0f0 + 800a910: 08016748 .word 0x08016748 + 800a914: 2000039c .word 0x2000039c + 800a918: 200003b0 .word 0x200003b0 + 800a91c: 88888889 .word 0x88888889 + 800a920: 20000860 .word 0x20000860 + 800a924: 200003b8 .word 0x200003b8 + 800a928: 08016770 .word 0x08016770 + 800a92c: fcf0c0fd .word 0xfcf0c0fd + 800a930: 2000031c .word 0x2000031c + 800a934: 200003bc .word 0x200003bc + 800a938: 200003c1 .word 0x200003c1 + +0800a93c : + + + +void GBT_SwitchState(gbtState_t state){ + 800a93c: b580 push {r7, lr} + 800a93e: b082 sub sp, #8 + 800a940: af00 add r7, sp, #0 + 800a942: 4603 mov r3, r0 + 800a944: 71fb strb r3, [r7, #7] + GBT_State = state; + 800a946: 4a42 ldr r2, [pc, #264] @ (800aa50 ) + 800a948: 79fb ldrb r3, [r7, #7] + 800a94a: 7013 strb r3, [r2, #0] + GBT_state_tick = HAL_GetTick(); + 800a94c: f003 ff40 bl 800e7d0 + 800a950: 4603 mov r3, r0 + 800a952: 4a40 ldr r2, [pc, #256] @ (800aa54 ) + 800a954: 6013 str r3, [r2, #0] + + if(GBT_State == GBT_DISABLED) log_printf(LOG_INFO, "Disabled\n"); + 800a956: 4b3e ldr r3, [pc, #248] @ (800aa50 ) + 800a958: 781b ldrb r3, [r3, #0] + 800a95a: 2b10 cmp r3, #16 + 800a95c: d103 bne.n 800a966 + 800a95e: 493e ldr r1, [pc, #248] @ (800aa58 ) + 800a960: 2007 movs r0, #7 + 800a962: f000 fd7f bl 800b464 + if(GBT_State == GBT_S3_STARTED) log_printf(LOG_INFO, "Charging started\n"); + 800a966: 4b3a ldr r3, [pc, #232] @ (800aa50 ) + 800a968: 781b ldrb r3, [r3, #0] + 800a96a: 2b13 cmp r3, #19 + 800a96c: d103 bne.n 800a976 + 800a96e: 493b ldr r1, [pc, #236] @ (800aa5c ) + 800a970: 2007 movs r0, #7 + 800a972: f000 fd77 bl 800b464 + if(GBT_State == GBT_S31_WAIT_BHM) log_printf(LOG_INFO, "Waiting for BHM\n"); + 800a976: 4b36 ldr r3, [pc, #216] @ (800aa50 ) + 800a978: 781b ldrb r3, [r3, #0] + 800a97a: 2b14 cmp r3, #20 + 800a97c: d103 bne.n 800a986 + 800a97e: 4938 ldr r1, [pc, #224] @ (800aa60 ) + 800a980: 2007 movs r0, #7 + 800a982: f000 fd6f bl 800b464 + if(GBT_State == GBT_S4_WAIT_PSU_READY) log_printf(LOG_INFO, "Waiting for PSU ready\n"); + 800a986: 4b32 ldr r3, [pc, #200] @ (800aa50 ) + 800a988: 781b ldrb r3, [r3, #0] + 800a98a: 2b15 cmp r3, #21 + 800a98c: d103 bne.n 800a996 + 800a98e: 4935 ldr r1, [pc, #212] @ (800aa64 ) + 800a990: 2007 movs r0, #7 + 800a992: f000 fd67 bl 800b464 + if(GBT_State == GBT_S4_ISOTEST) log_printf(LOG_INFO, "Isolation test\n"); + 800a996: 4b2e ldr r3, [pc, #184] @ (800aa50 ) + 800a998: 781b ldrb r3, [r3, #0] + 800a99a: 2b17 cmp r3, #23 + 800a99c: d103 bne.n 800a9a6 + 800a99e: 4932 ldr r1, [pc, #200] @ (800aa68 ) + 800a9a0: 2007 movs r0, #7 + 800a9a2: f000 fd5f bl 800b464 + if(GBT_State == GBT_S5_BAT_INFO) log_printf(LOG_INFO, "Waiting for battery info\n"); + 800a9a6: 4b2a ldr r3, [pc, #168] @ (800aa50 ) + 800a9a8: 781b ldrb r3, [r3, #0] + 800a9aa: 2b19 cmp r3, #25 + 800a9ac: d103 bne.n 800a9b6 + 800a9ae: 492f ldr r1, [pc, #188] @ (800aa6c ) + 800a9b0: 2007 movs r0, #7 + 800a9b2: f000 fd57 bl 800b464 + if(GBT_State == GBT_S6_BAT_STAT) log_printf(LOG_INFO, "Waiting for battery status\n"); + 800a9b6: 4b26 ldr r3, [pc, #152] @ (800aa50 ) + 800a9b8: 781b ldrb r3, [r3, #0] + 800a9ba: 2b1a cmp r3, #26 + 800a9bc: d103 bne.n 800a9c6 + 800a9be: 492c ldr r1, [pc, #176] @ (800aa70 ) + 800a9c0: 2007 movs r0, #7 + 800a9c2: f000 fd4f bl 800b464 + if(GBT_State == GBT_S7_BMS_WAIT) log_printf(LOG_INFO, "Waiting for BMS\n"); + 800a9c6: 4b22 ldr r3, [pc, #136] @ (800aa50 ) + 800a9c8: 781b ldrb r3, [r3, #0] + 800a9ca: 2b1b cmp r3, #27 + 800a9cc: d103 bne.n 800a9d6 + 800a9ce: 4929 ldr r1, [pc, #164] @ (800aa74 ) + 800a9d0: 2007 movs r0, #7 + 800a9d2: f000 fd47 bl 800b464 + if(GBT_State == GBT_S8_INIT_CHARGER)log_printf(LOG_INFO, "Initializing charger\n"); + 800a9d6: 4b1e ldr r3, [pc, #120] @ (800aa50 ) + 800a9d8: 781b ldrb r3, [r3, #0] + 800a9da: 2b1c cmp r3, #28 + 800a9dc: d103 bne.n 800a9e6 + 800a9de: 4926 ldr r1, [pc, #152] @ (800aa78 ) + 800a9e0: 2007 movs r0, #7 + 800a9e2: f000 fd3f bl 800b464 + if(GBT_State == GBT_S9_WAIT_BCL) log_printf(LOG_INFO, "Waiting for BCL\n"); + 800a9e6: 4b1a ldr r3, [pc, #104] @ (800aa50 ) + 800a9e8: 781b ldrb r3, [r3, #0] + 800a9ea: 2b1d cmp r3, #29 + 800a9ec: d103 bne.n 800a9f6 + 800a9ee: 4923 ldr r1, [pc, #140] @ (800aa7c ) + 800a9f0: 2007 movs r0, #7 + 800a9f2: f000 fd37 bl 800b464 + if(GBT_State == GBT_S10_CHARGING) log_printf(LOG_INFO, "Charging in progress\n"); + 800a9f6: 4b16 ldr r3, [pc, #88] @ (800aa50 ) + 800a9f8: 781b ldrb r3, [r3, #0] + 800a9fa: 2b1e cmp r3, #30 + 800a9fc: d103 bne.n 800aa06 + 800a9fe: 4920 ldr r1, [pc, #128] @ (800aa80 ) + 800aa00: 2007 movs r0, #7 + 800aa02: f000 fd2f bl 800b464 + if(GBT_State == GBT_STOP) log_printf(LOG_INFO, "Charging Stopped\n"); + 800aa06: 4b12 ldr r3, [pc, #72] @ (800aa50 ) + 800aa08: 781b ldrb r3, [r3, #0] + 800aa0a: 2b1f cmp r3, #31 + 800aa0c: d103 bne.n 800aa16 + 800aa0e: 491d ldr r1, [pc, #116] @ (800aa84 ) + 800aa10: 2007 movs r0, #7 + 800aa12: f000 fd27 bl 800b464 + if(GBT_State == GBT_STOP_CSD) log_printf(LOG_INFO, "Charging Stopped with CSD\n"); + 800aa16: 4b0e ldr r3, [pc, #56] @ (800aa50 ) + 800aa18: 781b ldrb r3, [r3, #0] + 800aa1a: 2b20 cmp r3, #32 + 800aa1c: d103 bne.n 800aa26 + 800aa1e: 491a ldr r1, [pc, #104] @ (800aa88 ) + 800aa20: 2007 movs r0, #7 + 800aa22: f000 fd1f bl 800b464 + if(GBT_State == GBT_ERROR) log_printf(LOG_INFO, "Charging Error\n"); + 800aa26: 4b0a ldr r3, [pc, #40] @ (800aa50 ) + 800aa28: 781b ldrb r3, [r3, #0] + 800aa2a: 2b21 cmp r3, #33 @ 0x21 + 800aa2c: d103 bne.n 800aa36 + 800aa2e: 4917 ldr r1, [pc, #92] @ (800aa8c ) + 800aa30: 2007 movs r0, #7 + 800aa32: f000 fd17 bl 800b464 + if(GBT_State == GBT_COMPLETE) log_printf(LOG_INFO, "Charging Finished\n"); + 800aa36: 4b06 ldr r3, [pc, #24] @ (800aa50 ) + 800aa38: 781b ldrb r3, [r3, #0] + 800aa3a: 2b22 cmp r3, #34 @ 0x22 + 800aa3c: d103 bne.n 800aa46 + 800aa3e: 4914 ldr r1, [pc, #80] @ (800aa90 ) + 800aa40: 2007 movs r0, #7 + 800aa42: f000 fd0f bl 800b464 +} + 800aa46: bf00 nop + 800aa48: 3708 adds r7, #8 + 800aa4a: 46bd mov sp, r7 + 800aa4c: bd80 pop {r7, pc} + 800aa4e: bf00 nop + 800aa50: 20000308 .word 0x20000308 + 800aa54: 2000030c .word 0x2000030c + 800aa58: 08016780 .word 0x08016780 + 800aa5c: 0801678c .word 0x0801678c + 800aa60: 080167a0 .word 0x080167a0 + 800aa64: 080167b4 .word 0x080167b4 + 800aa68: 080167cc .word 0x080167cc + 800aa6c: 080167dc .word 0x080167dc + 800aa70: 080167f8 .word 0x080167f8 + 800aa74: 08016814 .word 0x08016814 + 800aa78: 08016828 .word 0x08016828 + 800aa7c: 08016840 .word 0x08016840 + 800aa80: 08016854 .word 0x08016854 + 800aa84: 0801686c .word 0x0801686c + 800aa88: 08016880 .word 0x08016880 + 800aa8c: 0801689c .word 0x0801689c + 800aa90: 080168ac .word 0x080168ac + +0800aa94 : + +uint32_t GBT_StateTick(){ + 800aa94: b580 push {r7, lr} + 800aa96: af00 add r7, sp, #0 + return HAL_GetTick() - GBT_state_tick; + 800aa98: f003 fe9a bl 800e7d0 + 800aa9c: 4602 mov r2, r0 + 800aa9e: 4b02 ldr r3, [pc, #8] @ (800aaa8 ) + 800aaa0: 681b ldr r3, [r3, #0] + 800aaa2: 1ad3 subs r3, r2, r3 +} + 800aaa4: 4618 mov r0, r3 + 800aaa6: bd80 pop {r7, pc} + 800aaa8: 2000030c .word 0x2000030c + +0800aaac : + +void GBT_Delay(uint32_t delay){ + 800aaac: b580 push {r7, lr} + 800aaae: b082 sub sp, #8 + 800aab0: af00 add r7, sp, #0 + 800aab2: 6078 str r0, [r7, #4] + GBT_delay_start = HAL_GetTick(); + 800aab4: f003 fe8c bl 800e7d0 + 800aab8: 4603 mov r3, r0 + 800aaba: 4a04 ldr r2, [pc, #16] @ (800aacc ) + 800aabc: 6013 str r3, [r2, #0] + GBT_delay = delay; + 800aabe: 4a04 ldr r2, [pc, #16] @ (800aad0 ) + 800aac0: 687b ldr r3, [r7, #4] + 800aac2: 6013 str r3, [r2, #0] +} + 800aac4: bf00 nop + 800aac6: 3708 adds r7, #8 + 800aac8: 46bd mov sp, r7 + 800aaca: bd80 pop {r7, pc} + 800aacc: 20000310 .word 0x20000310 + 800aad0: 20000314 .word 0x20000314 + +0800aad4 : + +void GBT_StopEV(uint32_t causecode){ // --> Suspend EV + 800aad4: b580 push {r7, lr} + 800aad6: b082 sub sp, #8 + 800aad8: af00 add r7, sp, #0 + 800aada: 6078 str r0, [r7, #4] + if (CONN.chargingError){ + 800aadc: 4b0c ldr r3, [pc, #48] @ (800ab10 ) + 800aade: 7f5b ldrb r3, [r3, #29] + 800aae0: 2b00 cmp r3, #0 + 800aae2: d003 beq.n 800aaec + GBT_StopSource = GBT_STOP_EVSE; + 800aae4: 4b0b ldr r3, [pc, #44] @ (800ab14 ) + 800aae6: 2200 movs r2, #0 + 800aae8: 701a strb r2, [r3, #0] + 800aaea: e002 b.n 800aaf2 + }else{ + GBT_StopSource = GBT_STOP_EV; + 800aaec: 4b09 ldr r3, [pc, #36] @ (800ab14 ) + 800aaee: 2201 movs r2, #1 + 800aaf0: 701a strb r2, [r3, #0] + } + GBT_StopCauseCode = causecode; + 800aaf2: 4a09 ldr r2, [pc, #36] @ (800ab18 ) + 800aaf4: 687b ldr r3, [r7, #4] + 800aaf6: 6013 str r3, [r2, #0] + if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); + 800aaf8: 4b08 ldr r3, [pc, #32] @ (800ab1c ) + 800aafa: 781b ldrb r3, [r3, #0] + 800aafc: 2b1f cmp r3, #31 + 800aafe: d002 beq.n 800ab06 + 800ab00: 201f movs r0, #31 + 800ab02: f7ff ff1b bl 800a93c +} + 800ab06: bf00 nop + 800ab08: 3708 adds r7, #8 + 800ab0a: 46bd mov sp, r7 + 800ab0c: bd80 pop {r7, pc} + 800ab0e: bf00 nop + 800ab10: 200002e8 .word 0x200002e8 + 800ab14: 200003c0 .word 0x200003c0 + 800ab18: 200003b8 .word 0x200003b8 + 800ab1c: 20000308 .word 0x20000308 + +0800ab20 : + +void GBT_StopEVSE(uint32_t causecode){ // --> Suspend EVSE + 800ab20: b580 push {r7, lr} + 800ab22: b082 sub sp, #8 + 800ab24: af00 add r7, sp, #0 + 800ab26: 6078 str r0, [r7, #4] + GBT_StopSource = GBT_STOP_EVSE; + 800ab28: 4b08 ldr r3, [pc, #32] @ (800ab4c ) + 800ab2a: 2200 movs r2, #0 + 800ab2c: 701a strb r2, [r3, #0] + GBT_StopCauseCode = causecode; + 800ab2e: 4a08 ldr r2, [pc, #32] @ (800ab50 ) + 800ab30: 687b ldr r3, [r7, #4] + 800ab32: 6013 str r3, [r2, #0] + if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); + 800ab34: 4b07 ldr r3, [pc, #28] @ (800ab54 ) + 800ab36: 781b ldrb r3, [r3, #0] + 800ab38: 2b1f cmp r3, #31 + 800ab3a: d002 beq.n 800ab42 + 800ab3c: 201f movs r0, #31 + 800ab3e: f7ff fefd bl 800a93c +} + 800ab42: bf00 nop + 800ab44: 3708 adds r7, #8 + 800ab46: 46bd mov sp, r7 + 800ab48: bd80 pop {r7, pc} + 800ab4a: bf00 nop + 800ab4c: 200003c0 .word 0x200003c0 + 800ab50: 200003b8 .word 0x200003b8 + 800ab54: 20000308 .word 0x20000308 + +0800ab58 : + +void GBT_StopOCPP(uint32_t causecode){ // --> Finished + 800ab58: b580 push {r7, lr} + 800ab5a: b082 sub sp, #8 + 800ab5c: af00 add r7, sp, #0 + 800ab5e: 6078 str r0, [r7, #4] + GBT_StopSource = GBT_STOP_OCPP; + 800ab60: 4b08 ldr r3, [pc, #32] @ (800ab84 ) + 800ab62: 2202 movs r2, #2 + 800ab64: 701a strb r2, [r3, #0] + GBT_StopCauseCode = causecode; + 800ab66: 4a08 ldr r2, [pc, #32] @ (800ab88 ) + 800ab68: 687b ldr r3, [r7, #4] + 800ab6a: 6013 str r3, [r2, #0] + if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); + 800ab6c: 4b07 ldr r3, [pc, #28] @ (800ab8c ) + 800ab6e: 781b ldrb r3, [r3, #0] + 800ab70: 2b1f cmp r3, #31 + 800ab72: d002 beq.n 800ab7a + 800ab74: 201f movs r0, #31 + 800ab76: f7ff fee1 bl 800a93c +} + 800ab7a: bf00 nop + 800ab7c: 3708 adds r7, #8 + 800ab7e: 46bd mov sp, r7 + 800ab80: bd80 pop {r7, pc} + 800ab82: bf00 nop + 800ab84: 200003c0 .word 0x200003c0 + 800ab88: 200003b8 .word 0x200003b8 + 800ab8c: 20000308 .word 0x20000308 + +0800ab90 : + +void GBT_ForceStop(){ // --> Suspend EV + 800ab90: b580 push {r7, lr} + 800ab92: af00 add r7, sp, #0 + GBT_StopSource = GBT_STOP_EV; + 800ab94: 4b0a ldr r3, [pc, #40] @ (800abc0 ) + 800ab96: 2201 movs r2, #1 + 800ab98: 701a strb r2, [r3, #0] + CONN.EnableOutput = 0; + 800ab9a: 4b0a ldr r3, [pc, #40] @ (800abc4 ) + 800ab9c: 2200 movs r2, #0 + 800ab9e: 75da strb r2, [r3, #23] + GBT_SwitchState(GBT_COMPLETE); + 800aba0: 2022 movs r0, #34 @ 0x22 + 800aba2: f7ff fecb bl 800a93c + GBT_Lock(0); + 800aba6: 2000 movs r0, #0 + 800aba8: f001 f906 bl 800bdb8 + RELAY_Write(RELAY_AUX0, 0); + 800abac: 2100 movs r1, #0 + 800abae: 2000 movs r0, #0 + 800abb0: f7fe fd9c bl 80096ec + RELAY_Write(RELAY_AUX1, 0); + 800abb4: 2100 movs r1, #0 + 800abb6: 2001 movs r0, #1 + 800abb8: f7fe fd98 bl 80096ec +} + 800abbc: bf00 nop + 800abbe: bd80 pop {r7, pc} + 800abc0: 200003c0 .word 0x200003c0 + 800abc4: 200002e8 .word 0x200002e8 + +0800abc8 : + +void GBT_Error(uint32_t errorcode){ // --> Suspend EV + 800abc8: b580 push {r7, lr} + 800abca: b082 sub sp, #8 + 800abcc: af00 add r7, sp, #0 + 800abce: 6078 str r0, [r7, #4] + GBT_StopSource = GBT_STOP_EV; + 800abd0: 4b08 ldr r3, [pc, #32] @ (800abf4 ) + 800abd2: 2201 movs r2, #1 + 800abd4: 701a strb r2, [r3, #0] + log_printf(LOG_ERR, "GBT Error code: 0x%X\n", errorcode); + 800abd6: 687a ldr r2, [r7, #4] + 800abd8: 4907 ldr r1, [pc, #28] @ (800abf8 ) + 800abda: 2004 movs r0, #4 + 800abdc: f000 fc42 bl 800b464 + GBT_ErrorCode = errorcode; + 800abe0: 4a06 ldr r2, [pc, #24] @ (800abfc ) + 800abe2: 687b ldr r3, [r7, #4] + 800abe4: 6013 str r3, [r2, #0] + GBT_SwitchState(GBT_ERROR); + 800abe6: 2021 movs r0, #33 @ 0x21 + 800abe8: f7ff fea8 bl 800a93c +} + 800abec: bf00 nop + 800abee: 3708 adds r7, #8 + 800abf0: 46bd mov sp, r7 + 800abf2: bd80 pop {r7, pc} + 800abf4: 200003c0 .word 0x200003c0 + 800abf8: 080168c0 .word 0x080168c0 + 800abfc: 200003bc .word 0x200003bc + +0800ac00 : + + +void GBT_Reset(){ + 800ac00: b580 push {r7, lr} + 800ac02: af00 add r7, sp, #0 + GBT_last_BCL_BCS_BSM_tick = HAL_GetTick(); + 800ac04: f003 fde4 bl 800e7d0 + 800ac08: 4603 mov r3, r0 + 800ac0a: 4a31 ldr r2, [pc, #196] @ (800acd0 ) + 800ac0c: 6013 str r3, [r2, #0] + GBT_BAT_INFO_recv = 0; + 800ac0e: 4b31 ldr r3, [pc, #196] @ (800acd4 ) + 800ac10: 2200 movs r2, #0 + 800ac12: 701a strb r2, [r3, #0] + GBT_BAT_STAT_recv = 0; + 800ac14: 4b30 ldr r3, [pc, #192] @ (800acd8 ) + 800ac16: 2200 movs r2, #0 + 800ac18: 701a strb r2, [r3, #0] + GBT_BRO_recv = 0; + 800ac1a: 4b30 ldr r3, [pc, #192] @ (800acdc ) + 800ac1c: 2200 movs r2, #0 + 800ac1e: 701a strb r2, [r3, #0] + GBT_BHM_recv = 0; + 800ac20: 4b2f ldr r3, [pc, #188] @ (800ace0 ) + 800ac22: 2200 movs r2, #0 + 800ac24: 701a strb r2, [r3, #0] + GBT_BSD_recv = 0; + 800ac26: 4b2f ldr r3, [pc, #188] @ (800ace4 ) + 800ac28: 2200 movs r2, #0 + 800ac2a: 701a strb r2, [r3, #0] + EV_ready = 0; + 800ac2c: 4b2e ldr r3, [pc, #184] @ (800ace8 ) + 800ac2e: 2200 movs r2, #0 + 800ac30: 701a strb r2, [r3, #0] + CONN.SOC = 0; + 800ac32: 4b2e ldr r3, [pc, #184] @ (800acec ) + 800ac34: 2200 movs r2, #0 + 800ac36: 709a strb r2, [r3, #2] + CONN.EnableOutput = 0; + 800ac38: 4b2c ldr r3, [pc, #176] @ (800acec ) + 800ac3a: 2200 movs r2, #0 + 800ac3c: 75da strb r2, [r3, #23] + CONN.WantedCurrent = 0; + 800ac3e: 4b2b ldr r3, [pc, #172] @ (800acec ) + 800ac40: 2200 movs r2, #0 + 800ac42: 76da strb r2, [r3, #27] + 800ac44: 2200 movs r2, #0 + 800ac46: 771a strb r2, [r3, #28] + CONN.RequestedVoltage = 0; + 800ac48: 4b28 ldr r3, [pc, #160] @ (800acec ) + 800ac4a: 2200 movs r2, #0 + 800ac4c: 73da strb r2, [r3, #15] + 800ac4e: 2200 movs r2, #0 + 800ac50: 741a strb r2, [r3, #16] + memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); + 800ac52: 2231 movs r2, #49 @ 0x31 + 800ac54: 2100 movs r1, #0 + 800ac56: 4826 ldr r0, [pc, #152] @ (800acf0 ) + 800ac58: f009 fa1a bl 8014090 + memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); + 800ac5c: 220d movs r2, #13 + 800ac5e: 2100 movs r1, #0 + 800ac60: 4824 ldr r0, [pc, #144] @ (800acf4 ) + 800ac62: f009 fa15 bl 8014090 + memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); + 800ac66: 2205 movs r2, #5 + 800ac68: 2100 movs r1, #0 + 800ac6a: 4823 ldr r0, [pc, #140] @ (800acf8 ) + 800ac6c: f009 fa10 bl 8014090 + memset(&GBT_CurrPower, 0, sizeof (GBT_CurrPower)); + 800ac70: 2205 movs r2, #5 + 800ac72: 2100 movs r1, #0 + 800ac74: 4821 ldr r0, [pc, #132] @ (800acfc ) + 800ac76: f009 fa0b bl 8014090 + memset(&GBT_MaxVoltage, 0, sizeof (GBT_MaxVoltage)); + 800ac7a: 2202 movs r2, #2 + 800ac7c: 2100 movs r1, #0 + 800ac7e: 4820 ldr r0, [pc, #128] @ (800ad00 ) + 800ac80: f009 fa06 bl 8014090 + memset(&GBT_ChargingStatus, 0, sizeof (GBT_ChargingStatus)); + 800ac84: 2209 movs r2, #9 + 800ac86: 2100 movs r1, #0 + 800ac88: 481e ldr r0, [pc, #120] @ (800ad04 ) + 800ac8a: f009 fa01 bl 8014090 + memset(&GBT_BatteryStatus, 0, sizeof (GBT_BatteryStatus)); + 800ac8e: 2207 movs r2, #7 + 800ac90: 2100 movs r1, #0 + 800ac92: 481d ldr r0, [pc, #116] @ (800ad08 ) + 800ac94: f009 f9fc bl 8014090 + memset(&GBT_ChargerCurrentStatus, 0, sizeof (GBT_ChargerCurrentStatus)); + 800ac98: 2208 movs r2, #8 + 800ac9a: 2100 movs r1, #0 + 800ac9c: 481b ldr r0, [pc, #108] @ (800ad0c ) + 800ac9e: f009 f9f7 bl 8014090 + memset(&GBT_ChargerStop, 0, sizeof (GBT_ChargerStop)); + 800aca2: 2208 movs r2, #8 + 800aca4: 2100 movs r1, #0 + 800aca6: 481a ldr r0, [pc, #104] @ (800ad10 ) + 800aca8: f009 f9f2 bl 8014090 + GBT_CurrPower.requestedCurrent = 4000; //0A + 800acac: 4b13 ldr r3, [pc, #76] @ (800acfc ) + 800acae: f44f 627a mov.w r2, #4000 @ 0xfa0 + 800acb2: 805a strh r2, [r3, #2] + GBT_CurrPower.requestedVoltage = 500; //50V + 800acb4: 4b11 ldr r3, [pc, #68] @ (800acfc ) + 800acb6: f44f 72fa mov.w r2, #500 @ 0x1f4 + 800acba: 801a strh r2, [r3, #0] + GBT_TimeChargingStarted = 0; + 800acbc: 4b15 ldr r3, [pc, #84] @ (800ad14 ) + 800acbe: 2200 movs r2, #0 + 800acc0: 601a str r2, [r3, #0] + GBT_BRO = 0x00; + 800acc2: 4b15 ldr r3, [pc, #84] @ (800ad18 ) + 800acc4: 2200 movs r2, #0 + 800acc6: 701a strb r2, [r3, #0] + GBT_LockResetError(); + 800acc8: f001 f980 bl 800bfcc +} + 800accc: bf00 nop + 800acce: bd80 pop {r7, pc} + 800acd0: 200003b4 .word 0x200003b4 + 800acd4: 20000318 .word 0x20000318 + 800acd8: 20000319 .word 0x20000319 + 800acdc: 2000031a .word 0x2000031a + 800ace0: 2000031b .word 0x2000031b + 800ace4: 2000031c .word 0x2000031c + 800ace8: 2000031d .word 0x2000031d + 800acec: 200002e8 .word 0x200002e8 + 800acf0: 20000334 .word 0x20000334 + 800acf4: 20000368 .word 0x20000368 + 800acf8: 20000378 .word 0x20000378 + 800acfc: 20000380 .word 0x20000380 + 800ad00: 20000330 .word 0x20000330 + 800ad04: 20000388 .word 0x20000388 + 800ad08: 20000394 .word 0x20000394 + 800ad0c: 2000039c .word 0x2000039c + 800ad10: 200003a4 .word 0x200003a4 + 800ad14: 200003b0 .word 0x200003b0 + 800ad18: 200003ac .word 0x200003ac + +0800ad1c : +void GBT_Start(){ + 800ad1c: b580 push {r7, lr} + 800ad1e: af00 add r7, sp, #0 + RELAY_Write(RELAY_AUX0, 1); + 800ad20: 2101 movs r1, #1 + 800ad22: 2000 movs r0, #0 + 800ad24: f7fe fce2 bl 80096ec + RELAY_Write(RELAY_AUX1, 1); + 800ad28: 2101 movs r1, #1 + 800ad2a: 2001 movs r0, #1 + 800ad2c: f7fe fcde bl 80096ec + + GBT_SwitchState(GBT_S3_STARTED); + 800ad30: 2013 movs r0, #19 + 800ad32: f7ff fe03 bl 800a93c +} + 800ad36: bf00 nop + 800ad38: bd80 pop {r7, pc} + ... + +0800ad3c : + +extern uint8_t config_initialized; + +gbtCcState_t CC_STATE_FILTERED; + +void CONN_Task(){ + 800ad3c: b580 push {r7, lr} + 800ad3e: af00 add r7, sp, #0 + + switch (connectorState){ + 800ad40: 4b85 ldr r3, [pc, #532] @ (800af58 ) + 800ad42: 781b ldrb r3, [r3, #0] + 800ad44: 2b0c cmp r3, #12 + 800ad46: f200 80f3 bhi.w 800af30 + 800ad4a: a201 add r2, pc, #4 @ (adr r2, 800ad50 ) + 800ad4c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ad50: 0800ad85 .word 0x0800ad85 + 800ad54: 0800adc3 .word 0x0800adc3 + 800ad58: 0800ad9d .word 0x0800ad9d + 800ad5c: 0800ae4f .word 0x0800ae4f + 800ad60: 0800ae09 .word 0x0800ae09 + 800ad64: 0800af31 .word 0x0800af31 + 800ad68: 0800af31 .word 0x0800af31 + 800ad6c: 0800af31 .word 0x0800af31 + 800ad70: 0800aea3 .word 0x0800aea3 + 800ad74: 0800af31 .word 0x0800af31 + 800ad78: 0800af05 .word 0x0800af05 + 800ad7c: 0800aef7 .word 0x0800aef7 + 800ad80: 0800aee9 .word 0x0800aee9 + case Unknown: // unlocked, waiting for config + GBT_Lock(0); + 800ad84: 2000 movs r0, #0 + 800ad86: f001 f817 bl 800bdb8 + if (config_initialized) { + 800ad8a: 4b74 ldr r3, [pc, #464] @ (800af5c ) + 800ad8c: 781b ldrb r3, [r3, #0] + 800ad8e: 2b00 cmp r3, #0 + 800ad90: f000 80d2 beq.w 800af38 + CONN_SetState(Unplugged); + 800ad94: 2001 movs r0, #1 + 800ad96: f000 f8e9 bl 800af6c + } + break; + 800ad9a: e0cd b.n 800af38 + + case Disabled: // faulted, unlocked + GBT_Lock(0); + 800ad9c: 2000 movs r0, #0 + 800ad9e: f001 f80b bl 800bdb8 + if(CONN.chargingError == 0) CONN_SetState(Unplugged); + 800ada2: 4b6f ldr r3, [pc, #444] @ (800af60 ) + 800ada4: 7f5b ldrb r3, [r3, #29] + 800ada6: 2b00 cmp r3, #0 + 800ada8: d102 bne.n 800adb0 + 800adaa: 2001 movs r0, #1 + 800adac: f000 f8de bl 800af6c + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + 800adb0: 4b6b ldr r3, [pc, #428] @ (800af60 ) + 800adb2: 781b ldrb r3, [r3, #0] + 800adb4: 2b03 cmp r3, #3 + 800adb6: f040 80c1 bne.w 800af3c + 800adba: 2000 movs r0, #0 + 800adbc: f000 ffc8 bl 800bd50 + break; + 800adc0: e0bc b.n 800af3c + + case Unplugged: // unlocked, waiting to connect + GBT_Lock(0); + 800adc2: 2000 movs r0, #0 + 800adc4: f000 fff8 bl 800bdb8 + if(CONN.chargingError != 0) CONN_SetState(Disabled); + 800adc8: 4b65 ldr r3, [pc, #404] @ (800af60 ) + 800adca: 7f5b ldrb r3, [r3, #29] + 800adcc: 2b00 cmp r3, #0 + 800adce: d002 beq.n 800add6 + 800add0: 2002 movs r0, #2 + 800add2: f000 f8cb bl 800af6c + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + 800add6: 4b62 ldr r3, [pc, #392] @ (800af60 ) + 800add8: 781b ldrb r3, [r3, #0] + 800adda: 2b03 cmp r3, #3 + 800addc: d102 bne.n 800ade4 + 800adde: 2000 movs r0, #0 + 800ade0: f000 ffb6 bl 800bd50 + + if((CONN_CC_GetState()==GBT_CC_4V) && (CONN.connControl != CMD_FORCE_UNLOCK)){ + 800ade4: f000 f99e bl 800b124 + 800ade8: 4603 mov r3, r0 + 800adea: 2b03 cmp r3, #3 + 800adec: f040 80a8 bne.w 800af40 + 800adf0: 4b5b ldr r3, [pc, #364] @ (800af60 ) + 800adf2: 781b ldrb r3, [r3, #0] + 800adf4: 2b03 cmp r3, #3 + 800adf6: f000 80a3 beq.w 800af40 + CONN_SetState(AuthRequired); + 800adfa: 2004 movs r0, #4 + 800adfc: f000 f8b6 bl 800af6c + GBT_Lock(0); + 800ae00: 2000 movs r0, #0 + 800ae02: f000 ffd9 bl 800bdb8 + } + break; + 800ae06: e09b b.n 800af40 + + case AuthRequired: // plugged, waiting to start charge + GBT_Lock(0); + 800ae08: 2000 movs r0, #0 + 800ae0a: f000 ffd5 bl 800bdb8 + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + 800ae0e: 4b54 ldr r3, [pc, #336] @ (800af60 ) + 800ae10: 781b ldrb r3, [r3, #0] + 800ae12: 2b03 cmp r3, #3 + 800ae14: d102 bne.n 800ae1c + 800ae16: 2000 movs r0, #0 + 800ae18: f000 ff9a bl 800bd50 + if(CONN_CC_GetState()==GBT_CC_4V){ + 800ae1c: f000 f982 bl 800b124 + 800ae20: 4603 mov r3, r0 + 800ae22: 2b03 cmp r3, #3 + 800ae24: d10f bne.n 800ae46 + if(CONN.connControl == CMD_START){ + 800ae26: 4b4e ldr r3, [pc, #312] @ (800af60 ) + 800ae28: 781b ldrb r3, [r3, #0] + 800ae2a: 2b02 cmp r3, #2 + 800ae2c: d102 bne.n 800ae34 + CONN_SetState(Preparing); + 800ae2e: 2003 movs r0, #3 + 800ae30: f000 f89c bl 800af6c + } + if(CONN.connControl == CMD_FORCE_UNLOCK){ + 800ae34: 4b4a ldr r3, [pc, #296] @ (800af60 ) + 800ae36: 781b ldrb r3, [r3, #0] + 800ae38: 2b03 cmp r3, #3 + 800ae3a: f040 8083 bne.w 800af44 + CONN_SetState(Unplugged); + 800ae3e: 2001 movs r0, #1 + 800ae40: f000 f894 bl 800af6c + } + // if CHARGING_NOT_ALLOWED — stay here + }else{ + CONN_SetState(Unplugged); + } + break; + 800ae44: e07e b.n 800af44 + CONN_SetState(Unplugged); + 800ae46: 2001 movs r0, #1 + 800ae48: f000 f890 bl 800af6c + break; + 800ae4c: e07a b.n 800af44 + + case Preparing: // charging, locked + GBT_Lock(1); + 800ae4e: 2001 movs r0, #1 + 800ae50: f000 ffb2 bl 800bdb8 + + if(GBT_State == GBT_COMPLETE){ + 800ae54: 4b43 ldr r3, [pc, #268] @ (800af64 ) + 800ae56: 781b ldrb r3, [r3, #0] + 800ae58: 2b22 cmp r3, #34 @ 0x22 + 800ae5a: d11a bne.n 800ae92 + if(GBT_StopSource == GBT_STOP_EVSE){ + 800ae5c: 4b42 ldr r3, [pc, #264] @ (800af68 ) + 800ae5e: 781b ldrb r3, [r3, #0] + 800ae60: 2b00 cmp r3, #0 + 800ae62: d103 bne.n 800ae6c + CONN_SetState(FinishedEVSE); + 800ae64: 200b movs r0, #11 + 800ae66: f000 f881 bl 800af6c + 800ae6a: e012 b.n 800ae92 + }else if(GBT_StopSource == GBT_STOP_EV){ + 800ae6c: 4b3e ldr r3, [pc, #248] @ (800af68 ) + 800ae6e: 781b ldrb r3, [r3, #0] + 800ae70: 2b01 cmp r3, #1 + 800ae72: d103 bne.n 800ae7c + CONN_SetState(FinishedEV); + 800ae74: 200c movs r0, #12 + 800ae76: f000 f879 bl 800af6c + 800ae7a: e00a b.n 800ae92 + }else if(GBT_StopSource == GBT_STOP_OCPP){ + 800ae7c: 4b3a ldr r3, [pc, #232] @ (800af68 ) + 800ae7e: 781b ldrb r3, [r3, #0] + 800ae80: 2b02 cmp r3, #2 + 800ae82: d103 bne.n 800ae8c + CONN_SetState(Finished); + 800ae84: 200a movs r0, #10 + 800ae86: f000 f871 bl 800af6c + 800ae8a: e002 b.n 800ae92 + }else{ + CONN_SetState(FinishedEVSE); + 800ae8c: 200b movs r0, #11 + 800ae8e: f000 f86d bl 800af6c + } + } + if(GBT_State == GBT_S10_CHARGING){ + 800ae92: 4b34 ldr r3, [pc, #208] @ (800af64 ) + 800ae94: 781b ldrb r3, [r3, #0] + 800ae96: 2b1e cmp r3, #30 + 800ae98: d156 bne.n 800af48 + CONN_SetState(Charging); + 800ae9a: 2008 movs r0, #8 + 800ae9c: f000 f866 bl 800af6c + } + break; + 800aea0: e052 b.n 800af48 + case Charging: // charging, locked + GBT_Lock(1); + 800aea2: 2001 movs r0, #1 + 800aea4: f000 ff88 bl 800bdb8 + + if(GBT_State == GBT_COMPLETE){ + 800aea8: 4b2e ldr r3, [pc, #184] @ (800af64 ) + 800aeaa: 781b ldrb r3, [r3, #0] + 800aeac: 2b22 cmp r3, #34 @ 0x22 + 800aeae: d14d bne.n 800af4c + if(GBT_StopSource == GBT_STOP_EVSE){ + 800aeb0: 4b2d ldr r3, [pc, #180] @ (800af68 ) + 800aeb2: 781b ldrb r3, [r3, #0] + 800aeb4: 2b00 cmp r3, #0 + 800aeb6: d103 bne.n 800aec0 + CONN_SetState(FinishedEVSE); + 800aeb8: 200b movs r0, #11 + 800aeba: f000 f857 bl 800af6c + CONN_SetState(Finished); + }else{ + CONN_SetState(FinishedEVSE); + } + } + break; + 800aebe: e045 b.n 800af4c + }else if(GBT_StopSource == GBT_STOP_EV){ + 800aec0: 4b29 ldr r3, [pc, #164] @ (800af68 ) + 800aec2: 781b ldrb r3, [r3, #0] + 800aec4: 2b01 cmp r3, #1 + 800aec6: d103 bne.n 800aed0 + CONN_SetState(FinishedEV); + 800aec8: 200c movs r0, #12 + 800aeca: f000 f84f bl 800af6c + break; + 800aece: e03d b.n 800af4c + }else if(GBT_StopSource == GBT_STOP_OCPP){ + 800aed0: 4b25 ldr r3, [pc, #148] @ (800af68 ) + 800aed2: 781b ldrb r3, [r3, #0] + 800aed4: 2b02 cmp r3, #2 + 800aed6: d103 bne.n 800aee0 + CONN_SetState(Finished); + 800aed8: 200a movs r0, #10 + 800aeda: f000 f847 bl 800af6c + break; + 800aede: e035 b.n 800af4c + CONN_SetState(FinishedEVSE); + 800aee0: 200b movs r0, #11 + 800aee2: f000 f843 bl 800af6c + break; + 800aee6: e031 b.n 800af4c + + case FinishedEV: // charging completed by EV, waiting to transaction stop + GBT_Lock(0); + 800aee8: 2000 movs r0, #0 + 800aeea: f000 ff65 bl 800bdb8 + CONN_SetState(Finished); + 800aeee: 200a movs r0, #10 + 800aef0: f000 f83c bl 800af6c + break; + 800aef4: e02d b.n 800af52 + + case FinishedEVSE: // charging completed by EVSE, waiting to transaction stop + GBT_Lock(0); + 800aef6: 2000 movs r0, #0 + 800aef8: f000 ff5e bl 800bdb8 + CONN_SetState(Finished); + 800aefc: 200a movs r0, #10 + 800aefe: f000 f835 bl 800af6c + break; + 800af02: e026 b.n 800af52 + + case Finished: // charging completed, waiting to disconnect, unlocked + GBT_Lock(0); + 800af04: 2000 movs r0, #0 + 800af06: f000 ff57 bl 800bdb8 + + //TODO Force unlock time limit + if(CONN.connControl == CMD_FORCE_UNLOCK) GBT_ForceLock(0); + 800af0a: 4b15 ldr r3, [pc, #84] @ (800af60 ) + 800af0c: 781b ldrb r3, [r3, #0] + 800af0e: 2b03 cmp r3, #3 + 800af10: d102 bne.n 800af18 + 800af12: 2000 movs r0, #0 + 800af14: f000 ff1c bl 800bd50 + + if(CONN_CC_GetState()==GBT_CC_6V){ + 800af18: f000 f904 bl 800b124 + 800af1c: 4603 mov r3, r0 + 800af1e: 2b02 cmp r3, #2 + 800af20: d116 bne.n 800af50 + GBT_Lock(0); + 800af22: 2000 movs r0, #0 + 800af24: f000 ff48 bl 800bdb8 + CONN_SetState(Unplugged); + 800af28: 2001 movs r0, #1 + 800af2a: f000 f81f bl 800af6c + } + break; + 800af2e: e00f b.n 800af50 + + default: + CONN_SetState(Unknown); + 800af30: 2000 movs r0, #0 + 800af32: f000 f81b bl 800af6c + } + +} + 800af36: e00c b.n 800af52 + break; + 800af38: bf00 nop + 800af3a: e00a b.n 800af52 + break; + 800af3c: bf00 nop + 800af3e: e008 b.n 800af52 + break; + 800af40: bf00 nop + 800af42: e006 b.n 800af52 + break; + 800af44: bf00 nop + 800af46: e004 b.n 800af52 + break; + 800af48: bf00 nop + 800af4a: e002 b.n 800af52 + break; + 800af4c: bf00 nop + 800af4e: e000 b.n 800af52 + break; + 800af50: bf00 nop +} + 800af52: bf00 nop + 800af54: bd80 pop {r7, pc} + 800af56: bf00 nop + 800af58: 200003c1 .word 0x200003c1 + 800af5c: 20000cf2 .word 0x20000cf2 + 800af60: 200002e8 .word 0x200002e8 + 800af64: 20000308 .word 0x20000308 + 800af68: 200003c0 .word 0x200003c0 + +0800af6c : +//external +//CONN_SetState(Disabled); + +void CONN_SetState(CONN_State_t state){ + 800af6c: b580 push {r7, lr} + 800af6e: b082 sub sp, #8 + 800af70: af00 add r7, sp, #0 + 800af72: 4603 mov r3, r0 + 800af74: 71fb strb r3, [r7, #7] + connectorState = state; + 800af76: 4a3d ldr r2, [pc, #244] @ (800b06c ) + 800af78: 79fb ldrb r3, [r7, #7] + 800af7a: 7013 strb r3, [r2, #0] + + if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); + 800af7c: 4b3b ldr r3, [pc, #236] @ (800b06c ) + 800af7e: 781b ldrb r3, [r3, #0] + 800af80: 2b00 cmp r3, #0 + 800af82: d103 bne.n 800af8c + 800af84: 493a ldr r1, [pc, #232] @ (800b070 ) + 800af86: 2007 movs r0, #7 + 800af88: f000 fa6c bl 800b464 + if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); + 800af8c: 4b37 ldr r3, [pc, #220] @ (800b06c ) + 800af8e: 781b ldrb r3, [r3, #0] + 800af90: 2b01 cmp r3, #1 + 800af92: d103 bne.n 800af9c + 800af94: 4937 ldr r1, [pc, #220] @ (800b074 ) + 800af96: 2007 movs r0, #7 + 800af98: f000 fa64 bl 800b464 + if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); + 800af9c: 4b33 ldr r3, [pc, #204] @ (800b06c ) + 800af9e: 781b ldrb r3, [r3, #0] + 800afa0: 2b02 cmp r3, #2 + 800afa2: d103 bne.n 800afac + 800afa4: 4934 ldr r1, [pc, #208] @ (800b078 ) + 800afa6: 2007 movs r0, #7 + 800afa8: f000 fa5c bl 800b464 + if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); + 800afac: 4b2f ldr r3, [pc, #188] @ (800b06c ) + 800afae: 781b ldrb r3, [r3, #0] + 800afb0: 2b03 cmp r3, #3 + 800afb2: d103 bne.n 800afbc + 800afb4: 4931 ldr r1, [pc, #196] @ (800b07c ) + 800afb6: 2007 movs r0, #7 + 800afb8: f000 fa54 bl 800b464 + if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); + 800afbc: 4b2b ldr r3, [pc, #172] @ (800b06c ) + 800afbe: 781b ldrb r3, [r3, #0] + 800afc0: 2b04 cmp r3, #4 + 800afc2: d103 bne.n 800afcc + 800afc4: 492e ldr r1, [pc, #184] @ (800b080 ) + 800afc6: 2007 movs r0, #7 + 800afc8: f000 fa4c bl 800b464 + if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); + 800afcc: 4b27 ldr r3, [pc, #156] @ (800b06c ) + 800afce: 781b ldrb r3, [r3, #0] + 800afd0: 2b05 cmp r3, #5 + 800afd2: d103 bne.n 800afdc + 800afd4: 492b ldr r1, [pc, #172] @ (800b084 ) + 800afd6: 2007 movs r0, #7 + 800afd8: f000 fa44 bl 800b464 + if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); + 800afdc: 4b23 ldr r3, [pc, #140] @ (800b06c ) + 800afde: 781b ldrb r3, [r3, #0] + 800afe0: 2b06 cmp r3, #6 + 800afe2: d103 bne.n 800afec + 800afe4: 4928 ldr r1, [pc, #160] @ (800b088 ) + 800afe6: 2007 movs r0, #7 + 800afe8: f000 fa3c bl 800b464 + if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); + 800afec: 4b1f ldr r3, [pc, #124] @ (800b06c ) + 800afee: 781b ldrb r3, [r3, #0] + 800aff0: 2b07 cmp r3, #7 + 800aff2: d103 bne.n 800affc + 800aff4: 4925 ldr r1, [pc, #148] @ (800b08c ) + 800aff6: 2007 movs r0, #7 + 800aff8: f000 fa34 bl 800b464 + if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); + 800affc: 4b1b ldr r3, [pc, #108] @ (800b06c ) + 800affe: 781b ldrb r3, [r3, #0] + 800b000: 2b08 cmp r3, #8 + 800b002: d103 bne.n 800b00c + 800b004: 4922 ldr r1, [pc, #136] @ (800b090 ) + 800b006: 2007 movs r0, #7 + 800b008: f000 fa2c bl 800b464 + if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); + 800b00c: 4b17 ldr r3, [pc, #92] @ (800b06c ) + 800b00e: 781b ldrb r3, [r3, #0] + 800b010: 2b09 cmp r3, #9 + 800b012: d103 bne.n 800b01c + 800b014: 491f ldr r1, [pc, #124] @ (800b094 ) + 800b016: 2007 movs r0, #7 + 800b018: f000 fa24 bl 800b464 + if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); + 800b01c: 4b13 ldr r3, [pc, #76] @ (800b06c ) + 800b01e: 781b ldrb r3, [r3, #0] + 800b020: 2b0a cmp r3, #10 + 800b022: d103 bne.n 800b02c + 800b024: 491c ldr r1, [pc, #112] @ (800b098 ) + 800b026: 2007 movs r0, #7 + 800b028: f000 fa1c bl 800b464 + if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); + 800b02c: 4b0f ldr r3, [pc, #60] @ (800b06c ) + 800b02e: 781b ldrb r3, [r3, #0] + 800b030: 2b0b cmp r3, #11 + 800b032: d103 bne.n 800b03c + 800b034: 4919 ldr r1, [pc, #100] @ (800b09c ) + 800b036: 2007 movs r0, #7 + 800b038: f000 fa14 bl 800b464 + if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); + 800b03c: 4b0b ldr r3, [pc, #44] @ (800b06c ) + 800b03e: 781b ldrb r3, [r3, #0] + 800b040: 2b0c cmp r3, #12 + 800b042: d103 bne.n 800b04c + 800b044: 4916 ldr r1, [pc, #88] @ (800b0a0 ) + 800b046: 2007 movs r0, #7 + 800b048: f000 fa0c bl 800b464 + if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); + 800b04c: 4b07 ldr r3, [pc, #28] @ (800b06c ) + 800b04e: 781b ldrb r3, [r3, #0] + 800b050: 2b0d cmp r3, #13 + 800b052: d103 bne.n 800b05c + 800b054: 4913 ldr r1, [pc, #76] @ (800b0a4 ) + 800b056: 2007 movs r0, #7 + 800b058: f000 fa04 bl 800b464 + + CONN.connState = state; + 800b05c: 4a12 ldr r2, [pc, #72] @ (800b0a8 ) + 800b05e: 79fb ldrb r3, [r7, #7] + 800b060: 7053 strb r3, [r2, #1] +} + 800b062: bf00 nop + 800b064: 3708 adds r7, #8 + 800b066: 46bd mov sp, r7 + 800b068: bd80 pop {r7, pc} + 800b06a: bf00 nop + 800b06c: 200003c1 .word 0x200003c1 + 800b070: 080168d8 .word 0x080168d8 + 800b074: 080168ec .word 0x080168ec + 800b078: 08016904 .word 0x08016904 + 800b07c: 0801691c .word 0x0801691c + 800b080: 08016934 .word 0x08016934 + 800b084: 08016950 .word 0x08016950 + 800b088: 08016970 .word 0x08016970 + 800b08c: 08016990 .word 0x08016990 + 800b090: 080169b0 .word 0x080169b0 + 800b094: 080169c8 .word 0x080169c8 + 800b098: 080169e0 .word 0x080169e0 + 800b09c: 080169f8 .word 0x080169f8 + 800b0a0: 08016a14 .word 0x08016a14 + 800b0a4: 08016a2c .word 0x08016a2c + 800b0a8: 200002e8 .word 0x200002e8 + +0800b0ac : + +void CONN_CC_ReadStateFiltered() { + 800b0ac: b580 push {r7, lr} + 800b0ae: b082 sub sp, #8 + 800b0b0: af00 add r7, sp, #0 + static uint32_t last_change_time = 0; + static uint32_t last_check_time = 0; + static uint8_t prev_state = 0; + + if((HAL_GetTick()-last_check_time)<100) return; + 800b0b2: f003 fb8d bl 800e7d0 + 800b0b6: 4602 mov r2, r0 + 800b0b8: 4b16 ldr r3, [pc, #88] @ (800b114 ) + 800b0ba: 681b ldr r3, [r3, #0] + 800b0bc: 1ad3 subs r3, r2, r3 + 800b0be: 2b63 cmp r3, #99 @ 0x63 + 800b0c0: d924 bls.n 800b10c + + last_check_time = HAL_GetTick(); + 800b0c2: f003 fb85 bl 800e7d0 + 800b0c6: 4603 mov r3, r0 + 800b0c8: 4a12 ldr r2, [pc, #72] @ (800b114 ) + 800b0ca: 6013 str r3, [r2, #0] + + uint8_t new_state = CONN_CC_GetStateRaw(); + 800b0cc: f000 f834 bl 800b138 + 800b0d0: 4603 mov r3, r0 + 800b0d2: 71fb strb r3, [r7, #7] + + if (new_state != prev_state) { + 800b0d4: 4b10 ldr r3, [pc, #64] @ (800b118 ) + 800b0d6: 781b ldrb r3, [r3, #0] + 800b0d8: 79fa ldrb r2, [r7, #7] + 800b0da: 429a cmp r2, r3 + 800b0dc: d008 beq.n 800b0f0 + last_change_time = HAL_GetTick(); + 800b0de: f003 fb77 bl 800e7d0 + 800b0e2: 4603 mov r3, r0 + 800b0e4: 4a0d ldr r2, [pc, #52] @ (800b11c ) + 800b0e6: 6013 str r3, [r2, #0] + prev_state = new_state; + 800b0e8: 4a0b ldr r2, [pc, #44] @ (800b118 ) + 800b0ea: 79fb ldrb r3, [r7, #7] + 800b0ec: 7013 strb r3, [r2, #0] + 800b0ee: e00e b.n 800b10e + } else if ((HAL_GetTick() - last_change_time) >= 300) { + 800b0f0: f003 fb6e bl 800e7d0 + 800b0f4: 4602 mov r2, r0 + 800b0f6: 4b09 ldr r3, [pc, #36] @ (800b11c ) + 800b0f8: 681b ldr r3, [r3, #0] + 800b0fa: 1ad3 subs r3, r2, r3 + 800b0fc: f5b3 7f96 cmp.w r3, #300 @ 0x12c + 800b100: d305 bcc.n 800b10e + CC_STATE_FILTERED = prev_state; + 800b102: 4b05 ldr r3, [pc, #20] @ (800b118 ) + 800b104: 781a ldrb r2, [r3, #0] + 800b106: 4b06 ldr r3, [pc, #24] @ (800b120 ) + 800b108: 701a strb r2, [r3, #0] + 800b10a: e000 b.n 800b10e + if((HAL_GetTick()-last_check_time)<100) return; + 800b10c: bf00 nop + } +} + 800b10e: 3708 adds r7, #8 + 800b110: 46bd mov sp, r7 + 800b112: bd80 pop {r7, pc} + 800b114: 200003c4 .word 0x200003c4 + 800b118: 200003c8 .word 0x200003c8 + 800b11c: 200003cc .word 0x200003cc + 800b120: 200003c2 .word 0x200003c2 + +0800b124 : + +uint8_t CONN_CC_GetState(){ + 800b124: b480 push {r7} + 800b126: af00 add r7, sp, #0 + return CC_STATE_FILTERED; + 800b128: 4b02 ldr r3, [pc, #8] @ (800b134 ) + 800b12a: 781b ldrb r3, [r3, #0] +} + 800b12c: 4618 mov r0, r3 + 800b12e: 46bd mov sp, r7 + 800b130: bc80 pop {r7} + 800b132: 4770 bx lr + 800b134: 200003c2 .word 0x200003c2 + +0800b138 : +uint8_t CONN_CC_GetStateRaw(){ + 800b138: b580 push {r7, lr} + 800b13a: b082 sub sp, #8 + 800b13c: af00 add r7, sp, #0 + float volt = CONN_CC_GetAdc(); + 800b13e: f000 f851 bl 800b1e4 + 800b142: 6078 str r0, [r7, #4] +// if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; +// if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; +// if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; +// if((volt<2.8f) && (volt>1.2f)) return GBT_CC_2V; + if((volt<13.0f) && (volt>11.0f)) return GBT_CC_12V; + 800b144: 4922 ldr r1, [pc, #136] @ (800b1d0 ) + 800b146: 6878 ldr r0, [r7, #4] + 800b148: f7fe f806 bl 8009158 <__aeabi_fcmplt> + 800b14c: 4603 mov r3, r0 + 800b14e: 2b00 cmp r3, #0 + 800b150: d008 beq.n 800b164 + 800b152: 4920 ldr r1, [pc, #128] @ (800b1d4 ) + 800b154: 6878 ldr r0, [r7, #4] + 800b156: f7fe f81d bl 8009194 <__aeabi_fcmpgt> + 800b15a: 4603 mov r3, r0 + 800b15c: 2b00 cmp r3, #0 + 800b15e: d001 beq.n 800b164 + 800b160: 2301 movs r3, #1 + 800b162: e031 b.n 800b1c8 + if((volt<7.2f) && (volt>4.8f)) return GBT_CC_6V; + 800b164: 491c ldr r1, [pc, #112] @ (800b1d8 ) + 800b166: 6878 ldr r0, [r7, #4] + 800b168: f7fd fff6 bl 8009158 <__aeabi_fcmplt> + 800b16c: 4603 mov r3, r0 + 800b16e: 2b00 cmp r3, #0 + 800b170: d008 beq.n 800b184 + 800b172: 491a ldr r1, [pc, #104] @ (800b1dc ) + 800b174: 6878 ldr r0, [r7, #4] + 800b176: f7fe f80d bl 8009194 <__aeabi_fcmpgt> + 800b17a: 4603 mov r3, r0 + 800b17c: 2b00 cmp r3, #0 + 800b17e: d001 beq.n 800b184 + 800b180: 2302 movs r3, #2 + 800b182: e021 b.n 800b1c8 + if((volt<4.8f) && (volt>3.0f)) return GBT_CC_4V; + 800b184: 4915 ldr r1, [pc, #84] @ (800b1dc ) + 800b186: 6878 ldr r0, [r7, #4] + 800b188: f7fd ffe6 bl 8009158 <__aeabi_fcmplt> + 800b18c: 4603 mov r3, r0 + 800b18e: 2b00 cmp r3, #0 + 800b190: d008 beq.n 800b1a4 + 800b192: 4913 ldr r1, [pc, #76] @ (800b1e0 ) + 800b194: 6878 ldr r0, [r7, #4] + 800b196: f7fd fffd bl 8009194 <__aeabi_fcmpgt> + 800b19a: 4603 mov r3, r0 + 800b19c: 2b00 cmp r3, #0 + 800b19e: d001 beq.n 800b1a4 + 800b1a0: 2303 movs r3, #3 + 800b1a2: e011 b.n 800b1c8 + if((volt<3.0f) && (volt>1.0f)) return GBT_CC_2V; + 800b1a4: 490e ldr r1, [pc, #56] @ (800b1e0 ) + 800b1a6: 6878 ldr r0, [r7, #4] + 800b1a8: f7fd ffd6 bl 8009158 <__aeabi_fcmplt> + 800b1ac: 4603 mov r3, r0 + 800b1ae: 2b00 cmp r3, #0 + 800b1b0: d009 beq.n 800b1c6 + 800b1b2: f04f 517e mov.w r1, #1065353216 @ 0x3f800000 + 800b1b6: 6878 ldr r0, [r7, #4] + 800b1b8: f7fd ffec bl 8009194 <__aeabi_fcmpgt> + 800b1bc: 4603 mov r3, r0 + 800b1be: 2b00 cmp r3, #0 + 800b1c0: d001 beq.n 800b1c6 + 800b1c2: 2304 movs r3, #4 + 800b1c4: e000 b.n 800b1c8 + return GBT_CC_UNKNOWN; + 800b1c6: 2300 movs r3, #0 +} + 800b1c8: 4618 mov r0, r3 + 800b1ca: 3708 adds r7, #8 + 800b1cc: 46bd mov sp, r7 + 800b1ce: bd80 pop {r7, pc} + 800b1d0: 41500000 .word 0x41500000 + 800b1d4: 41300000 .word 0x41300000 + 800b1d8: 40e66666 .word 0x40e66666 + 800b1dc: 4099999a .word 0x4099999a + 800b1e0: 40400000 .word 0x40400000 + +0800b1e4 : + +float CONN_CC_GetAdc(){ + 800b1e4: b580 push {r7, lr} + 800b1e6: b082 sub sp, #8 + 800b1e8: af00 add r7, sp, #0 + //Vin*k= 1.09v + //12vin = 1353 ADC + + uint32_t adc; + float volt; + ADC_Select_Channel(ADC_CHANNEL_3); + 800b1ea: 2003 movs r0, #3 + 800b1ec: f7fe fc1c bl 8009a28 + HAL_ADC_Start(&hadc1); + 800b1f0: 480e ldr r0, [pc, #56] @ (800b22c ) + 800b1f2: f003 fbf3 bl 800e9dc + HAL_ADC_PollForConversion(&hadc1, 100); + 800b1f6: 2164 movs r1, #100 @ 0x64 + 800b1f8: 480c ldr r0, [pc, #48] @ (800b22c ) + 800b1fa: f003 fcc9 bl 800eb90 + adc = HAL_ADC_GetValue(&hadc1); + 800b1fe: 480b ldr r0, [pc, #44] @ (800b22c ) + 800b200: f003 fdcc bl 800ed9c + 800b204: 6078 str r0, [r7, #4] + HAL_ADC_Stop(&hadc1); + 800b206: 4809 ldr r0, [pc, #36] @ (800b22c ) + 800b208: f003 fc96 bl 800eb38 + + volt = (float)adc/113.4f; + 800b20c: 6878 ldr r0, [r7, #4] + 800b20e: f7fd fdad bl 8008d6c <__aeabi_ui2f> + 800b212: 4603 mov r3, r0 + 800b214: 4906 ldr r1, [pc, #24] @ (800b230 ) + 800b216: 4618 mov r0, r3 + 800b218: f7fd feb4 bl 8008f84 <__aeabi_fdiv> + 800b21c: 4603 mov r3, r0 + 800b21e: 603b str r3, [r7, #0] + + return volt; + 800b220: 683b ldr r3, [r7, #0] +} + 800b222: 4618 mov r0, r3 + 800b224: 3708 adds r7, #8 + 800b226: 46bd mov sp, r7 + 800b228: bd80 pop {r7, pc} + 800b22a: bf00 nop + 800b22c: 2000025c .word 0x2000025c + 800b230: 42e2cccd .word 0x42e2cccd + +0800b234 : + +CRC_HandleTypeDef hcrc; + +/* CRC init function */ +void MX_CRC_Init(void) +{ + 800b234: b580 push {r7, lr} + 800b236: af00 add r7, sp, #0 + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + 800b238: 4b06 ldr r3, [pc, #24] @ (800b254 ) + 800b23a: 4a07 ldr r2, [pc, #28] @ (800b258 ) + 800b23c: 601a str r2, [r3, #0] + if (HAL_CRC_Init(&hcrc) != HAL_OK) + 800b23e: 4805 ldr r0, [pc, #20] @ (800b254 ) + 800b240: f004 ffd3 bl 80101ea + 800b244: 4603 mov r3, r0 + 800b246: 2b00 cmp r3, #0 + 800b248: d001 beq.n 800b24e + { + Error_Handler(); + 800b24a: f001 f84d bl 800c2e8 + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + 800b24e: bf00 nop + 800b250: bd80 pop {r7, pc} + 800b252: bf00 nop + 800b254: 200003d0 .word 0x200003d0 + 800b258: 40023000 .word 0x40023000 + +0800b25c : + +void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) +{ + 800b25c: b480 push {r7} + 800b25e: b085 sub sp, #20 + 800b260: af00 add r7, sp, #0 + 800b262: 6078 str r0, [r7, #4] + + if(crcHandle->Instance==CRC) + 800b264: 687b ldr r3, [r7, #4] + 800b266: 681b ldr r3, [r3, #0] + 800b268: 4a09 ldr r2, [pc, #36] @ (800b290 ) + 800b26a: 4293 cmp r3, r2 + 800b26c: d10b bne.n 800b286 + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* CRC clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + 800b26e: 4b09 ldr r3, [pc, #36] @ (800b294 ) + 800b270: 695b ldr r3, [r3, #20] + 800b272: 4a08 ldr r2, [pc, #32] @ (800b294 ) + 800b274: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800b278: 6153 str r3, [r2, #20] + 800b27a: 4b06 ldr r3, [pc, #24] @ (800b294 ) + 800b27c: 695b ldr r3, [r3, #20] + 800b27e: f003 0340 and.w r3, r3, #64 @ 0x40 + 800b282: 60fb str r3, [r7, #12] + 800b284: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } +} + 800b286: bf00 nop + 800b288: 3714 adds r7, #20 + 800b28a: 46bd mov sp, r7 + 800b28c: bc80 pop {r7} + 800b28e: 4770 bx lr + 800b290: 40023000 .word 0x40023000 + 800b294: 40021000 .word 0x40021000 + +0800b298 <_write>: + + + +#if defined(__GNUC__) +int _write(int fd, char * ptr, int len) +{ + 800b298: b580 push {r7, lr} + 800b29a: b084 sub sp, #16 + 800b29c: af00 add r7, sp, #0 + 800b29e: 60f8 str r0, [r7, #12] + 800b2a0: 60b9 str r1, [r7, #8] + 800b2a2: 607a str r2, [r7, #4] + debug_buffer_add((const uint8_t*)ptr, len); + 800b2a4: 687b ldr r3, [r7, #4] + 800b2a6: b29b uxth r3, r3 + 800b2a8: 4619 mov r1, r3 + 800b2aa: 68b8 ldr r0, [r7, #8] + 800b2ac: f000 f806 bl 800b2bc + return len; + 800b2b0: 687b ldr r3, [r7, #4] +} + 800b2b2: 4618 mov r0, r3 + 800b2b4: 3710 adds r7, #16 + 800b2b6: 46bd mov sp, r7 + 800b2b8: bd80 pop {r7, pc} + ... + +0800b2bc : +#endif + +// Добавляет данные в кольцевой буфер +void debug_buffer_add(const uint8_t* data, uint16_t len) +{ + 800b2bc: b480 push {r7} + 800b2be: b085 sub sp, #20 + 800b2c0: af00 add r7, sp, #0 + 800b2c2: 6078 str r0, [r7, #4] + 800b2c4: 460b mov r3, r1 + 800b2c6: 807b strh r3, [r7, #2] + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800b2c8: b672 cpsid i +} + 800b2ca: bf00 nop + __disable_irq(); + + for (uint16_t i = 0; i < len; i++) { + 800b2cc: 2300 movs r3, #0 + 800b2ce: 81fb strh r3, [r7, #14] + 800b2d0: e045 b.n 800b35e + // Если буфер полон, перезаписываем старые данные + if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { + 800b2d2: 4b28 ldr r3, [pc, #160] @ (800b374 ) + 800b2d4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b2d8: b29b uxth r3, r3 + 800b2da: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 800b2de: d318 bcc.n 800b312 + debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; + 800b2e0: 4b24 ldr r3, [pc, #144] @ (800b374 ) + 800b2e2: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 + 800b2e6: b29b uxth r3, r3 + 800b2e8: 3301 adds r3, #1 + 800b2ea: 425a negs r2, r3 + 800b2ec: f3c3 0309 ubfx r3, r3, #0, #10 + 800b2f0: f3c2 0209 ubfx r2, r2, #0, #10 + 800b2f4: bf58 it pl + 800b2f6: 4253 negpl r3, r2 + 800b2f8: b29a uxth r2, r3 + 800b2fa: 4b1e ldr r3, [pc, #120] @ (800b374 ) + 800b2fc: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 + debug_buffer.count--; + 800b300: 4b1c ldr r3, [pc, #112] @ (800b374 ) + 800b302: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b306: b29b uxth r3, r3 + 800b308: 3b01 subs r3, #1 + 800b30a: b29a uxth r2, r3 + 800b30c: 4b19 ldr r3, [pc, #100] @ (800b374 ) + 800b30e: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 + } + + debug_buffer.buffer[debug_buffer.write_index] = data[i]; + 800b312: 89fb ldrh r3, [r7, #14] + 800b314: 687a ldr r2, [r7, #4] + 800b316: 4413 add r3, r2 + 800b318: 4a16 ldr r2, [pc, #88] @ (800b374 ) + 800b31a: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 + 800b31e: b292 uxth r2, r2 + 800b320: 7819 ldrb r1, [r3, #0] + 800b322: 4b14 ldr r3, [pc, #80] @ (800b374 ) + 800b324: 5499 strb r1, [r3, r2] + debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; + 800b326: 4b13 ldr r3, [pc, #76] @ (800b374 ) + 800b328: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 + 800b32c: b29b uxth r3, r3 + 800b32e: 3301 adds r3, #1 + 800b330: 425a negs r2, r3 + 800b332: f3c3 0309 ubfx r3, r3, #0, #10 + 800b336: f3c2 0209 ubfx r2, r2, #0, #10 + 800b33a: bf58 it pl + 800b33c: 4253 negpl r3, r2 + 800b33e: b29a uxth r2, r3 + 800b340: 4b0c ldr r3, [pc, #48] @ (800b374 ) + 800b342: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 + debug_buffer.count++; + 800b346: 4b0b ldr r3, [pc, #44] @ (800b374 ) + 800b348: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b34c: b29b uxth r3, r3 + 800b34e: 3301 adds r3, #1 + 800b350: b29a uxth r2, r3 + 800b352: 4b08 ldr r3, [pc, #32] @ (800b374 ) + 800b354: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 + for (uint16_t i = 0; i < len; i++) { + 800b358: 89fb ldrh r3, [r7, #14] + 800b35a: 3301 adds r3, #1 + 800b35c: 81fb strh r3, [r7, #14] + 800b35e: 89fa ldrh r2, [r7, #14] + 800b360: 887b ldrh r3, [r7, #2] + 800b362: 429a cmp r2, r3 + 800b364: d3b5 bcc.n 800b2d2 + __ASM volatile ("cpsie i" : : : "memory"); + 800b366: b662 cpsie i +} + 800b368: bf00 nop + } + + __enable_irq(); +} + 800b36a: bf00 nop + 800b36c: 3714 adds r7, #20 + 800b36e: 46bd mov sp, r7 + 800b370: bc80 pop {r7} + 800b372: 4770 bx lr + 800b374: 200003d8 .word 0x200003d8 + +0800b378 : + +// Возвращает количество доступных данных в буфере +uint16_t debug_buffer_available(void) +{ + 800b378: b480 push {r7} + 800b37a: b083 sub sp, #12 + 800b37c: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 800b37e: b672 cpsid i +} + 800b380: bf00 nop + __disable_irq(); + uint16_t count = debug_buffer.count; + 800b382: 4b06 ldr r3, [pc, #24] @ (800b39c ) + 800b384: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b388: 80fb strh r3, [r7, #6] + __ASM volatile ("cpsie i" : : : "memory"); + 800b38a: b662 cpsie i +} + 800b38c: bf00 nop + __enable_irq(); + return count; + 800b38e: 88fb ldrh r3, [r7, #6] +} + 800b390: 4618 mov r0, r3 + 800b392: 370c adds r7, #12 + 800b394: 46bd mov sp, r7 + 800b396: bc80 pop {r7} + 800b398: 4770 bx lr + 800b39a: bf00 nop + 800b39c: 200003d8 .word 0x200003d8 + +0800b3a0 : + +// Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) +void debug_buffer_send(void) +{ + 800b3a0: b580 push {r7, lr} + 800b3a2: b082 sub sp, #8 + 800b3a4: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 800b3a6: b672 cpsid i +} + 800b3a8: bf00 nop + __disable_irq(); + + // Если буфер пуст, ничего не делаем + if (debug_buffer.count == 0) { + 800b3aa: 4b2d ldr r3, [pc, #180] @ (800b460 ) + 800b3ac: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b3b0: b29b uxth r3, r3 + 800b3b2: 2b00 cmp r3, #0 + 800b3b4: d102 bne.n 800b3bc + __ASM volatile ("cpsie i" : : : "memory"); + 800b3b6: b662 cpsie i +} + 800b3b8: bf00 nop + __enable_irq(); + return; + 800b3ba: e04e b.n 800b45a + } + + // Определяем сколько байт можно отправить (не более 250) + uint16_t bytes_to_send = debug_buffer.count; + 800b3bc: 4b28 ldr r3, [pc, #160] @ (800b460 ) + 800b3be: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b3c2: 80fb strh r3, [r7, #6] + if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { + 800b3c4: 88fb ldrh r3, [r7, #6] + 800b3c6: 2b80 cmp r3, #128 @ 0x80 + 800b3c8: d901 bls.n 800b3ce + bytes_to_send = DEBUG_BUFFER_MAX_COUNT; + 800b3ca: 2380 movs r3, #128 @ 0x80 + 800b3cc: 80fb strh r3, [r7, #6] + } + + // Вычисляем сколько байт до конца буфера + uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; + 800b3ce: 4b24 ldr r3, [pc, #144] @ (800b460 ) + 800b3d0: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 + 800b3d4: b29b uxth r3, r3 + 800b3d6: f5c3 6380 rsb r3, r3, #1024 @ 0x400 + 800b3da: 80bb strh r3, [r7, #4] + + // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) + if (bytes_to_send > bytes_to_end) { + 800b3dc: 88fa ldrh r2, [r7, #6] + 800b3de: 88bb ldrh r3, [r7, #4] + 800b3e0: 429a cmp r2, r3 + 800b3e2: d901 bls.n 800b3e8 + bytes_to_send = bytes_to_end; + 800b3e4: 88bb ldrh r3, [r7, #4] + 800b3e6: 80fb strh r3, [r7, #6] + } + + // Отправляем данные напрямую из буфера + if(bytes_to_send == debug_buffer.count){ + 800b3e8: 4b1d ldr r3, [pc, #116] @ (800b460 ) + 800b3ea: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b3ee: b29b uxth r3, r3 + 800b3f0: 88fa ldrh r2, [r7, #6] + 800b3f2: 429a cmp r2, r3 + 800b3f4: d10c bne.n 800b410 + SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); + 800b3f6: 4b1a ldr r3, [pc, #104] @ (800b460 ) + 800b3f8: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 + 800b3fc: b29b uxth r3, r3 + 800b3fe: 461a mov r2, r3 + 800b400: 4b17 ldr r3, [pc, #92] @ (800b460 ) + 800b402: 4413 add r3, r2 + 800b404: 88f9 ldrh r1, [r7, #6] + 800b406: 2250 movs r2, #80 @ 0x50 + 800b408: 4618 mov r0, r3 + 800b40a: f002 f91b bl 800d644 + 800b40e: e00b b.n 800b428 + }else{ + SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); + 800b410: 4b13 ldr r3, [pc, #76] @ (800b460 ) + 800b412: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 + 800b416: b29b uxth r3, r3 + 800b418: 461a mov r2, r3 + 800b41a: 4b11 ldr r3, [pc, #68] @ (800b460 ) + 800b41c: 4413 add r3, r2 + 800b41e: 88f9 ldrh r1, [r7, #6] + 800b420: 2251 movs r2, #81 @ 0x51 + 800b422: 4618 mov r0, r3 + 800b424: f002 f90e bl 800d644 + } + debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; + 800b428: 4b0d ldr r3, [pc, #52] @ (800b460 ) + 800b42a: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 + 800b42e: b29a uxth r2, r3 + 800b430: 88fb ldrh r3, [r7, #6] + 800b432: 4413 add r3, r2 + 800b434: b29b uxth r3, r3 + 800b436: f3c3 0309 ubfx r3, r3, #0, #10 + 800b43a: b29a uxth r2, r3 + 800b43c: 4b08 ldr r3, [pc, #32] @ (800b460 ) + 800b43e: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 + debug_buffer.count -= bytes_to_send; + 800b442: 4b07 ldr r3, [pc, #28] @ (800b460 ) + 800b444: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 + 800b448: b29a uxth r2, r3 + 800b44a: 88fb ldrh r3, [r7, #6] + 800b44c: 1ad3 subs r3, r2, r3 + 800b44e: b29a uxth r2, r3 + 800b450: 4b03 ldr r3, [pc, #12] @ (800b460 ) + 800b452: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 + __ASM volatile ("cpsie i" : : : "memory"); + 800b456: b662 cpsie i +} + 800b458: bf00 nop + + __enable_irq(); +} + 800b45a: 3708 adds r7, #8 + 800b45c: 46bd mov sp, r7 + 800b45e: bd80 pop {r7, pc} + 800b460: 200003d8 .word 0x200003d8 + +0800b464 : +#define LOG_BUFFER_SIZE 128 +uint8_t log_buffer[LOG_BUFFER_SIZE]; + +// Кастомный printf с приоритетом лога +int log_printf(LogLevel_t level, const char *format, ...) +{ + 800b464: b40e push {r1, r2, r3} + 800b466: b580 push {r7, lr} + 800b468: b085 sub sp, #20 + 800b46a: af00 add r7, sp, #0 + 800b46c: 4603 mov r3, r0 + 800b46e: 71fb strb r3, [r7, #7] + va_list args; + int result; + + // Добавляем приоритет первым байтом + log_buffer[0] = (uint8_t)level; + 800b470: 4a15 ldr r2, [pc, #84] @ (800b4c8 ) + 800b472: 79fb ldrb r3, [r7, #7] + 800b474: 7013 strb r3, [r2, #0] + + // Форматируем строку начиная со второго байта + va_start(args, format); + 800b476: f107 0320 add.w r3, r7, #32 + 800b47a: 60bb str r3, [r7, #8] + result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); + 800b47c: 68bb ldr r3, [r7, #8] + 800b47e: 69fa ldr r2, [r7, #28] + 800b480: 217e movs r1, #126 @ 0x7e + 800b482: 4812 ldr r0, [pc, #72] @ (800b4cc ) + 800b484: f008 fdc6 bl 8014014 + 800b488: 60f8 str r0, [r7, #12] + va_end(args); + + // Проверяем, не переполнился ли буфер + if (result < 0) { + 800b48a: 68fb ldr r3, [r7, #12] + 800b48c: 2b00 cmp r3, #0 + 800b48e: da01 bge.n 800b494 + return result; + 800b490: 68fb ldr r3, [r7, #12] + 800b492: e012 b.n 800b4ba + } + + // Ограничиваем размер, чтобы оставить место для нуль-терминатора + if (result >= (LOG_BUFFER_SIZE - 2)) { + 800b494: 68fb ldr r3, [r7, #12] + 800b496: 2b7d cmp r3, #125 @ 0x7d + 800b498: dd01 ble.n 800b49e + result = LOG_BUFFER_SIZE - 2; + 800b49a: 237e movs r3, #126 @ 0x7e + 800b49c: 60fb str r3, [r7, #12] + } + + // Добавляем нуль-терминатор в конец + log_buffer[result + 1] = '\0'; + 800b49e: 68fb ldr r3, [r7, #12] + 800b4a0: 3301 adds r3, #1 + 800b4a2: 4a09 ldr r2, [pc, #36] @ (800b4c8 ) + 800b4a4: 2100 movs r1, #0 + 800b4a6: 54d1 strb r1, [r2, r3] + + // Отправляем в буфер (приоритет + строка + нуль-терминатор) + debug_buffer_add(log_buffer, result + 2); + 800b4a8: 68fb ldr r3, [r7, #12] + 800b4aa: b29b uxth r3, r3 + 800b4ac: 3302 adds r3, #2 + 800b4ae: b29b uxth r3, r3 + 800b4b0: 4619 mov r1, r3 + 800b4b2: 4805 ldr r0, [pc, #20] @ (800b4c8 ) + 800b4b4: f7ff ff02 bl 800b2bc + + return result; + 800b4b8: 68fb ldr r3, [r7, #12] +} + 800b4ba: 4618 mov r0, r3 + 800b4bc: 3714 adds r7, #20 + 800b4be: 46bd mov sp, r7 + 800b4c0: e8bd 4080 ldmia.w sp!, {r7, lr} + 800b4c4: b003 add sp, #12 + 800b4c6: 4770 bx lr + 800b4c8: 200007e0 .word 0x200007e0 + 800b4cc: 200007e1 .word 0x200007e1 + +0800b4d0 : +// GB/T Time Synchronization Packet +#include "main.h" +#include "soft_rtc.h" +#include "charger_gbt.h" + +void GBT_SendCTS(){ + 800b4d0: b580 push {r7, lr} + 800b4d2: b082 sub sp, #8 + 800b4d4: af00 add r7, sp, #0 + + uint8_t data[7]; + unix_to_bcd(get_Current_Time(), data); + 800b4d6: f002 fb89 bl 800dbec + 800b4da: 4602 mov r2, r0 + 800b4dc: 463b mov r3, r7 + 800b4de: 4619 mov r1, r3 + 800b4e0: 4610 mov r0, r2 + 800b4e2: f002 fbc1 bl 800dc68 +// data[3] = 0x05; //days +// data[4] = 0x05; //month +// data[5] = 0x24; //years +// data[6] = 0x20; //centuries + + J_SendPacket(0x000700, 6, 7, data); + 800b4e6: 463b mov r3, r7 + 800b4e8: 2207 movs r2, #7 + 800b4ea: 2106 movs r1, #6 + 800b4ec: f44f 60e0 mov.w r0, #1792 @ 0x700 + 800b4f0: f000 fb60 bl 800bbb4 +} + 800b4f4: bf00 nop + 800b4f6: 3708 adds r7, #8 + 800b4f8: 46bd mov sp, r7 + 800b4fa: bd80 pop {r7, pc} + +0800b4fc : + +//GB/T Max Load Packet +void GBT_SendCML(){ + 800b4fc: b580 push {r7, lr} + 800b4fe: af00 add r7, sp, #0 +// data[4] = 0xC4; //-150A maximum output current +// data[5] = 0x09; // +// data[6] = 0x8C; //-2A minimum output current +// data[7] = 0x0F; // + + J_SendPacket(0x000800, 6, 8, (uint8_t*)&GBT_MaxLoad); + 800b500: 4b04 ldr r3, [pc, #16] @ (800b514 ) + 800b502: 2208 movs r2, #8 + 800b504: 2106 movs r1, #6 + 800b506: f44f 6000 mov.w r0, #2048 @ 0x800 + 800b50a: f000 fb53 bl 800bbb4 + +} + 800b50e: bf00 nop + 800b510: bd80 pop {r7, pc} + 800b512: bf00 nop + 800b514: 20000320 .word 0x20000320 + +0800b518 : + +//GB/T Version packet +void GBT_SendCHM(){ + 800b518: b580 push {r7, lr} + 800b51a: b082 sub sp, #8 + 800b51c: af00 add r7, sp, #0 + uint8_t data[3]; + data[0] = 0x01; + 800b51e: 2301 movs r3, #1 + 800b520: 713b strb r3, [r7, #4] + data[1] = 0x01; + 800b522: 2301 movs r3, #1 + 800b524: 717b strb r3, [r7, #5] + data[2] = 0x00; + 800b526: 2300 movs r3, #0 + 800b528: 71bb strb r3, [r7, #6] + J_SendPacket(0x2600, 6, 3, data); + 800b52a: 1d3b adds r3, r7, #4 + 800b52c: 2203 movs r2, #3 + 800b52e: 2106 movs r1, #6 + 800b530: f44f 5018 mov.w r0, #9728 @ 0x2600 + 800b534: f000 fb3e bl 800bbb4 +} + 800b538: bf00 nop + 800b53a: 3708 adds r7, #8 + 800b53c: 46bd mov sp, r7 + 800b53e: bd80 pop {r7, pc} + +0800b540 : + +//GB/T CRM Packet (state=BMS identified) +void GBT_SendCRM(uint8_t state){ + 800b540: b580 push {r7, lr} + 800b542: b082 sub sp, #8 + 800b544: af00 add r7, sp, #0 + 800b546: 4603 mov r3, r0 + 800b548: 71fb strb r3, [r7, #7] +// data[3] = 0x01; +// data[4] = 0x00; +// data[5] = 0x42; //TODO: location BFG +// data[6] = 0x46; +// data[7] = 0x47; + GBT_ChargerInfo.bmsIdentified = state; + 800b54a: 4a07 ldr r2, [pc, #28] @ (800b568 ) + 800b54c: 79fb ldrb r3, [r7, #7] + 800b54e: 7013 strb r3, [r2, #0] + J_SendPacket(0x100, 6, 8, (uint8_t *)&GBT_ChargerInfo); + 800b550: 4b05 ldr r3, [pc, #20] @ (800b568 ) + 800b552: 2208 movs r2, #8 + 800b554: 2106 movs r1, #6 + 800b556: f44f 7080 mov.w r0, #256 @ 0x100 + 800b55a: f000 fb2b bl 800bbb4 +} + 800b55e: bf00 nop + 800b560: 3708 adds r7, #8 + 800b562: 46bd mov sp, r7 + 800b564: bd80 pop {r7, pc} + 800b566: bf00 nop + 800b568: 20000328 .word 0x20000328 + +0800b56c : + +//GB/T CRO packet (Charger ready) +void GBT_SendCRO(uint8_t state){ + 800b56c: b580 push {r7, lr} + 800b56e: b084 sub sp, #16 + 800b570: af00 add r7, sp, #0 + 800b572: 4603 mov r3, r0 + 800b574: 71fb strb r3, [r7, #7] + uint8_t data[1]; + data[0] = state; + 800b576: 79fb ldrb r3, [r7, #7] + 800b578: 733b strb r3, [r7, #12] + J_SendPacket(0xA00, 4, 1, data); + 800b57a: f107 030c add.w r3, r7, #12 + 800b57e: 2201 movs r2, #1 + 800b580: 2104 movs r1, #4 + 800b582: f44f 6020 mov.w r0, #2560 @ 0xa00 + 800b586: f000 fb15 bl 800bbb4 +} + 800b58a: bf00 nop + 800b58c: 3710 adds r7, #16 + 800b58e: 46bd mov sp, r7 + 800b590: bd80 pop {r7, pc} + ... + +0800b594 : + +//GB/T CCS packet (Charger current status) +void GBT_SendCCS(){ + 800b594: b580 push {r7, lr} + 800b596: af00 add r7, sp, #0 +// data[3] = GBT_CurrPower.requestedCurrent>>8; //TODO: current +// data[4] = GBT_StateTick()/60000; //charging time (min) +// data[5] = 0; //TODO: 255 min+ +// data[6] = 0b11111101; //charging not permitted +// data[7] = 0xFF; + J_SendPacket(0x1200, 6, 8, (uint8_t *)&GBT_ChargerCurrentStatus); + 800b598: 4b04 ldr r3, [pc, #16] @ (800b5ac ) + 800b59a: 2208 movs r2, #8 + 800b59c: 2106 movs r1, #6 + 800b59e: f44f 5090 mov.w r0, #4608 @ 0x1200 + 800b5a2: f000 fb07 bl 800bbb4 +} + 800b5a6: bf00 nop + 800b5a8: bd80 pop {r7, pc} + 800b5aa: bf00 nop + 800b5ac: 2000039c .word 0x2000039c + +0800b5b0 : + +// GB/T Charging Stop packet +void GBT_SendCST(uint32_t Cause){ + 800b5b0: b580 push {r7, lr} + 800b5b2: b084 sub sp, #16 + 800b5b4: af00 add r7, sp, #0 + 800b5b6: 6078 str r0, [r7, #4] + uint8_t data[8]; + data[0] = (Cause>>24) & 0xFF; // Error + 800b5b8: 687b ldr r3, [r7, #4] + 800b5ba: 0e1b lsrs r3, r3, #24 + 800b5bc: b2db uxtb r3, r3 + 800b5be: 723b strb r3, [r7, #8] + data[1] = (Cause>>16) & 0xFF; // + 800b5c0: 687b ldr r3, [r7, #4] + 800b5c2: 0c1b lsrs r3, r3, #16 + 800b5c4: b2db uxtb r3, r3 + 800b5c6: 727b strb r3, [r7, #9] + data[2] = (Cause>>8) & 0xFF; // + 800b5c8: 687b ldr r3, [r7, #4] + 800b5ca: 0a1b lsrs r3, r3, #8 + 800b5cc: b2db uxtb r3, r3 + 800b5ce: 72bb strb r3, [r7, #10] + data[3] = Cause & 0xFF; // + 800b5d0: 687b ldr r3, [r7, #4] + 800b5d2: b2db uxtb r3, r3 + 800b5d4: 72fb strb r3, [r7, #11] + + J_SendPacket(0x1A00, 4, 4, data); + 800b5d6: f107 0308 add.w r3, r7, #8 + 800b5da: 2204 movs r2, #4 + 800b5dc: 2104 movs r1, #4 + 800b5de: f44f 50d0 mov.w r0, #6656 @ 0x1a00 + 800b5e2: f000 fae7 bl 800bbb4 +} + 800b5e6: bf00 nop + 800b5e8: 3710 adds r7, #16 + 800b5ea: 46bd mov sp, r7 + 800b5ec: bd80 pop {r7, pc} + ... + +0800b5f0 : + +void GBT_SendCSD(){ + 800b5f0: b580 push {r7, lr} + 800b5f2: af00 add r7, sp, #0 + GBT_ChargerStop.chargerNumber = GBT_ChargerInfo.chargerNumber; + 800b5f4: 4b0b ldr r3, [pc, #44] @ (800b624 ) + 800b5f6: f8d3 3001 ldr.w r3, [r3, #1] + 800b5fa: 4a0b ldr r2, [pc, #44] @ (800b628 ) + 800b5fc: 6053 str r3, [r2, #4] + GBT_ChargerStop.outputEnergy = 0; //TODO Energy meters + 800b5fe: 4b0a ldr r3, [pc, #40] @ (800b628 ) + 800b600: 2200 movs r2, #0 + 800b602: 709a strb r2, [r3, #2] + 800b604: 2200 movs r2, #0 + 800b606: 70da strb r2, [r3, #3] + GBT_ChargerStop.chargingTime = GBT_ChargerCurrentStatus.chargingTime; + 800b608: 4b08 ldr r3, [pc, #32] @ (800b62c ) + 800b60a: 889b ldrh r3, [r3, #4] + 800b60c: b29a uxth r2, r3 + 800b60e: 4b06 ldr r3, [pc, #24] @ (800b628 ) + 800b610: 801a strh r2, [r3, #0] + J_SendPacket(0x1D00, 6, 7, (uint8_t *)&GBT_ChargerStop); + 800b612: 4b05 ldr r3, [pc, #20] @ (800b628 ) + 800b614: 2207 movs r2, #7 + 800b616: 2106 movs r1, #6 + 800b618: f44f 50e8 mov.w r0, #7424 @ 0x1d00 + 800b61c: f000 faca bl 800bbb4 + +} + 800b620: bf00 nop + 800b622: bd80 pop {r7, pc} + 800b624: 20000328 .word 0x20000328 + 800b628: 200003a4 .word 0x200003a4 + 800b62c: 2000039c .word 0x2000039c + +0800b630 : + +void GBT_SendCEM(uint32_t ErrorCode){ + 800b630: b580 push {r7, lr} + 800b632: b084 sub sp, #16 + 800b634: af00 add r7, sp, #0 + 800b636: 6078 str r0, [r7, #4] + uint8_t data[8]; + data[0] = (ErrorCode>>24) & 0xFF; // Error + 800b638: 687b ldr r3, [r7, #4] + 800b63a: 0e1b lsrs r3, r3, #24 + 800b63c: b2db uxtb r3, r3 + 800b63e: 723b strb r3, [r7, #8] + data[1] = (ErrorCode>>16) & 0xFF; // + 800b640: 687b ldr r3, [r7, #4] + 800b642: 0c1b lsrs r3, r3, #16 + 800b644: b2db uxtb r3, r3 + 800b646: 727b strb r3, [r7, #9] + data[2] = (ErrorCode>>8) & 0xFF; // + 800b648: 687b ldr r3, [r7, #4] + 800b64a: 0a1b lsrs r3, r3, #8 + 800b64c: b2db uxtb r3, r3 + 800b64e: 72bb strb r3, [r7, #10] + data[3] = ErrorCode & 0xFF; // + 800b650: 687b ldr r3, [r7, #4] + 800b652: b2db uxtb r3, r3 + 800b654: 72fb strb r3, [r7, #11] + + J_SendPacket(0x1F00, 4, 4, data); + 800b656: f107 0308 add.w r3, r7, #8 + 800b65a: 2204 movs r2, #4 + 800b65c: 2104 movs r1, #4 + 800b65e: f44f 50f8 mov.w r0, #7936 @ 0x1f00 + 800b662: f000 faa7 bl 800bbb4 +} + 800b666: bf00 nop + 800b668: 3710 adds r7, #16 + 800b66a: 46bd mov sp, r7 + 800b66c: bd80 pop {r7, pc} + ... + +0800b670 : + * EXTI + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA +*/ +void MX_GPIO_Init(void) +{ + 800b670: b580 push {r7, lr} + 800b672: b08a sub sp, #40 @ 0x28 + 800b674: af00 add r7, sp, #0 + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800b676: f107 0314 add.w r3, r7, #20 + 800b67a: 2200 movs r2, #0 + 800b67c: 601a str r2, [r3, #0] + 800b67e: 605a str r2, [r3, #4] + 800b680: 609a str r2, [r3, #8] + 800b682: 60da str r2, [r3, #12] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800b684: 4b7d ldr r3, [pc, #500] @ (800b87c ) + 800b686: 699b ldr r3, [r3, #24] + 800b688: 4a7c ldr r2, [pc, #496] @ (800b87c ) + 800b68a: f043 0310 orr.w r3, r3, #16 + 800b68e: 6193 str r3, [r2, #24] + 800b690: 4b7a ldr r3, [pc, #488] @ (800b87c ) + 800b692: 699b ldr r3, [r3, #24] + 800b694: f003 0310 and.w r3, r3, #16 + 800b698: 613b str r3, [r7, #16] + 800b69a: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800b69c: 4b77 ldr r3, [pc, #476] @ (800b87c ) + 800b69e: 699b ldr r3, [r3, #24] + 800b6a0: 4a76 ldr r2, [pc, #472] @ (800b87c ) + 800b6a2: f043 0304 orr.w r3, r3, #4 + 800b6a6: 6193 str r3, [r2, #24] + 800b6a8: 4b74 ldr r3, [pc, #464] @ (800b87c ) + 800b6aa: 699b ldr r3, [r3, #24] + 800b6ac: f003 0304 and.w r3, r3, #4 + 800b6b0: 60fb str r3, [r7, #12] + 800b6b2: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800b6b4: 4b71 ldr r3, [pc, #452] @ (800b87c ) + 800b6b6: 699b ldr r3, [r3, #24] + 800b6b8: 4a70 ldr r2, [pc, #448] @ (800b87c ) + 800b6ba: f043 0308 orr.w r3, r3, #8 + 800b6be: 6193 str r3, [r2, #24] + 800b6c0: 4b6e ldr r3, [pc, #440] @ (800b87c ) + 800b6c2: 699b ldr r3, [r3, #24] + 800b6c4: f003 0308 and.w r3, r3, #8 + 800b6c8: 60bb str r3, [r7, #8] + 800b6ca: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 800b6cc: 4b6b ldr r3, [pc, #428] @ (800b87c ) + 800b6ce: 699b ldr r3, [r3, #24] + 800b6d0: 4a6a ldr r2, [pc, #424] @ (800b87c ) + 800b6d2: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800b6d6: 6193 str r3, [r2, #24] + 800b6d8: 4b68 ldr r3, [pc, #416] @ (800b87c ) + 800b6da: 699b ldr r3, [r3, #24] + 800b6dc: f003 0340 and.w r3, r3, #64 @ 0x40 + 800b6e0: 607b str r3, [r7, #4] + 800b6e2: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800b6e4: 4b65 ldr r3, [pc, #404] @ (800b87c ) + 800b6e6: 699b ldr r3, [r3, #24] + 800b6e8: 4a64 ldr r2, [pc, #400] @ (800b87c ) + 800b6ea: f043 0320 orr.w r3, r3, #32 + 800b6ee: 6193 str r3, [r2, #24] + 800b6f0: 4b62 ldr r3, [pc, #392] @ (800b87c ) + 800b6f2: 699b ldr r3, [r3, #24] + 800b6f4: f003 0320 and.w r3, r3, #32 + 800b6f8: 603b str r3, [r7, #0] + 800b6fa: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); + 800b6fc: 2200 movs r2, #0 + 800b6fe: 2130 movs r1, #48 @ 0x30 + 800b700: 485f ldr r0, [pc, #380] @ (800b880 ) + 800b702: f005 f86c bl 80107de + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin + 800b706: 2200 movs r2, #0 + 800b708: f44f 51f8 mov.w r1, #7936 @ 0x1f00 + 800b70c: 485d ldr r0, [pc, #372] @ (800b884 ) + 800b70e: f005 f866 bl 80107de + |RELAY5_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); + 800b712: 2200 movs r2, #0 + 800b714: f44f 4100 mov.w r1, #32768 @ 0x8000 + 800b718: 485b ldr r0, [pc, #364] @ (800b888 ) + 800b71a: f005 f860 bl 80107de + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); + 800b71e: 2200 movs r2, #0 + 800b720: 2118 movs r1, #24 + 800b722: 485a ldr r0, [pc, #360] @ (800b88c ) + 800b724: f005 f85b bl 80107de + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); + 800b728: 2200 movs r2, #0 + 800b72a: 2180 movs r1, #128 @ 0x80 + 800b72c: 4858 ldr r0, [pc, #352] @ (800b890 ) + 800b72e: f005 f856 bl 80107de + + /*Configure GPIO pin : IN_SW0_Pin */ + GPIO_InitStruct.Pin = IN_SW0_Pin; + 800b732: 2302 movs r3, #2 + 800b734: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800b736: 2300 movs r3, #0 + 800b738: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b73a: 2300 movs r3, #0 + 800b73c: 61fb str r3, [r7, #28] + HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); + 800b73e: f107 0314 add.w r3, r7, #20 + 800b742: 4619 mov r1, r3 + 800b744: 4850 ldr r0, [pc, #320] @ (800b888 ) + 800b746: f004 feaf bl 80104a8 + + /*Configure GPIO pin : IN_SW1_Pin */ + GPIO_InitStruct.Pin = IN_SW1_Pin; + 800b74a: 2304 movs r3, #4 + 800b74c: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800b74e: 2300 movs r3, #0 + 800b750: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 800b752: 2302 movs r3, #2 + 800b754: 61fb str r3, [r7, #28] + HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); + 800b756: f107 0314 add.w r3, r7, #20 + 800b75a: 4619 mov r1, r3 + 800b75c: 484a ldr r0, [pc, #296] @ (800b888 ) + 800b75e: f004 fea3 bl 80104a8 + + /*Configure GPIO pins : LOCK_A_Pin LOCK_B_Pin */ + GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; + 800b762: 2330 movs r3, #48 @ 0x30 + 800b764: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800b766: 2301 movs r3, #1 + 800b768: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b76a: 2300 movs r3, #0 + 800b76c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800b76e: 2302 movs r3, #2 + 800b770: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800b772: f107 0314 add.w r3, r7, #20 + 800b776: 4619 mov r1, r3 + 800b778: 4841 ldr r0, [pc, #260] @ (800b880 ) + 800b77a: f004 fe95 bl 80104a8 + + /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ + GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; + 800b77e: f244 0382 movw r3, #16514 @ 0x4082 + 800b782: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800b784: 2300 movs r3, #0 + 800b786: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b788: 2300 movs r3, #0 + 800b78a: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 800b78c: f107 0314 add.w r3, r7, #20 + 800b790: 4619 mov r1, r3 + 800b792: 483c ldr r0, [pc, #240] @ (800b884 ) + 800b794: f004 fe88 bl 80104a8 + + /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin + RELAY5_Pin */ + GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin + 800b798: f44f 53f8 mov.w r3, #7936 @ 0x1f00 + 800b79c: 617b str r3, [r7, #20] + |RELAY5_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800b79e: 2301 movs r3, #1 + 800b7a0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b7a2: 2300 movs r3, #0 + 800b7a4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800b7a6: 2302 movs r3, #2 + 800b7a8: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 800b7aa: f107 0314 add.w r3, r7, #20 + 800b7ae: 4619 mov r1, r3 + 800b7b0: 4834 ldr r0, [pc, #208] @ (800b884 ) + 800b7b2: f004 fe79 bl 80104a8 + + /*Configure GPIO pin : RELAY_CC_Pin */ + GPIO_InitStruct.Pin = RELAY_CC_Pin; + 800b7b6: f44f 4300 mov.w r3, #32768 @ 0x8000 + 800b7ba: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800b7bc: 2301 movs r3, #1 + 800b7be: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b7c0: 2300 movs r3, #0 + 800b7c2: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800b7c4: 2302 movs r3, #2 + 800b7c6: 623b str r3, [r7, #32] + HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); + 800b7c8: f107 0314 add.w r3, r7, #20 + 800b7cc: 4619 mov r1, r3 + 800b7ce: 482e ldr r0, [pc, #184] @ (800b888 ) + 800b7d0: f004 fe6a bl 80104a8 + + /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ + GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; + 800b7d4: 2318 movs r3, #24 + 800b7d6: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800b7d8: 2301 movs r3, #1 + 800b7da: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b7dc: 2300 movs r3, #0 + 800b7de: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800b7e0: 2302 movs r3, #2 + 800b7e2: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800b7e4: f107 0314 add.w r3, r7, #20 + 800b7e8: 4619 mov r1, r3 + 800b7ea: 4828 ldr r0, [pc, #160] @ (800b88c ) + 800b7ec: f004 fe5c bl 80104a8 + + /*Configure GPIO pin : IN_ESTOP_Pin */ + GPIO_InitStruct.Pin = IN_ESTOP_Pin; + 800b7f0: 2380 movs r3, #128 @ 0x80 + 800b7f2: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800b7f4: 2300 movs r3, #0 + 800b7f6: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b7f8: 2300 movs r3, #0 + 800b7fa: 61fb str r3, [r7, #28] + HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); + 800b7fc: f107 0314 add.w r3, r7, #20 + 800b800: 4619 mov r1, r3 + 800b802: 4822 ldr r0, [pc, #136] @ (800b88c ) + 800b804: f004 fe50 bl 80104a8 + + /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ + GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; + 800b808: 2318 movs r3, #24 + 800b80a: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800b80c: 2300 movs r3, #0 + 800b80e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b810: 2300 movs r3, #0 + 800b812: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800b814: f107 0314 add.w r3, r7, #20 + 800b818: 4619 mov r1, r3 + 800b81a: 481d ldr r0, [pc, #116] @ (800b890 ) + 800b81c: f004 fe44 bl 80104a8 + + /*Configure GPIO pin : EE_WP_Pin */ + GPIO_InitStruct.Pin = EE_WP_Pin; + 800b820: 2380 movs r3, #128 @ 0x80 + 800b822: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800b824: 2301 movs r3, #1 + 800b826: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800b828: 2300 movs r3, #0 + 800b82a: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800b82c: 2302 movs r3, #2 + 800b82e: 623b str r3, [r7, #32] + HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); + 800b830: f107 0314 add.w r3, r7, #20 + 800b834: 4619 mov r1, r3 + 800b836: 4816 ldr r0, [pc, #88] @ (800b890 ) + 800b838: f004 fe36 bl 80104a8 + + /*Configure GPIO pins : PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + 800b83c: f44f 7340 mov.w r3, #768 @ 0x300 + 800b840: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 800b842: 2312 movs r3, #18 + 800b844: 61bb str r3, [r7, #24] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800b846: 2303 movs r3, #3 + 800b848: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800b84a: f107 0314 add.w r3, r7, #20 + 800b84e: 4619 mov r1, r3 + 800b850: 480f ldr r0, [pc, #60] @ (800b890 ) + 800b852: f004 fe29 bl 80104a8 + + /*Configure peripheral I/O remapping */ + __HAL_AFIO_REMAP_I2C1_ENABLE(); + 800b856: 4b0f ldr r3, [pc, #60] @ (800b894 ) + 800b858: 685b ldr r3, [r3, #4] + 800b85a: 627b str r3, [r7, #36] @ 0x24 + 800b85c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800b85e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 800b862: 627b str r3, [r7, #36] @ 0x24 + 800b864: 6a7b ldr r3, [r7, #36] @ 0x24 + 800b866: f043 0302 orr.w r3, r3, #2 + 800b86a: 627b str r3, [r7, #36] @ 0x24 + 800b86c: 4a09 ldr r2, [pc, #36] @ (800b894 ) + 800b86e: 6a7b ldr r3, [r7, #36] @ 0x24 + 800b870: 6053 str r3, [r2, #4] + +} + 800b872: bf00 nop + 800b874: 3728 adds r7, #40 @ 0x28 + 800b876: 46bd mov sp, r7 + 800b878: bd80 pop {r7, pc} + 800b87a: bf00 nop + 800b87c: 40021000 .word 0x40021000 + 800b880: 40011000 .word 0x40011000 + 800b884: 40011800 .word 0x40011800 + 800b888: 40010800 .word 0x40010800 + 800b88c: 40011400 .word 0x40011400 + 800b890: 40010c00 .word 0x40010c00 + 800b894: 40010000 .word 0x40010000 + +0800b898 : +extern GBT_BCL_t GBT_CurrPower; + +j_receive_t j_rx; + +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + 800b898: b590 push {r4, r7, lr} + 800b89a: b0cd sub sp, #308 @ 0x134 + 800b89c: af40 add r7, sp, #256 @ 0x100 + 800b89e: 6078 str r0, [r7, #4] + CAN_RxHeaderTypeDef RxHeader; + uint8_t RxData[8] = {0,}; + 800b8a0: f107 030c add.w r3, r7, #12 + 800b8a4: 2200 movs r2, #0 + 800b8a6: 601a str r2, [r3, #0] + 800b8a8: 605a str r2, [r3, #4] + + if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) == HAL_OK) + 800b8aa: f107 030c add.w r3, r7, #12 + 800b8ae: f107 0214 add.w r2, r7, #20 + 800b8b2: 2100 movs r1, #0 + 800b8b4: 6878 ldr r0, [r7, #4] + 800b8b6: f004 f82b bl 800f910 + 800b8ba: 4603 mov r3, r0 + 800b8bc: 2b00 cmp r3, #0 + 800b8be: f040 8153 bne.w 800bb68 + { + if((RxHeader.ExtId & 0x00FFFF) == ((J_ID_SE << 8) | J_ID_EV)){ // SA, DA match + 800b8c2: 69bb ldr r3, [r7, #24] + 800b8c4: b29b uxth r3, r3 + 800b8c6: f245 62f4 movw r2, #22260 @ 0x56f4 + 800b8ca: 4293 cmp r3, r2 + 800b8cc: f040 814c bne.w 800bb68 + switch ((RxHeader.ExtId>>8) & 0x00FF00){ + 800b8d0: 69bb ldr r3, [r7, #24] + 800b8d2: 0a1b lsrs r3, r3, #8 + 800b8d4: f403 437f and.w r3, r3, #65280 @ 0xff00 + 800b8d8: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 + 800b8dc: d013 beq.n 800b906 + 800b8de: f5b3 4f6c cmp.w r3, #60416 @ 0xec00 + 800b8e2: f200 810c bhi.w 800bafe + 800b8e6: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 + 800b8ea: d057 beq.n 800b99c + 800b8ec: f5b3 4f6b cmp.w r3, #60160 @ 0xeb00 + 800b8f0: f200 8105 bhi.w 800bafe + 800b8f4: f5b3 5fc8 cmp.w r3, #6400 @ 0x1900 + 800b8f8: f000 80dd beq.w 800bab6 + 800b8fc: f5b3 5ff0 cmp.w r3, #7680 @ 0x1e00 + 800b900: f000 80b6 beq.w 800ba70 + 800b904: e0fb b.n 800bafe + + case 0xEC00: //PGN Connection Management Message + if(RxData[0] == 16){ //Request to Send + 800b906: 7b3b ldrb r3, [r7, #12] + 800b908: 2b10 cmp r3, #16 + 800b90a: d13e bne.n 800b98a + /* Set the RTS values */ + j_rx.size = RxData[1] | (RxData[2]<<8); + 800b90c: 7b7b ldrb r3, [r7, #13] + 800b90e: b21a sxth r2, r3 + 800b910: 7bbb ldrb r3, [r7, #14] + 800b912: b21b sxth r3, r3 + 800b914: 021b lsls r3, r3, #8 + 800b916: b21b sxth r3, r3 + 800b918: 4313 orrs r3, r2 + 800b91a: b21b sxth r3, r3 + 800b91c: b29a uxth r2, r3 + 800b91e: 4b94 ldr r3, [pc, #592] @ (800bb70 ) + 800b920: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 + j_rx.packet = 1; + 800b924: 4b92 ldr r3, [pc, #584] @ (800bb70 ) + 800b926: 2201 movs r2, #1 + 800b928: f883 2107 strb.w r2, [r3, #263] @ 0x107 + j_rx.packets = RxData[3]; + 800b92c: 7bfa ldrb r2, [r7, #15] + 800b92e: 4b90 ldr r3, [pc, #576] @ (800bb70 ) + 800b930: f883 2106 strb.w r2, [r3, #262] @ 0x106 + j_rx.step = 2; //TODO + 800b934: 4b8e ldr r3, [pc, #568] @ (800bb70 ) + 800b936: 2202 movs r2, #2 + 800b938: f883 2108 strb.w r2, [r3, #264] @ 0x108 + j_rx.step_cts_remain = j_rx.step; + 800b93c: 4b8c ldr r3, [pc, #560] @ (800bb70 ) + 800b93e: f893 2108 ldrb.w r2, [r3, #264] @ 0x108 + 800b942: 4b8b ldr r3, [pc, #556] @ (800bb70 ) + 800b944: f883 2109 strb.w r2, [r3, #265] @ 0x109 + j_rx.PGN = (RxData[7] << 16) | (RxData[6] << 8) | RxData[5]; + 800b948: 7cfb ldrb r3, [r7, #19] + 800b94a: 041a lsls r2, r3, #16 + 800b94c: 7cbb ldrb r3, [r7, #18] + 800b94e: 021b lsls r3, r3, #8 + 800b950: 4313 orrs r3, r2 + 800b952: 7c7a ldrb r2, [r7, #17] + 800b954: 4313 orrs r3, r2 + 800b956: 461a mov r2, r3 + 800b958: 4b85 ldr r3, [pc, #532] @ (800bb70 ) + 800b95a: f8c3 2100 str.w r2, [r3, #256] @ 0x100 + if(j_rx.size<256) { //TODO: valid check + 800b95e: 4b84 ldr r3, [pc, #528] @ (800bb70 ) + 800b960: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 + 800b964: 2bff cmp r3, #255 @ 0xff + 800b966: d810 bhi.n 800b98a + J_SendCTS(j_rx); + 800b968: 4c81 ldr r4, [pc, #516] @ (800bb70 ) + 800b96a: 4668 mov r0, sp + 800b96c: f104 0310 add.w r3, r4, #16 + 800b970: f44f 7280 mov.w r2, #256 @ 0x100 + 800b974: 4619 mov r1, r3 + 800b976: f008 fc99 bl 80142ac + 800b97a: e894 000f ldmia.w r4, {r0, r1, r2, r3} + 800b97e: f000 f941 bl 800bc04 + j_rx.state = 1; + 800b982: 4b7b ldr r3, [pc, #492] @ (800bb70 ) + 800b984: 2201 movs r2, #1 + 800b986: f883 210a strb.w r2, [r3, #266] @ 0x10a + } + } + if(RxData[0] == 255){ //Connection Abort + 800b98a: 7b3b ldrb r3, [r7, #12] + 800b98c: 2bff cmp r3, #255 @ 0xff + 800b98e: f040 80e6 bne.w 800bb5e + j_rx.state = 0; + 800b992: 4b77 ldr r3, [pc, #476] @ (800bb70 ) + 800b994: 2200 movs r2, #0 + 800b996: f883 210a strb.w r2, [r3, #266] @ 0x10a + * 1CECF456 11 02 01 FF FF 00 02 00 + * 1CEB56F4 01 01 01 00 03 46 05 40 + * 1CEC56F4 FF FF FF FF FF 00 00 00 + */ + + break; + 800b99a: e0e0 b.n 800bb5e + + case 0xEB00: //PGN Data Message + if(j_rx.state != 1) break; + 800b99c: 4b74 ldr r3, [pc, #464] @ (800bb70 ) + 800b99e: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800b9a2: 2b01 cmp r3, #1 + 800b9a4: f040 80dd bne.w 800bb62 + if((RxData[0]>0) && (RxData[0]<35)){ //Array limit check + 800b9a8: 7b3b ldrb r3, [r7, #12] + 800b9aa: 2b00 cmp r3, #0 + 800b9ac: f000 80db beq.w 800bb66 + 800b9b0: 7b3b ldrb r3, [r7, #12] + 800b9b2: 2b22 cmp r3, #34 @ 0x22 + 800b9b4: f200 80d7 bhi.w 800bb66 + if(j_rx.packet == RxData[0]){ //step check + 800b9b8: 4b6d ldr r3, [pc, #436] @ (800bb70 ) + 800b9ba: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 + 800b9be: 7b3b ldrb r3, [r7, #12] + 800b9c0: 429a cmp r2, r3 + 800b9c2: f040 80d0 bne.w 800bb66 + memcpy (&j_rx.data[(RxData[0]-1)*7], &RxData[1],7); + 800b9c6: 7b3b ldrb r3, [r7, #12] + 800b9c8: 1e5a subs r2, r3, #1 + 800b9ca: 4613 mov r3, r2 + 800b9cc: 00db lsls r3, r3, #3 + 800b9ce: 1a9b subs r3, r3, r2 + 800b9d0: 4a67 ldr r2, [pc, #412] @ (800bb70 ) + 800b9d2: 1898 adds r0, r3, r2 + 800b9d4: f107 030c add.w r3, r7, #12 + 800b9d8: 3301 adds r3, #1 + 800b9da: 2207 movs r2, #7 + 800b9dc: 4619 mov r1, r3 + 800b9de: f008 fc65 bl 80142ac + j_rx.packet++; + 800b9e2: 4b63 ldr r3, [pc, #396] @ (800bb70 ) + 800b9e4: f893 3107 ldrb.w r3, [r3, #263] @ 0x107 + 800b9e8: 3301 adds r3, #1 + 800b9ea: b2da uxtb r2, r3 + 800b9ec: 4b60 ldr r3, [pc, #384] @ (800bb70 ) + 800b9ee: f883 2107 strb.w r2, [r3, #263] @ 0x107 + if(j_rx.packet > j_rx.packets){ + 800b9f2: 4b5f ldr r3, [pc, #380] @ (800bb70 ) + 800b9f4: f893 2107 ldrb.w r2, [r3, #263] @ 0x107 + 800b9f8: 4b5d ldr r3, [pc, #372] @ (800bb70 ) + 800b9fa: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 + 800b9fe: 429a cmp r2, r3 + 800ba00: d911 bls.n 800ba26 + //End of transmission + J_SendACK(j_rx); + 800ba02: 4c5b ldr r4, [pc, #364] @ (800bb70 ) + 800ba04: 4668 mov r0, sp + 800ba06: f104 0310 add.w r3, r4, #16 + 800ba0a: f44f 7280 mov.w r2, #256 @ 0x100 + 800ba0e: 4619 mov r1, r3 + 800ba10: f008 fc4c bl 80142ac + 800ba14: e894 000f ldmia.w r4, {r0, r1, r2, r3} + 800ba18: f000 f93a bl 800bc90 + + j_rx.state = 2; + 800ba1c: 4b54 ldr r3, [pc, #336] @ (800bb70 ) + 800ba1e: 2202 movs r2, #2 + 800ba20: f883 210a strb.w r2, [r3, #266] @ 0x10a + j_rx.step_cts_remain = 2; + } + } + } + } + break; + 800ba24: e09f b.n 800bb66 + if(j_rx.step_cts_remain > 0) j_rx.step_cts_remain--; + 800ba26: 4b52 ldr r3, [pc, #328] @ (800bb70 ) + 800ba28: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 + 800ba2c: 2b00 cmp r3, #0 + 800ba2e: d007 beq.n 800ba40 + 800ba30: 4b4f ldr r3, [pc, #316] @ (800bb70 ) + 800ba32: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 + 800ba36: 3b01 subs r3, #1 + 800ba38: b2da uxtb r2, r3 + 800ba3a: 4b4d ldr r3, [pc, #308] @ (800bb70 ) + 800ba3c: f883 2109 strb.w r2, [r3, #265] @ 0x109 + if(j_rx.step_cts_remain == 0){ + 800ba40: 4b4b ldr r3, [pc, #300] @ (800bb70 ) + 800ba42: f893 3109 ldrb.w r3, [r3, #265] @ 0x109 + 800ba46: 2b00 cmp r3, #0 + 800ba48: f040 808d bne.w 800bb66 + J_SendCTS(j_rx); + 800ba4c: 4c48 ldr r4, [pc, #288] @ (800bb70 ) + 800ba4e: 4668 mov r0, sp + 800ba50: f104 0310 add.w r3, r4, #16 + 800ba54: f44f 7280 mov.w r2, #256 @ 0x100 + 800ba58: 4619 mov r1, r3 + 800ba5a: f008 fc27 bl 80142ac + 800ba5e: e894 000f ldmia.w r4, {r0, r1, r2, r3} + 800ba62: f000 f8cf bl 800bc04 + j_rx.step_cts_remain = 2; + 800ba66: 4b42 ldr r3, [pc, #264] @ (800bb70 ) + 800ba68: 2202 movs r2, #2 + 800ba6a: f883 2109 strb.w r2, [r3, #265] @ 0x109 + break; + 800ba6e: e07a b.n 800bb66 + + case 0x1E00: //PGN BEM (ERROR) + //Error force stop + // --> Suspend EV + log_printf(LOG_ERR, "BEM Received, force stopping...\n"); + 800ba70: 4940 ldr r1, [pc, #256] @ (800bb74 ) + 800ba72: 2004 movs r0, #4 + 800ba74: f7ff fcf6 bl 800b464 + log_printf(LOG_ERR, "BEM: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); + 800ba78: 7b3b ldrb r3, [r7, #12] + 800ba7a: 4619 mov r1, r3 + 800ba7c: 7b7b ldrb r3, [r7, #13] + 800ba7e: 4618 mov r0, r3 + 800ba80: 7bbb ldrb r3, [r7, #14] + 800ba82: 7bfa ldrb r2, [r7, #15] + 800ba84: 9201 str r2, [sp, #4] + 800ba86: 9300 str r3, [sp, #0] + 800ba88: 4603 mov r3, r0 + 800ba8a: 460a mov r2, r1 + 800ba8c: 493a ldr r1, [pc, #232] @ (800bb78 ) + 800ba8e: 2004 movs r0, #4 + 800ba90: f7ff fce8 bl 800b464 + log_printf(LOG_ERR, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); + 800ba94: 7c3b ldrb r3, [r7, #16] + 800ba96: 4619 mov r1, r3 + 800ba98: 7c7b ldrb r3, [r7, #17] + 800ba9a: 4618 mov r0, r3 + 800ba9c: 7cbb ldrb r3, [r7, #18] + 800ba9e: 7cfa ldrb r2, [r7, #19] + 800baa0: 9201 str r2, [sp, #4] + 800baa2: 9300 str r3, [sp, #0] + 800baa4: 4603 mov r3, r0 + 800baa6: 460a mov r2, r1 + 800baa8: 4934 ldr r1, [pc, #208] @ (800bb7c ) + 800baaa: 2004 movs r0, #4 + 800baac: f7ff fcda bl 800b464 + GBT_ForceStop(); + 800bab0: f7ff f86e bl 800ab90 + break; + 800bab4: e058 b.n 800bb68 + + case 0x1900: //PGN BST (STOP) + //Normal stop + + // --> Suspend EV + log_printf(LOG_INFO, "BST Received, stopping...\n"); + 800bab6: 4932 ldr r1, [pc, #200] @ (800bb80 ) + 800bab8: 2007 movs r0, #7 + 800baba: f7ff fcd3 bl 800b464 + log_printf(LOG_INFO, "BST: %02X %02X %02X %02X", RxData[0], RxData[1], RxData[2], RxData[3]); + 800babe: 7b3b ldrb r3, [r7, #12] + 800bac0: 4619 mov r1, r3 + 800bac2: 7b7b ldrb r3, [r7, #13] + 800bac4: 4618 mov r0, r3 + 800bac6: 7bbb ldrb r3, [r7, #14] + 800bac8: 7bfa ldrb r2, [r7, #15] + 800baca: 9201 str r2, [sp, #4] + 800bacc: 9300 str r3, [sp, #0] + 800bace: 4603 mov r3, r0 + 800bad0: 460a mov r2, r1 + 800bad2: 492c ldr r1, [pc, #176] @ (800bb84 ) + 800bad4: 2007 movs r0, #7 + 800bad6: f7ff fcc5 bl 800b464 + log_printf(LOG_INFO, " %02X %02X %02X %02X\n", RxData[4], RxData[5], RxData[6], RxData[7]); + 800bada: 7c3b ldrb r3, [r7, #16] + 800badc: 4619 mov r1, r3 + 800bade: 7c7b ldrb r3, [r7, #17] + 800bae0: 4618 mov r0, r3 + 800bae2: 7cbb ldrb r3, [r7, #18] + 800bae4: 7cfa ldrb r2, [r7, #19] + 800bae6: 9201 str r2, [sp, #4] + 800bae8: 9300 str r3, [sp, #0] + 800baea: 4603 mov r3, r0 + 800baec: 460a mov r2, r1 + 800baee: 4923 ldr r1, [pc, #140] @ (800bb7c ) + 800baf0: 2007 movs r0, #7 + 800baf2: f7ff fcb7 bl 800b464 + GBT_StopEV(GBT_CST_BMS_ACTIVELY_SUSPENDS); + 800baf6: 4824 ldr r0, [pc, #144] @ (800bb88 ) + 800baf8: f7fe ffec bl 800aad4 + + break; + 800bafc: e034 b.n 800bb68 + + default: + if(j_rx.state == 0){//TODO protections + 800bafe: 4b1c ldr r3, [pc, #112] @ (800bb70 ) + 800bb00: f893 310a ldrb.w r3, [r3, #266] @ 0x10a + 800bb04: 2b00 cmp r3, #0 + 800bb06: d12f bne.n 800bb68 + //Short packet + j_rx.size = RxHeader.DLC; + 800bb08: 6a7b ldr r3, [r7, #36] @ 0x24 + 800bb0a: b29a uxth r2, r3 + 800bb0c: 4b18 ldr r3, [pc, #96] @ (800bb70 ) + 800bb0e: f8a3 2104 strh.w r2, [r3, #260] @ 0x104 + j_rx.packet = 1; + 800bb12: 4b17 ldr r3, [pc, #92] @ (800bb70 ) + 800bb14: 2201 movs r2, #1 + 800bb16: f883 2107 strb.w r2, [r3, #263] @ 0x107 + j_rx.packets = 1; + 800bb1a: 4b15 ldr r3, [pc, #84] @ (800bb70 ) + 800bb1c: 2201 movs r2, #1 + 800bb1e: f883 2106 strb.w r2, [r3, #262] @ 0x106 + j_rx.step = 1; + 800bb22: 4b13 ldr r3, [pc, #76] @ (800bb70 ) + 800bb24: 2201 movs r2, #1 + 800bb26: f883 2108 strb.w r2, [r3, #264] @ 0x108 + j_rx.step_cts_remain = 0; + 800bb2a: 4b11 ldr r3, [pc, #68] @ (800bb70 ) + 800bb2c: 2200 movs r2, #0 + 800bb2e: f883 2109 strb.w r2, [r3, #265] @ 0x109 + j_rx.PGN = (RxHeader.ExtId>>8) & 0x00FF00; + 800bb32: 69bb ldr r3, [r7, #24] + 800bb34: 0a1b lsrs r3, r3, #8 + 800bb36: f403 437f and.w r3, r3, #65280 @ 0xff00 + 800bb3a: 4a0d ldr r2, [pc, #52] @ (800bb70 ) + 800bb3c: f8c2 3100 str.w r3, [r2, #256] @ 0x100 + j_rx.state = 2; + 800bb40: 4b0b ldr r3, [pc, #44] @ (800bb70 ) + 800bb42: 2202 movs r2, #2 + 800bb44: f883 210a strb.w r2, [r3, #266] @ 0x10a + memcpy (j_rx.data, RxData, j_rx.size); + 800bb48: 4b09 ldr r3, [pc, #36] @ (800bb70 ) + 800bb4a: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 + 800bb4e: 461a mov r2, r3 + 800bb50: f107 030c add.w r3, r7, #12 + 800bb54: 4619 mov r1, r3 + 800bb56: 4806 ldr r0, [pc, #24] @ (800bb70 ) + 800bb58: f008 fba8 bl 80142ac + } + } + } + } +} + 800bb5c: e004 b.n 800bb68 + break; + 800bb5e: bf00 nop + 800bb60: e002 b.n 800bb68 + if(j_rx.state != 1) break; + 800bb62: bf00 nop + 800bb64: e000 b.n 800bb68 + break; + 800bb66: bf00 nop +} + 800bb68: bf00 nop + 800bb6a: 3734 adds r7, #52 @ 0x34 + 800bb6c: 46bd mov sp, r7 + 800bb6e: bd90 pop {r4, r7, pc} + 800bb70: 20000860 .word 0x20000860 + 800bb74: 08016a44 .word 0x08016a44 + 800bb78: 08016a68 .word 0x08016a68 + 800bb7c: 08016a84 .word 0x08016a84 + 800bb80: 08016a9c .word 0x08016a9c + 800bb84: 08016ab8 .word 0x08016ab8 + 800bb88: 4000f0f0 .word 0x4000f0f0 + +0800bb8c : + +void GBT_CAN_ReInit(){ + 800bb8c: b580 push {r7, lr} + 800bb8e: af00 add r7, sp, #0 + HAL_CAN_Stop(&hcan1); + 800bb90: 4807 ldr r0, [pc, #28] @ (800bbb0 ) + 800bb92: f003 fd71 bl 800f678 + MX_CAN1_Init(); + 800bb96: f7fd ff63 bl 8009a60 + GBT_CAN_FilterInit(); + 800bb9a: f000 f8b3 bl 800bd04 + HAL_CAN_Start(&hcan1); + 800bb9e: 4804 ldr r0, [pc, #16] @ (800bbb0 ) + 800bba0: f003 fd26 bl 800f5f0 + HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); + 800bba4: 2102 movs r1, #2 + 800bba6: 4802 ldr r0, [pc, #8] @ (800bbb0 ) + 800bba8: f003 ffd3 bl 800fb52 +} + 800bbac: bf00 nop + 800bbae: bd80 pop {r7, pc} + 800bbb0: 20000294 .word 0x20000294 + +0800bbb4 : + +void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ + 800bbb4: b580 push {r7, lr} + 800bbb6: b08c sub sp, #48 @ 0x30 + 800bbb8: af00 add r7, sp, #0 + 800bbba: 60f8 str r0, [r7, #12] + 800bbbc: 607b str r3, [r7, #4] + 800bbbe: 460b mov r3, r1 + 800bbc0: 72fb strb r3, [r7, #11] + 800bbc2: 4613 mov r3, r2 + 800bbc4: 72bb strb r3, [r7, #10] + + CAN_TxHeaderTypeDef tx_header; + uint32_t tx_mailbox; + + tx_header.ExtId = (pri << 26) | (PGN << 8) | (J_ID_EV << 8) | J_ID_SE; + 800bbc6: 7afb ldrb r3, [r7, #11] + 800bbc8: 069a lsls r2, r3, #26 + 800bbca: 68fb ldr r3, [r7, #12] + 800bbcc: 021b lsls r3, r3, #8 + 800bbce: 4313 orrs r3, r2 + 800bbd0: f443 4374 orr.w r3, r3, #62464 @ 0xf400 + 800bbd4: f043 0356 orr.w r3, r3, #86 @ 0x56 + 800bbd8: 61fb str r3, [r7, #28] + tx_header.RTR = CAN_RTR_DATA; + 800bbda: 2300 movs r3, #0 + 800bbdc: 627b str r3, [r7, #36] @ 0x24 + tx_header.IDE = CAN_ID_EXT; + 800bbde: 2304 movs r3, #4 + 800bbe0: 623b str r3, [r7, #32] + tx_header.DLC = DLC; + 800bbe2: 7abb ldrb r3, [r7, #10] + 800bbe4: 62bb str r3, [r7, #40] @ 0x28 + + //TODO buffer wait + HAL_CAN_AddTxMessage(&hcan1, &tx_header, data, &tx_mailbox); + 800bbe6: f107 0314 add.w r3, r7, #20 + 800bbea: f107 0118 add.w r1, r7, #24 + 800bbee: 687a ldr r2, [r7, #4] + 800bbf0: 4803 ldr r0, [pc, #12] @ (800bc00 ) + 800bbf2: f003 fd8a bl 800f70a + //HAL_Delay(2); + +} + 800bbf6: bf00 nop + 800bbf8: 3730 adds r7, #48 @ 0x30 + 800bbfa: 46bd mov sp, r7 + 800bbfc: bd80 pop {r7, pc} + 800bbfe: bf00 nop + 800bc00: 20000294 .word 0x20000294 + +0800bc04 : +//void J_SendPacketLong(){ +// //TODO (no need) +//} + +// J1939 sequence Clear To Send packet +void J_SendCTS(j_receive_t rx){ + 800bc04: b084 sub sp, #16 + 800bc06: b580 push {r7, lr} + 800bc08: b082 sub sp, #8 + 800bc0a: af00 add r7, sp, #0 + 800bc0c: f107 0c10 add.w ip, r7, #16 + 800bc10: e88c 000f stmia.w ip, {r0, r1, r2, r3} + + //if(rx.packets <= rx.packet) return; TODO + uint8_t data[8]; + data[0] = 17; //CONTROL_BYTE_TP_CM_CTS + 800bc14: 2311 movs r3, #17 + 800bc16: 703b strb r3, [r7, #0] + data[1] = rx.step;//total_number_of_packages_transmitted + 800bc18: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 + 800bc1c: 707b strb r3, [r7, #1] + if (rx.step > (rx.packets - rx.packet+1)) data[1] = rx.packets - rx.packet+1; + 800bc1e: f897 3118 ldrb.w r3, [r7, #280] @ 0x118 + 800bc22: 461a mov r2, r3 + 800bc24: f897 3116 ldrb.w r3, [r7, #278] @ 0x116 + 800bc28: 4619 mov r1, r3 + 800bc2a: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 + 800bc2e: 1acb subs r3, r1, r3 + 800bc30: 3301 adds r3, #1 + 800bc32: 429a cmp r2, r3 + 800bc34: dd08 ble.n 800bc48 + 800bc36: f897 2116 ldrb.w r2, [r7, #278] @ 0x116 + 800bc3a: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 + 800bc3e: 1ad3 subs r3, r2, r3 + 800bc40: b2db uxtb r3, r3 + 800bc42: 3301 adds r3, #1 + 800bc44: b2db uxtb r3, r3 + 800bc46: 707b strb r3, [r7, #1] + data[2] = rx.packet;//next_packet_number_transmitted + 800bc48: f897 3117 ldrb.w r3, [r7, #279] @ 0x117 + 800bc4c: 70bb strb r3, [r7, #2] + data[3] = 0xFF; /* Reserved */ + 800bc4e: 23ff movs r3, #255 @ 0xff + 800bc50: 70fb strb r3, [r7, #3] + data[4] = 0xFF; + 800bc52: 23ff movs r3, #255 @ 0xff + 800bc54: 713b strb r3, [r7, #4] + data[5] = rx.PGN; + 800bc56: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bc5a: b2db uxtb r3, r3 + 800bc5c: 717b strb r3, [r7, #5] + data[6] = rx.PGN >> 8; + 800bc5e: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bc62: 0a1b lsrs r3, r3, #8 + 800bc64: b2db uxtb r3, r3 + 800bc66: 71bb strb r3, [r7, #6] + data[7] = rx.PGN >> 16; + 800bc68: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bc6c: 0c1b lsrs r3, r3, #16 + 800bc6e: b2db uxtb r3, r3 + 800bc70: 71fb strb r3, [r7, #7] + + J_SendPacket(0x00EC00, 7, 8, data); + 800bc72: 463b mov r3, r7 + 800bc74: 2208 movs r2, #8 + 800bc76: 2107 movs r1, #7 + 800bc78: f44f 406c mov.w r0, #60416 @ 0xec00 + 800bc7c: f7ff ff9a bl 800bbb4 +} + 800bc80: bf00 nop + 800bc82: 3708 adds r7, #8 + 800bc84: 46bd mov sp, r7 + 800bc86: e8bd 4080 ldmia.w sp!, {r7, lr} + 800bc8a: b004 add sp, #16 + 800bc8c: 4770 bx lr + ... + +0800bc90 : + +// J1939 sequence ACK packet +void J_SendACK(j_receive_t rx){//uint32_t PGN, uint8_t step, uint8_t packet){ + 800bc90: b084 sub sp, #16 + 800bc92: b580 push {r7, lr} + 800bc94: b082 sub sp, #8 + 800bc96: af00 add r7, sp, #0 + 800bc98: f107 0c10 add.w ip, r7, #16 + 800bc9c: e88c 000f stmia.w ip, {r0, r1, r2, r3} + + uint8_t data[8]; + data[0] = 19; //CONTROL_BYTE_TP_CM_ACK + 800bca0: 2313 movs r3, #19 + 800bca2: 703b strb r3, [r7, #0] + data[1] = j_rx.size; + 800bca4: 4b16 ldr r3, [pc, #88] @ (800bd00 ) + 800bca6: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 + 800bcaa: b2db uxtb r3, r3 + 800bcac: 707b strb r3, [r7, #1] + data[2] = j_rx.size>>8; + 800bcae: 4b14 ldr r3, [pc, #80] @ (800bd00 ) + 800bcb0: f8b3 3104 ldrh.w r3, [r3, #260] @ 0x104 + 800bcb4: 0a1b lsrs r3, r3, #8 + 800bcb6: b29b uxth r3, r3 + 800bcb8: b2db uxtb r3, r3 + 800bcba: 70bb strb r3, [r7, #2] + data[3] = j_rx.packets; + 800bcbc: 4b10 ldr r3, [pc, #64] @ (800bd00 ) + 800bcbe: f893 3106 ldrb.w r3, [r3, #262] @ 0x106 + 800bcc2: 70fb strb r3, [r7, #3] + data[4] = 0xFF;//TODO + 800bcc4: 23ff movs r3, #255 @ 0xff + 800bcc6: 713b strb r3, [r7, #4] + data[5] = rx.PGN; + 800bcc8: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bccc: b2db uxtb r3, r3 + 800bcce: 717b strb r3, [r7, #5] + data[6] = rx.PGN >> 8; + 800bcd0: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bcd4: 0a1b lsrs r3, r3, #8 + 800bcd6: b2db uxtb r3, r3 + 800bcd8: 71bb strb r3, [r7, #6] + data[7] = rx.PGN >> 16; + 800bcda: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110 + 800bcde: 0c1b lsrs r3, r3, #16 + 800bce0: b2db uxtb r3, r3 + 800bce2: 71fb strb r3, [r7, #7] + + J_SendPacket(0x00EC00, 7, 8, data); + 800bce4: 463b mov r3, r7 + 800bce6: 2208 movs r2, #8 + 800bce8: 2107 movs r1, #7 + 800bcea: f44f 406c mov.w r0, #60416 @ 0xec00 + 800bcee: f7ff ff61 bl 800bbb4 +} + 800bcf2: bf00 nop + 800bcf4: 3708 adds r7, #8 + 800bcf6: 46bd mov sp, r7 + 800bcf8: e8bd 4080 ldmia.w sp!, {r7, lr} + 800bcfc: b004 add sp, #16 + 800bcfe: 4770 bx lr + 800bd00: 20000860 .word 0x20000860 + +0800bd04 : + +void GBT_CAN_FilterInit(){ + 800bd04: b580 push {r7, lr} + 800bd06: b08a sub sp, #40 @ 0x28 + 800bd08: af00 add r7, sp, #0 + CAN_FilterTypeDef sFilterConfig; + + sFilterConfig.FilterBank = 0; + 800bd0a: 2300 movs r3, #0 + 800bd0c: 617b str r3, [r7, #20] + sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; + 800bd0e: 2300 movs r3, #0 + 800bd10: 61bb str r3, [r7, #24] + sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; + 800bd12: 2301 movs r3, #1 + 800bd14: 61fb str r3, [r7, #28] + sFilterConfig.FilterIdHigh = 0x0000; + 800bd16: 2300 movs r3, #0 + 800bd18: 603b str r3, [r7, #0] + sFilterConfig.FilterIdLow = 0x0000; + 800bd1a: 2300 movs r3, #0 + 800bd1c: 607b str r3, [r7, #4] + sFilterConfig.FilterMaskIdHigh = 0x0000; + 800bd1e: 2300 movs r3, #0 + 800bd20: 60bb str r3, [r7, #8] + sFilterConfig.FilterMaskIdLow = 0x0000; + 800bd22: 2300 movs r3, #0 + 800bd24: 60fb str r3, [r7, #12] + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; + 800bd26: 2300 movs r3, #0 + 800bd28: 613b str r3, [r7, #16] + sFilterConfig.FilterActivation = ENABLE; + 800bd2a: 2301 movs r3, #1 + 800bd2c: 623b str r3, [r7, #32] + //sFilterConfig.SlaveStartFilterBank = 14; + if(HAL_CAN_ConfigFilter(&hcan1, &sFilterConfig) != HAL_OK) + 800bd2e: 463b mov r3, r7 + 800bd30: 4619 mov r1, r3 + 800bd32: 4806 ldr r0, [pc, #24] @ (800bd4c ) + 800bd34: f003 fb7c bl 800f430 + 800bd38: 4603 mov r3, r0 + 800bd3a: 2b00 cmp r3, #0 + 800bd3c: d001 beq.n 800bd42 + { + Error_Handler(); + 800bd3e: f000 fad3 bl 800c2e8 + } + +} + 800bd42: bf00 nop + 800bd44: 3728 adds r7, #40 @ 0x28 + 800bd46: 46bd mov sp, r7 + 800bd48: bd80 pop {r7, pc} + 800bd4a: bf00 nop + 800bd4c: 20000294 .word 0x20000294 + +0800bd50 : + .retry_count = 0, + .error_tick = 0 +}; + + +void GBT_ForceLock(uint8_t state){ + 800bd50: b480 push {r7} + 800bd52: b083 sub sp, #12 + 800bd54: af00 add r7, sp, #0 + 800bd56: 4603 mov r3, r0 + 800bd58: 71fb strb r3, [r7, #7] + // Устанавливаем флаг для выполнения действия + GBT_LockState.action_requested = state ? 1 : 0; + 800bd5a: 79fb ldrb r3, [r7, #7] + 800bd5c: 2b00 cmp r3, #0 + 800bd5e: bf14 ite ne + 800bd60: 2301 movne r3, #1 + 800bd62: 2300 moveq r3, #0 + 800bd64: b2db uxtb r3, r3 + 800bd66: 461a mov r2, r3 + 800bd68: 4b04 ldr r3, [pc, #16] @ (800bd7c ) + 800bd6a: 709a strb r2, [r3, #2] + GBT_LockState.retry_count = 0; + 800bd6c: 4b03 ldr r3, [pc, #12] @ (800bd7c ) + 800bd6e: 2200 movs r2, #0 + 800bd70: 721a strb r2, [r3, #8] +} + 800bd72: bf00 nop + 800bd74: 370c adds r7, #12 + 800bd76: 46bd mov sp, r7 + 800bd78: bc80 pop {r7} + 800bd7a: 4770 bx lr + 800bd7c: 20000008 .word 0x20000008 + +0800bd80 : + +uint8_t GBT_LockGetState(){ + 800bd80: b580 push {r7, lr} + 800bd82: af00 add r7, sp, #0 + //1 = locked + //0 = unlocked + if(LOCK_POLARITY){ + 800bd84: 4b0a ldr r3, [pc, #40] @ (800bdb0 ) + 800bd86: 781b ldrb r3, [r3, #0] + 800bd88: 2b00 cmp r3, #0 + 800bd8a: d005 beq.n 800bd98 + return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); + 800bd8c: 2180 movs r1, #128 @ 0x80 + 800bd8e: 4809 ldr r0, [pc, #36] @ (800bdb4 ) + 800bd90: f004 fd0e bl 80107b0 + 800bd94: 4603 mov r3, r0 + 800bd96: e009 b.n 800bdac + }else{ + return !HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); + 800bd98: 2180 movs r1, #128 @ 0x80 + 800bd9a: 4806 ldr r0, [pc, #24] @ (800bdb4 ) + 800bd9c: f004 fd08 bl 80107b0 + 800bda0: 4603 mov r3, r0 + 800bda2: 2b00 cmp r3, #0 + 800bda4: bf0c ite eq + 800bda6: 2301 moveq r3, #1 + 800bda8: 2300 movne r3, #0 + 800bdaa: b2db uxtb r3, r3 + + } +} + 800bdac: 4618 mov r0, r3 + 800bdae: bd80 pop {r7, pc} + 800bdb0: 20000004 .word 0x20000004 + 800bdb4: 40011800 .word 0x40011800 + +0800bdb8 : + +void GBT_Lock(uint8_t state){ + 800bdb8: b480 push {r7} + 800bdba: b083 sub sp, #12 + 800bdbc: af00 add r7, sp, #0 + 800bdbe: 4603 mov r3, r0 + 800bdc0: 71fb strb r3, [r7, #7] + GBT_LockState.demand = state; + 800bdc2: 4a04 ldr r2, [pc, #16] @ (800bdd4 ) + 800bdc4: 79fb ldrb r3, [r7, #7] + 800bdc6: 7013 strb r3, [r2, #0] +} + 800bdc8: bf00 nop + 800bdca: 370c adds r7, #12 + 800bdcc: 46bd mov sp, r7 + 800bdce: bc80 pop {r7} + 800bdd0: 4770 bx lr + 800bdd2: bf00 nop + 800bdd4: 20000008 .word 0x20000008 + +0800bdd8 : + tick = HAL_GetTick(); + + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, GBT_LockState.demand ? 1 : 0); +} + +void GBT_ManageLockMotor(){ + 800bdd8: b580 push {r7, lr} + 800bdda: b082 sub sp, #8 + 800bddc: af00 add r7, sp, #0 + static const uint8_t MAX_RETRIES = 5; + uint32_t current_tick = HAL_GetTick(); + 800bdde: f002 fcf7 bl 800e7d0 + 800bde2: 6078 str r0, [r7, #4] + + // Проверяем таймаут сброса ошибки (до проверки error, чтобы можно было сбросить) + GBT_ResetErrorTimeout(); + 800bde4: f000 f904 bl 800bff0 + + if (GBT_LockState.error) { + 800bde8: 4b72 ldr r3, [pc, #456] @ (800bfb4 ) + 800bdea: 785b ldrb r3, [r3, #1] + 800bdec: 2b00 cmp r3, #0 + 800bdee: f040 80dd bne.w 800bfac + return; + } + + // Проверяем, нужно ли выполнить действие + bool lock_is_open = GBT_LockGetState() == 0; + 800bdf2: f7ff ffc5 bl 800bd80 + 800bdf6: 4603 mov r3, r0 + 800bdf8: 2b00 cmp r3, #0 + 800bdfa: bf0c ite eq + 800bdfc: 2301 moveq r3, #1 + 800bdfe: 2300 movne r3, #0 + 800be00: 70fb strb r3, [r7, #3] + bool lock_should_be_open = GBT_LockState.demand == 0; + 800be02: 4b6c ldr r3, [pc, #432] @ (800bfb4 ) + 800be04: 781b ldrb r3, [r3, #0] + 800be06: 2b00 cmp r3, #0 + 800be08: bf0c ite eq + 800be0a: 2301 moveq r3, #1 + 800be0c: 2300 movne r3, #0 + 800be0e: 70bb strb r3, [r7, #2] + + // Если есть запрошенное действие или состояние не соответствует требуемому + if (GBT_LockState.action_requested != 255 || (lock_is_open != lock_should_be_open)) { + 800be10: 4b68 ldr r3, [pc, #416] @ (800bfb4 ) + 800be12: 789b ldrb r3, [r3, #2] + 800be14: 2bff cmp r3, #255 @ 0xff + 800be16: d104 bne.n 800be22 + 800be18: 78fa ldrb r2, [r7, #3] + 800be1a: 78bb ldrb r3, [r7, #2] + 800be1c: 429a cmp r2, r3 + 800be1e: f000 80ad beq.w 800bf7c + // Если действие еще не запрошено, запрашиваем его + if (GBT_LockState.action_requested == 255) { + 800be22: 4b64 ldr r3, [pc, #400] @ (800bfb4 ) + 800be24: 789b ldrb r3, [r3, #2] + 800be26: 2bff cmp r3, #255 @ 0xff + 800be28: d109 bne.n 800be3e + GBT_LockState.action_requested = lock_should_be_open ? 0 : 1; + 800be2a: 78bb ldrb r3, [r7, #2] + 800be2c: f083 0301 eor.w r3, r3, #1 + 800be30: b2db uxtb r3, r3 + 800be32: 461a mov r2, r3 + 800be34: 4b5f ldr r3, [pc, #380] @ (800bfb4 ) + 800be36: 709a strb r2, [r3, #2] + GBT_LockState.retry_count = 0; + 800be38: 4b5e ldr r3, [pc, #376] @ (800bfb4 ) + 800be3a: 2200 movs r2, #0 + 800be3c: 721a strb r2, [r3, #8] + } + + // Управление мотором через машину состояний + switch (GBT_LockState.motor_state) { + 800be3e: 4b5d ldr r3, [pc, #372] @ (800bfb4 ) + 800be40: 78db ldrb r3, [r3, #3] + 800be42: 2b02 cmp r3, #2 + 800be44: d04a beq.n 800bedc + 800be46: 2b02 cmp r3, #2 + 800be48: f300 80b1 bgt.w 800bfae + 800be4c: 2b00 cmp r3, #0 + 800be4e: d002 beq.n 800be56 + 800be50: 2b01 cmp r3, #1 + 800be52: d02a beq.n 800beaa + 800be54: e0ab b.n 800bfae + case 0: // idle - мотор выключен + // Определяем, какой пин нужно включить + if (LOCK_MOTOR_POLARITY) { + 800be56: 4b58 ldr r3, [pc, #352] @ (800bfb8 ) + 800be58: 781b ldrb r3, [r3, #0] + 800be5a: 2b00 cmp r3, #0 + 800be5c: d00f beq.n 800be7e + if (GBT_LockState.action_requested == 1) { // LOCK + 800be5e: 4b55 ldr r3, [pc, #340] @ (800bfb4 ) + 800be60: 789b ldrb r3, [r3, #2] + 800be62: 2b01 cmp r3, #1 + 800be64: d105 bne.n 800be72 + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); + 800be66: 2201 movs r2, #1 + 800be68: 2120 movs r1, #32 + 800be6a: 4854 ldr r0, [pc, #336] @ (800bfbc ) + 800be6c: f004 fcb7 bl 80107de + 800be70: e014 b.n 800be9c + } else { // UNLOCK + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); + 800be72: 2201 movs r2, #1 + 800be74: 2110 movs r1, #16 + 800be76: 4851 ldr r0, [pc, #324] @ (800bfbc ) + 800be78: f004 fcb1 bl 80107de + 800be7c: e00e b.n 800be9c + } + } else { + if (GBT_LockState.action_requested == 1) { // LOCK + 800be7e: 4b4d ldr r3, [pc, #308] @ (800bfb4 ) + 800be80: 789b ldrb r3, [r3, #2] + 800be82: 2b01 cmp r3, #1 + 800be84: d105 bne.n 800be92 + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); + 800be86: 2201 movs r2, #1 + 800be88: 2110 movs r1, #16 + 800be8a: 484c ldr r0, [pc, #304] @ (800bfbc ) + 800be8c: f004 fca7 bl 80107de + 800be90: e004 b.n 800be9c + } else { // UNLOCK + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); + 800be92: 2201 movs r2, #1 + 800be94: 2120 movs r1, #32 + 800be96: 4849 ldr r0, [pc, #292] @ (800bfbc ) + 800be98: f004 fca1 bl 80107de + } + } + GBT_LockState.motor_state = 1; // motor_on + 800be9c: 4b45 ldr r3, [pc, #276] @ (800bfb4 ) + 800be9e: 2201 movs r2, #1 + 800bea0: 70da strb r2, [r3, #3] + GBT_LockState.last_action_time = current_tick; + 800bea2: 4a44 ldr r2, [pc, #272] @ (800bfb4 ) + 800bea4: 687b ldr r3, [r7, #4] + 800bea6: 6053 str r3, [r2, #4] + break; + 800bea8: e067 b.n 800bf7a + + case 1: // motor_on - мотор включен, ждем LOCK_DELAY + if (current_tick - GBT_LockState.last_action_time >= LOCK_DELAY) { + 800beaa: 4b42 ldr r3, [pc, #264] @ (800bfb4 ) + 800beac: 685b ldr r3, [r3, #4] + 800beae: 687a ldr r2, [r7, #4] + 800beb0: 1ad3 subs r3, r2, r3 + 800beb2: 4a43 ldr r2, [pc, #268] @ (800bfc0 ) + 800beb4: 8812 ldrh r2, [r2, #0] + 800beb6: 4293 cmp r3, r2 + 800beb8: d35c bcc.n 800bf74 + // Выключаем оба пина + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); + 800beba: 2200 movs r2, #0 + 800bebc: 2110 movs r1, #16 + 800bebe: 483f ldr r0, [pc, #252] @ (800bfbc ) + 800bec0: f004 fc8d bl 80107de + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); + 800bec4: 2200 movs r2, #0 + 800bec6: 2120 movs r1, #32 + 800bec8: 483c ldr r0, [pc, #240] @ (800bfbc ) + 800beca: f004 fc88 bl 80107de + GBT_LockState.motor_state = 2; // waiting_off + 800bece: 4b39 ldr r3, [pc, #228] @ (800bfb4 ) + 800bed0: 2202 movs r2, #2 + 800bed2: 70da strb r2, [r3, #3] + GBT_LockState.last_action_time = current_tick; + 800bed4: 4a37 ldr r2, [pc, #220] @ (800bfb4 ) + 800bed6: 687b ldr r3, [r7, #4] + 800bed8: 6053 str r3, [r2, #4] + } + break; + 800beda: e04b b.n 800bf74 + + case 2: // waiting_off - ждем немного перед проверкой состояния + // Небольшая задержка перед проверкой состояния (например, 50мс) + if (current_tick - GBT_LockState.last_action_time >= 50) { + 800bedc: 4b35 ldr r3, [pc, #212] @ (800bfb4 ) + 800bede: 685b ldr r3, [r3, #4] + 800bee0: 687a ldr r2, [r7, #4] + 800bee2: 1ad3 subs r3, r2, r3 + 800bee4: 2b31 cmp r3, #49 @ 0x31 + 800bee6: d947 bls.n 800bf78 + // Проверяем, достигнуто ли требуемое состояние + lock_is_open = GBT_LockGetState() == 0; + 800bee8: f7ff ff4a bl 800bd80 + 800beec: 4603 mov r3, r0 + 800beee: 2b00 cmp r3, #0 + 800bef0: bf0c ite eq + 800bef2: 2301 moveq r3, #1 + 800bef4: 2300 movne r3, #0 + 800bef6: 70fb strb r3, [r7, #3] + bool action_success = (lock_is_open == (GBT_LockState.action_requested == 0)); + 800bef8: 78fb ldrb r3, [r7, #3] + 800befa: 4a2e ldr r2, [pc, #184] @ (800bfb4 ) + 800befc: 7892 ldrb r2, [r2, #2] + 800befe: 2a00 cmp r2, #0 + 800bf00: bf0c ite eq + 800bf02: 2201 moveq r2, #1 + 800bf04: 2200 movne r2, #0 + 800bf06: b2d2 uxtb r2, r2 + 800bf08: 4293 cmp r3, r2 + 800bf0a: bf0c ite eq + 800bf0c: 2301 moveq r3, #1 + 800bf0e: 2300 movne r3, #0 + 800bf10: 707b strb r3, [r7, #1] + + if (action_success) { + 800bf12: 787b ldrb r3, [r7, #1] + 800bf14: 2b00 cmp r3, #0 + 800bf16: d009 beq.n 800bf2c + // Действие выполнено успешно + GBT_LockState.action_requested = 255; // сбрасываем флаг + 800bf18: 4b26 ldr r3, [pc, #152] @ (800bfb4 ) + 800bf1a: 22ff movs r2, #255 @ 0xff + 800bf1c: 709a strb r2, [r3, #2] + GBT_LockState.motor_state = 0; // idle + 800bf1e: 4b25 ldr r3, [pc, #148] @ (800bfb4 ) + 800bf20: 2200 movs r2, #0 + 800bf22: 70da strb r2, [r3, #3] + GBT_LockState.retry_count = 0; + 800bf24: 4b23 ldr r3, [pc, #140] @ (800bfb4 ) + 800bf26: 2200 movs r2, #0 + 800bf28: 721a strb r2, [r3, #8] + // Повторяем попытку + GBT_LockState.motor_state = 0; // возвращаемся к началу + } + } + } + break; + 800bf2a: e025 b.n 800bf78 + GBT_LockState.retry_count++; + 800bf2c: 4b21 ldr r3, [pc, #132] @ (800bfb4 ) + 800bf2e: 7a1b ldrb r3, [r3, #8] + 800bf30: 3301 adds r3, #1 + 800bf32: b2da uxtb r2, r3 + 800bf34: 4b1f ldr r3, [pc, #124] @ (800bfb4 ) + 800bf36: 721a strb r2, [r3, #8] + if (GBT_LockState.retry_count >= MAX_RETRIES) { + 800bf38: 4b1e ldr r3, [pc, #120] @ (800bfb4 ) + 800bf3a: 7a1a ldrb r2, [r3, #8] + 800bf3c: 4b21 ldr r3, [pc, #132] @ (800bfc4 ) + 800bf3e: 781b ldrb r3, [r3, #0] + 800bf40: 429a cmp r2, r3 + 800bf42: d313 bcc.n 800bf6c + GBT_LockState.error = 1; + 800bf44: 4b1b ldr r3, [pc, #108] @ (800bfb4 ) + 800bf46: 2201 movs r2, #1 + 800bf48: 705a strb r2, [r3, #1] + GBT_LockState.error_tick = current_tick; // сохраняем время установки ошибки + 800bf4a: 4a1a ldr r2, [pc, #104] @ (800bfb4 ) + 800bf4c: 687b ldr r3, [r7, #4] + 800bf4e: 60d3 str r3, [r2, #12] + GBT_LockState.action_requested = 0; // пытаемся разблокировать + 800bf50: 4b18 ldr r3, [pc, #96] @ (800bfb4 ) + 800bf52: 2200 movs r2, #0 + 800bf54: 709a strb r2, [r3, #2] + GBT_LockState.motor_state = 0; + 800bf56: 4b17 ldr r3, [pc, #92] @ (800bfb4 ) + 800bf58: 2200 movs r2, #0 + 800bf5a: 70da strb r2, [r3, #3] + GBT_LockState.retry_count = 0; + 800bf5c: 4b15 ldr r3, [pc, #84] @ (800bfb4 ) + 800bf5e: 2200 movs r2, #0 + 800bf60: 721a strb r2, [r3, #8] + log_printf(LOG_ERR, "Lock error\n"); + 800bf62: 4919 ldr r1, [pc, #100] @ (800bfc8 ) + 800bf64: 2004 movs r0, #4 + 800bf66: f7ff fa7d bl 800b464 + break; + 800bf6a: e005 b.n 800bf78 + GBT_LockState.motor_state = 0; // возвращаемся к началу + 800bf6c: 4b11 ldr r3, [pc, #68] @ (800bfb4 ) + 800bf6e: 2200 movs r2, #0 + 800bf70: 70da strb r2, [r3, #3] + break; + 800bf72: e001 b.n 800bf78 + break; + 800bf74: bf00 nop + 800bf76: e01a b.n 800bfae + break; + 800bf78: bf00 nop + switch (GBT_LockState.motor_state) { + 800bf7a: e018 b.n 800bfae + } + } else { + // Состояние соответствует требуемому, сбрасываем флаги + if (GBT_LockState.motor_state != 0) { + 800bf7c: 4b0d ldr r3, [pc, #52] @ (800bfb4 ) + 800bf7e: 78db ldrb r3, [r3, #3] + 800bf80: 2b00 cmp r3, #0 + 800bf82: d00c beq.n 800bf9e + HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); + 800bf84: 2200 movs r2, #0 + 800bf86: 2110 movs r1, #16 + 800bf88: 480c ldr r0, [pc, #48] @ (800bfbc ) + 800bf8a: f004 fc28 bl 80107de + HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); + 800bf8e: 2200 movs r2, #0 + 800bf90: 2120 movs r1, #32 + 800bf92: 480a ldr r0, [pc, #40] @ (800bfbc ) + 800bf94: f004 fc23 bl 80107de + GBT_LockState.motor_state = 0; + 800bf98: 4b06 ldr r3, [pc, #24] @ (800bfb4 ) + 800bf9a: 2200 movs r2, #0 + 800bf9c: 70da strb r2, [r3, #3] + } + GBT_LockState.action_requested = 255; + 800bf9e: 4b05 ldr r3, [pc, #20] @ (800bfb4 ) + 800bfa0: 22ff movs r2, #255 @ 0xff + 800bfa2: 709a strb r2, [r3, #2] + GBT_LockState.retry_count = 0; + 800bfa4: 4b03 ldr r3, [pc, #12] @ (800bfb4 ) + 800bfa6: 2200 movs r2, #0 + 800bfa8: 721a strb r2, [r3, #8] + 800bfaa: e000 b.n 800bfae + return; + 800bfac: bf00 nop + } +} + 800bfae: 3708 adds r7, #8 + 800bfb0: 46bd mov sp, r7 + 800bfb2: bd80 pop {r7, pc} + 800bfb4: 20000008 .word 0x20000008 + 800bfb8: 20000005 .word 0x20000005 + 800bfbc: 40011000 .word 0x40011000 + 800bfc0: 20000006 .word 0x20000006 + 800bfc4: 08016bc7 .word 0x08016bc7 + 800bfc8: 08016ad4 .word 0x08016ad4 + +0800bfcc : + +void GBT_LockResetError(){ + 800bfcc: b580 push {r7, lr} + 800bfce: af00 add r7, sp, #0 + GBT_LockState.error = 0; + 800bfd0: 4b05 ldr r3, [pc, #20] @ (800bfe8 ) + 800bfd2: 2200 movs r2, #0 + 800bfd4: 705a strb r2, [r3, #1] + GBT_LockState.error_tick = 0; + 800bfd6: 4b04 ldr r3, [pc, #16] @ (800bfe8 ) + 800bfd8: 2200 movs r2, #0 + 800bfda: 60da str r2, [r3, #12] + log_printf(LOG_INFO, "Lock error reset\n"); + 800bfdc: 4903 ldr r1, [pc, #12] @ (800bfec ) + 800bfde: 2007 movs r0, #7 + 800bfe0: f7ff fa40 bl 800b464 +} + 800bfe4: bf00 nop + 800bfe6: bd80 pop {r7, pc} + 800bfe8: 20000008 .word 0x20000008 + 800bfec: 08016ae0 .word 0x08016ae0 + +0800bff0 : + +void GBT_ResetErrorTimeout(){ + 800bff0: b580 push {r7, lr} + 800bff2: af00 add r7, sp, #0 + static const uint32_t ERROR_TIMEOUT_MS = 300000; // 5 минут + + if (GBT_LockState.error && GBT_LockState.error_tick != 0) { + 800bff4: 4b0a ldr r3, [pc, #40] @ (800c020 ) + 800bff6: 785b ldrb r3, [r3, #1] + 800bff8: 2b00 cmp r3, #0 + 800bffa: d00f beq.n 800c01c + 800bffc: 4b08 ldr r3, [pc, #32] @ (800c020 ) + 800bffe: 68db ldr r3, [r3, #12] + 800c000: 2b00 cmp r3, #0 + 800c002: d00b beq.n 800c01c + + if ((HAL_GetTick()-GBT_LockState.error_tick) >= ERROR_TIMEOUT_MS) { + 800c004: f002 fbe4 bl 800e7d0 + 800c008: 4602 mov r2, r0 + 800c00a: 4b05 ldr r3, [pc, #20] @ (800c020 ) + 800c00c: 68db ldr r3, [r3, #12] + 800c00e: 1ad2 subs r2, r2, r3 + 800c010: 4b04 ldr r3, [pc, #16] @ (800c024 ) + 800c012: 681b ldr r3, [r3, #0] + 800c014: 429a cmp r2, r3 + 800c016: d301 bcc.n 800c01c + // Прошло 5 минут, сбрасываем ошибку + GBT_LockResetError(); + 800c018: f7ff ffd8 bl 800bfcc + } + } +} + 800c01c: bf00 nop + 800c01e: bd80 pop {r7, pc} + 800c020: 20000008 .word 0x20000008 + 800c024: 08016bc8 .word 0x08016bc8 + +0800c028 : + * bootloader before starting this program. Unfortunately, function + * SystemInit() overwrites this change again. + * @return none. + */ +static void VectorBase_Config(void) +{ + 800c028: b480 push {r7} + 800c02a: af00 add r7, sp, #0 + * c-startup code. + */ + extern const unsigned long g_pfnVectors[]; + + /* Remap the vector table to where the vector table is located for this program. */ + SCB->VTOR = (unsigned long)&g_pfnVectors[0]; + 800c02c: 4b03 ldr r3, [pc, #12] @ (800c03c ) + 800c02e: 4a04 ldr r2, [pc, #16] @ (800c040 ) + 800c030: 609a str r2, [r3, #8] +} + 800c032: bf00 nop + 800c034: 46bd mov sp, r7 + 800c036: bc80 pop {r7} + 800c038: 4770 bx lr + 800c03a: bf00 nop + 800c03c: e000ed00 .word 0xe000ed00 + 800c040: 08008000 .word 0x08008000 + +0800c044 : + +uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ + 800c044: b480 push {r7} + 800c046: b085 sub sp, #20 + 800c048: af00 add r7, sp, #0 + 800c04a: 4603 mov r3, r0 + 800c04c: 460a mov r2, r1 + 800c04e: 71fb strb r3, [r7, #7] + 800c050: 4613 mov r3, r2 + 800c052: 71bb strb r3, [r7, #6] + static uint8_t memory[32]; + if(id > 31) return 0; + 800c054: 79bb ldrb r3, [r7, #6] + 800c056: 2b1f cmp r3, #31 + 800c058: d901 bls.n 800c05e + 800c05a: 2300 movs r3, #0 + 800c05c: e00e b.n 800c07c + uint8_t result = 0; + 800c05e: 2300 movs r3, #0 + 800c060: 73fb strb r3, [r7, #15] + if(memory[id] != flag){ + 800c062: 79bb ldrb r3, [r7, #6] + 800c064: 4a08 ldr r2, [pc, #32] @ (800c088 ) + 800c066: 5cd3 ldrb r3, [r2, r3] + 800c068: 79fa ldrb r2, [r7, #7] + 800c06a: 429a cmp r2, r3 + 800c06c: d001 beq.n 800c072 + result = 1; + 800c06e: 2301 movs r3, #1 + 800c070: 73fb strb r3, [r7, #15] + } + memory[id] = flag; + 800c072: 79bb ldrb r3, [r7, #6] + 800c074: 4904 ldr r1, [pc, #16] @ (800c088 ) + 800c076: 79fa ldrb r2, [r7, #7] + 800c078: 54ca strb r2, [r1, r3] + return result; + 800c07a: 7bfb ldrb r3, [r7, #15] +} + 800c07c: 4618 mov r0, r3 + 800c07e: 3714 adds r7, #20 + 800c080: 46bd mov sp, r7 + 800c082: bc80 pop {r7} + 800c084: 4770 bx lr + 800c086: bf00 nop + 800c088: 20000970 .word 0x20000970 + +0800c08c : + + +void ED_Delay(uint32_t Delay) +{ + 800c08c: b580 push {r7, lr} + 800c08e: b084 sub sp, #16 + 800c090: af00 add r7, sp, #0 + 800c092: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 800c094: f002 fb9c bl 800e7d0 + 800c098: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800c09a: 687b ldr r3, [r7, #4] + 800c09c: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800c09e: 68fb ldr r3, [r7, #12] + 800c0a0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800c0a4: d012 beq.n 800c0cc + { + wait += (uint32_t)(uwTickFreq); + 800c0a6: 4b10 ldr r3, [pc, #64] @ (800c0e8 ) + 800c0a8: 781b ldrb r3, [r3, #0] + 800c0aa: 461a mov r2, r3 + 800c0ac: 68fb ldr r3, [r7, #12] + 800c0ae: 4413 add r3, r2 + 800c0b0: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait){ + 800c0b2: e00b b.n 800c0cc + CONN_CC_ReadStateFiltered(); + 800c0b4: f7fe fffa bl 800b0ac + GBT_ManageLockMotor(); + 800c0b8: f7ff fe8e bl 800bdd8 + CONN_Task(); + 800c0bc: f7fe fe3e bl 800ad3c + GBT_ChargerTask(); + 800c0c0: f7fd feb6 bl 8009e30 + LED_Task(); + 800c0c4: f000 fff4 bl 800d0b0 + SC_Task(); + 800c0c8: f001 f900 bl 800d2cc + while ((HAL_GetTick() - tickstart) < wait){ + 800c0cc: f002 fb80 bl 800e7d0 + 800c0d0: 4602 mov r2, r0 + 800c0d2: 68bb ldr r3, [r7, #8] + 800c0d4: 1ad3 subs r3, r2, r3 + 800c0d6: 68fa ldr r2, [r7, #12] + 800c0d8: 429a cmp r2, r3 + 800c0da: d8eb bhi.n 800c0b4 + // if(huart2.gState != HAL_UART_STATE_BUSY_TX) debug_buffer_send(); // TEST + } +} + 800c0dc: bf00 nop + 800c0de: bf00 nop + 800c0e0: 3710 adds r7, #16 + 800c0e2: 46bd mov sp, r7 + 800c0e4: bd80 pop {r7, pc} + 800c0e6: bf00 nop + 800c0e8: 20000074 .word 0x20000074 + +0800c0ec : + +void StopButtonControl(){ + 800c0ec: b580 push {r7, lr} + 800c0ee: af00 add r7, sp, #0 + + //Charging do nothing + if(!IN_ReadInput(IN_ESTOP)){ + 800c0f0: 2003 movs r0, #3 + 800c0f2: f7fd fb6f bl 80097d4 + 800c0f6: 4603 mov r3, r0 + 800c0f8: 2b00 cmp r3, #0 + 800c0fa: d102 bne.n 800c102 + CONN.connControl = CMD_STOP; + 800c0fc: 4b02 ldr r3, [pc, #8] @ (800c108 ) + 800c0fe: 2201 movs r2, #1 + 800c100: 701a strb r2, [r3, #0] + } + +} + 800c102: bf00 nop + 800c104: bd80 pop {r7, pc} + 800c106: bf00 nop + 800c108: 200002e8 .word 0x200002e8 + +0800c10c
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800c10c: b580 push {r7, lr} + 800c10e: b082 sub sp, #8 + 800c110: af02 add r7, sp, #8 + + /* USER CODE BEGIN 1 */ + VectorBase_Config(); + 800c112: f7ff ff89 bl 800c028 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800c116: f002 fb03 bl 800e720 + + /* USER CODE BEGIN Init */ + HAL_RCC_DeInit(); + 800c11a: f004 fb85 bl 8010828 + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800c11e: f000 f873 bl 800c208 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 800c122: f7ff faa5 bl 800b670 + MX_ADC1_Init(); + 800c126: f7fd fa4f bl 80095c8 + MX_CAN1_Init(); + 800c12a: f7fd fc99 bl 8009a60 + MX_CAN2_Init(); + 800c12e: f7fd fccd bl 8009acc + MX_RTC_Init(); + 800c132: f001 f85b bl 800d1ec + MX_TIM4_Init(); + 800c136: f001 fff1 bl 800e11c + MX_USART2_UART_Init(); + 800c13a: f002 f931 bl 800e3a0 + MX_CRC_Init(); + 800c13e: f7ff f879 bl 800b234 + MX_UART5_Init(); + 800c142: f002 f8d9 bl 800e2f8 + MX_USART1_UART_Init(); + 800c146: f002 f901 bl 800e34c + MX_USART3_UART_Init(); + 800c14a: f002 f953 bl 800e3f4 + /* USER CODE BEGIN 2 */ + Init_Peripheral(); + 800c14e: f7fd fb93 bl 8009878 + LED_Init(); + 800c152: f000 ff8d bl 800d070 + + HAL_Delay(300); + 800c156: f44f 7096 mov.w r0, #300 @ 0x12c + 800c15a: f002 fb43 bl 800e7e4 + GBT_Init(); + 800c15e: f7fd fe29 bl 8009db4 + SC_Init(); + 800c162: f001 f8a7 bl 800d2b4 + log_printf(LOG_INFO, "GBT Charger v%d.%d\n", GBT_CH_VER_MAJOR, GBT_CH_VER_MINOR); + 800c166: 2300 movs r3, #0 + 800c168: 2201 movs r2, #1 + 800c16a: 4922 ldr r1, [pc, #136] @ (800c1f4 ) + 800c16c: 2007 movs r0, #7 + 800c16e: f7ff f979 bl 800b464 + ReadVersion(); + 800c172: f001 f87b bl 800d26c + log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); + 800c176: 4b20 ldr r3, [pc, #128] @ (800c1f8 ) + 800c178: 881b ldrh r3, [r3, #0] + 800c17a: b29b uxth r3, r3 + 800c17c: 461a mov r2, r3 + 800c17e: 491f ldr r1, [pc, #124] @ (800c1fc ) + 800c180: 2007 movs r0, #7 + 800c182: f7ff f96f bl 800b464 + log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); + 800c186: 4b1c ldr r3, [pc, #112] @ (800c1f8 ) + 800c188: 789b ldrb r3, [r3, #2] + 800c18a: 461a mov r2, r3 + 800c18c: 491c ldr r1, [pc, #112] @ (800c200 ) + 800c18e: 2007 movs r0, #7 + 800c190: f7ff f968 bl 800b464 + log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); + 800c194: 4b18 ldr r3, [pc, #96] @ (800c1f8 ) + 800c196: 889b ldrh r3, [r3, #4] + 800c198: b29b uxth r3, r3 + 800c19a: 461a mov r2, r3 + 800c19c: 4b16 ldr r3, [pc, #88] @ (800c1f8 ) + 800c19e: 88db ldrh r3, [r3, #6] + 800c1a0: b29b uxth r3, r3 + 800c1a2: 4619 mov r1, r3 + 800c1a4: 4b14 ldr r3, [pc, #80] @ (800c1f8 ) + 800c1a6: 891b ldrh r3, [r3, #8] + 800c1a8: b29b uxth r3, r3 + 800c1aa: 9300 str r3, [sp, #0] + 800c1ac: 460b mov r3, r1 + 800c1ae: 4915 ldr r1, [pc, #84] @ (800c204 ) + 800c1b0: 2007 movs r0, #7 + 800c1b2: f7ff f957 bl 800b464 + GBT_SetConfig(); + 800c1b6: f7fd fe1b bl 8009df0 + GBT_CAN_ReInit(); + 800c1ba: f7ff fce7 bl 800bb8c + PSU_Init(); + 800c1be: f000 fa7d bl 800c6bc + CONN_Init(); + 800c1c2: f7fd fd97 bl 8009cf4 + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + + PSU_ReadWrite(); + 800c1c6: f000 fb87 bl 800c8d8 + PSU_Task(); + 800c1ca: f000 fc23 bl 800ca14 + ED_Delay(10); + 800c1ce: 200a movs r0, #10 + 800c1d0: f7ff ff5c bl 800c08c + METER_CalculateEnergy(); + 800c1d4: f000 f88e bl 800c2f4 + CONN_Loop(); + 800c1d8: f7fd fda2 bl 8009d20 + LED_Write(); + 800c1dc: f000 fe0e bl 800cdfc + ED_Delay(10); + 800c1e0: 200a movs r0, #10 + 800c1e2: f7ff ff53 bl 800c08c + StopButtonControl(); + 800c1e6: f7ff ff81 bl 800c0ec + ED_Delay(50); + 800c1ea: 2032 movs r0, #50 @ 0x32 + 800c1ec: f7ff ff4e bl 800c08c + { + 800c1f0: bf00 nop + 800c1f2: e7e8 b.n 800c1c6 + 800c1f4: 08016af4 .word 0x08016af4 + 800c1f8: 20000ce8 .word 0x20000ce8 + 800c1fc: 08016b08 .word 0x08016b08 + 800c200: 08016b1c .word 0x08016b1c + 800c204: 08016b30 .word 0x08016b30 + +0800c208 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800c208: b580 push {r7, lr} + 800c20a: b09c sub sp, #112 @ 0x70 + 800c20c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800c20e: f107 0338 add.w r3, r7, #56 @ 0x38 + 800c212: 2238 movs r2, #56 @ 0x38 + 800c214: 2100 movs r1, #0 + 800c216: 4618 mov r0, r3 + 800c218: f007 ff3a bl 8014090 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800c21c: f107 0324 add.w r3, r7, #36 @ 0x24 + 800c220: 2200 movs r2, #0 + 800c222: 601a str r2, [r3, #0] + 800c224: 605a str r2, [r3, #4] + 800c226: 609a str r2, [r3, #8] + 800c228: 60da str r2, [r3, #12] + 800c22a: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 800c22c: 1d3b adds r3, r7, #4 + 800c22e: 2220 movs r2, #32 + 800c230: 2100 movs r1, #0 + 800c232: 4618 mov r0, r3 + 800c234: f007 ff2c bl 8014090 + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; + 800c238: 2305 movs r3, #5 + 800c23a: 63bb str r3, [r7, #56] @ 0x38 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 800c23c: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800c240: 643b str r3, [r7, #64] @ 0x40 + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; + 800c242: 2304 movs r3, #4 + 800c244: 647b str r3, [r7, #68] @ 0x44 + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 800c246: 2301 movs r3, #1 + 800c248: 64bb str r3, [r7, #72] @ 0x48 + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800c24a: 2301 movs r3, #1 + 800c24c: 64fb str r3, [r7, #76] @ 0x4c + RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; + 800c24e: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800c252: 63fb str r3, [r7, #60] @ 0x3c + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 800c254: 2302 movs r3, #2 + 800c256: 65bb str r3, [r7, #88] @ 0x58 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 800c258: f44f 3380 mov.w r3, #65536 @ 0x10000 + 800c25c: 65fb str r3, [r7, #92] @ 0x5c + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + 800c25e: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 + 800c262: 663b str r3, [r7, #96] @ 0x60 + RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; + 800c264: 2302 movs r3, #2 + 800c266: 667b str r3, [r7, #100] @ 0x64 + RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; + 800c268: f44f 63c0 mov.w r3, #1536 @ 0x600 + 800c26c: 66bb str r3, [r7, #104] @ 0x68 + RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; + 800c26e: 2340 movs r3, #64 @ 0x40 + 800c270: 66fb str r3, [r7, #108] @ 0x6c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800c272: f107 0338 add.w r3, r7, #56 @ 0x38 + 800c276: 4618 mov r0, r3 + 800c278: f004 fba6 bl 80109c8 + 800c27c: 4603 mov r3, r0 + 800c27e: 2b00 cmp r3, #0 + 800c280: d001 beq.n 800c286 + { + Error_Handler(); + 800c282: f000 f831 bl 800c2e8 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 800c286: 230f movs r3, #15 + 800c288: 627b str r3, [r7, #36] @ 0x24 + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 800c28a: 2302 movs r3, #2 + 800c28c: 62bb str r3, [r7, #40] @ 0x28 + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800c28e: 2300 movs r3, #0 + 800c290: 62fb str r3, [r7, #44] @ 0x2c + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 800c292: f44f 6380 mov.w r3, #1024 @ 0x400 + 800c296: 633b str r3, [r7, #48] @ 0x30 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 800c298: 2300 movs r3, #0 + 800c29a: 637b str r3, [r7, #52] @ 0x34 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 800c29c: f107 0324 add.w r3, r7, #36 @ 0x24 + 800c2a0: 2102 movs r1, #2 + 800c2a2: 4618 mov r0, r3 + 800c2a4: f004 fea6 bl 8010ff4 + 800c2a8: 4603 mov r3, r0 + 800c2aa: 2b00 cmp r3, #0 + 800c2ac: d001 beq.n 800c2b2 + { + Error_Handler(); + 800c2ae: f000 f81b bl 800c2e8 + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; + 800c2b2: 2303 movs r3, #3 + 800c2b4: 607b str r3, [r7, #4] + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 800c2b6: f44f 7380 mov.w r3, #256 @ 0x100 + 800c2ba: 60bb str r3, [r7, #8] + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + 800c2bc: f44f 4300 mov.w r3, #32768 @ 0x8000 + 800c2c0: 60fb str r3, [r7, #12] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 800c2c2: 1d3b adds r3, r7, #4 + 800c2c4: 4618 mov r0, r3 + 800c2c6: f005 f88b bl 80113e0 + 800c2ca: 4603 mov r3, r0 + 800c2cc: 2b00 cmp r3, #0 + 800c2ce: d001 beq.n 800c2d4 + { + Error_Handler(); + 800c2d0: f000 f80a bl 800c2e8 + } + + /** Configure the Systick interrupt time + */ + __HAL_RCC_PLLI2S_ENABLE(); + 800c2d4: 4b03 ldr r3, [pc, #12] @ (800c2e4 ) + 800c2d6: 2201 movs r2, #1 + 800c2d8: 601a str r2, [r3, #0] +} + 800c2da: bf00 nop + 800c2dc: 3770 adds r7, #112 @ 0x70 + 800c2de: 46bd mov sp, r7 + 800c2e0: bd80 pop {r7, pc} + 800c2e2: bf00 nop + 800c2e4: 42420070 .word 0x42420070 + +0800c2e8 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800c2e8: b480 push {r7} + 800c2ea: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 800c2ec: b672 cpsid i +} + 800c2ee: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800c2f0: bf00 nop + 800c2f2: e7fd b.n 800c2f0 + +0800c2f4 : + + +METER_t METER; + +// Функция для расчета и накопления энергии c дробной частью без счетчиков +void METER_CalculateEnergy() { + 800c2f4: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 800c2f8: b084 sub sp, #16 + 800c2fa: af00 add r7, sp, #0 + // Проверяем, что индекс находится в пределах массива + + METER.online = 0; + 800c2fc: 4b2e ldr r3, [pc, #184] @ (800c3b8 ) + 800c2fe: 2200 movs r2, #0 + 800c300: 711a strb r2, [r3, #4] + + if(CONN.connState == Charging){ + 800c302: 4b2e ldr r3, [pc, #184] @ (800c3bc ) + 800c304: 785b ldrb r3, [r3, #1] + 800c306: 2b08 cmp r3, #8 + 800c308: d104 bne.n 800c314 + METER.enable = 1; + 800c30a: 4b2b ldr r3, [pc, #172] @ (800c3b8 ) + 800c30c: 2201 movs r2, #1 + 800c30e: f883 2024 strb.w r2, [r3, #36] @ 0x24 + 800c312: e003 b.n 800c31c + }else{ + METER.enable = 0; + 800c314: 4b28 ldr r3, [pc, #160] @ (800c3b8 ) + 800c316: 2200 movs r2, #0 + 800c318: f883 2024 strb.w r2, [r3, #36] @ 0x24 + } + + uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах + 800c31c: f002 fa58 bl 800e7d0 + 800c320: 60f8 str r0, [r7, #12] + uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах + 800c322: 4b25 ldr r3, [pc, #148] @ (800c3b8 ) + 800c324: 689b ldr r3, [r3, #8] + 800c326: 68fa ldr r2, [r7, #12] + 800c328: 1ad3 subs r3, r2, r3 + 800c32a: 60bb str r3, [r7, #8] + METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора + 800c32c: 4a22 ldr r2, [pc, #136] @ (800c3b8 ) + 800c32e: 68fb ldr r3, [r7, #12] + 800c330: 6093 str r3, [r2, #8] + uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени + 800c332: 4b22 ldr r3, [pc, #136] @ (800c3bc ) + 800c334: f8d3 3003 ldr.w r3, [r3, #3] + 800c338: 68ba ldr r2, [r7, #8] + 800c33a: fb02 f303 mul.w r3, r2, r3 + 800c33e: 4a20 ldr r2, [pc, #128] @ (800c3c0 ) + 800c340: fba2 2303 umull r2, r3, r2, r3 + 800c344: 099b lsrs r3, r3, #6 + 800c346: 607b str r3, [r7, #4] + + //Расчет энергии теперь идет всегда, смещение берем суммарное + METER.EnergyPSU_Ws += energyWs; + 800c348: 4b1b ldr r3, [pc, #108] @ (800c3b8 ) + 800c34a: e9d3 2304 ldrd r2, r3, [r3, #16] + 800c34e: 6879 ldr r1, [r7, #4] + 800c350: 2000 movs r0, #0 + 800c352: 460c mov r4, r1 + 800c354: 4605 mov r5, r0 + 800c356: eb12 0804 adds.w r8, r2, r4 + 800c35a: eb43 0905 adc.w r9, r3, r5 + 800c35e: 4b16 ldr r3, [pc, #88] @ (800c3b8 ) + 800c360: e9c3 8904 strd r8, r9, [r3, #16] + + // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков + METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час + 800c364: 4b14 ldr r3, [pc, #80] @ (800c3b8 ) + 800c366: e9d3 2304 ldrd r2, r3, [r3, #16] + 800c36a: 4b16 ldr r3, [pc, #88] @ (800c3c4 ) + 800c36c: fba3 2302 umull r2, r3, r3, r2 + 800c370: 0adb lsrs r3, r3, #11 + 800c372: 4a11 ldr r2, [pc, #68] @ (800c3b8 ) + 800c374: 6193 str r3, [r2, #24] + + if(METER.enable) { + 800c376: 4b10 ldr r3, [pc, #64] @ (800c3b8 ) + 800c378: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800c37c: 2b00 cmp r3, #0 + 800c37e: d008 beq.n 800c392 + //enabled state + CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час + 800c380: 4b0d ldr r3, [pc, #52] @ (800c3b8 ) + 800c382: 699a ldr r2, [r3, #24] + 800c384: 4b0c ldr r3, [pc, #48] @ (800c3b8 ) + 800c386: 69db ldr r3, [r3, #28] + 800c388: 1ad3 subs r3, r2, r3 + 800c38a: 4a0c ldr r2, [pc, #48] @ (800c3bc ) + 800c38c: f8c2 3007 str.w r3, [r2, #7] + METER.EnergyOffset = METER.AbsoluteEnergy; + + } + + +} + 800c390: e00c b.n 800c3ac + CONN.Energy = 0; + 800c392: 4b0a ldr r3, [pc, #40] @ (800c3bc ) + 800c394: 2200 movs r2, #0 + 800c396: 71da strb r2, [r3, #7] + 800c398: 2200 movs r2, #0 + 800c39a: 721a strb r2, [r3, #8] + 800c39c: 2200 movs r2, #0 + 800c39e: 725a strb r2, [r3, #9] + 800c3a0: 2200 movs r2, #0 + 800c3a2: 729a strb r2, [r3, #10] + METER.EnergyOffset = METER.AbsoluteEnergy; + 800c3a4: 4b04 ldr r3, [pc, #16] @ (800c3b8 ) + 800c3a6: 699b ldr r3, [r3, #24] + 800c3a8: 4a03 ldr r2, [pc, #12] @ (800c3b8 ) + 800c3aa: 61d3 str r3, [r2, #28] +} + 800c3ac: bf00 nop + 800c3ae: 3710 adds r7, #16 + 800c3b0: 46bd mov sp, r7 + 800c3b2: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800c3b6: bf00 nop + 800c3b8: 20000990 .word 0x20000990 + 800c3bc: 200002e8 .word 0x200002e8 + 800c3c0: 10624dd3 .word 0x10624dd3 + 800c3c4: 91a2b3c5 .word 0x91a2b3c5 + +0800c3c8 : + +uint32_t can_lastpacket; + +extern CAN_HandleTypeDef hcan2; + +static void PSU_SwitchState(PSU_State_t state){ + 800c3c8: b580 push {r7, lr} + 800c3ca: b082 sub sp, #8 + 800c3cc: af00 add r7, sp, #0 + 800c3ce: 4603 mov r3, r0 + 800c3d0: 71fb strb r3, [r7, #7] + PSU0.state = state; + 800c3d2: 4a06 ldr r2, [pc, #24] @ (800c3ec ) + 800c3d4: 79fb ldrb r3, [r7, #7] + 800c3d6: 71d3 strb r3, [r2, #7] + PSU0.statetick = HAL_GetTick(); + 800c3d8: f002 f9fa bl 800e7d0 + 800c3dc: 4603 mov r3, r0 + 800c3de: 4a03 ldr r2, [pc, #12] @ (800c3ec ) + 800c3e0: 6113 str r3, [r2, #16] +} + 800c3e2: bf00 nop + 800c3e4: 3708 adds r7, #8 + 800c3e6: 46bd mov sp, r7 + 800c3e8: bd80 pop {r7, pc} + 800c3ea: bf00 nop + 800c3ec: 200009fc .word 0x200009fc + +0800c3f0 : + +static uint32_t PSU_StateTime(void){ + 800c3f0: b580 push {r7, lr} + 800c3f2: af00 add r7, sp, #0 + return HAL_GetTick() - PSU0.statetick; + 800c3f4: f002 f9ec bl 800e7d0 + 800c3f8: 4602 mov r2, r0 + 800c3fa: 4b02 ldr r3, [pc, #8] @ (800c404 ) + 800c3fc: 691b ldr r3, [r3, #16] + 800c3fe: 1ad3 subs r3, r2, r3 +} + 800c400: 4618 mov r0, r3 + 800c402: bd80 pop {r7, pc} + 800c404: 200009fc .word 0x200009fc + +0800c408 : + +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ + 800c408: b580 push {r7, lr} + 800c40a: b084 sub sp, #16 + 800c40c: af00 add r7, sp, #0 + 800c40e: 6078 str r0, [r7, #4] + + static CAN_RxHeaderTypeDef RxHeader; + static uint8_t RxData[8] = {0,}; + CanId_t CanId; + + if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) + 800c410: 4b88 ldr r3, [pc, #544] @ (800c634 ) + 800c412: 4a89 ldr r2, [pc, #548] @ (800c638 ) + 800c414: 2101 movs r1, #1 + 800c416: 6878 ldr r0, [r7, #4] + 800c418: f003 fa7a bl 800f910 + 800c41c: 4603 mov r3, r0 + 800c41e: 2b00 cmp r3, #0 + 800c420: f040 8104 bne.w 800c62c + { + memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); + 800c424: 4b84 ldr r3, [pc, #528] @ (800c638 ) + 800c426: 685b ldr r3, [r3, #4] + 800c428: 60bb str r3, [r7, #8] + + /* Для DC30 поддерживается только один силовой модуль (source == 0) */ + if(CanId.source != 0) return; + 800c42a: 7a3b ldrb r3, [r7, #8] + 800c42c: 2b00 cmp r3, #0 + 800c42e: f040 80fc bne.w 800c62a + can_lastpacket = HAL_GetTick(); + 800c432: f002 f9cd bl 800e7d0 + 800c436: 4603 mov r3, r0 + 800c438: 4a80 ldr r2, [pc, #512] @ (800c63c ) + 800c43a: 6013 str r3, [r2, #0] + + if(CanId.command==0x02){ + 800c43c: 7abb ldrb r3, [r7, #10] + 800c43e: f003 033f and.w r3, r3, #63 @ 0x3f + 800c442: b2db uxtb r3, r3 + 800c444: 2b02 cmp r3, #2 + 800c446: d105 bne.n 800c454 + memcpy(&PSU_02, RxData, 8); + 800c448: 4b7d ldr r3, [pc, #500] @ (800c640 ) + 800c44a: 4a7a ldr r2, [pc, #488] @ (800c634 ) + 800c44c: e892 0003 ldmia.w r2, {r0, r1} + 800c450: e883 0003 stmia.w r3, {r0, r1} + } + if(CanId.command==0x04){ + 800c454: 7abb ldrb r3, [r7, #10] + 800c456: f003 033f and.w r3, r3, #63 @ 0x3f + 800c45a: b2db uxtb r3, r3 + 800c45c: 2b04 cmp r3, #4 + 800c45e: d119 bne.n 800c494 + memcpy(&PSU_04, RxData, 8); + 800c460: 4b78 ldr r3, [pc, #480] @ (800c644 ) + 800c462: 4a74 ldr r2, [pc, #464] @ (800c634 ) + 800c464: e892 0003 ldmia.w r2, {r0, r1} + 800c468: e883 0003 stmia.w r3, {r0, r1} + + PSU0.tempAmbient = PSU_04.moduleTemperature; + 800c46c: 4b75 ldr r3, [pc, #468] @ (800c644 ) + 800c46e: 791b ldrb r3, [r3, #4] + 800c470: 461a mov r2, r3 + 800c472: 4b75 ldr r3, [pc, #468] @ (800c648 ) + 800c474: 61da str r2, [r3, #28] + PSU0.status0.raw = PSU_04.modularForm0; + 800c476: 4b73 ldr r3, [pc, #460] @ (800c644 ) + 800c478: 7a1a ldrb r2, [r3, #8] + 800c47a: 4b73 ldr r3, [pc, #460] @ (800c648 ) + 800c47c: f883 2020 strb.w r2, [r3, #32] + PSU0.status1.raw = PSU_04.modularForm1; + 800c480: 4b70 ldr r3, [pc, #448] @ (800c644 ) + 800c482: 79da ldrb r2, [r3, #7] + 800c484: 4b70 ldr r3, [pc, #448] @ (800c648 ) + 800c486: f883 2021 strb.w r2, [r3, #33] @ 0x21 + PSU0.status2.raw = PSU_04.modularForm2; + 800c48a: 4b6e ldr r3, [pc, #440] @ (800c644 ) + 800c48c: 799a ldrb r2, [r3, #6] + 800c48e: 4b6e ldr r3, [pc, #440] @ (800c648 ) + 800c490: f883 2022 strb.w r2, [r3, #34] @ 0x22 + } + if(CanId.command==0x06){ + 800c494: 7abb ldrb r3, [r7, #10] + 800c496: f003 033f and.w r3, r3, #63 @ 0x3f + 800c49a: b2db uxtb r3, r3 + 800c49c: 2b06 cmp r3, #6 + 800c49e: d123 bne.n 800c4e8 + memcpy(&PSU_06, RxData, 8); + 800c4a0: 4b6a ldr r3, [pc, #424] @ (800c64c ) + 800c4a2: 4a64 ldr r2, [pc, #400] @ (800c634 ) + 800c4a4: e892 0003 ldmia.w r2, {r0, r1} + 800c4a8: e883 0003 stmia.w r3, {r0, r1} + + PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); + 800c4ac: 4b67 ldr r3, [pc, #412] @ (800c64c ) + 800c4ae: 785b ldrb r3, [r3, #1] + 800c4b0: 461a mov r2, r3 + 800c4b2: 4b66 ldr r3, [pc, #408] @ (800c64c ) + 800c4b4: 781b ldrb r3, [r3, #0] + 800c4b6: 021b lsls r3, r3, #8 + 800c4b8: 4413 add r3, r2 + 800c4ba: 461a mov r2, r3 + 800c4bc: 4b63 ldr r3, [pc, #396] @ (800c64c ) + 800c4be: 609a str r2, [r3, #8] + PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); + 800c4c0: 4b62 ldr r3, [pc, #392] @ (800c64c ) + 800c4c2: 78db ldrb r3, [r3, #3] + 800c4c4: 461a mov r2, r3 + 800c4c6: 4b61 ldr r3, [pc, #388] @ (800c64c ) + 800c4c8: 789b ldrb r3, [r3, #2] + 800c4ca: 021b lsls r3, r3, #8 + 800c4cc: 4413 add r3, r2 + 800c4ce: 461a mov r2, r3 + 800c4d0: 4b5e ldr r3, [pc, #376] @ (800c64c ) + 800c4d2: 60da str r2, [r3, #12] + PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); + 800c4d4: 4b5d ldr r3, [pc, #372] @ (800c64c ) + 800c4d6: 795b ldrb r3, [r3, #5] + 800c4d8: 461a mov r2, r3 + 800c4da: 4b5c ldr r3, [pc, #368] @ (800c64c ) + 800c4dc: 791b ldrb r3, [r3, #4] + 800c4de: 021b lsls r3, r3, #8 + 800c4e0: 4413 add r3, r2 + 800c4e2: 461a mov r2, r3 + 800c4e4: 4b59 ldr r3, [pc, #356] @ (800c64c ) + 800c4e6: 611a str r2, [r3, #16] + + } + if(CanId.command==0x08){ + 800c4e8: 7abb ldrb r3, [r7, #10] + 800c4ea: f003 033f and.w r3, r3, #63 @ 0x3f + 800c4ee: b2db uxtb r3, r3 + 800c4f0: 2b08 cmp r3, #8 + 800c4f2: d105 bne.n 800c500 + memcpy(&PSU_08, RxData, 8); + 800c4f4: 4b56 ldr r3, [pc, #344] @ (800c650 ) + 800c4f6: 4a4f ldr r2, [pc, #316] @ (800c634 ) + 800c4f8: e892 0003 ldmia.w r2, {r0, r1} + 800c4fc: e883 0003 stmia.w r3, {r0, r1} + } + if(CanId.command==0x09){ + 800c500: 7abb ldrb r3, [r7, #10] + 800c502: f003 033f and.w r3, r3, #63 @ 0x3f + 800c506: b2db uxtb r3, r3 + 800c508: 2b09 cmp r3, #9 + 800c50a: f040 808f bne.w 800c62c + + memcpy(&PSU_09, RxData, 8); + 800c50e: 4b51 ldr r3, [pc, #324] @ (800c654 ) + 800c510: 4a48 ldr r2, [pc, #288] @ (800c634 ) + 800c512: e892 0003 ldmia.w r2, {r0, r1} + 800c516: e883 0003 stmia.w r3, {r0, r1} + PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; + 800c51a: 4b4e ldr r3, [pc, #312] @ (800c654 ) + 800c51c: 79db ldrb r3, [r3, #7] + 800c51e: 461a mov r2, r3 + 800c520: 4b4c ldr r3, [pc, #304] @ (800c654 ) + 800c522: 60da str r2, [r3, #12] + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; + 800c524: 4b4b ldr r3, [pc, #300] @ (800c654 ) + 800c526: 68da ldr r2, [r3, #12] + 800c528: 4b4a ldr r3, [pc, #296] @ (800c654 ) + 800c52a: 799b ldrb r3, [r3, #6] + 800c52c: 021b lsls r3, r3, #8 + 800c52e: 4313 orrs r3, r2 + 800c530: 4a48 ldr r2, [pc, #288] @ (800c654 ) + 800c532: 60d3 str r3, [r2, #12] + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; + 800c534: 4b47 ldr r3, [pc, #284] @ (800c654 ) + 800c536: 68da ldr r2, [r3, #12] + 800c538: 4b46 ldr r3, [pc, #280] @ (800c654 ) + 800c53a: 795b ldrb r3, [r3, #5] + 800c53c: 041b lsls r3, r3, #16 + 800c53e: 4313 orrs r3, r2 + 800c540: 4a44 ldr r2, [pc, #272] @ (800c654 ) + 800c542: 60d3 str r3, [r2, #12] + PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; + 800c544: 4b43 ldr r3, [pc, #268] @ (800c654 ) + 800c546: 68da ldr r2, [r3, #12] + 800c548: 4b42 ldr r3, [pc, #264] @ (800c654 ) + 800c54a: 791b ldrb r3, [r3, #4] + 800c54c: 061b lsls r3, r3, #24 + 800c54e: 4313 orrs r3, r2 + 800c550: 4a40 ldr r2, [pc, #256] @ (800c654 ) + 800c552: 60d3 str r3, [r2, #12] + + PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; + 800c554: 4b3f ldr r3, [pc, #252] @ (800c654 ) + 800c556: 78db ldrb r3, [r3, #3] + 800c558: 461a mov r2, r3 + 800c55a: 4b3e ldr r3, [pc, #248] @ (800c654 ) + 800c55c: 609a str r2, [r3, #8] + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; + 800c55e: 4b3d ldr r3, [pc, #244] @ (800c654 ) + 800c560: 689a ldr r2, [r3, #8] + 800c562: 4b3c ldr r3, [pc, #240] @ (800c654 ) + 800c564: 789b ldrb r3, [r3, #2] + 800c566: 021b lsls r3, r3, #8 + 800c568: 4313 orrs r3, r2 + 800c56a: 4a3a ldr r2, [pc, #232] @ (800c654 ) + 800c56c: 6093 str r3, [r2, #8] + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; + 800c56e: 4b39 ldr r3, [pc, #228] @ (800c654 ) + 800c570: 689a ldr r2, [r3, #8] + 800c572: 4b38 ldr r3, [pc, #224] @ (800c654 ) + 800c574: 785b ldrb r3, [r3, #1] + 800c576: 041b lsls r3, r3, #16 + 800c578: 4313 orrs r3, r2 + 800c57a: 4a36 ldr r2, [pc, #216] @ (800c654 ) + 800c57c: 6093 str r3, [r2, #8] + PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; + 800c57e: 4b35 ldr r3, [pc, #212] @ (800c654 ) + 800c580: 689a ldr r2, [r3, #8] + 800c582: 4b34 ldr r3, [pc, #208] @ (800c654 ) + 800c584: 781b ldrb r3, [r3, #0] + 800c586: 061b lsls r3, r3, #24 + 800c588: 4313 orrs r3, r2 + 800c58a: 4a32 ldr r2, [pc, #200] @ (800c654 ) + 800c58c: 6093 str r3, [r2, #8] + + // PSU_09 -> PSU -> CONN (один модуль) + { + uint16_t v = PSU_09.moduleNVoltage / 1000; + 800c58e: 4b31 ldr r3, [pc, #196] @ (800c654 ) + 800c590: 689b ldr r3, [r3, #8] + 800c592: 4a31 ldr r2, [pc, #196] @ (800c658 ) + 800c594: fba2 2303 umull r2, r3, r2, r3 + 800c598: 099b lsrs r3, r3, #6 + 800c59a: 81fb strh r3, [r7, #14] + int16_t i = PSU_09.moduleNCurrent / 100; + 800c59c: 4b2d ldr r3, [pc, #180] @ (800c654 ) + 800c59e: 68db ldr r3, [r3, #12] + 800c5a0: 4a2e ldr r2, [pc, #184] @ (800c65c ) + 800c5a2: fba2 2303 umull r2, r3, r2, r3 + 800c5a6: 095b lsrs r3, r3, #5 + 800c5a8: 81bb strh r3, [r7, #12] + + // Обновляем модель PSU0 по телеметрии + PSU0.outputVoltage = v; + 800c5aa: 4a27 ldr r2, [pc, #156] @ (800c648 ) + 800c5ac: 89fb ldrh r3, [r7, #14] + 800c5ae: 8053 strh r3, [r2, #2] + PSU0.outputCurrent = i; + 800c5b0: 4a25 ldr r2, [pc, #148] @ (800c648 ) + 800c5b2: 89bb ldrh r3, [r7, #12] + 800c5b4: 8093 strh r3, [r2, #4] + PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); + 800c5b6: 89fb ldrh r3, [r7, #14] + 800c5b8: 2b13 cmp r3, #19 + 800c5ba: bf8c ite hi + 800c5bc: 2301 movhi r3, #1 + 800c5be: 2300 movls r3, #0 + 800c5c0: b2db uxtb r3, r3 + 800c5c2: 461a mov r2, r3 + 800c5c4: 4b20 ldr r3, [pc, #128] @ (800c648 ) + 800c5c6: 729a strb r2, [r3, #10] + PSU0.online = 1; + 800c5c8: 4b1f ldr r3, [pc, #124] @ (800c648 ) + 800c5ca: 2201 movs r2, #1 + 800c5cc: 721a strb r2, [r3, #8] + PSU0.temperature = PSU_04.moduleTemperature; + 800c5ce: 4b1d ldr r3, [pc, #116] @ (800c644 ) + 800c5d0: 791a ldrb r2, [r3, #4] + 800c5d2: 4b1d ldr r3, [pc, #116] @ (800c648 ) + 800c5d4: 719a strb r2, [r3, #6] + + // Экспортируем значения из PSU0 в CONN только, + // когда модуль хотя бы в состоянии READY и выше + if(PSU0.state >= PSU_READY){ + 800c5d6: 4b1c ldr r3, [pc, #112] @ (800c648 ) + 800c5d8: 79db ldrb r3, [r3, #7] + 800c5da: 2b01 cmp r3, #1 + 800c5dc: d926 bls.n 800c62c + CONN.MeasuredVoltage = PSU0.outputVoltage; + 800c5de: 4b1a ldr r3, [pc, #104] @ (800c648 ) + 800c5e0: 885a ldrh r2, [r3, #2] + 800c5e2: 4b1f ldr r3, [pc, #124] @ (800c660 ) + 800c5e4: f8a3 2013 strh.w r2, [r3, #19] + CONN.MeasuredCurrent = PSU0.outputCurrent; + 800c5e8: 4b17 ldr r3, [pc, #92] @ (800c648 ) + 800c5ea: f9b3 3004 ldrsh.w r3, [r3, #4] + 800c5ee: b29a uxth r2, r3 + 800c5f0: 4b1b ldr r3, [pc, #108] @ (800c660 ) + 800c5f2: f8a3 2015 strh.w r2, [r3, #21] + CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; + 800c5f6: 4b1a ldr r3, [pc, #104] @ (800c660 ) + 800c5f8: f8b3 3015 ldrh.w r3, [r3, #21] + 800c5fc: b29b uxth r3, r3 + 800c5fe: 461a mov r2, r3 + 800c600: 4b17 ldr r3, [pc, #92] @ (800c660 ) + 800c602: f8b3 3013 ldrh.w r3, [r3, #19] + 800c606: b29b uxth r3, r3 + 800c608: fb02 f303 mul.w r3, r2, r3 + 800c60c: 4a15 ldr r2, [pc, #84] @ (800c664 ) + 800c60e: fb82 1203 smull r1, r2, r2, r3 + 800c612: 1092 asrs r2, r2, #2 + 800c614: 17db asrs r3, r3, #31 + 800c616: 1ad3 subs r3, r2, r3 + 800c618: 461a mov r2, r3 + 800c61a: 4b11 ldr r3, [pc, #68] @ (800c660 ) + 800c61c: f8c3 2003 str.w r2, [r3, #3] + CONN.outputEnabled = PSU0.PSU_enabled; + 800c620: 4b09 ldr r3, [pc, #36] @ (800c648 ) + 800c622: 7a9a ldrb r2, [r3, #10] + 800c624: 4b0e ldr r3, [pc, #56] @ (800c660 ) + 800c626: 761a strb r2, [r3, #24] + 800c628: e000 b.n 800c62c + if(CanId.source != 0) return; + 800c62a: bf00 nop + } + } + } + } +} + 800c62c: 3710 adds r7, #16 + 800c62e: 46bd mov sp, r7 + 800c630: bd80 pop {r7, pc} + 800c632: bf00 nop + 800c634: 20000a40 .word 0x20000a40 + 800c638: 20000a24 .word 0x20000a24 + 800c63c: 20000a20 .word 0x20000a20 + 800c640: 200009b8 .word 0x200009b8 + 800c644: 200009c4 .word 0x200009c4 + 800c648: 200009fc .word 0x200009fc + 800c64c: 200009d0 .word 0x200009d0 + 800c650: 200009e4 .word 0x200009e4 + 800c654: 200009ec .word 0x200009ec + 800c658: 10624dd3 .word 0x10624dd3 + 800c65c: 51eb851f .word 0x51eb851f + 800c660: 200002e8 .word 0x200002e8 + 800c664: 66666667 .word 0x66666667 + +0800c668 : + +void PSU_CAN_FilterInit(){ + 800c668: b580 push {r7, lr} + 800c66a: b08a sub sp, #40 @ 0x28 + 800c66c: af00 add r7, sp, #0 + CAN_FilterTypeDef sFilterConfig; + + sFilterConfig.FilterBank = 14; + 800c66e: 230e movs r3, #14 + 800c670: 617b str r3, [r7, #20] + sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; + 800c672: 2300 movs r3, #0 + 800c674: 61bb str r3, [r7, #24] + sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; + 800c676: 2301 movs r3, #1 + 800c678: 61fb str r3, [r7, #28] + sFilterConfig.FilterIdHigh = 0x0000; + 800c67a: 2300 movs r3, #0 + 800c67c: 603b str r3, [r7, #0] + sFilterConfig.FilterIdLow = 0x0000; + 800c67e: 2300 movs r3, #0 + 800c680: 607b str r3, [r7, #4] + sFilterConfig.FilterMaskIdHigh = 0x0000; + 800c682: 2300 movs r3, #0 + 800c684: 60bb str r3, [r7, #8] + sFilterConfig.FilterMaskIdLow = 0x0000; + 800c686: 2300 movs r3, #0 + 800c688: 60fb str r3, [r7, #12] + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; + 800c68a: 2300 movs r3, #0 + 800c68c: 613b str r3, [r7, #16] + sFilterConfig.FilterActivation = ENABLE; + 800c68e: 2301 movs r3, #1 + 800c690: 623b str r3, [r7, #32] + + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; + 800c692: 2301 movs r3, #1 + 800c694: 613b str r3, [r7, #16] + sFilterConfig.SlaveStartFilterBank = 14; + 800c696: 230e movs r3, #14 + 800c698: 627b str r3, [r7, #36] @ 0x24 + + + if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) + 800c69a: 463b mov r3, r7 + 800c69c: 4619 mov r1, r3 + 800c69e: 4806 ldr r0, [pc, #24] @ (800c6b8 ) + 800c6a0: f002 fec6 bl 800f430 + 800c6a4: 4603 mov r3, r0 + 800c6a6: 2b00 cmp r3, #0 + 800c6a8: d001 beq.n 800c6ae + { + Error_Handler(); + 800c6aa: f7ff fe1d bl 800c2e8 + } +} + 800c6ae: bf00 nop + 800c6b0: 3728 adds r7, #40 @ 0x28 + 800c6b2: 46bd mov sp, r7 + 800c6b4: bd80 pop {r7, pc} + 800c6b6: bf00 nop + 800c6b8: 200002bc .word 0x200002bc + +0800c6bc : + +void PSU_Init(){ + 800c6bc: b580 push {r7, lr} + 800c6be: af00 add r7, sp, #0 + + HAL_CAN_Stop(&hcan2); + 800c6c0: 4813 ldr r0, [pc, #76] @ (800c710 ) + 800c6c2: f002 ffd9 bl 800f678 + MX_CAN2_Init(); + 800c6c6: f7fd fa01 bl 8009acc + PSU_CAN_FilterInit(); + 800c6ca: f7ff ffcd bl 800c668 + HAL_CAN_Start(&hcan2); + 800c6ce: 4810 ldr r0, [pc, #64] @ (800c710 ) + 800c6d0: f002 ff8e bl 800f5f0 + HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); + 800c6d4: 2110 movs r1, #16 + 800c6d6: 480e ldr r0, [pc, #56] @ (800c710 ) + 800c6d8: f003 fa3b bl 800fb52 + memset(&PSU0, 0, sizeof(PSU0)); + 800c6dc: 2224 movs r2, #36 @ 0x24 + 800c6de: 2100 movs r1, #0 + 800c6e0: 480c ldr r0, [pc, #48] @ (800c714 ) + 800c6e2: f007 fcd5 bl 8014090 + PSU0.state = PSU_UNREADY; + 800c6e6: 4b0b ldr r3, [pc, #44] @ (800c714 ) + 800c6e8: 2200 movs r2, #0 + 800c6ea: 71da strb r2, [r3, #7] + PSU0.statetick = HAL_GetTick(); + 800c6ec: f002 f870 bl 800e7d0 + 800c6f0: 4603 mov r3, r0 + 800c6f2: 4a08 ldr r2, [pc, #32] @ (800c714 ) + 800c6f4: 6113 str r3, [r2, #16] + + PSU0.power_limit = PSU_MAX_POWER; // kW + 800c6f6: 4b07 ldr r3, [pc, #28] @ (800c714 ) + 800c6f8: f247 5230 movw r2, #30000 @ 0x7530 + 800c6fc: 615a str r2, [r3, #20] + PSU0.hv_mode = 0; + 800c6fe: 4b05 ldr r3, [pc, #20] @ (800c714 ) + 800c700: 2200 movs r2, #0 + 800c702: 761a strb r2, [r3, #24] + + PSU_Enable(0, 0); + 800c704: 2100 movs r1, #0 + 800c706: 2000 movs r0, #0 + 800c708: f000 f806 bl 800c718 +} + 800c70c: bf00 nop + 800c70e: bd80 pop {r7, pc} + 800c710: 200002bc .word 0x200002bc + 800c714: 200009fc .word 0x200009fc + +0800c718 : + +void PSU_Enable(uint8_t addr, uint8_t enable){ + 800c718: b580 push {r7, lr} + 800c71a: b084 sub sp, #16 + 800c71c: af00 add r7, sp, #0 + 800c71e: 4603 mov r3, r0 + 800c720: 460a mov r2, r1 + 800c722: 71fb strb r3, [r7, #7] + 800c724: 4613 mov r3, r2 + 800c726: 71bb strb r3, [r7, #6] + PSU_1A_t data; + memset(&data, 0, sizeof(data)); + 800c728: f107 0308 add.w r3, r7, #8 + 800c72c: 2208 movs r2, #8 + 800c72e: 2100 movs r1, #0 + 800c730: 4618 mov r0, r3 + 800c732: f007 fcad bl 8014090 + /* Для DC30 поддерживается только один модуль с адресом 0 */ + if(addr != 0) return; + 800c736: 79fb ldrb r3, [r7, #7] + 800c738: 2b00 cmp r3, #0 + 800c73a: d115 bne.n 800c768 + if(PSU0.online == 0) return; + 800c73c: 4b0d ldr r3, [pc, #52] @ (800c774 ) + 800c73e: 7a1b ldrb r3, [r3, #8] + 800c740: 2b00 cmp r3, #0 + 800c742: d013 beq.n 800c76c + + data.enable = !enable; + 800c744: 79bb ldrb r3, [r7, #6] + 800c746: 2b00 cmp r3, #0 + 800c748: bf0c ite eq + 800c74a: 2301 moveq r3, #1 + 800c74c: 2300 movne r3, #0 + 800c74e: b2db uxtb r3, r3 + 800c750: 723b strb r3, [r7, #8] + PSU_SendCmd(0xF0, addr, 0x1A, &data); + 800c752: 79f9 ldrb r1, [r7, #7] + 800c754: f107 0308 add.w r3, r7, #8 + 800c758: 221a movs r2, #26 + 800c75a: 20f0 movs r0, #240 @ 0xf0 + 800c75c: f000 f866 bl 800c82c + ED_Delay(CAN_DELAY); + 800c760: 2014 movs r0, #20 + 800c762: f7ff fc93 bl 800c08c + 800c766: e002 b.n 800c76e + if(addr != 0) return; + 800c768: bf00 nop + 800c76a: e000 b.n 800c76e + if(PSU0.online == 0) return; + 800c76c: bf00 nop +} + 800c76e: 3710 adds r7, #16 + 800c770: 46bd mov sp, r7 + 800c772: bd80 pop {r7, pc} + 800c774: 200009fc .word 0x200009fc + +0800c778 : + memset(&data, 0, sizeof(data)); + data.enable = !enable; + if(addr != 0) return; + PSU_SendCmd(0xF0, addr, 0x1D, &data); +} +void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ + 800c778: b580 push {r7, lr} + 800c77a: b086 sub sp, #24 + 800c77c: af00 add r7, sp, #0 + 800c77e: 4603 mov r3, r0 + 800c780: 71fb strb r3, [r7, #7] + 800c782: 460b mov r3, r1 + 800c784: 80bb strh r3, [r7, #4] + 800c786: 4613 mov r3, r2 + 800c788: 807b strh r3, [r7, #2] + PSU_1C_t data; + memset(&data, 0, sizeof(data)); + 800c78a: f107 0308 add.w r3, r7, #8 + 800c78e: 2208 movs r2, #8 + 800c790: 2100 movs r1, #0 + 800c792: 4618 mov r0, r3 + 800c794: f007 fc7c bl 8014090 + + if(addr != 0) return; + 800c798: 79fb ldrb r3, [r7, #7] + 800c79a: 2b00 cmp r3, #0 + 800c79c: d140 bne.n 800c820 + + if(voltage + 800c7a4: 2396 movs r3, #150 @ 0x96 + 800c7a6: 80bb strh r3, [r7, #4] + + if((PSU0.hv_mode==0) && voltage>499) voltage = 499; + 800c7a8: 4b1f ldr r3, [pc, #124] @ (800c828 ) + 800c7aa: 7e1b ldrb r3, [r3, #24] + 800c7ac: 2b00 cmp r3, #0 + 800c7ae: d106 bne.n 800c7be + 800c7b0: 88bb ldrh r3, [r7, #4] + 800c7b2: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 + 800c7b6: d302 bcc.n 800c7be + 800c7b8: f240 13f3 movw r3, #499 @ 0x1f3 + 800c7bc: 80bb strh r3, [r7, #4] + + uint32_t current_ma = current * 100; + 800c7be: 887b ldrh r3, [r7, #2] + 800c7c0: 2264 movs r2, #100 @ 0x64 + 800c7c2: fb02 f303 mul.w r3, r2, r3 + 800c7c6: 617b str r3, [r7, #20] + uint32_t voltage_mv = voltage * 1000; + 800c7c8: 88bb ldrh r3, [r7, #4] + 800c7ca: f44f 727a mov.w r2, #1000 @ 0x3e8 + 800c7ce: fb02 f303 mul.w r3, r2, r3 + 800c7d2: 613b str r3, [r7, #16] + + data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; + 800c7d4: 697b ldr r3, [r7, #20] + 800c7d6: 0e1b lsrs r3, r3, #24 + 800c7d8: b2db uxtb r3, r3 + 800c7da: 733b strb r3, [r7, #12] + data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; + 800c7dc: 697b ldr r3, [r7, #20] + 800c7de: 0c1b lsrs r3, r3, #16 + 800c7e0: b2db uxtb r3, r3 + 800c7e2: 737b strb r3, [r7, #13] + data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; + 800c7e4: 697b ldr r3, [r7, #20] + 800c7e6: 0a1b lsrs r3, r3, #8 + 800c7e8: b2db uxtb r3, r3 + 800c7ea: 73bb strb r3, [r7, #14] + data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; + 800c7ec: 697b ldr r3, [r7, #20] + 800c7ee: b2db uxtb r3, r3 + 800c7f0: 73fb strb r3, [r7, #15] + + data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; + 800c7f2: 693b ldr r3, [r7, #16] + 800c7f4: 0e1b lsrs r3, r3, #24 + 800c7f6: b2db uxtb r3, r3 + 800c7f8: 723b strb r3, [r7, #8] + data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; + 800c7fa: 693b ldr r3, [r7, #16] + 800c7fc: 0c1b lsrs r3, r3, #16 + 800c7fe: b2db uxtb r3, r3 + 800c800: 727b strb r3, [r7, #9] + data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; + 800c802: 693b ldr r3, [r7, #16] + 800c804: 0a1b lsrs r3, r3, #8 + 800c806: b2db uxtb r3, r3 + 800c808: 72bb strb r3, [r7, #10] + data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; + 800c80a: 693b ldr r3, [r7, #16] + 800c80c: b2db uxtb r3, r3 + 800c80e: 72fb strb r3, [r7, #11] + + PSU_SendCmd(0xF0, addr, 0x1C, &data); + 800c810: 79f9 ldrb r1, [r7, #7] + 800c812: f107 0308 add.w r3, r7, #8 + 800c816: 221c movs r2, #28 + 800c818: 20f0 movs r0, #240 @ 0xf0 + 800c81a: f000 f807 bl 800c82c + 800c81e: e000 b.n 800c822 + if(addr != 0) return; + 800c820: bf00 nop + +} + 800c822: 3718 adds r7, #24 + 800c824: 46bd mov sp, r7 + 800c826: bd80 pop {r7, pc} + 800c828: 200009fc .word 0x200009fc + +0800c82c : + +void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ + 800c82c: b580 push {r7, lr} + 800c82e: b08c sub sp, #48 @ 0x30 + 800c830: af00 add r7, sp, #0 + 800c832: 603b str r3, [r7, #0] + 800c834: 4603 mov r3, r0 + 800c836: 71fb strb r3, [r7, #7] + 800c838: 460b mov r3, r1 + 800c83a: 71bb strb r3, [r7, #6] + 800c83c: 4613 mov r3, r2 + 800c83e: 717b strb r3, [r7, #5] + CanId_t CanId; + CanId.source = source; + 800c840: 79fb ldrb r3, [r7, #7] + 800c842: f887 3028 strb.w r3, [r7, #40] @ 0x28 + CanId.destination = destination; + 800c846: 79bb ldrb r3, [r7, #6] + 800c848: f887 3029 strb.w r3, [r7, #41] @ 0x29 + CanId.command = cmd; + 800c84c: 797b ldrb r3, [r7, #5] + 800c84e: f003 033f and.w r3, r3, #63 @ 0x3f + 800c852: b2da uxtb r2, r3 + 800c854: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 800c858: f362 0305 bfi r3, r2, #0, #6 + 800c85c: f887 302a strb.w r3, [r7, #42] @ 0x2a + CanId.device = 0x0A; + 800c860: 8d7b ldrh r3, [r7, #42] @ 0x2a + 800c862: 220a movs r2, #10 + 800c864: f362 1389 bfi r3, r2, #6, #4 + 800c868: 857b strh r3, [r7, #42] @ 0x2a + + int8_t retry_counter = 10; + 800c86a: 230a movs r3, #10 + 800c86c: f887 302f strb.w r3, [r7, #47] @ 0x2f + CAN_TxHeaderTypeDef tx_header; + uint32_t tx_mailbox; + HAL_StatusTypeDef CAN_result; + + memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); + 800c870: 6abb ldr r3, [r7, #40] @ 0x28 + 800c872: 617b str r3, [r7, #20] + + tx_header.RTR = CAN_RTR_DATA; + 800c874: 2300 movs r3, #0 + 800c876: 61fb str r3, [r7, #28] + tx_header.IDE = CAN_ID_EXT; + 800c878: 2304 movs r3, #4 + 800c87a: 61bb str r3, [r7, #24] + tx_header.DLC = 8; + 800c87c: 2308 movs r3, #8 + 800c87e: 623b str r3, [r7, #32] + + while(retry_counter>0){ //если буфер полон, ждем пока он освободится + 800c880: e01e b.n 800c8c0 + if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ + 800c882: 4814 ldr r0, [pc, #80] @ (800c8d4 ) + 800c884: f003 f810 bl 800f8a8 + 800c888: 4603 mov r3, r0 + 800c88a: 2b00 cmp r3, #0 + 800c88c: d00e beq.n 800c8ac + /* отправка сообщения */ + CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); + 800c88e: f107 030c add.w r3, r7, #12 + 800c892: f107 0110 add.w r1, r7, #16 + 800c896: 683a ldr r2, [r7, #0] + 800c898: 480e ldr r0, [pc, #56] @ (800c8d4 ) + 800c89a: f002 ff36 bl 800f70a + 800c89e: 4603 mov r3, r0 + 800c8a0: f887 302e strb.w r3, [r7, #46] @ 0x2e + + /* если отправка удалась, выход */ + if(CAN_result == HAL_OK) { + 800c8a4: f897 302e ldrb.w r3, [r7, #46] @ 0x2e + 800c8a8: 2b00 cmp r3, #0 + 800c8aa: d00e beq.n 800c8ca + return; + retry_counter = 0; + } + } + ED_Delay(1); + 800c8ac: 2001 movs r0, #1 + 800c8ae: f7ff fbed bl 800c08c + + retry_counter--; + 800c8b2: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f + 800c8b6: b2db uxtb r3, r3 + 800c8b8: 3b01 subs r3, #1 + 800c8ba: b2db uxtb r3, r3 + 800c8bc: f887 302f strb.w r3, [r7, #47] @ 0x2f + while(retry_counter>0){ //если буфер полон, ждем пока он освободится + 800c8c0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f + 800c8c4: 2b00 cmp r3, #0 + 800c8c6: dcdc bgt.n 800c882 + 800c8c8: e000 b.n 800c8cc + return; + 800c8ca: bf00 nop + } + +} + 800c8cc: 3730 adds r7, #48 @ 0x30 + 800c8ce: 46bd mov sp, r7 + 800c8d0: bd80 pop {r7, pc} + 800c8d2: bf00 nop + 800c8d4: 200002bc .word 0x200002bc + +0800c8d8 : +uint32_t max(uint32_t a, uint32_t b){ + if(a>b) return a; + else return b; +} + +void PSU_ReadWrite(){ + 800c8d8: b580 push {r7, lr} + 800c8da: b082 sub sp, #8 + 800c8dc: af00 add r7, sp, #0 + + uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; + 800c8de: 463b mov r3, r7 + 800c8e0: 2200 movs r2, #0 + 800c8e2: 601a str r2, [r3, #0] + 800c8e4: 605a str r2, [r3, #4] + + PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); + 800c8e6: 463b mov r3, r7 + 800c8e8: 2204 movs r2, #4 + 800c8ea: 2100 movs r1, #0 + 800c8ec: 20f0 movs r0, #240 @ 0xf0 + 800c8ee: f7ff ff9d bl 800c82c + 800c8f2: 2014 movs r0, #20 + 800c8f4: f7ff fbca bl 800c08c + PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); + 800c8f8: 463b mov r3, r7 + 800c8fa: 2206 movs r2, #6 + 800c8fc: 2100 movs r1, #0 + 800c8fe: 20f0 movs r0, #240 @ 0xf0 + 800c900: f7ff ff94 bl 800c82c + 800c904: 2014 movs r0, #20 + 800c906: f7ff fbc1 bl 800c08c + // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); + PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); + 800c90a: 463b mov r3, r7 + 800c90c: 2209 movs r2, #9 + 800c90e: 2100 movs r1, #0 + 800c910: 20f0 movs r0, #240 @ 0xf0 + 800c912: f7ff ff8b bl 800c82c + 800c916: 2014 movs r0, #20 + 800c918: f7ff fbb8 bl 800c08c + + // Power Limit + if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ + 800c91c: 4b39 ldr r3, [pc, #228] @ (800ca04 ) + 800c91e: f8b3 301b ldrh.w r3, [r3, #27] + 800c922: b29b uxth r3, r3 + 800c924: 4a38 ldr r2, [pc, #224] @ (800ca08 ) + 800c926: fba2 2303 umull r2, r3, r2, r3 + 800c92a: 08db lsrs r3, r3, #3 + 800c92c: b29b uxth r3, r3 + 800c92e: 461a mov r2, r3 + 800c930: 4b34 ldr r3, [pc, #208] @ (800ca04 ) + 800c932: f8b3 3013 ldrh.w r3, [r3, #19] + 800c936: b29b uxth r3, r3 + 800c938: fb02 f303 mul.w r3, r2, r3 + 800c93c: 461a mov r2, r3 + 800c93e: 4b33 ldr r3, [pc, #204] @ (800ca0c ) + 800c940: 695b ldr r3, [r3, #20] + 800c942: 429a cmp r2, r3 + 800c944: d911 bls.n 800c96a + CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; + 800c946: 4b31 ldr r3, [pc, #196] @ (800ca0c ) + 800c948: 695a ldr r2, [r3, #20] + 800c94a: 4613 mov r3, r2 + 800c94c: 009b lsls r3, r3, #2 + 800c94e: 4413 add r3, r2 + 800c950: 005b lsls r3, r3, #1 + 800c952: 461a mov r2, r3 + 800c954: 4b2b ldr r3, [pc, #172] @ (800ca04 ) + 800c956: f8b3 3013 ldrh.w r3, [r3, #19] + 800c95a: b29b uxth r3, r3 + 800c95c: fbb2 f3f3 udiv r3, r2, r3 + 800c960: b29a uxth r2, r3 + 800c962: 4b28 ldr r3, [pc, #160] @ (800ca04 ) + 800c964: f8a3 2011 strh.w r2, [r3, #17] + 800c968: e006 b.n 800c978 + }else{ + CONN.RequestedCurrent = CONN.WantedCurrent; + 800c96a: 4b26 ldr r3, [pc, #152] @ (800ca04 ) + 800c96c: f8b3 301b ldrh.w r3, [r3, #27] + 800c970: b29a uxth r2, r3 + 800c972: 4b24 ldr r3, [pc, #144] @ (800ca04 ) + 800c974: f8a3 2011 strh.w r2, [r3, #17] + } + + if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ + 800c978: 4b22 ldr r3, [pc, #136] @ (800ca04 ) + 800c97a: f8b3 3011 ldrh.w r3, [r3, #17] + 800c97e: b29b uxth r3, r3 + 800c980: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800c984: d908 bls.n 800c998 + CONN.RequestedCurrent = PSU_MAX_CURRENT*10; + 800c986: 4b1f ldr r3, [pc, #124] @ (800ca04 ) + 800c988: 2200 movs r2, #0 + 800c98a: f062 0217 orn r2, r2, #23 + 800c98e: 745a strb r2, [r3, #17] + 800c990: 2200 movs r2, #0 + 800c992: f042 0203 orr.w r2, r2, #3 + 800c996: 749a strb r2, [r3, #18] + } + CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; + 800c998: 4b1a ldr r3, [pc, #104] @ (800ca04 ) + 800c99a: f8b3 3011 ldrh.w r3, [r3, #17] + 800c99e: b29b uxth r3, r3 + 800c9a0: 461a mov r2, r3 + 800c9a2: 4b18 ldr r3, [pc, #96] @ (800ca04 ) + 800c9a4: f8b3 300f ldrh.w r3, [r3, #15] + 800c9a8: b29b uxth r3, r3 + 800c9aa: fb02 f303 mul.w r3, r2, r3 + 800c9ae: 4a18 ldr r2, [pc, #96] @ (800ca10 ) + 800c9b0: fb82 1203 smull r1, r2, r2, r3 + 800c9b4: 1092 asrs r2, r2, #2 + 800c9b6: 17db asrs r3, r3, #31 + 800c9b8: 1ad3 subs r3, r2, r3 + 800c9ba: 461a mov r2, r3 + 800c9bc: 4b11 ldr r3, [pc, #68] @ (800ca04 ) + 800c9be: f8c3 200b str.w r2, [r3, #11] + + + if(PSU0.ready){ + 800c9c2: 4b12 ldr r3, [pc, #72] @ (800ca0c ) + 800c9c4: 7a5b ldrb r3, [r3, #9] + 800c9c6: 2b00 cmp r3, #0 + 800c9c8: d018 beq.n 800c9fc + PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode + 800c9ca: 4b0e ldr r3, [pc, #56] @ (800ca04 ) + 800c9cc: f8b3 300f ldrh.w r3, [r3, #15] + 800c9d0: b29b uxth r3, r3 + 800c9d2: 4a0c ldr r2, [pc, #48] @ (800ca04 ) + 800c9d4: f8b2 2011 ldrh.w r2, [r2, #17] + 800c9d8: b292 uxth r2, r2 + 800c9da: 4619 mov r1, r3 + 800c9dc: 2000 movs r0, #0 + 800c9de: f7ff fecb bl 800c778 + ED_Delay(CAN_DELAY); + 800c9e2: 2014 movs r0, #20 + 800c9e4: f7ff fb52 bl 800c08c + if(CONN.MeasuredVoltage>490) PSU0.hv_mode = 1; + 800c9e8: 4b06 ldr r3, [pc, #24] @ (800ca04 ) + 800c9ea: f8b3 3013 ldrh.w r3, [r3, #19] + 800c9ee: b29b uxth r3, r3 + 800c9f0: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea + 800c9f4: d902 bls.n 800c9fc + 800c9f6: 4b05 ldr r3, [pc, #20] @ (800ca0c ) + 800c9f8: 2201 movs r2, #1 + 800c9fa: 761a strb r2, [r3, #24] + } + + // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need + // ED_Delay(CAN_DELAY); + +} + 800c9fc: bf00 nop + 800c9fe: 3708 adds r7, #8 + 800ca00: 46bd mov sp, r7 + 800ca02: bd80 pop {r7, pc} + 800ca04: 200002e8 .word 0x200002e8 + 800ca08: cccccccd .word 0xcccccccd + 800ca0c: 200009fc .word 0x200009fc + 800ca10: 66666667 .word 0x66666667 + +0800ca14 : + +void PSU_Task(void){ + 800ca14: b598 push {r3, r4, r7, lr} + 800ca16: af00 add r7, sp, #0 + static uint32_t psu_on_tick = 0; + static uint32_t dc_on_tick = 0; + static uint32_t cont_ok_tick = 0; + + // Обновляем ONLINE/READY по таймауту + if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ + 800ca18: f001 feda bl 800e7d0 + 800ca1c: 4602 mov r2, r0 + 800ca1e: 4bb4 ldr r3, [pc, #720] @ (800ccf0 ) + 800ca20: 681b ldr r3, [r3, #0] + 800ca22: 1ad3 subs r3, r2, r3 + 800ca24: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 + 800ca28: d920 bls.n 800ca6c + PSU0.online = 0; + 800ca2a: 4bb2 ldr r3, [pc, #712] @ (800ccf4 ) + 800ca2c: 2200 movs r2, #0 + 800ca2e: 721a strb r2, [r3, #8] + PSU0.PSU_enabled = 0; + 800ca30: 4bb0 ldr r3, [pc, #704] @ (800ccf4 ) + 800ca32: 2200 movs r2, #0 + 800ca34: 729a strb r2, [r3, #10] + PSU_04.moduleTemperature = 0; + 800ca36: 4bb0 ldr r3, [pc, #704] @ (800ccf8 ) + 800ca38: 2200 movs r2, #0 + 800ca3a: 711a strb r2, [r3, #4] + PSU_04.modularForm0 = 0; + 800ca3c: 4bae ldr r3, [pc, #696] @ (800ccf8 ) + 800ca3e: 2200 movs r2, #0 + 800ca40: 721a strb r2, [r3, #8] + PSU_04.modularForm1 = 0; + 800ca42: 4bad ldr r3, [pc, #692] @ (800ccf8 ) + 800ca44: 2200 movs r2, #0 + 800ca46: 71da strb r2, [r3, #7] + PSU_04.modularForm2 = 0; + 800ca48: 4bab ldr r3, [pc, #684] @ (800ccf8 ) + 800ca4a: 2200 movs r2, #0 + 800ca4c: 719a strb r2, [r3, #6] + PSU_06.VAB = 0; + 800ca4e: 4bab ldr r3, [pc, #684] @ (800ccfc ) + 800ca50: 2200 movs r2, #0 + 800ca52: 609a str r2, [r3, #8] + PSU_06.VBC = 0; + 800ca54: 4ba9 ldr r3, [pc, #676] @ (800ccfc ) + 800ca56: 2200 movs r2, #0 + 800ca58: 60da str r2, [r3, #12] + PSU_06.VCA = 0; + 800ca5a: 4ba8 ldr r3, [pc, #672] @ (800ccfc ) + 800ca5c: 2200 movs r2, #0 + 800ca5e: 611a str r2, [r3, #16] + PSU_09.moduleNCurrent = 0; + 800ca60: 4ba7 ldr r3, [pc, #668] @ (800cd00 ) + 800ca62: 2200 movs r2, #0 + 800ca64: 60da str r2, [r3, #12] + PSU_09.moduleNVoltage = 0; + 800ca66: 4ba6 ldr r3, [pc, #664] @ (800cd00 ) + 800ca68: 2200 movs r2, #0 + 800ca6a: 609a str r2, [r3, #8] + } + if(!PSU0.online || !PSU0.enableAC){ + 800ca6c: 4ba1 ldr r3, [pc, #644] @ (800ccf4 ) + 800ca6e: 7a1b ldrb r3, [r3, #8] + 800ca70: 2b00 cmp r3, #0 + 800ca72: d003 beq.n 800ca7c + 800ca74: 4b9f ldr r3, [pc, #636] @ (800ccf4 ) + 800ca76: 781b ldrb r3, [r3, #0] + 800ca78: 2b00 cmp r3, #0 + 800ca7a: d10c bne.n 800ca96 + CONN.MeasuredVoltage = 0; + 800ca7c: 4ba1 ldr r3, [pc, #644] @ (800cd04 ) + 800ca7e: 2200 movs r2, #0 + 800ca80: 74da strb r2, [r3, #19] + 800ca82: 2200 movs r2, #0 + 800ca84: 751a strb r2, [r3, #20] + CONN.MeasuredCurrent = 0; + 800ca86: 4b9f ldr r3, [pc, #636] @ (800cd04 ) + 800ca88: 2200 movs r2, #0 + 800ca8a: 755a strb r2, [r3, #21] + 800ca8c: 2200 movs r2, #0 + 800ca8e: 759a strb r2, [r3, #22] + CONN.outputEnabled = 0; + 800ca90: 4b9c ldr r3, [pc, #624] @ (800cd04 ) + 800ca92: 2200 movs r2, #0 + 800ca94: 761a strb r2, [r3, #24] + } + + // Управление AC-контактором с задержкой отключения 1 минута + if(CONN.EvConnected){ + 800ca96: 4b9b ldr r3, [pc, #620] @ (800cd04 ) + 800ca98: 7f9b ldrb r3, [r3, #30] + 800ca9a: 2b00 cmp r3, #0 + 800ca9c: d00c beq.n 800cab8 + RELAY_Write(RELAY_AC, 1); + 800ca9e: 2101 movs r1, #1 + 800caa0: 2004 movs r0, #4 + 800caa2: f7fc fe23 bl 80096ec + psu_on_tick = HAL_GetTick(); + 800caa6: f001 fe93 bl 800e7d0 + 800caaa: 4603 mov r3, r0 + 800caac: 4a96 ldr r2, [pc, #600] @ (800cd08 ) + 800caae: 6013 str r3, [r2, #0] + PSU0.enableAC = 1; + 800cab0: 4b90 ldr r3, [pc, #576] @ (800ccf4 ) + 800cab2: 2201 movs r2, #1 + 800cab4: 701a strb r2, [r3, #0] + 800cab6: e010 b.n 800cada + }else{ + if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ + 800cab8: f001 fe8a bl 800e7d0 + 800cabc: 4602 mov r2, r0 + 800cabe: 4b92 ldr r3, [pc, #584] @ (800cd08 ) + 800cac0: 681b ldr r3, [r3, #0] + 800cac2: 1ad3 subs r3, r2, r3 + 800cac4: f64e 2260 movw r2, #60000 @ 0xea60 + 800cac8: 4293 cmp r3, r2 + 800caca: d906 bls.n 800cada + RELAY_Write(RELAY_AC, 0); + 800cacc: 2100 movs r1, #0 + 800cace: 2004 movs r0, #4 + 800cad0: f7fc fe0c bl 80096ec + PSU0.enableAC = 0; + 800cad4: 4b87 ldr r3, [pc, #540] @ (800ccf4 ) + 800cad6: 2200 movs r2, #0 + 800cad8: 701a strb r2, [r3, #0] + } + } + + // Текущее состояние DC-контактора по обратной связи + PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); + 800cada: 2005 movs r0, #5 + 800cadc: f7fc fe7a bl 80097d4 + 800cae0: 4603 mov r3, r0 + 800cae2: 461a mov r2, r3 + 800cae4: 4b83 ldr r3, [pc, #524] @ (800ccf4 ) + 800cae6: 72da strb r2, [r3, #11] + + // Обновляем ready с учётом ошибок + if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ + 800cae8: 4b82 ldr r3, [pc, #520] @ (800ccf4 ) + 800caea: 7a1b ldrb r3, [r3, #8] + 800caec: 2b00 cmp r3, #0 + 800caee: d007 beq.n 800cb00 + 800caf0: 4b80 ldr r3, [pc, #512] @ (800ccf4 ) + 800caf2: 7b1b ldrb r3, [r3, #12] + 800caf4: 2b00 cmp r3, #0 + 800caf6: d103 bne.n 800cb00 + 800caf8: 4b7e ldr r3, [pc, #504] @ (800ccf4 ) + 800cafa: 781b ldrb r3, [r3, #0] + 800cafc: 2b00 cmp r3, #0 + 800cafe: d102 bne.n 800cb06 + // PSU0.ready = 1; + }else{ + PSU0.ready = 0; + 800cb00: 4b7c ldr r3, [pc, #496] @ (800ccf4 ) + 800cb02: 2200 movs r2, #0 + 800cb04: 725a strb r2, [r3, #9] + } + + switch(PSU0.state){ + 800cb06: 4b7b ldr r3, [pc, #492] @ (800ccf4 ) + 800cb08: 79db ldrb r3, [r3, #7] + 800cb0a: 2b09 cmp r3, #9 + 800cb0c: f200 8155 bhi.w 800cdba + 800cb10: a201 add r2, pc, #4 @ (adr r2, 800cb18 ) + 800cb12: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800cb16: bf00 nop + 800cb18: 0800cb41 .word 0x0800cb41 + 800cb1c: 0800cb75 .word 0x0800cb75 + 800cb20: 0800cb91 .word 0x0800cb91 + 800cb24: 0800cbc9 .word 0x0800cbc9 + 800cb28: 0800cc17 .word 0x0800cc17 + 800cb2c: 0800cc59 .word 0x0800cc59 + 800cb30: 0800ccc3 .word 0x0800ccc3 + 800cb34: 0800cd6d .word 0x0800cd6d + 800cb38: 0800cd1d .word 0x0800cd1d + 800cb3c: 0800cda7 .word 0x0800cda7 + case PSU_UNREADY: + PSU0.enableOutput = 0; + 800cb40: 4b6c ldr r3, [pc, #432] @ (800ccf4 ) + 800cb42: 2200 movs r2, #0 + 800cb44: 705a strb r2, [r3, #1] + RELAY_Write(RELAY_DC, 0); + 800cb46: 2100 movs r1, #0 + 800cb48: 2003 movs r0, #3 + 800cb4a: f7fc fdcf bl 80096ec + if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ + 800cb4e: 4b69 ldr r3, [pc, #420] @ (800ccf4 ) + 800cb50: 7a1b ldrb r3, [r3, #8] + 800cb52: 2b00 cmp r3, #0 + 800cb54: f000 8135 beq.w 800cdc2 + 800cb58: 4b66 ldr r3, [pc, #408] @ (800ccf4 ) + 800cb5a: 781b ldrb r3, [r3, #0] + 800cb5c: 2b00 cmp r3, #0 + 800cb5e: f000 8130 beq.w 800cdc2 + 800cb62: 4b64 ldr r3, [pc, #400] @ (800ccf4 ) + 800cb64: 7b1b ldrb r3, [r3, #12] + 800cb66: 2b00 cmp r3, #0 + 800cb68: f040 812b bne.w 800cdc2 + PSU_SwitchState(PSU_INITIALIZING); + 800cb6c: 2001 movs r0, #1 + 800cb6e: f7ff fc2b bl 800c3c8 + } + break; + 800cb72: e126 b.n 800cdc2 + + case PSU_INITIALIZING: + if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize + 800cb74: f7ff fc3c bl 800c3f0 + 800cb78: 4603 mov r3, r0 + 800cb7a: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 + 800cb7e: f240 8122 bls.w 800cdc6 + PSU0.ready = 1; + 800cb82: 4b5c ldr r3, [pc, #368] @ (800ccf4 ) + 800cb84: 2201 movs r2, #1 + 800cb86: 725a strb r2, [r3, #9] + PSU_SwitchState(PSU_READY); + 800cb88: 2002 movs r0, #2 + 800cb8a: f7ff fc1d bl 800c3c8 + } + break; + 800cb8e: e11a b.n 800cdc6 + + case PSU_READY: + // модуль готов, но выключен + PSU0.hv_mode = 0; + 800cb90: 4b58 ldr r3, [pc, #352] @ (800ccf4 ) + 800cb92: 2200 movs r2, #0 + 800cb94: 761a strb r2, [r3, #24] + + RELAY_Write(RELAY_DC, 0); + 800cb96: 2100 movs r1, #0 + 800cb98: 2003 movs r0, #3 + 800cb9a: f7fc fda7 bl 80096ec + if(!PSU0.ready){ + 800cb9e: 4b55 ldr r3, [pc, #340] @ (800ccf4 ) + 800cba0: 7a5b ldrb r3, [r3, #9] + 800cba2: 2b00 cmp r3, #0 + 800cba4: d103 bne.n 800cbae + PSU_SwitchState(PSU_UNREADY); + 800cba6: 2000 movs r0, #0 + 800cba8: f7ff fc0e bl 800c3c8 + break; + 800cbac: e11c b.n 800cde8 + } + if(CONN.EnableOutput){ + 800cbae: 4b55 ldr r3, [pc, #340] @ (800cd04 ) + 800cbb0: 7ddb ldrb r3, [r3, #23] + 800cbb2: 2b00 cmp r3, #0 + 800cbb4: f000 8109 beq.w 800cdca + PSU_Enable(0, 1); + 800cbb8: 2101 movs r1, #1 + 800cbba: 2000 movs r0, #0 + 800cbbc: f7ff fdac bl 800c718 + PSU_SwitchState(PSU_WAIT_ACK_ON); + 800cbc0: 2003 movs r0, #3 + 800cbc2: f7ff fc01 bl 800c3c8 + } + break; + 800cbc6: e100 b.n 800cdca + + case PSU_WAIT_ACK_ON: + + if(PSU0.PSU_enabled && PSU0.ready){ + 800cbc8: 4b4a ldr r3, [pc, #296] @ (800ccf4 ) + 800cbca: 7a9b ldrb r3, [r3, #10] + 800cbcc: 2b00 cmp r3, #0 + 800cbce: d00c beq.n 800cbea + 800cbd0: 4b48 ldr r3, [pc, #288] @ (800ccf4 ) + 800cbd2: 7a5b ldrb r3, [r3, #9] + 800cbd4: 2b00 cmp r3, #0 + 800cbd6: d008 beq.n 800cbea + dc_on_tick = HAL_GetTick(); + 800cbd8: f001 fdfa bl 800e7d0 + 800cbdc: 4603 mov r3, r0 + 800cbde: 4a4b ldr r2, [pc, #300] @ (800cd0c ) + 800cbe0: 6013 str r3, [r2, #0] + PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); + 800cbe2: 2004 movs r0, #4 + 800cbe4: f7ff fbf0 bl 800c3c8 + PSU0.psu_fault = 1; + CONN.chargingError = CONN_ERR_PSU_FAULT; + PSU_SwitchState(PSU_UNREADY); + log_printf(LOG_ERR, "PSU on timeout\n"); + } + break; + 800cbe8: e0f1 b.n 800cdce + }else if(PSU_StateTime() > 10000){ + 800cbea: f7ff fc01 bl 800c3f0 + 800cbee: 4603 mov r3, r0 + 800cbf0: f242 7210 movw r2, #10000 @ 0x2710 + 800cbf4: 4293 cmp r3, r2 + 800cbf6: f240 80ea bls.w 800cdce + PSU0.psu_fault = 1; + 800cbfa: 4b3e ldr r3, [pc, #248] @ (800ccf4 ) + 800cbfc: 2201 movs r2, #1 + 800cbfe: 735a strb r2, [r3, #13] + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800cc00: 4b40 ldr r3, [pc, #256] @ (800cd04 ) + 800cc02: 220a movs r2, #10 + 800cc04: 775a strb r2, [r3, #29] + PSU_SwitchState(PSU_UNREADY); + 800cc06: 2000 movs r0, #0 + 800cc08: f7ff fbde bl 800c3c8 + log_printf(LOG_ERR, "PSU on timeout\n"); + 800cc0c: 4940 ldr r1, [pc, #256] @ (800cd10 ) + 800cc0e: 2004 movs r0, #4 + 800cc10: f7fe fc28 bl 800b464 + break; + 800cc14: e0db b.n 800cdce + + case PSU_CONT_WAIT_ACK_ON: + // замыкаем DC-контактор и ждём подтверждение + RELAY_Write(RELAY_DC, 1); + 800cc16: 2101 movs r1, #1 + 800cc18: 2003 movs r0, #3 + 800cc1a: f7fc fd67 bl 80096ec + if(PSU0.CONT_enabled){ + 800cc1e: 4b35 ldr r3, [pc, #212] @ (800ccf4 ) + 800cc20: 7adb ldrb r3, [r3, #11] + 800cc22: 2b00 cmp r3, #0 + 800cc24: d003 beq.n 800cc2e + PSU_SwitchState(PSU_CONNECTED); + 800cc26: 2005 movs r0, #5 + 800cc28: f7ff fbce bl 800c3c8 + PSU0.cont_fault = 1; + CONN.chargingError = CONN_ERR_CONTACTOR; + PSU_SwitchState(PSU_CURRENT_DROP); + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + } + break; + 800cc2c: e0d1 b.n 800cdd2 + }else if(PSU_StateTime() > 1000){ + 800cc2e: f7ff fbdf bl 800c3f0 + 800cc32: 4603 mov r3, r0 + 800cc34: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800cc38: f240 80cb bls.w 800cdd2 + PSU0.cont_fault = 1; + 800cc3c: 4b2d ldr r3, [pc, #180] @ (800ccf4 ) + 800cc3e: 2201 movs r2, #1 + 800cc40: 731a strb r2, [r3, #12] + CONN.chargingError = CONN_ERR_CONTACTOR; + 800cc42: 4b30 ldr r3, [pc, #192] @ (800cd04 ) + 800cc44: 2207 movs r2, #7 + 800cc46: 775a strb r2, [r3, #29] + PSU_SwitchState(PSU_CURRENT_DROP); + 800cc48: 2006 movs r0, #6 + 800cc4a: f7ff fbbd bl 800c3c8 + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + 800cc4e: 4931 ldr r1, [pc, #196] @ (800cd14 ) + 800cc50: 2004 movs r0, #4 + 800cc52: f7fe fc07 bl 800b464 + break; + 800cc56: e0bc b.n 800cdd2 + + case PSU_CONNECTED: + // Основное рабочее состояние + if(!CONN.EnableOutput || !PSU0.ready){ + 800cc58: 4b2a ldr r3, [pc, #168] @ (800cd04 ) + 800cc5a: 7ddb ldrb r3, [r3, #23] + 800cc5c: 2b00 cmp r3, #0 + 800cc5e: d003 beq.n 800cc68 + 800cc60: 4b24 ldr r3, [pc, #144] @ (800ccf4 ) + 800cc62: 7a5b ldrb r3, [r3, #9] + 800cc64: 2b00 cmp r3, #0 + 800cc66: d103 bne.n 800cc70 + PSU_SwitchState(PSU_CURRENT_DROP); + 800cc68: 2006 movs r0, #6 + 800cc6a: f7ff fbad bl 800c3c8 + break; + 800cc6e: e0bb b.n 800cde8 + } + // контроль контактора: 1 c таймаут + if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ + 800cc70: 2005 movs r0, #5 + 800cc72: f7fc fdaf bl 80097d4 + 800cc76: 4603 mov r3, r0 + 800cc78: 461c mov r4, r3 + 800cc7a: 2003 movs r0, #3 + 800cc7c: f7fc fd9a bl 80097b4 + 800cc80: 4603 mov r3, r0 + 800cc82: 429c cmp r4, r3 + 800cc84: d017 beq.n 800ccb6 + if((HAL_GetTick() - cont_ok_tick) > 1000){ + 800cc86: f001 fda3 bl 800e7d0 + 800cc8a: 4602 mov r2, r0 + 800cc8c: 4b22 ldr r3, [pc, #136] @ (800cd18 ) + 800cc8e: 681b ldr r3, [r3, #0] + 800cc90: 1ad3 subs r3, r2, r3 + 800cc92: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800cc96: f240 809e bls.w 800cdd6 + CONN.chargingError = CONN_ERR_CONTACTOR; + 800cc9a: 4b1a ldr r3, [pc, #104] @ (800cd04 ) + 800cc9c: 2207 movs r2, #7 + 800cc9e: 775a strb r2, [r3, #29] + PSU0.cont_fault = 1; + 800cca0: 4b14 ldr r3, [pc, #80] @ (800ccf4 ) + 800cca2: 2201 movs r2, #1 + 800cca4: 731a strb r2, [r3, #12] + PSU_SwitchState(PSU_CURRENT_DROP); + 800cca6: 2006 movs r0, #6 + 800cca8: f7ff fb8e bl 800c3c8 + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + 800ccac: 4919 ldr r1, [pc, #100] @ (800cd14 ) + 800ccae: 2004 movs r0, #4 + 800ccb0: f7fe fbd8 bl 800b464 + } + }else{ + cont_ok_tick = HAL_GetTick(); + } + break; + 800ccb4: e08f b.n 800cdd6 + cont_ok_tick = HAL_GetTick(); + 800ccb6: f001 fd8b bl 800e7d0 + 800ccba: 4603 mov r3, r0 + 800ccbc: 4a16 ldr r2, [pc, #88] @ (800cd18 ) + 800ccbe: 6013 str r3, [r2, #0] + break; + 800ccc0: e089 b.n 800cdd6 + + case PSU_CURRENT_DROP: + // снижаем ток до нуля перед отключением DC + CONN.RequestedCurrent = 0; + 800ccc2: 4b10 ldr r3, [pc, #64] @ (800cd04 ) + 800ccc4: 2200 movs r2, #0 + 800ccc6: 745a strb r2, [r3, #17] + 800ccc8: 2200 movs r2, #0 + 800ccca: 749a strb r2, [r3, #18] + + // если ток действительно упал или вышло время, отключаем DC + if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ + 800cccc: 4b0d ldr r3, [pc, #52] @ (800cd04 ) + 800ccce: f8b3 3015 ldrh.w r3, [r3, #21] + 800ccd2: b29b uxth r3, r3 + 800ccd4: 2b1d cmp r3, #29 + 800ccd6: d906 bls.n 800cce6 + 800ccd8: f7ff fb8a bl 800c3f0 + 800ccdc: 4603 mov r3, r0 + 800ccde: f241 3288 movw r2, #5000 @ 0x1388 + 800cce2: 4293 cmp r3, r2 + 800cce4: d979 bls.n 800cdda + PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); + 800cce6: 2008 movs r0, #8 + 800cce8: f7ff fb6e bl 800c3c8 + } + break; + 800ccec: e075 b.n 800cdda + 800ccee: bf00 nop + 800ccf0: 20000a20 .word 0x20000a20 + 800ccf4: 200009fc .word 0x200009fc + 800ccf8: 200009c4 .word 0x200009c4 + 800ccfc: 200009d0 .word 0x200009d0 + 800cd00: 200009ec .word 0x200009ec + 800cd04: 200002e8 .word 0x200002e8 + 800cd08: 20000a48 .word 0x20000a48 + 800cd0c: 20000a4c .word 0x20000a4c + 800cd10: 08016b48 .word 0x08016b48 + 800cd14: 08016b58 .word 0x08016b58 + 800cd18: 20000a50 .word 0x20000a50 + + case PSU_CONT_WAIT_ACK_OFF: + RELAY_Write(RELAY_DC, 0); + 800cd1c: 2100 movs r1, #0 + 800cd1e: 2003 movs r0, #3 + 800cd20: f7fc fce4 bl 80096ec + if(!PSU0.CONT_enabled){ + 800cd24: 4b31 ldr r3, [pc, #196] @ (800cdec ) + 800cd26: 7adb ldrb r3, [r3, #11] + 800cd28: 2b00 cmp r3, #0 + 800cd2a: d107 bne.n 800cd3c + PSU_Enable(0, 0); + 800cd2c: 2100 movs r1, #0 + 800cd2e: 2000 movs r0, #0 + 800cd30: f7ff fcf2 bl 800c718 + PSU_SwitchState(PSU_WAIT_ACK_OFF); + 800cd34: 2007 movs r0, #7 + 800cd36: f7ff fb47 bl 800c3c8 + CONN.chargingError = CONN_ERR_CONTACTOR; + PSU_Enable(0, 0); + PSU_SwitchState(PSU_WAIT_ACK_OFF); + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + } + break; + 800cd3a: e050 b.n 800cdde + }else if(PSU_StateTime() > 1000){ + 800cd3c: f7ff fb58 bl 800c3f0 + 800cd40: 4603 mov r3, r0 + 800cd42: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800cd46: d94a bls.n 800cdde + PSU0.cont_fault = 1; + 800cd48: 4b28 ldr r3, [pc, #160] @ (800cdec ) + 800cd4a: 2201 movs r2, #1 + 800cd4c: 731a strb r2, [r3, #12] + CONN.chargingError = CONN_ERR_CONTACTOR; + 800cd4e: 4b28 ldr r3, [pc, #160] @ (800cdf0 ) + 800cd50: 2207 movs r2, #7 + 800cd52: 775a strb r2, [r3, #29] + PSU_Enable(0, 0); + 800cd54: 2100 movs r1, #0 + 800cd56: 2000 movs r0, #0 + 800cd58: f7ff fcde bl 800c718 + PSU_SwitchState(PSU_WAIT_ACK_OFF); + 800cd5c: 2007 movs r0, #7 + 800cd5e: f7ff fb33 bl 800c3c8 + log_printf(LOG_ERR, "Contactor error, stopping...\n"); + 800cd62: 4924 ldr r1, [pc, #144] @ (800cdf4 ) + 800cd64: 2004 movs r0, #4 + 800cd66: f7fe fb7d bl 800b464 + break; + 800cd6a: e038 b.n 800cdde + + case PSU_WAIT_ACK_OFF: + if(!PSU0.PSU_enabled){ + 800cd6c: 4b1f ldr r3, [pc, #124] @ (800cdec ) + 800cd6e: 7a9b ldrb r3, [r3, #10] + 800cd70: 2b00 cmp r3, #0 + 800cd72: d103 bne.n 800cd7c + PSU_SwitchState(PSU_OFF_PAUSE); + 800cd74: 2009 movs r0, #9 + 800cd76: f7ff fb27 bl 800c3c8 + PSU0.psu_fault = 1; + CONN.chargingError = CONN_ERR_PSU_FAULT; + PSU_SwitchState(PSU_UNREADY); + log_printf(LOG_ERR, "PSU off timeout\n"); + } + break; + 800cd7a: e032 b.n 800cde2 + }else if(PSU_StateTime() > 10000){ + 800cd7c: f7ff fb38 bl 800c3f0 + 800cd80: 4603 mov r3, r0 + 800cd82: f242 7210 movw r2, #10000 @ 0x2710 + 800cd86: 4293 cmp r3, r2 + 800cd88: d92b bls.n 800cde2 + PSU0.psu_fault = 1; + 800cd8a: 4b18 ldr r3, [pc, #96] @ (800cdec ) + 800cd8c: 2201 movs r2, #1 + 800cd8e: 735a strb r2, [r3, #13] + CONN.chargingError = CONN_ERR_PSU_FAULT; + 800cd90: 4b17 ldr r3, [pc, #92] @ (800cdf0 ) + 800cd92: 220a movs r2, #10 + 800cd94: 775a strb r2, [r3, #29] + PSU_SwitchState(PSU_UNREADY); + 800cd96: 2000 movs r0, #0 + 800cd98: f7ff fb16 bl 800c3c8 + log_printf(LOG_ERR, "PSU off timeout\n"); + 800cd9c: 4916 ldr r1, [pc, #88] @ (800cdf8 ) + 800cd9e: 2004 movs r0, #4 + 800cda0: f7fe fb60 bl 800b464 + break; + 800cda4: e01d b.n 800cde2 + case PSU_OFF_PAUSE: + if(PSU_StateTime() > 4000){ + 800cda6: f7ff fb23 bl 800c3f0 + 800cdaa: 4603 mov r3, r0 + 800cdac: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 + 800cdb0: d919 bls.n 800cde6 + PSU_SwitchState(PSU_READY); + 800cdb2: 2002 movs r0, #2 + 800cdb4: f7ff fb08 bl 800c3c8 + } + break; + 800cdb8: e015 b.n 800cde6 + + + + default: + PSU_SwitchState(PSU_UNREADY); + 800cdba: 2000 movs r0, #0 + 800cdbc: f7ff fb04 bl 800c3c8 + break; + 800cdc0: e012 b.n 800cde8 + break; + 800cdc2: bf00 nop + 800cdc4: e010 b.n 800cde8 + break; + 800cdc6: bf00 nop + 800cdc8: e00e b.n 800cde8 + break; + 800cdca: bf00 nop + 800cdcc: e00c b.n 800cde8 + break; + 800cdce: bf00 nop + 800cdd0: e00a b.n 800cde8 + break; + 800cdd2: bf00 nop + 800cdd4: e008 b.n 800cde8 + break; + 800cdd6: bf00 nop + 800cdd8: e006 b.n 800cde8 + break; + 800cdda: bf00 nop + 800cddc: e004 b.n 800cde8 + break; + 800cdde: bf00 nop + 800cde0: e002 b.n 800cde8 + break; + 800cde2: bf00 nop + 800cde4: e000 b.n 800cde8 + break; + 800cde6: bf00 nop + } +} + 800cde8: bf00 nop + 800cdea: bd98 pop {r3, r4, r7, pc} + 800cdec: 200009fc .word 0x200009fc + 800cdf0: 200002e8 .word 0x200002e8 + 800cdf4: 08016b58 .word 0x08016b58 + 800cdf8: 08016b78 .word 0x08016b78 + +0800cdfc : + .Th = 10, + .Tf = 50, + .Tl = 0, +}; + +void LED_Write(){ + 800cdfc: b580 push {r7, lr} + 800cdfe: af00 add r7, sp, #0 + if(CONN.chargingError != CONN_NO_ERROR){ + 800ce00: 4b34 ldr r3, [pc, #208] @ (800ced4 ) + 800ce02: 7f5b ldrb r3, [r3, #29] + 800ce04: 2b00 cmp r3, #0 + 800ce06: d003 beq.n 800ce10 + LED_SetColor(&color_error); + 800ce08: 4833 ldr r0, [pc, #204] @ (800ced8 ) + 800ce0a: f000 f91f bl 800d04c + return; + 800ce0e: e05f b.n 800ced0 + } + switch(CONN.connState){ + 800ce10: 4b30 ldr r3, [pc, #192] @ (800ced4 ) + 800ce12: 785b ldrb r3, [r3, #1] + 800ce14: 2b0d cmp r3, #13 + 800ce16: d857 bhi.n 800cec8 + 800ce18: a201 add r2, pc, #4 @ (adr r2, 800ce20 ) + 800ce1a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ce1e: bf00 nop + 800ce20: 0800ce59 .word 0x0800ce59 + 800ce24: 0800ce61 .word 0x0800ce61 + 800ce28: 0800ce69 .word 0x0800ce69 + 800ce2c: 0800ce71 .word 0x0800ce71 + 800ce30: 0800ce79 .word 0x0800ce79 + 800ce34: 0800ce81 .word 0x0800ce81 + 800ce38: 0800ce89 .word 0x0800ce89 + 800ce3c: 0800ce91 .word 0x0800ce91 + 800ce40: 0800ce99 .word 0x0800ce99 + 800ce44: 0800cea1 .word 0x0800cea1 + 800ce48: 0800cea9 .word 0x0800cea9 + 800ce4c: 0800ceb1 .word 0x0800ceb1 + 800ce50: 0800ceb9 .word 0x0800ceb9 + 800ce54: 0800cec1 .word 0x0800cec1 + case Unknown: + LED_SetColor(&color_unknown); + 800ce58: 4820 ldr r0, [pc, #128] @ (800cedc ) + 800ce5a: f000 f8f7 bl 800d04c + break; + 800ce5e: e037 b.n 800ced0 + case Unplugged: + LED_SetColor(&color_unplugged); + 800ce60: 481f ldr r0, [pc, #124] @ (800cee0 ) + 800ce62: f000 f8f3 bl 800d04c + break; + 800ce66: e033 b.n 800ced0 + case Disabled: + LED_SetColor(&color_error); + 800ce68: 481b ldr r0, [pc, #108] @ (800ced8 ) + 800ce6a: f000 f8ef bl 800d04c + break; + 800ce6e: e02f b.n 800ced0 + case Preparing: + LED_SetColor(&color_preparing); + 800ce70: 481c ldr r0, [pc, #112] @ (800cee4 ) + 800ce72: f000 f8eb bl 800d04c + break; + 800ce76: e02b b.n 800ced0 + case AuthRequired: + LED_SetColor(&color_preparing); + 800ce78: 481a ldr r0, [pc, #104] @ (800cee4 ) + 800ce7a: f000 f8e7 bl 800d04c + break; + 800ce7e: e027 b.n 800ced0 + case WaitingForEnergy: + LED_SetColor(&color_charging); + 800ce80: 4819 ldr r0, [pc, #100] @ (800cee8 ) + 800ce82: f000 f8e3 bl 800d04c + break; + 800ce86: e023 b.n 800ced0 + case ChargingPausedEV: + LED_SetColor(&color_charging); + 800ce88: 4817 ldr r0, [pc, #92] @ (800cee8 ) + 800ce8a: f000 f8df bl 800d04c + break; + 800ce8e: e01f b.n 800ced0 + case ChargingPausedEVSE: + LED_SetColor(&color_charging); + 800ce90: 4815 ldr r0, [pc, #84] @ (800cee8 ) + 800ce92: f000 f8db bl 800d04c + break; + 800ce96: e01b b.n 800ced0 + case Charging: + LED_SetColor(&color_charging); + 800ce98: 4813 ldr r0, [pc, #76] @ (800cee8 ) + 800ce9a: f000 f8d7 bl 800d04c + break; + 800ce9e: e017 b.n 800ced0 + case AuthTimeout: + LED_SetColor(&color_finished); + 800cea0: 4812 ldr r0, [pc, #72] @ (800ceec ) + 800cea2: f000 f8d3 bl 800d04c + break; + 800cea6: e013 b.n 800ced0 + case Finished: + LED_SetColor(&color_finished); + 800cea8: 4810 ldr r0, [pc, #64] @ (800ceec ) + 800ceaa: f000 f8cf bl 800d04c + break; + 800ceae: e00f b.n 800ced0 + case FinishedEVSE: + LED_SetColor(&color_finished); + 800ceb0: 480e ldr r0, [pc, #56] @ (800ceec ) + 800ceb2: f000 f8cb bl 800d04c + break; + 800ceb6: e00b b.n 800ced0 + case FinishedEV: + LED_SetColor(&color_finished); + 800ceb8: 480c ldr r0, [pc, #48] @ (800ceec ) + 800ceba: f000 f8c7 bl 800d04c + break; + 800cebe: e007 b.n 800ced0 + case Replugging: + LED_SetColor(&color_preparing); + 800cec0: 4808 ldr r0, [pc, #32] @ (800cee4 ) + 800cec2: f000 f8c3 bl 800d04c + break; + 800cec6: e003 b.n 800ced0 + default: + LED_SetColor(&color_unknown); + 800cec8: 4804 ldr r0, [pc, #16] @ (800cedc ) + 800ceca: f000 f8bf bl 800d04c + break; + 800cece: bf00 nop + } + } + 800ced0: bd80 pop {r7, pc} + 800ced2: bf00 nop + 800ced4: 200002e8 .word 0x200002e8 + 800ced8: 20000054 .word 0x20000054 + 800cedc: 20000018 .word 0x20000018 + 800cee0: 20000024 .word 0x20000024 + 800cee4: 20000030 .word 0x20000030 + 800cee8: 2000003c .word 0x2000003c + 800ceec: 20000048 .word 0x20000048 + +0800cef0 : + +void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { + 800cef0: b480 push {r7} + 800cef2: b087 sub sp, #28 + 800cef4: af00 add r7, sp, #0 + 800cef6: 60f8 str r0, [r7, #12] + 800cef8: 60b9 str r1, [r7, #8] + 800cefa: 4611 mov r1, r2 + 800cefc: 461a mov r2, r3 + 800cefe: 460b mov r3, r1 + 800cf00: 80fb strh r3, [r7, #6] + 800cf02: 4613 mov r3, r2 + 800cf04: 80bb strh r3, [r7, #4] + + // Проверяем, чтобы a не выходила за пределы диапазона + if (a > b) a = b; + 800cf06: 88fa ldrh r2, [r7, #6] + 800cf08: 88bb ldrh r3, [r7, #4] + 800cf0a: 429a cmp r2, r3 + 800cf0c: d901 bls.n 800cf12 + 800cf0e: 88bb ldrh r3, [r7, #4] + 800cf10: 80fb strh r3, [r7, #6] + + if(b==0) b = 1; + 800cf12: 88bb ldrh r3, [r7, #4] + 800cf14: 2b00 cmp r3, #0 + 800cf16: d101 bne.n 800cf1c + 800cf18: 2301 movs r3, #1 + 800cf1a: 80bb strh r3, [r7, #4] + + // Вычисляем коэффициент смешивания в виде целого числа + uint16_t t = (a * 255) / b; // t будет от 0 до 255 + 800cf1c: 88fa ldrh r2, [r7, #6] + 800cf1e: 4613 mov r3, r2 + 800cf20: 021b lsls r3, r3, #8 + 800cf22: 1a9a subs r2, r3, r2 + 800cf24: 88bb ldrh r3, [r7, #4] + 800cf26: fb92 f3f3 sdiv r3, r2, r3 + 800cf2a: 82fb strh r3, [r7, #22] + + // Линейная интерполяция с использованием целых чисел + result->R = (color1->R * (255 - t) + color2->R * t) / 255; + 800cf2c: 68fb ldr r3, [r7, #12] + 800cf2e: 781b ldrb r3, [r3, #0] + 800cf30: 461a mov r2, r3 + 800cf32: 8afb ldrh r3, [r7, #22] + 800cf34: f1c3 03ff rsb r3, r3, #255 @ 0xff + 800cf38: fb03 f202 mul.w r2, r3, r2 + 800cf3c: 68bb ldr r3, [r7, #8] + 800cf3e: 781b ldrb r3, [r3, #0] + 800cf40: 4619 mov r1, r3 + 800cf42: 8afb ldrh r3, [r7, #22] + 800cf44: fb01 f303 mul.w r3, r1, r3 + 800cf48: 4413 add r3, r2 + 800cf4a: 4a20 ldr r2, [pc, #128] @ (800cfcc ) + 800cf4c: fb82 1203 smull r1, r2, r2, r3 + 800cf50: 441a add r2, r3 + 800cf52: 11d2 asrs r2, r2, #7 + 800cf54: 17db asrs r3, r3, #31 + 800cf56: 1ad3 subs r3, r2, r3 + 800cf58: b2da uxtb r2, r3 + 800cf5a: 6a3b ldr r3, [r7, #32] + 800cf5c: 701a strb r2, [r3, #0] + result->G = (color1->G * (255 - t) + color2->G * t) / 255; + 800cf5e: 68fb ldr r3, [r7, #12] + 800cf60: 785b ldrb r3, [r3, #1] + 800cf62: 461a mov r2, r3 + 800cf64: 8afb ldrh r3, [r7, #22] + 800cf66: f1c3 03ff rsb r3, r3, #255 @ 0xff + 800cf6a: fb03 f202 mul.w r2, r3, r2 + 800cf6e: 68bb ldr r3, [r7, #8] + 800cf70: 785b ldrb r3, [r3, #1] + 800cf72: 4619 mov r1, r3 + 800cf74: 8afb ldrh r3, [r7, #22] + 800cf76: fb01 f303 mul.w r3, r1, r3 + 800cf7a: 4413 add r3, r2 + 800cf7c: 4a13 ldr r2, [pc, #76] @ (800cfcc ) + 800cf7e: fb82 1203 smull r1, r2, r2, r3 + 800cf82: 441a add r2, r3 + 800cf84: 11d2 asrs r2, r2, #7 + 800cf86: 17db asrs r3, r3, #31 + 800cf88: 1ad3 subs r3, r2, r3 + 800cf8a: b2da uxtb r2, r3 + 800cf8c: 6a3b ldr r3, [r7, #32] + 800cf8e: 705a strb r2, [r3, #1] + result->B = (color1->B * (255 - t) + color2->B * t) / 255; + 800cf90: 68fb ldr r3, [r7, #12] + 800cf92: 789b ldrb r3, [r3, #2] + 800cf94: 461a mov r2, r3 + 800cf96: 8afb ldrh r3, [r7, #22] + 800cf98: f1c3 03ff rsb r3, r3, #255 @ 0xff + 800cf9c: fb03 f202 mul.w r2, r3, r2 + 800cfa0: 68bb ldr r3, [r7, #8] + 800cfa2: 789b ldrb r3, [r3, #2] + 800cfa4: 4619 mov r1, r3 + 800cfa6: 8afb ldrh r3, [r7, #22] + 800cfa8: fb01 f303 mul.w r3, r1, r3 + 800cfac: 4413 add r3, r2 + 800cfae: 4a07 ldr r2, [pc, #28] @ (800cfcc ) + 800cfb0: fb82 1203 smull r1, r2, r2, r3 + 800cfb4: 441a add r2, r3 + 800cfb6: 11d2 asrs r2, r2, #7 + 800cfb8: 17db asrs r3, r3, #31 + 800cfba: 1ad3 subs r3, r2, r3 + 800cfbc: b2da uxtb r2, r3 + 800cfbe: 6a3b ldr r3, [r7, #32] + 800cfc0: 709a strb r2, [r3, #2] + +} + 800cfc2: bf00 nop + 800cfc4: 371c adds r7, #28 + 800cfc6: 46bd mov sp, r7 + 800cfc8: bc80 pop {r7} + 800cfca: 4770 bx lr + 800cfcc: 80808081 .word 0x80808081 + +0800cfd0 : + + +void RGB_SetColor(RGB_t *color){ + 800cfd0: b480 push {r7} + 800cfd2: b083 sub sp, #12 + 800cfd4: af00 add r7, sp, #0 + 800cfd6: 6078 str r0, [r7, #4] + htim4.Instance->CCR2 = color->R * 100 / 255; + 800cfd8: 687b ldr r3, [r7, #4] + 800cfda: 781b ldrb r3, [r3, #0] + 800cfdc: 461a mov r2, r3 + 800cfde: 2364 movs r3, #100 @ 0x64 + 800cfe0: fb02 f303 mul.w r3, r2, r3 + 800cfe4: 4a17 ldr r2, [pc, #92] @ (800d044 ) + 800cfe6: fb82 1203 smull r1, r2, r2, r3 + 800cfea: 441a add r2, r3 + 800cfec: 11d2 asrs r2, r2, #7 + 800cfee: 17db asrs r3, r3, #31 + 800cff0: 1ad2 subs r2, r2, r3 + 800cff2: 4b15 ldr r3, [pc, #84] @ (800d048 ) + 800cff4: 681b ldr r3, [r3, #0] + 800cff6: 639a str r2, [r3, #56] @ 0x38 + htim4.Instance->CCR3 = color->G * 100 / 255; + 800cff8: 687b ldr r3, [r7, #4] + 800cffa: 785b ldrb r3, [r3, #1] + 800cffc: 461a mov r2, r3 + 800cffe: 2364 movs r3, #100 @ 0x64 + 800d000: fb02 f303 mul.w r3, r2, r3 + 800d004: 4a0f ldr r2, [pc, #60] @ (800d044 ) + 800d006: fb82 1203 smull r1, r2, r2, r3 + 800d00a: 441a add r2, r3 + 800d00c: 11d2 asrs r2, r2, #7 + 800d00e: 17db asrs r3, r3, #31 + 800d010: 1ad2 subs r2, r2, r3 + 800d012: 4b0d ldr r3, [pc, #52] @ (800d048 ) + 800d014: 681b ldr r3, [r3, #0] + 800d016: 63da str r2, [r3, #60] @ 0x3c + htim4.Instance->CCR4 = color->B * 100 / 255; + 800d018: 687b ldr r3, [r7, #4] + 800d01a: 789b ldrb r3, [r3, #2] + 800d01c: 461a mov r2, r3 + 800d01e: 2364 movs r3, #100 @ 0x64 + 800d020: fb02 f303 mul.w r3, r2, r3 + 800d024: 4a07 ldr r2, [pc, #28] @ (800d044 ) + 800d026: fb82 1203 smull r1, r2, r2, r3 + 800d02a: 441a add r2, r3 + 800d02c: 11d2 asrs r2, r2, #7 + 800d02e: 17db asrs r3, r3, #31 + 800d030: 1ad2 subs r2, r2, r3 + 800d032: 4b05 ldr r3, [pc, #20] @ (800d048 ) + 800d034: 681b ldr r3, [r3, #0] + 800d036: 641a str r2, [r3, #64] @ 0x40 +} + 800d038: bf00 nop + 800d03a: 370c adds r7, #12 + 800d03c: 46bd mov sp, r7 + 800d03e: bc80 pop {r7} + 800d040: 4770 bx lr + 800d042: bf00 nop + 800d044: 80808081 .word 0x80808081 + 800d048: 20000cf8 .word 0x20000cf8 + +0800d04c : + +void LED_SetColor(RGB_Cycle_t *color){ + 800d04c: b480 push {r7} + 800d04e: b083 sub sp, #12 + 800d050: af00 add r7, sp, #0 + 800d052: 6078 str r0, [r7, #4] + memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); + 800d054: 4b05 ldr r3, [pc, #20] @ (800d06c ) + 800d056: 687a ldr r2, [r7, #4] + 800d058: 6810 ldr r0, [r2, #0] + 800d05a: 6851 ldr r1, [r2, #4] + 800d05c: c303 stmia r3!, {r0, r1} + 800d05e: 8912 ldrh r2, [r2, #8] + 800d060: 801a strh r2, [r3, #0] +} + 800d062: bf00 nop + 800d064: 370c adds r7, #12 + 800d066: 46bd mov sp, r7 + 800d068: bc80 pop {r7} + 800d06a: 4770 bx lr + 800d06c: 20000a5c .word 0x20000a5c + +0800d070 : + + +void LED_Init(){ + 800d070: b580 push {r7, lr} + 800d072: b082 sub sp, #8 + 800d074: af00 add r7, sp, #0 + RGB_t color = {.R=0, .G=0, .B=0}; + 800d076: 2300 movs r3, #0 + 800d078: 713b strb r3, [r7, #4] + 800d07a: 2300 movs r3, #0 + 800d07c: 717b strb r3, [r7, #5] + 800d07e: 2300 movs r3, #0 + 800d080: 71bb strb r3, [r7, #6] + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); + 800d082: 2104 movs r1, #4 + 800d084: 4809 ldr r0, [pc, #36] @ (800d0ac ) + 800d086: f004 fddf bl 8011c48 + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); + 800d08a: 2108 movs r1, #8 + 800d08c: 4807 ldr r0, [pc, #28] @ (800d0ac ) + 800d08e: f004 fddb bl 8011c48 + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); + 800d092: 210c movs r1, #12 + 800d094: 4805 ldr r0, [pc, #20] @ (800d0ac ) + 800d096: f004 fdd7 bl 8011c48 + RGB_SetColor(&color); + 800d09a: 1d3b adds r3, r7, #4 + 800d09c: 4618 mov r0, r3 + 800d09e: f7ff ff97 bl 800cfd0 +} + 800d0a2: bf00 nop + 800d0a4: 3708 adds r7, #8 + 800d0a6: 46bd mov sp, r7 + 800d0a8: bd80 pop {r7, pc} + 800d0aa: bf00 nop + 800d0ac: 20000cf8 .word 0x20000cf8 + +0800d0b0 : +// } +// } +// } +// } + +void LED_Task(){ + 800d0b0: b580 push {r7, lr} + 800d0b2: b082 sub sp, #8 + 800d0b4: af02 add r7, sp, #8 + static uint32_t led_tick; + if((HAL_GetTick() - led_tick) > 20){ + 800d0b6: f001 fb8b bl 800e7d0 + 800d0ba: 4602 mov r2, r0 + 800d0bc: 4b46 ldr r3, [pc, #280] @ (800d1d8 ) + 800d0be: 681b ldr r3, [r3, #0] + 800d0c0: 1ad3 subs r3, r2, r3 + 800d0c2: 2b14 cmp r3, #20 + 800d0c4: f240 8085 bls.w 800d1d2 + led_tick = HAL_GetTick(); + 800d0c8: f001 fb82 bl 800e7d0 + 800d0cc: 4603 mov r3, r0 + 800d0ce: 4a42 ldr r2, [pc, #264] @ (800d1d8 ) + 800d0d0: 6013 str r3, [r2, #0] + LED_State.tick++; + 800d0d2: 4b42 ldr r3, [pc, #264] @ (800d1dc ) + 800d0d4: 885b ldrh r3, [r3, #2] + 800d0d6: 3301 adds r3, #1 + 800d0d8: b29a uxth r2, r3 + 800d0da: 4b40 ldr r3, [pc, #256] @ (800d1dc ) + 800d0dc: 805a strh r2, [r3, #2] + // LED_PhaseSync(led_n); + switch(LED_State.state){ + 800d0de: 4b3f ldr r3, [pc, #252] @ (800d1dc ) + 800d0e0: 781b ldrb r3, [r3, #0] + 800d0e2: 2b03 cmp r3, #3 + 800d0e4: d867 bhi.n 800d1b6 + 800d0e6: a201 add r2, pc, #4 @ (adr r2, 800d0ec ) + 800d0e8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800d0ec: 0800d0fd .word 0x0800d0fd + 800d0f0: 0800d12f .word 0x0800d12f + 800d0f4: 0800d15b .word 0x0800d15b + 800d0f8: 0800d18d .word 0x0800d18d + case LED_RISING: + interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); + 800d0fc: 4b37 ldr r3, [pc, #220] @ (800d1dc ) + 800d0fe: 885a ldrh r2, [r3, #2] + 800d100: 4b37 ldr r3, [pc, #220] @ (800d1e0 ) + 800d102: 78db ldrb r3, [r3, #3] + 800d104: 4619 mov r1, r3 + 800d106: 4b37 ldr r3, [pc, #220] @ (800d1e4 ) + 800d108: 9300 str r3, [sp, #0] + 800d10a: 460b mov r3, r1 + 800d10c: 4934 ldr r1, [pc, #208] @ (800d1e0 ) + 800d10e: 4836 ldr r0, [pc, #216] @ (800d1e8 ) + 800d110: f7ff feee bl 800cef0 + + if(LED_State.tick>LED_Cycle.Tr){ + 800d114: 4b31 ldr r3, [pc, #196] @ (800d1dc ) + 800d116: 885b ldrh r3, [r3, #2] + 800d118: 4a31 ldr r2, [pc, #196] @ (800d1e0 ) + 800d11a: 78d2 ldrb r2, [r2, #3] + 800d11c: 4293 cmp r3, r2 + 800d11e: d94e bls.n 800d1be + LED_State.state = LED_HIGH; + 800d120: 4b2e ldr r3, [pc, #184] @ (800d1dc ) + 800d122: 2201 movs r2, #1 + 800d124: 701a strb r2, [r3, #0] + LED_State.tick = 0; + 800d126: 4b2d ldr r3, [pc, #180] @ (800d1dc ) + 800d128: 2200 movs r2, #0 + 800d12a: 805a strh r2, [r3, #2] + } + break; + 800d12c: e047 b.n 800d1be + case LED_HIGH: + memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); + 800d12e: 4b2b ldr r3, [pc, #172] @ (800d1dc ) + 800d130: 4a2b ldr r2, [pc, #172] @ (800d1e0 ) + 800d132: 3304 adds r3, #4 + 800d134: 6812 ldr r2, [r2, #0] + 800d136: 4611 mov r1, r2 + 800d138: 8019 strh r1, [r3, #0] + 800d13a: 3302 adds r3, #2 + 800d13c: 0c12 lsrs r2, r2, #16 + 800d13e: 701a strb r2, [r3, #0] + + if(LED_State.tick>LED_Cycle.Th){ + 800d140: 4b26 ldr r3, [pc, #152] @ (800d1dc ) + 800d142: 885b ldrh r3, [r3, #2] + 800d144: 4a26 ldr r2, [pc, #152] @ (800d1e0 ) + 800d146: 7912 ldrb r2, [r2, #4] + 800d148: 4293 cmp r3, r2 + 800d14a: d93a bls.n 800d1c2 + LED_State.state = LED_FALLING; + 800d14c: 4b23 ldr r3, [pc, #140] @ (800d1dc ) + 800d14e: 2202 movs r2, #2 + 800d150: 701a strb r2, [r3, #0] + LED_State.tick = 0; + 800d152: 4b22 ldr r3, [pc, #136] @ (800d1dc ) + 800d154: 2200 movs r2, #0 + 800d156: 805a strh r2, [r3, #2] + } + break; + 800d158: e033 b.n 800d1c2 + case LED_FALLING: + interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); + 800d15a: 4b20 ldr r3, [pc, #128] @ (800d1dc ) + 800d15c: 885a ldrh r2, [r3, #2] + 800d15e: 4b20 ldr r3, [pc, #128] @ (800d1e0 ) + 800d160: 795b ldrb r3, [r3, #5] + 800d162: 4619 mov r1, r3 + 800d164: 4b1f ldr r3, [pc, #124] @ (800d1e4 ) + 800d166: 9300 str r3, [sp, #0] + 800d168: 460b mov r3, r1 + 800d16a: 491f ldr r1, [pc, #124] @ (800d1e8 ) + 800d16c: 481c ldr r0, [pc, #112] @ (800d1e0 ) + 800d16e: f7ff febf bl 800cef0 + + if(LED_State.tick>LED_Cycle.Tf){ + 800d172: 4b1a ldr r3, [pc, #104] @ (800d1dc ) + 800d174: 885b ldrh r3, [r3, #2] + 800d176: 4a1a ldr r2, [pc, #104] @ (800d1e0 ) + 800d178: 7952 ldrb r2, [r2, #5] + 800d17a: 4293 cmp r3, r2 + 800d17c: d923 bls.n 800d1c6 + LED_State.state = LED_LOW; + 800d17e: 4b17 ldr r3, [pc, #92] @ (800d1dc ) + 800d180: 2203 movs r2, #3 + 800d182: 701a strb r2, [r3, #0] + LED_State.tick = 0; + 800d184: 4b15 ldr r3, [pc, #84] @ (800d1dc ) + 800d186: 2200 movs r2, #0 + 800d188: 805a strh r2, [r3, #2] + } + break; + 800d18a: e01c b.n 800d1c6 + case LED_LOW: + memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); + 800d18c: 4b13 ldr r3, [pc, #76] @ (800d1dc ) + 800d18e: 4a14 ldr r2, [pc, #80] @ (800d1e0 ) + 800d190: 3304 adds r3, #4 + 800d192: 3207 adds r2, #7 + 800d194: 8811 ldrh r1, [r2, #0] + 800d196: 7892 ldrb r2, [r2, #2] + 800d198: 8019 strh r1, [r3, #0] + 800d19a: 709a strb r2, [r3, #2] + + if(LED_State.tick>LED_Cycle.Tl){ + 800d19c: 4b0f ldr r3, [pc, #60] @ (800d1dc ) + 800d19e: 885b ldrh r3, [r3, #2] + 800d1a0: 4a0f ldr r2, [pc, #60] @ (800d1e0 ) + 800d1a2: 7992 ldrb r2, [r2, #6] + 800d1a4: 4293 cmp r3, r2 + 800d1a6: d910 bls.n 800d1ca + LED_State.state = LED_RISING; + 800d1a8: 4b0c ldr r3, [pc, #48] @ (800d1dc ) + 800d1aa: 2200 movs r2, #0 + 800d1ac: 701a strb r2, [r3, #0] + LED_State.tick = 0; + 800d1ae: 4b0b ldr r3, [pc, #44] @ (800d1dc ) + 800d1b0: 2200 movs r2, #0 + 800d1b2: 805a strh r2, [r3, #2] + } + break; + 800d1b4: e009 b.n 800d1ca + default: + LED_State.state = LED_RISING; + 800d1b6: 4b09 ldr r3, [pc, #36] @ (800d1dc ) + 800d1b8: 2200 movs r2, #0 + 800d1ba: 701a strb r2, [r3, #0] + 800d1bc: e006 b.n 800d1cc + break; + 800d1be: bf00 nop + 800d1c0: e004 b.n 800d1cc + break; + 800d1c2: bf00 nop + 800d1c4: e002 b.n 800d1cc + break; + 800d1c6: bf00 nop + 800d1c8: e000 b.n 800d1cc + break; + 800d1ca: bf00 nop + } + RGB_SetColor(&LED_State.color); + 800d1cc: 4805 ldr r0, [pc, #20] @ (800d1e4 ) + 800d1ce: f7ff feff bl 800cfd0 + } +} + 800d1d2: bf00 nop + 800d1d4: 46bd mov sp, r7 + 800d1d6: bd80 pop {r7, pc} + 800d1d8: 20000a68 .word 0x20000a68 + 800d1dc: 20000a54 .word 0x20000a54 + 800d1e0: 20000a5c .word 0x20000a5c + 800d1e4: 20000a58 .word 0x20000a58 + 800d1e8: 20000a63 .word 0x20000a63 + +0800d1ec : + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + 800d1ec: b580 push {r7, lr} + 800d1ee: af00 add r7, sp, #0 + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 800d1f0: 4b0a ldr r3, [pc, #40] @ (800d21c ) + 800d1f2: 4a0b ldr r2, [pc, #44] @ (800d220 ) + 800d1f4: 601a str r2, [r3, #0] + hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; + 800d1f6: 4b09 ldr r3, [pc, #36] @ (800d21c ) + 800d1f8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 800d1fc: 605a str r2, [r3, #4] + hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; + 800d1fe: 4b07 ldr r3, [pc, #28] @ (800d21c ) + 800d200: f44f 7280 mov.w r2, #256 @ 0x100 + 800d204: 609a str r2, [r3, #8] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 800d206: 4805 ldr r0, [pc, #20] @ (800d21c ) + 800d208: f004 fb6e bl 80118e8 + 800d20c: 4603 mov r3, r0 + 800d20e: 2b00 cmp r3, #0 + 800d210: d001 beq.n 800d216 + { + Error_Handler(); + 800d212: f7ff f869 bl 800c2e8 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 800d216: bf00 nop + 800d218: bd80 pop {r7, pc} + 800d21a: bf00 nop + 800d21c: 20000a6c .word 0x20000a6c + 800d220: 40002800 .word 0x40002800 + +0800d224 : + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + 800d224: b580 push {r7, lr} + 800d226: b084 sub sp, #16 + 800d228: af00 add r7, sp, #0 + 800d22a: 6078 str r0, [r7, #4] + + if(rtcHandle->Instance==RTC) + 800d22c: 687b ldr r3, [r7, #4] + 800d22e: 681b ldr r3, [r3, #0] + 800d230: 4a0b ldr r2, [pc, #44] @ (800d260 ) + 800d232: 4293 cmp r3, r2 + 800d234: d110 bne.n 800d258 + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + HAL_PWR_EnableBkUpAccess(); + 800d236: f003 faeb bl 8010810 + /* Enable BKP CLK enable for backup registers */ + __HAL_RCC_BKP_CLK_ENABLE(); + 800d23a: 4b0a ldr r3, [pc, #40] @ (800d264 ) + 800d23c: 69db ldr r3, [r3, #28] + 800d23e: 4a09 ldr r2, [pc, #36] @ (800d264 ) + 800d240: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 800d244: 61d3 str r3, [r2, #28] + 800d246: 4b07 ldr r3, [pc, #28] @ (800d264 ) + 800d248: 69db ldr r3, [r3, #28] + 800d24a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 800d24e: 60fb str r3, [r7, #12] + 800d250: 68fb ldr r3, [r7, #12] + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + 800d252: 4b05 ldr r3, [pc, #20] @ (800d268 ) + 800d254: 2201 movs r2, #1 + 800d256: 601a str r2, [r3, #0] + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + 800d258: bf00 nop + 800d25a: 3710 adds r7, #16 + 800d25c: 46bd mov sp, r7 + 800d25e: bd80 pop {r7, pc} + 800d260: 40002800 .word 0x40002800 + 800d264: 40021000 .word 0x40021000 + 800d268: 4242043c .word 0x4242043c + +0800d26c : + .fw_version_major = 0, + .fw_version_minor = 0, + .fw_version_patch = 0, +}; + +void ReadVersion(){ + 800d26c: b480 push {r7} + 800d26e: af00 add r7, sp, #0 + infoPacket.serialNumber = InfoBlock->serialNumber; + 800d270: 4b0e ldr r3, [pc, #56] @ (800d2ac ) + 800d272: 681b ldr r3, [r3, #0] + 800d274: 681b ldr r3, [r3, #0] + 800d276: b29a uxth r2, r3 + 800d278: 4b0d ldr r3, [pc, #52] @ (800d2b0 ) + 800d27a: 801a strh r2, [r3, #0] + infoPacket.boardVersion = InfoBlock->boardVersion; + 800d27c: 4b0b ldr r3, [pc, #44] @ (800d2ac ) + 800d27e: 681b ldr r3, [r3, #0] + 800d280: 795a ldrb r2, [r3, #5] + 800d282: 4b0b ldr r3, [pc, #44] @ (800d2b0 ) + 800d284: 709a strb r2, [r3, #2] + infoPacket.stationType = InfoBlock->stationType; + 800d286: 4b09 ldr r3, [pc, #36] @ (800d2ac ) + 800d288: 681b ldr r3, [r3, #0] + 800d28a: 791a ldrb r2, [r3, #4] + 800d28c: 4b08 ldr r3, [pc, #32] @ (800d2b0 ) + 800d28e: 70da strb r2, [r3, #3] + infoPacket.fw_version_major = FW_VERSION_MAJOR; + 800d290: 4b07 ldr r3, [pc, #28] @ (800d2b0 ) + 800d292: 2201 movs r2, #1 + 800d294: 809a strh r2, [r3, #4] + infoPacket.fw_version_minor = FW_VERSION_MINOR; + 800d296: 4b06 ldr r3, [pc, #24] @ (800d2b0 ) + 800d298: 2200 movs r2, #0 + 800d29a: 80da strh r2, [r3, #6] + infoPacket.fw_version_patch = FW_VERSION_PATCH; + 800d29c: 4b04 ldr r3, [pc, #16] @ (800d2b0 ) + 800d29e: 2201 movs r2, #1 + 800d2a0: 811a strh r2, [r3, #8] +} + 800d2a2: bf00 nop + 800d2a4: 46bd mov sp, r7 + 800d2a6: bc80 pop {r7} + 800d2a8: 4770 bx lr + 800d2aa: bf00 nop + 800d2ac: 20000000 .word 0x20000000 + 800d2b0: 20000ce8 .word 0x20000ce8 + +0800d2b4 : + +// Внешняя функция обработки команд (определена в serial_handler.c) +extern void SC_CommandHandler(ReceivedCommand_t* cmd); + +void SC_Init() { + 800d2b4: b580 push {r7, lr} + 800d2b6: af00 add r7, sp, #0 + // Обнуляем структуру + memset(&serial_control, 0, sizeof(SerialControl_t)); + 800d2b8: f44f 7204 mov.w r2, #528 @ 0x210 + 800d2bc: 2100 movs r1, #0 + 800d2be: 4802 ldr r0, [pc, #8] @ (800d2c8 ) + 800d2c0: f006 fee6 bl 8014090 +} + 800d2c4: bf00 nop + 800d2c6: bd80 pop {r7, pc} + 800d2c8: 20000a80 .word 0x20000a80 + +0800d2cc : + +void SC_Task() { + 800d2cc: b580 push {r7, lr} + 800d2ce: af00 add r7, sp, #0 + // Запуск приема в режиме прерывания с ожиданием idle + if((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); + 800d2d0: 4b25 ldr r3, [pc, #148] @ (800d368 ) + 800d2d2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 800d2d6: b2db uxtb r3, r3 + 800d2d8: 2b20 cmp r3, #32 + 800d2da: d10a bne.n 800d2f2 + 800d2dc: 4b23 ldr r3, [pc, #140] @ (800d36c ) + 800d2de: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 + 800d2e2: b2db uxtb r3, r3 + 800d2e4: 2b00 cmp r3, #0 + 800d2e6: d104 bne.n 800d2f2 + 800d2e8: 22ff movs r2, #255 @ 0xff + 800d2ea: 4921 ldr r1, [pc, #132] @ (800d370 ) + 800d2ec: 481e ldr r0, [pc, #120] @ (800d368 ) + 800d2ee: f005 fa84 bl 80127fa + + // Проверка таймаута отправки пакета (больше 100 мс) + if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { + 800d2f2: 4b1d ldr r3, [pc, #116] @ (800d368 ) + 800d2f4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800d2f8: b2db uxtb r3, r3 + 800d2fa: 2b21 cmp r3, #33 @ 0x21 + 800d2fc: d119 bne.n 800d332 + 800d2fe: 4b1b ldr r3, [pc, #108] @ (800d36c ) + 800d300: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c + 800d304: 2b00 cmp r3, #0 + 800d306: d014 beq.n 800d332 + if ((HAL_GetTick() - serial_control.tx_tick) > 100) { + 800d308: f001 fa62 bl 800e7d0 + 800d30c: 4602 mov r2, r0 + 800d30e: 4b17 ldr r3, [pc, #92] @ (800d36c ) + 800d310: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c + 800d314: 1ad3 subs r3, r2, r3 + 800d316: 2b64 cmp r3, #100 @ 0x64 + 800d318: d90b bls.n 800d332 + // Таймаут: принудительно сбрасываем передачу + HAL_UART_Abort_IT(&huart2); + 800d31a: 4813 ldr r0, [pc, #76] @ (800d368 ) + 800d31c: f005 faca bl 80128b4 + // Выключаем DIR при сбросе передачи + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + 800d320: 2200 movs r2, #0 + 800d322: 2110 movs r1, #16 + 800d324: 4813 ldr r0, [pc, #76] @ (800d374 ) + 800d326: f003 fa5a bl 80107de + serial_control.tx_tick = 0; // Сбрасываем tick + 800d32a: 4b10 ldr r3, [pc, #64] @ (800d36c ) + 800d32c: 2200 movs r2, #0 + 800d32e: f8c3 220c str.w r2, [r3, #524] @ 0x20c + } + } + + // Проверка наличия принятой команды для обработки + if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { + 800d332: 4b0e ldr r3, [pc, #56] @ (800d36c ) + 800d334: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 + 800d338: b2db uxtb r3, r3 + 800d33a: 2b00 cmp r3, #0 + 800d33c: d011 beq.n 800d362 + 800d33e: 4b0a ldr r3, [pc, #40] @ (800d368 ) + 800d340: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800d344: b2db uxtb r3, r3 + 800d346: 2b21 cmp r3, #33 @ 0x21 + 800d348: d00b beq.n 800d362 +// HAL_Delay(2); + SC_CommandHandler(&serial_control.received_command); + 800d34a: 480b ldr r0, [pc, #44] @ (800d378 ) + 800d34c: f000 fa24 bl 800d798 + HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); + 800d350: 22ff movs r2, #255 @ 0xff + 800d352: 4907 ldr r1, [pc, #28] @ (800d370 ) + 800d354: 4804 ldr r0, [pc, #16] @ (800d368 ) + 800d356: f005 fa50 bl 80127fa + serial_control.command_ready = 0; // Сбрасываем флаг + 800d35a: 4b04 ldr r3, [pc, #16] @ (800d36c ) + 800d35c: 2200 movs r2, #0 + 800d35e: f883 2208 strb.w r2, [r3, #520] @ 0x208 + } +} + 800d362: bf00 nop + 800d364: bd80 pop {r7, pc} + 800d366: bf00 nop + 800d368: 20000dd0 .word 0x20000dd0 + 800d36c: 20000a80 .word 0x20000a80 + 800d370: 20000b80 .word 0x20000b80 + 800d374: 40011400 .word 0x40011400 + 800d378: 20000c80 .word 0x20000c80 + +0800d37c : + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { + 800d37c: b580 push {r7, lr} + 800d37e: b082 sub sp, #8 + 800d380: af00 add r7, sp, #0 + 800d382: 6078 str r0, [r7, #4] + 800d384: 460b mov r3, r1 + 800d386: 807b strh r3, [r7, #2] + if (huart->Instance == huart2.Instance) { + 800d388: 687b ldr r3, [r7, #4] + 800d38a: 681a ldr r2, [r3, #0] + 800d38c: 4b0a ldr r3, [pc, #40] @ (800d3b8 ) + 800d38e: 681b ldr r3, [r3, #0] + 800d390: 429a cmp r2, r3 + 800d392: d10c bne.n 800d3ae + if(!process_received_packet(serial_control.rx_buffer, Size)){ + 800d394: 887b ldrh r3, [r7, #2] + 800d396: 4619 mov r1, r3 + 800d398: 4808 ldr r0, [pc, #32] @ (800d3bc ) + 800d39a: f000 f98f bl 800d6bc + 800d39e: 4603 mov r3, r0 + 800d3a0: 2b00 cmp r3, #0 + 800d3a2: d104 bne.n 800d3ae + SC_SendPacket(NULL, 0, RESP_INVALID); + 800d3a4: 2214 movs r2, #20 + 800d3a6: 2100 movs r1, #0 + 800d3a8: 2000 movs r0, #0 + 800d3aa: f000 f94b bl 800d644 + } + } +} + 800d3ae: bf00 nop + 800d3b0: 3708 adds r7, #8 + 800d3b2: 46bd mov sp, r7 + 800d3b4: bd80 pop {r7, pc} + 800d3b6: bf00 nop + 800d3b8: 20000dd0 .word 0x20000dd0 + 800d3bc: 20000b80 .word 0x20000b80 + +0800d3c0 : + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { + 800d3c0: b580 push {r7, lr} + 800d3c2: b082 sub sp, #8 + 800d3c4: af00 add r7, sp, #0 + 800d3c6: 6078 str r0, [r7, #4] + if (huart->Instance == huart2.Instance) { + 800d3c8: 687b ldr r3, [r7, #4] + 800d3ca: 681a ldr r2, [r3, #0] + 800d3cc: 4b08 ldr r3, [pc, #32] @ (800d3f0 ) + 800d3ce: 681b ldr r3, [r3, #0] + 800d3d0: 429a cmp r2, r3 + 800d3d2: d108 bne.n 800d3e6 + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + 800d3d4: 2200 movs r2, #0 + 800d3d6: 2110 movs r1, #16 + 800d3d8: 4806 ldr r0, [pc, #24] @ (800d3f4 ) + 800d3da: f003 fa00 bl 80107de + serial_control.tx_tick = 0; + 800d3de: 4b06 ldr r3, [pc, #24] @ (800d3f8 ) + 800d3e0: 2200 movs r2, #0 + 800d3e2: f8c3 220c str.w r2, [r3, #524] @ 0x20c + } +} + 800d3e6: bf00 nop + 800d3e8: 3708 adds r7, #8 + 800d3ea: 46bd mov sp, r7 + 800d3ec: bd80 pop {r7, pc} + 800d3ee: bf00 nop + 800d3f0: 20000dd0 .word 0x20000dd0 + 800d3f4: 40011400 .word 0x40011400 + 800d3f8: 20000a80 .word 0x20000a80 + +0800d3fc : + +// Приватные функции реализации +uint32_t revbit(uint32_t uData) { + 800d3fc: b480 push {r7} + 800d3fe: b085 sub sp, #20 + 800d400: af00 add r7, sp, #0 + 800d402: 6078 str r0, [r7, #4] + uint32_t uRevData = 0, uIndex = 0; + 800d404: 2300 movs r3, #0 + 800d406: 60fb str r3, [r7, #12] + 800d408: 2300 movs r3, #0 + 800d40a: 60bb str r3, [r7, #8] + uRevData |= ((uData >> uIndex) & 0x01); + 800d40c: 687a ldr r2, [r7, #4] + 800d40e: 68bb ldr r3, [r7, #8] + 800d410: fa22 f303 lsr.w r3, r2, r3 + 800d414: f003 0301 and.w r3, r3, #1 + 800d418: 68fa ldr r2, [r7, #12] + 800d41a: 4313 orrs r3, r2 + 800d41c: 60fb str r3, [r7, #12] + for(uIndex = 1; uIndex < 32; uIndex++) { + 800d41e: 2301 movs r3, #1 + 800d420: 60bb str r3, [r7, #8] + 800d422: e00e b.n 800d442 + uRevData <<= 1; + 800d424: 68fb ldr r3, [r7, #12] + 800d426: 005b lsls r3, r3, #1 + 800d428: 60fb str r3, [r7, #12] + uRevData |= ((uData >> uIndex) & 0x01); + 800d42a: 687a ldr r2, [r7, #4] + 800d42c: 68bb ldr r3, [r7, #8] + 800d42e: fa22 f303 lsr.w r3, r2, r3 + 800d432: f003 0301 and.w r3, r3, #1 + 800d436: 68fa ldr r2, [r7, #12] + 800d438: 4313 orrs r3, r2 + 800d43a: 60fb str r3, [r7, #12] + for(uIndex = 1; uIndex < 32; uIndex++) { + 800d43c: 68bb ldr r3, [r7, #8] + 800d43e: 3301 adds r3, #1 + 800d440: 60bb str r3, [r7, #8] + 800d442: 68bb ldr r3, [r7, #8] + 800d444: 2b1f cmp r3, #31 + 800d446: d9ed bls.n 800d424 + } + return uRevData; + 800d448: 68fb ldr r3, [r7, #12] +} + 800d44a: 4618 mov r0, r3 + 800d44c: 3714 adds r7, #20 + 800d44e: 46bd mov sp, r7 + 800d450: bc80 pop {r7} + 800d452: 4770 bx lr + +0800d454 : + +uint32_t CRC32_ForBytes(uint8_t *pData, uint32_t uLen) { + 800d454: b580 push {r7, lr} + 800d456: b086 sub sp, #24 + 800d458: af00 add r7, sp, #0 + 800d45a: 6078 str r0, [r7, #4] + 800d45c: 6039 str r1, [r7, #0] + uint32_t uIndex = 0, uData = 0, i; + 800d45e: 2300 movs r3, #0 + 800d460: 617b str r3, [r7, #20] + 800d462: 2300 movs r3, #0 + 800d464: 60fb str r3, [r7, #12] + uIndex = uLen >> 2; + 800d466: 683b ldr r3, [r7, #0] + 800d468: 089b lsrs r3, r3, #2 + 800d46a: 617b str r3, [r7, #20] + + SERIAL_PROTOCOL_CRC_CLK_ENABLE(); + 800d46c: 4b3d ldr r3, [pc, #244] @ (800d564 ) + 800d46e: 695b ldr r3, [r3, #20] + 800d470: 4a3c ldr r2, [pc, #240] @ (800d564 ) + 800d472: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800d476: 6153 str r3, [r2, #20] + 800d478: 4b3a ldr r3, [pc, #232] @ (800d564 ) + 800d47a: 695b ldr r3, [r3, #20] + 800d47c: f003 0340 and.w r3, r3, #64 @ 0x40 + 800d480: 60bb str r3, [r7, #8] + 800d482: 68bb ldr r3, [r7, #8] + + __HAL_CRC_DR_RESET(&hcrc); + 800d484: 4b38 ldr r3, [pc, #224] @ (800d568 ) + 800d486: 681b ldr r3, [r3, #0] + 800d488: 689a ldr r2, [r3, #8] + 800d48a: 4b37 ldr r3, [pc, #220] @ (800d568 ) + 800d48c: 681b ldr r3, [r3, #0] + 800d48e: f042 0201 orr.w r2, r2, #1 + 800d492: 609a str r2, [r3, #8] + + while(uIndex--) { + 800d494: e023 b.n 800d4de + ((uint8_t *) & uData)[0] = pData[0]; + 800d496: f107 030c add.w r3, r7, #12 + 800d49a: 687a ldr r2, [r7, #4] + 800d49c: 7812 ldrb r2, [r2, #0] + 800d49e: 701a strb r2, [r3, #0] + ((uint8_t *) & uData)[1] = pData[1]; + 800d4a0: f107 030c add.w r3, r7, #12 + 800d4a4: 3301 adds r3, #1 + 800d4a6: 687a ldr r2, [r7, #4] + 800d4a8: 7852 ldrb r2, [r2, #1] + 800d4aa: 701a strb r2, [r3, #0] + ((uint8_t *) & uData)[2] = pData[2]; + 800d4ac: f107 030c add.w r3, r7, #12 + 800d4b0: 3302 adds r3, #2 + 800d4b2: 687a ldr r2, [r7, #4] + 800d4b4: 7892 ldrb r2, [r2, #2] + 800d4b6: 701a strb r2, [r3, #0] + ((uint8_t *) & uData)[3] = pData[3]; + 800d4b8: f107 030c add.w r3, r7, #12 + 800d4bc: 3303 adds r3, #3 + 800d4be: 687a ldr r2, [r7, #4] + 800d4c0: 78d2 ldrb r2, [r2, #3] + 800d4c2: 701a strb r2, [r3, #0] + pData += 4; + 800d4c4: 687b ldr r3, [r7, #4] + 800d4c6: 3304 adds r3, #4 + 800d4c8: 607b str r3, [r7, #4] + uData = revbit(uData); + 800d4ca: 68fb ldr r3, [r7, #12] + 800d4cc: 4618 mov r0, r3 + 800d4ce: f7ff ff95 bl 800d3fc + 800d4d2: 4603 mov r3, r0 + 800d4d4: 60fb str r3, [r7, #12] + hcrc.Instance->DR = uData; + 800d4d6: 4b24 ldr r3, [pc, #144] @ (800d568 ) + 800d4d8: 681b ldr r3, [r3, #0] + 800d4da: 68fa ldr r2, [r7, #12] + 800d4dc: 601a str r2, [r3, #0] + while(uIndex--) { + 800d4de: 697b ldr r3, [r7, #20] + 800d4e0: 1e5a subs r2, r3, #1 + 800d4e2: 617a str r2, [r7, #20] + 800d4e4: 2b00 cmp r3, #0 + 800d4e6: d1d6 bne.n 800d496 + } + uData = revbit(hcrc.Instance->DR); + 800d4e8: 4b1f ldr r3, [pc, #124] @ (800d568 ) + 800d4ea: 681b ldr r3, [r3, #0] + 800d4ec: 681b ldr r3, [r3, #0] + 800d4ee: 4618 mov r0, r3 + 800d4f0: f7ff ff84 bl 800d3fc + 800d4f4: 4603 mov r3, r0 + 800d4f6: 60fb str r3, [r7, #12] + uIndex = uLen & 0x03; + 800d4f8: 683b ldr r3, [r7, #0] + 800d4fa: f003 0303 and.w r3, r3, #3 + 800d4fe: 617b str r3, [r7, #20] + while(uIndex--) { + 800d500: e01e b.n 800d540 + uData ^= (uint32_t) * pData++; + 800d502: 687b ldr r3, [r7, #4] + 800d504: 1c5a adds r2, r3, #1 + 800d506: 607a str r2, [r7, #4] + 800d508: 781b ldrb r3, [r3, #0] + 800d50a: 461a mov r2, r3 + 800d50c: 68fb ldr r3, [r7, #12] + 800d50e: 4053 eors r3, r2 + 800d510: 60fb str r3, [r7, #12] + for(i = 0; i < 8; i++) + 800d512: 2300 movs r3, #0 + 800d514: 613b str r3, [r7, #16] + 800d516: e010 b.n 800d53a + if (uData & 0x1) + 800d518: 68fb ldr r3, [r7, #12] + 800d51a: f003 0301 and.w r3, r3, #1 + 800d51e: 2b00 cmp r3, #0 + 800d520: d005 beq.n 800d52e + uData = (uData >> 1) ^ CRC32_POLYNOMIAL; + 800d522: 68fb ldr r3, [r7, #12] + 800d524: 085a lsrs r2, r3, #1 + 800d526: 4b11 ldr r3, [pc, #68] @ (800d56c ) + 800d528: 4053 eors r3, r2 + 800d52a: 60fb str r3, [r7, #12] + 800d52c: e002 b.n 800d534 + else + uData >>= 1; + 800d52e: 68fb ldr r3, [r7, #12] + 800d530: 085b lsrs r3, r3, #1 + 800d532: 60fb str r3, [r7, #12] + for(i = 0; i < 8; i++) + 800d534: 693b ldr r3, [r7, #16] + 800d536: 3301 adds r3, #1 + 800d538: 613b str r3, [r7, #16] + 800d53a: 693b ldr r3, [r7, #16] + 800d53c: 2b07 cmp r3, #7 + 800d53e: d9eb bls.n 800d518 + while(uIndex--) { + 800d540: 697b ldr r3, [r7, #20] + 800d542: 1e5a subs r2, r3, #1 + 800d544: 617a str r2, [r7, #20] + 800d546: 2b00 cmp r3, #0 + 800d548: d1db bne.n 800d502 + } + + SERIAL_PROTOCOL_CRC_CLK_DISABLE(); + 800d54a: 4b06 ldr r3, [pc, #24] @ (800d564 ) + 800d54c: 695b ldr r3, [r3, #20] + 800d54e: 4a05 ldr r2, [pc, #20] @ (800d564 ) + 800d550: f023 0340 bic.w r3, r3, #64 @ 0x40 + 800d554: 6153 str r3, [r2, #20] + + return uData ^ 0xFFFFFFFF; + 800d556: 68fb ldr r3, [r7, #12] + 800d558: 43db mvns r3, r3 +} + 800d55a: 4618 mov r0, r3 + 800d55c: 3718 adds r7, #24 + 800d55e: 46bd mov sp, r7 + 800d560: bd80 pop {r7, pc} + 800d562: bf00 nop + 800d564: 40021000 .word 0x40021000 + 800d568: 200003d0 .word 0x200003d0 + 800d56c: edb88320 .word 0xedb88320 + +0800d570 : + +uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { + 800d570: b580 push {r7, lr} + 800d572: b082 sub sp, #8 + 800d574: af00 add r7, sp, #0 + 800d576: 6078 str r0, [r7, #4] + 800d578: 460b mov r3, r1 + 800d57a: 807b strh r3, [r7, #2] + return CRC32_ForBytes((uint8_t*)data, (uint32_t)length); + 800d57c: 887b ldrh r3, [r7, #2] + 800d57e: 4619 mov r1, r3 + 800d580: 6878 ldr r0, [r7, #4] + 800d582: f7ff ff67 bl 800d454 + 800d586: 4603 mov r3, r0 +} + 800d588: 4618 mov r0, r3 + 800d58a: 3708 adds r7, #8 + 800d58c: 46bd mov sp, r7 + 800d58e: bd80 pop {r7, pc} + +0800d590 : + +uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { + 800d590: b580 push {r7, lr} + 800d592: b088 sub sp, #32 + 800d594: af00 add r7, sp, #0 + 800d596: 60f8 str r0, [r7, #12] + 800d598: 607a str r2, [r7, #4] + 800d59a: 461a mov r2, r3 + 800d59c: 460b mov r3, r1 + 800d59e: 817b strh r3, [r7, #10] + 800d5a0: 4613 mov r3, r2 + 800d5a2: 727b strb r3, [r7, #9] + uint16_t out_index = 0; + 800d5a4: 2300 movs r3, #0 + 800d5a6: 83fb strh r3, [r7, #30] + + output[out_index++] = response_code; + 800d5a8: 8bfb ldrh r3, [r7, #30] + 800d5aa: 1c5a adds r2, r3, #1 + 800d5ac: 83fa strh r2, [r7, #30] + 800d5ae: 461a mov r2, r3 + 800d5b0: 687b ldr r3, [r7, #4] + 800d5b2: 4413 add r3, r2 + 800d5b4: 7a7a ldrb r2, [r7, #9] + 800d5b6: 701a strb r2, [r3, #0] + + if (payload != NULL) { + 800d5b8: 68fb ldr r3, [r7, #12] + 800d5ba: 2b00 cmp r3, #0 + 800d5bc: d019 beq.n 800d5f2 + // Просто копируем полезную нагрузку без какого‑либо экранирования + for (uint16_t i = 0; i < payload_len; i++) { + 800d5be: 2300 movs r3, #0 + 800d5c0: 83bb strh r3, [r7, #28] + 800d5c2: e012 b.n 800d5ea + output[out_index++] = payload[i]; + 800d5c4: 8bbb ldrh r3, [r7, #28] + 800d5c6: 68fa ldr r2, [r7, #12] + 800d5c8: 441a add r2, r3 + 800d5ca: 8bfb ldrh r3, [r7, #30] + 800d5cc: 1c59 adds r1, r3, #1 + 800d5ce: 83f9 strh r1, [r7, #30] + 800d5d0: 4619 mov r1, r3 + 800d5d2: 687b ldr r3, [r7, #4] + 800d5d4: 440b add r3, r1 + 800d5d6: 7812 ldrb r2, [r2, #0] + 800d5d8: 701a strb r2, [r3, #0] + + // Проверка переполнения + if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE + 800d5da: 8bfb ldrh r3, [r7, #30] + 800d5dc: 2bfa cmp r3, #250 @ 0xfa + 800d5de: d901 bls.n 800d5e4 + return 0; + 800d5e0: 2300 movs r3, #0 + 800d5e2: e02a b.n 800d63a + for (uint16_t i = 0; i < payload_len; i++) { + 800d5e4: 8bbb ldrh r3, [r7, #28] + 800d5e6: 3301 adds r3, #1 + 800d5e8: 83bb strh r3, [r7, #28] + 800d5ea: 8bba ldrh r2, [r7, #28] + 800d5ec: 897b ldrh r3, [r7, #10] + 800d5ee: 429a cmp r2, r3 + 800d5f0: d3e8 bcc.n 800d5c4 + } + } + } + + // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) + uint32_t crc = calculate_crc32(output, out_index); + 800d5f2: 8bfb ldrh r3, [r7, #30] + 800d5f4: 4619 mov r1, r3 + 800d5f6: 6878 ldr r0, [r7, #4] + 800d5f8: f7ff ffba bl 800d570 + 800d5fc: 4603 mov r3, r0 + 800d5fe: 613b str r3, [r7, #16] + uint8_t* crc_bytes = (uint8_t*)&crc; + 800d600: f107 0310 add.w r3, r7, #16 + 800d604: 617b str r3, [r7, #20] + + // Добавляем CRC без экранирования + for (int i = 0; i < 4; i++) { + 800d606: 2300 movs r3, #0 + 800d608: 61bb str r3, [r7, #24] + 800d60a: e012 b.n 800d632 + output[out_index++] = crc_bytes[i]; + 800d60c: 69bb ldr r3, [r7, #24] + 800d60e: 697a ldr r2, [r7, #20] + 800d610: 441a add r2, r3 + 800d612: 8bfb ldrh r3, [r7, #30] + 800d614: 1c59 adds r1, r3, #1 + 800d616: 83f9 strh r1, [r7, #30] + 800d618: 4619 mov r1, r3 + 800d61a: 687b ldr r3, [r7, #4] + 800d61c: 440b add r3, r1 + 800d61e: 7812 ldrb r2, [r2, #0] + 800d620: 701a strb r2, [r3, #0] + + if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE + 800d622: 8bfb ldrh r3, [r7, #30] + 800d624: 2bfe cmp r3, #254 @ 0xfe + 800d626: d901 bls.n 800d62c + return 0; + 800d628: 2300 movs r3, #0 + 800d62a: e006 b.n 800d63a + for (int i = 0; i < 4; i++) { + 800d62c: 69bb ldr r3, [r7, #24] + 800d62e: 3301 adds r3, #1 + 800d630: 61bb str r3, [r7, #24] + 800d632: 69bb ldr r3, [r7, #24] + 800d634: 2b03 cmp r3, #3 + 800d636: dde9 ble.n 800d60c + } + } + + return out_index; + 800d638: 8bfb ldrh r3, [r7, #30] +} + 800d63a: 4618 mov r0, r3 + 800d63c: 3720 adds r7, #32 + 800d63e: 46bd mov sp, r7 + 800d640: bd80 pop {r7, pc} + ... + +0800d644 : + +void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { + 800d644: b580 push {r7, lr} + 800d646: b084 sub sp, #16 + 800d648: af00 add r7, sp, #0 + 800d64a: 6078 str r0, [r7, #4] + 800d64c: 460b mov r3, r1 + 800d64e: 807b strh r3, [r7, #2] + 800d650: 4613 mov r3, r2 + 800d652: 707b strb r3, [r7, #1] + uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); + 800d654: 787b ldrb r3, [r7, #1] + 800d656: 8879 ldrh r1, [r7, #2] + 800d658: 4a15 ldr r2, [pc, #84] @ (800d6b0 ) + 800d65a: 6878 ldr r0, [r7, #4] + 800d65c: f7ff ff98 bl 800d590 + 800d660: 4603 mov r3, r0 + 800d662: 81fb strh r3, [r7, #14] + + if (packet_len > 0) { + 800d664: 89fb ldrh r3, [r7, #14] + 800d666: 2b00 cmp r3, #0 + 800d668: d01e beq.n 800d6a8 + if (huart2.gState == HAL_UART_STATE_BUSY_TX) { + 800d66a: 4b12 ldr r3, [pc, #72] @ (800d6b4 ) + 800d66c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800d670: b2db uxtb r3, r3 + 800d672: 2b21 cmp r3, #33 @ 0x21 + 800d674: d107 bne.n 800d686 + HAL_UART_Abort_IT(&huart2); + 800d676: 480f ldr r0, [pc, #60] @ (800d6b4 ) + 800d678: f005 f91c bl 80128b4 + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); + 800d67c: 2200 movs r2, #0 + 800d67e: 2110 movs r1, #16 + 800d680: 480d ldr r0, [pc, #52] @ (800d6b8 ) + 800d682: f003 f8ac bl 80107de + } + + HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); + 800d686: 2201 movs r2, #1 + 800d688: 2110 movs r1, #16 + 800d68a: 480b ldr r0, [pc, #44] @ (800d6b8 ) + 800d68c: f003 f8a7 bl 80107de + + HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); + 800d690: 89fb ldrh r3, [r7, #14] + 800d692: 461a mov r2, r3 + 800d694: 4906 ldr r1, [pc, #24] @ (800d6b0 ) + 800d696: 4807 ldr r0, [pc, #28] @ (800d6b4 ) + 800d698: f005 f87a bl 8012790 + + serial_control.tx_tick = HAL_GetTick(); + 800d69c: f001 f898 bl 800e7d0 + 800d6a0: 4603 mov r3, r0 + 800d6a2: 4a03 ldr r2, [pc, #12] @ (800d6b0 ) + 800d6a4: f8c2 320c str.w r3, [r2, #524] @ 0x20c + } +} + 800d6a8: bf00 nop + 800d6aa: 3710 adds r7, #16 + 800d6ac: 46bd mov sp, r7 + 800d6ae: bd80 pop {r7, pc} + 800d6b0: 20000a80 .word 0x20000a80 + 800d6b4: 20000dd0 .word 0x20000dd0 + 800d6b8: 40011400 .word 0x40011400 + +0800d6bc : + +uint8_t process_received_packet(const uint8_t* packet_data, uint16_t packet_len) { + 800d6bc: b580 push {r7, lr} + 800d6be: b086 sub sp, #24 + 800d6c0: af00 add r7, sp, #0 + 800d6c2: 6078 str r0, [r7, #4] + 800d6c4: 460b mov r3, r1 + 800d6c6: 807b strh r3, [r7, #2] + // }else{ + // test_crc_invalid = 5; + // } + + // Минимальный размер: 1 байт команды + 4 байта CRC + if (packet_len < 5) return 0; + 800d6c8: 887b ldrh r3, [r7, #2] + 800d6ca: 2b04 cmp r3, #4 + 800d6cc: d801 bhi.n 800d6d2 + 800d6ce: 2300 movs r3, #0 + 800d6d0: e046 b.n 800d760 + if (packet_len > MAX_RX_BUFFER_SIZE) return 0; + 800d6d2: 887b ldrh r3, [r7, #2] + 800d6d4: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800d6d8: d901 bls.n 800d6de + 800d6da: 2300 movs r3, #0 + 800d6dc: e040 b.n 800d760 + + uint16_t payload_length = packet_len - 4; + 800d6de: 887b ldrh r3, [r7, #2] + 800d6e0: 3b04 subs r3, #4 + 800d6e2: 82fb strh r3, [r7, #22] + + // Извлекаем принятую CRC (последние 4 байта, little-endian) + uint32_t received_checksum = + ((uint32_t)packet_data[payload_length] << 0) | + 800d6e4: 8afb ldrh r3, [r7, #22] + 800d6e6: 687a ldr r2, [r7, #4] + 800d6e8: 4413 add r3, r2 + 800d6ea: 781b ldrb r3, [r3, #0] + 800d6ec: 4619 mov r1, r3 + ((uint32_t)packet_data[payload_length + 1] << 8) | + 800d6ee: 8afb ldrh r3, [r7, #22] + 800d6f0: 3301 adds r3, #1 + 800d6f2: 687a ldr r2, [r7, #4] + 800d6f4: 4413 add r3, r2 + 800d6f6: 781b ldrb r3, [r3, #0] + 800d6f8: 021b lsls r3, r3, #8 + ((uint32_t)packet_data[payload_length] << 0) | + 800d6fa: ea41 0203 orr.w r2, r1, r3 + ((uint32_t)packet_data[payload_length + 2] << 16) | + 800d6fe: 8afb ldrh r3, [r7, #22] + 800d700: 3302 adds r3, #2 + 800d702: 6879 ldr r1, [r7, #4] + 800d704: 440b add r3, r1 + 800d706: 781b ldrb r3, [r3, #0] + 800d708: 041b lsls r3, r3, #16 + ((uint32_t)packet_data[payload_length + 1] << 8) | + 800d70a: 431a orrs r2, r3 + ((uint32_t)packet_data[payload_length + 3] << 24); + 800d70c: 8afb ldrh r3, [r7, #22] + 800d70e: 3303 adds r3, #3 + 800d710: 6879 ldr r1, [r7, #4] + 800d712: 440b add r3, r1 + 800d714: 781b ldrb r3, [r3, #0] + 800d716: 061b lsls r3, r3, #24 + uint32_t received_checksum = + 800d718: 4313 orrs r3, r2 + 800d71a: 613b str r3, [r7, #16] + + // Вычисляем CRC для полезной нагрузки + uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); + 800d71c: 8afb ldrh r3, [r7, #22] + 800d71e: 4619 mov r1, r3 + 800d720: 6878 ldr r0, [r7, #4] + 800d722: f7ff ff25 bl 800d570 + 800d726: 60f8 str r0, [r7, #12] + + if (received_checksum != calculated_checksum) return 0; // CRC не совпадает + 800d728: 693a ldr r2, [r7, #16] + 800d72a: 68fb ldr r3, [r7, #12] + 800d72c: 429a cmp r2, r3 + 800d72e: d001 beq.n 800d734 + 800d730: 2300 movs r3, #0 + 800d732: e015 b.n 800d760 + + serial_control.received_command.argument = &packet_data[1]; + 800d734: 687b ldr r3, [r7, #4] + 800d736: 3301 adds r3, #1 + 800d738: 4a0b ldr r2, [pc, #44] @ (800d768 ) + 800d73a: f8c2 3204 str.w r3, [r2, #516] @ 0x204 + serial_control.received_command.command = packet_data[0]; + 800d73e: 687b ldr r3, [r7, #4] + 800d740: 781a ldrb r2, [r3, #0] + 800d742: 4b09 ldr r3, [pc, #36] @ (800d768 ) + 800d744: f883 2200 strb.w r2, [r3, #512] @ 0x200 + serial_control.received_command.argument_length = payload_length - 1; + 800d748: 8afb ldrh r3, [r7, #22] + 800d74a: b2db uxtb r3, r3 + 800d74c: 3b01 subs r3, #1 + 800d74e: b2da uxtb r2, r3 + 800d750: 4b05 ldr r3, [pc, #20] @ (800d768 ) + 800d752: f883 2201 strb.w r2, [r3, #513] @ 0x201 + serial_control.command_ready = 1; + 800d756: 4b04 ldr r3, [pc, #16] @ (800d768 ) + 800d758: 2201 movs r2, #1 + 800d75a: f883 2208 strb.w r2, [r3, #520] @ 0x208 + return 1; + 800d75e: 2301 movs r3, #1 +} + 800d760: 4618 mov r0, r3 + 800d762: 3718 adds r7, #24 + 800d764: 46bd mov sp, r7 + 800d766: bd80 pop {r7, pc} + 800d768: 20000a80 .word 0x20000a80 + +0800d76c <__NVIC_SystemReset>: +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + 800d76c: b480 push {r7} + 800d76e: af00 add r7, sp, #0 + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 800d770: f3bf 8f4f dsb sy +} + 800d774: bf00 nop + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 800d776: 4b06 ldr r3, [pc, #24] @ (800d790 <__NVIC_SystemReset+0x24>) + 800d778: 68db ldr r3, [r3, #12] + 800d77a: f403 62e0 and.w r2, r3, #1792 @ 0x700 + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 800d77e: 4904 ldr r1, [pc, #16] @ (800d790 <__NVIC_SystemReset+0x24>) + 800d780: 4b04 ldr r3, [pc, #16] @ (800d794 <__NVIC_SystemReset+0x28>) + 800d782: 4313 orrs r3, r2 + 800d784: 60cb str r3, [r1, #12] + __ASM volatile ("dsb 0xF":::"memory"); + 800d786: f3bf 8f4f dsb sy +} + 800d78a: bf00 nop + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + 800d78c: bf00 nop + 800d78e: e7fd b.n 800d78c <__NVIC_SystemReset+0x20> + 800d790: e000ed00 .word 0xe000ed00 + 800d794: 05fa0004 .word 0x05fa0004 + +0800d798 : + .chargerNumber = 00001, + .unixTime = 1721651966, +}; + +// Единая функция-обработчик всех команд со switch-case +void SC_CommandHandler(ReceivedCommand_t* cmd) { + 800d798: b580 push {r7, lr} + 800d79a: b084 sub sp, #16 + 800d79c: af00 add r7, sp, #0 + 800d79e: 6078 str r0, [r7, #4] + + uint8_t response_code = RESP_FAILED; + 800d7a0: 2313 movs r3, #19 + 800d7a2: 73fb strb r3, [r7, #15] + + switch (cmd->command) { + 800d7a4: 687b ldr r3, [r7, #4] + 800d7a6: 781b ldrb r3, [r3, #0] + 800d7a8: 2bc2 cmp r3, #194 @ 0xc2 + 800d7aa: f300 80b0 bgt.w 800d90e + 800d7ae: 2bb0 cmp r3, #176 @ 0xb0 + 800d7b0: da09 bge.n 800d7c6 + 800d7b2: 2b60 cmp r3, #96 @ 0x60 + 800d7b4: d03c beq.n 800d830 + 800d7b6: 2b60 cmp r3, #96 @ 0x60 + 800d7b8: f300 80a9 bgt.w 800d90e + 800d7bc: 2b40 cmp r3, #64 @ 0x40 + 800d7be: d02f beq.n 800d820 + 800d7c0: 2b50 cmp r3, #80 @ 0x50 + 800d7c2: d03b beq.n 800d83c + 800d7c4: e0a3 b.n 800d90e + 800d7c6: 3bb0 subs r3, #176 @ 0xb0 + 800d7c8: 2b12 cmp r3, #18 + 800d7ca: f200 80a0 bhi.w 800d90e + 800d7ce: a201 add r2, pc, #4 @ (adr r2, 800d7d4 ) + 800d7d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800d7d4: 0800d843 .word 0x0800d843 + 800d7d8: 0800d90f .word 0x0800d90f + 800d7dc: 0800d90f .word 0x0800d90f + 800d7e0: 0800d90f .word 0x0800d90f + 800d7e4: 0800d90f .word 0x0800d90f + 800d7e8: 0800d8f3 .word 0x0800d8f3 + 800d7ec: 0800d90f .word 0x0800d90f + 800d7f0: 0800d90f .word 0x0800d90f + 800d7f4: 0800d90f .word 0x0800d90f + 800d7f8: 0800d90f .word 0x0800d90f + 800d7fc: 0800d90f .word 0x0800d90f + 800d800: 0800d90f .word 0x0800d90f + 800d804: 0800d90f .word 0x0800d90f + 800d808: 0800d90f .word 0x0800d90f + 800d80c: 0800d90f .word 0x0800d90f + 800d810: 0800d90f .word 0x0800d90f + 800d814: 0800d889 .word 0x0800d889 + 800d818: 0800d8ed .word 0x0800d8ed + 800d81c: 0800d8c1 .word 0x0800d8c1 + // Команды БЕЗ аргументов + case CMD_GET_STATUS: + // Логика получения информации + monitoring_data_callback(); + 800d820: f000 f896 bl 800d950 + + // Отправляем с нормальным приоритетом + SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); + 800d824: 2240 movs r2, #64 @ 0x40 + 800d826: 2158 movs r1, #88 @ 0x58 + 800d828: 483f ldr r0, [pc, #252] @ (800d928 ) + 800d82a: f7ff ff0b bl 800d644 + return; // Специальный ответ уже отправлен + 800d82e: e077 b.n 800d920 + + case CMD_GET_INFO: + SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); + 800d830: 2260 movs r2, #96 @ 0x60 + 800d832: 210a movs r1, #10 + 800d834: 483d ldr r0, [pc, #244] @ (800d92c ) + 800d836: f7ff ff05 bl 800d644 + return; + 800d83a: e071 b.n 800d920 + + case CMD_GET_LOG: + debug_buffer_send(); + 800d83c: f7fd fdb0 bl 800b3a0 + return; // Ответ формируется внутри debug_buffer_send + 800d840: e06e b.n 800d920 + + // Команды С аргументами + + case CMD_SET_CONFIG: + if (cmd->argument_length == sizeof(ConfigBlock_t)) { + 800d842: 687b ldr r3, [r7, #4] + 800d844: 785b ldrb r3, [r3, #1] + 800d846: 2b0b cmp r3, #11 + 800d848: d11b bne.n 800d882 + memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); + 800d84a: 687b ldr r3, [r7, #4] + 800d84c: 685a ldr r2, [r3, #4] + 800d84e: 4b38 ldr r3, [pc, #224] @ (800d930 ) + 800d850: 6810 ldr r0, [r2, #0] + 800d852: 6851 ldr r1, [r2, #4] + 800d854: c303 stmia r3!, {r0, r1} + 800d856: 8911 ldrh r1, [r2, #8] + 800d858: 7a92 ldrb r2, [r2, #10] + 800d85a: 8019 strh r1, [r3, #0] + 800d85c: 709a strb r2, [r3, #2] + GBT_SetConfig(); + 800d85e: f7fc fac7 bl 8009df0 + config_initialized = 1; + 800d862: 4b34 ldr r3, [pc, #208] @ (800d934 ) + 800d864: 2201 movs r2, #1 + 800d866: 701a strb r2, [r3, #0] + GBT_SetConfig(); + 800d868: f7fc fac2 bl 8009df0 +// CONN.connState = CONN_Available; // + log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); + 800d86c: 4b30 ldr r3, [pc, #192] @ (800d930 ) + 800d86e: f8d3 3003 ldr.w r3, [r3, #3] + 800d872: 4a2f ldr r2, [pc, #188] @ (800d930 ) + 800d874: 4930 ldr r1, [pc, #192] @ (800d938 ) + 800d876: 2007 movs r0, #7 + 800d878: f7fd fdf4 bl 800b464 + response_code = RESP_SUCCESS; + 800d87c: 2312 movs r3, #18 + 800d87e: 73fb strb r3, [r7, #15] + break; + 800d880: e048 b.n 800d914 + } + response_code = RESP_FAILED; + 800d882: 2313 movs r3, #19 + 800d884: 73fb strb r3, [r7, #15] + break; + 800d886: e045 b.n 800d914 + case CMD_SET_POWER_LIMIT: + if (cmd->argument_length == 1) { + 800d888: 687b ldr r3, [r7, #4] + 800d88a: 785b ldrb r3, [r3, #1] + 800d88c: 2b01 cmp r3, #1 + 800d88e: d114 bne.n 800d8ba + PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; + 800d890: 687b ldr r3, [r7, #4] + 800d892: 685b ldr r3, [r3, #4] + 800d894: 781b ldrb r3, [r3, #0] + 800d896: 461a mov r2, r3 + 800d898: f44f 737a mov.w r3, #1000 @ 0x3e8 + 800d89c: fb02 f303 mul.w r3, r2, r3 + 800d8a0: 461a mov r2, r3 + 800d8a2: 4b26 ldr r3, [pc, #152] @ (800d93c ) + 800d8a4: 615a str r2, [r3, #20] + log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); + 800d8a6: 4b25 ldr r3, [pc, #148] @ (800d93c ) + 800d8a8: 695b ldr r3, [r3, #20] + 800d8aa: 461a mov r2, r3 + 800d8ac: 4924 ldr r1, [pc, #144] @ (800d940 ) + 800d8ae: 2007 movs r0, #7 + 800d8b0: f7fd fdd8 bl 800b464 + //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; + response_code = RESP_SUCCESS; + 800d8b4: 2312 movs r3, #18 + 800d8b6: 73fb strb r3, [r7, #15] + break; + 800d8b8: e02c b.n 800d914 + } + response_code = RESP_FAILED; + 800d8ba: 2313 movs r3, #19 + 800d8bc: 73fb strb r3, [r7, #15] + break; + 800d8be: e029 b.n 800d914 + case CMD_CHARGE_PERMIT: + if (cmd->argument_length == 1) { + 800d8c0: 687b ldr r3, [r7, #4] + 800d8c2: 785b ldrb r3, [r3, #1] + 800d8c4: 2b01 cmp r3, #1 + 800d8c6: d10e bne.n 800d8e6 + CONN.connControl = ((uint8_t*)cmd->argument)[0]; + 800d8c8: 687b ldr r3, [r7, #4] + 800d8ca: 685b ldr r3, [r3, #4] + 800d8cc: 781a ldrb r2, [r3, #0] + 800d8ce: 4b1d ldr r3, [pc, #116] @ (800d944 ) + 800d8d0: 701a strb r2, [r3, #0] + log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); + 800d8d2: 4b1c ldr r3, [pc, #112] @ (800d944 ) + 800d8d4: 781b ldrb r3, [r3, #0] + 800d8d6: 461a mov r2, r3 + 800d8d8: 491b ldr r1, [pc, #108] @ (800d948 ) + 800d8da: 2007 movs r0, #7 + 800d8dc: f7fd fdc2 bl 800b464 + response_code = RESP_SUCCESS; + 800d8e0: 2312 movs r3, #18 + 800d8e2: 73fb strb r3, [r7, #15] + break; + 800d8e4: e016 b.n 800d914 + } + response_code = RESP_FAILED; + 800d8e6: 2313 movs r3, #19 + 800d8e8: 73fb strb r3, [r7, #15] + break; + 800d8ea: e013 b.n 800d914 + // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); + // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); + // response_code = RESP_SUCCESS; + // break; + // } + response_code = RESP_FAILED; + 800d8ec: 2313 movs r3, #19 + 800d8ee: 73fb strb r3, [r7, #15] + break; + 800d8f0: e010 b.n 800d914 + case CMD_DEVICE_RESET: + // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) + SC_SendPacket(NULL, 0, RESP_SUCCESS); + 800d8f2: 2212 movs r2, #18 + 800d8f4: 2100 movs r1, #0 + 800d8f6: 2000 movs r0, #0 + 800d8f8: f7ff fea4 bl 800d644 + + while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи + 800d8fc: bf00 nop + 800d8fe: 4b13 ldr r3, [pc, #76] @ (800d94c ) + 800d900: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800d904: b2db uxtb r3, r3 + 800d906: 2b21 cmp r3, #33 @ 0x21 + 800d908: d0f9 beq.n 800d8fe + // 3. Выполняем программный сброс + NVIC_SystemReset(); + 800d90a: f7ff ff2f bl 800d76c <__NVIC_SystemReset> + return; // Сюда код уже не дойдет, но для компилятора нужно + + default: + // Неизвестная команда + response_code = RESP_FAILED; + 800d90e: 2313 movs r3, #19 + 800d910: 73fb strb r3, [r7, #15] + break; + 800d912: bf00 nop + } + + // Отправляем финальный ответ (для команд без собственного ответа) + SC_SendPacket(NULL, 0, response_code); + 800d914: 7bfb ldrb r3, [r7, #15] + 800d916: 461a mov r2, r3 + 800d918: 2100 movs r1, #0 + 800d91a: 2000 movs r0, #0 + 800d91c: f7ff fe92 bl 800d644 +} + 800d920: 3710 adds r7, #16 + 800d922: 46bd mov sp, r7 + 800d924: bd80 pop {r7, pc} + 800d926: bf00 nop + 800d928: 20000c90 .word 0x20000c90 + 800d92c: 20000ce8 .word 0x20000ce8 + 800d930: 20000060 .word 0x20000060 + 800d934: 20000cf2 .word 0x20000cf2 + 800d938: 08016b8c .word 0x08016b8c + 800d93c: 200009fc .word 0x200009fc + 800d940: 08016ba0 .word 0x08016ba0 + 800d944: 200002e8 .word 0x200002e8 + 800d948: 08016bb4 .word 0x08016bb4 + 800d94c: 20000dd0 .word 0x20000dd0 + +0800d950 : + + +// Колбэк для заполнения данных мониторинга +void monitoring_data_callback() { + 800d950: b5b0 push {r4, r5, r7, lr} + 800d952: af00 add r7, sp, #0 + + // Информация о зарядной сессии + statusPacket.SOC = CONN.SOC; + 800d954: 4b9d ldr r3, [pc, #628] @ (800dbcc ) + 800d956: 789a ldrb r2, [r3, #2] + 800d958: 4b9d ldr r3, [pc, #628] @ (800dbd0 ) + 800d95a: 709a strb r2, [r3, #2] + statusPacket.Energy = CONN.Energy; + 800d95c: 4b9b ldr r3, [pc, #620] @ (800dbcc ) + 800d95e: f8d3 3007 ldr.w r3, [r3, #7] + 800d962: 4a9b ldr r2, [pc, #620] @ (800dbd0 ) + 800d964: f8c2 3003 str.w r3, [r2, #3] + statusPacket.RequestedVoltage = CONN.RequestedVoltage; + 800d968: 4b98 ldr r3, [pc, #608] @ (800dbcc ) + 800d96a: f8b3 300f ldrh.w r3, [r3, #15] + 800d96e: b29a uxth r2, r3 + 800d970: 4b97 ldr r3, [pc, #604] @ (800dbd0 ) + 800d972: f8a3 2007 strh.w r2, [r3, #7] + statusPacket.RequestedCurrent = CONN.WantedCurrent; + 800d976: 4b95 ldr r3, [pc, #596] @ (800dbcc ) + 800d978: f8b3 301b ldrh.w r3, [r3, #27] + 800d97c: b29a uxth r2, r3 + 800d97e: 4b94 ldr r3, [pc, #592] @ (800dbd0 ) + 800d980: f8a3 2009 strh.w r2, [r3, #9] + statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; + 800d984: 4b91 ldr r3, [pc, #580] @ (800dbcc ) + 800d986: f8b3 3013 ldrh.w r3, [r3, #19] + 800d98a: b29a uxth r2, r3 + 800d98c: 4b90 ldr r3, [pc, #576] @ (800dbd0 ) + 800d98e: f8a3 200b strh.w r2, [r3, #11] + statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; + 800d992: 4b8e ldr r3, [pc, #568] @ (800dbcc ) + 800d994: f8b3 3015 ldrh.w r3, [r3, #21] + 800d998: b29a uxth r2, r3 + 800d99a: 4b8d ldr r3, [pc, #564] @ (800dbd0 ) + 800d99c: f8a3 200d strh.w r2, [r3, #13] + statusPacket.outputEnabled = CONN.outputEnabled; + 800d9a0: 4b8a ldr r3, [pc, #552] @ (800dbcc ) + 800d9a2: 7e1a ldrb r2, [r3, #24] + 800d9a4: 4b8a ldr r3, [pc, #552] @ (800dbd0 ) + 800d9a6: 73da strb r2, [r3, #15] + statusPacket.chargingError = CONN.chargingError; + 800d9a8: 4b88 ldr r3, [pc, #544] @ (800dbcc ) + 800d9aa: 7f5a ldrb r2, [r3, #29] + 800d9ac: 4b88 ldr r3, [pc, #544] @ (800dbd0 ) + 800d9ae: 705a strb r2, [r3, #1] + statusPacket.connState = CONN.connState; + 800d9b0: 4b86 ldr r3, [pc, #536] @ (800dbcc ) + 800d9b2: 785a ldrb r2, [r3, #1] + 800d9b4: 4b86 ldr r3, [pc, #536] @ (800dbd0 ) + 800d9b6: 701a strb r2, [r3, #0] + statusPacket.chargingElapsedTimeMin = 0; + 800d9b8: 4b85 ldr r3, [pc, #532] @ (800dbd0 ) + 800d9ba: 2200 movs r2, #0 + 800d9bc: 741a strb r2, [r3, #16] + 800d9be: 2200 movs r2, #0 + 800d9c0: 745a strb r2, [r3, #17] + statusPacket.chargingElapsedTimeSec = 0; + 800d9c2: 4b83 ldr r3, [pc, #524] @ (800dbd0 ) + 800d9c4: 2200 movs r2, #0 + 800d9c6: 749a strb r2, [r3, #18] + statusPacket.estimatedRemainingChargingTime = 0; + 800d9c8: 4b81 ldr r3, [pc, #516] @ (800dbd0 ) + 800d9ca: 2200 movs r2, #0 + 800d9cc: 74da strb r2, [r3, #19] + 800d9ce: 2200 movs r2, #0 + 800d9d0: 751a strb r2, [r3, #20] + + // состояние зарядной станции + statusPacket.relayAC = RELAY_Read(RELAY_AC); + 800d9d2: 2004 movs r0, #4 + 800d9d4: f7fb feee bl 80097b4 + 800d9d8: 4603 mov r3, r0 + 800d9da: f003 0301 and.w r3, r3, #1 + 800d9de: b2d9 uxtb r1, r3 + 800d9e0: 4a7b ldr r2, [pc, #492] @ (800dbd0 ) + 800d9e2: 7d53 ldrb r3, [r2, #21] + 800d9e4: f361 0300 bfi r3, r1, #0, #1 + 800d9e8: 7553 strb r3, [r2, #21] + statusPacket.relayDC = RELAY_Read(RELAY_DC); + 800d9ea: 2003 movs r0, #3 + 800d9ec: f7fb fee2 bl 80097b4 + 800d9f0: 4603 mov r3, r0 + 800d9f2: f003 0301 and.w r3, r3, #1 + 800d9f6: b2d9 uxtb r1, r3 + 800d9f8: 4a75 ldr r2, [pc, #468] @ (800dbd0 ) + 800d9fa: 7d53 ldrb r3, [r2, #21] + 800d9fc: f361 0341 bfi r3, r1, #1, #1 + 800da00: 7553 strb r3, [r2, #21] + statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); + 800da02: 2000 movs r0, #0 + 800da04: f7fb fed6 bl 80097b4 + 800da08: 4603 mov r3, r0 + 800da0a: f003 0301 and.w r3, r3, #1 + 800da0e: b2d9 uxtb r1, r3 + 800da10: 4a6f ldr r2, [pc, #444] @ (800dbd0 ) + 800da12: 7d53 ldrb r3, [r2, #21] + 800da14: f361 0382 bfi r3, r1, #2, #1 + 800da18: 7553 strb r3, [r2, #21] + statusPacket.lockState = GBT_LockGetState(); + 800da1a: f7fe f9b1 bl 800bd80 + 800da1e: 4603 mov r3, r0 + 800da20: f003 0301 and.w r3, r3, #1 + 800da24: b2d9 uxtb r1, r3 + 800da26: 4a6a ldr r2, [pc, #424] @ (800dbd0 ) + 800da28: 7d53 ldrb r3, [r2, #21] + 800da2a: f361 03c3 bfi r3, r1, #3, #1 + 800da2e: 7553 strb r3, [r2, #21] + statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); + 800da30: 2003 movs r0, #3 + 800da32: f7fb fecf bl 80097d4 + 800da36: 4603 mov r3, r0 + 800da38: 2b00 cmp r3, #0 + 800da3a: bf0c ite eq + 800da3c: 2301 moveq r3, #1 + 800da3e: 2300 movne r3, #0 + 800da40: b2d9 uxtb r1, r3 + 800da42: 4a63 ldr r2, [pc, #396] @ (800dbd0 ) + 800da44: 7d53 ldrb r3, [r2, #21] + 800da46: f361 1304 bfi r3, r1, #4, #1 + 800da4a: 7553 strb r3, [r2, #21] + statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; + 800da4c: f7fd fc94 bl 800b378 + 800da50: 4603 mov r3, r0 + 800da52: 2b00 cmp r3, #0 + 800da54: bf14 ite ne + 800da56: 2301 movne r3, #1 + 800da58: 2300 moveq r3, #0 + 800da5a: b2d9 uxtb r1, r3 + 800da5c: 4a5c ldr r2, [pc, #368] @ (800dbd0 ) + 800da5e: 7d53 ldrb r3, [r2, #21] + 800da60: f361 1345 bfi r3, r1, #5, #1 + 800da64: 7553 strb r3, [r2, #21] + statusPacket.evInfoAvailable = GBT_BAT_STAT_recv; + 800da66: 4b5b ldr r3, [pc, #364] @ (800dbd4 ) + 800da68: 781b ldrb r3, [r3, #0] + 800da6a: f003 0301 and.w r3, r3, #1 + 800da6e: b2d9 uxtb r1, r3 + 800da70: 4a57 ldr r2, [pc, #348] @ (800dbd0 ) + 800da72: 7d53 ldrb r3, [r2, #21] + 800da74: f361 1386 bfi r3, r1, #6, #1 + 800da78: 7553 strb r3, [r2, #21] + statusPacket.psuOnline = PSU0.online; + 800da7a: 4b57 ldr r3, [pc, #348] @ (800dbd8 ) + 800da7c: 7a1b ldrb r3, [r3, #8] + 800da7e: f003 0301 and.w r3, r3, #1 + 800da82: b2d9 uxtb r1, r3 + 800da84: 4a52 ldr r2, [pc, #328] @ (800dbd0 ) + 800da86: 7d53 ldrb r3, [r2, #21] + 800da88: f361 13c7 bfi r3, r1, #7, #1 + 800da8c: 7553 strb r3, [r2, #21] + + statusPacket.tempConnector0 = GBT_ReadTemp(0); // температура коннектора + 800da8e: 2000 movs r0, #0 + 800da90: f7fb ff84 bl 800999c + 800da94: 4603 mov r3, r0 + 800da96: b25a sxtb r2, r3 + 800da98: 4b4d ldr r3, [pc, #308] @ (800dbd0 ) + 800da9a: 765a strb r2, [r3, #25] + statusPacket.tempConnector1 = GBT_ReadTemp(1); + 800da9c: 2001 movs r0, #1 + 800da9e: f7fb ff7d bl 800999c + 800daa2: 4603 mov r3, r0 + 800daa4: b25a sxtb r2, r3 + 800daa6: 4b4a ldr r3, [pc, #296] @ (800dbd0 ) + 800daa8: 769a strb r2, [r3, #26] + statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха + 800daaa: 4b4b ldr r3, [pc, #300] @ (800dbd8 ) + 800daac: 69db ldr r3, [r3, #28] + 800daae: b25a sxtb r2, r3 + 800dab0: 4b47 ldr r3, [pc, #284] @ (800dbd0 ) + 800dab2: 76da strb r2, [r3, #27] + statusPacket.tempBatteryMax = GBT_BatteryStatus.batteryHighestTemp; // максимальная температура батареи + 800dab4: 4b49 ldr r3, [pc, #292] @ (800dbdc ) + 800dab6: 785b ldrb r3, [r3, #1] + 800dab8: b25a sxtb r2, r3 + 800daba: 4b45 ldr r3, [pc, #276] @ (800dbd0 ) + 800dabc: 771a strb r2, [r3, #28] + statusPacket.tempBatteryMin = GBT_BatteryStatus.batteryLowestTemp; // минимальная температура батареи + 800dabe: 4b47 ldr r3, [pc, #284] @ (800dbdc ) + 800dac0: 78db ldrb r3, [r3, #3] + 800dac2: b25a sxtb r2, r3 + 800dac4: 4b42 ldr r3, [pc, #264] @ (800dbd0 ) + 800dac6: 775a strb r2, [r3, #29] + + statusPacket.highestVoltageOfBatteryCell = GBT_ChargingStatus.highestVoltageOfBatteryCell; + 800dac8: 4b45 ldr r3, [pc, #276] @ (800dbe0 ) + 800daca: 889b ldrh r3, [r3, #4] + 800dacc: b29a uxth r2, r3 + 800dace: 4b40 ldr r3, [pc, #256] @ (800dbd0 ) + 800dad0: 83da strh r2, [r3, #30] + statusPacket.batteryStatus = GBT_BatteryStatus.batteryStatus; + 800dad2: 4b42 ldr r3, [pc, #264] @ (800dbdc ) + 800dad4: 799a ldrb r2, [r3, #6] + 800dad6: 4b3e ldr r3, [pc, #248] @ (800dbd0 ) + 800dad8: f883 2020 strb.w r2, [r3, #32] + + statusPacket.phaseVoltageAB = PSU_06.VAB; + 800dadc: 4b41 ldr r3, [pc, #260] @ (800dbe4 ) + 800dade: 689b ldr r3, [r3, #8] + 800dae0: b29a uxth r2, r3 + 800dae2: 4b3b ldr r3, [pc, #236] @ (800dbd0 ) + 800dae4: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 + statusPacket.phaseVoltageBC = PSU_06.VBC; + 800dae8: 4b3e ldr r3, [pc, #248] @ (800dbe4 ) + 800daea: 68db ldr r3, [r3, #12] + 800daec: b29a uxth r2, r3 + 800daee: 4b38 ldr r3, [pc, #224] @ (800dbd0 ) + 800daf0: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 + statusPacket.phaseVoltageCA = PSU_06.VCA; + 800daf4: 4b3b ldr r3, [pc, #236] @ (800dbe4 ) + 800daf6: 691b ldr r3, [r3, #16] + 800daf8: b29a uxth r2, r3 + 800dafa: 4b35 ldr r3, [pc, #212] @ (800dbd0 ) + 800dafc: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 + + memcpy(statusPacket.VIN, GBT_EVInfo.EVIN, sizeof(GBT_EVInfo.EVIN)); + 800db00: 4b33 ldr r3, [pc, #204] @ (800dbd0 ) + 800db02: 4a39 ldr r2, [pc, #228] @ (800dbe8 ) + 800db04: 3327 adds r3, #39 @ 0x27 + 800db06: 3218 adds r2, #24 + 800db08: 6815 ldr r5, [r2, #0] + 800db0a: 6854 ldr r4, [r2, #4] + 800db0c: 6890 ldr r0, [r2, #8] + 800db0e: 68d1 ldr r1, [r2, #12] + 800db10: 601d str r5, [r3, #0] + 800db12: 605c str r4, [r3, #4] + 800db14: 6098 str r0, [r3, #8] + 800db16: 60d9 str r1, [r3, #12] + 800db18: 7c12 ldrb r2, [r2, #16] + 800db1a: 741a strb r2, [r3, #16] + + statusPacket.batteryType = GBT_EVInfo.batteryType; + 800db1c: 4b32 ldr r3, [pc, #200] @ (800dbe8 ) + 800db1e: 78da ldrb r2, [r3, #3] + 800db20: 4b2b ldr r3, [pc, #172] @ (800dbd0 ) + 800db22: f883 2038 strb.w r2, [r3, #56] @ 0x38 + statusPacket.batteryCapacity = GBT_EVInfo.batteryCapacity; + 800db26: 4b30 ldr r3, [pc, #192] @ (800dbe8 ) + 800db28: 889b ldrh r3, [r3, #4] + 800db2a: b29a uxth r2, r3 + 800db2c: 4b28 ldr r3, [pc, #160] @ (800dbd0 ) + 800db2e: f8a3 2039 strh.w r2, [r3, #57] @ 0x39 + statusPacket.batteryVoltage = GBT_EVInfo.batteryVoltage; + 800db32: 4b2d ldr r3, [pc, #180] @ (800dbe8 ) + 800db34: 88db ldrh r3, [r3, #6] + 800db36: b29a uxth r2, r3 + 800db38: 4b25 ldr r3, [pc, #148] @ (800dbd0 ) + 800db3a: f8a3 203b strh.w r2, [r3, #59] @ 0x3b + memcpy(statusPacket.batteryVendor, GBT_EVInfo.batteryVendor, sizeof(statusPacket.batteryVendor)); + 800db3e: 4b2a ldr r3, [pc, #168] @ (800dbe8 ) + 800db40: 689b ldr r3, [r3, #8] + 800db42: 461a mov r2, r3 + 800db44: 4b22 ldr r3, [pc, #136] @ (800dbd0 ) + 800db46: f8c3 203d str.w r2, [r3, #61] @ 0x3d + statusPacket.batterySN = GBT_EVInfo.batterySN; + 800db4a: 4b27 ldr r3, [pc, #156] @ (800dbe8 ) + 800db4c: 68db ldr r3, [r3, #12] + 800db4e: 4a20 ldr r2, [pc, #128] @ (800dbd0 ) + 800db50: f8c2 3041 str.w r3, [r2, #65] @ 0x41 + statusPacket.batteryManuD = GBT_EVInfo.batteryManuD; + 800db54: 4b24 ldr r3, [pc, #144] @ (800dbe8 ) + 800db56: 7c9a ldrb r2, [r3, #18] + 800db58: 4b1d ldr r3, [pc, #116] @ (800dbd0 ) + 800db5a: f883 2047 strb.w r2, [r3, #71] @ 0x47 + statusPacket.batteryManuM = GBT_EVInfo.batteryManuM; + 800db5e: 4b22 ldr r3, [pc, #136] @ (800dbe8 ) + 800db60: 7c5a ldrb r2, [r3, #17] + 800db62: 4b1b ldr r3, [pc, #108] @ (800dbd0 ) + 800db64: f883 2046 strb.w r2, [r3, #70] @ 0x46 + statusPacket.batteryManuY = GBT_EVInfo.batteryManuY; + 800db68: 4b1f ldr r3, [pc, #124] @ (800dbe8 ) + 800db6a: 7c1a ldrb r2, [r3, #16] + 800db6c: 4b18 ldr r3, [pc, #96] @ (800dbd0 ) + 800db6e: f883 2045 strb.w r2, [r3, #69] @ 0x45 + statusPacket.batteryCycleCount = GBT_EVInfo.batteryCycleCount; + 800db72: 4b1d ldr r3, [pc, #116] @ (800dbe8 ) + 800db74: 7cda ldrb r2, [r3, #19] + 800db76: 7d19 ldrb r1, [r3, #20] + 800db78: 0209 lsls r1, r1, #8 + 800db7a: 430a orrs r2, r1 + 800db7c: 7d5b ldrb r3, [r3, #21] + 800db7e: 041b lsls r3, r3, #16 + 800db80: 4313 orrs r3, r2 + 800db82: b29a uxth r2, r3 + 800db84: 4b12 ldr r3, [pc, #72] @ (800dbd0 ) + 800db86: f8a3 2048 strh.w r2, [r3, #72] @ 0x48 + statusPacket.ownAuto = GBT_EVInfo.ownAuto; + 800db8a: 4b17 ldr r3, [pc, #92] @ (800dbe8 ) + 800db8c: 7d9a ldrb r2, [r3, #22] + 800db8e: 4b10 ldr r3, [pc, #64] @ (800dbd0 ) + 800db90: f883 204a strb.w r2, [r3, #74] @ 0x4a + memcpy(statusPacket.EV_SW_VER, GBT_EVInfo.EV_SW_VER, sizeof(statusPacket.EV_SW_VER)); + 800db94: 4b0e ldr r3, [pc, #56] @ (800dbd0 ) + 800db96: 4a14 ldr r2, [pc, #80] @ (800dbe8 ) + 800db98: 334b adds r3, #75 @ 0x4b + 800db9a: 3229 adds r2, #41 @ 0x29 + 800db9c: 6811 ldr r1, [r2, #0] + 800db9e: 6852 ldr r2, [r2, #4] + 800dba0: 6019 str r1, [r3, #0] + 800dba2: 605a str r2, [r3, #4] + + statusPacket.testMode = 0; + 800dba4: 4b0a ldr r3, [pc, #40] @ (800dbd0 ) + 800dba6: 2200 movs r2, #0 + 800dba8: f883 2053 strb.w r2, [r3, #83] @ 0x53 + statusPacket.testVoltage = 0; + 800dbac: 4b08 ldr r3, [pc, #32] @ (800dbd0 ) + 800dbae: 2200 movs r2, #0 + 800dbb0: f883 2054 strb.w r2, [r3, #84] @ 0x54 + 800dbb4: 2200 movs r2, #0 + 800dbb6: f883 2055 strb.w r2, [r3, #85] @ 0x55 + statusPacket.testCurrent = 0; + 800dbba: 4b05 ldr r3, [pc, #20] @ (800dbd0 ) + 800dbbc: 2200 movs r2, #0 + 800dbbe: f883 2056 strb.w r2, [r3, #86] @ 0x56 + 800dbc2: 2200 movs r2, #0 + 800dbc4: f883 2057 strb.w r2, [r3, #87] @ 0x57 + // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() + // Если такой функции нет, закомментируйте следующую строку: + // statusPacket.connState = CONN_GetState(); + + +} + 800dbc8: bf00 nop + 800dbca: bdb0 pop {r4, r5, r7, pc} + 800dbcc: 200002e8 .word 0x200002e8 + 800dbd0: 20000c90 .word 0x20000c90 + 800dbd4: 20000319 .word 0x20000319 + 800dbd8: 200009fc .word 0x200009fc + 800dbdc: 20000394 .word 0x20000394 + 800dbe0: 20000388 .word 0x20000388 + 800dbe4: 200009d0 .word 0x200009d0 + 800dbe8: 20000334 .word 0x20000334 + +0800dbec : +static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc); + + +uint32_t get_Current_Time(){ + 800dbec: b580 push {r7, lr} + 800dbee: af00 add r7, sp, #0 + return RTC1_ReadTimeCounter(&hrtc); + 800dbf0: 4802 ldr r0, [pc, #8] @ (800dbfc ) + 800dbf2: f000 f8a5 bl 800dd40 + 800dbf6: 4603 mov r3, r0 +} + 800dbf8: 4618 mov r0, r3 + 800dbfa: bd80 pop {r7, pc} + 800dbfc: 20000a6c .word 0x20000a6c + +0800dc00 : + +void set_Time(uint32_t unix_time){ + 800dc00: b580 push {r7, lr} + 800dc02: b082 sub sp, #8 + 800dc04: af00 add r7, sp, #0 + 800dc06: 6078 str r0, [r7, #4] + RTC1_WriteTimeCounter(&hrtc, unix_time); + 800dc08: 6879 ldr r1, [r7, #4] + 800dc0a: 4803 ldr r0, [pc, #12] @ (800dc18 ) + 800dc0c: f000 f8c8 bl 800dda0 +} + 800dc10: bf00 nop + 800dc12: 3708 adds r7, #8 + 800dc14: 46bd mov sp, r7 + 800dc16: bd80 pop {r7, pc} + 800dc18: 20000a6c .word 0x20000a6c + +0800dc1c : + +uint8_t to_bcd(int value) { + 800dc1c: b480 push {r7} + 800dc1e: b083 sub sp, #12 + 800dc20: af00 add r7, sp, #0 + 800dc22: 6078 str r0, [r7, #4] + return ((value / 10) << 4) | (value % 10); + 800dc24: 687b ldr r3, [r7, #4] + 800dc26: 4a0f ldr r2, [pc, #60] @ (800dc64 ) + 800dc28: fb82 1203 smull r1, r2, r2, r3 + 800dc2c: 1092 asrs r2, r2, #2 + 800dc2e: 17db asrs r3, r3, #31 + 800dc30: 1ad3 subs r3, r2, r3 + 800dc32: b25b sxtb r3, r3 + 800dc34: 011b lsls r3, r3, #4 + 800dc36: b258 sxtb r0, r3 + 800dc38: 687a ldr r2, [r7, #4] + 800dc3a: 4b0a ldr r3, [pc, #40] @ (800dc64 ) + 800dc3c: fb83 1302 smull r1, r3, r3, r2 + 800dc40: 1099 asrs r1, r3, #2 + 800dc42: 17d3 asrs r3, r2, #31 + 800dc44: 1ac9 subs r1, r1, r3 + 800dc46: 460b mov r3, r1 + 800dc48: 009b lsls r3, r3, #2 + 800dc4a: 440b add r3, r1 + 800dc4c: 005b lsls r3, r3, #1 + 800dc4e: 1ad1 subs r1, r2, r3 + 800dc50: b24b sxtb r3, r1 + 800dc52: 4303 orrs r3, r0 + 800dc54: b25b sxtb r3, r3 + 800dc56: b2db uxtb r3, r3 +} + 800dc58: 4618 mov r0, r3 + 800dc5a: 370c adds r7, #12 + 800dc5c: 46bd mov sp, r7 + 800dc5e: bc80 pop {r7} + 800dc60: 4770 bx lr + 800dc62: bf00 nop + 800dc64: 66666667 .word 0x66666667 + +0800dc68 : + +void unix_to_bcd(uint32_t unix_time, uint8_t *time) { + 800dc68: b590 push {r4, r7, lr} + 800dc6a: b087 sub sp, #28 + 800dc6c: af00 add r7, sp, #0 + 800dc6e: 6078 str r0, [r7, #4] + 800dc70: 6039 str r1, [r7, #0] + struct tm *tm_info; + time_t raw_time = (time_t)unix_time; + 800dc72: 6879 ldr r1, [r7, #4] + 800dc74: 2000 movs r0, #0 + 800dc76: 460a mov r2, r1 + 800dc78: 4603 mov r3, r0 + 800dc7a: e9c7 2302 strd r2, r3, [r7, #8] + tm_info = gmtime(&raw_time); + 800dc7e: f107 0308 add.w r3, r7, #8 + 800dc82: 4618 mov r0, r3 + 800dc84: f006 fa0c bl 80140a0 + 800dc88: 6178 str r0, [r7, #20] + + time[0] = to_bcd(tm_info->tm_sec); + 800dc8a: 697b ldr r3, [r7, #20] + 800dc8c: 681b ldr r3, [r3, #0] + 800dc8e: 4618 mov r0, r3 + 800dc90: f7ff ffc4 bl 800dc1c + 800dc94: 4603 mov r3, r0 + 800dc96: 461a mov r2, r3 + 800dc98: 683b ldr r3, [r7, #0] + 800dc9a: 701a strb r2, [r3, #0] + time[1] = to_bcd(tm_info->tm_min); + 800dc9c: 697b ldr r3, [r7, #20] + 800dc9e: 685a ldr r2, [r3, #4] + 800dca0: 683b ldr r3, [r7, #0] + 800dca2: 1c5c adds r4, r3, #1 + 800dca4: 4610 mov r0, r2 + 800dca6: f7ff ffb9 bl 800dc1c + 800dcaa: 4603 mov r3, r0 + 800dcac: 7023 strb r3, [r4, #0] + time[2] = to_bcd(tm_info->tm_hour); + 800dcae: 697b ldr r3, [r7, #20] + 800dcb0: 689a ldr r2, [r3, #8] + 800dcb2: 683b ldr r3, [r7, #0] + 800dcb4: 1c9c adds r4, r3, #2 + 800dcb6: 4610 mov r0, r2 + 800dcb8: f7ff ffb0 bl 800dc1c + 800dcbc: 4603 mov r3, r0 + 800dcbe: 7023 strb r3, [r4, #0] + time[3] = to_bcd(tm_info->tm_mday); + 800dcc0: 697b ldr r3, [r7, #20] + 800dcc2: 68da ldr r2, [r3, #12] + 800dcc4: 683b ldr r3, [r7, #0] + 800dcc6: 1cdc adds r4, r3, #3 + 800dcc8: 4610 mov r0, r2 + 800dcca: f7ff ffa7 bl 800dc1c + 800dcce: 4603 mov r3, r0 + 800dcd0: 7023 strb r3, [r4, #0] + time[4] = to_bcd(tm_info->tm_mon + 1); // tm_mon is 0-11 + 800dcd2: 697b ldr r3, [r7, #20] + 800dcd4: 691b ldr r3, [r3, #16] + 800dcd6: 1c5a adds r2, r3, #1 + 800dcd8: 683b ldr r3, [r7, #0] + 800dcda: 1d1c adds r4, r3, #4 + 800dcdc: 4610 mov r0, r2 + 800dcde: f7ff ff9d bl 800dc1c + 800dce2: 4603 mov r3, r0 + 800dce4: 7023 strb r3, [r4, #0] + time[5] = to_bcd((tm_info->tm_year + 1900) % 100); // Year in 2 digits + 800dce6: 697b ldr r3, [r7, #20] + 800dce8: 695b ldr r3, [r3, #20] + 800dcea: f203 736c addw r3, r3, #1900 @ 0x76c + 800dcee: 4a13 ldr r2, [pc, #76] @ (800dd3c ) + 800dcf0: fb82 1203 smull r1, r2, r2, r3 + 800dcf4: 1151 asrs r1, r2, #5 + 800dcf6: 17da asrs r2, r3, #31 + 800dcf8: 1a8a subs r2, r1, r2 + 800dcfa: 2164 movs r1, #100 @ 0x64 + 800dcfc: fb01 f202 mul.w r2, r1, r2 + 800dd00: 1a9a subs r2, r3, r2 + 800dd02: 683b ldr r3, [r7, #0] + 800dd04: 1d5c adds r4, r3, #5 + 800dd06: 4610 mov r0, r2 + 800dd08: f7ff ff88 bl 800dc1c + 800dd0c: 4603 mov r3, r0 + 800dd0e: 7023 strb r3, [r4, #0] + time[6] = to_bcd((tm_info->tm_year + 1900) / 100); // Century in 2 digits + 800dd10: 697b ldr r3, [r7, #20] + 800dd12: 695b ldr r3, [r3, #20] + 800dd14: f203 736c addw r3, r3, #1900 @ 0x76c + 800dd18: 4a08 ldr r2, [pc, #32] @ (800dd3c ) + 800dd1a: fb82 1203 smull r1, r2, r2, r3 + 800dd1e: 1152 asrs r2, r2, #5 + 800dd20: 17db asrs r3, r3, #31 + 800dd22: 1ad2 subs r2, r2, r3 + 800dd24: 683b ldr r3, [r7, #0] + 800dd26: 1d9c adds r4, r3, #6 + 800dd28: 4610 mov r0, r2 + 800dd2a: f7ff ff77 bl 800dc1c + 800dd2e: 4603 mov r3, r0 + 800dd30: 7023 strb r3, [r4, #0] +} + 800dd32: bf00 nop + 800dd34: 371c adds r7, #28 + 800dd36: 46bd mov sp, r7 + 800dd38: bd90 pop {r4, r7, pc} + 800dd3a: bf00 nop + 800dd3c: 51eb851f .word 0x51eb851f + +0800dd40 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC1_ReadTimeCounter(RTC_HandleTypeDef *hrtc) +{ + 800dd40: b480 push {r7} + 800dd42: b087 sub sp, #28 + 800dd44: af00 add r7, sp, #0 + 800dd46: 6078 str r0, [r7, #4] + uint16_t high1 = 0U, high2 = 0U, low = 0U; + 800dd48: 2300 movs r3, #0 + 800dd4a: 827b strh r3, [r7, #18] + 800dd4c: 2300 movs r3, #0 + 800dd4e: 823b strh r3, [r7, #16] + 800dd50: 2300 movs r3, #0 + 800dd52: 81fb strh r3, [r7, #14] + uint32_t timecounter = 0U; + 800dd54: 2300 movs r3, #0 + 800dd56: 617b str r3, [r7, #20] + + high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + 800dd58: 687b ldr r3, [r7, #4] + 800dd5a: 681b ldr r3, [r3, #0] + 800dd5c: 699b ldr r3, [r3, #24] + 800dd5e: 827b strh r3, [r7, #18] + low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); + 800dd60: 687b ldr r3, [r7, #4] + 800dd62: 681b ldr r3, [r3, #0] + 800dd64: 69db ldr r3, [r3, #28] + 800dd66: 81fb strh r3, [r7, #14] + high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + 800dd68: 687b ldr r3, [r7, #4] + 800dd6a: 681b ldr r3, [r3, #0] + 800dd6c: 699b ldr r3, [r3, #24] + 800dd6e: 823b strh r3, [r7, #16] + + if (high1 != high2) + 800dd70: 8a7a ldrh r2, [r7, #18] + 800dd72: 8a3b ldrh r3, [r7, #16] + 800dd74: 429a cmp r2, r3 + 800dd76: d008 beq.n 800dd8a + { + /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); + 800dd78: 8a3b ldrh r3, [r7, #16] + 800dd7a: 041a lsls r2, r3, #16 + 800dd7c: 687b ldr r3, [r7, #4] + 800dd7e: 681b ldr r3, [r3, #0] + 800dd80: 69db ldr r3, [r3, #28] + 800dd82: b29b uxth r3, r3 + 800dd84: 4313 orrs r3, r2 + 800dd86: 617b str r3, [r7, #20] + 800dd88: e004 b.n 800dd94 + } + else + { + /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + timecounter = (((uint32_t) high1 << 16U) | low); + 800dd8a: 8a7b ldrh r3, [r7, #18] + 800dd8c: 041a lsls r2, r3, #16 + 800dd8e: 89fb ldrh r3, [r7, #14] + 800dd90: 4313 orrs r3, r2 + 800dd92: 617b str r3, [r7, #20] + } + + return timecounter; + 800dd94: 697b ldr r3, [r7, #20] +} + 800dd96: 4618 mov r0, r3 + 800dd98: 371c adds r7, #28 + 800dd9a: 46bd mov sp, r7 + 800dd9c: bc80 pop {r7} + 800dd9e: 4770 bx lr + +0800dda0 : + * the configuration information for RTC. + * @param TimeCounter: Counter to write in RTC_CNT registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC1_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) +{ + 800dda0: b580 push {r7, lr} + 800dda2: b084 sub sp, #16 + 800dda4: af00 add r7, sp, #0 + 800dda6: 6078 str r0, [r7, #4] + 800dda8: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 800ddaa: 2300 movs r3, #0 + 800ddac: 73fb strb r3, [r7, #15] + + /* Set Initialization mode */ + if (RTC1_EnterInitMode(hrtc) != HAL_OK) + 800ddae: 6878 ldr r0, [r7, #4] + 800ddb0: f000 f81d bl 800ddee + 800ddb4: 4603 mov r3, r0 + 800ddb6: 2b00 cmp r3, #0 + 800ddb8: d002 beq.n 800ddc0 + { + status = HAL_ERROR; + 800ddba: 2301 movs r3, #1 + 800ddbc: 73fb strb r3, [r7, #15] + 800ddbe: e011 b.n 800dde4 + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); + 800ddc0: 687b ldr r3, [r7, #4] + 800ddc2: 681b ldr r3, [r3, #0] + 800ddc4: 683a ldr r2, [r7, #0] + 800ddc6: 0c12 lsrs r2, r2, #16 + 800ddc8: 619a str r2, [r3, #24] + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); + 800ddca: 687b ldr r3, [r7, #4] + 800ddcc: 681b ldr r3, [r3, #0] + 800ddce: 683a ldr r2, [r7, #0] + 800ddd0: b292 uxth r2, r2 + 800ddd2: 61da str r2, [r3, #28] + + /* Wait for synchro */ + if (RTC1_ExitInitMode(hrtc) != HAL_OK) + 800ddd4: 6878 ldr r0, [r7, #4] + 800ddd6: f000 f832 bl 800de3e + 800ddda: 4603 mov r3, r0 + 800dddc: 2b00 cmp r3, #0 + 800ddde: d001 beq.n 800dde4 + { + status = HAL_ERROR; + 800dde0: 2301 movs r3, #1 + 800dde2: 73fb strb r3, [r7, #15] + } + } + + return status; + 800dde4: 7bfb ldrb r3, [r7, #15] +} + 800dde6: 4618 mov r0, r3 + 800dde8: 3710 adds r7, #16 + 800ddea: 46bd mov sp, r7 + 800ddec: bd80 pop {r7, pc} + +0800ddee : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC1_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 800ddee: b580 push {r7, lr} + 800ddf0: b084 sub sp, #16 + 800ddf2: af00 add r7, sp, #0 + 800ddf4: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800ddf6: 2300 movs r3, #0 + 800ddf8: 60fb str r3, [r7, #12] + + tickstart = HAL_GetTick(); + 800ddfa: f000 fce9 bl 800e7d0 + 800ddfe: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 800de00: e009 b.n 800de16 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 800de02: f000 fce5 bl 800e7d0 + 800de06: 4602 mov r2, r0 + 800de08: 68fb ldr r3, [r7, #12] + 800de0a: 1ad3 subs r3, r2, r3 + 800de0c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800de10: d901 bls.n 800de16 + { + return HAL_TIMEOUT; + 800de12: 2303 movs r3, #3 + 800de14: e00f b.n 800de36 + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 800de16: 687b ldr r3, [r7, #4] + 800de18: 681b ldr r3, [r3, #0] + 800de1a: 685b ldr r3, [r3, #4] + 800de1c: f003 0320 and.w r3, r3, #32 + 800de20: 2b00 cmp r3, #0 + 800de22: d0ee beq.n 800de02 + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 800de24: 687b ldr r3, [r7, #4] + 800de26: 681b ldr r3, [r3, #0] + 800de28: 685a ldr r2, [r3, #4] + 800de2a: 687b ldr r3, [r7, #4] + 800de2c: 681b ldr r3, [r3, #0] + 800de2e: f042 0210 orr.w r2, r2, #16 + 800de32: 605a str r2, [r3, #4] + + + return HAL_OK; + 800de34: 2300 movs r3, #0 +} + 800de36: 4618 mov r0, r3 + 800de38: 3710 adds r7, #16 + 800de3a: 46bd mov sp, r7 + 800de3c: bd80 pop {r7, pc} + +0800de3e : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC1_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 800de3e: b580 push {r7, lr} + 800de40: b084 sub sp, #16 + 800de42: af00 add r7, sp, #0 + 800de44: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800de46: 2300 movs r3, #0 + 800de48: 60fb str r3, [r7, #12] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800de4a: 687b ldr r3, [r7, #4] + 800de4c: 681b ldr r3, [r3, #0] + 800de4e: 685a ldr r2, [r3, #4] + 800de50: 687b ldr r3, [r7, #4] + 800de52: 681b ldr r3, [r3, #0] + 800de54: f022 0210 bic.w r2, r2, #16 + 800de58: 605a str r2, [r3, #4] + + tickstart = HAL_GetTick(); + 800de5a: f000 fcb9 bl 800e7d0 + 800de5e: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 800de60: e009 b.n 800de76 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 800de62: f000 fcb5 bl 800e7d0 + 800de66: 4602 mov r2, r0 + 800de68: 68fb ldr r3, [r7, #12] + 800de6a: 1ad3 subs r3, r2, r3 + 800de6c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 800de70: d901 bls.n 800de76 + { + return HAL_TIMEOUT; + 800de72: 2303 movs r3, #3 + 800de74: e007 b.n 800de86 + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 800de76: 687b ldr r3, [r7, #4] + 800de78: 681b ldr r3, [r3, #0] + 800de7a: 685b ldr r3, [r3, #4] + 800de7c: f003 0320 and.w r3, r3, #32 + 800de80: 2b00 cmp r3, #0 + 800de82: d0ee beq.n 800de62 + } + } + + return HAL_OK; + 800de84: 2300 movs r3, #0 +} + 800de86: 4618 mov r0, r3 + 800de88: 3710 adds r7, #16 + 800de8a: 46bd mov sp, r7 + 800de8c: bd80 pop {r7, pc} + ... + +0800de90 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 800de90: b480 push {r7} + 800de92: b085 sub sp, #20 + 800de94: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_AFIO_CLK_ENABLE(); + 800de96: 4b15 ldr r3, [pc, #84] @ (800deec ) + 800de98: 699b ldr r3, [r3, #24] + 800de9a: 4a14 ldr r2, [pc, #80] @ (800deec ) + 800de9c: f043 0301 orr.w r3, r3, #1 + 800dea0: 6193 str r3, [r2, #24] + 800dea2: 4b12 ldr r3, [pc, #72] @ (800deec ) + 800dea4: 699b ldr r3, [r3, #24] + 800dea6: f003 0301 and.w r3, r3, #1 + 800deaa: 60bb str r3, [r7, #8] + 800deac: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800deae: 4b0f ldr r3, [pc, #60] @ (800deec ) + 800deb0: 69db ldr r3, [r3, #28] + 800deb2: 4a0e ldr r2, [pc, #56] @ (800deec ) + 800deb4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800deb8: 61d3 str r3, [r2, #28] + 800deba: 4b0c ldr r3, [pc, #48] @ (800deec ) + 800debc: 69db ldr r3, [r3, #28] + 800debe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800dec2: 607b str r3, [r7, #4] + 800dec4: 687b ldr r3, [r7, #4] + + /* System interrupt init*/ + + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + */ + __HAL_AFIO_REMAP_SWJ_NOJTAG(); + 800dec6: 4b0a ldr r3, [pc, #40] @ (800def0 ) + 800dec8: 685b ldr r3, [r3, #4] + 800deca: 60fb str r3, [r7, #12] + 800decc: 68fb ldr r3, [r7, #12] + 800dece: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 + 800ded2: 60fb str r3, [r7, #12] + 800ded4: 68fb ldr r3, [r7, #12] + 800ded6: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 800deda: 60fb str r3, [r7, #12] + 800dedc: 4a04 ldr r2, [pc, #16] @ (800def0 ) + 800dede: 68fb ldr r3, [r7, #12] + 800dee0: 6053 str r3, [r2, #4] + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 800dee2: bf00 nop + 800dee4: 3714 adds r7, #20 + 800dee6: 46bd mov sp, r7 + 800dee8: bc80 pop {r7} + 800deea: 4770 bx lr + 800deec: 40021000 .word 0x40021000 + 800def0: 40010000 .word 0x40010000 + +0800def4 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 800def4: b480 push {r7} + 800def6: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 800def8: bf00 nop + 800defa: e7fd b.n 800def8 + +0800defc : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800defc: b480 push {r7} + 800defe: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 800df00: bf00 nop + 800df02: e7fd b.n 800df00 + +0800df04 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 800df04: b480 push {r7} + 800df06: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 800df08: bf00 nop + 800df0a: e7fd b.n 800df08 + +0800df0c : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800df0c: b480 push {r7} + 800df0e: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800df10: bf00 nop + 800df12: e7fd b.n 800df10 + +0800df14 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 800df14: b480 push {r7} + 800df16: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 800df18: bf00 nop + 800df1a: e7fd b.n 800df18 + +0800df1c : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 800df1c: b480 push {r7} + 800df1e: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 800df20: bf00 nop + 800df22: 46bd mov sp, r7 + 800df24: bc80 pop {r7} + 800df26: 4770 bx lr + +0800df28 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 800df28: b480 push {r7} + 800df2a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800df2c: bf00 nop + 800df2e: 46bd mov sp, r7 + 800df30: bc80 pop {r7} + 800df32: 4770 bx lr + +0800df34 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 800df34: b480 push {r7} + 800df36: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 800df38: bf00 nop + 800df3a: 46bd mov sp, r7 + 800df3c: bc80 pop {r7} + 800df3e: 4770 bx lr + +0800df40 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800df40: b580 push {r7, lr} + 800df42: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800df44: f000 fc32 bl 800e7ac + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 800df48: bf00 nop + 800df4a: bd80 pop {r7, pc} + +0800df4c : + +/** + * @brief This function handles CAN1 RX0 interrupt. + */ +void CAN1_RX0_IRQHandler(void) +{ + 800df4c: b580 push {r7, lr} + 800df4e: af00 add r7, sp, #0 + /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ + + /* USER CODE END CAN1_RX0_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + 800df50: 4802 ldr r0, [pc, #8] @ (800df5c ) + 800df52: f001 fe23 bl 800fb9c + /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ + + /* USER CODE END CAN1_RX0_IRQn 1 */ +} + 800df56: bf00 nop + 800df58: bd80 pop {r7, pc} + 800df5a: bf00 nop + 800df5c: 20000294 .word 0x20000294 + +0800df60 : + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + 800df60: b580 push {r7, lr} + 800df62: af00 add r7, sp, #0 + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + 800df64: 4802 ldr r0, [pc, #8] @ (800df70 ) + 800df66: f004 fdb9 bl 8012adc + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + 800df6a: bf00 nop + 800df6c: bd80 pop {r7, pc} + 800df6e: bf00 nop + 800df70: 20000d88 .word 0x20000d88 + +0800df74 : + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + 800df74: b580 push {r7, lr} + 800df76: af00 add r7, sp, #0 + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + 800df78: 4802 ldr r0, [pc, #8] @ (800df84 ) + 800df7a: f004 fdaf bl 8012adc + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + 800df7e: bf00 nop + 800df80: bd80 pop {r7, pc} + 800df82: bf00 nop + 800df84: 20000dd0 .word 0x20000dd0 + +0800df88 : + +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + 800df88: b580 push {r7, lr} + 800df8a: af00 add r7, sp, #0 + /* USER CODE BEGIN USART3_IRQn 0 */ + + /* USER CODE END USART3_IRQn 0 */ + HAL_UART_IRQHandler(&huart3); + 800df8c: 4802 ldr r0, [pc, #8] @ (800df98 ) + 800df8e: f004 fda5 bl 8012adc + /* USER CODE BEGIN USART3_IRQn 1 */ + + /* USER CODE END USART3_IRQn 1 */ +} + 800df92: bf00 nop + 800df94: bd80 pop {r7, pc} + 800df96: bf00 nop + 800df98: 20000e18 .word 0x20000e18 + +0800df9c : + +/** + * @brief This function handles CAN2 TX interrupt. + */ +void CAN2_TX_IRQHandler(void) +{ + 800df9c: b580 push {r7, lr} + 800df9e: af00 add r7, sp, #0 + /* USER CODE BEGIN CAN2_TX_IRQn 0 */ + + /* USER CODE END CAN2_TX_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + 800dfa0: 4802 ldr r0, [pc, #8] @ (800dfac ) + 800dfa2: f001 fdfb bl 800fb9c + /* USER CODE BEGIN CAN2_TX_IRQn 1 */ + + /* USER CODE END CAN2_TX_IRQn 1 */ +} + 800dfa6: bf00 nop + 800dfa8: bd80 pop {r7, pc} + 800dfaa: bf00 nop + 800dfac: 200002bc .word 0x200002bc + +0800dfb0 : + +/** + * @brief This function handles CAN2 RX1 interrupt. + */ +void CAN2_RX1_IRQHandler(void) +{ + 800dfb0: b580 push {r7, lr} + 800dfb2: af00 add r7, sp, #0 + /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ + + /* USER CODE END CAN2_RX1_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + 800dfb4: 4802 ldr r0, [pc, #8] @ (800dfc0 ) + 800dfb6: f001 fdf1 bl 800fb9c + /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ + + /* USER CODE END CAN2_RX1_IRQn 1 */ +} + 800dfba: bf00 nop + 800dfbc: bd80 pop {r7, pc} + 800dfbe: bf00 nop + 800dfc0: 200002bc .word 0x200002bc + +0800dfc4 <_getpid>: +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + 800dfc4: b480 push {r7} + 800dfc6: af00 add r7, sp, #0 + return 1; + 800dfc8: 2301 movs r3, #1 +} + 800dfca: 4618 mov r0, r3 + 800dfcc: 46bd mov sp, r7 + 800dfce: bc80 pop {r7} + 800dfd0: 4770 bx lr + +0800dfd2 <_kill>: + +int _kill(int pid, int sig) +{ + 800dfd2: b580 push {r7, lr} + 800dfd4: b082 sub sp, #8 + 800dfd6: af00 add r7, sp, #0 + 800dfd8: 6078 str r0, [r7, #4] + 800dfda: 6039 str r1, [r7, #0] + (void)pid; + (void)sig; + errno = EINVAL; + 800dfdc: f006 f926 bl 801422c <__errno> + 800dfe0: 4603 mov r3, r0 + 800dfe2: 2216 movs r2, #22 + 800dfe4: 601a str r2, [r3, #0] + return -1; + 800dfe6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +} + 800dfea: 4618 mov r0, r3 + 800dfec: 3708 adds r7, #8 + 800dfee: 46bd mov sp, r7 + 800dff0: bd80 pop {r7, pc} + +0800dff2 <_exit>: + +void _exit (int status) +{ + 800dff2: b580 push {r7, lr} + 800dff4: b082 sub sp, #8 + 800dff6: af00 add r7, sp, #0 + 800dff8: 6078 str r0, [r7, #4] + _kill(status, -1); + 800dffa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 800dffe: 6878 ldr r0, [r7, #4] + 800e000: f7ff ffe7 bl 800dfd2 <_kill> + while (1) {} /* Make sure we hang here */ + 800e004: bf00 nop + 800e006: e7fd b.n 800e004 <_exit+0x12> + +0800e008 <_read>: +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 800e008: b580 push {r7, lr} + 800e00a: b086 sub sp, #24 + 800e00c: af00 add r7, sp, #0 + 800e00e: 60f8 str r0, [r7, #12] + 800e010: 60b9 str r1, [r7, #8] + 800e012: 607a str r2, [r7, #4] + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 800e014: 2300 movs r3, #0 + 800e016: 617b str r3, [r7, #20] + 800e018: e00a b.n 800e030 <_read+0x28> + { + *ptr++ = __io_getchar(); + 800e01a: f3af 8000 nop.w + 800e01e: 4601 mov r1, r0 + 800e020: 68bb ldr r3, [r7, #8] + 800e022: 1c5a adds r2, r3, #1 + 800e024: 60ba str r2, [r7, #8] + 800e026: b2ca uxtb r2, r1 + 800e028: 701a strb r2, [r3, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 800e02a: 697b ldr r3, [r7, #20] + 800e02c: 3301 adds r3, #1 + 800e02e: 617b str r3, [r7, #20] + 800e030: 697a ldr r2, [r7, #20] + 800e032: 687b ldr r3, [r7, #4] + 800e034: 429a cmp r2, r3 + 800e036: dbf0 blt.n 800e01a <_read+0x12> + } + + return len; + 800e038: 687b ldr r3, [r7, #4] +} + 800e03a: 4618 mov r0, r3 + 800e03c: 3718 adds r7, #24 + 800e03e: 46bd mov sp, r7 + 800e040: bd80 pop {r7, pc} + +0800e042 <_close>: + } + return len; +} + +int _close(int file) +{ + 800e042: b480 push {r7} + 800e044: b083 sub sp, #12 + 800e046: af00 add r7, sp, #0 + 800e048: 6078 str r0, [r7, #4] + (void)file; + return -1; + 800e04a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +} + 800e04e: 4618 mov r0, r3 + 800e050: 370c adds r7, #12 + 800e052: 46bd mov sp, r7 + 800e054: bc80 pop {r7} + 800e056: 4770 bx lr + +0800e058 <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 800e058: b480 push {r7} + 800e05a: b083 sub sp, #12 + 800e05c: af00 add r7, sp, #0 + 800e05e: 6078 str r0, [r7, #4] + 800e060: 6039 str r1, [r7, #0] + (void)file; + st->st_mode = S_IFCHR; + 800e062: 683b ldr r3, [r7, #0] + 800e064: f44f 5200 mov.w r2, #8192 @ 0x2000 + 800e068: 605a str r2, [r3, #4] + return 0; + 800e06a: 2300 movs r3, #0 +} + 800e06c: 4618 mov r0, r3 + 800e06e: 370c adds r7, #12 + 800e070: 46bd mov sp, r7 + 800e072: bc80 pop {r7} + 800e074: 4770 bx lr + +0800e076 <_isatty>: + +int _isatty(int file) +{ + 800e076: b480 push {r7} + 800e078: b083 sub sp, #12 + 800e07a: af00 add r7, sp, #0 + 800e07c: 6078 str r0, [r7, #4] + (void)file; + return 1; + 800e07e: 2301 movs r3, #1 +} + 800e080: 4618 mov r0, r3 + 800e082: 370c adds r7, #12 + 800e084: 46bd mov sp, r7 + 800e086: bc80 pop {r7} + 800e088: 4770 bx lr + +0800e08a <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 800e08a: b480 push {r7} + 800e08c: b085 sub sp, #20 + 800e08e: af00 add r7, sp, #0 + 800e090: 60f8 str r0, [r7, #12] + 800e092: 60b9 str r1, [r7, #8] + 800e094: 607a str r2, [r7, #4] + (void)file; + (void)ptr; + (void)dir; + return 0; + 800e096: 2300 movs r3, #0 +} + 800e098: 4618 mov r0, r3 + 800e09a: 3714 adds r7, #20 + 800e09c: 46bd mov sp, r7 + 800e09e: bc80 pop {r7} + 800e0a0: 4770 bx lr + ... + +0800e0a4 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 800e0a4: b580 push {r7, lr} + 800e0a6: b086 sub sp, #24 + 800e0a8: af00 add r7, sp, #0 + 800e0aa: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 800e0ac: 4a14 ldr r2, [pc, #80] @ (800e100 <_sbrk+0x5c>) + 800e0ae: 4b15 ldr r3, [pc, #84] @ (800e104 <_sbrk+0x60>) + 800e0b0: 1ad3 subs r3, r2, r3 + 800e0b2: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 800e0b4: 697b ldr r3, [r7, #20] + 800e0b6: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 800e0b8: 4b13 ldr r3, [pc, #76] @ (800e108 <_sbrk+0x64>) + 800e0ba: 681b ldr r3, [r3, #0] + 800e0bc: 2b00 cmp r3, #0 + 800e0be: d102 bne.n 800e0c6 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 800e0c0: 4b11 ldr r3, [pc, #68] @ (800e108 <_sbrk+0x64>) + 800e0c2: 4a12 ldr r2, [pc, #72] @ (800e10c <_sbrk+0x68>) + 800e0c4: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 800e0c6: 4b10 ldr r3, [pc, #64] @ (800e108 <_sbrk+0x64>) + 800e0c8: 681a ldr r2, [r3, #0] + 800e0ca: 687b ldr r3, [r7, #4] + 800e0cc: 4413 add r3, r2 + 800e0ce: 693a ldr r2, [r7, #16] + 800e0d0: 429a cmp r2, r3 + 800e0d2: d207 bcs.n 800e0e4 <_sbrk+0x40> + { + errno = ENOMEM; + 800e0d4: f006 f8aa bl 801422c <__errno> + 800e0d8: 4603 mov r3, r0 + 800e0da: 220c movs r2, #12 + 800e0dc: 601a str r2, [r3, #0] + return (void *)-1; + 800e0de: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff + 800e0e2: e009 b.n 800e0f8 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 800e0e4: 4b08 ldr r3, [pc, #32] @ (800e108 <_sbrk+0x64>) + 800e0e6: 681b ldr r3, [r3, #0] + 800e0e8: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 800e0ea: 4b07 ldr r3, [pc, #28] @ (800e108 <_sbrk+0x64>) + 800e0ec: 681a ldr r2, [r3, #0] + 800e0ee: 687b ldr r3, [r7, #4] + 800e0f0: 4413 add r3, r2 + 800e0f2: 4a05 ldr r2, [pc, #20] @ (800e108 <_sbrk+0x64>) + 800e0f4: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 800e0f6: 68fb ldr r3, [r7, #12] +} + 800e0f8: 4618 mov r0, r3 + 800e0fa: 3718 adds r7, #24 + 800e0fc: 46bd mov sp, r7 + 800e0fe: bd80 pop {r7, pc} + 800e100: 20010000 .word 0x20010000 + 800e104: 00000400 .word 0x00000400 + 800e108: 20000cf4 .word 0x20000cf4 + 800e10c: 20000fb0 .word 0x20000fb0 + +0800e110 : + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 800e110: b480 push {r7} + 800e112: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 800e114: bf00 nop + 800e116: 46bd mov sp, r7 + 800e118: bc80 pop {r7} + 800e11a: 4770 bx lr + +0800e11c : + +TIM_HandleTypeDef htim4; + +/* TIM4 init function */ +void MX_TIM4_Init(void) +{ + 800e11c: b580 push {r7, lr} + 800e11e: b08e sub sp, #56 @ 0x38 + 800e120: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800e122: f107 0328 add.w r3, r7, #40 @ 0x28 + 800e126: 2200 movs r2, #0 + 800e128: 601a str r2, [r3, #0] + 800e12a: 605a str r2, [r3, #4] + 800e12c: 609a str r2, [r3, #8] + 800e12e: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 800e130: f107 0320 add.w r3, r7, #32 + 800e134: 2200 movs r2, #0 + 800e136: 601a str r2, [r3, #0] + 800e138: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 800e13a: 1d3b adds r3, r7, #4 + 800e13c: 2200 movs r2, #0 + 800e13e: 601a str r2, [r3, #0] + 800e140: 605a str r2, [r3, #4] + 800e142: 609a str r2, [r3, #8] + 800e144: 60da str r2, [r3, #12] + 800e146: 611a str r2, [r3, #16] + 800e148: 615a str r2, [r3, #20] + 800e14a: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + 800e14c: 4b37 ldr r3, [pc, #220] @ (800e22c ) + 800e14e: 4a38 ldr r2, [pc, #224] @ (800e230 ) + 800e150: 601a str r2, [r3, #0] + htim4.Init.Prescaler = 720; + 800e152: 4b36 ldr r3, [pc, #216] @ (800e22c ) + 800e154: f44f 7234 mov.w r2, #720 @ 0x2d0 + 800e158: 605a str r2, [r3, #4] + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 800e15a: 4b34 ldr r3, [pc, #208] @ (800e22c ) + 800e15c: 2200 movs r2, #0 + 800e15e: 609a str r2, [r3, #8] + htim4.Init.Period = 100; + 800e160: 4b32 ldr r3, [pc, #200] @ (800e22c ) + 800e162: 2264 movs r2, #100 @ 0x64 + 800e164: 60da str r2, [r3, #12] + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 800e166: 4b31 ldr r3, [pc, #196] @ (800e22c ) + 800e168: 2200 movs r2, #0 + 800e16a: 611a str r2, [r3, #16] + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800e16c: 4b2f ldr r3, [pc, #188] @ (800e22c ) + 800e16e: 2200 movs r2, #0 + 800e170: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + 800e172: 482e ldr r0, [pc, #184] @ (800e22c ) + 800e174: f003 fcc1 bl 8011afa + 800e178: 4603 mov r3, r0 + 800e17a: 2b00 cmp r3, #0 + 800e17c: d001 beq.n 800e182 + { + Error_Handler(); + 800e17e: f7fe f8b3 bl 800c2e8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800e182: f44f 5380 mov.w r3, #4096 @ 0x1000 + 800e186: 62bb str r3, [r7, #40] @ 0x28 + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + 800e188: f107 0328 add.w r3, r7, #40 @ 0x28 + 800e18c: 4619 mov r1, r3 + 800e18e: 4827 ldr r0, [pc, #156] @ (800e22c ) + 800e190: f003 fec6 bl 8011f20 + 800e194: 4603 mov r3, r0 + 800e196: 2b00 cmp r3, #0 + 800e198: d001 beq.n 800e19e + { + Error_Handler(); + 800e19a: f7fe f8a5 bl 800c2e8 + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + 800e19e: 4823 ldr r0, [pc, #140] @ (800e22c ) + 800e1a0: f003 fcfa bl 8011b98 + 800e1a4: 4603 mov r3, r0 + 800e1a6: 2b00 cmp r3, #0 + 800e1a8: d001 beq.n 800e1ae + { + Error_Handler(); + 800e1aa: f7fe f89d bl 800c2e8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800e1ae: 2300 movs r3, #0 + 800e1b0: 623b str r3, [r7, #32] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800e1b2: 2300 movs r3, #0 + 800e1b4: 627b str r3, [r7, #36] @ 0x24 + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 800e1b6: f107 0320 add.w r3, r7, #32 + 800e1ba: 4619 mov r1, r3 + 800e1bc: 481b ldr r0, [pc, #108] @ (800e22c ) + 800e1be: f004 fa31 bl 8012624 + 800e1c2: 4603 mov r3, r0 + 800e1c4: 2b00 cmp r3, #0 + 800e1c6: d001 beq.n 800e1cc + { + Error_Handler(); + 800e1c8: f7fe f88e bl 800c2e8 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 800e1cc: 2360 movs r3, #96 @ 0x60 + 800e1ce: 607b str r3, [r7, #4] + sConfigOC.Pulse = 0; + 800e1d0: 2300 movs r3, #0 + 800e1d2: 60bb str r3, [r7, #8] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 800e1d4: 2300 movs r3, #0 + 800e1d6: 60fb str r3, [r7, #12] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 800e1d8: 2300 movs r3, #0 + 800e1da: 617b str r3, [r7, #20] + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 800e1dc: 1d3b adds r3, r7, #4 + 800e1de: 2204 movs r2, #4 + 800e1e0: 4619 mov r1, r3 + 800e1e2: 4812 ldr r0, [pc, #72] @ (800e22c ) + 800e1e4: f003 fdda bl 8011d9c + 800e1e8: 4603 mov r3, r0 + 800e1ea: 2b00 cmp r3, #0 + 800e1ec: d001 beq.n 800e1f2 + { + Error_Handler(); + 800e1ee: f7fe f87b bl 800c2e8 + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 800e1f2: 1d3b adds r3, r7, #4 + 800e1f4: 2208 movs r2, #8 + 800e1f6: 4619 mov r1, r3 + 800e1f8: 480c ldr r0, [pc, #48] @ (800e22c ) + 800e1fa: f003 fdcf bl 8011d9c + 800e1fe: 4603 mov r3, r0 + 800e200: 2b00 cmp r3, #0 + 800e202: d001 beq.n 800e208 + { + Error_Handler(); + 800e204: f7fe f870 bl 800c2e8 + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 800e208: 1d3b adds r3, r7, #4 + 800e20a: 220c movs r2, #12 + 800e20c: 4619 mov r1, r3 + 800e20e: 4807 ldr r0, [pc, #28] @ (800e22c ) + 800e210: f003 fdc4 bl 8011d9c + 800e214: 4603 mov r3, r0 + 800e216: 2b00 cmp r3, #0 + 800e218: d001 beq.n 800e21e + { + Error_Handler(); + 800e21a: f7fe f865 bl 800c2e8 + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + 800e21e: 4803 ldr r0, [pc, #12] @ (800e22c ) + 800e220: f000 f826 bl 800e270 + +} + 800e224: bf00 nop + 800e226: 3738 adds r7, #56 @ 0x38 + 800e228: 46bd mov sp, r7 + 800e22a: bd80 pop {r7, pc} + 800e22c: 20000cf8 .word 0x20000cf8 + 800e230: 40000800 .word 0x40000800 + +0800e234 : + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + 800e234: b480 push {r7} + 800e236: b085 sub sp, #20 + 800e238: af00 add r7, sp, #0 + 800e23a: 6078 str r0, [r7, #4] + + if(tim_baseHandle->Instance==TIM4) + 800e23c: 687b ldr r3, [r7, #4] + 800e23e: 681b ldr r3, [r3, #0] + 800e240: 4a09 ldr r2, [pc, #36] @ (800e268 ) + 800e242: 4293 cmp r3, r2 + 800e244: d10b bne.n 800e25e + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* TIM4 clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + 800e246: 4b09 ldr r3, [pc, #36] @ (800e26c ) + 800e248: 69db ldr r3, [r3, #28] + 800e24a: 4a08 ldr r2, [pc, #32] @ (800e26c ) + 800e24c: f043 0304 orr.w r3, r3, #4 + 800e250: 61d3 str r3, [r2, #28] + 800e252: 4b06 ldr r3, [pc, #24] @ (800e26c ) + 800e254: 69db ldr r3, [r3, #28] + 800e256: f003 0304 and.w r3, r3, #4 + 800e25a: 60fb str r3, [r7, #12] + 800e25c: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } +} + 800e25e: bf00 nop + 800e260: 3714 adds r7, #20 + 800e262: 46bd mov sp, r7 + 800e264: bc80 pop {r7} + 800e266: 4770 bx lr + 800e268: 40000800 .word 0x40000800 + 800e26c: 40021000 .word 0x40021000 + +0800e270 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + 800e270: b580 push {r7, lr} + 800e272: b088 sub sp, #32 + 800e274: af00 add r7, sp, #0 + 800e276: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800e278: f107 030c add.w r3, r7, #12 + 800e27c: 2200 movs r2, #0 + 800e27e: 601a str r2, [r3, #0] + 800e280: 605a str r2, [r3, #4] + 800e282: 609a str r2, [r3, #8] + 800e284: 60da str r2, [r3, #12] + if(timHandle->Instance==TIM4) + 800e286: 687b ldr r3, [r7, #4] + 800e288: 681b ldr r3, [r3, #0] + 800e28a: 4a17 ldr r2, [pc, #92] @ (800e2e8 ) + 800e28c: 4293 cmp r3, r2 + 800e28e: d126 bne.n 800e2de + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800e290: 4b16 ldr r3, [pc, #88] @ (800e2ec ) + 800e292: 699b ldr r3, [r3, #24] + 800e294: 4a15 ldr r2, [pc, #84] @ (800e2ec ) + 800e296: f043 0320 orr.w r3, r3, #32 + 800e29a: 6193 str r3, [r2, #24] + 800e29c: 4b13 ldr r3, [pc, #76] @ (800e2ec ) + 800e29e: 699b ldr r3, [r3, #24] + 800e2a0: f003 0320 and.w r3, r3, #32 + 800e2a4: 60bb str r3, [r7, #8] + 800e2a6: 68bb ldr r3, [r7, #8] + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + 800e2a8: f44f 4360 mov.w r3, #57344 @ 0xe000 + 800e2ac: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800e2ae: 2302 movs r3, #2 + 800e2b0: 613b str r3, [r7, #16] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800e2b2: 2302 movs r3, #2 + 800e2b4: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800e2b6: f107 030c add.w r3, r7, #12 + 800e2ba: 4619 mov r1, r3 + 800e2bc: 480c ldr r0, [pc, #48] @ (800e2f0 ) + 800e2be: f002 f8f3 bl 80104a8 + + __HAL_AFIO_REMAP_TIM4_ENABLE(); + 800e2c2: 4b0c ldr r3, [pc, #48] @ (800e2f4 ) + 800e2c4: 685b ldr r3, [r3, #4] + 800e2c6: 61fb str r3, [r7, #28] + 800e2c8: 69fb ldr r3, [r7, #28] + 800e2ca: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 800e2ce: 61fb str r3, [r7, #28] + 800e2d0: 69fb ldr r3, [r7, #28] + 800e2d2: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800e2d6: 61fb str r3, [r7, #28] + 800e2d8: 4a06 ldr r2, [pc, #24] @ (800e2f4 ) + 800e2da: 69fb ldr r3, [r7, #28] + 800e2dc: 6053 str r3, [r2, #4] + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} + 800e2de: bf00 nop + 800e2e0: 3720 adds r7, #32 + 800e2e2: 46bd mov sp, r7 + 800e2e4: bd80 pop {r7, pc} + 800e2e6: bf00 nop + 800e2e8: 40000800 .word 0x40000800 + 800e2ec: 40021000 .word 0x40021000 + 800e2f0: 40011400 .word 0x40011400 + 800e2f4: 40010000 .word 0x40010000 + +0800e2f8 : +UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; + +/* UART5 init function */ +void MX_UART5_Init(void) +{ + 800e2f8: b580 push {r7, lr} + 800e2fa: af00 add r7, sp, #0 + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + 800e2fc: 4b11 ldr r3, [pc, #68] @ (800e344 ) + 800e2fe: 4a12 ldr r2, [pc, #72] @ (800e348 ) + 800e300: 601a str r2, [r3, #0] + huart5.Init.BaudRate = 115200; + 800e302: 4b10 ldr r3, [pc, #64] @ (800e344 ) + 800e304: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 800e308: 605a str r2, [r3, #4] + huart5.Init.WordLength = UART_WORDLENGTH_8B; + 800e30a: 4b0e ldr r3, [pc, #56] @ (800e344 ) + 800e30c: 2200 movs r2, #0 + 800e30e: 609a str r2, [r3, #8] + huart5.Init.StopBits = UART_STOPBITS_1; + 800e310: 4b0c ldr r3, [pc, #48] @ (800e344 ) + 800e312: 2200 movs r2, #0 + 800e314: 60da str r2, [r3, #12] + huart5.Init.Parity = UART_PARITY_NONE; + 800e316: 4b0b ldr r3, [pc, #44] @ (800e344 ) + 800e318: 2200 movs r2, #0 + 800e31a: 611a str r2, [r3, #16] + huart5.Init.Mode = UART_MODE_TX_RX; + 800e31c: 4b09 ldr r3, [pc, #36] @ (800e344 ) + 800e31e: 220c movs r2, #12 + 800e320: 615a str r2, [r3, #20] + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800e322: 4b08 ldr r3, [pc, #32] @ (800e344 ) + 800e324: 2200 movs r2, #0 + 800e326: 619a str r2, [r3, #24] + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + 800e328: 4b06 ldr r3, [pc, #24] @ (800e344 ) + 800e32a: 2200 movs r2, #0 + 800e32c: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart5) != HAL_OK) + 800e32e: 4805 ldr r0, [pc, #20] @ (800e344 ) + 800e330: f004 f9de bl 80126f0 + 800e334: 4603 mov r3, r0 + 800e336: 2b00 cmp r3, #0 + 800e338: d001 beq.n 800e33e + { + Error_Handler(); + 800e33a: f7fd ffd5 bl 800c2e8 + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} + 800e33e: bf00 nop + 800e340: bd80 pop {r7, pc} + 800e342: bf00 nop + 800e344: 20000d40 .word 0x20000d40 + 800e348: 40005000 .word 0x40005000 + +0800e34c : +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + 800e34c: b580 push {r7, lr} + 800e34e: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 800e350: 4b11 ldr r3, [pc, #68] @ (800e398 ) + 800e352: 4a12 ldr r2, [pc, #72] @ (800e39c ) + 800e354: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 800e356: 4b10 ldr r3, [pc, #64] @ (800e398 ) + 800e358: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 800e35c: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 800e35e: 4b0e ldr r3, [pc, #56] @ (800e398 ) + 800e360: 2200 movs r2, #0 + 800e362: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 800e364: 4b0c ldr r3, [pc, #48] @ (800e398 ) + 800e366: 2200 movs r2, #0 + 800e368: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 800e36a: 4b0b ldr r3, [pc, #44] @ (800e398 ) + 800e36c: 2200 movs r2, #0 + 800e36e: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 800e370: 4b09 ldr r3, [pc, #36] @ (800e398 ) + 800e372: 220c movs r2, #12 + 800e374: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800e376: 4b08 ldr r3, [pc, #32] @ (800e398 ) + 800e378: 2200 movs r2, #0 + 800e37a: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 800e37c: 4b06 ldr r3, [pc, #24] @ (800e398 ) + 800e37e: 2200 movs r2, #0 + 800e380: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart1) != HAL_OK) + 800e382: 4805 ldr r0, [pc, #20] @ (800e398 ) + 800e384: f004 f9b4 bl 80126f0 + 800e388: 4603 mov r3, r0 + 800e38a: 2b00 cmp r3, #0 + 800e38c: d001 beq.n 800e392 + { + Error_Handler(); + 800e38e: f7fd ffab bl 800c2e8 + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 800e392: bf00 nop + 800e394: bd80 pop {r7, pc} + 800e396: bf00 nop + 800e398: 20000d88 .word 0x20000d88 + 800e39c: 40013800 .word 0x40013800 + +0800e3a0 : +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + 800e3a0: b580 push {r7, lr} + 800e3a2: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 800e3a4: 4b11 ldr r3, [pc, #68] @ (800e3ec ) + 800e3a6: 4a12 ldr r2, [pc, #72] @ (800e3f0 ) + 800e3a8: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 800e3aa: 4b10 ldr r3, [pc, #64] @ (800e3ec ) + 800e3ac: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 800e3b0: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 800e3b2: 4b0e ldr r3, [pc, #56] @ (800e3ec ) + 800e3b4: 2200 movs r2, #0 + 800e3b6: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 800e3b8: 4b0c ldr r3, [pc, #48] @ (800e3ec ) + 800e3ba: 2200 movs r2, #0 + 800e3bc: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 800e3be: 4b0b ldr r3, [pc, #44] @ (800e3ec ) + 800e3c0: 2200 movs r2, #0 + 800e3c2: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 800e3c4: 4b09 ldr r3, [pc, #36] @ (800e3ec ) + 800e3c6: 220c movs r2, #12 + 800e3c8: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800e3ca: 4b08 ldr r3, [pc, #32] @ (800e3ec ) + 800e3cc: 2200 movs r2, #0 + 800e3ce: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 800e3d0: 4b06 ldr r3, [pc, #24] @ (800e3ec ) + 800e3d2: 2200 movs r2, #0 + 800e3d4: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart2) != HAL_OK) + 800e3d6: 4805 ldr r0, [pc, #20] @ (800e3ec ) + 800e3d8: f004 f98a bl 80126f0 + 800e3dc: 4603 mov r3, r0 + 800e3de: 2b00 cmp r3, #0 + 800e3e0: d001 beq.n 800e3e6 + { + Error_Handler(); + 800e3e2: f7fd ff81 bl 800c2e8 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 800e3e6: bf00 nop + 800e3e8: bd80 pop {r7, pc} + 800e3ea: bf00 nop + 800e3ec: 20000dd0 .word 0x20000dd0 + 800e3f0: 40004400 .word 0x40004400 + +0800e3f4 : +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + 800e3f4: b580 push {r7, lr} + 800e3f6: af00 add r7, sp, #0 + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + 800e3f8: 4b11 ldr r3, [pc, #68] @ (800e440 ) + 800e3fa: 4a12 ldr r2, [pc, #72] @ (800e444 ) + 800e3fc: 601a str r2, [r3, #0] + huart3.Init.BaudRate = 115200; + 800e3fe: 4b10 ldr r3, [pc, #64] @ (800e440 ) + 800e400: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 800e404: 605a str r2, [r3, #4] + huart3.Init.WordLength = UART_WORDLENGTH_8B; + 800e406: 4b0e ldr r3, [pc, #56] @ (800e440 ) + 800e408: 2200 movs r2, #0 + 800e40a: 609a str r2, [r3, #8] + huart3.Init.StopBits = UART_STOPBITS_1; + 800e40c: 4b0c ldr r3, [pc, #48] @ (800e440 ) + 800e40e: 2200 movs r2, #0 + 800e410: 60da str r2, [r3, #12] + huart3.Init.Parity = UART_PARITY_NONE; + 800e412: 4b0b ldr r3, [pc, #44] @ (800e440 ) + 800e414: 2200 movs r2, #0 + 800e416: 611a str r2, [r3, #16] + huart3.Init.Mode = UART_MODE_TX_RX; + 800e418: 4b09 ldr r3, [pc, #36] @ (800e440 ) + 800e41a: 220c movs r2, #12 + 800e41c: 615a str r2, [r3, #20] + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800e41e: 4b08 ldr r3, [pc, #32] @ (800e440 ) + 800e420: 2200 movs r2, #0 + 800e422: 619a str r2, [r3, #24] + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + 800e424: 4b06 ldr r3, [pc, #24] @ (800e440 ) + 800e426: 2200 movs r2, #0 + 800e428: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart3) != HAL_OK) + 800e42a: 4805 ldr r0, [pc, #20] @ (800e440 ) + 800e42c: f004 f960 bl 80126f0 + 800e430: 4603 mov r3, r0 + 800e432: 2b00 cmp r3, #0 + 800e434: d001 beq.n 800e43a + { + Error_Handler(); + 800e436: f7fd ff57 bl 800c2e8 + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + 800e43a: bf00 nop + 800e43c: bd80 pop {r7, pc} + 800e43e: bf00 nop + 800e440: 20000e18 .word 0x20000e18 + 800e444: 40004800 .word 0x40004800 + +0800e448 : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 800e448: b580 push {r7, lr} + 800e44a: b092 sub sp, #72 @ 0x48 + 800e44c: af00 add r7, sp, #0 + 800e44e: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800e450: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e454: 2200 movs r2, #0 + 800e456: 601a str r2, [r3, #0] + 800e458: 605a str r2, [r3, #4] + 800e45a: 609a str r2, [r3, #8] + 800e45c: 60da str r2, [r3, #12] + if(uartHandle->Instance==UART5) + 800e45e: 687b ldr r3, [r7, #4] + 800e460: 681b ldr r3, [r3, #0] + 800e462: 4a91 ldr r2, [pc, #580] @ (800e6a8 ) + 800e464: 4293 cmp r3, r2 + 800e466: d13d bne.n 800e4e4 + { + /* USER CODE BEGIN UART5_MspInit 0 */ + + /* USER CODE END UART5_MspInit 0 */ + /* UART5 clock enable */ + __HAL_RCC_UART5_CLK_ENABLE(); + 800e468: 4b90 ldr r3, [pc, #576] @ (800e6ac ) + 800e46a: 69db ldr r3, [r3, #28] + 800e46c: 4a8f ldr r2, [pc, #572] @ (800e6ac ) + 800e46e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 800e472: 61d3 str r3, [r2, #28] + 800e474: 4b8d ldr r3, [pc, #564] @ (800e6ac ) + 800e476: 69db ldr r3, [r3, #28] + 800e478: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800e47c: 62fb str r3, [r7, #44] @ 0x2c + 800e47e: 6afb ldr r3, [r7, #44] @ 0x2c + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800e480: 4b8a ldr r3, [pc, #552] @ (800e6ac ) + 800e482: 699b ldr r3, [r3, #24] + 800e484: 4a89 ldr r2, [pc, #548] @ (800e6ac ) + 800e486: f043 0310 orr.w r3, r3, #16 + 800e48a: 6193 str r3, [r2, #24] + 800e48c: 4b87 ldr r3, [pc, #540] @ (800e6ac ) + 800e48e: 699b ldr r3, [r3, #24] + 800e490: f003 0310 and.w r3, r3, #16 + 800e494: 62bb str r3, [r7, #40] @ 0x28 + 800e496: 6abb ldr r3, [r7, #40] @ 0x28 + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800e498: 4b84 ldr r3, [pc, #528] @ (800e6ac ) + 800e49a: 699b ldr r3, [r3, #24] + 800e49c: 4a83 ldr r2, [pc, #524] @ (800e6ac ) + 800e49e: f043 0320 orr.w r3, r3, #32 + 800e4a2: 6193 str r3, [r2, #24] + 800e4a4: 4b81 ldr r3, [pc, #516] @ (800e6ac ) + 800e4a6: 699b ldr r3, [r3, #24] + 800e4a8: f003 0320 and.w r3, r3, #32 + 800e4ac: 627b str r3, [r7, #36] @ 0x24 + 800e4ae: 6a7b ldr r3, [r7, #36] @ 0x24 + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + 800e4b0: f44f 5380 mov.w r3, #4096 @ 0x1000 + 800e4b4: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800e4b6: 2302 movs r3, #2 + 800e4b8: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800e4ba: 2303 movs r3, #3 + 800e4bc: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800e4be: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e4c2: 4619 mov r1, r3 + 800e4c4: 487a ldr r0, [pc, #488] @ (800e6b0 ) + 800e4c6: f001 ffef bl 80104a8 + + GPIO_InitStruct.Pin = GPIO_PIN_2; + 800e4ca: 2304 movs r3, #4 + 800e4cc: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800e4ce: 2300 movs r3, #0 + 800e4d0: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800e4d2: 2300 movs r3, #0 + 800e4d4: 63bb str r3, [r7, #56] @ 0x38 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800e4d6: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e4da: 4619 mov r1, r3 + 800e4dc: 4875 ldr r0, [pc, #468] @ (800e6b4 ) + 800e4de: f001 ffe3 bl 80104a8 + HAL_NVIC_EnableIRQ(USART3_IRQn); + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } +} + 800e4e2: e0dc b.n 800e69e + else if(uartHandle->Instance==USART1) + 800e4e4: 687b ldr r3, [r7, #4] + 800e4e6: 681b ldr r3, [r3, #0] + 800e4e8: 4a73 ldr r2, [pc, #460] @ (800e6b8 ) + 800e4ea: 4293 cmp r3, r2 + 800e4ec: d13a bne.n 800e564 + __HAL_RCC_USART1_CLK_ENABLE(); + 800e4ee: 4b6f ldr r3, [pc, #444] @ (800e6ac ) + 800e4f0: 699b ldr r3, [r3, #24] + 800e4f2: 4a6e ldr r2, [pc, #440] @ (800e6ac ) + 800e4f4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800e4f8: 6193 str r3, [r2, #24] + 800e4fa: 4b6c ldr r3, [pc, #432] @ (800e6ac ) + 800e4fc: 699b ldr r3, [r3, #24] + 800e4fe: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 800e502: 623b str r3, [r7, #32] + 800e504: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800e506: 4b69 ldr r3, [pc, #420] @ (800e6ac ) + 800e508: 699b ldr r3, [r3, #24] + 800e50a: 4a68 ldr r2, [pc, #416] @ (800e6ac ) + 800e50c: f043 0304 orr.w r3, r3, #4 + 800e510: 6193 str r3, [r2, #24] + 800e512: 4b66 ldr r3, [pc, #408] @ (800e6ac ) + 800e514: 699b ldr r3, [r3, #24] + 800e516: f003 0304 and.w r3, r3, #4 + 800e51a: 61fb str r3, [r7, #28] + 800e51c: 69fb ldr r3, [r7, #28] + GPIO_InitStruct.Pin = GPIO_PIN_9; + 800e51e: f44f 7300 mov.w r3, #512 @ 0x200 + 800e522: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800e524: 2302 movs r3, #2 + 800e526: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800e528: 2303 movs r3, #3 + 800e52a: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800e52c: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e530: 4619 mov r1, r3 + 800e532: 4862 ldr r0, [pc, #392] @ (800e6bc ) + 800e534: f001 ffb8 bl 80104a8 + GPIO_InitStruct.Pin = GPIO_PIN_10; + 800e538: f44f 6380 mov.w r3, #1024 @ 0x400 + 800e53c: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800e53e: 2300 movs r3, #0 + 800e540: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800e542: 2300 movs r3, #0 + 800e544: 63bb str r3, [r7, #56] @ 0x38 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800e546: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e54a: 4619 mov r1, r3 + 800e54c: 485b ldr r0, [pc, #364] @ (800e6bc ) + 800e54e: f001 ffab bl 80104a8 + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + 800e552: 2200 movs r2, #0 + 800e554: 2100 movs r1, #0 + 800e556: 2025 movs r0, #37 @ 0x25 + 800e558: f001 fe11 bl 801017e + HAL_NVIC_EnableIRQ(USART1_IRQn); + 800e55c: 2025 movs r0, #37 @ 0x25 + 800e55e: f001 fe2a bl 80101b6 +} + 800e562: e09c b.n 800e69e + else if(uartHandle->Instance==USART2) + 800e564: 687b ldr r3, [r7, #4] + 800e566: 681b ldr r3, [r3, #0] + 800e568: 4a55 ldr r2, [pc, #340] @ (800e6c0 ) + 800e56a: 4293 cmp r3, r2 + 800e56c: d146 bne.n 800e5fc + __HAL_RCC_USART2_CLK_ENABLE(); + 800e56e: 4b4f ldr r3, [pc, #316] @ (800e6ac ) + 800e570: 69db ldr r3, [r3, #28] + 800e572: 4a4e ldr r2, [pc, #312] @ (800e6ac ) + 800e574: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 800e578: 61d3 str r3, [r2, #28] + 800e57a: 4b4c ldr r3, [pc, #304] @ (800e6ac ) + 800e57c: 69db ldr r3, [r3, #28] + 800e57e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800e582: 61bb str r3, [r7, #24] + 800e584: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800e586: 4b49 ldr r3, [pc, #292] @ (800e6ac ) + 800e588: 699b ldr r3, [r3, #24] + 800e58a: 4a48 ldr r2, [pc, #288] @ (800e6ac ) + 800e58c: f043 0320 orr.w r3, r3, #32 + 800e590: 6193 str r3, [r2, #24] + 800e592: 4b46 ldr r3, [pc, #280] @ (800e6ac ) + 800e594: 699b ldr r3, [r3, #24] + 800e596: f003 0320 and.w r3, r3, #32 + 800e59a: 617b str r3, [r7, #20] + 800e59c: 697b ldr r3, [r7, #20] + GPIO_InitStruct.Pin = GPIO_PIN_5; + 800e59e: 2320 movs r3, #32 + 800e5a0: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800e5a2: 2302 movs r3, #2 + 800e5a4: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800e5a6: 2303 movs r3, #3 + 800e5a8: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800e5aa: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e5ae: 4619 mov r1, r3 + 800e5b0: 4840 ldr r0, [pc, #256] @ (800e6b4 ) + 800e5b2: f001 ff79 bl 80104a8 + GPIO_InitStruct.Pin = GPIO_PIN_6; + 800e5b6: 2340 movs r3, #64 @ 0x40 + 800e5b8: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800e5ba: 2300 movs r3, #0 + 800e5bc: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800e5be: 2300 movs r3, #0 + 800e5c0: 63bb str r3, [r7, #56] @ 0x38 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800e5c2: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e5c6: 4619 mov r1, r3 + 800e5c8: 483a ldr r0, [pc, #232] @ (800e6b4 ) + 800e5ca: f001 ff6d bl 80104a8 + __HAL_AFIO_REMAP_USART2_ENABLE(); + 800e5ce: 4b3d ldr r3, [pc, #244] @ (800e6c4 ) + 800e5d0: 685b ldr r3, [r3, #4] + 800e5d2: 643b str r3, [r7, #64] @ 0x40 + 800e5d4: 6c3b ldr r3, [r7, #64] @ 0x40 + 800e5d6: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 800e5da: 643b str r3, [r7, #64] @ 0x40 + 800e5dc: 6c3b ldr r3, [r7, #64] @ 0x40 + 800e5de: f043 0308 orr.w r3, r3, #8 + 800e5e2: 643b str r3, [r7, #64] @ 0x40 + 800e5e4: 4a37 ldr r2, [pc, #220] @ (800e6c4 ) + 800e5e6: 6c3b ldr r3, [r7, #64] @ 0x40 + 800e5e8: 6053 str r3, [r2, #4] + HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); + 800e5ea: 2200 movs r2, #0 + 800e5ec: 2100 movs r1, #0 + 800e5ee: 2026 movs r0, #38 @ 0x26 + 800e5f0: f001 fdc5 bl 801017e + HAL_NVIC_EnableIRQ(USART2_IRQn); + 800e5f4: 2026 movs r0, #38 @ 0x26 + 800e5f6: f001 fdde bl 80101b6 +} + 800e5fa: e050 b.n 800e69e + else if(uartHandle->Instance==USART3) + 800e5fc: 687b ldr r3, [r7, #4] + 800e5fe: 681b ldr r3, [r3, #0] + 800e600: 4a31 ldr r2, [pc, #196] @ (800e6c8 ) + 800e602: 4293 cmp r3, r2 + 800e604: d14b bne.n 800e69e + __HAL_RCC_USART3_CLK_ENABLE(); + 800e606: 4b29 ldr r3, [pc, #164] @ (800e6ac ) + 800e608: 69db ldr r3, [r3, #28] + 800e60a: 4a28 ldr r2, [pc, #160] @ (800e6ac ) + 800e60c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800e610: 61d3 str r3, [r2, #28] + 800e612: 4b26 ldr r3, [pc, #152] @ (800e6ac ) + 800e614: 69db ldr r3, [r3, #28] + 800e616: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 800e61a: 613b str r3, [r7, #16] + 800e61c: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800e61e: 4b23 ldr r3, [pc, #140] @ (800e6ac ) + 800e620: 699b ldr r3, [r3, #24] + 800e622: 4a22 ldr r2, [pc, #136] @ (800e6ac ) + 800e624: f043 0310 orr.w r3, r3, #16 + 800e628: 6193 str r3, [r2, #24] + 800e62a: 4b20 ldr r3, [pc, #128] @ (800e6ac ) + 800e62c: 699b ldr r3, [r3, #24] + 800e62e: f003 0310 and.w r3, r3, #16 + 800e632: 60fb str r3, [r7, #12] + 800e634: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_10; + 800e636: f44f 6380 mov.w r3, #1024 @ 0x400 + 800e63a: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800e63c: 2302 movs r3, #2 + 800e63e: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800e640: 2303 movs r3, #3 + 800e642: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800e644: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e648: 4619 mov r1, r3 + 800e64a: 4819 ldr r0, [pc, #100] @ (800e6b0 ) + 800e64c: f001 ff2c bl 80104a8 + GPIO_InitStruct.Pin = GPIO_PIN_11; + 800e650: f44f 6300 mov.w r3, #2048 @ 0x800 + 800e654: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800e656: 2300 movs r3, #0 + 800e658: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800e65a: 2300 movs r3, #0 + 800e65c: 63bb str r3, [r7, #56] @ 0x38 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800e65e: f107 0330 add.w r3, r7, #48 @ 0x30 + 800e662: 4619 mov r1, r3 + 800e664: 4812 ldr r0, [pc, #72] @ (800e6b0 ) + 800e666: f001 ff1f bl 80104a8 + __HAL_AFIO_REMAP_USART3_PARTIAL(); + 800e66a: 4b16 ldr r3, [pc, #88] @ (800e6c4 ) + 800e66c: 685b ldr r3, [r3, #4] + 800e66e: 647b str r3, [r7, #68] @ 0x44 + 800e670: 6c7b ldr r3, [r7, #68] @ 0x44 + 800e672: f023 0330 bic.w r3, r3, #48 @ 0x30 + 800e676: 647b str r3, [r7, #68] @ 0x44 + 800e678: 6c7b ldr r3, [r7, #68] @ 0x44 + 800e67a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 + 800e67e: 647b str r3, [r7, #68] @ 0x44 + 800e680: 6c7b ldr r3, [r7, #68] @ 0x44 + 800e682: f043 0310 orr.w r3, r3, #16 + 800e686: 647b str r3, [r7, #68] @ 0x44 + 800e688: 4a0e ldr r2, [pc, #56] @ (800e6c4 ) + 800e68a: 6c7b ldr r3, [r7, #68] @ 0x44 + 800e68c: 6053 str r3, [r2, #4] + HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); + 800e68e: 2200 movs r2, #0 + 800e690: 2100 movs r1, #0 + 800e692: 2027 movs r0, #39 @ 0x27 + 800e694: f001 fd73 bl 801017e + HAL_NVIC_EnableIRQ(USART3_IRQn); + 800e698: 2027 movs r0, #39 @ 0x27 + 800e69a: f001 fd8c bl 80101b6 +} + 800e69e: bf00 nop + 800e6a0: 3748 adds r7, #72 @ 0x48 + 800e6a2: 46bd mov sp, r7 + 800e6a4: bd80 pop {r7, pc} + 800e6a6: bf00 nop + 800e6a8: 40005000 .word 0x40005000 + 800e6ac: 40021000 .word 0x40021000 + 800e6b0: 40011000 .word 0x40011000 + 800e6b4: 40011400 .word 0x40011400 + 800e6b8: 40013800 .word 0x40013800 + 800e6bc: 40010800 .word 0x40010800 + 800e6c0: 40004400 .word 0x40004400 + 800e6c4: 40010000 .word 0x40010000 + 800e6c8: 40004800 .word 0x40004800 + +0800e6cc : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 800e6cc: f8df d034 ldr.w sp, [pc, #52] @ 800e704 + +/* Call the clock system initialization function.*/ + bl SystemInit + 800e6d0: f7ff fd1e bl 800e110 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 800e6d4: 480c ldr r0, [pc, #48] @ (800e708 ) + ldr r1, =_edata + 800e6d6: 490d ldr r1, [pc, #52] @ (800e70c ) + ldr r2, =_sidata + 800e6d8: 4a0d ldr r2, [pc, #52] @ (800e710 ) + movs r3, #0 + 800e6da: 2300 movs r3, #0 + b LoopCopyDataInit + 800e6dc: e002 b.n 800e6e4 + +0800e6de : + +CopyDataInit: + ldr r4, [r2, r3] + 800e6de: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 800e6e0: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 800e6e2: 3304 adds r3, #4 + +0800e6e4 : + +LoopCopyDataInit: + adds r4, r0, r3 + 800e6e4: 18c4 adds r4, r0, r3 + cmp r4, r1 + 800e6e6: 428c cmp r4, r1 + bcc CopyDataInit + 800e6e8: d3f9 bcc.n 800e6de + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 800e6ea: 4a0a ldr r2, [pc, #40] @ (800e714 ) + ldr r4, =_ebss + 800e6ec: 4c0a ldr r4, [pc, #40] @ (800e718 ) + movs r3, #0 + 800e6ee: 2300 movs r3, #0 + b LoopFillZerobss + 800e6f0: e001 b.n 800e6f6 + +0800e6f2 : + +FillZerobss: + str r3, [r2] + 800e6f2: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 800e6f4: 3204 adds r2, #4 + +0800e6f6 : + +LoopFillZerobss: + cmp r2, r4 + 800e6f6: 42a2 cmp r2, r4 + bcc FillZerobss + 800e6f8: d3fb bcc.n 800e6f2 + + +/* Call static constructors */ + bl __libc_init_array + 800e6fa: f005 fd9d bl 8014238 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800e6fe: f7fd fd05 bl 800c10c
+ bx lr + 800e702: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 800e704: 20010000 .word 0x20010000 + ldr r0, =_sdata + 800e708: 20000000 .word 0x20000000 + ldr r1, =_edata + 800e70c: 20000240 .word 0x20000240 + ldr r2, =_sidata + 800e710: 08017004 .word 0x08017004 + ldr r2, =_sbss + 800e714: 20000240 .word 0x20000240 + ldr r4, =_ebss + 800e718: 20000fb0 .word 0x20000fb0 + +0800e71c : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 800e71c: e7fe b.n 800e71c + ... + +0800e720 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 800e720: b580 push {r7, lr} + 800e722: af00 add r7, sp, #0 + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 800e724: 4b08 ldr r3, [pc, #32] @ (800e748 ) + 800e726: 681b ldr r3, [r3, #0] + 800e728: 4a07 ldr r2, [pc, #28] @ (800e748 ) + 800e72a: f043 0310 orr.w r3, r3, #16 + 800e72e: 6013 str r3, [r2, #0] +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 800e730: 2003 movs r0, #3 + 800e732: f001 fd19 bl 8010168 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 800e736: 200f movs r0, #15 + 800e738: f000 f808 bl 800e74c + + /* Init the low level hardware */ + HAL_MspInit(); + 800e73c: f7ff fba8 bl 800de90 + + /* Return function status */ + return HAL_OK; + 800e740: 2300 movs r3, #0 +} + 800e742: 4618 mov r0, r3 + 800e744: bd80 pop {r7, pc} + 800e746: bf00 nop + 800e748: 40022000 .word 0x40022000 + +0800e74c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 800e74c: b580 push {r7, lr} + 800e74e: b082 sub sp, #8 + 800e750: af00 add r7, sp, #0 + 800e752: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 800e754: 4b12 ldr r3, [pc, #72] @ (800e7a0 ) + 800e756: 681a ldr r2, [r3, #0] + 800e758: 4b12 ldr r3, [pc, #72] @ (800e7a4 ) + 800e75a: 781b ldrb r3, [r3, #0] + 800e75c: 4619 mov r1, r3 + 800e75e: f44f 737a mov.w r3, #1000 @ 0x3e8 + 800e762: fbb3 f3f1 udiv r3, r3, r1 + 800e766: fbb2 f3f3 udiv r3, r2, r3 + 800e76a: 4618 mov r0, r3 + 800e76c: f001 fd31 bl 80101d2 + 800e770: 4603 mov r3, r0 + 800e772: 2b00 cmp r3, #0 + 800e774: d001 beq.n 800e77a + { + return HAL_ERROR; + 800e776: 2301 movs r3, #1 + 800e778: e00e b.n 800e798 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 800e77a: 687b ldr r3, [r7, #4] + 800e77c: 2b0f cmp r3, #15 + 800e77e: d80a bhi.n 800e796 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 800e780: 2200 movs r2, #0 + 800e782: 6879 ldr r1, [r7, #4] + 800e784: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800e788: f001 fcf9 bl 801017e + uwTickPrio = TickPriority; + 800e78c: 4a06 ldr r2, [pc, #24] @ (800e7a8 ) + 800e78e: 687b ldr r3, [r7, #4] + 800e790: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 800e792: 2300 movs r3, #0 + 800e794: e000 b.n 800e798 + return HAL_ERROR; + 800e796: 2301 movs r3, #1 +} + 800e798: 4618 mov r0, r3 + 800e79a: 3708 adds r7, #8 + 800e79c: 46bd mov sp, r7 + 800e79e: bd80 pop {r7, pc} + 800e7a0: 2000006c .word 0x2000006c + 800e7a4: 20000074 .word 0x20000074 + 800e7a8: 20000070 .word 0x20000070 + +0800e7ac : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 800e7ac: b480 push {r7} + 800e7ae: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 800e7b0: 4b05 ldr r3, [pc, #20] @ (800e7c8 ) + 800e7b2: 781b ldrb r3, [r3, #0] + 800e7b4: 461a mov r2, r3 + 800e7b6: 4b05 ldr r3, [pc, #20] @ (800e7cc ) + 800e7b8: 681b ldr r3, [r3, #0] + 800e7ba: 4413 add r3, r2 + 800e7bc: 4a03 ldr r2, [pc, #12] @ (800e7cc ) + 800e7be: 6013 str r3, [r2, #0] +} + 800e7c0: bf00 nop + 800e7c2: 46bd mov sp, r7 + 800e7c4: bc80 pop {r7} + 800e7c6: 4770 bx lr + 800e7c8: 20000074 .word 0x20000074 + 800e7cc: 20000e60 .word 0x20000e60 + +0800e7d0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 800e7d0: b480 push {r7} + 800e7d2: af00 add r7, sp, #0 + return uwTick; + 800e7d4: 4b02 ldr r3, [pc, #8] @ (800e7e0 ) + 800e7d6: 681b ldr r3, [r3, #0] +} + 800e7d8: 4618 mov r0, r3 + 800e7da: 46bd mov sp, r7 + 800e7dc: bc80 pop {r7} + 800e7de: 4770 bx lr + 800e7e0: 20000e60 .word 0x20000e60 + +0800e7e4 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 800e7e4: b580 push {r7, lr} + 800e7e6: b084 sub sp, #16 + 800e7e8: af00 add r7, sp, #0 + 800e7ea: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 800e7ec: f7ff fff0 bl 800e7d0 + 800e7f0: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800e7f2: 687b ldr r3, [r7, #4] + 800e7f4: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800e7f6: 68fb ldr r3, [r7, #12] + 800e7f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800e7fc: d005 beq.n 800e80a + { + wait += (uint32_t)(uwTickFreq); + 800e7fe: 4b0a ldr r3, [pc, #40] @ (800e828 ) + 800e800: 781b ldrb r3, [r3, #0] + 800e802: 461a mov r2, r3 + 800e804: 68fb ldr r3, [r7, #12] + 800e806: 4413 add r3, r2 + 800e808: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 800e80a: bf00 nop + 800e80c: f7ff ffe0 bl 800e7d0 + 800e810: 4602 mov r2, r0 + 800e812: 68bb ldr r3, [r7, #8] + 800e814: 1ad3 subs r3, r2, r3 + 800e816: 68fa ldr r2, [r7, #12] + 800e818: 429a cmp r2, r3 + 800e81a: d8f7 bhi.n 800e80c + { + } +} + 800e81c: bf00 nop + 800e81e: bf00 nop + 800e820: 3710 adds r7, #16 + 800e822: 46bd mov sp, r7 + 800e824: bd80 pop {r7, pc} + 800e826: bf00 nop + 800e828: 20000074 .word 0x20000074 + +0800e82c : + * of structure "ADC_InitTypeDef". + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + 800e82c: b580 push {r7, lr} + 800e82e: b086 sub sp, #24 + 800e830: af00 add r7, sp, #0 + 800e832: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 800e834: 2300 movs r3, #0 + 800e836: 75fb strb r3, [r7, #23] + uint32_t tmp_cr1 = 0U; + 800e838: 2300 movs r3, #0 + 800e83a: 613b str r3, [r7, #16] + uint32_t tmp_cr2 = 0U; + 800e83c: 2300 movs r3, #0 + 800e83e: 60bb str r3, [r7, #8] + uint32_t tmp_sqr1 = 0U; + 800e840: 2300 movs r3, #0 + 800e842: 60fb str r3, [r7, #12] + + /* Check ADC handle */ + if(hadc == NULL) + 800e844: 687b ldr r3, [r7, #4] + 800e846: 2b00 cmp r3, #0 + 800e848: d101 bne.n 800e84e + { + return HAL_ERROR; + 800e84a: 2301 movs r3, #1 + 800e84c: e0be b.n 800e9cc + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + 800e84e: 687b ldr r3, [r7, #4] + 800e850: 689b ldr r3, [r3, #8] + 800e852: 2b00 cmp r3, #0 + /* Refer to header of this file for more details on clock enabling */ + /* procedure. */ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + 800e854: 687b ldr r3, [r7, #4] + 800e856: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e858: 2b00 cmp r3, #0 + 800e85a: d109 bne.n 800e870 + { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 800e85c: 687b ldr r3, [r7, #4] + 800e85e: 2200 movs r2, #0 + 800e860: 62da str r2, [r3, #44] @ 0x2c + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + 800e862: 687b ldr r3, [r7, #4] + 800e864: 2200 movs r2, #0 + 800e866: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 800e86a: 6878 ldr r0, [r7, #4] + 800e86c: f7fa feea bl 8009644 + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + /* Note: In case of ADC already enabled, precaution to not launch an */ + /* unwanted conversion while modifying register CR2 by writing 1 to */ + /* bit ADON. */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + 800e870: 6878 ldr r0, [r7, #4] + 800e872: f000 fbf1 bl 800f058 + 800e876: 4603 mov r3, r0 + 800e878: 75fb strb r3, [r7, #23] + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && + 800e87a: 687b ldr r3, [r7, #4] + 800e87c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e87e: f003 0310 and.w r3, r3, #16 + 800e882: 2b00 cmp r3, #0 + 800e884: f040 8099 bne.w 800e9ba + 800e888: 7dfb ldrb r3, [r7, #23] + 800e88a: 2b00 cmp r3, #0 + 800e88c: f040 8095 bne.w 800e9ba + (tmp_hal_status == HAL_OK) ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800e890: 687b ldr r3, [r7, #4] + 800e892: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e894: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 800e898: f023 0302 bic.w r3, r3, #2 + 800e89c: f043 0202 orr.w r2, r3, #2 + 800e8a0: 687b ldr r3, [r7, #4] + 800e8a2: 629a str r2, [r3, #40] @ 0x28 + /* - continuous conversion mode */ + /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ + /* HAL_ADC_Start_xxx functions because if set in this function, */ + /* a conversion on injected group would start a conversion also on */ + /* regular group after ADC enabling. */ + tmp_cr2 |= (hadc->Init.DataAlign | + 800e8a4: 687b ldr r3, [r7, #4] + 800e8a6: 685a ldr r2, [r3, #4] + ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | + 800e8a8: 687b ldr r3, [r7, #4] + 800e8aa: 69db ldr r3, [r3, #28] + tmp_cr2 |= (hadc->Init.DataAlign | + 800e8ac: 431a orrs r2, r3 + ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); + 800e8ae: 687b ldr r3, [r7, #4] + 800e8b0: 7b1b ldrb r3, [r3, #12] + 800e8b2: 005b lsls r3, r3, #1 + ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | + 800e8b4: 4313 orrs r3, r2 + tmp_cr2 |= (hadc->Init.DataAlign | + 800e8b6: 68ba ldr r2, [r7, #8] + 800e8b8: 4313 orrs r3, r2 + 800e8ba: 60bb str r3, [r7, #8] + + /* Configuration of ADC: */ + /* - scan mode */ + /* - discontinuous mode disable/enable */ + /* - discontinuous mode number of conversions */ + tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); + 800e8bc: 687b ldr r3, [r7, #4] + 800e8be: 689b ldr r3, [r3, #8] + 800e8c0: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800e8c4: d003 beq.n 800e8ce + 800e8c6: 687b ldr r3, [r7, #4] + 800e8c8: 689b ldr r3, [r3, #8] + 800e8ca: 2b01 cmp r3, #1 + 800e8cc: d102 bne.n 800e8d4 + 800e8ce: f44f 7380 mov.w r3, #256 @ 0x100 + 800e8d2: e000 b.n 800e8d6 + 800e8d4: 2300 movs r3, #0 + 800e8d6: 693a ldr r2, [r7, #16] + 800e8d8: 4313 orrs r3, r2 + 800e8da: 613b str r3, [r7, #16] + + /* Enable discontinuous mode only if continuous mode is disabled */ + /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ + /* discontinuous is set anyway, but will have no effect on ADC HW. */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + 800e8dc: 687b ldr r3, [r7, #4] + 800e8de: 7d1b ldrb r3, [r3, #20] + 800e8e0: 2b01 cmp r3, #1 + 800e8e2: d119 bne.n 800e918 + { + if (hadc->Init.ContinuousConvMode == DISABLE) + 800e8e4: 687b ldr r3, [r7, #4] + 800e8e6: 7b1b ldrb r3, [r3, #12] + 800e8e8: 2b00 cmp r3, #0 + 800e8ea: d109 bne.n 800e900 + { + /* Enable the selected ADC regular discontinuous mode */ + /* Set the number of channels to be converted in discontinuous mode */ + SET_BIT(tmp_cr1, ADC_CR1_DISCEN | + 800e8ec: 687b ldr r3, [r7, #4] + 800e8ee: 699b ldr r3, [r3, #24] + 800e8f0: 3b01 subs r3, #1 + 800e8f2: 035a lsls r2, r3, #13 + 800e8f4: 693b ldr r3, [r7, #16] + 800e8f6: 4313 orrs r3, r2 + 800e8f8: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 800e8fc: 613b str r3, [r7, #16] + 800e8fe: e00b b.n 800e918 + { + /* ADC regular group settings continuous and sequencer discontinuous*/ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 800e900: 687b ldr r3, [r7, #4] + 800e902: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e904: f043 0220 orr.w r2, r3, #32 + 800e908: 687b ldr r3, [r7, #4] + 800e90a: 629a str r2, [r3, #40] @ 0x28 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 800e90c: 687b ldr r3, [r7, #4] + 800e90e: 6adb ldr r3, [r3, #44] @ 0x2c + 800e910: f043 0201 orr.w r2, r3, #1 + 800e914: 687b ldr r3, [r7, #4] + 800e916: 62da str r2, [r3, #44] @ 0x2c + } + } + + /* Update ADC configuration register CR1 with previous settings */ + MODIFY_REG(hadc->Instance->CR1, + 800e918: 687b ldr r3, [r7, #4] + 800e91a: 681b ldr r3, [r3, #0] + 800e91c: 685b ldr r3, [r3, #4] + 800e91e: f423 4169 bic.w r1, r3, #59648 @ 0xe900 + 800e922: 687b ldr r3, [r7, #4] + 800e924: 681b ldr r3, [r3, #0] + 800e926: 693a ldr r2, [r7, #16] + 800e928: 430a orrs r2, r1 + 800e92a: 605a str r2, [r3, #4] + ADC_CR1_DISCEN | + ADC_CR1_DISCNUM , + tmp_cr1 ); + + /* Update ADC configuration register CR2 with previous settings */ + MODIFY_REG(hadc->Instance->CR2, + 800e92c: 687b ldr r3, [r7, #4] + 800e92e: 681b ldr r3, [r3, #0] + 800e930: 689a ldr r2, [r3, #8] + 800e932: 4b28 ldr r3, [pc, #160] @ (800e9d4 ) + 800e934: 4013 ands r3, r2 + 800e936: 687a ldr r2, [r7, #4] + 800e938: 6812 ldr r2, [r2, #0] + 800e93a: 68b9 ldr r1, [r7, #8] + 800e93c: 430b orrs r3, r1 + 800e93e: 6093 str r3, [r2, #8] + /* Note: Scan mode is present by hardware on this device and, if */ + /* disabled, discards automatically nb of conversions. Anyway, nb of */ + /* conversions is forced to 0x00 for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion" */ + if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) + 800e940: 687b ldr r3, [r7, #4] + 800e942: 689b ldr r3, [r3, #8] + 800e944: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 800e948: d003 beq.n 800e952 + 800e94a: 687b ldr r3, [r7, #4] + 800e94c: 689b ldr r3, [r3, #8] + 800e94e: 2b01 cmp r3, #1 + 800e950: d104 bne.n 800e95c + { + tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); + 800e952: 687b ldr r3, [r7, #4] + 800e954: 691b ldr r3, [r3, #16] + 800e956: 3b01 subs r3, #1 + 800e958: 051b lsls r3, r3, #20 + 800e95a: 60fb str r3, [r7, #12] + } + + MODIFY_REG(hadc->Instance->SQR1, + 800e95c: 687b ldr r3, [r7, #4] + 800e95e: 681b ldr r3, [r3, #0] + 800e960: 6adb ldr r3, [r3, #44] @ 0x2c + 800e962: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 + 800e966: 687b ldr r3, [r7, #4] + 800e968: 681b ldr r3, [r3, #0] + 800e96a: 68fa ldr r2, [r7, #12] + 800e96c: 430a orrs r2, r1 + 800e96e: 62da str r2, [r3, #44] @ 0x2c + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CR2 (excluding bits set in other functions: */ + /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ + /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ + /* measurement path bit (TSVREFE). */ + if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | + 800e970: 687b ldr r3, [r7, #4] + 800e972: 681b ldr r3, [r3, #0] + 800e974: 689a ldr r2, [r3, #8] + 800e976: 4b18 ldr r3, [pc, #96] @ (800e9d8 ) + 800e978: 4013 ands r3, r2 + 800e97a: 68ba ldr r2, [r7, #8] + 800e97c: 429a cmp r2, r3 + 800e97e: d10b bne.n 800e998 + ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | + ADC_CR2_TSVREFE )) + == tmp_cr2) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 800e980: 687b ldr r3, [r7, #4] + 800e982: 2200 movs r2, #0 + 800e984: 62da str r2, [r3, #44] @ 0x2c + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800e986: 687b ldr r3, [r7, #4] + 800e988: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e98a: f023 0303 bic.w r3, r3, #3 + 800e98e: f043 0201 orr.w r2, r3, #1 + 800e992: 687b ldr r3, [r7, #4] + 800e994: 629a str r2, [r3, #40] @ 0x28 + if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | + 800e996: e018 b.n 800e9ca + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + 800e998: 687b ldr r3, [r7, #4] + 800e99a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e99c: f023 0312 bic.w r3, r3, #18 + 800e9a0: f043 0210 orr.w r2, r3, #16 + 800e9a4: 687b ldr r3, [r7, #4] + 800e9a6: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 800e9a8: 687b ldr r3, [r7, #4] + 800e9aa: 6adb ldr r3, [r3, #44] @ 0x2c + 800e9ac: f043 0201 orr.w r2, r3, #1 + 800e9b0: 687b ldr r3, [r7, #4] + 800e9b2: 62da str r2, [r3, #44] @ 0x2c + + tmp_hal_status = HAL_ERROR; + 800e9b4: 2301 movs r3, #1 + 800e9b6: 75fb strb r3, [r7, #23] + if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | + 800e9b8: e007 b.n 800e9ca + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 800e9ba: 687b ldr r3, [r7, #4] + 800e9bc: 6a9b ldr r3, [r3, #40] @ 0x28 + 800e9be: f043 0210 orr.w r2, r3, #16 + 800e9c2: 687b ldr r3, [r7, #4] + 800e9c4: 629a str r2, [r3, #40] @ 0x28 + + tmp_hal_status = HAL_ERROR; + 800e9c6: 2301 movs r3, #1 + 800e9c8: 75fb strb r3, [r7, #23] + } + + /* Return function status */ + return tmp_hal_status; + 800e9ca: 7dfb ldrb r3, [r7, #23] +} + 800e9cc: 4618 mov r0, r3 + 800e9ce: 3718 adds r7, #24 + 800e9d0: 46bd mov sp, r7 + 800e9d2: bd80 pop {r7, pc} + 800e9d4: ffe1f7fd .word 0xffe1f7fd + 800e9d8: ff1f0efe .word 0xff1f0efe + +0800e9dc : + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + 800e9dc: b580 push {r7, lr} + 800e9de: b084 sub sp, #16 + 800e9e0: af00 add r7, sp, #0 + 800e9e2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 800e9e4: 2300 movs r3, #0 + 800e9e6: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + 800e9e8: 687b ldr r3, [r7, #4] + 800e9ea: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800e9ee: 2b01 cmp r3, #1 + 800e9f0: d101 bne.n 800e9f6 + 800e9f2: 2302 movs r3, #2 + 800e9f4: e098 b.n 800eb28 + 800e9f6: 687b ldr r3, [r7, #4] + 800e9f8: 2201 movs r2, #1 + 800e9fa: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + 800e9fe: 6878 ldr r0, [r7, #4] + 800ea00: f000 fad0 bl 800efa4 + 800ea04: 4603 mov r3, r0 + 800ea06: 73fb strb r3, [r7, #15] + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + 800ea08: 7bfb ldrb r3, [r7, #15] + 800ea0a: 2b00 cmp r3, #0 + 800ea0c: f040 8087 bne.w 800eb1e + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + 800ea10: 687b ldr r3, [r7, #4] + 800ea12: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ea14: f423 7340 bic.w r3, r3, #768 @ 0x300 + 800ea18: f023 0301 bic.w r3, r3, #1 + 800ea1c: f443 7280 orr.w r2, r3, #256 @ 0x100 + 800ea20: 687b ldr r3, [r7, #4] + 800ea22: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_REG_BUSY); + + /* Set group injected state (from auto-injection) and multimode state */ + /* for all cases of multimode: independent mode, multimode ADC master */ + /* or multimode ADC slave (for devices with several ADCs): */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + 800ea24: 687b ldr r3, [r7, #4] + 800ea26: 681b ldr r3, [r3, #0] + 800ea28: 4a41 ldr r2, [pc, #260] @ (800eb30 ) + 800ea2a: 4293 cmp r3, r2 + 800ea2c: d105 bne.n 800ea3a + 800ea2e: 4b41 ldr r3, [pc, #260] @ (800eb34 ) + 800ea30: 685b ldr r3, [r3, #4] + 800ea32: f403 2370 and.w r3, r3, #983040 @ 0xf0000 + 800ea36: 2b00 cmp r3, #0 + 800ea38: d115 bne.n 800ea66 + { + /* Set ADC state (ADC independent or master) */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + 800ea3a: 687b ldr r3, [r7, #4] + 800ea3c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ea3e: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 + 800ea42: 687b ldr r3, [r7, #4] + 800ea44: 629a str r2, [r3, #40] @ 0x28 + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 800ea46: 687b ldr r3, [r7, #4] + 800ea48: 681b ldr r3, [r3, #0] + 800ea4a: 685b ldr r3, [r3, #4] + 800ea4c: f403 6380 and.w r3, r3, #1024 @ 0x400 + 800ea50: 2b00 cmp r3, #0 + 800ea52: d026 beq.n 800eaa2 + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + 800ea54: 687b ldr r3, [r7, #4] + 800ea56: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ea58: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 800ea5c: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 800ea60: 687b ldr r3, [r7, #4] + 800ea62: 629a str r2, [r3, #40] @ 0x28 + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 800ea64: e01d b.n 800eaa2 + } + } + else + { + /* Set ADC state (ADC slave) */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + 800ea66: 687b ldr r3, [r7, #4] + 800ea68: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ea6a: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 + 800ea6e: 687b ldr r3, [r7, #4] + 800ea70: 629a str r2, [r3, #40] @ 0x28 + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) + 800ea72: 687b ldr r3, [r7, #4] + 800ea74: 681b ldr r3, [r3, #0] + 800ea76: 4a2f ldr r2, [pc, #188] @ (800eb34 ) + 800ea78: 4293 cmp r3, r2 + 800ea7a: d004 beq.n 800ea86 + 800ea7c: 687b ldr r3, [r7, #4] + 800ea7e: 681b ldr r3, [r3, #0] + 800ea80: 4a2b ldr r2, [pc, #172] @ (800eb30 ) + 800ea82: 4293 cmp r3, r2 + 800ea84: d10d bne.n 800eaa2 + 800ea86: 4b2b ldr r3, [pc, #172] @ (800eb34 ) + 800ea88: 685b ldr r3, [r3, #4] + 800ea8a: f403 6380 and.w r3, r3, #1024 @ 0x400 + 800ea8e: 2b00 cmp r3, #0 + 800ea90: d007 beq.n 800eaa2 + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + 800ea92: 687b ldr r3, [r7, #4] + 800ea94: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ea96: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 800ea9a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 800ea9e: 687b ldr r3, [r7, #4] + 800eaa0: 629a str r2, [r3, #40] @ 0x28 + } + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 800eaa2: 687b ldr r3, [r7, #4] + 800eaa4: 6a9b ldr r3, [r3, #40] @ 0x28 + 800eaa6: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 800eaaa: 2b00 cmp r3, #0 + 800eaac: d006 beq.n 800eabc + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + 800eaae: 687b ldr r3, [r7, #4] + 800eab0: 6adb ldr r3, [r3, #44] @ 0x2c + 800eab2: f023 0206 bic.w r2, r3, #6 + 800eab6: 687b ldr r3, [r7, #4] + 800eab8: 62da str r2, [r3, #44] @ 0x2c + 800eaba: e002 b.n 800eac2 + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + 800eabc: 687b ldr r3, [r7, #4] + 800eabe: 2200 movs r2, #0 + 800eac0: 62da str r2, [r3, #44] @ 0x2c + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + 800eac2: 687b ldr r3, [r7, #4] + 800eac4: 2200 movs r2, #0 + 800eac6: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Clear regular group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + 800eaca: 687b ldr r3, [r7, #4] + 800eacc: 681b ldr r3, [r3, #0] + 800eace: f06f 0202 mvn.w r2, #2 + 800ead2: 601a str r2, [r3, #0] + /* - if ADC is slave, ADC is enabled only (conversion is not started). */ + /* - if ADC is master, ADC is enabled and conversion is started. */ + /* If ADC is master, ADC is enabled and conversion is started. */ + /* Note: Alternate trigger for single conversion could be to force an */ + /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800ead4: 687b ldr r3, [r7, #4] + 800ead6: 681b ldr r3, [r3, #0] + 800ead8: 689b ldr r3, [r3, #8] + 800eada: f403 2360 and.w r3, r3, #917504 @ 0xe0000 + 800eade: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 + 800eae2: d113 bne.n 800eb0c + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + 800eae4: 687b ldr r3, [r7, #4] + 800eae6: 681b ldr r3, [r3, #0] + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800eae8: 4a11 ldr r2, [pc, #68] @ (800eb30 ) + 800eaea: 4293 cmp r3, r2 + 800eaec: d105 bne.n 800eafa + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + 800eaee: 4b11 ldr r3, [pc, #68] @ (800eb34 ) + 800eaf0: 685b ldr r3, [r3, #4] + 800eaf2: f403 2370 and.w r3, r3, #983040 @ 0xf0000 + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800eaf6: 2b00 cmp r3, #0 + 800eaf8: d108 bne.n 800eb0c + { + /* Start ADC conversion on regular group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); + 800eafa: 687b ldr r3, [r7, #4] + 800eafc: 681b ldr r3, [r3, #0] + 800eafe: 689a ldr r2, [r3, #8] + 800eb00: 687b ldr r3, [r7, #4] + 800eb02: 681b ldr r3, [r3, #0] + 800eb04: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 + 800eb08: 609a str r2, [r3, #8] + 800eb0a: e00c b.n 800eb26 + } + else + { + /* Start ADC conversion on regular group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); + 800eb0c: 687b ldr r3, [r7, #4] + 800eb0e: 681b ldr r3, [r3, #0] + 800eb10: 689a ldr r2, [r3, #8] + 800eb12: 687b ldr r3, [r7, #4] + 800eb14: 681b ldr r3, [r3, #0] + 800eb16: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 + 800eb1a: 609a str r2, [r3, #8] + 800eb1c: e003 b.n 800eb26 + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800eb1e: 687b ldr r3, [r7, #4] + 800eb20: 2200 movs r2, #0 + 800eb22: f883 2024 strb.w r2, [r3, #36] @ 0x24 + } + + /* Return function status */ + return tmp_hal_status; + 800eb26: 7bfb ldrb r3, [r7, #15] +} + 800eb28: 4618 mov r0, r3 + 800eb2a: 3710 adds r7, #16 + 800eb2c: 46bd mov sp, r7 + 800eb2e: bd80 pop {r7, pc} + 800eb30: 40012800 .word 0x40012800 + 800eb34: 40012400 .word 0x40012400 + +0800eb38 : + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + 800eb38: b580 push {r7, lr} + 800eb3a: b084 sub sp, #16 + 800eb3c: af00 add r7, sp, #0 + 800eb3e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 800eb40: 2300 movs r3, #0 + 800eb42: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + 800eb44: 687b ldr r3, [r7, #4] + 800eb46: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800eb4a: 2b01 cmp r3, #1 + 800eb4c: d101 bne.n 800eb52 + 800eb4e: 2302 movs r3, #2 + 800eb50: e01a b.n 800eb88 + 800eb52: 687b ldr r3, [r7, #4] + 800eb54: 2201 movs r2, #1 + 800eb56: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + 800eb5a: 6878 ldr r0, [r7, #4] + 800eb5c: f000 fa7c bl 800f058 + 800eb60: 4603 mov r3, r0 + 800eb62: 73fb strb r3, [r7, #15] + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + 800eb64: 7bfb ldrb r3, [r7, #15] + 800eb66: 2b00 cmp r3, #0 + 800eb68: d109 bne.n 800eb7e + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800eb6a: 687b ldr r3, [r7, #4] + 800eb6c: 6a9b ldr r3, [r3, #40] @ 0x28 + 800eb6e: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 800eb72: f023 0301 bic.w r3, r3, #1 + 800eb76: f043 0201 orr.w r2, r3, #1 + 800eb7a: 687b ldr r3, [r7, #4] + 800eb7c: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800eb7e: 687b ldr r3, [r7, #4] + 800eb80: 2200 movs r2, #0 + 800eb82: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Return function status */ + return tmp_hal_status; + 800eb86: 7bfb ldrb r3, [r7, #15] +} + 800eb88: 4618 mov r0, r3 + 800eb8a: 3710 adds r7, #16 + 800eb8c: 46bd mov sp, r7 + 800eb8e: bd80 pop {r7, pc} + +0800eb90 : + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + 800eb90: b590 push {r4, r7, lr} + 800eb92: b087 sub sp, #28 + 800eb94: af00 add r7, sp, #0 + 800eb96: 6078 str r0, [r7, #4] + 800eb98: 6039 str r1, [r7, #0] + uint32_t tickstart = 0U; + 800eb9a: 2300 movs r3, #0 + 800eb9c: 617b str r3, [r7, #20] + + /* Variables for polling in case of scan mode enabled and polling for each */ + /* conversion. */ + __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; + 800eb9e: 2300 movs r3, #0 + 800eba0: 60fb str r3, [r7, #12] + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; + 800eba2: 2300 movs r3, #0 + 800eba4: 613b str r3, [r7, #16] + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + 800eba6: f7ff fe13 bl 800e7d0 + 800ebaa: 6178 str r0, [r7, #20] + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) + 800ebac: 687b ldr r3, [r7, #4] + 800ebae: 681b ldr r3, [r3, #0] + 800ebb0: 689b ldr r3, [r3, #8] + 800ebb2: f403 7380 and.w r3, r3, #256 @ 0x100 + 800ebb6: 2b00 cmp r3, #0 + 800ebb8: d00b beq.n 800ebd2 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 800ebba: 687b ldr r3, [r7, #4] + 800ebbc: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ebbe: f043 0220 orr.w r2, r3, #32 + 800ebc2: 687b ldr r3, [r7, #4] + 800ebc4: 629a str r2, [r3, #40] @ 0x28 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800ebc6: 687b ldr r3, [r7, #4] + 800ebc8: 2200 movs r2, #0 + 800ebca: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800ebce: 2301 movs r3, #1 + 800ebd0: e0d3 b.n 800ed7a + /* from ADC conversion time (selected sampling time + conversion time of */ + /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ + /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ + /* As flag EOC is not set after each conversion, no timeout status can */ + /* be set. */ + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && + 800ebd2: 687b ldr r3, [r7, #4] + 800ebd4: 681b ldr r3, [r3, #0] + 800ebd6: 685b ldr r3, [r3, #4] + 800ebd8: f403 7380 and.w r3, r3, #256 @ 0x100 + 800ebdc: 2b00 cmp r3, #0 + 800ebde: d131 bne.n 800ec44 + HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) + 800ebe0: 687b ldr r3, [r7, #4] + 800ebe2: 681b ldr r3, [r3, #0] + 800ebe4: 6adb ldr r3, [r3, #44] @ 0x2c + 800ebe6: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && + 800ebea: 2b00 cmp r3, #0 + 800ebec: d12a bne.n 800ec44 + { + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + 800ebee: e021 b.n 800ec34 + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + 800ebf0: 683b ldr r3, [r7, #0] + 800ebf2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800ebf6: d01d beq.n 800ec34 + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + 800ebf8: 683b ldr r3, [r7, #0] + 800ebfa: 2b00 cmp r3, #0 + 800ebfc: d007 beq.n 800ec0e + 800ebfe: f7ff fde7 bl 800e7d0 + 800ec02: 4602 mov r2, r0 + 800ec04: 697b ldr r3, [r7, #20] + 800ec06: 1ad3 subs r3, r2, r3 + 800ec08: 683a ldr r2, [r7, #0] + 800ec0a: 429a cmp r2, r3 + 800ec0c: d212 bcs.n 800ec34 + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + 800ec0e: 687b ldr r3, [r7, #4] + 800ec10: 681b ldr r3, [r3, #0] + 800ec12: 681b ldr r3, [r3, #0] + 800ec14: f003 0302 and.w r3, r3, #2 + 800ec18: 2b00 cmp r3, #0 + 800ec1a: d10b bne.n 800ec34 + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + 800ec1c: 687b ldr r3, [r7, #4] + 800ec1e: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ec20: f043 0204 orr.w r2, r3, #4 + 800ec24: 687b ldr r3, [r7, #4] + 800ec26: 629a str r2, [r3, #40] @ 0x28 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800ec28: 687b ldr r3, [r7, #4] + 800ec2a: 2200 movs r2, #0 + 800ec2c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_TIMEOUT; + 800ec30: 2303 movs r3, #3 + 800ec32: e0a2 b.n 800ed7a + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + 800ec34: 687b ldr r3, [r7, #4] + 800ec36: 681b ldr r3, [r3, #0] + 800ec38: 681b ldr r3, [r3, #0] + 800ec3a: f003 0302 and.w r3, r3, #2 + 800ec3e: 2b00 cmp r3, #0 + 800ec40: d0d6 beq.n 800ebf0 + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && + 800ec42: e070 b.n 800ed26 + /* Replace polling by wait for maximum conversion time */ + /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ + /* and ADC maximum conversion cycles on all channels. */ + /* - Wait for the expected ADC clock cycles delay */ + Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock + / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) + 800ec44: 4b4f ldr r3, [pc, #316] @ (800ed84 ) + 800ec46: 681c ldr r4, [r3, #0] + 800ec48: 2002 movs r0, #2 + 800ec4a: f002 fcfb bl 8011644 + 800ec4e: 4603 mov r3, r0 + 800ec50: fbb4 f2f3 udiv r2, r4, r3 + * ADC_CONVCYCLES_MAX_RANGE(hadc) ); + 800ec54: 687b ldr r3, [r7, #4] + 800ec56: 681b ldr r3, [r3, #0] + 800ec58: 6919 ldr r1, [r3, #16] + 800ec5a: 4b4b ldr r3, [pc, #300] @ (800ed88 ) + 800ec5c: 400b ands r3, r1 + 800ec5e: 2b00 cmp r3, #0 + 800ec60: d118 bne.n 800ec94 + 800ec62: 687b ldr r3, [r7, #4] + 800ec64: 681b ldr r3, [r3, #0] + 800ec66: 68d9 ldr r1, [r3, #12] + 800ec68: 4b48 ldr r3, [pc, #288] @ (800ed8c ) + 800ec6a: 400b ands r3, r1 + 800ec6c: 2b00 cmp r3, #0 + 800ec6e: d111 bne.n 800ec94 + 800ec70: 687b ldr r3, [r7, #4] + 800ec72: 681b ldr r3, [r3, #0] + 800ec74: 6919 ldr r1, [r3, #16] + 800ec76: 4b46 ldr r3, [pc, #280] @ (800ed90 ) + 800ec78: 400b ands r3, r1 + 800ec7a: 2b00 cmp r3, #0 + 800ec7c: d108 bne.n 800ec90 + 800ec7e: 687b ldr r3, [r7, #4] + 800ec80: 681b ldr r3, [r3, #0] + 800ec82: 68d9 ldr r1, [r3, #12] + 800ec84: 4b43 ldr r3, [pc, #268] @ (800ed94 ) + 800ec86: 400b ands r3, r1 + 800ec88: 2b00 cmp r3, #0 + 800ec8a: d101 bne.n 800ec90 + 800ec8c: 2314 movs r3, #20 + 800ec8e: e020 b.n 800ecd2 + 800ec90: 2329 movs r3, #41 @ 0x29 + 800ec92: e01e b.n 800ecd2 + 800ec94: 687b ldr r3, [r7, #4] + 800ec96: 681b ldr r3, [r3, #0] + 800ec98: 6919 ldr r1, [r3, #16] + 800ec9a: 4b3d ldr r3, [pc, #244] @ (800ed90 ) + 800ec9c: 400b ands r3, r1 + 800ec9e: 2b00 cmp r3, #0 + 800eca0: d106 bne.n 800ecb0 + 800eca2: 687b ldr r3, [r7, #4] + 800eca4: 681b ldr r3, [r3, #0] + 800eca6: 68d9 ldr r1, [r3, #12] + 800eca8: 4b3a ldr r3, [pc, #232] @ (800ed94 ) + 800ecaa: 400b ands r3, r1 + 800ecac: 2b00 cmp r3, #0 + 800ecae: d00d beq.n 800eccc + 800ecb0: 687b ldr r3, [r7, #4] + 800ecb2: 681b ldr r3, [r3, #0] + 800ecb4: 6919 ldr r1, [r3, #16] + 800ecb6: 4b38 ldr r3, [pc, #224] @ (800ed98 ) + 800ecb8: 400b ands r3, r1 + 800ecba: 2b00 cmp r3, #0 + 800ecbc: d108 bne.n 800ecd0 + 800ecbe: 687b ldr r3, [r7, #4] + 800ecc0: 681b ldr r3, [r3, #0] + 800ecc2: 68d9 ldr r1, [r3, #12] + 800ecc4: 4b34 ldr r3, [pc, #208] @ (800ed98 ) + 800ecc6: 400b ands r3, r1 + 800ecc8: 2b00 cmp r3, #0 + 800ecca: d101 bne.n 800ecd0 + 800eccc: 2354 movs r3, #84 @ 0x54 + 800ecce: e000 b.n 800ecd2 + 800ecd0: 23fc movs r3, #252 @ 0xfc + Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock + 800ecd2: fb02 f303 mul.w r3, r2, r3 + 800ecd6: 613b str r3, [r7, #16] + + while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + 800ecd8: e021 b.n 800ed1e + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + 800ecda: 683b ldr r3, [r7, #0] + 800ecdc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800ece0: d01a beq.n 800ed18 + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + 800ece2: 683b ldr r3, [r7, #0] + 800ece4: 2b00 cmp r3, #0 + 800ece6: d007 beq.n 800ecf8 + 800ece8: f7ff fd72 bl 800e7d0 + 800ecec: 4602 mov r2, r0 + 800ecee: 697b ldr r3, [r7, #20] + 800ecf0: 1ad3 subs r3, r2, r3 + 800ecf2: 683a ldr r2, [r7, #0] + 800ecf4: 429a cmp r2, r3 + 800ecf6: d20f bcs.n 800ed18 + { + /* New check to avoid false timeout detection in case of preemption */ + if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + 800ecf8: 68fb ldr r3, [r7, #12] + 800ecfa: 693a ldr r2, [r7, #16] + 800ecfc: 429a cmp r2, r3 + 800ecfe: d90b bls.n 800ed18 + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + 800ed00: 687b ldr r3, [r7, #4] + 800ed02: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ed04: f043 0204 orr.w r2, r3, #4 + 800ed08: 687b ldr r3, [r7, #4] + 800ed0a: 629a str r2, [r3, #40] @ 0x28 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800ed0c: 687b ldr r3, [r7, #4] + 800ed0e: 2200 movs r2, #0 + 800ed10: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_TIMEOUT; + 800ed14: 2303 movs r3, #3 + 800ed16: e030 b.n 800ed7a + } + } + } + Conversion_Timeout_CPU_cycles ++; + 800ed18: 68fb ldr r3, [r7, #12] + 800ed1a: 3301 adds r3, #1 + 800ed1c: 60fb str r3, [r7, #12] + while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + 800ed1e: 68fb ldr r3, [r7, #12] + 800ed20: 693a ldr r2, [r7, #16] + 800ed22: 429a cmp r2, r3 + 800ed24: d8d9 bhi.n 800ecda + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + 800ed26: 687b ldr r3, [r7, #4] + 800ed28: 681b ldr r3, [r3, #0] + 800ed2a: f06f 0212 mvn.w r2, #18 + 800ed2e: 601a str r2, [r3, #0] + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 800ed30: 687b ldr r3, [r7, #4] + 800ed32: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ed34: f443 7200 orr.w r2, r3, #512 @ 0x200 + 800ed38: 687b ldr r3, [r7, #4] + 800ed3a: 629a str r2, [r3, #40] @ 0x28 + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* (several ranks selected), end of conversion flag is raised */ + /* at the end of the sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800ed3c: 687b ldr r3, [r7, #4] + 800ed3e: 681b ldr r3, [r3, #0] + 800ed40: 689b ldr r3, [r3, #8] + 800ed42: f403 2360 and.w r3, r3, #917504 @ 0xe0000 + 800ed46: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 + 800ed4a: d115 bne.n 800ed78 + (hadc->Init.ContinuousConvMode == DISABLE) ) + 800ed4c: 687b ldr r3, [r7, #4] + 800ed4e: 7b1b ldrb r3, [r3, #12] + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800ed50: 2b00 cmp r3, #0 + 800ed52: d111 bne.n 800ed78 + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + 800ed54: 687b ldr r3, [r7, #4] + 800ed56: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ed58: f423 7280 bic.w r2, r3, #256 @ 0x100 + 800ed5c: 687b ldr r3, [r7, #4] + 800ed5e: 629a str r2, [r3, #40] @ 0x28 + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 800ed60: 687b ldr r3, [r7, #4] + 800ed62: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ed64: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 800ed68: 2b00 cmp r3, #0 + 800ed6a: d105 bne.n 800ed78 + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 800ed6c: 687b ldr r3, [r7, #4] + 800ed6e: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ed70: f043 0201 orr.w r2, r3, #1 + 800ed74: 687b ldr r3, [r7, #4] + 800ed76: 629a str r2, [r3, #40] @ 0x28 + } + } + + /* Return ADC state */ + return HAL_OK; + 800ed78: 2300 movs r3, #0 +} + 800ed7a: 4618 mov r0, r3 + 800ed7c: 371c adds r7, #28 + 800ed7e: 46bd mov sp, r7 + 800ed80: bd90 pop {r4, r7, pc} + 800ed82: bf00 nop + 800ed84: 2000006c .word 0x2000006c + 800ed88: 24924924 .word 0x24924924 + 800ed8c: 00924924 .word 0x00924924 + 800ed90: 12492492 .word 0x12492492 + 800ed94: 00492492 .word 0x00492492 + 800ed98: 00249249 .word 0x00249249 + +0800ed9c : + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc: ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + 800ed9c: b480 push {r7} + 800ed9e: b083 sub sp, #12 + 800eda0: af00 add r7, sp, #0 + 800eda2: 6078 str r0, [r7, #4] + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; + 800eda4: 687b ldr r3, [r7, #4] + 800eda6: 681b ldr r3, [r3, #0] + 800eda8: 6cdb ldr r3, [r3, #76] @ 0x4c +} + 800edaa: 4618 mov r0, r3 + 800edac: 370c adds r7, #12 + 800edae: 46bd mov sp, r7 + 800edb0: bc80 pop {r7} + 800edb2: 4770 bx lr + +0800edb4 : + * @param hadc: ADC handle + * @param sConfig: Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + 800edb4: b480 push {r7} + 800edb6: b085 sub sp, #20 + 800edb8: af00 add r7, sp, #0 + 800edba: 6078 str r0, [r7, #4] + 800edbc: 6039 str r1, [r7, #0] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 800edbe: 2300 movs r3, #0 + 800edc0: 73fb strb r3, [r7, #15] + __IO uint32_t wait_loop_index = 0U; + 800edc2: 2300 movs r3, #0 + 800edc4: 60bb str r3, [r7, #8] + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + 800edc6: 687b ldr r3, [r7, #4] + 800edc8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800edcc: 2b01 cmp r3, #1 + 800edce: d101 bne.n 800edd4 + 800edd0: 2302 movs r3, #2 + 800edd2: e0dc b.n 800ef8e + 800edd4: 687b ldr r3, [r7, #4] + 800edd6: 2201 movs r2, #1 + 800edd8: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + + /* Regular sequence configuration */ + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7U) + 800eddc: 683b ldr r3, [r7, #0] + 800edde: 685b ldr r3, [r3, #4] + 800ede0: 2b06 cmp r3, #6 + 800ede2: d81c bhi.n 800ee1e + { + MODIFY_REG(hadc->Instance->SQR3 , + 800ede4: 687b ldr r3, [r7, #4] + 800ede6: 681b ldr r3, [r3, #0] + 800ede8: 6b59 ldr r1, [r3, #52] @ 0x34 + 800edea: 683b ldr r3, [r7, #0] + 800edec: 685a ldr r2, [r3, #4] + 800edee: 4613 mov r3, r2 + 800edf0: 009b lsls r3, r3, #2 + 800edf2: 4413 add r3, r2 + 800edf4: 3b05 subs r3, #5 + 800edf6: 221f movs r2, #31 + 800edf8: fa02 f303 lsl.w r3, r2, r3 + 800edfc: 43db mvns r3, r3 + 800edfe: 4019 ands r1, r3 + 800ee00: 683b ldr r3, [r7, #0] + 800ee02: 6818 ldr r0, [r3, #0] + 800ee04: 683b ldr r3, [r7, #0] + 800ee06: 685a ldr r2, [r3, #4] + 800ee08: 4613 mov r3, r2 + 800ee0a: 009b lsls r3, r3, #2 + 800ee0c: 4413 add r3, r2 + 800ee0e: 3b05 subs r3, #5 + 800ee10: fa00 f203 lsl.w r2, r0, r3 + 800ee14: 687b ldr r3, [r7, #4] + 800ee16: 681b ldr r3, [r3, #0] + 800ee18: 430a orrs r2, r1 + 800ee1a: 635a str r2, [r3, #52] @ 0x34 + 800ee1c: e03c b.n 800ee98 + ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , + ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13U) + 800ee1e: 683b ldr r3, [r7, #0] + 800ee20: 685b ldr r3, [r3, #4] + 800ee22: 2b0c cmp r3, #12 + 800ee24: d81c bhi.n 800ee60 + { + MODIFY_REG(hadc->Instance->SQR2 , + 800ee26: 687b ldr r3, [r7, #4] + 800ee28: 681b ldr r3, [r3, #0] + 800ee2a: 6b19 ldr r1, [r3, #48] @ 0x30 + 800ee2c: 683b ldr r3, [r7, #0] + 800ee2e: 685a ldr r2, [r3, #4] + 800ee30: 4613 mov r3, r2 + 800ee32: 009b lsls r3, r3, #2 + 800ee34: 4413 add r3, r2 + 800ee36: 3b23 subs r3, #35 @ 0x23 + 800ee38: 221f movs r2, #31 + 800ee3a: fa02 f303 lsl.w r3, r2, r3 + 800ee3e: 43db mvns r3, r3 + 800ee40: 4019 ands r1, r3 + 800ee42: 683b ldr r3, [r7, #0] + 800ee44: 6818 ldr r0, [r3, #0] + 800ee46: 683b ldr r3, [r7, #0] + 800ee48: 685a ldr r2, [r3, #4] + 800ee4a: 4613 mov r3, r2 + 800ee4c: 009b lsls r3, r3, #2 + 800ee4e: 4413 add r3, r2 + 800ee50: 3b23 subs r3, #35 @ 0x23 + 800ee52: fa00 f203 lsl.w r2, r0, r3 + 800ee56: 687b ldr r3, [r7, #4] + 800ee58: 681b ldr r3, [r3, #0] + 800ee5a: 430a orrs r2, r1 + 800ee5c: 631a str r2, [r3, #48] @ 0x30 + 800ee5e: e01b b.n 800ee98 + ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 13 to 16 */ + else + { + MODIFY_REG(hadc->Instance->SQR1 , + 800ee60: 687b ldr r3, [r7, #4] + 800ee62: 681b ldr r3, [r3, #0] + 800ee64: 6ad9 ldr r1, [r3, #44] @ 0x2c + 800ee66: 683b ldr r3, [r7, #0] + 800ee68: 685a ldr r2, [r3, #4] + 800ee6a: 4613 mov r3, r2 + 800ee6c: 009b lsls r3, r3, #2 + 800ee6e: 4413 add r3, r2 + 800ee70: 3b41 subs r3, #65 @ 0x41 + 800ee72: 221f movs r2, #31 + 800ee74: fa02 f303 lsl.w r3, r2, r3 + 800ee78: 43db mvns r3, r3 + 800ee7a: 4019 ands r1, r3 + 800ee7c: 683b ldr r3, [r7, #0] + 800ee7e: 6818 ldr r0, [r3, #0] + 800ee80: 683b ldr r3, [r7, #0] + 800ee82: 685a ldr r2, [r3, #4] + 800ee84: 4613 mov r3, r2 + 800ee86: 009b lsls r3, r3, #2 + 800ee88: 4413 add r3, r2 + 800ee8a: 3b41 subs r3, #65 @ 0x41 + 800ee8c: fa00 f203 lsl.w r2, r0, r3 + 800ee90: 687b ldr r3, [r7, #4] + 800ee92: 681b ldr r3, [r3, #0] + 800ee94: 430a orrs r2, r1 + 800ee96: 62da str r2, [r3, #44] @ 0x2c + } + + + /* Channel sampling time configuration */ + /* For channels 10 to 17 */ + if (sConfig->Channel >= ADC_CHANNEL_10) + 800ee98: 683b ldr r3, [r7, #0] + 800ee9a: 681b ldr r3, [r3, #0] + 800ee9c: 2b09 cmp r3, #9 + 800ee9e: d91c bls.n 800eeda + { + MODIFY_REG(hadc->Instance->SMPR1 , + 800eea0: 687b ldr r3, [r7, #4] + 800eea2: 681b ldr r3, [r3, #0] + 800eea4: 68d9 ldr r1, [r3, #12] + 800eea6: 683b ldr r3, [r7, #0] + 800eea8: 681a ldr r2, [r3, #0] + 800eeaa: 4613 mov r3, r2 + 800eeac: 005b lsls r3, r3, #1 + 800eeae: 4413 add r3, r2 + 800eeb0: 3b1e subs r3, #30 + 800eeb2: 2207 movs r2, #7 + 800eeb4: fa02 f303 lsl.w r3, r2, r3 + 800eeb8: 43db mvns r3, r3 + 800eeba: 4019 ands r1, r3 + 800eebc: 683b ldr r3, [r7, #0] + 800eebe: 6898 ldr r0, [r3, #8] + 800eec0: 683b ldr r3, [r7, #0] + 800eec2: 681a ldr r2, [r3, #0] + 800eec4: 4613 mov r3, r2 + 800eec6: 005b lsls r3, r3, #1 + 800eec8: 4413 add r3, r2 + 800eeca: 3b1e subs r3, #30 + 800eecc: fa00 f203 lsl.w r2, r0, r3 + 800eed0: 687b ldr r3, [r7, #4] + 800eed2: 681b ldr r3, [r3, #0] + 800eed4: 430a orrs r2, r1 + 800eed6: 60da str r2, [r3, #12] + 800eed8: e019 b.n 800ef0e + ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , + ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); + } + else /* For channels 0 to 9 */ + { + MODIFY_REG(hadc->Instance->SMPR2 , + 800eeda: 687b ldr r3, [r7, #4] + 800eedc: 681b ldr r3, [r3, #0] + 800eede: 6919 ldr r1, [r3, #16] + 800eee0: 683b ldr r3, [r7, #0] + 800eee2: 681a ldr r2, [r3, #0] + 800eee4: 4613 mov r3, r2 + 800eee6: 005b lsls r3, r3, #1 + 800eee8: 4413 add r3, r2 + 800eeea: 2207 movs r2, #7 + 800eeec: fa02 f303 lsl.w r3, r2, r3 + 800eef0: 43db mvns r3, r3 + 800eef2: 4019 ands r1, r3 + 800eef4: 683b ldr r3, [r7, #0] + 800eef6: 6898 ldr r0, [r3, #8] + 800eef8: 683b ldr r3, [r7, #0] + 800eefa: 681a ldr r2, [r3, #0] + 800eefc: 4613 mov r3, r2 + 800eefe: 005b lsls r3, r3, #1 + 800ef00: 4413 add r3, r2 + 800ef02: fa00 f203 lsl.w r2, r0, r3 + 800ef06: 687b ldr r3, [r7, #4] + 800ef08: 681b ldr r3, [r3, #0] + 800ef0a: 430a orrs r2, r1 + 800ef0c: 611a str r2, [r3, #16] + ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); + } + + /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || + 800ef0e: 683b ldr r3, [r7, #0] + 800ef10: 681b ldr r3, [r3, #0] + 800ef12: 2b10 cmp r3, #16 + 800ef14: d003 beq.n 800ef1e + (sConfig->Channel == ADC_CHANNEL_VREFINT) ) + 800ef16: 683b ldr r3, [r7, #0] + 800ef18: 681b ldr r3, [r3, #0] + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || + 800ef1a: 2b11 cmp r3, #17 + 800ef1c: d132 bne.n 800ef84 + { + /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ + /* measurement channels (VrefInt/TempSensor). If these channels are */ + /* intended to be set on other ADC instances, an error is reported. */ + if (hadc->Instance == ADC1) + 800ef1e: 687b ldr r3, [r7, #4] + 800ef20: 681b ldr r3, [r3, #0] + 800ef22: 4a1d ldr r2, [pc, #116] @ (800ef98 ) + 800ef24: 4293 cmp r3, r2 + 800ef26: d125 bne.n 800ef74 + { + if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) + 800ef28: 687b ldr r3, [r7, #4] + 800ef2a: 681b ldr r3, [r3, #0] + 800ef2c: 689b ldr r3, [r3, #8] + 800ef2e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 800ef32: 2b00 cmp r3, #0 + 800ef34: d126 bne.n 800ef84 + { + SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); + 800ef36: 687b ldr r3, [r7, #4] + 800ef38: 681b ldr r3, [r3, #0] + 800ef3a: 689a ldr r2, [r3, #8] + 800ef3c: 687b ldr r3, [r7, #4] + 800ef3e: 681b ldr r3, [r3, #0] + 800ef40: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 + 800ef44: 609a str r2, [r3, #8] + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 800ef46: 683b ldr r3, [r7, #0] + 800ef48: 681b ldr r3, [r3, #0] + 800ef4a: 2b10 cmp r3, #16 + 800ef4c: d11a bne.n 800ef84 + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + 800ef4e: 4b13 ldr r3, [pc, #76] @ (800ef9c ) + 800ef50: 681b ldr r3, [r3, #0] + 800ef52: 4a13 ldr r2, [pc, #76] @ (800efa0 ) + 800ef54: fba2 2303 umull r2, r3, r2, r3 + 800ef58: 0c9a lsrs r2, r3, #18 + 800ef5a: 4613 mov r3, r2 + 800ef5c: 009b lsls r3, r3, #2 + 800ef5e: 4413 add r3, r2 + 800ef60: 005b lsls r3, r3, #1 + 800ef62: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 800ef64: e002 b.n 800ef6c + { + wait_loop_index--; + 800ef66: 68bb ldr r3, [r7, #8] + 800ef68: 3b01 subs r3, #1 + 800ef6a: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 800ef6c: 68bb ldr r3, [r7, #8] + 800ef6e: 2b00 cmp r3, #0 + 800ef70: d1f9 bne.n 800ef66 + 800ef72: e007 b.n 800ef84 + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 800ef74: 687b ldr r3, [r7, #4] + 800ef76: 6a9b ldr r3, [r3, #40] @ 0x28 + 800ef78: f043 0220 orr.w r2, r3, #32 + 800ef7c: 687b ldr r3, [r7, #4] + 800ef7e: 629a str r2, [r3, #40] @ 0x28 + + tmp_hal_status = HAL_ERROR; + 800ef80: 2301 movs r3, #1 + 800ef82: 73fb strb r3, [r7, #15] + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800ef84: 687b ldr r3, [r7, #4] + 800ef86: 2200 movs r2, #0 + 800ef88: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Return function status */ + return tmp_hal_status; + 800ef8c: 7bfb ldrb r3, [r7, #15] +} + 800ef8e: 4618 mov r0, r3 + 800ef90: 3714 adds r7, #20 + 800ef92: 46bd mov sp, r7 + 800ef94: bc80 pop {r7} + 800ef96: 4770 bx lr + 800ef98: 40012400 .word 0x40012400 + 800ef9c: 2000006c .word 0x2000006c + 800efa0: 431bde83 .word 0x431bde83 + +0800efa4 : + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +{ + 800efa4: b580 push {r7, lr} + 800efa6: b084 sub sp, #16 + 800efa8: af00 add r7, sp, #0 + 800efaa: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800efac: 2300 movs r3, #0 + 800efae: 60fb str r3, [r7, #12] + __IO uint32_t wait_loop_index = 0U; + 800efb0: 2300 movs r3, #0 + 800efb2: 60bb str r3, [r7, #8] + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (ADC_IS_ENABLE(hadc) == RESET) + 800efb4: 687b ldr r3, [r7, #4] + 800efb6: 681b ldr r3, [r3, #0] + 800efb8: 689b ldr r3, [r3, #8] + 800efba: f003 0301 and.w r3, r3, #1 + 800efbe: 2b01 cmp r3, #1 + 800efc0: d040 beq.n 800f044 + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + 800efc2: 687b ldr r3, [r7, #4] + 800efc4: 681b ldr r3, [r3, #0] + 800efc6: 689a ldr r2, [r3, #8] + 800efc8: 687b ldr r3, [r7, #4] + 800efca: 681b ldr r3, [r3, #0] + 800efcc: f042 0201 orr.w r2, r2, #1 + 800efd0: 609a str r2, [r3, #8] + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + 800efd2: 4b1f ldr r3, [pc, #124] @ (800f050 ) + 800efd4: 681b ldr r3, [r3, #0] + 800efd6: 4a1f ldr r2, [pc, #124] @ (800f054 ) + 800efd8: fba2 2303 umull r2, r3, r2, r3 + 800efdc: 0c9b lsrs r3, r3, #18 + 800efde: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 800efe0: e002 b.n 800efe8 + { + wait_loop_index--; + 800efe2: 68bb ldr r3, [r7, #8] + 800efe4: 3b01 subs r3, #1 + 800efe6: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 800efe8: 68bb ldr r3, [r7, #8] + 800efea: 2b00 cmp r3, #0 + 800efec: d1f9 bne.n 800efe2 + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + 800efee: f7ff fbef bl 800e7d0 + 800eff2: 60f8 str r0, [r7, #12] + + /* Wait for ADC effectively enabled */ + while(ADC_IS_ENABLE(hadc) == RESET) + 800eff4: e01f b.n 800f036 + { + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + 800eff6: f7ff fbeb bl 800e7d0 + 800effa: 4602 mov r2, r0 + 800effc: 68fb ldr r3, [r7, #12] + 800effe: 1ad3 subs r3, r2, r3 + 800f000: 2b02 cmp r3, #2 + 800f002: d918 bls.n 800f036 + { + /* New check to avoid false timeout detection in case of preemption */ + if(ADC_IS_ENABLE(hadc) == RESET) + 800f004: 687b ldr r3, [r7, #4] + 800f006: 681b ldr r3, [r3, #0] + 800f008: 689b ldr r3, [r3, #8] + 800f00a: f003 0301 and.w r3, r3, #1 + 800f00e: 2b01 cmp r3, #1 + 800f010: d011 beq.n 800f036 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 800f012: 687b ldr r3, [r7, #4] + 800f014: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f016: f043 0210 orr.w r2, r3, #16 + 800f01a: 687b ldr r3, [r7, #4] + 800f01c: 629a str r2, [r3, #40] @ 0x28 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 800f01e: 687b ldr r3, [r7, #4] + 800f020: 6adb ldr r3, [r3, #44] @ 0x2c + 800f022: f043 0201 orr.w r2, r3, #1 + 800f026: 687b ldr r3, [r7, #4] + 800f028: 62da str r2, [r3, #44] @ 0x2c + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800f02a: 687b ldr r3, [r7, #4] + 800f02c: 2200 movs r2, #0 + 800f02e: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f032: 2301 movs r3, #1 + 800f034: e007 b.n 800f046 + while(ADC_IS_ENABLE(hadc) == RESET) + 800f036: 687b ldr r3, [r7, #4] + 800f038: 681b ldr r3, [r3, #0] + 800f03a: 689b ldr r3, [r3, #8] + 800f03c: f003 0301 and.w r3, r3, #1 + 800f040: 2b01 cmp r3, #1 + 800f042: d1d8 bne.n 800eff6 + } + } + } + + /* Return HAL status */ + return HAL_OK; + 800f044: 2300 movs r3, #0 +} + 800f046: 4618 mov r0, r3 + 800f048: 3710 adds r7, #16 + 800f04a: 46bd mov sp, r7 + 800f04c: bd80 pop {r7, pc} + 800f04e: bf00 nop + 800f050: 2000006c .word 0x2000006c + 800f054: 431bde83 .word 0x431bde83 + +0800f058 : + * stopped to disable the ADC. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) +{ + 800f058: b580 push {r7, lr} + 800f05a: b084 sub sp, #16 + 800f05c: af00 add r7, sp, #0 + 800f05e: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800f060: 2300 movs r3, #0 + 800f062: 60fb str r3, [r7, #12] + + /* Verification if ADC is not already disabled */ + if (ADC_IS_ENABLE(hadc) != RESET) + 800f064: 687b ldr r3, [r7, #4] + 800f066: 681b ldr r3, [r3, #0] + 800f068: 689b ldr r3, [r3, #8] + 800f06a: f003 0301 and.w r3, r3, #1 + 800f06e: 2b01 cmp r3, #1 + 800f070: d12e bne.n 800f0d0 + { + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + 800f072: 687b ldr r3, [r7, #4] + 800f074: 681b ldr r3, [r3, #0] + 800f076: 689a ldr r2, [r3, #8] + 800f078: 687b ldr r3, [r7, #4] + 800f07a: 681b ldr r3, [r3, #0] + 800f07c: f022 0201 bic.w r2, r2, #1 + 800f080: 609a str r2, [r3, #8] + + /* Get tick count */ + tickstart = HAL_GetTick(); + 800f082: f7ff fba5 bl 800e7d0 + 800f086: 60f8 str r0, [r7, #12] + + /* Wait for ADC effectively disabled */ + while(ADC_IS_ENABLE(hadc) != RESET) + 800f088: e01b b.n 800f0c2 + { + if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + 800f08a: f7ff fba1 bl 800e7d0 + 800f08e: 4602 mov r2, r0 + 800f090: 68fb ldr r3, [r7, #12] + 800f092: 1ad3 subs r3, r2, r3 + 800f094: 2b02 cmp r3, #2 + 800f096: d914 bls.n 800f0c2 + { + /* New check to avoid false timeout detection in case of preemption */ + if(ADC_IS_ENABLE(hadc) != RESET) + 800f098: 687b ldr r3, [r7, #4] + 800f09a: 681b ldr r3, [r3, #0] + 800f09c: 689b ldr r3, [r3, #8] + 800f09e: f003 0301 and.w r3, r3, #1 + 800f0a2: 2b01 cmp r3, #1 + 800f0a4: d10d bne.n 800f0c2 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 800f0a6: 687b ldr r3, [r7, #4] + 800f0a8: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f0aa: f043 0210 orr.w r2, r3, #16 + 800f0ae: 687b ldr r3, [r7, #4] + 800f0b0: 629a str r2, [r3, #40] @ 0x28 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 800f0b2: 687b ldr r3, [r7, #4] + 800f0b4: 6adb ldr r3, [r3, #44] @ 0x2c + 800f0b6: f043 0201 orr.w r2, r3, #1 + 800f0ba: 687b ldr r3, [r7, #4] + 800f0bc: 62da str r2, [r3, #44] @ 0x2c + + return HAL_ERROR; + 800f0be: 2301 movs r3, #1 + 800f0c0: e007 b.n 800f0d2 + while(ADC_IS_ENABLE(hadc) != RESET) + 800f0c2: 687b ldr r3, [r7, #4] + 800f0c4: 681b ldr r3, [r3, #0] + 800f0c6: 689b ldr r3, [r3, #8] + 800f0c8: f003 0301 and.w r3, r3, #1 + 800f0cc: 2b01 cmp r3, #1 + 800f0ce: d0dc beq.n 800f08a + } + } + } + + /* Return HAL status */ + return HAL_OK; + 800f0d0: 2300 movs r3, #0 +} + 800f0d2: 4618 mov r0, r3 + 800f0d4: 3710 adds r7, #16 + 800f0d6: 46bd mov sp, r7 + 800f0d8: bd80 pop {r7, pc} + ... + +0800f0dc : + * the completion of this function. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) +{ + 800f0dc: b590 push {r4, r7, lr} + 800f0de: b087 sub sp, #28 + 800f0e0: af00 add r7, sp, #0 + 800f0e2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 800f0e4: 2300 movs r3, #0 + 800f0e6: 75fb strb r3, [r7, #23] + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0U; + 800f0e8: 2300 movs r3, #0 + 800f0ea: 60fb str r3, [r7, #12] + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + 800f0ec: 687b ldr r3, [r7, #4] + 800f0ee: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800f0f2: 2b01 cmp r3, #1 + 800f0f4: d101 bne.n 800f0fa + 800f0f6: 2302 movs r3, #2 + 800f0f8: e097 b.n 800f22a + 800f0fa: 687b ldr r3, [r7, #4] + 800f0fc: 2201 movs r2, #1 + 800f0fe: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* 1. Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + 800f102: 6878 ldr r0, [r7, #4] + 800f104: f7ff ffa8 bl 800f058 + 800f108: 4603 mov r3, r0 + 800f10a: 75fb strb r3, [r7, #23] + + /* 2. Calibration prerequisite delay before starting the calibration. */ + /* - ADC must be enabled for at least two ADC clock cycles */ + tmp_hal_status = ADC_Enable(hadc); + 800f10c: 6878 ldr r0, [r7, #4] + 800f10e: f7ff ff49 bl 800efa4 + 800f112: 4603 mov r3, r0 + 800f114: 75fb strb r3, [r7, #23] + + /* Check if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + 800f116: 7dfb ldrb r3, [r7, #23] + 800f118: 2b00 cmp r3, #0 + 800f11a: f040 8081 bne.w 800f220 + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800f11e: 687b ldr r3, [r7, #4] + 800f120: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f122: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 800f126: f023 0302 bic.w r3, r3, #2 + 800f12a: f043 0202 orr.w r2, r3, #2 + 800f12e: 687b ldr r3, [r7, #4] + 800f130: 629a str r2, [r3, #40] @ 0x28 + + /* Hardware prerequisite: delay before starting the calibration. */ + /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ + /* - Wait for the expected ADC clock cycles delay */ + wait_loop_index = ((SystemCoreClock + / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) + 800f132: 4b40 ldr r3, [pc, #256] @ (800f234 ) + 800f134: 681c ldr r4, [r3, #0] + 800f136: 2002 movs r0, #2 + 800f138: f002 fa84 bl 8011644 + 800f13c: 4603 mov r3, r0 + 800f13e: fbb4 f3f3 udiv r3, r4, r3 + * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); + 800f142: 005b lsls r3, r3, #1 + wait_loop_index = ((SystemCoreClock + 800f144: 60fb str r3, [r7, #12] + + while(wait_loop_index != 0U) + 800f146: e002 b.n 800f14e + { + wait_loop_index--; + 800f148: 68fb ldr r3, [r7, #12] + 800f14a: 3b01 subs r3, #1 + 800f14c: 60fb str r3, [r7, #12] + while(wait_loop_index != 0U) + 800f14e: 68fb ldr r3, [r7, #12] + 800f150: 2b00 cmp r3, #0 + 800f152: d1f9 bne.n 800f148 + } + + /* 3. Resets ADC calibration registers */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); + 800f154: 687b ldr r3, [r7, #4] + 800f156: 681b ldr r3, [r3, #0] + 800f158: 689a ldr r2, [r3, #8] + 800f15a: 687b ldr r3, [r7, #4] + 800f15c: 681b ldr r3, [r3, #0] + 800f15e: f042 0208 orr.w r2, r2, #8 + 800f162: 609a str r2, [r3, #8] + + tickstart = HAL_GetTick(); + 800f164: f7ff fb34 bl 800e7d0 + 800f168: 6138 str r0, [r7, #16] + + /* Wait for calibration reset completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) + 800f16a: e01b b.n 800f1a4 + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + 800f16c: f7ff fb30 bl 800e7d0 + 800f170: 4602 mov r2, r0 + 800f172: 693b ldr r3, [r7, #16] + 800f174: 1ad3 subs r3, r2, r3 + 800f176: 2b0a cmp r3, #10 + 800f178: d914 bls.n 800f1a4 + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) + 800f17a: 687b ldr r3, [r7, #4] + 800f17c: 681b ldr r3, [r3, #0] + 800f17e: 689b ldr r3, [r3, #8] + 800f180: f003 0308 and.w r3, r3, #8 + 800f184: 2b00 cmp r3, #0 + 800f186: d00d beq.n 800f1a4 + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + 800f188: 687b ldr r3, [r7, #4] + 800f18a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f18c: f023 0312 bic.w r3, r3, #18 + 800f190: f043 0210 orr.w r2, r3, #16 + 800f194: 687b ldr r3, [r7, #4] + 800f196: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800f198: 687b ldr r3, [r7, #4] + 800f19a: 2200 movs r2, #0 + 800f19c: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f1a0: 2301 movs r3, #1 + 800f1a2: e042 b.n 800f22a + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) + 800f1a4: 687b ldr r3, [r7, #4] + 800f1a6: 681b ldr r3, [r3, #0] + 800f1a8: 689b ldr r3, [r3, #8] + 800f1aa: f003 0308 and.w r3, r3, #8 + 800f1ae: 2b00 cmp r3, #0 + 800f1b0: d1dc bne.n 800f16c + } + } + } + + /* 4. Start ADC calibration */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); + 800f1b2: 687b ldr r3, [r7, #4] + 800f1b4: 681b ldr r3, [r3, #0] + 800f1b6: 689a ldr r2, [r3, #8] + 800f1b8: 687b ldr r3, [r7, #4] + 800f1ba: 681b ldr r3, [r3, #0] + 800f1bc: f042 0204 orr.w r2, r2, #4 + 800f1c0: 609a str r2, [r3, #8] + + tickstart = HAL_GetTick(); + 800f1c2: f7ff fb05 bl 800e7d0 + 800f1c6: 6138 str r0, [r7, #16] + + /* Wait for calibration completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) + 800f1c8: e01b b.n 800f202 + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + 800f1ca: f7ff fb01 bl 800e7d0 + 800f1ce: 4602 mov r2, r0 + 800f1d0: 693b ldr r3, [r7, #16] + 800f1d2: 1ad3 subs r3, r2, r3 + 800f1d4: 2b0a cmp r3, #10 + 800f1d6: d914 bls.n 800f202 + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) + 800f1d8: 687b ldr r3, [r7, #4] + 800f1da: 681b ldr r3, [r3, #0] + 800f1dc: 689b ldr r3, [r3, #8] + 800f1de: f003 0304 and.w r3, r3, #4 + 800f1e2: 2b00 cmp r3, #0 + 800f1e4: d00d beq.n 800f202 + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + 800f1e6: 687b ldr r3, [r7, #4] + 800f1e8: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f1ea: f023 0312 bic.w r3, r3, #18 + 800f1ee: f043 0210 orr.w r2, r3, #16 + 800f1f2: 687b ldr r3, [r7, #4] + 800f1f4: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800f1f6: 687b ldr r3, [r7, #4] + 800f1f8: 2200 movs r2, #0 + 800f1fa: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f1fe: 2301 movs r3, #1 + 800f200: e013 b.n 800f22a + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) + 800f202: 687b ldr r3, [r7, #4] + 800f204: 681b ldr r3, [r3, #0] + 800f206: 689b ldr r3, [r3, #8] + 800f208: f003 0304 and.w r3, r3, #4 + 800f20c: 2b00 cmp r3, #0 + 800f20e: d1dc bne.n 800f1ca + } + } + } + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800f210: 687b ldr r3, [r7, #4] + 800f212: 6a9b ldr r3, [r3, #40] @ 0x28 + 800f214: f023 0303 bic.w r3, r3, #3 + 800f218: f043 0201 orr.w r2, r3, #1 + 800f21c: 687b ldr r3, [r7, #4] + 800f21e: 629a str r2, [r3, #40] @ 0x28 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800f220: 687b ldr r3, [r7, #4] + 800f222: 2200 movs r2, #0 + 800f224: f883 2024 strb.w r2, [r3, #36] @ 0x24 + + /* Return function status */ + return tmp_hal_status; + 800f228: 7dfb ldrb r3, [r7, #23] +} + 800f22a: 4618 mov r0, r3 + 800f22c: 371c adds r7, #28 + 800f22e: 46bd mov sp, r7 + 800f230: bd90 pop {r4, r7, pc} + 800f232: bf00 nop + 800f234: 2000006c .word 0x2000006c + +0800f238 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + 800f238: b580 push {r7, lr} + 800f23a: b084 sub sp, #16 + 800f23c: af00 add r7, sp, #0 + 800f23e: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + 800f240: 687b ldr r3, [r7, #4] + 800f242: 2b00 cmp r3, #0 + 800f244: d101 bne.n 800f24a + { + return HAL_ERROR; + 800f246: 2301 movs r3, #1 + 800f248: e0ed b.n 800f426 + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + 800f24a: 687b ldr r3, [r7, #4] + 800f24c: f893 3020 ldrb.w r3, [r3, #32] + 800f250: b2db uxtb r3, r3 + 800f252: 2b00 cmp r3, #0 + 800f254: d102 bne.n 800f25c + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + 800f256: 6878 ldr r0, [r7, #4] + 800f258: f7fa fc6e bl 8009b38 + } +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 800f25c: 687b ldr r3, [r7, #4] + 800f25e: 681b ldr r3, [r3, #0] + 800f260: 681a ldr r2, [r3, #0] + 800f262: 687b ldr r3, [r7, #4] + 800f264: 681b ldr r3, [r3, #0] + 800f266: f042 0201 orr.w r2, r2, #1 + 800f26a: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800f26c: f7ff fab0 bl 800e7d0 + 800f270: 60f8 str r0, [r7, #12] + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 800f272: e012 b.n 800f29a + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800f274: f7ff faac bl 800e7d0 + 800f278: 4602 mov r2, r0 + 800f27a: 68fb ldr r3, [r7, #12] + 800f27c: 1ad3 subs r3, r2, r3 + 800f27e: 2b0a cmp r3, #10 + 800f280: d90b bls.n 800f29a + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800f282: 687b ldr r3, [r7, #4] + 800f284: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f286: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 800f28a: 687b ldr r3, [r7, #4] + 800f28c: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800f28e: 687b ldr r3, [r7, #4] + 800f290: 2205 movs r2, #5 + 800f292: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800f296: 2301 movs r3, #1 + 800f298: e0c5 b.n 800f426 + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 800f29a: 687b ldr r3, [r7, #4] + 800f29c: 681b ldr r3, [r3, #0] + 800f29e: 685b ldr r3, [r3, #4] + 800f2a0: f003 0301 and.w r3, r3, #1 + 800f2a4: 2b00 cmp r3, #0 + 800f2a6: d0e5 beq.n 800f274 + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 800f2a8: 687b ldr r3, [r7, #4] + 800f2aa: 681b ldr r3, [r3, #0] + 800f2ac: 681a ldr r2, [r3, #0] + 800f2ae: 687b ldr r3, [r7, #4] + 800f2b0: 681b ldr r3, [r3, #0] + 800f2b2: f022 0202 bic.w r2, r2, #2 + 800f2b6: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800f2b8: f7ff fa8a bl 800e7d0 + 800f2bc: 60f8 str r0, [r7, #12] + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 800f2be: e012 b.n 800f2e6 + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800f2c0: f7ff fa86 bl 800e7d0 + 800f2c4: 4602 mov r2, r0 + 800f2c6: 68fb ldr r3, [r7, #12] + 800f2c8: 1ad3 subs r3, r2, r3 + 800f2ca: 2b0a cmp r3, #10 + 800f2cc: d90b bls.n 800f2e6 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800f2ce: 687b ldr r3, [r7, #4] + 800f2d0: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f2d2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 800f2d6: 687b ldr r3, [r7, #4] + 800f2d8: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800f2da: 687b ldr r3, [r7, #4] + 800f2dc: 2205 movs r2, #5 + 800f2de: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800f2e2: 2301 movs r3, #1 + 800f2e4: e09f b.n 800f426 + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 800f2e6: 687b ldr r3, [r7, #4] + 800f2e8: 681b ldr r3, [r3, #0] + 800f2ea: 685b ldr r3, [r3, #4] + 800f2ec: f003 0302 and.w r3, r3, #2 + 800f2f0: 2b00 cmp r3, #0 + 800f2f2: d1e5 bne.n 800f2c0 + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + 800f2f4: 687b ldr r3, [r7, #4] + 800f2f6: 7e1b ldrb r3, [r3, #24] + 800f2f8: 2b01 cmp r3, #1 + 800f2fa: d108 bne.n 800f30e + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 800f2fc: 687b ldr r3, [r7, #4] + 800f2fe: 681b ldr r3, [r3, #0] + 800f300: 681a ldr r2, [r3, #0] + 800f302: 687b ldr r3, [r7, #4] + 800f304: 681b ldr r3, [r3, #0] + 800f306: f042 0280 orr.w r2, r2, #128 @ 0x80 + 800f30a: 601a str r2, [r3, #0] + 800f30c: e007 b.n 800f31e + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 800f30e: 687b ldr r3, [r7, #4] + 800f310: 681b ldr r3, [r3, #0] + 800f312: 681a ldr r2, [r3, #0] + 800f314: 687b ldr r3, [r7, #4] + 800f316: 681b ldr r3, [r3, #0] + 800f318: f022 0280 bic.w r2, r2, #128 @ 0x80 + 800f31c: 601a str r2, [r3, #0] + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + 800f31e: 687b ldr r3, [r7, #4] + 800f320: 7e5b ldrb r3, [r3, #25] + 800f322: 2b01 cmp r3, #1 + 800f324: d108 bne.n 800f338 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 800f326: 687b ldr r3, [r7, #4] + 800f328: 681b ldr r3, [r3, #0] + 800f32a: 681a ldr r2, [r3, #0] + 800f32c: 687b ldr r3, [r7, #4] + 800f32e: 681b ldr r3, [r3, #0] + 800f330: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800f334: 601a str r2, [r3, #0] + 800f336: e007 b.n 800f348 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 800f338: 687b ldr r3, [r7, #4] + 800f33a: 681b ldr r3, [r3, #0] + 800f33c: 681a ldr r2, [r3, #0] + 800f33e: 687b ldr r3, [r7, #4] + 800f340: 681b ldr r3, [r3, #0] + 800f342: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800f346: 601a str r2, [r3, #0] + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + 800f348: 687b ldr r3, [r7, #4] + 800f34a: 7e9b ldrb r3, [r3, #26] + 800f34c: 2b01 cmp r3, #1 + 800f34e: d108 bne.n 800f362 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 800f350: 687b ldr r3, [r7, #4] + 800f352: 681b ldr r3, [r3, #0] + 800f354: 681a ldr r2, [r3, #0] + 800f356: 687b ldr r3, [r7, #4] + 800f358: 681b ldr r3, [r3, #0] + 800f35a: f042 0220 orr.w r2, r2, #32 + 800f35e: 601a str r2, [r3, #0] + 800f360: e007 b.n 800f372 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 800f362: 687b ldr r3, [r7, #4] + 800f364: 681b ldr r3, [r3, #0] + 800f366: 681a ldr r2, [r3, #0] + 800f368: 687b ldr r3, [r7, #4] + 800f36a: 681b ldr r3, [r3, #0] + 800f36c: f022 0220 bic.w r2, r2, #32 + 800f370: 601a str r2, [r3, #0] + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + 800f372: 687b ldr r3, [r7, #4] + 800f374: 7edb ldrb r3, [r3, #27] + 800f376: 2b01 cmp r3, #1 + 800f378: d108 bne.n 800f38c + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 800f37a: 687b ldr r3, [r7, #4] + 800f37c: 681b ldr r3, [r3, #0] + 800f37e: 681a ldr r2, [r3, #0] + 800f380: 687b ldr r3, [r7, #4] + 800f382: 681b ldr r3, [r3, #0] + 800f384: f022 0210 bic.w r2, r2, #16 + 800f388: 601a str r2, [r3, #0] + 800f38a: e007 b.n 800f39c + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 800f38c: 687b ldr r3, [r7, #4] + 800f38e: 681b ldr r3, [r3, #0] + 800f390: 681a ldr r2, [r3, #0] + 800f392: 687b ldr r3, [r7, #4] + 800f394: 681b ldr r3, [r3, #0] + 800f396: f042 0210 orr.w r2, r2, #16 + 800f39a: 601a str r2, [r3, #0] + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + 800f39c: 687b ldr r3, [r7, #4] + 800f39e: 7f1b ldrb r3, [r3, #28] + 800f3a0: 2b01 cmp r3, #1 + 800f3a2: d108 bne.n 800f3b6 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 800f3a4: 687b ldr r3, [r7, #4] + 800f3a6: 681b ldr r3, [r3, #0] + 800f3a8: 681a ldr r2, [r3, #0] + 800f3aa: 687b ldr r3, [r7, #4] + 800f3ac: 681b ldr r3, [r3, #0] + 800f3ae: f042 0208 orr.w r2, r2, #8 + 800f3b2: 601a str r2, [r3, #0] + 800f3b4: e007 b.n 800f3c6 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 800f3b6: 687b ldr r3, [r7, #4] + 800f3b8: 681b ldr r3, [r3, #0] + 800f3ba: 681a ldr r2, [r3, #0] + 800f3bc: 687b ldr r3, [r7, #4] + 800f3be: 681b ldr r3, [r3, #0] + 800f3c0: f022 0208 bic.w r2, r2, #8 + 800f3c4: 601a str r2, [r3, #0] + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + 800f3c6: 687b ldr r3, [r7, #4] + 800f3c8: 7f5b ldrb r3, [r3, #29] + 800f3ca: 2b01 cmp r3, #1 + 800f3cc: d108 bne.n 800f3e0 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800f3ce: 687b ldr r3, [r7, #4] + 800f3d0: 681b ldr r3, [r3, #0] + 800f3d2: 681a ldr r2, [r3, #0] + 800f3d4: 687b ldr r3, [r7, #4] + 800f3d6: 681b ldr r3, [r3, #0] + 800f3d8: f042 0204 orr.w r2, r2, #4 + 800f3dc: 601a str r2, [r3, #0] + 800f3de: e007 b.n 800f3f0 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800f3e0: 687b ldr r3, [r7, #4] + 800f3e2: 681b ldr r3, [r3, #0] + 800f3e4: 681a ldr r2, [r3, #0] + 800f3e6: 687b ldr r3, [r7, #4] + 800f3e8: 681b ldr r3, [r3, #0] + 800f3ea: f022 0204 bic.w r2, r2, #4 + 800f3ee: 601a str r2, [r3, #0] + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + 800f3f0: 687b ldr r3, [r7, #4] + 800f3f2: 689a ldr r2, [r3, #8] + 800f3f4: 687b ldr r3, [r7, #4] + 800f3f6: 68db ldr r3, [r3, #12] + 800f3f8: 431a orrs r2, r3 + 800f3fa: 687b ldr r3, [r7, #4] + 800f3fc: 691b ldr r3, [r3, #16] + 800f3fe: 431a orrs r2, r3 + 800f400: 687b ldr r3, [r7, #4] + 800f402: 695b ldr r3, [r3, #20] + 800f404: ea42 0103 orr.w r1, r2, r3 + 800f408: 687b ldr r3, [r7, #4] + 800f40a: 685b ldr r3, [r3, #4] + 800f40c: 1e5a subs r2, r3, #1 + 800f40e: 687b ldr r3, [r7, #4] + 800f410: 681b ldr r3, [r3, #0] + 800f412: 430a orrs r2, r1 + 800f414: 61da str r2, [r3, #28] + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 800f416: 687b ldr r3, [r7, #4] + 800f418: 2200 movs r2, #0 + 800f41a: 625a str r2, [r3, #36] @ 0x24 + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + 800f41c: 687b ldr r3, [r7, #4] + 800f41e: 2201 movs r2, #1 + 800f420: f883 2020 strb.w r2, [r3, #32] + + /* Return function status */ + return HAL_OK; + 800f424: 2300 movs r3, #0 +} + 800f426: 4618 mov r0, r3 + 800f428: 3710 adds r7, #16 + 800f42a: 46bd mov sp, r7 + 800f42c: bd80 pop {r7, pc} + ... + +0800f430 : + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) +{ + 800f430: b480 push {r7} + 800f432: b087 sub sp, #28 + 800f434: af00 add r7, sp, #0 + 800f436: 6078 str r0, [r7, #4] + 800f438: 6039 str r1, [r7, #0] + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + 800f43a: 687b ldr r3, [r7, #4] + 800f43c: 681b ldr r3, [r3, #0] + 800f43e: 617b str r3, [r7, #20] + HAL_CAN_StateTypeDef state = hcan->State; + 800f440: 687b ldr r3, [r7, #4] + 800f442: f893 3020 ldrb.w r3, [r3, #32] + 800f446: 74fb strb r3, [r7, #19] + + if ((state == HAL_CAN_STATE_READY) || + 800f448: 7cfb ldrb r3, [r7, #19] + 800f44a: 2b01 cmp r3, #1 + 800f44c: d003 beq.n 800f456 + 800f44e: 7cfb ldrb r3, [r7, #19] + 800f450: 2b02 cmp r3, #2 + 800f452: f040 80be bne.w 800f5d2 + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + 800f456: 4b65 ldr r3, [pc, #404] @ (800f5ec ) + 800f458: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif /* CAN3 */ + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + 800f45a: 697b ldr r3, [r7, #20] + 800f45c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 800f460: f043 0201 orr.w r2, r3, #1 + 800f464: 697b ldr r3, [r7, #20] + 800f466: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + 800f46a: 697b ldr r3, [r7, #20] + 800f46c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 800f470: f423 527c bic.w r2, r3, #16128 @ 0x3f00 + 800f474: 697b ldr r3, [r7, #20] + 800f476: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + 800f47a: 697b ldr r3, [r7, #20] + 800f47c: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 + 800f480: 683b ldr r3, [r7, #0] + 800f482: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f484: 021b lsls r3, r3, #8 + 800f486: 431a orrs r2, r3 + 800f488: 697b ldr r3, [r7, #20] + 800f48a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + +#endif /* CAN3 */ + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + 800f48e: 683b ldr r3, [r7, #0] + 800f490: 695b ldr r3, [r3, #20] + 800f492: f003 031f and.w r3, r3, #31 + 800f496: 2201 movs r2, #1 + 800f498: fa02 f303 lsl.w r3, r2, r3 + 800f49c: 60fb str r3, [r7, #12] + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + 800f49e: 697b ldr r3, [r7, #20] + 800f4a0: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 800f4a4: 68fb ldr r3, [r7, #12] + 800f4a6: 43db mvns r3, r3 + 800f4a8: 401a ands r2, r3 + 800f4aa: 697b ldr r3, [r7, #20] + 800f4ac: f8c3 221c str.w r2, [r3, #540] @ 0x21c + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + 800f4b0: 683b ldr r3, [r7, #0] + 800f4b2: 69db ldr r3, [r3, #28] + 800f4b4: 2b00 cmp r3, #0 + 800f4b6: d123 bne.n 800f500 + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + 800f4b8: 697b ldr r3, [r7, #20] + 800f4ba: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 800f4be: 68fb ldr r3, [r7, #12] + 800f4c0: 43db mvns r3, r3 + 800f4c2: 401a ands r2, r3 + 800f4c4: 697b ldr r3, [r7, #20] + 800f4c6: f8c3 220c str.w r2, [r3, #524] @ 0x20c + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 800f4ca: 683b ldr r3, [r7, #0] + 800f4cc: 68db ldr r3, [r3, #12] + 800f4ce: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 800f4d0: 683b ldr r3, [r7, #0] + 800f4d2: 685b ldr r3, [r3, #4] + 800f4d4: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800f4d6: 683a ldr r2, [r7, #0] + 800f4d8: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 800f4da: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800f4dc: 697b ldr r3, [r7, #20] + 800f4de: 3248 adds r2, #72 @ 0x48 + 800f4e0: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 800f4e4: 683b ldr r3, [r7, #0] + 800f4e6: 689b ldr r3, [r3, #8] + 800f4e8: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 800f4ea: 683b ldr r3, [r7, #0] + 800f4ec: 681b ldr r3, [r3, #0] + 800f4ee: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 800f4f0: 683b ldr r3, [r7, #0] + 800f4f2: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 800f4f4: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 800f4f6: 6979 ldr r1, [r7, #20] + 800f4f8: 3348 adds r3, #72 @ 0x48 + 800f4fa: 00db lsls r3, r3, #3 + 800f4fc: 440b add r3, r1 + 800f4fe: 605a str r2, [r3, #4] + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + 800f500: 683b ldr r3, [r7, #0] + 800f502: 69db ldr r3, [r3, #28] + 800f504: 2b01 cmp r3, #1 + 800f506: d122 bne.n 800f54e + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + 800f508: 697b ldr r3, [r7, #20] + 800f50a: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c + 800f50e: 68fb ldr r3, [r7, #12] + 800f510: 431a orrs r2, r3 + 800f512: 697b ldr r3, [r7, #20] + 800f514: f8c3 220c str.w r2, [r3, #524] @ 0x20c + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 800f518: 683b ldr r3, [r7, #0] + 800f51a: 681b ldr r3, [r3, #0] + 800f51c: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 800f51e: 683b ldr r3, [r7, #0] + 800f520: 685b ldr r3, [r3, #4] + 800f522: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800f524: 683a ldr r2, [r7, #0] + 800f526: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 800f528: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800f52a: 697b ldr r3, [r7, #20] + 800f52c: 3248 adds r2, #72 @ 0x48 + 800f52e: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 800f532: 683b ldr r3, [r7, #0] + 800f534: 689b ldr r3, [r3, #8] + 800f536: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 800f538: 683b ldr r3, [r7, #0] + 800f53a: 68db ldr r3, [r3, #12] + 800f53c: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 800f53e: 683b ldr r3, [r7, #0] + 800f540: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 800f542: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 800f544: 6979 ldr r1, [r7, #20] + 800f546: 3348 adds r3, #72 @ 0x48 + 800f548: 00db lsls r3, r3, #3 + 800f54a: 440b add r3, r1 + 800f54c: 605a str r2, [r3, #4] + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + 800f54e: 683b ldr r3, [r7, #0] + 800f550: 699b ldr r3, [r3, #24] + 800f552: 2b00 cmp r3, #0 + 800f554: d109 bne.n 800f56a + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + 800f556: 697b ldr r3, [r7, #20] + 800f558: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 800f55c: 68fb ldr r3, [r7, #12] + 800f55e: 43db mvns r3, r3 + 800f560: 401a ands r2, r3 + 800f562: 697b ldr r3, [r7, #20] + 800f564: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + 800f568: e007 b.n 800f57a + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + 800f56a: 697b ldr r3, [r7, #20] + 800f56c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 + 800f570: 68fb ldr r3, [r7, #12] + 800f572: 431a orrs r2, r3 + 800f574: 697b ldr r3, [r7, #20] + 800f576: f8c3 2204 str.w r2, [r3, #516] @ 0x204 + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + 800f57a: 683b ldr r3, [r7, #0] + 800f57c: 691b ldr r3, [r3, #16] + 800f57e: 2b00 cmp r3, #0 + 800f580: d109 bne.n 800f596 + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + 800f582: 697b ldr r3, [r7, #20] + 800f584: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 800f588: 68fb ldr r3, [r7, #12] + 800f58a: 43db mvns r3, r3 + 800f58c: 401a ands r2, r3 + 800f58e: 697b ldr r3, [r7, #20] + 800f590: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + 800f594: e007 b.n 800f5a6 + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + 800f596: 697b ldr r3, [r7, #20] + 800f598: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 + 800f59c: 68fb ldr r3, [r7, #12] + 800f59e: 431a orrs r2, r3 + 800f5a0: 697b ldr r3, [r7, #20] + 800f5a2: f8c3 2214 str.w r2, [r3, #532] @ 0x214 + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + 800f5a6: 683b ldr r3, [r7, #0] + 800f5a8: 6a1b ldr r3, [r3, #32] + 800f5aa: 2b01 cmp r3, #1 + 800f5ac: d107 bne.n 800f5be + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + 800f5ae: 697b ldr r3, [r7, #20] + 800f5b0: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c + 800f5b4: 68fb ldr r3, [r7, #12] + 800f5b6: 431a orrs r2, r3 + 800f5b8: 697b ldr r3, [r7, #20] + 800f5ba: f8c3 221c str.w r2, [r3, #540] @ 0x21c + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + 800f5be: 697b ldr r3, [r7, #20] + 800f5c0: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 + 800f5c4: f023 0201 bic.w r2, r3, #1 + 800f5c8: 697b ldr r3, [r7, #20] + 800f5ca: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + + /* Return function status */ + return HAL_OK; + 800f5ce: 2300 movs r3, #0 + 800f5d0: e006 b.n 800f5e0 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 800f5d2: 687b ldr r3, [r7, #4] + 800f5d4: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f5d6: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 800f5da: 687b ldr r3, [r7, #4] + 800f5dc: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f5de: 2301 movs r3, #1 + } +} + 800f5e0: 4618 mov r0, r3 + 800f5e2: 371c adds r7, #28 + 800f5e4: 46bd mov sp, r7 + 800f5e6: bc80 pop {r7} + 800f5e8: 4770 bx lr + 800f5ea: bf00 nop + 800f5ec: 40006400 .word 0x40006400 + +0800f5f0 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + 800f5f0: b580 push {r7, lr} + 800f5f2: b084 sub sp, #16 + 800f5f4: af00 add r7, sp, #0 + 800f5f6: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + 800f5f8: 687b ldr r3, [r7, #4] + 800f5fa: f893 3020 ldrb.w r3, [r3, #32] + 800f5fe: b2db uxtb r3, r3 + 800f600: 2b01 cmp r3, #1 + 800f602: d12e bne.n 800f662 + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + 800f604: 687b ldr r3, [r7, #4] + 800f606: 2202 movs r2, #2 + 800f608: f883 2020 strb.w r2, [r3, #32] + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 800f60c: 687b ldr r3, [r7, #4] + 800f60e: 681b ldr r3, [r3, #0] + 800f610: 681a ldr r2, [r3, #0] + 800f612: 687b ldr r3, [r7, #4] + 800f614: 681b ldr r3, [r3, #0] + 800f616: f022 0201 bic.w r2, r2, #1 + 800f61a: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800f61c: f7ff f8d8 bl 800e7d0 + 800f620: 60f8 str r0, [r7, #12] + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 800f622: e012 b.n 800f64a + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800f624: f7ff f8d4 bl 800e7d0 + 800f628: 4602 mov r2, r0 + 800f62a: 68fb ldr r3, [r7, #12] + 800f62c: 1ad3 subs r3, r2, r3 + 800f62e: 2b0a cmp r3, #10 + 800f630: d90b bls.n 800f64a + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800f632: 687b ldr r3, [r7, #4] + 800f634: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f636: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 800f63a: 687b ldr r3, [r7, #4] + 800f63c: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800f63e: 687b ldr r3, [r7, #4] + 800f640: 2205 movs r2, #5 + 800f642: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800f646: 2301 movs r3, #1 + 800f648: e012 b.n 800f670 + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 800f64a: 687b ldr r3, [r7, #4] + 800f64c: 681b ldr r3, [r3, #0] + 800f64e: 685b ldr r3, [r3, #4] + 800f650: f003 0301 and.w r3, r3, #1 + 800f654: 2b00 cmp r3, #0 + 800f656: d1e5 bne.n 800f624 + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 800f658: 687b ldr r3, [r7, #4] + 800f65a: 2200 movs r2, #0 + 800f65c: 625a str r2, [r3, #36] @ 0x24 + + /* Return function status */ + return HAL_OK; + 800f65e: 2300 movs r3, #0 + 800f660: e006 b.n 800f670 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + 800f662: 687b ldr r3, [r7, #4] + 800f664: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f666: f443 2200 orr.w r2, r3, #524288 @ 0x80000 + 800f66a: 687b ldr r3, [r7, #4] + 800f66c: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f66e: 2301 movs r3, #1 + } +} + 800f670: 4618 mov r0, r3 + 800f672: 3710 adds r7, #16 + 800f674: 46bd mov sp, r7 + 800f676: bd80 pop {r7, pc} + +0800f678 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + 800f678: b580 push {r7, lr} + 800f67a: b084 sub sp, #16 + 800f67c: af00 add r7, sp, #0 + 800f67e: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + 800f680: 687b ldr r3, [r7, #4] + 800f682: f893 3020 ldrb.w r3, [r3, #32] + 800f686: b2db uxtb r3, r3 + 800f688: 2b02 cmp r3, #2 + 800f68a: d133 bne.n 800f6f4 + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 800f68c: 687b ldr r3, [r7, #4] + 800f68e: 681b ldr r3, [r3, #0] + 800f690: 681a ldr r2, [r3, #0] + 800f692: 687b ldr r3, [r7, #4] + 800f694: 681b ldr r3, [r3, #0] + 800f696: f042 0201 orr.w r2, r2, #1 + 800f69a: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800f69c: f7ff f898 bl 800e7d0 + 800f6a0: 60f8 str r0, [r7, #12] + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 800f6a2: e012 b.n 800f6ca + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800f6a4: f7ff f894 bl 800e7d0 + 800f6a8: 4602 mov r2, r0 + 800f6aa: 68fb ldr r3, [r7, #12] + 800f6ac: 1ad3 subs r3, r2, r3 + 800f6ae: 2b0a cmp r3, #10 + 800f6b0: d90b bls.n 800f6ca + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800f6b2: 687b ldr r3, [r7, #4] + 800f6b4: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f6b6: f443 3200 orr.w r2, r3, #131072 @ 0x20000 + 800f6ba: 687b ldr r3, [r7, #4] + 800f6bc: 625a str r2, [r3, #36] @ 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800f6be: 687b ldr r3, [r7, #4] + 800f6c0: 2205 movs r2, #5 + 800f6c2: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800f6c6: 2301 movs r3, #1 + 800f6c8: e01b b.n 800f702 + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 800f6ca: 687b ldr r3, [r7, #4] + 800f6cc: 681b ldr r3, [r3, #0] + 800f6ce: 685b ldr r3, [r3, #4] + 800f6d0: f003 0301 and.w r3, r3, #1 + 800f6d4: 2b00 cmp r3, #0 + 800f6d6: d0e5 beq.n 800f6a4 + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 800f6d8: 687b ldr r3, [r7, #4] + 800f6da: 681b ldr r3, [r3, #0] + 800f6dc: 681a ldr r2, [r3, #0] + 800f6de: 687b ldr r3, [r7, #4] + 800f6e0: 681b ldr r3, [r3, #0] + 800f6e2: f022 0202 bic.w r2, r2, #2 + 800f6e6: 601a str r2, [r3, #0] + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + 800f6e8: 687b ldr r3, [r7, #4] + 800f6ea: 2201 movs r2, #1 + 800f6ec: f883 2020 strb.w r2, [r3, #32] + + /* Return function status */ + return HAL_OK; + 800f6f0: 2300 movs r3, #0 + 800f6f2: e006 b.n 800f702 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + 800f6f4: 687b ldr r3, [r7, #4] + 800f6f6: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f6f8: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 + 800f6fc: 687b ldr r3, [r7, #4] + 800f6fe: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f700: 2301 movs r3, #1 + } +} + 800f702: 4618 mov r0, r3 + 800f704: 3710 adds r7, #16 + 800f706: 46bd mov sp, r7 + 800f708: bd80 pop {r7, pc} + +0800f70a : + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) +{ + 800f70a: b480 push {r7} + 800f70c: b089 sub sp, #36 @ 0x24 + 800f70e: af00 add r7, sp, #0 + 800f710: 60f8 str r0, [r7, #12] + 800f712: 60b9 str r1, [r7, #8] + 800f714: 607a str r2, [r7, #4] + 800f716: 603b str r3, [r7, #0] + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + 800f718: 68fb ldr r3, [r7, #12] + 800f71a: f893 3020 ldrb.w r3, [r3, #32] + 800f71e: 77fb strb r3, [r7, #31] + uint32_t tsr = READ_REG(hcan->Instance->TSR); + 800f720: 68fb ldr r3, [r7, #12] + 800f722: 681b ldr r3, [r3, #0] + 800f724: 689b ldr r3, [r3, #8] + 800f726: 61bb str r3, [r7, #24] + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + 800f728: 7ffb ldrb r3, [r7, #31] + 800f72a: 2b01 cmp r3, #1 + 800f72c: d003 beq.n 800f736 + 800f72e: 7ffb ldrb r3, [r7, #31] + 800f730: 2b02 cmp r3, #2 + 800f732: f040 80ad bne.w 800f890 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + 800f736: 69bb ldr r3, [r7, #24] + 800f738: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 800f73c: 2b00 cmp r3, #0 + 800f73e: d10a bne.n 800f756 + ((tsr & CAN_TSR_TME1) != 0U) || + 800f740: 69bb ldr r3, [r7, #24] + 800f742: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + if (((tsr & CAN_TSR_TME0) != 0U) || + 800f746: 2b00 cmp r3, #0 + 800f748: d105 bne.n 800f756 + ((tsr & CAN_TSR_TME2) != 0U)) + 800f74a: 69bb ldr r3, [r7, #24] + 800f74c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + ((tsr & CAN_TSR_TME1) != 0U) || + 800f750: 2b00 cmp r3, #0 + 800f752: f000 8095 beq.w 800f880 + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + 800f756: 69bb ldr r3, [r7, #24] + 800f758: 0e1b lsrs r3, r3, #24 + 800f75a: f003 0303 and.w r3, r3, #3 + 800f75e: 617b str r3, [r7, #20] + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + 800f760: 2201 movs r2, #1 + 800f762: 697b ldr r3, [r7, #20] + 800f764: 409a lsls r2, r3 + 800f766: 683b ldr r3, [r7, #0] + 800f768: 601a str r2, [r3, #0] + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + 800f76a: 68bb ldr r3, [r7, #8] + 800f76c: 689b ldr r3, [r3, #8] + 800f76e: 2b00 cmp r3, #0 + 800f770: d10d bne.n 800f78e + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + 800f772: 68bb ldr r3, [r7, #8] + 800f774: 681b ldr r3, [r3, #0] + 800f776: 055a lsls r2, r3, #21 + pHeader->RTR); + 800f778: 68bb ldr r3, [r7, #8] + 800f77a: 68db ldr r3, [r3, #12] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + 800f77c: 68f9 ldr r1, [r7, #12] + 800f77e: 6809 ldr r1, [r1, #0] + 800f780: 431a orrs r2, r3 + 800f782: 697b ldr r3, [r7, #20] + 800f784: 3318 adds r3, #24 + 800f786: 011b lsls r3, r3, #4 + 800f788: 440b add r3, r1 + 800f78a: 601a str r2, [r3, #0] + 800f78c: e00f b.n 800f7ae + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 800f78e: 68bb ldr r3, [r7, #8] + 800f790: 685b ldr r3, [r3, #4] + 800f792: 00da lsls r2, r3, #3 + pHeader->IDE | + 800f794: 68bb ldr r3, [r7, #8] + 800f796: 689b ldr r3, [r3, #8] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 800f798: 431a orrs r2, r3 + pHeader->RTR); + 800f79a: 68bb ldr r3, [r7, #8] + 800f79c: 68db ldr r3, [r3, #12] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 800f79e: 68f9 ldr r1, [r7, #12] + 800f7a0: 6809 ldr r1, [r1, #0] + pHeader->IDE | + 800f7a2: 431a orrs r2, r3 + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 800f7a4: 697b ldr r3, [r7, #20] + 800f7a6: 3318 adds r3, #24 + 800f7a8: 011b lsls r3, r3, #4 + 800f7aa: 440b add r3, r1 + 800f7ac: 601a str r2, [r3, #0] + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + 800f7ae: 68fb ldr r3, [r7, #12] + 800f7b0: 6819 ldr r1, [r3, #0] + 800f7b2: 68bb ldr r3, [r7, #8] + 800f7b4: 691a ldr r2, [r3, #16] + 800f7b6: 697b ldr r3, [r7, #20] + 800f7b8: 3318 adds r3, #24 + 800f7ba: 011b lsls r3, r3, #4 + 800f7bc: 440b add r3, r1 + 800f7be: 3304 adds r3, #4 + 800f7c0: 601a str r2, [r3, #0] + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + 800f7c2: 68bb ldr r3, [r7, #8] + 800f7c4: 7d1b ldrb r3, [r3, #20] + 800f7c6: 2b01 cmp r3, #1 + 800f7c8: d111 bne.n 800f7ee + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + 800f7ca: 68fb ldr r3, [r7, #12] + 800f7cc: 681a ldr r2, [r3, #0] + 800f7ce: 697b ldr r3, [r7, #20] + 800f7d0: 3318 adds r3, #24 + 800f7d2: 011b lsls r3, r3, #4 + 800f7d4: 4413 add r3, r2 + 800f7d6: 3304 adds r3, #4 + 800f7d8: 681b ldr r3, [r3, #0] + 800f7da: 68fa ldr r2, [r7, #12] + 800f7dc: 6811 ldr r1, [r2, #0] + 800f7de: f443 7280 orr.w r2, r3, #256 @ 0x100 + 800f7e2: 697b ldr r3, [r7, #20] + 800f7e4: 3318 adds r3, #24 + 800f7e6: 011b lsls r3, r3, #4 + 800f7e8: 440b add r3, r1 + 800f7ea: 3304 adds r3, #4 + 800f7ec: 601a str r2, [r3, #0] + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + 800f7ee: 687b ldr r3, [r7, #4] + 800f7f0: 3307 adds r3, #7 + 800f7f2: 781b ldrb r3, [r3, #0] + 800f7f4: 061a lsls r2, r3, #24 + 800f7f6: 687b ldr r3, [r7, #4] + 800f7f8: 3306 adds r3, #6 + 800f7fa: 781b ldrb r3, [r3, #0] + 800f7fc: 041b lsls r3, r3, #16 + 800f7fe: 431a orrs r2, r3 + 800f800: 687b ldr r3, [r7, #4] + 800f802: 3305 adds r3, #5 + 800f804: 781b ldrb r3, [r3, #0] + 800f806: 021b lsls r3, r3, #8 + 800f808: 4313 orrs r3, r2 + 800f80a: 687a ldr r2, [r7, #4] + 800f80c: 3204 adds r2, #4 + 800f80e: 7812 ldrb r2, [r2, #0] + 800f810: 4610 mov r0, r2 + 800f812: 68fa ldr r2, [r7, #12] + 800f814: 6811 ldr r1, [r2, #0] + 800f816: ea43 0200 orr.w r2, r3, r0 + 800f81a: 697b ldr r3, [r7, #20] + 800f81c: 011b lsls r3, r3, #4 + 800f81e: 440b add r3, r1 + 800f820: f503 73c6 add.w r3, r3, #396 @ 0x18c + 800f824: 601a str r2, [r3, #0] + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + 800f826: 687b ldr r3, [r7, #4] + 800f828: 3303 adds r3, #3 + 800f82a: 781b ldrb r3, [r3, #0] + 800f82c: 061a lsls r2, r3, #24 + 800f82e: 687b ldr r3, [r7, #4] + 800f830: 3302 adds r3, #2 + 800f832: 781b ldrb r3, [r3, #0] + 800f834: 041b lsls r3, r3, #16 + 800f836: 431a orrs r2, r3 + 800f838: 687b ldr r3, [r7, #4] + 800f83a: 3301 adds r3, #1 + 800f83c: 781b ldrb r3, [r3, #0] + 800f83e: 021b lsls r3, r3, #8 + 800f840: 4313 orrs r3, r2 + 800f842: 687a ldr r2, [r7, #4] + 800f844: 7812 ldrb r2, [r2, #0] + 800f846: 4610 mov r0, r2 + 800f848: 68fa ldr r2, [r7, #12] + 800f84a: 6811 ldr r1, [r2, #0] + 800f84c: ea43 0200 orr.w r2, r3, r0 + 800f850: 697b ldr r3, [r7, #20] + 800f852: 011b lsls r3, r3, #4 + 800f854: 440b add r3, r1 + 800f856: f503 73c4 add.w r3, r3, #392 @ 0x188 + 800f85a: 601a str r2, [r3, #0] + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + 800f85c: 68fb ldr r3, [r7, #12] + 800f85e: 681a ldr r2, [r3, #0] + 800f860: 697b ldr r3, [r7, #20] + 800f862: 3318 adds r3, #24 + 800f864: 011b lsls r3, r3, #4 + 800f866: 4413 add r3, r2 + 800f868: 681b ldr r3, [r3, #0] + 800f86a: 68fa ldr r2, [r7, #12] + 800f86c: 6811 ldr r1, [r2, #0] + 800f86e: f043 0201 orr.w r2, r3, #1 + 800f872: 697b ldr r3, [r7, #20] + 800f874: 3318 adds r3, #24 + 800f876: 011b lsls r3, r3, #4 + 800f878: 440b add r3, r1 + 800f87a: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 800f87c: 2300 movs r3, #0 + 800f87e: e00e b.n 800f89e + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 800f880: 68fb ldr r3, [r7, #12] + 800f882: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f884: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 800f888: 68fb ldr r3, [r7, #12] + 800f88a: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f88c: 2301 movs r3, #1 + 800f88e: e006 b.n 800f89e + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 800f890: 68fb ldr r3, [r7, #12] + 800f892: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f894: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 800f898: 68fb ldr r3, [r7, #12] + 800f89a: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f89c: 2301 movs r3, #1 + } +} + 800f89e: 4618 mov r0, r3 + 800f8a0: 3724 adds r7, #36 @ 0x24 + 800f8a2: 46bd mov sp, r7 + 800f8a4: bc80 pop {r7} + 800f8a6: 4770 bx lr + +0800f8a8 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) +{ + 800f8a8: b480 push {r7} + 800f8aa: b085 sub sp, #20 + 800f8ac: af00 add r7, sp, #0 + 800f8ae: 6078 str r0, [r7, #4] + uint32_t freelevel = 0U; + 800f8b0: 2300 movs r3, #0 + 800f8b2: 60fb str r3, [r7, #12] + HAL_CAN_StateTypeDef state = hcan->State; + 800f8b4: 687b ldr r3, [r7, #4] + 800f8b6: f893 3020 ldrb.w r3, [r3, #32] + 800f8ba: 72fb strb r3, [r7, #11] + + if ((state == HAL_CAN_STATE_READY) || + 800f8bc: 7afb ldrb r3, [r7, #11] + 800f8be: 2b01 cmp r3, #1 + 800f8c0: d002 beq.n 800f8c8 + 800f8c2: 7afb ldrb r3, [r7, #11] + 800f8c4: 2b02 cmp r3, #2 + 800f8c6: d11d bne.n 800f904 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + 800f8c8: 687b ldr r3, [r7, #4] + 800f8ca: 681b ldr r3, [r3, #0] + 800f8cc: 689b ldr r3, [r3, #8] + 800f8ce: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 800f8d2: 2b00 cmp r3, #0 + 800f8d4: d002 beq.n 800f8dc + { + freelevel++; + 800f8d6: 68fb ldr r3, [r7, #12] + 800f8d8: 3301 adds r3, #1 + 800f8da: 60fb str r3, [r7, #12] + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + 800f8dc: 687b ldr r3, [r7, #4] + 800f8de: 681b ldr r3, [r3, #0] + 800f8e0: 689b ldr r3, [r3, #8] + 800f8e2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 800f8e6: 2b00 cmp r3, #0 + 800f8e8: d002 beq.n 800f8f0 + { + freelevel++; + 800f8ea: 68fb ldr r3, [r7, #12] + 800f8ec: 3301 adds r3, #1 + 800f8ee: 60fb str r3, [r7, #12] + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + 800f8f0: 687b ldr r3, [r7, #4] + 800f8f2: 681b ldr r3, [r3, #0] + 800f8f4: 689b ldr r3, [r3, #8] + 800f8f6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800f8fa: 2b00 cmp r3, #0 + 800f8fc: d002 beq.n 800f904 + { + freelevel++; + 800f8fe: 68fb ldr r3, [r7, #12] + 800f900: 3301 adds r3, #1 + 800f902: 60fb str r3, [r7, #12] + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; + 800f904: 68fb ldr r3, [r7, #12] +} + 800f906: 4618 mov r0, r3 + 800f908: 3714 adds r7, #20 + 800f90a: 46bd mov sp, r7 + 800f90c: bc80 pop {r7} + 800f90e: 4770 bx lr + +0800f910 : + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + 800f910: b480 push {r7} + 800f912: b087 sub sp, #28 + 800f914: af00 add r7, sp, #0 + 800f916: 60f8 str r0, [r7, #12] + 800f918: 60b9 str r1, [r7, #8] + 800f91a: 607a str r2, [r7, #4] + 800f91c: 603b str r3, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 800f91e: 68fb ldr r3, [r7, #12] + 800f920: f893 3020 ldrb.w r3, [r3, #32] + 800f924: 75fb strb r3, [r7, #23] + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + 800f926: 7dfb ldrb r3, [r7, #23] + 800f928: 2b01 cmp r3, #1 + 800f92a: d003 beq.n 800f934 + 800f92c: 7dfb ldrb r3, [r7, #23] + 800f92e: 2b02 cmp r3, #2 + 800f930: f040 8103 bne.w 800fb3a + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 800f934: 68bb ldr r3, [r7, #8] + 800f936: 2b00 cmp r3, #0 + 800f938: d10e bne.n 800f958 + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + 800f93a: 68fb ldr r3, [r7, #12] + 800f93c: 681b ldr r3, [r3, #0] + 800f93e: 68db ldr r3, [r3, #12] + 800f940: f003 0303 and.w r3, r3, #3 + 800f944: 2b00 cmp r3, #0 + 800f946: d116 bne.n 800f976 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 800f948: 68fb ldr r3, [r7, #12] + 800f94a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f94c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 800f950: 68fb ldr r3, [r7, #12] + 800f952: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f954: 2301 movs r3, #1 + 800f956: e0f7 b.n 800fb48 + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + 800f958: 68fb ldr r3, [r7, #12] + 800f95a: 681b ldr r3, [r3, #0] + 800f95c: 691b ldr r3, [r3, #16] + 800f95e: f003 0303 and.w r3, r3, #3 + 800f962: 2b00 cmp r3, #0 + 800f964: d107 bne.n 800f976 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 800f966: 68fb ldr r3, [r7, #12] + 800f968: 6a5b ldr r3, [r3, #36] @ 0x24 + 800f96a: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 800f96e: 68fb ldr r3, [r7, #12] + 800f970: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800f972: 2301 movs r3, #1 + 800f974: e0e8 b.n 800fb48 + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + 800f976: 68fb ldr r3, [r7, #12] + 800f978: 681a ldr r2, [r3, #0] + 800f97a: 68bb ldr r3, [r7, #8] + 800f97c: 331b adds r3, #27 + 800f97e: 011b lsls r3, r3, #4 + 800f980: 4413 add r3, r2 + 800f982: 681b ldr r3, [r3, #0] + 800f984: f003 0204 and.w r2, r3, #4 + 800f988: 687b ldr r3, [r7, #4] + 800f98a: 609a str r2, [r3, #8] + if (pHeader->IDE == CAN_ID_STD) + 800f98c: 687b ldr r3, [r7, #4] + 800f98e: 689b ldr r3, [r3, #8] + 800f990: 2b00 cmp r3, #0 + 800f992: d10c bne.n 800f9ae + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + 800f994: 68fb ldr r3, [r7, #12] + 800f996: 681a ldr r2, [r3, #0] + 800f998: 68bb ldr r3, [r7, #8] + 800f99a: 331b adds r3, #27 + 800f99c: 011b lsls r3, r3, #4 + 800f99e: 4413 add r3, r2 + 800f9a0: 681b ldr r3, [r3, #0] + 800f9a2: 0d5b lsrs r3, r3, #21 + 800f9a4: f3c3 020a ubfx r2, r3, #0, #11 + 800f9a8: 687b ldr r3, [r7, #4] + 800f9aa: 601a str r2, [r3, #0] + 800f9ac: e00b b.n 800f9c6 + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 800f9ae: 68fb ldr r3, [r7, #12] + 800f9b0: 681a ldr r2, [r3, #0] + 800f9b2: 68bb ldr r3, [r7, #8] + 800f9b4: 331b adds r3, #27 + 800f9b6: 011b lsls r3, r3, #4 + 800f9b8: 4413 add r3, r2 + 800f9ba: 681b ldr r3, [r3, #0] + 800f9bc: 08db lsrs r3, r3, #3 + 800f9be: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + 800f9c2: 687b ldr r3, [r7, #4] + 800f9c4: 605a str r2, [r3, #4] + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 800f9c6: 68fb ldr r3, [r7, #12] + 800f9c8: 681a ldr r2, [r3, #0] + 800f9ca: 68bb ldr r3, [r7, #8] + 800f9cc: 331b adds r3, #27 + 800f9ce: 011b lsls r3, r3, #4 + 800f9d0: 4413 add r3, r2 + 800f9d2: 681b ldr r3, [r3, #0] + 800f9d4: f003 0202 and.w r2, r3, #2 + 800f9d8: 687b ldr r3, [r7, #4] + 800f9da: 60da str r2, [r3, #12] + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + 800f9dc: 68fb ldr r3, [r7, #12] + 800f9de: 681a ldr r2, [r3, #0] + 800f9e0: 68bb ldr r3, [r7, #8] + 800f9e2: 331b adds r3, #27 + 800f9e4: 011b lsls r3, r3, #4 + 800f9e6: 4413 add r3, r2 + 800f9e8: 3304 adds r3, #4 + 800f9ea: 681b ldr r3, [r3, #0] + 800f9ec: f003 0308 and.w r3, r3, #8 + 800f9f0: 2b00 cmp r3, #0 + 800f9f2: d003 beq.n 800f9fc + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + 800f9f4: 687b ldr r3, [r7, #4] + 800f9f6: 2208 movs r2, #8 + 800f9f8: 611a str r2, [r3, #16] + 800f9fa: e00b b.n 800fa14 + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + 800f9fc: 68fb ldr r3, [r7, #12] + 800f9fe: 681a ldr r2, [r3, #0] + 800fa00: 68bb ldr r3, [r7, #8] + 800fa02: 331b adds r3, #27 + 800fa04: 011b lsls r3, r3, #4 + 800fa06: 4413 add r3, r2 + 800fa08: 3304 adds r3, #4 + 800fa0a: 681b ldr r3, [r3, #0] + 800fa0c: f003 020f and.w r2, r3, #15 + 800fa10: 687b ldr r3, [r7, #4] + 800fa12: 611a str r2, [r3, #16] + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + 800fa14: 68fb ldr r3, [r7, #12] + 800fa16: 681a ldr r2, [r3, #0] + 800fa18: 68bb ldr r3, [r7, #8] + 800fa1a: 331b adds r3, #27 + 800fa1c: 011b lsls r3, r3, #4 + 800fa1e: 4413 add r3, r2 + 800fa20: 3304 adds r3, #4 + 800fa22: 681b ldr r3, [r3, #0] + 800fa24: 0a1b lsrs r3, r3, #8 + 800fa26: b2da uxtb r2, r3 + 800fa28: 687b ldr r3, [r7, #4] + 800fa2a: 619a str r2, [r3, #24] + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + 800fa2c: 68fb ldr r3, [r7, #12] + 800fa2e: 681a ldr r2, [r3, #0] + 800fa30: 68bb ldr r3, [r7, #8] + 800fa32: 331b adds r3, #27 + 800fa34: 011b lsls r3, r3, #4 + 800fa36: 4413 add r3, r2 + 800fa38: 3304 adds r3, #4 + 800fa3a: 681b ldr r3, [r3, #0] + 800fa3c: 0c1b lsrs r3, r3, #16 + 800fa3e: b29a uxth r2, r3 + 800fa40: 687b ldr r3, [r7, #4] + 800fa42: 615a str r2, [r3, #20] + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + 800fa44: 68fb ldr r3, [r7, #12] + 800fa46: 681a ldr r2, [r3, #0] + 800fa48: 68bb ldr r3, [r7, #8] + 800fa4a: 011b lsls r3, r3, #4 + 800fa4c: 4413 add r3, r2 + 800fa4e: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 800fa52: 681b ldr r3, [r3, #0] + 800fa54: b2da uxtb r2, r3 + 800fa56: 683b ldr r3, [r7, #0] + 800fa58: 701a strb r2, [r3, #0] + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + 800fa5a: 68fb ldr r3, [r7, #12] + 800fa5c: 681a ldr r2, [r3, #0] + 800fa5e: 68bb ldr r3, [r7, #8] + 800fa60: 011b lsls r3, r3, #4 + 800fa62: 4413 add r3, r2 + 800fa64: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 800fa68: 681b ldr r3, [r3, #0] + 800fa6a: 0a1a lsrs r2, r3, #8 + 800fa6c: 683b ldr r3, [r7, #0] + 800fa6e: 3301 adds r3, #1 + 800fa70: b2d2 uxtb r2, r2 + 800fa72: 701a strb r2, [r3, #0] + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + 800fa74: 68fb ldr r3, [r7, #12] + 800fa76: 681a ldr r2, [r3, #0] + 800fa78: 68bb ldr r3, [r7, #8] + 800fa7a: 011b lsls r3, r3, #4 + 800fa7c: 4413 add r3, r2 + 800fa7e: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 800fa82: 681b ldr r3, [r3, #0] + 800fa84: 0c1a lsrs r2, r3, #16 + 800fa86: 683b ldr r3, [r7, #0] + 800fa88: 3302 adds r3, #2 + 800fa8a: b2d2 uxtb r2, r2 + 800fa8c: 701a strb r2, [r3, #0] + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + 800fa8e: 68fb ldr r3, [r7, #12] + 800fa90: 681a ldr r2, [r3, #0] + 800fa92: 68bb ldr r3, [r7, #8] + 800fa94: 011b lsls r3, r3, #4 + 800fa96: 4413 add r3, r2 + 800fa98: f503 73dc add.w r3, r3, #440 @ 0x1b8 + 800fa9c: 681b ldr r3, [r3, #0] + 800fa9e: 0e1a lsrs r2, r3, #24 + 800faa0: 683b ldr r3, [r7, #0] + 800faa2: 3303 adds r3, #3 + 800faa4: b2d2 uxtb r2, r2 + 800faa6: 701a strb r2, [r3, #0] + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + 800faa8: 68fb ldr r3, [r7, #12] + 800faaa: 681a ldr r2, [r3, #0] + 800faac: 68bb ldr r3, [r7, #8] + 800faae: 011b lsls r3, r3, #4 + 800fab0: 4413 add r3, r2 + 800fab2: f503 73de add.w r3, r3, #444 @ 0x1bc + 800fab6: 681a ldr r2, [r3, #0] + 800fab8: 683b ldr r3, [r7, #0] + 800faba: 3304 adds r3, #4 + 800fabc: b2d2 uxtb r2, r2 + 800fabe: 701a strb r2, [r3, #0] + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + 800fac0: 68fb ldr r3, [r7, #12] + 800fac2: 681a ldr r2, [r3, #0] + 800fac4: 68bb ldr r3, [r7, #8] + 800fac6: 011b lsls r3, r3, #4 + 800fac8: 4413 add r3, r2 + 800faca: f503 73de add.w r3, r3, #444 @ 0x1bc + 800face: 681b ldr r3, [r3, #0] + 800fad0: 0a1a lsrs r2, r3, #8 + 800fad2: 683b ldr r3, [r7, #0] + 800fad4: 3305 adds r3, #5 + 800fad6: b2d2 uxtb r2, r2 + 800fad8: 701a strb r2, [r3, #0] + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + 800fada: 68fb ldr r3, [r7, #12] + 800fadc: 681a ldr r2, [r3, #0] + 800fade: 68bb ldr r3, [r7, #8] + 800fae0: 011b lsls r3, r3, #4 + 800fae2: 4413 add r3, r2 + 800fae4: f503 73de add.w r3, r3, #444 @ 0x1bc + 800fae8: 681b ldr r3, [r3, #0] + 800faea: 0c1a lsrs r2, r3, #16 + 800faec: 683b ldr r3, [r7, #0] + 800faee: 3306 adds r3, #6 + 800faf0: b2d2 uxtb r2, r2 + 800faf2: 701a strb r2, [r3, #0] + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + 800faf4: 68fb ldr r3, [r7, #12] + 800faf6: 681a ldr r2, [r3, #0] + 800faf8: 68bb ldr r3, [r7, #8] + 800fafa: 011b lsls r3, r3, #4 + 800fafc: 4413 add r3, r2 + 800fafe: f503 73de add.w r3, r3, #444 @ 0x1bc + 800fb02: 681b ldr r3, [r3, #0] + 800fb04: 0e1a lsrs r2, r3, #24 + 800fb06: 683b ldr r3, [r7, #0] + 800fb08: 3307 adds r3, #7 + 800fb0a: b2d2 uxtb r2, r2 + 800fb0c: 701a strb r2, [r3, #0] + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 800fb0e: 68bb ldr r3, [r7, #8] + 800fb10: 2b00 cmp r3, #0 + 800fb12: d108 bne.n 800fb26 + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + 800fb14: 68fb ldr r3, [r7, #12] + 800fb16: 681b ldr r3, [r3, #0] + 800fb18: 68da ldr r2, [r3, #12] + 800fb1a: 68fb ldr r3, [r7, #12] + 800fb1c: 681b ldr r3, [r3, #0] + 800fb1e: f042 0220 orr.w r2, r2, #32 + 800fb22: 60da str r2, [r3, #12] + 800fb24: e007 b.n 800fb36 + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + 800fb26: 68fb ldr r3, [r7, #12] + 800fb28: 681b ldr r3, [r3, #0] + 800fb2a: 691a ldr r2, [r3, #16] + 800fb2c: 68fb ldr r3, [r7, #12] + 800fb2e: 681b ldr r3, [r3, #0] + 800fb30: f042 0220 orr.w r2, r2, #32 + 800fb34: 611a str r2, [r3, #16] + } + + /* Return function status */ + return HAL_OK; + 800fb36: 2300 movs r3, #0 + 800fb38: e006 b.n 800fb48 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 800fb3a: 68fb ldr r3, [r7, #12] + 800fb3c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800fb3e: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 800fb42: 68fb ldr r3, [r7, #12] + 800fb44: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800fb46: 2301 movs r3, #1 + } +} + 800fb48: 4618 mov r0, r3 + 800fb4a: 371c adds r7, #28 + 800fb4c: 46bd mov sp, r7 + 800fb4e: bc80 pop {r7} + 800fb50: 4770 bx lr + +0800fb52 : + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + 800fb52: b480 push {r7} + 800fb54: b085 sub sp, #20 + 800fb56: af00 add r7, sp, #0 + 800fb58: 6078 str r0, [r7, #4] + 800fb5a: 6039 str r1, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 800fb5c: 687b ldr r3, [r7, #4] + 800fb5e: f893 3020 ldrb.w r3, [r3, #32] + 800fb62: 73fb strb r3, [r7, #15] + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + 800fb64: 7bfb ldrb r3, [r7, #15] + 800fb66: 2b01 cmp r3, #1 + 800fb68: d002 beq.n 800fb70 + 800fb6a: 7bfb ldrb r3, [r7, #15] + 800fb6c: 2b02 cmp r3, #2 + 800fb6e: d109 bne.n 800fb84 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + 800fb70: 687b ldr r3, [r7, #4] + 800fb72: 681b ldr r3, [r3, #0] + 800fb74: 6959 ldr r1, [r3, #20] + 800fb76: 687b ldr r3, [r7, #4] + 800fb78: 681b ldr r3, [r3, #0] + 800fb7a: 683a ldr r2, [r7, #0] + 800fb7c: 430a orrs r2, r1 + 800fb7e: 615a str r2, [r3, #20] + + /* Return function status */ + return HAL_OK; + 800fb80: 2300 movs r3, #0 + 800fb82: e006 b.n 800fb92 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 800fb84: 687b ldr r3, [r7, #4] + 800fb86: 6a5b ldr r3, [r3, #36] @ 0x24 + 800fb88: f443 2280 orr.w r2, r3, #262144 @ 0x40000 + 800fb8c: 687b ldr r3, [r7, #4] + 800fb8e: 625a str r2, [r3, #36] @ 0x24 + + return HAL_ERROR; + 800fb90: 2301 movs r3, #1 + } +} + 800fb92: 4618 mov r0, r3 + 800fb94: 3714 adds r7, #20 + 800fb96: 46bd mov sp, r7 + 800fb98: bc80 pop {r7} + 800fb9a: 4770 bx lr + +0800fb9c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + 800fb9c: b580 push {r7, lr} + 800fb9e: b08a sub sp, #40 @ 0x28 + 800fba0: af00 add r7, sp, #0 + 800fba2: 6078 str r0, [r7, #4] + uint32_t errorcode = HAL_CAN_ERROR_NONE; + 800fba4: 2300 movs r3, #0 + 800fba6: 627b str r3, [r7, #36] @ 0x24 + uint32_t interrupts = READ_REG(hcan->Instance->IER); + 800fba8: 687b ldr r3, [r7, #4] + 800fbaa: 681b ldr r3, [r3, #0] + 800fbac: 695b ldr r3, [r3, #20] + 800fbae: 623b str r3, [r7, #32] + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 800fbb0: 687b ldr r3, [r7, #4] + 800fbb2: 681b ldr r3, [r3, #0] + 800fbb4: 685b ldr r3, [r3, #4] + 800fbb6: 61fb str r3, [r7, #28] + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + 800fbb8: 687b ldr r3, [r7, #4] + 800fbba: 681b ldr r3, [r3, #0] + 800fbbc: 689b ldr r3, [r3, #8] + 800fbbe: 61bb str r3, [r7, #24] + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + 800fbc0: 687b ldr r3, [r7, #4] + 800fbc2: 681b ldr r3, [r3, #0] + 800fbc4: 68db ldr r3, [r3, #12] + 800fbc6: 617b str r3, [r7, #20] + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + 800fbc8: 687b ldr r3, [r7, #4] + 800fbca: 681b ldr r3, [r3, #0] + 800fbcc: 691b ldr r3, [r3, #16] + 800fbce: 613b str r3, [r7, #16] + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + 800fbd0: 687b ldr r3, [r7, #4] + 800fbd2: 681b ldr r3, [r3, #0] + 800fbd4: 699b ldr r3, [r3, #24] + 800fbd6: 60fb str r3, [r7, #12] + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + 800fbd8: 6a3b ldr r3, [r7, #32] + 800fbda: f003 0301 and.w r3, r3, #1 + 800fbde: 2b00 cmp r3, #0 + 800fbe0: d07c beq.n 800fcdc + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + 800fbe2: 69bb ldr r3, [r7, #24] + 800fbe4: f003 0301 and.w r3, r3, #1 + 800fbe8: 2b00 cmp r3, #0 + 800fbea: d023 beq.n 800fc34 + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + 800fbec: 687b ldr r3, [r7, #4] + 800fbee: 681b ldr r3, [r3, #0] + 800fbf0: 2201 movs r2, #1 + 800fbf2: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + 800fbf4: 69bb ldr r3, [r7, #24] + 800fbf6: f003 0302 and.w r3, r3, #2 + 800fbfa: 2b00 cmp r3, #0 + 800fbfc: d003 beq.n 800fc06 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + 800fbfe: 6878 ldr r0, [r7, #4] + 800fc00: f000 f983 bl 800ff0a + 800fc04: e016 b.n 800fc34 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + 800fc06: 69bb ldr r3, [r7, #24] + 800fc08: f003 0304 and.w r3, r3, #4 + 800fc0c: 2b00 cmp r3, #0 + 800fc0e: d004 beq.n 800fc1a + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + 800fc10: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fc12: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 800fc16: 627b str r3, [r7, #36] @ 0x24 + 800fc18: e00c b.n 800fc34 + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + 800fc1a: 69bb ldr r3, [r7, #24] + 800fc1c: f003 0308 and.w r3, r3, #8 + 800fc20: 2b00 cmp r3, #0 + 800fc22: d004 beq.n 800fc2e + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + 800fc24: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fc26: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800fc2a: 627b str r3, [r7, #36] @ 0x24 + 800fc2c: e002 b.n 800fc34 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + 800fc2e: 6878 ldr r0, [r7, #4] + 800fc30: f000 f986 bl 800ff40 + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + 800fc34: 69bb ldr r3, [r7, #24] + 800fc36: f403 7380 and.w r3, r3, #256 @ 0x100 + 800fc3a: 2b00 cmp r3, #0 + 800fc3c: d024 beq.n 800fc88 + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + 800fc3e: 687b ldr r3, [r7, #4] + 800fc40: 681b ldr r3, [r3, #0] + 800fc42: f44f 7280 mov.w r2, #256 @ 0x100 + 800fc46: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + 800fc48: 69bb ldr r3, [r7, #24] + 800fc4a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800fc4e: 2b00 cmp r3, #0 + 800fc50: d003 beq.n 800fc5a +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + 800fc52: 6878 ldr r0, [r7, #4] + 800fc54: f000 f962 bl 800ff1c + 800fc58: e016 b.n 800fc88 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + 800fc5a: 69bb ldr r3, [r7, #24] + 800fc5c: f403 6380 and.w r3, r3, #1024 @ 0x400 + 800fc60: 2b00 cmp r3, #0 + 800fc62: d004 beq.n 800fc6e + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + 800fc64: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fc66: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 800fc6a: 627b str r3, [r7, #36] @ 0x24 + 800fc6c: e00c b.n 800fc88 + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + 800fc6e: 69bb ldr r3, [r7, #24] + 800fc70: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800fc74: 2b00 cmp r3, #0 + 800fc76: d004 beq.n 800fc82 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + 800fc78: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fc7a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800fc7e: 627b str r3, [r7, #36] @ 0x24 + 800fc80: e002 b.n 800fc88 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + 800fc82: 6878 ldr r0, [r7, #4] + 800fc84: f000 f965 bl 800ff52 + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + 800fc88: 69bb ldr r3, [r7, #24] + 800fc8a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800fc8e: 2b00 cmp r3, #0 + 800fc90: d024 beq.n 800fcdc + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + 800fc92: 687b ldr r3, [r7, #4] + 800fc94: 681b ldr r3, [r3, #0] + 800fc96: f44f 3280 mov.w r2, #65536 @ 0x10000 + 800fc9a: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + 800fc9c: 69bb ldr r3, [r7, #24] + 800fc9e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800fca2: 2b00 cmp r3, #0 + 800fca4: d003 beq.n 800fcae +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + 800fca6: 6878 ldr r0, [r7, #4] + 800fca8: f000 f941 bl 800ff2e + 800fcac: e016 b.n 800fcdc +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + 800fcae: 69bb ldr r3, [r7, #24] + 800fcb0: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 800fcb4: 2b00 cmp r3, #0 + 800fcb6: d004 beq.n 800fcc2 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + 800fcb8: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fcba: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 800fcbe: 627b str r3, [r7, #36] @ 0x24 + 800fcc0: e00c b.n 800fcdc + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + 800fcc2: 69bb ldr r3, [r7, #24] + 800fcc4: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 800fcc8: 2b00 cmp r3, #0 + 800fcca: d004 beq.n 800fcd6 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + 800fccc: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fcce: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 800fcd2: 627b str r3, [r7, #36] @ 0x24 + 800fcd4: e002 b.n 800fcdc +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + 800fcd6: 6878 ldr r0, [r7, #4] + 800fcd8: f000 f944 bl 800ff64 + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + 800fcdc: 6a3b ldr r3, [r7, #32] + 800fcde: f003 0308 and.w r3, r3, #8 + 800fce2: 2b00 cmp r3, #0 + 800fce4: d00c beq.n 800fd00 + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + 800fce6: 697b ldr r3, [r7, #20] + 800fce8: f003 0310 and.w r3, r3, #16 + 800fcec: 2b00 cmp r3, #0 + 800fcee: d007 beq.n 800fd00 + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + 800fcf0: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fcf2: f443 7300 orr.w r3, r3, #512 @ 0x200 + 800fcf6: 627b str r3, [r7, #36] @ 0x24 + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + 800fcf8: 687b ldr r3, [r7, #4] + 800fcfa: 681b ldr r3, [r3, #0] + 800fcfc: 2210 movs r2, #16 + 800fcfe: 60da str r2, [r3, #12] + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + 800fd00: 6a3b ldr r3, [r7, #32] + 800fd02: f003 0304 and.w r3, r3, #4 + 800fd06: 2b00 cmp r3, #0 + 800fd08: d00b beq.n 800fd22 + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + 800fd0a: 697b ldr r3, [r7, #20] + 800fd0c: f003 0308 and.w r3, r3, #8 + 800fd10: 2b00 cmp r3, #0 + 800fd12: d006 beq.n 800fd22 + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + 800fd14: 687b ldr r3, [r7, #4] + 800fd16: 681b ldr r3, [r3, #0] + 800fd18: 2208 movs r2, #8 + 800fd1a: 60da str r2, [r3, #12] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + 800fd1c: 6878 ldr r0, [r7, #4] + 800fd1e: f000 f92a bl 800ff76 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + 800fd22: 6a3b ldr r3, [r7, #32] + 800fd24: f003 0302 and.w r3, r3, #2 + 800fd28: 2b00 cmp r3, #0 + 800fd2a: d009 beq.n 800fd40 + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + 800fd2c: 687b ldr r3, [r7, #4] + 800fd2e: 681b ldr r3, [r3, #0] + 800fd30: 68db ldr r3, [r3, #12] + 800fd32: f003 0303 and.w r3, r3, #3 + 800fd36: 2b00 cmp r3, #0 + 800fd38: d002 beq.n 800fd40 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + 800fd3a: 6878 ldr r0, [r7, #4] + 800fd3c: f7fb fdac bl 800b898 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + 800fd40: 6a3b ldr r3, [r7, #32] + 800fd42: f003 0340 and.w r3, r3, #64 @ 0x40 + 800fd46: 2b00 cmp r3, #0 + 800fd48: d00c beq.n 800fd64 + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + 800fd4a: 693b ldr r3, [r7, #16] + 800fd4c: f003 0310 and.w r3, r3, #16 + 800fd50: 2b00 cmp r3, #0 + 800fd52: d007 beq.n 800fd64 + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + 800fd54: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fd56: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800fd5a: 627b str r3, [r7, #36] @ 0x24 + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + 800fd5c: 687b ldr r3, [r7, #4] + 800fd5e: 681b ldr r3, [r3, #0] + 800fd60: 2210 movs r2, #16 + 800fd62: 611a str r2, [r3, #16] + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + 800fd64: 6a3b ldr r3, [r7, #32] + 800fd66: f003 0320 and.w r3, r3, #32 + 800fd6a: 2b00 cmp r3, #0 + 800fd6c: d00b beq.n 800fd86 + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + 800fd6e: 693b ldr r3, [r7, #16] + 800fd70: f003 0308 and.w r3, r3, #8 + 800fd74: 2b00 cmp r3, #0 + 800fd76: d006 beq.n 800fd86 + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + 800fd78: 687b ldr r3, [r7, #4] + 800fd7a: 681b ldr r3, [r3, #0] + 800fd7c: 2208 movs r2, #8 + 800fd7e: 611a str r2, [r3, #16] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + 800fd80: 6878 ldr r0, [r7, #4] + 800fd82: f000 f901 bl 800ff88 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + 800fd86: 6a3b ldr r3, [r7, #32] + 800fd88: f003 0310 and.w r3, r3, #16 + 800fd8c: 2b00 cmp r3, #0 + 800fd8e: d009 beq.n 800fda4 + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + 800fd90: 687b ldr r3, [r7, #4] + 800fd92: 681b ldr r3, [r3, #0] + 800fd94: 691b ldr r3, [r3, #16] + 800fd96: f003 0303 and.w r3, r3, #3 + 800fd9a: 2b00 cmp r3, #0 + 800fd9c: d002 beq.n 800fda4 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + 800fd9e: 6878 ldr r0, [r7, #4] + 800fda0: f7fc fb32 bl 800c408 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + 800fda4: 6a3b ldr r3, [r7, #32] + 800fda6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800fdaa: 2b00 cmp r3, #0 + 800fdac: d00b beq.n 800fdc6 + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + 800fdae: 69fb ldr r3, [r7, #28] + 800fdb0: f003 0310 and.w r3, r3, #16 + 800fdb4: 2b00 cmp r3, #0 + 800fdb6: d006 beq.n 800fdc6 + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + 800fdb8: 687b ldr r3, [r7, #4] + 800fdba: 681b ldr r3, [r3, #0] + 800fdbc: 2210 movs r2, #16 + 800fdbe: 605a str r2, [r3, #4] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + 800fdc0: 6878 ldr r0, [r7, #4] + 800fdc2: f000 f8ea bl 800ff9a +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + 800fdc6: 6a3b ldr r3, [r7, #32] + 800fdc8: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800fdcc: 2b00 cmp r3, #0 + 800fdce: d00b beq.n 800fde8 + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + 800fdd0: 69fb ldr r3, [r7, #28] + 800fdd2: f003 0308 and.w r3, r3, #8 + 800fdd6: 2b00 cmp r3, #0 + 800fdd8: d006 beq.n 800fde8 + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + 800fdda: 687b ldr r3, [r7, #4] + 800fddc: 681b ldr r3, [r3, #0] + 800fdde: 2208 movs r2, #8 + 800fde0: 605a str r2, [r3, #4] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + 800fde2: 6878 ldr r0, [r7, #4] + 800fde4: f000 f8e2 bl 800ffac +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + 800fde8: 6a3b ldr r3, [r7, #32] + 800fdea: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 800fdee: 2b00 cmp r3, #0 + 800fdf0: d07b beq.n 800feea + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + 800fdf2: 69fb ldr r3, [r7, #28] + 800fdf4: f003 0304 and.w r3, r3, #4 + 800fdf8: 2b00 cmp r3, #0 + 800fdfa: d072 beq.n 800fee2 + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + 800fdfc: 6a3b ldr r3, [r7, #32] + 800fdfe: f403 7380 and.w r3, r3, #256 @ 0x100 + 800fe02: 2b00 cmp r3, #0 + 800fe04: d008 beq.n 800fe18 + ((esrflags & CAN_ESR_EWGF) != 0U)) + 800fe06: 68fb ldr r3, [r7, #12] + 800fe08: f003 0301 and.w r3, r3, #1 + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + 800fe0c: 2b00 cmp r3, #0 + 800fe0e: d003 beq.n 800fe18 + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + 800fe10: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fe12: f043 0301 orr.w r3, r3, #1 + 800fe16: 627b str r3, [r7, #36] @ 0x24 + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + 800fe18: 6a3b ldr r3, [r7, #32] + 800fe1a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800fe1e: 2b00 cmp r3, #0 + 800fe20: d008 beq.n 800fe34 + ((esrflags & CAN_ESR_EPVF) != 0U)) + 800fe22: 68fb ldr r3, [r7, #12] + 800fe24: f003 0302 and.w r3, r3, #2 + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + 800fe28: 2b00 cmp r3, #0 + 800fe2a: d003 beq.n 800fe34 + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + 800fe2c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fe2e: f043 0302 orr.w r3, r3, #2 + 800fe32: 627b str r3, [r7, #36] @ 0x24 + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + 800fe34: 6a3b ldr r3, [r7, #32] + 800fe36: f403 6380 and.w r3, r3, #1024 @ 0x400 + 800fe3a: 2b00 cmp r3, #0 + 800fe3c: d008 beq.n 800fe50 + ((esrflags & CAN_ESR_BOFF) != 0U)) + 800fe3e: 68fb ldr r3, [r7, #12] + 800fe40: f003 0304 and.w r3, r3, #4 + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + 800fe44: 2b00 cmp r3, #0 + 800fe46: d003 beq.n 800fe50 + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + 800fe48: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fe4a: f043 0304 orr.w r3, r3, #4 + 800fe4e: 627b str r3, [r7, #36] @ 0x24 + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + 800fe50: 6a3b ldr r3, [r7, #32] + 800fe52: f403 6300 and.w r3, r3, #2048 @ 0x800 + 800fe56: 2b00 cmp r3, #0 + 800fe58: d043 beq.n 800fee2 + ((esrflags & CAN_ESR_LEC) != 0U)) + 800fe5a: 68fb ldr r3, [r7, #12] + 800fe5c: f003 0370 and.w r3, r3, #112 @ 0x70 + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + 800fe60: 2b00 cmp r3, #0 + 800fe62: d03e beq.n 800fee2 + { + switch (esrflags & CAN_ESR_LEC) + 800fe64: 68fb ldr r3, [r7, #12] + 800fe66: f003 0370 and.w r3, r3, #112 @ 0x70 + 800fe6a: 2b60 cmp r3, #96 @ 0x60 + 800fe6c: d02b beq.n 800fec6 + 800fe6e: 2b60 cmp r3, #96 @ 0x60 + 800fe70: d82e bhi.n 800fed0 + 800fe72: 2b50 cmp r3, #80 @ 0x50 + 800fe74: d022 beq.n 800febc + 800fe76: 2b50 cmp r3, #80 @ 0x50 + 800fe78: d82a bhi.n 800fed0 + 800fe7a: 2b40 cmp r3, #64 @ 0x40 + 800fe7c: d019 beq.n 800feb2 + 800fe7e: 2b40 cmp r3, #64 @ 0x40 + 800fe80: d826 bhi.n 800fed0 + 800fe82: 2b30 cmp r3, #48 @ 0x30 + 800fe84: d010 beq.n 800fea8 + 800fe86: 2b30 cmp r3, #48 @ 0x30 + 800fe88: d822 bhi.n 800fed0 + 800fe8a: 2b10 cmp r3, #16 + 800fe8c: d002 beq.n 800fe94 + 800fe8e: 2b20 cmp r3, #32 + 800fe90: d005 beq.n 800fe9e + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + 800fe92: e01d b.n 800fed0 + errorcode |= HAL_CAN_ERROR_STF; + 800fe94: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fe96: f043 0308 orr.w r3, r3, #8 + 800fe9a: 627b str r3, [r7, #36] @ 0x24 + break; + 800fe9c: e019 b.n 800fed2 + errorcode |= HAL_CAN_ERROR_FOR; + 800fe9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fea0: f043 0310 orr.w r3, r3, #16 + 800fea4: 627b str r3, [r7, #36] @ 0x24 + break; + 800fea6: e014 b.n 800fed2 + errorcode |= HAL_CAN_ERROR_ACK; + 800fea8: 6a7b ldr r3, [r7, #36] @ 0x24 + 800feaa: f043 0320 orr.w r3, r3, #32 + 800feae: 627b str r3, [r7, #36] @ 0x24 + break; + 800feb0: e00f b.n 800fed2 + errorcode |= HAL_CAN_ERROR_BR; + 800feb2: 6a7b ldr r3, [r7, #36] @ 0x24 + 800feb4: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800feb8: 627b str r3, [r7, #36] @ 0x24 + break; + 800feba: e00a b.n 800fed2 + errorcode |= HAL_CAN_ERROR_BD; + 800febc: 6a7b ldr r3, [r7, #36] @ 0x24 + 800febe: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800fec2: 627b str r3, [r7, #36] @ 0x24 + break; + 800fec4: e005 b.n 800fed2 + errorcode |= HAL_CAN_ERROR_CRC; + 800fec6: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fec8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800fecc: 627b str r3, [r7, #36] @ 0x24 + break; + 800fece: e000 b.n 800fed2 + break; + 800fed0: bf00 nop + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + 800fed2: 687b ldr r3, [r7, #4] + 800fed4: 681b ldr r3, [r3, #0] + 800fed6: 699a ldr r2, [r3, #24] + 800fed8: 687b ldr r3, [r7, #4] + 800feda: 681b ldr r3, [r3, #0] + 800fedc: f022 0270 bic.w r2, r2, #112 @ 0x70 + 800fee0: 619a str r2, [r3, #24] + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + 800fee2: 687b ldr r3, [r7, #4] + 800fee4: 681b ldr r3, [r3, #0] + 800fee6: 2204 movs r2, #4 + 800fee8: 605a str r2, [r3, #4] + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + 800feea: 6a7b ldr r3, [r7, #36] @ 0x24 + 800feec: 2b00 cmp r3, #0 + 800feee: d008 beq.n 800ff02 + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + 800fef0: 687b ldr r3, [r7, #4] + 800fef2: 6a5a ldr r2, [r3, #36] @ 0x24 + 800fef4: 6a7b ldr r3, [r7, #36] @ 0x24 + 800fef6: 431a orrs r2, r3 + 800fef8: 687b ldr r3, [r7, #4] + 800fefa: 625a str r2, [r3, #36] @ 0x24 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); + 800fefc: 6878 ldr r0, [r7, #4] + 800fefe: f000 f85e bl 800ffbe +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + 800ff02: bf00 nop + 800ff04: 3728 adds r7, #40 @ 0x28 + 800ff06: 46bd mov sp, r7 + 800ff08: bd80 pop {r7, pc} + +0800ff0a : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 800ff0a: b480 push {r7} + 800ff0c: b083 sub sp, #12 + 800ff0e: af00 add r7, sp, #0 + 800ff10: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + 800ff12: bf00 nop + 800ff14: 370c adds r7, #12 + 800ff16: 46bd mov sp, r7 + 800ff18: bc80 pop {r7} + 800ff1a: 4770 bx lr + +0800ff1c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 800ff1c: b480 push {r7} + 800ff1e: b083 sub sp, #12 + 800ff20: af00 add r7, sp, #0 + 800ff22: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + 800ff24: bf00 nop + 800ff26: 370c adds r7, #12 + 800ff28: 46bd mov sp, r7 + 800ff2a: bc80 pop {r7} + 800ff2c: 4770 bx lr + +0800ff2e : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 800ff2e: b480 push {r7} + 800ff30: b083 sub sp, #12 + 800ff32: af00 add r7, sp, #0 + 800ff34: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + 800ff36: bf00 nop + 800ff38: 370c adds r7, #12 + 800ff3a: 46bd mov sp, r7 + 800ff3c: bc80 pop {r7} + 800ff3e: 4770 bx lr + +0800ff40 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + 800ff40: b480 push {r7} + 800ff42: b083 sub sp, #12 + 800ff44: af00 add r7, sp, #0 + 800ff46: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + 800ff48: bf00 nop + 800ff4a: 370c adds r7, #12 + 800ff4c: 46bd mov sp, r7 + 800ff4e: bc80 pop {r7} + 800ff50: 4770 bx lr + +0800ff52 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + 800ff52: b480 push {r7} + 800ff54: b083 sub sp, #12 + 800ff56: af00 add r7, sp, #0 + 800ff58: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + 800ff5a: bf00 nop + 800ff5c: 370c adds r7, #12 + 800ff5e: 46bd mov sp, r7 + 800ff60: bc80 pop {r7} + 800ff62: 4770 bx lr + +0800ff64 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + 800ff64: b480 push {r7} + 800ff66: b083 sub sp, #12 + 800ff68: af00 add r7, sp, #0 + 800ff6a: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + 800ff6c: bf00 nop + 800ff6e: 370c adds r7, #12 + 800ff70: 46bd mov sp, r7 + 800ff72: bc80 pop {r7} + 800ff74: 4770 bx lr + +0800ff76 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + 800ff76: b480 push {r7} + 800ff78: b083 sub sp, #12 + 800ff7a: af00 add r7, sp, #0 + 800ff7c: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + 800ff7e: bf00 nop + 800ff80: 370c adds r7, #12 + 800ff82: 46bd mov sp, r7 + 800ff84: bc80 pop {r7} + 800ff86: 4770 bx lr + +0800ff88 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + 800ff88: b480 push {r7} + 800ff8a: b083 sub sp, #12 + 800ff8c: af00 add r7, sp, #0 + 800ff8e: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + 800ff90: bf00 nop + 800ff92: 370c adds r7, #12 + 800ff94: 46bd mov sp, r7 + 800ff96: bc80 pop {r7} + 800ff98: 4770 bx lr + +0800ff9a : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + 800ff9a: b480 push {r7} + 800ff9c: b083 sub sp, #12 + 800ff9e: af00 add r7, sp, #0 + 800ffa0: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + 800ffa2: bf00 nop + 800ffa4: 370c adds r7, #12 + 800ffa6: 46bd mov sp, r7 + 800ffa8: bc80 pop {r7} + 800ffaa: 4770 bx lr + +0800ffac : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + 800ffac: b480 push {r7} + 800ffae: b083 sub sp, #12 + 800ffb0: af00 add r7, sp, #0 + 800ffb2: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + 800ffb4: bf00 nop + 800ffb6: 370c adds r7, #12 + 800ffb8: 46bd mov sp, r7 + 800ffba: bc80 pop {r7} + 800ffbc: 4770 bx lr + +0800ffbe : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + 800ffbe: b480 push {r7} + 800ffc0: b083 sub sp, #12 + 800ffc2: af00 add r7, sp, #0 + 800ffc4: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + 800ffc6: bf00 nop + 800ffc8: 370c adds r7, #12 + 800ffca: 46bd mov sp, r7 + 800ffcc: bc80 pop {r7} + 800ffce: 4770 bx lr + +0800ffd0 <__NVIC_SetPriorityGrouping>: +{ + 800ffd0: b480 push {r7} + 800ffd2: b085 sub sp, #20 + 800ffd4: af00 add r7, sp, #0 + 800ffd6: 6078 str r0, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 800ffd8: 687b ldr r3, [r7, #4] + 800ffda: f003 0307 and.w r3, r3, #7 + 800ffde: 60fb str r3, [r7, #12] + reg_value = SCB->AIRCR; /* read old register configuration */ + 800ffe0: 4b0c ldr r3, [pc, #48] @ (8010014 <__NVIC_SetPriorityGrouping+0x44>) + 800ffe2: 68db ldr r3, [r3, #12] + 800ffe4: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 800ffe6: 68ba ldr r2, [r7, #8] + 800ffe8: f64f 03ff movw r3, #63743 @ 0xf8ff + 800ffec: 4013 ands r3, r2 + 800ffee: 60bb str r3, [r7, #8] + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800fff0: 68fb ldr r3, [r7, #12] + 800fff2: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 800fff4: 68bb ldr r3, [r7, #8] + 800fff6: 4313 orrs r3, r2 + reg_value = (reg_value | + 800fff8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 800fffc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8010000: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8010002: 4a04 ldr r2, [pc, #16] @ (8010014 <__NVIC_SetPriorityGrouping+0x44>) + 8010004: 68bb ldr r3, [r7, #8] + 8010006: 60d3 str r3, [r2, #12] +} + 8010008: bf00 nop + 801000a: 3714 adds r7, #20 + 801000c: 46bd mov sp, r7 + 801000e: bc80 pop {r7} + 8010010: 4770 bx lr + 8010012: bf00 nop + 8010014: e000ed00 .word 0xe000ed00 + +08010018 <__NVIC_GetPriorityGrouping>: +{ + 8010018: b480 push {r7} + 801001a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 801001c: 4b04 ldr r3, [pc, #16] @ (8010030 <__NVIC_GetPriorityGrouping+0x18>) + 801001e: 68db ldr r3, [r3, #12] + 8010020: 0a1b lsrs r3, r3, #8 + 8010022: f003 0307 and.w r3, r3, #7 +} + 8010026: 4618 mov r0, r3 + 8010028: 46bd mov sp, r7 + 801002a: bc80 pop {r7} + 801002c: 4770 bx lr + 801002e: bf00 nop + 8010030: e000ed00 .word 0xe000ed00 + +08010034 <__NVIC_EnableIRQ>: +{ + 8010034: b480 push {r7} + 8010036: b083 sub sp, #12 + 8010038: af00 add r7, sp, #0 + 801003a: 4603 mov r3, r0 + 801003c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 801003e: f997 3007 ldrsb.w r3, [r7, #7] + 8010042: 2b00 cmp r3, #0 + 8010044: db0b blt.n 801005e <__NVIC_EnableIRQ+0x2a> + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8010046: 79fb ldrb r3, [r7, #7] + 8010048: f003 021f and.w r2, r3, #31 + 801004c: 4906 ldr r1, [pc, #24] @ (8010068 <__NVIC_EnableIRQ+0x34>) + 801004e: f997 3007 ldrsb.w r3, [r7, #7] + 8010052: 095b lsrs r3, r3, #5 + 8010054: 2001 movs r0, #1 + 8010056: fa00 f202 lsl.w r2, r0, r2 + 801005a: f841 2023 str.w r2, [r1, r3, lsl #2] +} + 801005e: bf00 nop + 8010060: 370c adds r7, #12 + 8010062: 46bd mov sp, r7 + 8010064: bc80 pop {r7} + 8010066: 4770 bx lr + 8010068: e000e100 .word 0xe000e100 + +0801006c <__NVIC_SetPriority>: +{ + 801006c: b480 push {r7} + 801006e: b083 sub sp, #12 + 8010070: af00 add r7, sp, #0 + 8010072: 4603 mov r3, r0 + 8010074: 6039 str r1, [r7, #0] + 8010076: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8010078: f997 3007 ldrsb.w r3, [r7, #7] + 801007c: 2b00 cmp r3, #0 + 801007e: db0a blt.n 8010096 <__NVIC_SetPriority+0x2a> + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8010080: 683b ldr r3, [r7, #0] + 8010082: b2da uxtb r2, r3 + 8010084: 490c ldr r1, [pc, #48] @ (80100b8 <__NVIC_SetPriority+0x4c>) + 8010086: f997 3007 ldrsb.w r3, [r7, #7] + 801008a: 0112 lsls r2, r2, #4 + 801008c: b2d2 uxtb r2, r2 + 801008e: 440b add r3, r1 + 8010090: f883 2300 strb.w r2, [r3, #768] @ 0x300 +} + 8010094: e00a b.n 80100ac <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8010096: 683b ldr r3, [r7, #0] + 8010098: b2da uxtb r2, r3 + 801009a: 4908 ldr r1, [pc, #32] @ (80100bc <__NVIC_SetPriority+0x50>) + 801009c: 79fb ldrb r3, [r7, #7] + 801009e: f003 030f and.w r3, r3, #15 + 80100a2: 3b04 subs r3, #4 + 80100a4: 0112 lsls r2, r2, #4 + 80100a6: b2d2 uxtb r2, r2 + 80100a8: 440b add r3, r1 + 80100aa: 761a strb r2, [r3, #24] +} + 80100ac: bf00 nop + 80100ae: 370c adds r7, #12 + 80100b0: 46bd mov sp, r7 + 80100b2: bc80 pop {r7} + 80100b4: 4770 bx lr + 80100b6: bf00 nop + 80100b8: e000e100 .word 0xe000e100 + 80100bc: e000ed00 .word 0xe000ed00 + +080100c0 : +{ + 80100c0: b480 push {r7} + 80100c2: b089 sub sp, #36 @ 0x24 + 80100c4: af00 add r7, sp, #0 + 80100c6: 60f8 str r0, [r7, #12] + 80100c8: 60b9 str r1, [r7, #8] + 80100ca: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80100cc: 68fb ldr r3, [r7, #12] + 80100ce: f003 0307 and.w r3, r3, #7 + 80100d2: 61fb str r3, [r7, #28] + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80100d4: 69fb ldr r3, [r7, #28] + 80100d6: f1c3 0307 rsb r3, r3, #7 + 80100da: 2b04 cmp r3, #4 + 80100dc: bf28 it cs + 80100de: 2304 movcs r3, #4 + 80100e0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80100e2: 69fb ldr r3, [r7, #28] + 80100e4: 3304 adds r3, #4 + 80100e6: 2b06 cmp r3, #6 + 80100e8: d902 bls.n 80100f0 + 80100ea: 69fb ldr r3, [r7, #28] + 80100ec: 3b03 subs r3, #3 + 80100ee: e000 b.n 80100f2 + 80100f0: 2300 movs r3, #0 + 80100f2: 617b str r3, [r7, #20] + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80100f4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80100f8: 69bb ldr r3, [r7, #24] + 80100fa: fa02 f303 lsl.w r3, r2, r3 + 80100fe: 43da mvns r2, r3 + 8010100: 68bb ldr r3, [r7, #8] + 8010102: 401a ands r2, r3 + 8010104: 697b ldr r3, [r7, #20] + 8010106: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8010108: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 801010c: 697b ldr r3, [r7, #20] + 801010e: fa01 f303 lsl.w r3, r1, r3 + 8010112: 43d9 mvns r1, r3 + 8010114: 687b ldr r3, [r7, #4] + 8010116: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8010118: 4313 orrs r3, r2 +} + 801011a: 4618 mov r0, r3 + 801011c: 3724 adds r7, #36 @ 0x24 + 801011e: 46bd mov sp, r7 + 8010120: bc80 pop {r7} + 8010122: 4770 bx lr + +08010124 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8010124: b580 push {r7, lr} + 8010126: b082 sub sp, #8 + 8010128: af00 add r7, sp, #0 + 801012a: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 801012c: 687b ldr r3, [r7, #4] + 801012e: 3b01 subs r3, #1 + 8010130: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8010134: d301 bcc.n 801013a + { + return (1UL); /* Reload value impossible */ + 8010136: 2301 movs r3, #1 + 8010138: e00f b.n 801015a + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 801013a: 4a0a ldr r2, [pc, #40] @ (8010164 ) + 801013c: 687b ldr r3, [r7, #4] + 801013e: 3b01 subs r3, #1 + 8010140: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8010142: 210f movs r1, #15 + 8010144: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8010148: f7ff ff90 bl 801006c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 801014c: 4b05 ldr r3, [pc, #20] @ (8010164 ) + 801014e: 2200 movs r2, #0 + 8010150: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8010152: 4b04 ldr r3, [pc, #16] @ (8010164 ) + 8010154: 2207 movs r2, #7 + 8010156: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8010158: 2300 movs r3, #0 +} + 801015a: 4618 mov r0, r3 + 801015c: 3708 adds r7, #8 + 801015e: 46bd mov sp, r7 + 8010160: bd80 pop {r7, pc} + 8010162: bf00 nop + 8010164: e000e010 .word 0xe000e010 + +08010168 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8010168: b580 push {r7, lr} + 801016a: b082 sub sp, #8 + 801016c: af00 add r7, sp, #0 + 801016e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8010170: 6878 ldr r0, [r7, #4] + 8010172: f7ff ff2d bl 800ffd0 <__NVIC_SetPriorityGrouping> +} + 8010176: bf00 nop + 8010178: 3708 adds r7, #8 + 801017a: 46bd mov sp, r7 + 801017c: bd80 pop {r7, pc} + +0801017e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 801017e: b580 push {r7, lr} + 8010180: b086 sub sp, #24 + 8010182: af00 add r7, sp, #0 + 8010184: 4603 mov r3, r0 + 8010186: 60b9 str r1, [r7, #8] + 8010188: 607a str r2, [r7, #4] + 801018a: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 801018c: 2300 movs r3, #0 + 801018e: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8010190: f7ff ff42 bl 8010018 <__NVIC_GetPriorityGrouping> + 8010194: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8010196: 687a ldr r2, [r7, #4] + 8010198: 68b9 ldr r1, [r7, #8] + 801019a: 6978 ldr r0, [r7, #20] + 801019c: f7ff ff90 bl 80100c0 + 80101a0: 4602 mov r2, r0 + 80101a2: f997 300f ldrsb.w r3, [r7, #15] + 80101a6: 4611 mov r1, r2 + 80101a8: 4618 mov r0, r3 + 80101aa: f7ff ff5f bl 801006c <__NVIC_SetPriority> +} + 80101ae: bf00 nop + 80101b0: 3718 adds r7, #24 + 80101b2: 46bd mov sp, r7 + 80101b4: bd80 pop {r7, pc} + +080101b6 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80101b6: b580 push {r7, lr} + 80101b8: b082 sub sp, #8 + 80101ba: af00 add r7, sp, #0 + 80101bc: 4603 mov r3, r0 + 80101be: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80101c0: f997 3007 ldrsb.w r3, [r7, #7] + 80101c4: 4618 mov r0, r3 + 80101c6: f7ff ff35 bl 8010034 <__NVIC_EnableIRQ> +} + 80101ca: bf00 nop + 80101cc: 3708 adds r7, #8 + 80101ce: 46bd mov sp, r7 + 80101d0: bd80 pop {r7, pc} + +080101d2 : + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80101d2: b580 push {r7, lr} + 80101d4: b082 sub sp, #8 + 80101d6: af00 add r7, sp, #0 + 80101d8: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 80101da: 6878 ldr r0, [r7, #4] + 80101dc: f7ff ffa2 bl 8010124 + 80101e0: 4603 mov r3, r0 +} + 80101e2: 4618 mov r0, r3 + 80101e4: 3708 adds r7, #8 + 80101e6: 46bd mov sp, r7 + 80101e8: bd80 pop {r7, pc} + +080101ea : + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + 80101ea: b580 push {r7, lr} + 80101ec: b082 sub sp, #8 + 80101ee: af00 add r7, sp, #0 + 80101f0: 6078 str r0, [r7, #4] + /* Check the CRC handle allocation */ + if (hcrc == NULL) + 80101f2: 687b ldr r3, [r7, #4] + 80101f4: 2b00 cmp r3, #0 + 80101f6: d101 bne.n 80101fc + { + return HAL_ERROR; + 80101f8: 2301 movs r3, #1 + 80101fa: e00e b.n 801021a + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + 80101fc: 687b ldr r3, [r7, #4] + 80101fe: 795b ldrb r3, [r3, #5] + 8010200: b2db uxtb r3, r3 + 8010202: 2b00 cmp r3, #0 + 8010204: d105 bne.n 8010212 + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + 8010206: 687b ldr r3, [r7, #4] + 8010208: 2200 movs r2, #0 + 801020a: 711a strb r2, [r3, #4] + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + 801020c: 6878 ldr r0, [r7, #4] + 801020e: f7fb f825 bl 800b25c + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + 8010212: 687b ldr r3, [r7, #4] + 8010214: 2201 movs r2, #1 + 8010216: 715a strb r2, [r3, #5] + + /* Return function status */ + return HAL_OK; + 8010218: 2300 movs r3, #0 +} + 801021a: 4618 mov r0, r3 + 801021c: 3708 adds r7, #8 + 801021e: 46bd mov sp, r7 + 8010220: bd80 pop {r7, pc} + +08010222 : + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + 8010222: b480 push {r7} + 8010224: b085 sub sp, #20 + 8010226: af00 add r7, sp, #0 + 8010228: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 801022a: 2300 movs r3, #0 + 801022c: 73fb strb r3, [r7, #15] + + if(hdma->State != HAL_DMA_STATE_BUSY) + 801022e: 687b ldr r3, [r7, #4] + 8010230: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 8010234: b2db uxtb r3, r3 + 8010236: 2b02 cmp r3, #2 + 8010238: d008 beq.n 801024c + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 801023a: 687b ldr r3, [r7, #4] + 801023c: 2204 movs r2, #4 + 801023e: 639a str r2, [r3, #56] @ 0x38 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8010240: 687b ldr r3, [r7, #4] + 8010242: 2200 movs r2, #0 + 8010244: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 8010248: 2301 movs r3, #1 + 801024a: e020 b.n 801028e + } + else + + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 801024c: 687b ldr r3, [r7, #4] + 801024e: 681b ldr r3, [r3, #0] + 8010250: 681a ldr r2, [r3, #0] + 8010252: 687b ldr r3, [r7, #4] + 8010254: 681b ldr r3, [r3, #0] + 8010256: f022 020e bic.w r2, r2, #14 + 801025a: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 801025c: 687b ldr r3, [r7, #4] + 801025e: 681b ldr r3, [r3, #0] + 8010260: 681a ldr r2, [r3, #0] + 8010262: 687b ldr r3, [r7, #4] + 8010264: 681b ldr r3, [r3, #0] + 8010266: f022 0201 bic.w r2, r2, #1 + 801026a: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + 801026c: 687b ldr r3, [r7, #4] + 801026e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8010270: 687b ldr r3, [r7, #4] + 8010272: 6bdb ldr r3, [r3, #60] @ 0x3c + 8010274: 2101 movs r1, #1 + 8010276: fa01 f202 lsl.w r2, r1, r2 + 801027a: 605a str r2, [r3, #4] + } + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 801027c: 687b ldr r3, [r7, #4] + 801027e: 2201 movs r2, #1 + 8010280: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8010284: 687b ldr r3, [r7, #4] + 8010286: 2200 movs r2, #0 + 8010288: f883 2020 strb.w r2, [r3, #32] + + return status; + 801028c: 7bfb ldrb r3, [r7, #15] +} + 801028e: 4618 mov r0, r3 + 8010290: 3714 adds r7, #20 + 8010292: 46bd mov sp, r7 + 8010294: bc80 pop {r7} + 8010296: 4770 bx lr + +08010298 : + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8010298: b580 push {r7, lr} + 801029a: b084 sub sp, #16 + 801029c: af00 add r7, sp, #0 + 801029e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80102a0: 2300 movs r3, #0 + 80102a2: 73fb strb r3, [r7, #15] + + if(HAL_DMA_STATE_BUSY != hdma->State) + 80102a4: 687b ldr r3, [r7, #4] + 80102a6: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 + 80102aa: b2db uxtb r3, r3 + 80102ac: 2b02 cmp r3, #2 + 80102ae: d005 beq.n 80102bc + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 80102b0: 687b ldr r3, [r7, #4] + 80102b2: 2204 movs r2, #4 + 80102b4: 639a str r2, [r3, #56] @ 0x38 + + status = HAL_ERROR; + 80102b6: 2301 movs r3, #1 + 80102b8: 73fb strb r3, [r7, #15] + 80102ba: e0d6 b.n 801046a + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 80102bc: 687b ldr r3, [r7, #4] + 80102be: 681b ldr r3, [r3, #0] + 80102c0: 681a ldr r2, [r3, #0] + 80102c2: 687b ldr r3, [r7, #4] + 80102c4: 681b ldr r3, [r3, #0] + 80102c6: f022 020e bic.w r2, r2, #14 + 80102ca: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 80102cc: 687b ldr r3, [r7, #4] + 80102ce: 681b ldr r3, [r3, #0] + 80102d0: 681a ldr r2, [r3, #0] + 80102d2: 687b ldr r3, [r7, #4] + 80102d4: 681b ldr r3, [r3, #0] + 80102d6: f022 0201 bic.w r2, r2, #1 + 80102da: 601a str r2, [r3, #0] + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + 80102dc: 687b ldr r3, [r7, #4] + 80102de: 681b ldr r3, [r3, #0] + 80102e0: 461a mov r2, r3 + 80102e2: 4b64 ldr r3, [pc, #400] @ (8010474 ) + 80102e4: 429a cmp r2, r3 + 80102e6: d958 bls.n 801039a + 80102e8: 687b ldr r3, [r7, #4] + 80102ea: 681b ldr r3, [r3, #0] + 80102ec: 4a62 ldr r2, [pc, #392] @ (8010478 ) + 80102ee: 4293 cmp r3, r2 + 80102f0: d04f beq.n 8010392 + 80102f2: 687b ldr r3, [r7, #4] + 80102f4: 681b ldr r3, [r3, #0] + 80102f6: 4a61 ldr r2, [pc, #388] @ (801047c ) + 80102f8: 4293 cmp r3, r2 + 80102fa: d048 beq.n 801038e + 80102fc: 687b ldr r3, [r7, #4] + 80102fe: 681b ldr r3, [r3, #0] + 8010300: 4a5f ldr r2, [pc, #380] @ (8010480 ) + 8010302: 4293 cmp r3, r2 + 8010304: d040 beq.n 8010388 + 8010306: 687b ldr r3, [r7, #4] + 8010308: 681b ldr r3, [r3, #0] + 801030a: 4a5e ldr r2, [pc, #376] @ (8010484 ) + 801030c: 4293 cmp r3, r2 + 801030e: d038 beq.n 8010382 + 8010310: 687b ldr r3, [r7, #4] + 8010312: 681b ldr r3, [r3, #0] + 8010314: 4a5c ldr r2, [pc, #368] @ (8010488 ) + 8010316: 4293 cmp r3, r2 + 8010318: d030 beq.n 801037c + 801031a: 687b ldr r3, [r7, #4] + 801031c: 681b ldr r3, [r3, #0] + 801031e: 4a5b ldr r2, [pc, #364] @ (801048c ) + 8010320: 4293 cmp r3, r2 + 8010322: d028 beq.n 8010376 + 8010324: 687b ldr r3, [r7, #4] + 8010326: 681b ldr r3, [r3, #0] + 8010328: 4a52 ldr r2, [pc, #328] @ (8010474 ) + 801032a: 4293 cmp r3, r2 + 801032c: d020 beq.n 8010370 + 801032e: 687b ldr r3, [r7, #4] + 8010330: 681b ldr r3, [r3, #0] + 8010332: 4a57 ldr r2, [pc, #348] @ (8010490 ) + 8010334: 4293 cmp r3, r2 + 8010336: d019 beq.n 801036c + 8010338: 687b ldr r3, [r7, #4] + 801033a: 681b ldr r3, [r3, #0] + 801033c: 4a55 ldr r2, [pc, #340] @ (8010494 ) + 801033e: 4293 cmp r3, r2 + 8010340: d012 beq.n 8010368 + 8010342: 687b ldr r3, [r7, #4] + 8010344: 681b ldr r3, [r3, #0] + 8010346: 4a54 ldr r2, [pc, #336] @ (8010498 ) + 8010348: 4293 cmp r3, r2 + 801034a: d00a beq.n 8010362 + 801034c: 687b ldr r3, [r7, #4] + 801034e: 681b ldr r3, [r3, #0] + 8010350: 4a52 ldr r2, [pc, #328] @ (801049c ) + 8010352: 4293 cmp r3, r2 + 8010354: d102 bne.n 801035c + 8010356: f44f 5380 mov.w r3, #4096 @ 0x1000 + 801035a: e01b b.n 8010394 + 801035c: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8010360: e018 b.n 8010394 + 8010362: f44f 7380 mov.w r3, #256 @ 0x100 + 8010366: e015 b.n 8010394 + 8010368: 2310 movs r3, #16 + 801036a: e013 b.n 8010394 + 801036c: 2301 movs r3, #1 + 801036e: e011 b.n 8010394 + 8010370: f04f 7380 mov.w r3, #16777216 @ 0x1000000 + 8010374: e00e b.n 8010394 + 8010376: f44f 1380 mov.w r3, #1048576 @ 0x100000 + 801037a: e00b b.n 8010394 + 801037c: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8010380: e008 b.n 8010394 + 8010382: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8010386: e005 b.n 8010394 + 8010388: f44f 7380 mov.w r3, #256 @ 0x100 + 801038c: e002 b.n 8010394 + 801038e: 2310 movs r3, #16 + 8010390: e000 b.n 8010394 + 8010392: 2301 movs r3, #1 + 8010394: 4a42 ldr r2, [pc, #264] @ (80104a0 ) + 8010396: 6053 str r3, [r2, #4] + 8010398: e057 b.n 801044a + 801039a: 687b ldr r3, [r7, #4] + 801039c: 681b ldr r3, [r3, #0] + 801039e: 4a36 ldr r2, [pc, #216] @ (8010478 ) + 80103a0: 4293 cmp r3, r2 + 80103a2: d04f beq.n 8010444 + 80103a4: 687b ldr r3, [r7, #4] + 80103a6: 681b ldr r3, [r3, #0] + 80103a8: 4a34 ldr r2, [pc, #208] @ (801047c ) + 80103aa: 4293 cmp r3, r2 + 80103ac: d048 beq.n 8010440 + 80103ae: 687b ldr r3, [r7, #4] + 80103b0: 681b ldr r3, [r3, #0] + 80103b2: 4a33 ldr r2, [pc, #204] @ (8010480 ) + 80103b4: 4293 cmp r3, r2 + 80103b6: d040 beq.n 801043a + 80103b8: 687b ldr r3, [r7, #4] + 80103ba: 681b ldr r3, [r3, #0] + 80103bc: 4a31 ldr r2, [pc, #196] @ (8010484 ) + 80103be: 4293 cmp r3, r2 + 80103c0: d038 beq.n 8010434 + 80103c2: 687b ldr r3, [r7, #4] + 80103c4: 681b ldr r3, [r3, #0] + 80103c6: 4a30 ldr r2, [pc, #192] @ (8010488 ) + 80103c8: 4293 cmp r3, r2 + 80103ca: d030 beq.n 801042e + 80103cc: 687b ldr r3, [r7, #4] + 80103ce: 681b ldr r3, [r3, #0] + 80103d0: 4a2e ldr r2, [pc, #184] @ (801048c ) + 80103d2: 4293 cmp r3, r2 + 80103d4: d028 beq.n 8010428 + 80103d6: 687b ldr r3, [r7, #4] + 80103d8: 681b ldr r3, [r3, #0] + 80103da: 4a26 ldr r2, [pc, #152] @ (8010474 ) + 80103dc: 4293 cmp r3, r2 + 80103de: d020 beq.n 8010422 + 80103e0: 687b ldr r3, [r7, #4] + 80103e2: 681b ldr r3, [r3, #0] + 80103e4: 4a2a ldr r2, [pc, #168] @ (8010490 ) + 80103e6: 4293 cmp r3, r2 + 80103e8: d019 beq.n 801041e + 80103ea: 687b ldr r3, [r7, #4] + 80103ec: 681b ldr r3, [r3, #0] + 80103ee: 4a29 ldr r2, [pc, #164] @ (8010494 ) + 80103f0: 4293 cmp r3, r2 + 80103f2: d012 beq.n 801041a + 80103f4: 687b ldr r3, [r7, #4] + 80103f6: 681b ldr r3, [r3, #0] + 80103f8: 4a27 ldr r2, [pc, #156] @ (8010498 ) + 80103fa: 4293 cmp r3, r2 + 80103fc: d00a beq.n 8010414 + 80103fe: 687b ldr r3, [r7, #4] + 8010400: 681b ldr r3, [r3, #0] + 8010402: 4a26 ldr r2, [pc, #152] @ (801049c ) + 8010404: 4293 cmp r3, r2 + 8010406: d102 bne.n 801040e + 8010408: f44f 5380 mov.w r3, #4096 @ 0x1000 + 801040c: e01b b.n 8010446 + 801040e: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8010412: e018 b.n 8010446 + 8010414: f44f 7380 mov.w r3, #256 @ 0x100 + 8010418: e015 b.n 8010446 + 801041a: 2310 movs r3, #16 + 801041c: e013 b.n 8010446 + 801041e: 2301 movs r3, #1 + 8010420: e011 b.n 8010446 + 8010422: f04f 7380 mov.w r3, #16777216 @ 0x1000000 + 8010426: e00e b.n 8010446 + 8010428: f44f 1380 mov.w r3, #1048576 @ 0x100000 + 801042c: e00b b.n 8010446 + 801042e: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8010432: e008 b.n 8010446 + 8010434: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8010438: e005 b.n 8010446 + 801043a: f44f 7380 mov.w r3, #256 @ 0x100 + 801043e: e002 b.n 8010446 + 8010440: 2310 movs r3, #16 + 8010442: e000 b.n 8010446 + 8010444: 2301 movs r3, #1 + 8010446: 4a17 ldr r2, [pc, #92] @ (80104a4 ) + 8010448: 6053 str r3, [r2, #4] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 801044a: 687b ldr r3, [r7, #4] + 801044c: 2201 movs r2, #1 + 801044e: f883 2021 strb.w r2, [r3, #33] @ 0x21 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8010452: 687b ldr r3, [r7, #4] + 8010454: 2200 movs r2, #0 + 8010456: f883 2020 strb.w r2, [r3, #32] + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + 801045a: 687b ldr r3, [r7, #4] + 801045c: 6b5b ldr r3, [r3, #52] @ 0x34 + 801045e: 2b00 cmp r3, #0 + 8010460: d003 beq.n 801046a + { + hdma->XferAbortCallback(hdma); + 8010462: 687b ldr r3, [r7, #4] + 8010464: 6b5b ldr r3, [r3, #52] @ 0x34 + 8010466: 6878 ldr r0, [r7, #4] + 8010468: 4798 blx r3 + } + } + return status; + 801046a: 7bfb ldrb r3, [r7, #15] +} + 801046c: 4618 mov r0, r3 + 801046e: 3710 adds r7, #16 + 8010470: 46bd mov sp, r7 + 8010472: bd80 pop {r7, pc} + 8010474: 40020080 .word 0x40020080 + 8010478: 40020008 .word 0x40020008 + 801047c: 4002001c .word 0x4002001c + 8010480: 40020030 .word 0x40020030 + 8010484: 40020044 .word 0x40020044 + 8010488: 40020058 .word 0x40020058 + 801048c: 4002006c .word 0x4002006c + 8010490: 40020408 .word 0x40020408 + 8010494: 4002041c .word 0x4002041c + 8010498: 40020430 .word 0x40020430 + 801049c: 40020444 .word 0x40020444 + 80104a0: 40020400 .word 0x40020400 + 80104a4: 40020000 .word 0x40020000 + +080104a8 : + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80104a8: b480 push {r7} + 80104aa: b08b sub sp, #44 @ 0x2c + 80104ac: af00 add r7, sp, #0 + 80104ae: 6078 str r0, [r7, #4] + 80104b0: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80104b2: 2300 movs r3, #0 + 80104b4: 627b str r3, [r7, #36] @ 0x24 + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; + 80104b6: 2300 movs r3, #0 + 80104b8: 623b str r3, [r7, #32] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80104ba: e169 b.n 8010790 + { + /* Get the IO position */ + ioposition = (0x01uL << position); + 80104bc: 2201 movs r2, #1 + 80104be: 6a7b ldr r3, [r7, #36] @ 0x24 + 80104c0: fa02 f303 lsl.w r3, r2, r3 + 80104c4: 61fb str r3, [r7, #28] + + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 80104c6: 683b ldr r3, [r7, #0] + 80104c8: 681b ldr r3, [r3, #0] + 80104ca: 69fa ldr r2, [r7, #28] + 80104cc: 4013 ands r3, r2 + 80104ce: 61bb str r3, [r7, #24] + + if (iocurrent == ioposition) + 80104d0: 69ba ldr r2, [r7, #24] + 80104d2: 69fb ldr r3, [r7, #28] + 80104d4: 429a cmp r2, r3 + 80104d6: f040 8158 bne.w 801078a + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + + /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ + switch (GPIO_Init->Mode) + 80104da: 683b ldr r3, [r7, #0] + 80104dc: 685b ldr r3, [r3, #4] + 80104de: 4a9a ldr r2, [pc, #616] @ (8010748 ) + 80104e0: 4293 cmp r3, r2 + 80104e2: d05e beq.n 80105a2 + 80104e4: 4a98 ldr r2, [pc, #608] @ (8010748 ) + 80104e6: 4293 cmp r3, r2 + 80104e8: d875 bhi.n 80105d6 + 80104ea: 4a98 ldr r2, [pc, #608] @ (801074c ) + 80104ec: 4293 cmp r3, r2 + 80104ee: d058 beq.n 80105a2 + 80104f0: 4a96 ldr r2, [pc, #600] @ (801074c ) + 80104f2: 4293 cmp r3, r2 + 80104f4: d86f bhi.n 80105d6 + 80104f6: 4a96 ldr r2, [pc, #600] @ (8010750 ) + 80104f8: 4293 cmp r3, r2 + 80104fa: d052 beq.n 80105a2 + 80104fc: 4a94 ldr r2, [pc, #592] @ (8010750 ) + 80104fe: 4293 cmp r3, r2 + 8010500: d869 bhi.n 80105d6 + 8010502: 4a94 ldr r2, [pc, #592] @ (8010754 ) + 8010504: 4293 cmp r3, r2 + 8010506: d04c beq.n 80105a2 + 8010508: 4a92 ldr r2, [pc, #584] @ (8010754 ) + 801050a: 4293 cmp r3, r2 + 801050c: d863 bhi.n 80105d6 + 801050e: 4a92 ldr r2, [pc, #584] @ (8010758 ) + 8010510: 4293 cmp r3, r2 + 8010512: d046 beq.n 80105a2 + 8010514: 4a90 ldr r2, [pc, #576] @ (8010758 ) + 8010516: 4293 cmp r3, r2 + 8010518: d85d bhi.n 80105d6 + 801051a: 2b12 cmp r3, #18 + 801051c: d82a bhi.n 8010574 + 801051e: 2b12 cmp r3, #18 + 8010520: d859 bhi.n 80105d6 + 8010522: a201 add r2, pc, #4 @ (adr r2, 8010528 ) + 8010524: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8010528: 080105a3 .word 0x080105a3 + 801052c: 0801057d .word 0x0801057d + 8010530: 0801058f .word 0x0801058f + 8010534: 080105d1 .word 0x080105d1 + 8010538: 080105d7 .word 0x080105d7 + 801053c: 080105d7 .word 0x080105d7 + 8010540: 080105d7 .word 0x080105d7 + 8010544: 080105d7 .word 0x080105d7 + 8010548: 080105d7 .word 0x080105d7 + 801054c: 080105d7 .word 0x080105d7 + 8010550: 080105d7 .word 0x080105d7 + 8010554: 080105d7 .word 0x080105d7 + 8010558: 080105d7 .word 0x080105d7 + 801055c: 080105d7 .word 0x080105d7 + 8010560: 080105d7 .word 0x080105d7 + 8010564: 080105d7 .word 0x080105d7 + 8010568: 080105d7 .word 0x080105d7 + 801056c: 08010585 .word 0x08010585 + 8010570: 08010599 .word 0x08010599 + 8010574: 4a79 ldr r2, [pc, #484] @ (801075c ) + 8010576: 4293 cmp r3, r2 + 8010578: d013 beq.n 80105a2 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + break; + + /* Parameters are checked with assert_param */ + default: + break; + 801057a: e02c b.n 80105d6 + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; + 801057c: 683b ldr r3, [r7, #0] + 801057e: 68db ldr r3, [r3, #12] + 8010580: 623b str r3, [r7, #32] + break; + 8010582: e029 b.n 80105d8 + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; + 8010584: 683b ldr r3, [r7, #0] + 8010586: 68db ldr r3, [r3, #12] + 8010588: 3304 adds r3, #4 + 801058a: 623b str r3, [r7, #32] + break; + 801058c: e024 b.n 80105d8 + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; + 801058e: 683b ldr r3, [r7, #0] + 8010590: 68db ldr r3, [r3, #12] + 8010592: 3308 adds r3, #8 + 8010594: 623b str r3, [r7, #32] + break; + 8010596: e01f b.n 80105d8 + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; + 8010598: 683b ldr r3, [r7, #0] + 801059a: 68db ldr r3, [r3, #12] + 801059c: 330c adds r3, #12 + 801059e: 623b str r3, [r7, #32] + break; + 80105a0: e01a b.n 80105d8 + if (GPIO_Init->Pull == GPIO_NOPULL) + 80105a2: 683b ldr r3, [r7, #0] + 80105a4: 689b ldr r3, [r3, #8] + 80105a6: 2b00 cmp r3, #0 + 80105a8: d102 bne.n 80105b0 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; + 80105aa: 2304 movs r3, #4 + 80105ac: 623b str r3, [r7, #32] + break; + 80105ae: e013 b.n 80105d8 + else if (GPIO_Init->Pull == GPIO_PULLUP) + 80105b0: 683b ldr r3, [r7, #0] + 80105b2: 689b ldr r3, [r3, #8] + 80105b4: 2b01 cmp r3, #1 + 80105b6: d105 bne.n 80105c4 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80105b8: 2308 movs r3, #8 + 80105ba: 623b str r3, [r7, #32] + GPIOx->BSRR = ioposition; + 80105bc: 687b ldr r3, [r7, #4] + 80105be: 69fa ldr r2, [r7, #28] + 80105c0: 611a str r2, [r3, #16] + break; + 80105c2: e009 b.n 80105d8 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80105c4: 2308 movs r3, #8 + 80105c6: 623b str r3, [r7, #32] + GPIOx->BRR = ioposition; + 80105c8: 687b ldr r3, [r7, #4] + 80105ca: 69fa ldr r2, [r7, #28] + 80105cc: 615a str r2, [r3, #20] + break; + 80105ce: e003 b.n 80105d8 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + 80105d0: 2300 movs r3, #0 + 80105d2: 623b str r3, [r7, #32] + break; + 80105d4: e000 b.n 80105d8 + break; + 80105d6: bf00 nop + } + + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register*/ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + 80105d8: 69bb ldr r3, [r7, #24] + 80105da: 2bff cmp r3, #255 @ 0xff + 80105dc: d801 bhi.n 80105e2 + 80105de: 687b ldr r3, [r7, #4] + 80105e0: e001 b.n 80105e6 + 80105e2: 687b ldr r3, [r7, #4] + 80105e4: 3304 adds r3, #4 + 80105e6: 617b str r3, [r7, #20] + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + 80105e8: 69bb ldr r3, [r7, #24] + 80105ea: 2bff cmp r3, #255 @ 0xff + 80105ec: d802 bhi.n 80105f4 + 80105ee: 6a7b ldr r3, [r7, #36] @ 0x24 + 80105f0: 009b lsls r3, r3, #2 + 80105f2: e002 b.n 80105fa + 80105f4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80105f6: 3b08 subs r3, #8 + 80105f8: 009b lsls r3, r3, #2 + 80105fa: 613b str r3, [r7, #16] + + /* Apply the new configuration of the pin to the register */ + MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); + 80105fc: 697b ldr r3, [r7, #20] + 80105fe: 681a ldr r2, [r3, #0] + 8010600: 210f movs r1, #15 + 8010602: 693b ldr r3, [r7, #16] + 8010604: fa01 f303 lsl.w r3, r1, r3 + 8010608: 43db mvns r3, r3 + 801060a: 401a ands r2, r3 + 801060c: 6a39 ldr r1, [r7, #32] + 801060e: 693b ldr r3, [r7, #16] + 8010610: fa01 f303 lsl.w r3, r1, r3 + 8010614: 431a orrs r2, r3 + 8010616: 697b ldr r3, [r7, #20] + 8010618: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 801061a: 683b ldr r3, [r7, #0] + 801061c: 685b ldr r3, [r3, #4] + 801061e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8010622: 2b00 cmp r3, #0 + 8010624: f000 80b1 beq.w 801078a + { + /* Enable AFIO Clock */ + __HAL_RCC_AFIO_CLK_ENABLE(); + 8010628: 4b4d ldr r3, [pc, #308] @ (8010760 ) + 801062a: 699b ldr r3, [r3, #24] + 801062c: 4a4c ldr r2, [pc, #304] @ (8010760 ) + 801062e: f043 0301 orr.w r3, r3, #1 + 8010632: 6193 str r3, [r2, #24] + 8010634: 4b4a ldr r3, [pc, #296] @ (8010760 ) + 8010636: 699b ldr r3, [r3, #24] + 8010638: f003 0301 and.w r3, r3, #1 + 801063c: 60bb str r3, [r7, #8] + 801063e: 68bb ldr r3, [r7, #8] + temp = AFIO->EXTICR[position >> 2u]; + 8010640: 4a48 ldr r2, [pc, #288] @ (8010764 ) + 8010642: 6a7b ldr r3, [r7, #36] @ 0x24 + 8010644: 089b lsrs r3, r3, #2 + 8010646: 3302 adds r3, #2 + 8010648: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 801064c: 60fb str r3, [r7, #12] + CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); + 801064e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8010650: f003 0303 and.w r3, r3, #3 + 8010654: 009b lsls r3, r3, #2 + 8010656: 220f movs r2, #15 + 8010658: fa02 f303 lsl.w r3, r2, r3 + 801065c: 43db mvns r3, r3 + 801065e: 68fa ldr r2, [r7, #12] + 8010660: 4013 ands r3, r2 + 8010662: 60fb str r3, [r7, #12] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); + 8010664: 687b ldr r3, [r7, #4] + 8010666: 4a40 ldr r2, [pc, #256] @ (8010768 ) + 8010668: 4293 cmp r3, r2 + 801066a: d013 beq.n 8010694 + 801066c: 687b ldr r3, [r7, #4] + 801066e: 4a3f ldr r2, [pc, #252] @ (801076c ) + 8010670: 4293 cmp r3, r2 + 8010672: d00d beq.n 8010690 + 8010674: 687b ldr r3, [r7, #4] + 8010676: 4a3e ldr r2, [pc, #248] @ (8010770 ) + 8010678: 4293 cmp r3, r2 + 801067a: d007 beq.n 801068c + 801067c: 687b ldr r3, [r7, #4] + 801067e: 4a3d ldr r2, [pc, #244] @ (8010774 ) + 8010680: 4293 cmp r3, r2 + 8010682: d101 bne.n 8010688 + 8010684: 2303 movs r3, #3 + 8010686: e006 b.n 8010696 + 8010688: 2304 movs r3, #4 + 801068a: e004 b.n 8010696 + 801068c: 2302 movs r3, #2 + 801068e: e002 b.n 8010696 + 8010690: 2301 movs r3, #1 + 8010692: e000 b.n 8010696 + 8010694: 2300 movs r3, #0 + 8010696: 6a7a ldr r2, [r7, #36] @ 0x24 + 8010698: f002 0203 and.w r2, r2, #3 + 801069c: 0092 lsls r2, r2, #2 + 801069e: 4093 lsls r3, r2 + 80106a0: 68fa ldr r2, [r7, #12] + 80106a2: 4313 orrs r3, r2 + 80106a4: 60fb str r3, [r7, #12] + AFIO->EXTICR[position >> 2u] = temp; + 80106a6: 492f ldr r1, [pc, #188] @ (8010764 ) + 80106a8: 6a7b ldr r3, [r7, #36] @ 0x24 + 80106aa: 089b lsrs r3, r3, #2 + 80106ac: 3302 adds r3, #2 + 80106ae: 68fa ldr r2, [r7, #12] + 80106b0: f841 2023 str.w r2, [r1, r3, lsl #2] + + + /* Enable or disable the rising trigger */ + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 80106b4: 683b ldr r3, [r7, #0] + 80106b6: 685b ldr r3, [r3, #4] + 80106b8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 80106bc: 2b00 cmp r3, #0 + 80106be: d006 beq.n 80106ce + { + SET_BIT(EXTI->RTSR, iocurrent); + 80106c0: 4b2d ldr r3, [pc, #180] @ (8010778 ) + 80106c2: 689a ldr r2, [r3, #8] + 80106c4: 492c ldr r1, [pc, #176] @ (8010778 ) + 80106c6: 69bb ldr r3, [r7, #24] + 80106c8: 4313 orrs r3, r2 + 80106ca: 608b str r3, [r1, #8] + 80106cc: e006 b.n 80106dc + } + else + { + CLEAR_BIT(EXTI->RTSR, iocurrent); + 80106ce: 4b2a ldr r3, [pc, #168] @ (8010778 ) + 80106d0: 689a ldr r2, [r3, #8] + 80106d2: 69bb ldr r3, [r7, #24] + 80106d4: 43db mvns r3, r3 + 80106d6: 4928 ldr r1, [pc, #160] @ (8010778 ) + 80106d8: 4013 ands r3, r2 + 80106da: 608b str r3, [r1, #8] + } + + /* Enable or disable the falling trigger */ + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 80106dc: 683b ldr r3, [r7, #0] + 80106de: 685b ldr r3, [r3, #4] + 80106e0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 80106e4: 2b00 cmp r3, #0 + 80106e6: d006 beq.n 80106f6 + { + SET_BIT(EXTI->FTSR, iocurrent); + 80106e8: 4b23 ldr r3, [pc, #140] @ (8010778 ) + 80106ea: 68da ldr r2, [r3, #12] + 80106ec: 4922 ldr r1, [pc, #136] @ (8010778 ) + 80106ee: 69bb ldr r3, [r7, #24] + 80106f0: 4313 orrs r3, r2 + 80106f2: 60cb str r3, [r1, #12] + 80106f4: e006 b.n 8010704 + } + else + { + CLEAR_BIT(EXTI->FTSR, iocurrent); + 80106f6: 4b20 ldr r3, [pc, #128] @ (8010778 ) + 80106f8: 68da ldr r2, [r3, #12] + 80106fa: 69bb ldr r3, [r7, #24] + 80106fc: 43db mvns r3, r3 + 80106fe: 491e ldr r1, [pc, #120] @ (8010778 ) + 8010700: 4013 ands r3, r2 + 8010702: 60cb str r3, [r1, #12] + } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 8010704: 683b ldr r3, [r7, #0] + 8010706: 685b ldr r3, [r3, #4] + 8010708: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 801070c: 2b00 cmp r3, #0 + 801070e: d006 beq.n 801071e + { + SET_BIT(EXTI->EMR, iocurrent); + 8010710: 4b19 ldr r3, [pc, #100] @ (8010778 ) + 8010712: 685a ldr r2, [r3, #4] + 8010714: 4918 ldr r1, [pc, #96] @ (8010778 ) + 8010716: 69bb ldr r3, [r7, #24] + 8010718: 4313 orrs r3, r2 + 801071a: 604b str r3, [r1, #4] + 801071c: e006 b.n 801072c + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + 801071e: 4b16 ldr r3, [pc, #88] @ (8010778 ) + 8010720: 685a ldr r2, [r3, #4] + 8010722: 69bb ldr r3, [r7, #24] + 8010724: 43db mvns r3, r3 + 8010726: 4914 ldr r1, [pc, #80] @ (8010778 ) + 8010728: 4013 ands r3, r2 + 801072a: 604b str r3, [r1, #4] + } + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 801072c: 683b ldr r3, [r7, #0] + 801072e: 685b ldr r3, [r3, #4] + 8010730: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8010734: 2b00 cmp r3, #0 + 8010736: d021 beq.n 801077c + { + SET_BIT(EXTI->IMR, iocurrent); + 8010738: 4b0f ldr r3, [pc, #60] @ (8010778 ) + 801073a: 681a ldr r2, [r3, #0] + 801073c: 490e ldr r1, [pc, #56] @ (8010778 ) + 801073e: 69bb ldr r3, [r7, #24] + 8010740: 4313 orrs r3, r2 + 8010742: 600b str r3, [r1, #0] + 8010744: e021 b.n 801078a + 8010746: bf00 nop + 8010748: 10320000 .word 0x10320000 + 801074c: 10310000 .word 0x10310000 + 8010750: 10220000 .word 0x10220000 + 8010754: 10210000 .word 0x10210000 + 8010758: 10120000 .word 0x10120000 + 801075c: 10110000 .word 0x10110000 + 8010760: 40021000 .word 0x40021000 + 8010764: 40010000 .word 0x40010000 + 8010768: 40010800 .word 0x40010800 + 801076c: 40010c00 .word 0x40010c00 + 8010770: 40011000 .word 0x40011000 + 8010774: 40011400 .word 0x40011400 + 8010778: 40010400 .word 0x40010400 + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + 801077c: 4b0b ldr r3, [pc, #44] @ (80107ac ) + 801077e: 681a ldr r2, [r3, #0] + 8010780: 69bb ldr r3, [r7, #24] + 8010782: 43db mvns r3, r3 + 8010784: 4909 ldr r1, [pc, #36] @ (80107ac ) + 8010786: 4013 ands r3, r2 + 8010788: 600b str r3, [r1, #0] + } + } + } + + position++; + 801078a: 6a7b ldr r3, [r7, #36] @ 0x24 + 801078c: 3301 adds r3, #1 + 801078e: 627b str r3, [r7, #36] @ 0x24 + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8010790: 683b ldr r3, [r7, #0] + 8010792: 681a ldr r2, [r3, #0] + 8010794: 6a7b ldr r3, [r7, #36] @ 0x24 + 8010796: fa22 f303 lsr.w r3, r2, r3 + 801079a: 2b00 cmp r3, #0 + 801079c: f47f ae8e bne.w 80104bc + } +} + 80107a0: bf00 nop + 80107a2: bf00 nop + 80107a4: 372c adds r7, #44 @ 0x2c + 80107a6: 46bd mov sp, r7 + 80107a8: bc80 pop {r7} + 80107aa: 4770 bx lr + 80107ac: 40010400 .word 0x40010400 + +080107b0 : + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + 80107b0: b480 push {r7} + 80107b2: b085 sub sp, #20 + 80107b4: af00 add r7, sp, #0 + 80107b6: 6078 str r0, [r7, #4] + 80107b8: 460b mov r3, r1 + 80107ba: 807b strh r3, [r7, #2] + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 80107bc: 687b ldr r3, [r7, #4] + 80107be: 689a ldr r2, [r3, #8] + 80107c0: 887b ldrh r3, [r7, #2] + 80107c2: 4013 ands r3, r2 + 80107c4: 2b00 cmp r3, #0 + 80107c6: d002 beq.n 80107ce + { + bitstatus = GPIO_PIN_SET; + 80107c8: 2301 movs r3, #1 + 80107ca: 73fb strb r3, [r7, #15] + 80107cc: e001 b.n 80107d2 + } + else + { + bitstatus = GPIO_PIN_RESET; + 80107ce: 2300 movs r3, #0 + 80107d0: 73fb strb r3, [r7, #15] + } + return bitstatus; + 80107d2: 7bfb ldrb r3, [r7, #15] +} + 80107d4: 4618 mov r0, r3 + 80107d6: 3714 adds r7, #20 + 80107d8: 46bd mov sp, r7 + 80107da: bc80 pop {r7} + 80107dc: 4770 bx lr + +080107de : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80107de: b480 push {r7} + 80107e0: b083 sub sp, #12 + 80107e2: af00 add r7, sp, #0 + 80107e4: 6078 str r0, [r7, #4] + 80107e6: 460b mov r3, r1 + 80107e8: 807b strh r3, [r7, #2] + 80107ea: 4613 mov r3, r2 + 80107ec: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80107ee: 787b ldrb r3, [r7, #1] + 80107f0: 2b00 cmp r3, #0 + 80107f2: d003 beq.n 80107fc + { + GPIOx->BSRR = GPIO_Pin; + 80107f4: 887a ldrh r2, [r7, #2] + 80107f6: 687b ldr r3, [r7, #4] + 80107f8: 611a str r2, [r3, #16] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + } +} + 80107fa: e003 b.n 8010804 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + 80107fc: 887b ldrh r3, [r7, #2] + 80107fe: 041a lsls r2, r3, #16 + 8010800: 687b ldr r3, [r7, #4] + 8010802: 611a str r2, [r3, #16] +} + 8010804: bf00 nop + 8010806: 370c adds r7, #12 + 8010808: 46bd mov sp, r7 + 801080a: bc80 pop {r7} + 801080c: 4770 bx lr + ... + +08010810 : + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 8010810: b480 push {r7} + 8010812: af00 add r7, sp, #0 + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; + 8010814: 4b03 ldr r3, [pc, #12] @ (8010824 ) + 8010816: 2201 movs r2, #1 + 8010818: 601a str r2, [r3, #0] +} + 801081a: bf00 nop + 801081c: 46bd mov sp, r7 + 801081e: bc80 pop {r7} + 8010820: 4770 bx lr + 8010822: bf00 nop + 8010824: 420e0020 .word 0x420e0020 + +08010828 : + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + 8010828: b580 push {r7, lr} + 801082a: b082 sub sp, #8 + 801082c: af00 add r7, sp, #0 + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 801082e: f7fd ffcf bl 800e7d0 + 8010832: 6078 str r0, [r7, #4] + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + 8010834: 4b60 ldr r3, [pc, #384] @ (80109b8 ) + 8010836: 681b ldr r3, [r3, #0] + 8010838: 4a5f ldr r2, [pc, #380] @ (80109b8 ) + 801083a: f043 0301 orr.w r3, r3, #1 + 801083e: 6013 str r3, [r2, #0] + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + 8010840: e008 b.n 8010854 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8010842: f7fd ffc5 bl 800e7d0 + 8010846: 4602 mov r2, r0 + 8010848: 687b ldr r3, [r7, #4] + 801084a: 1ad3 subs r3, r2, r3 + 801084c: 2b02 cmp r3, #2 + 801084e: d901 bls.n 8010854 + { + return HAL_TIMEOUT; + 8010850: 2303 movs r3, #3 + 8010852: e0ac b.n 80109ae + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + 8010854: 4b58 ldr r3, [pc, #352] @ (80109b8 ) + 8010856: 681b ldr r3, [r3, #0] + 8010858: f003 0302 and.w r3, r3, #2 + 801085c: 2b00 cmp r3, #0 + 801085e: d0f0 beq.n 8010842 + } + } + + /* Set HSITRIM bits to the reset value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); + 8010860: 4b55 ldr r3, [pc, #340] @ (80109b8 ) + 8010862: 681b ldr r3, [r3, #0] + 8010864: f023 03f8 bic.w r3, r3, #248 @ 0xf8 + 8010868: 4a53 ldr r2, [pc, #332] @ (80109b8 ) + 801086a: f043 0380 orr.w r3, r3, #128 @ 0x80 + 801086e: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010870: f7fd ffae bl 800e7d0 + 8010874: 6078 str r0, [r7, #4] + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + 8010876: 4b50 ldr r3, [pc, #320] @ (80109b8 ) + 8010878: 2200 movs r2, #0 + 801087a: 605a str r2, [r3, #4] + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + 801087c: e00a b.n 8010894 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 801087e: f7fd ffa7 bl 800e7d0 + 8010882: 4602 mov r2, r0 + 8010884: 687b ldr r3, [r7, #4] + 8010886: 1ad3 subs r3, r2, r3 + 8010888: f241 3288 movw r2, #5000 @ 0x1388 + 801088c: 4293 cmp r3, r2 + 801088e: d901 bls.n 8010894 + { + return HAL_TIMEOUT; + 8010890: 2303 movs r3, #3 + 8010892: e08c b.n 80109ae + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + 8010894: 4b48 ldr r3, [pc, #288] @ (80109b8 ) + 8010896: 685b ldr r3, [r3, #4] + 8010898: f003 030c and.w r3, r3, #12 + 801089c: 2b00 cmp r3, #0 + 801089e: d1ee bne.n 801087e + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + 80108a0: 4b46 ldr r3, [pc, #280] @ (80109bc ) + 80108a2: 4a47 ldr r2, [pc, #284] @ (80109c0 ) + 80108a4: 601a str r2, [r3, #0] + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + 80108a6: 4b47 ldr r3, [pc, #284] @ (80109c4 ) + 80108a8: 681b ldr r3, [r3, #0] + 80108aa: 4618 mov r0, r3 + 80108ac: f7fd ff4e bl 800e74c + 80108b0: 4603 mov r3, r0 + 80108b2: 2b00 cmp r3, #0 + 80108b4: d001 beq.n 80108ba + { + return HAL_ERROR; + 80108b6: 2301 movs r3, #1 + 80108b8: e079 b.n 80109ae + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80108ba: f7fd ff89 bl 800e7d0 + 80108be: 6078 str r0, [r7, #4] + + /* Second step is to clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 80108c0: 4b3d ldr r3, [pc, #244] @ (80109b8 ) + 80108c2: 681b ldr r3, [r3, #0] + 80108c4: 4a3c ldr r2, [pc, #240] @ (80109b8 ) + 80108c6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 80108ca: 6013 str r3, [r2, #0] + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + 80108cc: e008 b.n 80108e0 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80108ce: f7fd ff7f bl 800e7d0 + 80108d2: 4602 mov r2, r0 + 80108d4: 687b ldr r3, [r7, #4] + 80108d6: 1ad3 subs r3, r2, r3 + 80108d8: 2b02 cmp r3, #2 + 80108da: d901 bls.n 80108e0 + { + return HAL_TIMEOUT; + 80108dc: 2303 movs r3, #3 + 80108de: e066 b.n 80109ae + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + 80108e0: 4b35 ldr r3, [pc, #212] @ (80109b8 ) + 80108e2: 681b ldr r3, [r3, #0] + 80108e4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80108e8: 2b00 cmp r3, #0 + 80108ea: d1f0 bne.n 80108ce + } + } + + /* Ensure to reset PLLSRC and PLLMUL bits */ + CLEAR_REG(RCC->CFGR); + 80108ec: 4b32 ldr r3, [pc, #200] @ (80109b8 ) + 80108ee: 2200 movs r2, #0 + 80108f0: 605a str r2, [r3, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80108f2: f7fd ff6d bl 800e7d0 + 80108f6: 6078 str r0, [r7, #4] + + /* Reset HSEON & CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); + 80108f8: 4b2f ldr r3, [pc, #188] @ (80109b8 ) + 80108fa: 681b ldr r3, [r3, #0] + 80108fc: 4a2e ldr r2, [pc, #184] @ (80109b8 ) + 80108fe: f423 2310 bic.w r3, r3, #589824 @ 0x90000 + 8010902: 6013 str r3, [r2, #0] + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + 8010904: e008 b.n 8010918 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8010906: f7fd ff63 bl 800e7d0 + 801090a: 4602 mov r2, r0 + 801090c: 687b ldr r3, [r7, #4] + 801090e: 1ad3 subs r3, r2, r3 + 8010910: 2b64 cmp r3, #100 @ 0x64 + 8010912: d901 bls.n 8010918 + { + return HAL_TIMEOUT; + 8010914: 2303 movs r3, #3 + 8010916: e04a b.n 80109ae + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + 8010918: 4b27 ldr r3, [pc, #156] @ (80109b8 ) + 801091a: 681b ldr r3, [r3, #0] + 801091c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8010920: 2b00 cmp r3, #0 + 8010922: d1f0 bne.n 8010906 + } + } + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 8010924: 4b24 ldr r3, [pc, #144] @ (80109b8 ) + 8010926: 681b ldr r3, [r3, #0] + 8010928: 4a23 ldr r2, [pc, #140] @ (80109b8 ) + 801092a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 801092e: 6013 str r3, [r2, #0] + +#if defined(RCC_PLL2_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010930: f7fd ff4e bl 800e7d0 + 8010934: 6078 str r0, [r7, #4] + + /* Clear PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + 8010936: 4b20 ldr r3, [pc, #128] @ (80109b8 ) + 8010938: 681b ldr r3, [r3, #0] + 801093a: 4a1f ldr r2, [pc, #124] @ (80109b8 ) + 801093c: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8010940: 6013 str r3, [r2, #0] + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) + 8010942: e008 b.n 8010956 + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + 8010944: f7fd ff44 bl 800e7d0 + 8010948: 4602 mov r2, r0 + 801094a: 687b ldr r3, [r7, #4] + 801094c: 1ad3 subs r3, r2, r3 + 801094e: 2b64 cmp r3, #100 @ 0x64 + 8010950: d901 bls.n 8010956 + { + return HAL_TIMEOUT; + 8010952: 2303 movs r3, #3 + 8010954: e02b b.n 80109ae + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) + 8010956: 4b18 ldr r3, [pc, #96] @ (80109b8 ) + 8010958: 681b ldr r3, [r3, #0] + 801095a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 801095e: 2b00 cmp r3, #0 + 8010960: d1f0 bne.n 8010944 + } +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010962: f7fd ff35 bl 800e7d0 + 8010966: 6078 str r0, [r7, #4] + + /* Clear PLL3ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + 8010968: 4b13 ldr r3, [pc, #76] @ (80109b8 ) + 801096a: 681b ldr r3, [r3, #0] + 801096c: 4a12 ldr r2, [pc, #72] @ (80109b8 ) + 801096e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8010972: 6013 str r3, [r2, #0] + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) + 8010974: e008 b.n 8010988 + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 8010976: f7fd ff2b bl 800e7d0 + 801097a: 4602 mov r2, r0 + 801097c: 687b ldr r3, [r7, #4] + 801097e: 1ad3 subs r3, r2, r3 + 8010980: 2b64 cmp r3, #100 @ 0x64 + 8010982: d901 bls.n 8010988 + { + return HAL_TIMEOUT; + 8010984: 2303 movs r3, #3 + 8010986: e012 b.n 80109ae + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) + 8010988: 4b0b ldr r3, [pc, #44] @ (80109b8 ) + 801098a: 681b ldr r3, [r3, #0] + 801098c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 8010990: 2b00 cmp r3, #0 + 8010992: d1f0 bne.n 8010976 + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_CFGR2_PREDIV1) + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + 8010994: 4b08 ldr r3, [pc, #32] @ (80109b8 ) + 8010996: 2200 movs r2, #0 + 8010998: 62da str r2, [r3, #44] @ 0x2c +#endif /* RCC_CFGR2_PREDIV1 */ + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + 801099a: 4b07 ldr r3, [pc, #28] @ (80109b8 ) + 801099c: 6a5b ldr r3, [r3, #36] @ 0x24 + 801099e: 4a06 ldr r2, [pc, #24] @ (80109b8 ) + 80109a0: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 80109a4: 6253 str r3, [r2, #36] @ 0x24 + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + 80109a6: 4b04 ldr r3, [pc, #16] @ (80109b8 ) + 80109a8: 2200 movs r2, #0 + 80109aa: 609a str r2, [r3, #8] + + return HAL_OK; + 80109ac: 2300 movs r3, #0 +} + 80109ae: 4618 mov r0, r3 + 80109b0: 3708 adds r7, #8 + 80109b2: 46bd mov sp, r7 + 80109b4: bd80 pop {r7, pc} + 80109b6: bf00 nop + 80109b8: 40021000 .word 0x40021000 + 80109bc: 2000006c .word 0x2000006c + 80109c0: 007a1200 .word 0x007a1200 + 80109c4: 20000070 .word 0x20000070 + +080109c8 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80109c8: b580 push {r7, lr} + 80109ca: b086 sub sp, #24 + 80109cc: af00 add r7, sp, #0 + 80109ce: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 80109d0: 687b ldr r3, [r7, #4] + 80109d2: 2b00 cmp r3, #0 + 80109d4: d101 bne.n 80109da + { + return HAL_ERROR; + 80109d6: 2301 movs r3, #1 + 80109d8: e304 b.n 8010fe4 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80109da: 687b ldr r3, [r7, #4] + 80109dc: 681b ldr r3, [r3, #0] + 80109de: f003 0301 and.w r3, r3, #1 + 80109e2: 2b00 cmp r3, #0 + 80109e4: f000 8087 beq.w 8010af6 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 80109e8: 4b92 ldr r3, [pc, #584] @ (8010c34 ) + 80109ea: 685b ldr r3, [r3, #4] + 80109ec: f003 030c and.w r3, r3, #12 + 80109f0: 2b04 cmp r3, #4 + 80109f2: d00c beq.n 8010a0e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + 80109f4: 4b8f ldr r3, [pc, #572] @ (8010c34 ) + 80109f6: 685b ldr r3, [r3, #4] + 80109f8: f003 030c and.w r3, r3, #12 + 80109fc: 2b08 cmp r3, #8 + 80109fe: d112 bne.n 8010a26 + 8010a00: 4b8c ldr r3, [pc, #560] @ (8010c34 ) + 8010a02: 685b ldr r3, [r3, #4] + 8010a04: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8010a08: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8010a0c: d10b bne.n 8010a26 + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8010a0e: 4b89 ldr r3, [pc, #548] @ (8010c34 ) + 8010a10: 681b ldr r3, [r3, #0] + 8010a12: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8010a16: 2b00 cmp r3, #0 + 8010a18: d06c beq.n 8010af4 + 8010a1a: 687b ldr r3, [r7, #4] + 8010a1c: 689b ldr r3, [r3, #8] + 8010a1e: 2b00 cmp r3, #0 + 8010a20: d168 bne.n 8010af4 + { + return HAL_ERROR; + 8010a22: 2301 movs r3, #1 + 8010a24: e2de b.n 8010fe4 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8010a26: 687b ldr r3, [r7, #4] + 8010a28: 689b ldr r3, [r3, #8] + 8010a2a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8010a2e: d106 bne.n 8010a3e + 8010a30: 4b80 ldr r3, [pc, #512] @ (8010c34 ) + 8010a32: 681b ldr r3, [r3, #0] + 8010a34: 4a7f ldr r2, [pc, #508] @ (8010c34 ) + 8010a36: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8010a3a: 6013 str r3, [r2, #0] + 8010a3c: e02e b.n 8010a9c + 8010a3e: 687b ldr r3, [r7, #4] + 8010a40: 689b ldr r3, [r3, #8] + 8010a42: 2b00 cmp r3, #0 + 8010a44: d10c bne.n 8010a60 + 8010a46: 4b7b ldr r3, [pc, #492] @ (8010c34 ) + 8010a48: 681b ldr r3, [r3, #0] + 8010a4a: 4a7a ldr r2, [pc, #488] @ (8010c34 ) + 8010a4c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8010a50: 6013 str r3, [r2, #0] + 8010a52: 4b78 ldr r3, [pc, #480] @ (8010c34 ) + 8010a54: 681b ldr r3, [r3, #0] + 8010a56: 4a77 ldr r2, [pc, #476] @ (8010c34 ) + 8010a58: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8010a5c: 6013 str r3, [r2, #0] + 8010a5e: e01d b.n 8010a9c + 8010a60: 687b ldr r3, [r7, #4] + 8010a62: 689b ldr r3, [r3, #8] + 8010a64: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8010a68: d10c bne.n 8010a84 + 8010a6a: 4b72 ldr r3, [pc, #456] @ (8010c34 ) + 8010a6c: 681b ldr r3, [r3, #0] + 8010a6e: 4a71 ldr r2, [pc, #452] @ (8010c34 ) + 8010a70: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8010a74: 6013 str r3, [r2, #0] + 8010a76: 4b6f ldr r3, [pc, #444] @ (8010c34 ) + 8010a78: 681b ldr r3, [r3, #0] + 8010a7a: 4a6e ldr r2, [pc, #440] @ (8010c34 ) + 8010a7c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8010a80: 6013 str r3, [r2, #0] + 8010a82: e00b b.n 8010a9c + 8010a84: 4b6b ldr r3, [pc, #428] @ (8010c34 ) + 8010a86: 681b ldr r3, [r3, #0] + 8010a88: 4a6a ldr r2, [pc, #424] @ (8010c34 ) + 8010a8a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8010a8e: 6013 str r3, [r2, #0] + 8010a90: 4b68 ldr r3, [pc, #416] @ (8010c34 ) + 8010a92: 681b ldr r3, [r3, #0] + 8010a94: 4a67 ldr r2, [pc, #412] @ (8010c34 ) + 8010a96: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8010a9a: 6013 str r3, [r2, #0] + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8010a9c: 687b ldr r3, [r7, #4] + 8010a9e: 689b ldr r3, [r3, #8] + 8010aa0: 2b00 cmp r3, #0 + 8010aa2: d013 beq.n 8010acc + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010aa4: f7fd fe94 bl 800e7d0 + 8010aa8: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8010aaa: e008 b.n 8010abe + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8010aac: f7fd fe90 bl 800e7d0 + 8010ab0: 4602 mov r2, r0 + 8010ab2: 693b ldr r3, [r7, #16] + 8010ab4: 1ad3 subs r3, r2, r3 + 8010ab6: 2b64 cmp r3, #100 @ 0x64 + 8010ab8: d901 bls.n 8010abe + { + return HAL_TIMEOUT; + 8010aba: 2303 movs r3, #3 + 8010abc: e292 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8010abe: 4b5d ldr r3, [pc, #372] @ (8010c34 ) + 8010ac0: 681b ldr r3, [r3, #0] + 8010ac2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8010ac6: 2b00 cmp r3, #0 + 8010ac8: d0f0 beq.n 8010aac + 8010aca: e014 b.n 8010af6 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010acc: f7fd fe80 bl 800e7d0 + 8010ad0: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8010ad2: e008 b.n 8010ae6 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8010ad4: f7fd fe7c bl 800e7d0 + 8010ad8: 4602 mov r2, r0 + 8010ada: 693b ldr r3, [r7, #16] + 8010adc: 1ad3 subs r3, r2, r3 + 8010ade: 2b64 cmp r3, #100 @ 0x64 + 8010ae0: d901 bls.n 8010ae6 + { + return HAL_TIMEOUT; + 8010ae2: 2303 movs r3, #3 + 8010ae4: e27e b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8010ae6: 4b53 ldr r3, [pc, #332] @ (8010c34 ) + 8010ae8: 681b ldr r3, [r3, #0] + 8010aea: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8010aee: 2b00 cmp r3, #0 + 8010af0: d1f0 bne.n 8010ad4 + 8010af2: e000 b.n 8010af6 + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8010af4: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8010af6: 687b ldr r3, [r7, #4] + 8010af8: 681b ldr r3, [r3, #0] + 8010afa: f003 0302 and.w r3, r3, #2 + 8010afe: 2b00 cmp r3, #0 + 8010b00: d063 beq.n 8010bca + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 8010b02: 4b4c ldr r3, [pc, #304] @ (8010c34 ) + 8010b04: 685b ldr r3, [r3, #4] + 8010b06: f003 030c and.w r3, r3, #12 + 8010b0a: 2b00 cmp r3, #0 + 8010b0c: d00b beq.n 8010b26 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + 8010b0e: 4b49 ldr r3, [pc, #292] @ (8010c34 ) + 8010b10: 685b ldr r3, [r3, #4] + 8010b12: f003 030c and.w r3, r3, #12 + 8010b16: 2b08 cmp r3, #8 + 8010b18: d11c bne.n 8010b54 + 8010b1a: 4b46 ldr r3, [pc, #280] @ (8010c34 ) + 8010b1c: 685b ldr r3, [r3, #4] + 8010b1e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8010b22: 2b00 cmp r3, #0 + 8010b24: d116 bne.n 8010b54 + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8010b26: 4b43 ldr r3, [pc, #268] @ (8010c34 ) + 8010b28: 681b ldr r3, [r3, #0] + 8010b2a: f003 0302 and.w r3, r3, #2 + 8010b2e: 2b00 cmp r3, #0 + 8010b30: d005 beq.n 8010b3e + 8010b32: 687b ldr r3, [r7, #4] + 8010b34: 695b ldr r3, [r3, #20] + 8010b36: 2b01 cmp r3, #1 + 8010b38: d001 beq.n 8010b3e + { + return HAL_ERROR; + 8010b3a: 2301 movs r3, #1 + 8010b3c: e252 b.n 8010fe4 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8010b3e: 4b3d ldr r3, [pc, #244] @ (8010c34 ) + 8010b40: 681b ldr r3, [r3, #0] + 8010b42: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8010b46: 687b ldr r3, [r7, #4] + 8010b48: 699b ldr r3, [r3, #24] + 8010b4a: 00db lsls r3, r3, #3 + 8010b4c: 4939 ldr r1, [pc, #228] @ (8010c34 ) + 8010b4e: 4313 orrs r3, r2 + 8010b50: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8010b52: e03a b.n 8010bca + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8010b54: 687b ldr r3, [r7, #4] + 8010b56: 695b ldr r3, [r3, #20] + 8010b58: 2b00 cmp r3, #0 + 8010b5a: d020 beq.n 8010b9e + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8010b5c: 4b36 ldr r3, [pc, #216] @ (8010c38 ) + 8010b5e: 2201 movs r2, #1 + 8010b60: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010b62: f7fd fe35 bl 800e7d0 + 8010b66: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8010b68: e008 b.n 8010b7c + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8010b6a: f7fd fe31 bl 800e7d0 + 8010b6e: 4602 mov r2, r0 + 8010b70: 693b ldr r3, [r7, #16] + 8010b72: 1ad3 subs r3, r2, r3 + 8010b74: 2b02 cmp r3, #2 + 8010b76: d901 bls.n 8010b7c + { + return HAL_TIMEOUT; + 8010b78: 2303 movs r3, #3 + 8010b7a: e233 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8010b7c: 4b2d ldr r3, [pc, #180] @ (8010c34 ) + 8010b7e: 681b ldr r3, [r3, #0] + 8010b80: f003 0302 and.w r3, r3, #2 + 8010b84: 2b00 cmp r3, #0 + 8010b86: d0f0 beq.n 8010b6a + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8010b88: 4b2a ldr r3, [pc, #168] @ (8010c34 ) + 8010b8a: 681b ldr r3, [r3, #0] + 8010b8c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8010b90: 687b ldr r3, [r7, #4] + 8010b92: 699b ldr r3, [r3, #24] + 8010b94: 00db lsls r3, r3, #3 + 8010b96: 4927 ldr r1, [pc, #156] @ (8010c34 ) + 8010b98: 4313 orrs r3, r2 + 8010b9a: 600b str r3, [r1, #0] + 8010b9c: e015 b.n 8010bca + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8010b9e: 4b26 ldr r3, [pc, #152] @ (8010c38 ) + 8010ba0: 2200 movs r2, #0 + 8010ba2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010ba4: f7fd fe14 bl 800e7d0 + 8010ba8: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8010baa: e008 b.n 8010bbe + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8010bac: f7fd fe10 bl 800e7d0 + 8010bb0: 4602 mov r2, r0 + 8010bb2: 693b ldr r3, [r7, #16] + 8010bb4: 1ad3 subs r3, r2, r3 + 8010bb6: 2b02 cmp r3, #2 + 8010bb8: d901 bls.n 8010bbe + { + return HAL_TIMEOUT; + 8010bba: 2303 movs r3, #3 + 8010bbc: e212 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8010bbe: 4b1d ldr r3, [pc, #116] @ (8010c34 ) + 8010bc0: 681b ldr r3, [r3, #0] + 8010bc2: f003 0302 and.w r3, r3, #2 + 8010bc6: 2b00 cmp r3, #0 + 8010bc8: d1f0 bne.n 8010bac + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8010bca: 687b ldr r3, [r7, #4] + 8010bcc: 681b ldr r3, [r3, #0] + 8010bce: f003 0308 and.w r3, r3, #8 + 8010bd2: 2b00 cmp r3, #0 + 8010bd4: d03a beq.n 8010c4c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8010bd6: 687b ldr r3, [r7, #4] + 8010bd8: 69db ldr r3, [r3, #28] + 8010bda: 2b00 cmp r3, #0 + 8010bdc: d019 beq.n 8010c12 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8010bde: 4b17 ldr r3, [pc, #92] @ (8010c3c ) + 8010be0: 2201 movs r2, #1 + 8010be2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010be4: f7fd fdf4 bl 800e7d0 + 8010be8: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8010bea: e008 b.n 8010bfe + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8010bec: f7fd fdf0 bl 800e7d0 + 8010bf0: 4602 mov r2, r0 + 8010bf2: 693b ldr r3, [r7, #16] + 8010bf4: 1ad3 subs r3, r2, r3 + 8010bf6: 2b02 cmp r3, #2 + 8010bf8: d901 bls.n 8010bfe + { + return HAL_TIMEOUT; + 8010bfa: 2303 movs r3, #3 + 8010bfc: e1f2 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8010bfe: 4b0d ldr r3, [pc, #52] @ (8010c34 ) + 8010c00: 6a5b ldr r3, [r3, #36] @ 0x24 + 8010c02: f003 0302 and.w r3, r3, #2 + 8010c06: 2b00 cmp r3, #0 + 8010c08: d0f0 beq.n 8010bec + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + 8010c0a: 2001 movs r0, #1 + 8010c0c: f000 fbca bl 80113a4 + 8010c10: e01c b.n 8010c4c + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8010c12: 4b0a ldr r3, [pc, #40] @ (8010c3c ) + 8010c14: 2200 movs r2, #0 + 8010c16: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010c18: f7fd fdda bl 800e7d0 + 8010c1c: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8010c1e: e00f b.n 8010c40 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8010c20: f7fd fdd6 bl 800e7d0 + 8010c24: 4602 mov r2, r0 + 8010c26: 693b ldr r3, [r7, #16] + 8010c28: 1ad3 subs r3, r2, r3 + 8010c2a: 2b02 cmp r3, #2 + 8010c2c: d908 bls.n 8010c40 + { + return HAL_TIMEOUT; + 8010c2e: 2303 movs r3, #3 + 8010c30: e1d8 b.n 8010fe4 + 8010c32: bf00 nop + 8010c34: 40021000 .word 0x40021000 + 8010c38: 42420000 .word 0x42420000 + 8010c3c: 42420480 .word 0x42420480 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8010c40: 4b9b ldr r3, [pc, #620] @ (8010eb0 ) + 8010c42: 6a5b ldr r3, [r3, #36] @ 0x24 + 8010c44: f003 0302 and.w r3, r3, #2 + 8010c48: 2b00 cmp r3, #0 + 8010c4a: d1e9 bne.n 8010c20 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8010c4c: 687b ldr r3, [r7, #4] + 8010c4e: 681b ldr r3, [r3, #0] + 8010c50: f003 0304 and.w r3, r3, #4 + 8010c54: 2b00 cmp r3, #0 + 8010c56: f000 80a6 beq.w 8010da6 + { + FlagStatus pwrclkchanged = RESET; + 8010c5a: 2300 movs r3, #0 + 8010c5c: 75fb strb r3, [r7, #23] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8010c5e: 4b94 ldr r3, [pc, #592] @ (8010eb0 ) + 8010c60: 69db ldr r3, [r3, #28] + 8010c62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8010c66: 2b00 cmp r3, #0 + 8010c68: d10d bne.n 8010c86 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8010c6a: 4b91 ldr r3, [pc, #580] @ (8010eb0 ) + 8010c6c: 69db ldr r3, [r3, #28] + 8010c6e: 4a90 ldr r2, [pc, #576] @ (8010eb0 ) + 8010c70: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8010c74: 61d3 str r3, [r2, #28] + 8010c76: 4b8e ldr r3, [pc, #568] @ (8010eb0 ) + 8010c78: 69db ldr r3, [r3, #28] + 8010c7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8010c7e: 60bb str r3, [r7, #8] + 8010c80: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8010c82: 2301 movs r3, #1 + 8010c84: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8010c86: 4b8b ldr r3, [pc, #556] @ (8010eb4 ) + 8010c88: 681b ldr r3, [r3, #0] + 8010c8a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8010c8e: 2b00 cmp r3, #0 + 8010c90: d118 bne.n 8010cc4 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8010c92: 4b88 ldr r3, [pc, #544] @ (8010eb4 ) + 8010c94: 681b ldr r3, [r3, #0] + 8010c96: 4a87 ldr r2, [pc, #540] @ (8010eb4 ) + 8010c98: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8010c9c: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8010c9e: f7fd fd97 bl 800e7d0 + 8010ca2: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8010ca4: e008 b.n 8010cb8 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8010ca6: f7fd fd93 bl 800e7d0 + 8010caa: 4602 mov r2, r0 + 8010cac: 693b ldr r3, [r7, #16] + 8010cae: 1ad3 subs r3, r2, r3 + 8010cb0: 2b64 cmp r3, #100 @ 0x64 + 8010cb2: d901 bls.n 8010cb8 + { + return HAL_TIMEOUT; + 8010cb4: 2303 movs r3, #3 + 8010cb6: e195 b.n 8010fe4 + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8010cb8: 4b7e ldr r3, [pc, #504] @ (8010eb4 ) + 8010cba: 681b ldr r3, [r3, #0] + 8010cbc: f403 7380 and.w r3, r3, #256 @ 0x100 + 8010cc0: 2b00 cmp r3, #0 + 8010cc2: d0f0 beq.n 8010ca6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8010cc4: 687b ldr r3, [r7, #4] + 8010cc6: 691b ldr r3, [r3, #16] + 8010cc8: 2b01 cmp r3, #1 + 8010cca: d106 bne.n 8010cda + 8010ccc: 4b78 ldr r3, [pc, #480] @ (8010eb0 ) + 8010cce: 6a1b ldr r3, [r3, #32] + 8010cd0: 4a77 ldr r2, [pc, #476] @ (8010eb0 ) + 8010cd2: f043 0301 orr.w r3, r3, #1 + 8010cd6: 6213 str r3, [r2, #32] + 8010cd8: e02d b.n 8010d36 + 8010cda: 687b ldr r3, [r7, #4] + 8010cdc: 691b ldr r3, [r3, #16] + 8010cde: 2b00 cmp r3, #0 + 8010ce0: d10c bne.n 8010cfc + 8010ce2: 4b73 ldr r3, [pc, #460] @ (8010eb0 ) + 8010ce4: 6a1b ldr r3, [r3, #32] + 8010ce6: 4a72 ldr r2, [pc, #456] @ (8010eb0 ) + 8010ce8: f023 0301 bic.w r3, r3, #1 + 8010cec: 6213 str r3, [r2, #32] + 8010cee: 4b70 ldr r3, [pc, #448] @ (8010eb0 ) + 8010cf0: 6a1b ldr r3, [r3, #32] + 8010cf2: 4a6f ldr r2, [pc, #444] @ (8010eb0 ) + 8010cf4: f023 0304 bic.w r3, r3, #4 + 8010cf8: 6213 str r3, [r2, #32] + 8010cfa: e01c b.n 8010d36 + 8010cfc: 687b ldr r3, [r7, #4] + 8010cfe: 691b ldr r3, [r3, #16] + 8010d00: 2b05 cmp r3, #5 + 8010d02: d10c bne.n 8010d1e + 8010d04: 4b6a ldr r3, [pc, #424] @ (8010eb0 ) + 8010d06: 6a1b ldr r3, [r3, #32] + 8010d08: 4a69 ldr r2, [pc, #420] @ (8010eb0 ) + 8010d0a: f043 0304 orr.w r3, r3, #4 + 8010d0e: 6213 str r3, [r2, #32] + 8010d10: 4b67 ldr r3, [pc, #412] @ (8010eb0 ) + 8010d12: 6a1b ldr r3, [r3, #32] + 8010d14: 4a66 ldr r2, [pc, #408] @ (8010eb0 ) + 8010d16: f043 0301 orr.w r3, r3, #1 + 8010d1a: 6213 str r3, [r2, #32] + 8010d1c: e00b b.n 8010d36 + 8010d1e: 4b64 ldr r3, [pc, #400] @ (8010eb0 ) + 8010d20: 6a1b ldr r3, [r3, #32] + 8010d22: 4a63 ldr r2, [pc, #396] @ (8010eb0 ) + 8010d24: f023 0301 bic.w r3, r3, #1 + 8010d28: 6213 str r3, [r2, #32] + 8010d2a: 4b61 ldr r3, [pc, #388] @ (8010eb0 ) + 8010d2c: 6a1b ldr r3, [r3, #32] + 8010d2e: 4a60 ldr r2, [pc, #384] @ (8010eb0 ) + 8010d30: f023 0304 bic.w r3, r3, #4 + 8010d34: 6213 str r3, [r2, #32] + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8010d36: 687b ldr r3, [r7, #4] + 8010d38: 691b ldr r3, [r3, #16] + 8010d3a: 2b00 cmp r3, #0 + 8010d3c: d015 beq.n 8010d6a + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010d3e: f7fd fd47 bl 800e7d0 + 8010d42: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8010d44: e00a b.n 8010d5c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8010d46: f7fd fd43 bl 800e7d0 + 8010d4a: 4602 mov r2, r0 + 8010d4c: 693b ldr r3, [r7, #16] + 8010d4e: 1ad3 subs r3, r2, r3 + 8010d50: f241 3288 movw r2, #5000 @ 0x1388 + 8010d54: 4293 cmp r3, r2 + 8010d56: d901 bls.n 8010d5c + { + return HAL_TIMEOUT; + 8010d58: 2303 movs r3, #3 + 8010d5a: e143 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8010d5c: 4b54 ldr r3, [pc, #336] @ (8010eb0 ) + 8010d5e: 6a1b ldr r3, [r3, #32] + 8010d60: f003 0302 and.w r3, r3, #2 + 8010d64: 2b00 cmp r3, #0 + 8010d66: d0ee beq.n 8010d46 + 8010d68: e014 b.n 8010d94 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010d6a: f7fd fd31 bl 800e7d0 + 8010d6e: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8010d70: e00a b.n 8010d88 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8010d72: f7fd fd2d bl 800e7d0 + 8010d76: 4602 mov r2, r0 + 8010d78: 693b ldr r3, [r7, #16] + 8010d7a: 1ad3 subs r3, r2, r3 + 8010d7c: f241 3288 movw r2, #5000 @ 0x1388 + 8010d80: 4293 cmp r3, r2 + 8010d82: d901 bls.n 8010d88 + { + return HAL_TIMEOUT; + 8010d84: 2303 movs r3, #3 + 8010d86: e12d b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8010d88: 4b49 ldr r3, [pc, #292] @ (8010eb0 ) + 8010d8a: 6a1b ldr r3, [r3, #32] + 8010d8c: f003 0302 and.w r3, r3, #2 + 8010d90: 2b00 cmp r3, #0 + 8010d92: d1ee bne.n 8010d72 + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + 8010d94: 7dfb ldrb r3, [r7, #23] + 8010d96: 2b01 cmp r3, #1 + 8010d98: d105 bne.n 8010da6 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8010d9a: 4b45 ldr r3, [pc, #276] @ (8010eb0 ) + 8010d9c: 69db ldr r3, [r3, #28] + 8010d9e: 4a44 ldr r2, [pc, #272] @ (8010eb0 ) + 8010da0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8010da4: 61d3 str r3, [r2, #28] + +#if defined(RCC_CR_PLL2ON) + /*-------------------------------- PLL2 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); + if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) + 8010da6: 687b ldr r3, [r7, #4] + 8010da8: 6adb ldr r3, [r3, #44] @ 0x2c + 8010daa: 2b00 cmp r3, #0 + 8010dac: f000 808c beq.w 8010ec8 + { + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + 8010db0: 4b3f ldr r3, [pc, #252] @ (8010eb0 ) + 8010db2: 685b ldr r3, [r3, #4] + 8010db4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8010db8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8010dbc: d10e bne.n 8010ddc + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + 8010dbe: 4b3c ldr r3, [pc, #240] @ (8010eb0 ) + 8010dc0: 685b ldr r3, [r3, #4] + 8010dc2: f003 030c and.w r3, r3, #12 + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + 8010dc6: 2b08 cmp r3, #8 + 8010dc8: d108 bne.n 8010ddc + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + 8010dca: 4b39 ldr r3, [pc, #228] @ (8010eb0 ) + 8010dcc: 6adb ldr r3, [r3, #44] @ 0x2c + 8010dce: f403 3380 and.w r3, r3, #65536 @ 0x10000 + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + 8010dd2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8010dd6: d101 bne.n 8010ddc + { + return HAL_ERROR; + 8010dd8: 2301 movs r3, #1 + 8010dda: e103 b.n 8010fe4 + } + else + { + if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) + 8010ddc: 687b ldr r3, [r7, #4] + 8010dde: 6adb ldr r3, [r3, #44] @ 0x2c + 8010de0: 2b02 cmp r3, #2 + 8010de2: d14e bne.n 8010e82 + assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + 8010de4: 4b32 ldr r3, [pc, #200] @ (8010eb0 ) + 8010de6: 681b ldr r3, [r3, #0] + 8010de8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8010dec: 2b00 cmp r3, #0 + 8010dee: d009 beq.n 8010e04 + (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) + 8010df0: 4b2f ldr r3, [pc, #188] @ (8010eb0 ) + 8010df2: 6adb ldr r3, [r3, #44] @ 0x2c + 8010df4: f003 02f0 and.w r2, r3, #240 @ 0xf0 + 8010df8: 687b ldr r3, [r7, #4] + 8010dfa: 6b5b ldr r3, [r3, #52] @ 0x34 + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + 8010dfc: 429a cmp r2, r3 + 8010dfe: d001 beq.n 8010e04 + { + return HAL_ERROR; + 8010e00: 2301 movs r3, #1 + 8010e02: e0ef b.n 8010fe4 + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + 8010e04: 4b2c ldr r3, [pc, #176] @ (8010eb8 ) + 8010e06: 2200 movs r2, #0 + 8010e08: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010e0a: f7fd fce1 bl 800e7d0 + 8010e0e: 6138 str r0, [r7, #16] + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + 8010e10: e008 b.n 8010e24 + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + 8010e12: f7fd fcdd bl 800e7d0 + 8010e16: 4602 mov r2, r0 + 8010e18: 693b ldr r3, [r7, #16] + 8010e1a: 1ad3 subs r3, r2, r3 + 8010e1c: 2b64 cmp r3, #100 @ 0x64 + 8010e1e: d901 bls.n 8010e24 + { + return HAL_TIMEOUT; + 8010e20: 2303 movs r3, #3 + 8010e22: e0df b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + 8010e24: 4b22 ldr r3, [pc, #136] @ (8010eb0 ) + 8010e26: 681b ldr r3, [r3, #0] + 8010e28: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8010e2c: 2b00 cmp r3, #0 + 8010e2e: d1f0 bne.n 8010e12 + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); + 8010e30: 4b1f ldr r3, [pc, #124] @ (8010eb0 ) + 8010e32: 6adb ldr r3, [r3, #44] @ 0x2c + 8010e34: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8010e38: 687b ldr r3, [r7, #4] + 8010e3a: 6b5b ldr r3, [r3, #52] @ 0x34 + 8010e3c: 491c ldr r1, [pc, #112] @ (8010eb0 ) + 8010e3e: 4313 orrs r3, r2 + 8010e40: 62cb str r3, [r1, #44] @ 0x2c + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); + 8010e42: 4b1b ldr r3, [pc, #108] @ (8010eb0 ) + 8010e44: 6adb ldr r3, [r3, #44] @ 0x2c + 8010e46: f423 6270 bic.w r2, r3, #3840 @ 0xf00 + 8010e4a: 687b ldr r3, [r7, #4] + 8010e4c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8010e4e: 4918 ldr r1, [pc, #96] @ (8010eb0 ) + 8010e50: 4313 orrs r3, r2 + 8010e52: 62cb str r3, [r1, #44] @ 0x2c + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + 8010e54: 4b18 ldr r3, [pc, #96] @ (8010eb8 ) + 8010e56: 2201 movs r2, #1 + 8010e58: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010e5a: f7fd fcb9 bl 800e7d0 + 8010e5e: 6138 str r0, [r7, #16] + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + 8010e60: e008 b.n 8010e74 + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + 8010e62: f7fd fcb5 bl 800e7d0 + 8010e66: 4602 mov r2, r0 + 8010e68: 693b ldr r3, [r7, #16] + 8010e6a: 1ad3 subs r3, r2, r3 + 8010e6c: 2b64 cmp r3, #100 @ 0x64 + 8010e6e: d901 bls.n 8010e74 + { + return HAL_TIMEOUT; + 8010e70: 2303 movs r3, #3 + 8010e72: e0b7 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + 8010e74: 4b0e ldr r3, [pc, #56] @ (8010eb0 ) + 8010e76: 681b ldr r3, [r3, #0] + 8010e78: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8010e7c: 2b00 cmp r3, #0 + 8010e7e: d0f0 beq.n 8010e62 + 8010e80: e022 b.n 8010ec8 + } + } + else + { + /* Set PREDIV1 source to HSE */ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); + 8010e82: 4b0b ldr r3, [pc, #44] @ (8010eb0 ) + 8010e84: 6adb ldr r3, [r3, #44] @ 0x2c + 8010e86: 4a0a ldr r2, [pc, #40] @ (8010eb0 ) + 8010e88: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8010e8c: 62d3 str r3, [r2, #44] @ 0x2c + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + 8010e8e: 4b0a ldr r3, [pc, #40] @ (8010eb8 ) + 8010e90: 2200 movs r2, #0 + 8010e92: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010e94: f7fd fc9c bl 800e7d0 + 8010e98: 6138 str r0, [r7, #16] + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + 8010e9a: e00f b.n 8010ebc + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + 8010e9c: f7fd fc98 bl 800e7d0 + 8010ea0: 4602 mov r2, r0 + 8010ea2: 693b ldr r3, [r7, #16] + 8010ea4: 1ad3 subs r3, r2, r3 + 8010ea6: 2b64 cmp r3, #100 @ 0x64 + 8010ea8: d908 bls.n 8010ebc + { + return HAL_TIMEOUT; + 8010eaa: 2303 movs r3, #3 + 8010eac: e09a b.n 8010fe4 + 8010eae: bf00 nop + 8010eb0: 40021000 .word 0x40021000 + 8010eb4: 40007000 .word 0x40007000 + 8010eb8: 42420068 .word 0x42420068 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + 8010ebc: 4b4b ldr r3, [pc, #300] @ (8010fec ) + 8010ebe: 681b ldr r3, [r3, #0] + 8010ec0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8010ec4: 2b00 cmp r3, #0 + 8010ec6: d1e9 bne.n 8010e9c + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8010ec8: 687b ldr r3, [r7, #4] + 8010eca: 6a1b ldr r3, [r3, #32] + 8010ecc: 2b00 cmp r3, #0 + 8010ece: f000 8088 beq.w 8010fe2 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8010ed2: 4b46 ldr r3, [pc, #280] @ (8010fec ) + 8010ed4: 685b ldr r3, [r3, #4] + 8010ed6: f003 030c and.w r3, r3, #12 + 8010eda: 2b08 cmp r3, #8 + 8010edc: d068 beq.n 8010fb0 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8010ede: 687b ldr r3, [r7, #4] + 8010ee0: 6a1b ldr r3, [r3, #32] + 8010ee2: 2b02 cmp r3, #2 + 8010ee4: d14d bne.n 8010f82 + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8010ee6: 4b42 ldr r3, [pc, #264] @ (8010ff0 ) + 8010ee8: 2200 movs r2, #0 + 8010eea: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010eec: f7fd fc70 bl 800e7d0 + 8010ef0: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8010ef2: e008 b.n 8010f06 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8010ef4: f7fd fc6c bl 800e7d0 + 8010ef8: 4602 mov r2, r0 + 8010efa: 693b ldr r3, [r7, #16] + 8010efc: 1ad3 subs r3, r2, r3 + 8010efe: 2b02 cmp r3, #2 + 8010f00: d901 bls.n 8010f06 + { + return HAL_TIMEOUT; + 8010f02: 2303 movs r3, #3 + 8010f04: e06e b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8010f06: 4b39 ldr r3, [pc, #228] @ (8010fec ) + 8010f08: 681b ldr r3, [r3, #0] + 8010f0a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8010f0e: 2b00 cmp r3, #0 + 8010f10: d1f0 bne.n 8010ef4 + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + 8010f12: 687b ldr r3, [r7, #4] + 8010f14: 6a5b ldr r3, [r3, #36] @ 0x24 + 8010f16: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8010f1a: d10f bne.n 8010f3c + assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); +#if defined(RCC_CFGR2_PREDIV1SRC) + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); + + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); + 8010f1c: 4b33 ldr r3, [pc, #204] @ (8010fec ) + 8010f1e: 6ada ldr r2, [r3, #44] @ 0x2c + 8010f20: 687b ldr r3, [r7, #4] + 8010f22: 685b ldr r3, [r3, #4] + 8010f24: 4931 ldr r1, [pc, #196] @ (8010fec ) + 8010f26: 4313 orrs r3, r2 + 8010f28: 62cb str r3, [r1, #44] @ 0x2c +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 8010f2a: 4b30 ldr r3, [pc, #192] @ (8010fec ) + 8010f2c: 6adb ldr r3, [r3, #44] @ 0x2c + 8010f2e: f023 020f bic.w r2, r3, #15 + 8010f32: 687b ldr r3, [r7, #4] + 8010f34: 68db ldr r3, [r3, #12] + 8010f36: 492d ldr r1, [pc, #180] @ (8010fec ) + 8010f38: 4313 orrs r3, r2 + 8010f3a: 62cb str r3, [r1, #44] @ 0x2c + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8010f3c: 4b2b ldr r3, [pc, #172] @ (8010fec ) + 8010f3e: 685b ldr r3, [r3, #4] + 8010f40: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 + 8010f44: 687b ldr r3, [r7, #4] + 8010f46: 6a59 ldr r1, [r3, #36] @ 0x24 + 8010f48: 687b ldr r3, [r7, #4] + 8010f4a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8010f4c: 430b orrs r3, r1 + 8010f4e: 4927 ldr r1, [pc, #156] @ (8010fec ) + 8010f50: 4313 orrs r3, r2 + 8010f52: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8010f54: 4b26 ldr r3, [pc, #152] @ (8010ff0 ) + 8010f56: 2201 movs r2, #1 + 8010f58: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010f5a: f7fd fc39 bl 800e7d0 + 8010f5e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8010f60: e008 b.n 8010f74 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8010f62: f7fd fc35 bl 800e7d0 + 8010f66: 4602 mov r2, r0 + 8010f68: 693b ldr r3, [r7, #16] + 8010f6a: 1ad3 subs r3, r2, r3 + 8010f6c: 2b02 cmp r3, #2 + 8010f6e: d901 bls.n 8010f74 + { + return HAL_TIMEOUT; + 8010f70: 2303 movs r3, #3 + 8010f72: e037 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8010f74: 4b1d ldr r3, [pc, #116] @ (8010fec ) + 8010f76: 681b ldr r3, [r3, #0] + 8010f78: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8010f7c: 2b00 cmp r3, #0 + 8010f7e: d0f0 beq.n 8010f62 + 8010f80: e02f b.n 8010fe2 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8010f82: 4b1b ldr r3, [pc, #108] @ (8010ff0 ) + 8010f84: 2200 movs r2, #0 + 8010f86: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8010f88: f7fd fc22 bl 800e7d0 + 8010f8c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8010f8e: e008 b.n 8010fa2 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8010f90: f7fd fc1e bl 800e7d0 + 8010f94: 4602 mov r2, r0 + 8010f96: 693b ldr r3, [r7, #16] + 8010f98: 1ad3 subs r3, r2, r3 + 8010f9a: 2b02 cmp r3, #2 + 8010f9c: d901 bls.n 8010fa2 + { + return HAL_TIMEOUT; + 8010f9e: 2303 movs r3, #3 + 8010fa0: e020 b.n 8010fe4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8010fa2: 4b12 ldr r3, [pc, #72] @ (8010fec ) + 8010fa4: 681b ldr r3, [r3, #0] + 8010fa6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8010faa: 2b00 cmp r3, #0 + 8010fac: d1f0 bne.n 8010f90 + 8010fae: e018 b.n 8010fe2 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8010fb0: 687b ldr r3, [r7, #4] + 8010fb2: 6a1b ldr r3, [r3, #32] + 8010fb4: 2b01 cmp r3, #1 + 8010fb6: d101 bne.n 8010fbc + { + return HAL_ERROR; + 8010fb8: 2301 movs r3, #1 + 8010fba: e013 b.n 8010fe4 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8010fbc: 4b0b ldr r3, [pc, #44] @ (8010fec ) + 8010fbe: 685b ldr r3, [r3, #4] + 8010fc0: 60fb str r3, [r7, #12] + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8010fc2: 68fb ldr r3, [r7, #12] + 8010fc4: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8010fc8: 687b ldr r3, [r7, #4] + 8010fca: 6a5b ldr r3, [r3, #36] @ 0x24 + 8010fcc: 429a cmp r2, r3 + 8010fce: d106 bne.n 8010fde + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + 8010fd0: 68fb ldr r3, [r7, #12] + 8010fd2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8010fd6: 687b ldr r3, [r7, #4] + 8010fd8: 6a9b ldr r3, [r3, #40] @ 0x28 + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8010fda: 429a cmp r2, r3 + 8010fdc: d001 beq.n 8010fe2 + { + return HAL_ERROR; + 8010fde: 2301 movs r3, #1 + 8010fe0: e000 b.n 8010fe4 + } + } + } + } + + return HAL_OK; + 8010fe2: 2300 movs r3, #0 +} + 8010fe4: 4618 mov r0, r3 + 8010fe6: 3718 adds r7, #24 + 8010fe8: 46bd mov sp, r7 + 8010fea: bd80 pop {r7, pc} + 8010fec: 40021000 .word 0x40021000 + 8010ff0: 42420060 .word 0x42420060 + +08010ff4 : + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8010ff4: b580 push {r7, lr} + 8010ff6: b084 sub sp, #16 + 8010ff8: af00 add r7, sp, #0 + 8010ffa: 6078 str r0, [r7, #4] + 8010ffc: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8010ffe: 687b ldr r3, [r7, #4] + 8011000: 2b00 cmp r3, #0 + 8011002: d101 bne.n 8011008 + { + return HAL_ERROR; + 8011004: 2301 movs r3, #1 + 8011006: e0d0 b.n 80111aa + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8011008: 4b6a ldr r3, [pc, #424] @ (80111b4 ) + 801100a: 681b ldr r3, [r3, #0] + 801100c: f003 0307 and.w r3, r3, #7 + 8011010: 683a ldr r2, [r7, #0] + 8011012: 429a cmp r2, r3 + 8011014: d910 bls.n 8011038 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8011016: 4b67 ldr r3, [pc, #412] @ (80111b4 ) + 8011018: 681b ldr r3, [r3, #0] + 801101a: f023 0207 bic.w r2, r3, #7 + 801101e: 4965 ldr r1, [pc, #404] @ (80111b4 ) + 8011020: 683b ldr r3, [r7, #0] + 8011022: 4313 orrs r3, r2 + 8011024: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8011026: 4b63 ldr r3, [pc, #396] @ (80111b4 ) + 8011028: 681b ldr r3, [r3, #0] + 801102a: f003 0307 and.w r3, r3, #7 + 801102e: 683a ldr r2, [r7, #0] + 8011030: 429a cmp r2, r3 + 8011032: d001 beq.n 8011038 + { + return HAL_ERROR; + 8011034: 2301 movs r3, #1 + 8011036: e0b8 b.n 80111aa + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8011038: 687b ldr r3, [r7, #4] + 801103a: 681b ldr r3, [r3, #0] + 801103c: f003 0302 and.w r3, r3, #2 + 8011040: 2b00 cmp r3, #0 + 8011042: d020 beq.n 8011086 + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8011044: 687b ldr r3, [r7, #4] + 8011046: 681b ldr r3, [r3, #0] + 8011048: f003 0304 and.w r3, r3, #4 + 801104c: 2b00 cmp r3, #0 + 801104e: d005 beq.n 801105c + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8011050: 4b59 ldr r3, [pc, #356] @ (80111b8 ) + 8011052: 685b ldr r3, [r3, #4] + 8011054: 4a58 ldr r2, [pc, #352] @ (80111b8 ) + 8011056: f443 63e0 orr.w r3, r3, #1792 @ 0x700 + 801105a: 6053 str r3, [r2, #4] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 801105c: 687b ldr r3, [r7, #4] + 801105e: 681b ldr r3, [r3, #0] + 8011060: f003 0308 and.w r3, r3, #8 + 8011064: 2b00 cmp r3, #0 + 8011066: d005 beq.n 8011074 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8011068: 4b53 ldr r3, [pc, #332] @ (80111b8 ) + 801106a: 685b ldr r3, [r3, #4] + 801106c: 4a52 ldr r2, [pc, #328] @ (80111b8 ) + 801106e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 + 8011072: 6053 str r3, [r2, #4] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8011074: 4b50 ldr r3, [pc, #320] @ (80111b8 ) + 8011076: 685b ldr r3, [r3, #4] + 8011078: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 801107c: 687b ldr r3, [r7, #4] + 801107e: 689b ldr r3, [r3, #8] + 8011080: 494d ldr r1, [pc, #308] @ (80111b8 ) + 8011082: 4313 orrs r3, r2 + 8011084: 604b str r3, [r1, #4] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8011086: 687b ldr r3, [r7, #4] + 8011088: 681b ldr r3, [r3, #0] + 801108a: f003 0301 and.w r3, r3, #1 + 801108e: 2b00 cmp r3, #0 + 8011090: d040 beq.n 8011114 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8011092: 687b ldr r3, [r7, #4] + 8011094: 685b ldr r3, [r3, #4] + 8011096: 2b01 cmp r3, #1 + 8011098: d107 bne.n 80110aa + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 801109a: 4b47 ldr r3, [pc, #284] @ (80111b8 ) + 801109c: 681b ldr r3, [r3, #0] + 801109e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80110a2: 2b00 cmp r3, #0 + 80110a4: d115 bne.n 80110d2 + { + return HAL_ERROR; + 80110a6: 2301 movs r3, #1 + 80110a8: e07f b.n 80111aa + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80110aa: 687b ldr r3, [r7, #4] + 80110ac: 685b ldr r3, [r3, #4] + 80110ae: 2b02 cmp r3, #2 + 80110b0: d107 bne.n 80110c2 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80110b2: 4b41 ldr r3, [pc, #260] @ (80111b8 ) + 80110b4: 681b ldr r3, [r3, #0] + 80110b6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80110ba: 2b00 cmp r3, #0 + 80110bc: d109 bne.n 80110d2 + { + return HAL_ERROR; + 80110be: 2301 movs r3, #1 + 80110c0: e073 b.n 80111aa + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80110c2: 4b3d ldr r3, [pc, #244] @ (80111b8 ) + 80110c4: 681b ldr r3, [r3, #0] + 80110c6: f003 0302 and.w r3, r3, #2 + 80110ca: 2b00 cmp r3, #0 + 80110cc: d101 bne.n 80110d2 + { + return HAL_ERROR; + 80110ce: 2301 movs r3, #1 + 80110d0: e06b b.n 80111aa + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80110d2: 4b39 ldr r3, [pc, #228] @ (80111b8 ) + 80110d4: 685b ldr r3, [r3, #4] + 80110d6: f023 0203 bic.w r2, r3, #3 + 80110da: 687b ldr r3, [r7, #4] + 80110dc: 685b ldr r3, [r3, #4] + 80110de: 4936 ldr r1, [pc, #216] @ (80111b8 ) + 80110e0: 4313 orrs r3, r2 + 80110e2: 604b str r3, [r1, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80110e4: f7fd fb74 bl 800e7d0 + 80110e8: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80110ea: e00a b.n 8011102 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80110ec: f7fd fb70 bl 800e7d0 + 80110f0: 4602 mov r2, r0 + 80110f2: 68fb ldr r3, [r7, #12] + 80110f4: 1ad3 subs r3, r2, r3 + 80110f6: f241 3288 movw r2, #5000 @ 0x1388 + 80110fa: 4293 cmp r3, r2 + 80110fc: d901 bls.n 8011102 + { + return HAL_TIMEOUT; + 80110fe: 2303 movs r3, #3 + 8011100: e053 b.n 80111aa + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8011102: 4b2d ldr r3, [pc, #180] @ (80111b8 ) + 8011104: 685b ldr r3, [r3, #4] + 8011106: f003 020c and.w r2, r3, #12 + 801110a: 687b ldr r3, [r7, #4] + 801110c: 685b ldr r3, [r3, #4] + 801110e: 009b lsls r3, r3, #2 + 8011110: 429a cmp r2, r3 + 8011112: d1eb bne.n 80110ec + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8011114: 4b27 ldr r3, [pc, #156] @ (80111b4 ) + 8011116: 681b ldr r3, [r3, #0] + 8011118: f003 0307 and.w r3, r3, #7 + 801111c: 683a ldr r2, [r7, #0] + 801111e: 429a cmp r2, r3 + 8011120: d210 bcs.n 8011144 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8011122: 4b24 ldr r3, [pc, #144] @ (80111b4 ) + 8011124: 681b ldr r3, [r3, #0] + 8011126: f023 0207 bic.w r2, r3, #7 + 801112a: 4922 ldr r1, [pc, #136] @ (80111b4 ) + 801112c: 683b ldr r3, [r7, #0] + 801112e: 4313 orrs r3, r2 + 8011130: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8011132: 4b20 ldr r3, [pc, #128] @ (80111b4 ) + 8011134: 681b ldr r3, [r3, #0] + 8011136: f003 0307 and.w r3, r3, #7 + 801113a: 683a ldr r2, [r7, #0] + 801113c: 429a cmp r2, r3 + 801113e: d001 beq.n 8011144 + { + return HAL_ERROR; + 8011140: 2301 movs r3, #1 + 8011142: e032 b.n 80111aa + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8011144: 687b ldr r3, [r7, #4] + 8011146: 681b ldr r3, [r3, #0] + 8011148: f003 0304 and.w r3, r3, #4 + 801114c: 2b00 cmp r3, #0 + 801114e: d008 beq.n 8011162 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8011150: 4b19 ldr r3, [pc, #100] @ (80111b8 ) + 8011152: 685b ldr r3, [r3, #4] + 8011154: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8011158: 687b ldr r3, [r7, #4] + 801115a: 68db ldr r3, [r3, #12] + 801115c: 4916 ldr r1, [pc, #88] @ (80111b8 ) + 801115e: 4313 orrs r3, r2 + 8011160: 604b str r3, [r1, #4] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8011162: 687b ldr r3, [r7, #4] + 8011164: 681b ldr r3, [r3, #0] + 8011166: f003 0308 and.w r3, r3, #8 + 801116a: 2b00 cmp r3, #0 + 801116c: d009 beq.n 8011182 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 801116e: 4b12 ldr r3, [pc, #72] @ (80111b8 ) + 8011170: 685b ldr r3, [r3, #4] + 8011172: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8011176: 687b ldr r3, [r7, #4] + 8011178: 691b ldr r3, [r3, #16] + 801117a: 00db lsls r3, r3, #3 + 801117c: 490e ldr r1, [pc, #56] @ (80111b8 ) + 801117e: 4313 orrs r3, r2 + 8011180: 604b str r3, [r1, #4] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 8011182: f000 f821 bl 80111c8 + 8011186: 4602 mov r2, r0 + 8011188: 4b0b ldr r3, [pc, #44] @ (80111b8 ) + 801118a: 685b ldr r3, [r3, #4] + 801118c: 091b lsrs r3, r3, #4 + 801118e: f003 030f and.w r3, r3, #15 + 8011192: 490a ldr r1, [pc, #40] @ (80111bc ) + 8011194: 5ccb ldrb r3, [r1, r3] + 8011196: fa22 f303 lsr.w r3, r2, r3 + 801119a: 4a09 ldr r2, [pc, #36] @ (80111c0 ) + 801119c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + 801119e: 4b09 ldr r3, [pc, #36] @ (80111c4 ) + 80111a0: 681b ldr r3, [r3, #0] + 80111a2: 4618 mov r0, r3 + 80111a4: f7fd fad2 bl 800e74c + + return HAL_OK; + 80111a8: 2300 movs r3, #0 +} + 80111aa: 4618 mov r0, r3 + 80111ac: 3710 adds r7, #16 + 80111ae: 46bd mov sp, r7 + 80111b0: bd80 pop {r7, pc} + 80111b2: bf00 nop + 80111b4: 40022000 .word 0x40022000 + 80111b8: 40021000 .word 0x40021000 + 80111bc: 08016bcc .word 0x08016bcc + 80111c0: 2000006c .word 0x2000006c + 80111c4: 20000070 .word 0x20000070 + +080111c8 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80111c8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 80111cc: b08e sub sp, #56 @ 0x38 + 80111ce: af00 add r7, sp, #0 +#else + static const uint8_t aPredivFactorTable[2U] = {1, 2}; +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 80111d0: 2300 movs r3, #0 + 80111d2: 62fb str r3, [r7, #44] @ 0x2c + 80111d4: 2300 movs r3, #0 + 80111d6: 62bb str r3, [r7, #40] @ 0x28 + 80111d8: 2300 movs r3, #0 + 80111da: 637b str r3, [r7, #52] @ 0x34 + 80111dc: 2300 movs r3, #0 + 80111de: 627b str r3, [r7, #36] @ 0x24 + uint32_t sysclockfreq = 0U; + 80111e0: 2300 movs r3, #0 + 80111e2: 633b str r3, [r7, #48] @ 0x30 +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; + 80111e4: 2300 movs r3, #0 + 80111e6: 623b str r3, [r7, #32] + 80111e8: 2300 movs r3, #0 + 80111ea: 61fb str r3, [r7, #28] +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + 80111ec: 4b4e ldr r3, [pc, #312] @ (8011328 ) + 80111ee: 685b ldr r3, [r3, #4] + 80111f0: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 80111f2: 6afb ldr r3, [r7, #44] @ 0x2c + 80111f4: f003 030c and.w r3, r3, #12 + 80111f8: 2b04 cmp r3, #4 + 80111fa: d002 beq.n 8011202 + 80111fc: 2b08 cmp r3, #8 + 80111fe: d003 beq.n 8011208 + 8011200: e089 b.n 8011316 + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8011202: 4b4a ldr r3, [pc, #296] @ (801132c ) + 8011204: 633b str r3, [r7, #48] @ 0x30 + break; + 8011206: e089 b.n 801131c + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + 8011208: 6afb ldr r3, [r7, #44] @ 0x2c + 801120a: 0c9b lsrs r3, r3, #18 + 801120c: f003 020f and.w r2, r3, #15 + 8011210: 4b47 ldr r3, [pc, #284] @ (8011330 ) + 8011212: 5c9b ldrb r3, [r3, r2] + 8011214: 627b str r3, [r7, #36] @ 0x24 + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 8011216: 6afb ldr r3, [r7, #44] @ 0x2c + 8011218: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 801121c: 2b00 cmp r3, #0 + 801121e: d072 beq.n 8011306 + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; + 8011220: 4b41 ldr r3, [pc, #260] @ (8011328 ) + 8011222: 6adb ldr r3, [r3, #44] @ 0x2c + 8011224: f003 020f and.w r2, r3, #15 + 8011228: 4b42 ldr r3, [pc, #264] @ (8011334 ) + 801122a: 5c9b ldrb r3, [r3, r2] + 801122c: 62bb str r3, [r7, #40] @ 0x28 +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /*RCC_CFGR2_PREDIV1*/ +#if defined(RCC_CFGR2_PREDIV1SRC) + + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + 801122e: 4b3e ldr r3, [pc, #248] @ (8011328 ) + 8011230: 6adb ldr r3, [r3, #44] @ 0x2c + 8011232: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8011236: 2b00 cmp r3, #0 + 8011238: d053 beq.n 80112e2 + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + 801123a: 4b3b ldr r3, [pc, #236] @ (8011328 ) + 801123c: 6adb ldr r3, [r3, #44] @ 0x2c + 801123e: 091b lsrs r3, r3, #4 + 8011240: f003 030f and.w r3, r3, #15 + 8011244: 3301 adds r3, #1 + 8011246: 623b str r3, [r7, #32] + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + 8011248: 4b37 ldr r3, [pc, #220] @ (8011328 ) + 801124a: 6adb ldr r3, [r3, #44] @ 0x2c + 801124c: 0a1b lsrs r3, r3, #8 + 801124e: f003 030f and.w r3, r3, #15 + 8011252: 3302 adds r3, #2 + 8011254: 61fb str r3, [r7, #28] + pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); + 8011256: 69fb ldr r3, [r7, #28] + 8011258: 2200 movs r2, #0 + 801125a: 469a mov sl, r3 + 801125c: 4693 mov fp, r2 + 801125e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8011260: 2200 movs r2, #0 + 8011262: 613b str r3, [r7, #16] + 8011264: 617a str r2, [r7, #20] + 8011266: 693b ldr r3, [r7, #16] + 8011268: fb03 f20b mul.w r2, r3, fp + 801126c: 697b ldr r3, [r7, #20] + 801126e: fb0a f303 mul.w r3, sl, r3 + 8011272: 4413 add r3, r2 + 8011274: 693a ldr r2, [r7, #16] + 8011276: fbaa 0102 umull r0, r1, sl, r2 + 801127a: 440b add r3, r1 + 801127c: 4619 mov r1, r3 + 801127e: 4b2b ldr r3, [pc, #172] @ (801132c ) + 8011280: fb03 f201 mul.w r2, r3, r1 + 8011284: 2300 movs r3, #0 + 8011286: fb00 f303 mul.w r3, r0, r3 + 801128a: 4413 add r3, r2 + 801128c: 4a27 ldr r2, [pc, #156] @ (801132c ) + 801128e: fba0 4502 umull r4, r5, r0, r2 + 8011292: 442b add r3, r5 + 8011294: 461d mov r5, r3 + 8011296: 6a3b ldr r3, [r7, #32] + 8011298: 2200 movs r2, #0 + 801129a: 60bb str r3, [r7, #8] + 801129c: 60fa str r2, [r7, #12] + 801129e: 6abb ldr r3, [r7, #40] @ 0x28 + 80112a0: 2200 movs r2, #0 + 80112a2: 603b str r3, [r7, #0] + 80112a4: 607a str r2, [r7, #4] + 80112a6: e9d7 0102 ldrd r0, r1, [r7, #8] + 80112aa: 460b mov r3, r1 + 80112ac: e9d7 ab00 ldrd sl, fp, [r7] + 80112b0: 4652 mov r2, sl + 80112b2: fb02 f203 mul.w r2, r2, r3 + 80112b6: 465b mov r3, fp + 80112b8: 4684 mov ip, r0 + 80112ba: fb0c f303 mul.w r3, ip, r3 + 80112be: 4413 add r3, r2 + 80112c0: 4602 mov r2, r0 + 80112c2: 4651 mov r1, sl + 80112c4: fba2 8901 umull r8, r9, r2, r1 + 80112c8: 444b add r3, r9 + 80112ca: 4699 mov r9, r3 + 80112cc: 4642 mov r2, r8 + 80112ce: 464b mov r3, r9 + 80112d0: 4620 mov r0, r4 + 80112d2: 4629 mov r1, r5 + 80112d4: f7f7 ffde bl 8009294 <__aeabi_uldivmod> + 80112d8: 4602 mov r2, r0 + 80112da: 460b mov r3, r1 + 80112dc: 4613 mov r3, r2 + 80112de: 637b str r3, [r7, #52] @ 0x34 + 80112e0: e007 b.n 80112f2 + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + 80112e2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80112e4: 4a11 ldr r2, [pc, #68] @ (801132c ) + 80112e6: fb03 f202 mul.w r2, r3, r2 + 80112ea: 6abb ldr r3, [r7, #40] @ 0x28 + 80112ec: fbb2 f3f3 udiv r3, r2, r3 + 80112f0: 637b str r3, [r7, #52] @ 0x34 + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + 80112f2: 4b0f ldr r3, [pc, #60] @ (8011330 ) + 80112f4: 7b5b ldrb r3, [r3, #13] + 80112f6: 461a mov r2, r3 + 80112f8: 6a7b ldr r3, [r7, #36] @ 0x24 + 80112fa: 4293 cmp r3, r2 + 80112fc: d108 bne.n 8011310 + { + pllclk = pllclk / 2; + 80112fe: 6b7b ldr r3, [r7, #52] @ 0x34 + 8011300: 085b lsrs r3, r3, #1 + 8011302: 637b str r3, [r7, #52] @ 0x34 + 8011304: e004 b.n 8011310 +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + 8011306: 6a7b ldr r3, [r7, #36] @ 0x24 + 8011308: 4a0b ldr r2, [pc, #44] @ (8011338 ) + 801130a: fb02 f303 mul.w r3, r2, r3 + 801130e: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllclk; + 8011310: 6b7b ldr r3, [r7, #52] @ 0x34 + 8011312: 633b str r3, [r7, #48] @ 0x30 + break; + 8011314: e002 b.n 801131c + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + 8011316: 4b09 ldr r3, [pc, #36] @ (801133c ) + 8011318: 633b str r3, [r7, #48] @ 0x30 + break; + 801131a: bf00 nop + } + } + return sysclockfreq; + 801131c: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 801131e: 4618 mov r0, r3 + 8011320: 3738 adds r7, #56 @ 0x38 + 8011322: 46bd mov sp, r7 + 8011324: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8011328: 40021000 .word 0x40021000 + 801132c: 017d7840 .word 0x017d7840 + 8011330: 08016be4 .word 0x08016be4 + 8011334: 08016bf4 .word 0x08016bf4 + 8011338: 003d0900 .word 0x003d0900 + 801133c: 007a1200 .word 0x007a1200 + +08011340 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8011340: b480 push {r7} + 8011342: af00 add r7, sp, #0 + return SystemCoreClock; + 8011344: 4b02 ldr r3, [pc, #8] @ (8011350 ) + 8011346: 681b ldr r3, [r3, #0] +} + 8011348: 4618 mov r0, r3 + 801134a: 46bd mov sp, r7 + 801134c: bc80 pop {r7} + 801134e: 4770 bx lr + 8011350: 2000006c .word 0x2000006c + +08011354 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8011354: b580 push {r7, lr} + 8011356: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 8011358: f7ff fff2 bl 8011340 + 801135c: 4602 mov r2, r0 + 801135e: 4b05 ldr r3, [pc, #20] @ (8011374 ) + 8011360: 685b ldr r3, [r3, #4] + 8011362: 0a1b lsrs r3, r3, #8 + 8011364: f003 0307 and.w r3, r3, #7 + 8011368: 4903 ldr r1, [pc, #12] @ (8011378 ) + 801136a: 5ccb ldrb r3, [r1, r3] + 801136c: fa22 f303 lsr.w r3, r2, r3 +} + 8011370: 4618 mov r0, r3 + 8011372: bd80 pop {r7, pc} + 8011374: 40021000 .word 0x40021000 + 8011378: 08016bdc .word 0x08016bdc + +0801137c : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 801137c: b580 push {r7, lr} + 801137e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + 8011380: f7ff ffde bl 8011340 + 8011384: 4602 mov r2, r0 + 8011386: 4b05 ldr r3, [pc, #20] @ (801139c ) + 8011388: 685b ldr r3, [r3, #4] + 801138a: 0adb lsrs r3, r3, #11 + 801138c: f003 0307 and.w r3, r3, #7 + 8011390: 4903 ldr r1, [pc, #12] @ (80113a0 ) + 8011392: 5ccb ldrb r3, [r1, r3] + 8011394: fa22 f303 lsr.w r3, r2, r3 +} + 8011398: 4618 mov r0, r3 + 801139a: bd80 pop {r7, pc} + 801139c: 40021000 .word 0x40021000 + 80113a0: 08016bdc .word 0x08016bdc + +080113a4 : + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + 80113a4: b480 push {r7} + 80113a6: b085 sub sp, #20 + 80113a8: af00 add r7, sp, #0 + 80113aa: 6078 str r0, [r7, #4] + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + 80113ac: 4b0a ldr r3, [pc, #40] @ (80113d8 ) + 80113ae: 681b ldr r3, [r3, #0] + 80113b0: 4a0a ldr r2, [pc, #40] @ (80113dc ) + 80113b2: fba2 2303 umull r2, r3, r2, r3 + 80113b6: 0a5b lsrs r3, r3, #9 + 80113b8: 687a ldr r2, [r7, #4] + 80113ba: fb02 f303 mul.w r3, r2, r3 + 80113be: 60fb str r3, [r7, #12] + do + { + __NOP(); + 80113c0: bf00 nop + } + while (Delay --); + 80113c2: 68fb ldr r3, [r7, #12] + 80113c4: 1e5a subs r2, r3, #1 + 80113c6: 60fa str r2, [r7, #12] + 80113c8: 2b00 cmp r3, #0 + 80113ca: d1f9 bne.n 80113c0 +} + 80113cc: bf00 nop + 80113ce: bf00 nop + 80113d0: 3714 adds r7, #20 + 80113d2: 46bd mov sp, r7 + 80113d4: bc80 pop {r7} + 80113d6: 4770 bx lr + 80113d8: 2000006c .word 0x2000006c + 80113dc: 10624dd3 .word 0x10624dd3 + +080113e0 : + * manually disable it. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 80113e0: b580 push {r7, lr} + 80113e2: b088 sub sp, #32 + 80113e4: af00 add r7, sp, #0 + 80113e6: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U, temp_reg = 0U; + 80113e8: 2300 movs r3, #0 + 80113ea: 617b str r3, [r7, #20] + 80113ec: 2300 movs r3, #0 + 80113ee: 613b str r3, [r7, #16] +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t pllactive = 0U; + 80113f0: 2300 movs r3, #0 + 80113f2: 61fb str r3, [r7, #28] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + 80113f4: 687b ldr r3, [r7, #4] + 80113f6: 681b ldr r3, [r3, #0] + 80113f8: f003 0301 and.w r3, r3, #1 + 80113fc: 2b00 cmp r3, #0 + 80113fe: d07d beq.n 80114fc + { + FlagStatus pwrclkchanged = RESET; + 8011400: 2300 movs r3, #0 + 8011402: 76fb strb r3, [r7, #27] + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8011404: 4b8b ldr r3, [pc, #556] @ (8011634 ) + 8011406: 69db ldr r3, [r3, #28] + 8011408: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 801140c: 2b00 cmp r3, #0 + 801140e: d10d bne.n 801142c + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8011410: 4b88 ldr r3, [pc, #544] @ (8011634 ) + 8011412: 69db ldr r3, [r3, #28] + 8011414: 4a87 ldr r2, [pc, #540] @ (8011634 ) + 8011416: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 801141a: 61d3 str r3, [r2, #28] + 801141c: 4b85 ldr r3, [pc, #532] @ (8011634 ) + 801141e: 69db ldr r3, [r3, #28] + 8011420: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8011424: 60fb str r3, [r7, #12] + 8011426: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 8011428: 2301 movs r3, #1 + 801142a: 76fb strb r3, [r7, #27] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 801142c: 4b82 ldr r3, [pc, #520] @ (8011638 ) + 801142e: 681b ldr r3, [r3, #0] + 8011430: f403 7380 and.w r3, r3, #256 @ 0x100 + 8011434: 2b00 cmp r3, #0 + 8011436: d118 bne.n 801146a + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8011438: 4b7f ldr r3, [pc, #508] @ (8011638 ) + 801143a: 681b ldr r3, [r3, #0] + 801143c: 4a7e ldr r2, [pc, #504] @ (8011638 ) + 801143e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8011442: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8011444: f7fd f9c4 bl 800e7d0 + 8011448: 6178 str r0, [r7, #20] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 801144a: e008 b.n 801145e + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 801144c: f7fd f9c0 bl 800e7d0 + 8011450: 4602 mov r2, r0 + 8011452: 697b ldr r3, [r7, #20] + 8011454: 1ad3 subs r3, r2, r3 + 8011456: 2b64 cmp r3, #100 @ 0x64 + 8011458: d901 bls.n 801145e + { + return HAL_TIMEOUT; + 801145a: 2303 movs r3, #3 + 801145c: e0e5 b.n 801162a + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 801145e: 4b76 ldr r3, [pc, #472] @ (8011638 ) + 8011460: 681b ldr r3, [r3, #0] + 8011462: f403 7380 and.w r3, r3, #256 @ 0x100 + 8011466: 2b00 cmp r3, #0 + 8011468: d0f0 beq.n 801144c + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 801146a: 4b72 ldr r3, [pc, #456] @ (8011634 ) + 801146c: 6a1b ldr r3, [r3, #32] + 801146e: f403 7340 and.w r3, r3, #768 @ 0x300 + 8011472: 613b str r3, [r7, #16] + if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8011474: 693b ldr r3, [r7, #16] + 8011476: 2b00 cmp r3, #0 + 8011478: d02e beq.n 80114d8 + 801147a: 687b ldr r3, [r7, #4] + 801147c: 685b ldr r3, [r3, #4] + 801147e: f403 7340 and.w r3, r3, #768 @ 0x300 + 8011482: 693a ldr r2, [r7, #16] + 8011484: 429a cmp r2, r3 + 8011486: d027 beq.n 80114d8 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8011488: 4b6a ldr r3, [pc, #424] @ (8011634 ) + 801148a: 6a1b ldr r3, [r3, #32] + 801148c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8011490: 613b str r3, [r7, #16] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8011492: 4b6a ldr r3, [pc, #424] @ (801163c ) + 8011494: 2201 movs r2, #1 + 8011496: 601a str r2, [r3, #0] + __HAL_RCC_BACKUPRESET_RELEASE(); + 8011498: 4b68 ldr r3, [pc, #416] @ (801163c ) + 801149a: 2200 movs r2, #0 + 801149c: 601a str r2, [r3, #0] + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + 801149e: 4a65 ldr r2, [pc, #404] @ (8011634 ) + 80114a0: 693b ldr r3, [r7, #16] + 80114a2: 6213 str r3, [r2, #32] + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 80114a4: 693b ldr r3, [r7, #16] + 80114a6: f003 0301 and.w r3, r3, #1 + 80114aa: 2b00 cmp r3, #0 + 80114ac: d014 beq.n 80114d8 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80114ae: f7fd f98f bl 800e7d0 + 80114b2: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80114b4: e00a b.n 80114cc + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80114b6: f7fd f98b bl 800e7d0 + 80114ba: 4602 mov r2, r0 + 80114bc: 697b ldr r3, [r7, #20] + 80114be: 1ad3 subs r3, r2, r3 + 80114c0: f241 3288 movw r2, #5000 @ 0x1388 + 80114c4: 4293 cmp r3, r2 + 80114c6: d901 bls.n 80114cc + { + return HAL_TIMEOUT; + 80114c8: 2303 movs r3, #3 + 80114ca: e0ae b.n 801162a + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80114cc: 4b59 ldr r3, [pc, #356] @ (8011634 ) + 80114ce: 6a1b ldr r3, [r3, #32] + 80114d0: f003 0302 and.w r3, r3, #2 + 80114d4: 2b00 cmp r3, #0 + 80114d6: d0ee beq.n 80114b6 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 80114d8: 4b56 ldr r3, [pc, #344] @ (8011634 ) + 80114da: 6a1b ldr r3, [r3, #32] + 80114dc: f423 7240 bic.w r2, r3, #768 @ 0x300 + 80114e0: 687b ldr r3, [r7, #4] + 80114e2: 685b ldr r3, [r3, #4] + 80114e4: 4953 ldr r1, [pc, #332] @ (8011634 ) + 80114e6: 4313 orrs r3, r2 + 80114e8: 620b str r3, [r1, #32] + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + 80114ea: 7efb ldrb r3, [r7, #27] + 80114ec: 2b01 cmp r3, #1 + 80114ee: d105 bne.n 80114fc + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80114f0: 4b50 ldr r3, [pc, #320] @ (8011634 ) + 80114f2: 69db ldr r3, [r3, #28] + 80114f4: 4a4f ldr r2, [pc, #316] @ (8011634 ) + 80114f6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80114fa: 61d3 str r3, [r2, #28] + } + } + + /*------------------------------ ADC clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 80114fc: 687b ldr r3, [r7, #4] + 80114fe: 681b ldr r3, [r3, #0] + 8011500: f003 0302 and.w r3, r3, #2 + 8011504: 2b00 cmp r3, #0 + 8011506: d008 beq.n 801151a + { + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8011508: 4b4a ldr r3, [pc, #296] @ (8011634 ) + 801150a: 685b ldr r3, [r3, #4] + 801150c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 + 8011510: 687b ldr r3, [r7, #4] + 8011512: 689b ldr r3, [r3, #8] + 8011514: 4947 ldr r1, [pc, #284] @ (8011634 ) + 8011516: 4313 orrs r3, r2 + 8011518: 604b str r3, [r1, #4] + } + +#if defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ I2S2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + 801151a: 687b ldr r3, [r7, #4] + 801151c: 681b ldr r3, [r3, #0] + 801151e: f003 0304 and.w r3, r3, #4 + 8011522: 2b00 cmp r3, #0 + 8011524: d008 beq.n 8011538 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 8011526: 4b43 ldr r3, [pc, #268] @ (8011634 ) + 8011528: 6adb ldr r3, [r3, #44] @ 0x2c + 801152a: f423 3200 bic.w r2, r3, #131072 @ 0x20000 + 801152e: 687b ldr r3, [r7, #4] + 8011530: 68db ldr r3, [r3, #12] + 8011532: 4940 ldr r1, [pc, #256] @ (8011634 ) + 8011534: 4313 orrs r3, r2 + 8011536: 62cb str r3, [r1, #44] @ 0x2c + } + + /*------------------------------ I2S3 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) + 8011538: 687b ldr r3, [r7, #4] + 801153a: 681b ldr r3, [r3, #0] + 801153c: f003 0308 and.w r3, r3, #8 + 8011540: 2b00 cmp r3, #0 + 8011542: d008 beq.n 8011556 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); + + /* Configure the I2S3 clock source */ + __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); + 8011544: 4b3b ldr r3, [pc, #236] @ (8011634 ) + 8011546: 6adb ldr r3, [r3, #44] @ 0x2c + 8011548: f423 2280 bic.w r2, r3, #262144 @ 0x40000 + 801154c: 687b ldr r3, [r7, #4] + 801154e: 691b ldr r3, [r3, #16] + 8011550: 4938 ldr r1, [pc, #224] @ (8011634 ) + 8011552: 4313 orrs r3, r2 + 8011554: 62cb str r3, [r1, #44] @ 0x2c + } + + /*------------------------------ PLL I2S Configuration ----------------------*/ + /* Check that PLLI2S need to be enabled */ + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + 8011556: 4b37 ldr r3, [pc, #220] @ (8011634 ) + 8011558: 6adb ldr r3, [r3, #44] @ 0x2c + 801155a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 801155e: 2b00 cmp r3, #0 + 8011560: d105 bne.n 801156e + 8011562: 4b34 ldr r3, [pc, #208] @ (8011634 ) + 8011564: 6adb ldr r3, [r3, #44] @ 0x2c + 8011566: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 801156a: 2b00 cmp r3, #0 + 801156c: d001 beq.n 8011572 + { + /* Update flag to indicate that PLL I2S should be active */ + pllactive = 1; + 801156e: 2301 movs r3, #1 + 8011570: 61fb str r3, [r7, #28] + } + + /* Check if PLL I2S need to be enabled */ + if (pllactive == 1) + 8011572: 69fb ldr r3, [r7, #28] + 8011574: 2b01 cmp r3, #1 + 8011576: d148 bne.n 801160a + { + /* Enable PLL I2S only if not active */ + if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) + 8011578: 4b2e ldr r3, [pc, #184] @ (8011634 ) + 801157a: 681b ldr r3, [r3, #0] + 801157c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8011580: 2b00 cmp r3, #0 + 8011582: d138 bne.n 80115f6 + assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + 8011584: 4b2b ldr r3, [pc, #172] @ (8011634 ) + 8011586: 681b ldr r3, [r3, #0] + 8011588: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 801158c: 2b00 cmp r3, #0 + 801158e: d009 beq.n 80115a4 + (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) + 8011590: 4b28 ldr r3, [pc, #160] @ (8011634 ) + 8011592: 6adb ldr r3, [r3, #44] @ 0x2c + 8011594: f003 02f0 and.w r2, r3, #240 @ 0xf0 + 8011598: 687b ldr r3, [r7, #4] + 801159a: 699b ldr r3, [r3, #24] + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + 801159c: 429a cmp r2, r3 + 801159e: d001 beq.n 80115a4 + { + return HAL_ERROR; + 80115a0: 2301 movs r3, #1 + 80115a2: e042 b.n 801162a + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); + 80115a4: 4b23 ldr r3, [pc, #140] @ (8011634 ) + 80115a6: 6adb ldr r3, [r3, #44] @ 0x2c + 80115a8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80115ac: 687b ldr r3, [r7, #4] + 80115ae: 699b ldr r3, [r3, #24] + 80115b0: 4920 ldr r1, [pc, #128] @ (8011634 ) + 80115b2: 4313 orrs r3, r2 + 80115b4: 62cb str r3, [r1, #44] @ 0x2c + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); + 80115b6: 4b1f ldr r3, [pc, #124] @ (8011634 ) + 80115b8: 6adb ldr r3, [r3, #44] @ 0x2c + 80115ba: f423 4270 bic.w r2, r3, #61440 @ 0xf000 + 80115be: 687b ldr r3, [r7, #4] + 80115c0: 695b ldr r3, [r3, #20] + 80115c2: 491c ldr r1, [pc, #112] @ (8011634 ) + 80115c4: 4313 orrs r3, r2 + 80115c6: 62cb str r3, [r1, #44] @ 0x2c + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + 80115c8: 4b1d ldr r3, [pc, #116] @ (8011640 ) + 80115ca: 2201 movs r2, #1 + 80115cc: 601a str r2, [r3, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80115ce: f7fd f8ff bl 800e7d0 + 80115d2: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80115d4: e008 b.n 80115e8 + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 80115d6: f7fd f8fb bl 800e7d0 + 80115da: 4602 mov r2, r0 + 80115dc: 697b ldr r3, [r7, #20] + 80115de: 1ad3 subs r3, r2, r3 + 80115e0: 2b64 cmp r3, #100 @ 0x64 + 80115e2: d901 bls.n 80115e8 + { + return HAL_TIMEOUT; + 80115e4: 2303 movs r3, #3 + 80115e6: e020 b.n 801162a + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80115e8: 4b12 ldr r3, [pc, #72] @ (8011634 ) + 80115ea: 681b ldr r3, [r3, #0] + 80115ec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 80115f0: 2b00 cmp r3, #0 + 80115f2: d0f0 beq.n 80115d6 + 80115f4: e009 b.n 801160a + } + } + else + { + /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ + if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) + 80115f6: 4b0f ldr r3, [pc, #60] @ (8011634 ) + 80115f8: 6adb ldr r3, [r3, #44] @ 0x2c + 80115fa: f403 4270 and.w r2, r3, #61440 @ 0xf000 + 80115fe: 687b ldr r3, [r7, #4] + 8011600: 695b ldr r3, [r3, #20] + 8011602: 429a cmp r2, r3 + 8011604: d001 beq.n 801160a + { + return HAL_ERROR; + 8011606: 2301 movs r3, #1 + 8011608: e00f b.n 801162a + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ USB clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 801160a: 687b ldr r3, [r7, #4] + 801160c: 681b ldr r3, [r3, #0] + 801160e: f003 0310 and.w r3, r3, #16 + 8011612: 2b00 cmp r3, #0 + 8011614: d008 beq.n 8011628 + { + /* Check the parameters */ + assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 8011616: 4b07 ldr r3, [pc, #28] @ (8011634 ) + 8011618: 685b ldr r3, [r3, #4] + 801161a: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 + 801161e: 687b ldr r3, [r7, #4] + 8011620: 69db ldr r3, [r3, #28] + 8011622: 4904 ldr r1, [pc, #16] @ (8011634 ) + 8011624: 4313 orrs r3, r2 + 8011626: 604b str r3, [r1, #4] + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + + return HAL_OK; + 8011628: 2300 movs r3, #0 +} + 801162a: 4618 mov r0, r3 + 801162c: 3720 adds r7, #32 + 801162e: 46bd mov sp, r7 + 8011630: bd80 pop {r7, pc} + 8011632: bf00 nop + 8011634: 40021000 .word 0x40021000 + 8011638: 40007000 .word 0x40007000 + 801163c: 42420440 .word 0x42420440 + 8011640: 42420070 .word 0x42420070 + +08011644 : + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + 8011644: b580 push {r7, lr} + 8011646: b08a sub sp, #40 @ 0x28 + 8011648: af00 add r7, sp, #0 + 801164a: 6078 str r0, [r7, #4] +#if defined(STM32F105xC) || defined(STM32F107xC) + static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + 801164c: 2300 movs r3, #0 + 801164e: 61fb str r3, [r7, #28] + 8011650: 2300 movs r3, #0 + 8011652: 627b str r3, [r7, #36] @ 0x24 + 8011654: 2300 movs r3, #0 + 8011656: 61bb str r3, [r7, #24] + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; + 8011658: 2300 movs r3, #0 + 801165a: 617b str r3, [r7, #20] + 801165c: 2300 movs r3, #0 + 801165e: 613b str r3, [r7, #16] + 8011660: 2300 movs r3, #0 + 8011662: 60fb str r3, [r7, #12] + static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + static const uint8_t aPredivFactorTable[2U] = {1, 2}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; + 8011664: 2300 movs r3, #0 + 8011666: 60bb str r3, [r7, #8] + 8011668: 2300 movs r3, #0 + 801166a: 623b str r3, [r7, #32] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + 801166c: 687b ldr r3, [r7, #4] + 801166e: 3b01 subs r3, #1 + 8011670: 2b0f cmp r3, #15 + 8011672: f200 811d bhi.w 80118b0 + 8011676: a201 add r2, pc, #4 @ (adr r2, 801167c ) + 8011678: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 801167c: 08011831 .word 0x08011831 + 8011680: 08011895 .word 0x08011895 + 8011684: 080118b1 .word 0x080118b1 + 8011688: 0801178f .word 0x0801178f + 801168c: 080118b1 .word 0x080118b1 + 8011690: 080118b1 .word 0x080118b1 + 8011694: 080118b1 .word 0x080118b1 + 8011698: 080117e1 .word 0x080117e1 + 801169c: 080118b1 .word 0x080118b1 + 80116a0: 080118b1 .word 0x080118b1 + 80116a4: 080118b1 .word 0x080118b1 + 80116a8: 080118b1 .word 0x080118b1 + 80116ac: 080118b1 .word 0x080118b1 + 80116b0: 080118b1 .word 0x080118b1 + 80116b4: 080118b1 .word 0x080118b1 + 80116b8: 080116bd .word 0x080116bd + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_USB: + { + /* Get RCC configuration ------------------------------------------------------*/ + temp_reg = RCC->CFGR; + 80116bc: 4b83 ldr r3, [pc, #524] @ (80118cc ) + 80116be: 685b ldr r3, [r3, #4] + 80116c0: 60bb str r3, [r7, #8] + + /* Check if PLL is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) + 80116c2: 4b82 ldr r3, [pc, #520] @ (80118cc ) + 80116c4: 681b ldr r3, [r3, #0] + 80116c6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 80116ca: 2b00 cmp r3, #0 + 80116cc: f000 80f2 beq.w 80118b4 + { + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + 80116d0: 68bb ldr r3, [r7, #8] + 80116d2: 0c9b lsrs r3, r3, #18 + 80116d4: f003 030f and.w r3, r3, #15 + 80116d8: 4a7d ldr r2, [pc, #500] @ (80118d0 ) + 80116da: 5cd3 ldrb r3, [r2, r3] + 80116dc: 61bb str r3, [r7, #24] + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 80116de: 68bb ldr r3, [r7, #8] + 80116e0: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80116e4: 2b00 cmp r3, #0 + 80116e6: d03b beq.n 8011760 + { +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; + 80116e8: 4b78 ldr r3, [pc, #480] @ (80118cc ) + 80116ea: 6adb ldr r3, [r3, #44] @ 0x2c + 80116ec: f003 030f and.w r3, r3, #15 + 80116f0: 4a78 ldr r2, [pc, #480] @ (80118d4 ) + 80116f2: 5cd3 ldrb r3, [r2, r3] + 80116f4: 61fb str r3, [r7, #28] +#else + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + 80116f6: 4b75 ldr r3, [pc, #468] @ (80118cc ) + 80116f8: 6adb ldr r3, [r3, #44] @ 0x2c + 80116fa: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80116fe: 2b00 cmp r3, #0 + 8011700: d01c beq.n 801173c + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + 8011702: 4b72 ldr r3, [pc, #456] @ (80118cc ) + 8011704: 6adb ldr r3, [r3, #44] @ 0x2c + 8011706: 091b lsrs r3, r3, #4 + 8011708: f003 030f and.w r3, r3, #15 + 801170c: 3301 adds r3, #1 + 801170e: 60fb str r3, [r7, #12] + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + 8011710: 4b6e ldr r3, [pc, #440] @ (80118cc ) + 8011712: 6adb ldr r3, [r3, #44] @ 0x2c + 8011714: 0a1b lsrs r3, r3, #8 + 8011716: f003 030f and.w r3, r3, #15 + 801171a: 3302 adds r3, #2 + 801171c: 617b str r3, [r7, #20] + pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); + 801171e: 4a6e ldr r2, [pc, #440] @ (80118d8 ) + 8011720: 68fb ldr r3, [r7, #12] + 8011722: fbb2 f3f3 udiv r3, r2, r3 + 8011726: 697a ldr r2, [r7, #20] + 8011728: fb03 f202 mul.w r2, r3, r2 + 801172c: 69fb ldr r3, [r7, #28] + 801172e: fbb2 f2f3 udiv r2, r2, r3 + 8011732: 69bb ldr r3, [r7, #24] + 8011734: fb02 f303 mul.w r3, r2, r3 + 8011738: 627b str r3, [r7, #36] @ 0x24 + 801173a: e007 b.n 801174c + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + 801173c: 4a66 ldr r2, [pc, #408] @ (80118d8 ) + 801173e: 69fb ldr r3, [r7, #28] + 8011740: fbb2 f2f3 udiv r2, r2, r3 + 8011744: 69bb ldr r3, [r7, #24] + 8011746: fb02 f303 mul.w r3, r2, r3 + 801174a: 627b str r3, [r7, #36] @ 0x24 + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + 801174c: 4b60 ldr r3, [pc, #384] @ (80118d0 ) + 801174e: 7b5b ldrb r3, [r3, #13] + 8011750: 461a mov r2, r3 + 8011752: 69bb ldr r3, [r7, #24] + 8011754: 4293 cmp r3, r2 + 8011756: d108 bne.n 801176a + { + pllclk = pllclk / 2; + 8011758: 6a7b ldr r3, [r7, #36] @ 0x24 + 801175a: 085b lsrs r3, r3, #1 + 801175c: 627b str r3, [r7, #36] @ 0x24 + 801175e: e004 b.n 801176a +#endif /* STM32F105xC || STM32F107xC */ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + 8011760: 69bb ldr r3, [r7, #24] + 8011762: 4a5e ldr r2, [pc, #376] @ (80118dc ) + 8011764: fb02 f303 mul.w r3, r2, r3 + 8011768: 627b str r3, [r7, #36] @ 0x24 + } + + /* Calcul of the USB frequency*/ +#if defined(STM32F105xC) || defined(STM32F107xC) + /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) + 801176a: 4b58 ldr r3, [pc, #352] @ (80118cc ) + 801176c: 685b ldr r3, [r3, #4] + 801176e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8011772: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8011776: d102 bne.n 801177e + { + /* Prescaler of 2 selected for USB */ + frequency = pllclk; + 8011778: 6a7b ldr r3, [r7, #36] @ 0x24 + 801177a: 623b str r3, [r7, #32] + /* Prescaler of 1.5 selected for USB */ + frequency = (pllclk * 2) / 3; + } +#endif + } + break; + 801177c: e09a b.n 80118b4 + frequency = (2 * pllclk) / 3; + 801177e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8011780: 005b lsls r3, r3, #1 + 8011782: 4a57 ldr r2, [pc, #348] @ (80118e0 ) + 8011784: fba2 2303 umull r2, r3, r2, r3 + 8011788: 085b lsrs r3, r3, #1 + 801178a: 623b str r3, [r7, #32] + break; + 801178c: e092 b.n 80118b4 + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) + 801178e: 4b4f ldr r3, [pc, #316] @ (80118cc ) + 8011790: 6adb ldr r3, [r3, #44] @ 0x2c + 8011792: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8011796: 2b00 cmp r3, #0 + 8011798: d103 bne.n 80117a2 + { + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); + 801179a: f7ff fd15 bl 80111c8 + 801179e: 6238 str r0, [r7, #32] + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + 80117a0: e08a b.n 80118b8 + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + 80117a2: 4b4a ldr r3, [pc, #296] @ (80118cc ) + 80117a4: 681b ldr r3, [r3, #0] + 80117a6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80117aa: 2b00 cmp r3, #0 + 80117ac: f000 8084 beq.w 80118b8 + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + 80117b0: 4b46 ldr r3, [pc, #280] @ (80118cc ) + 80117b2: 6adb ldr r3, [r3, #44] @ 0x2c + 80117b4: 091b lsrs r3, r3, #4 + 80117b6: f003 030f and.w r3, r3, #15 + 80117ba: 3301 adds r3, #1 + 80117bc: 60fb str r3, [r7, #12] + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + 80117be: 4b43 ldr r3, [pc, #268] @ (80118cc ) + 80117c0: 6adb ldr r3, [r3, #44] @ 0x2c + 80117c2: 0b1b lsrs r3, r3, #12 + 80117c4: f003 030f and.w r3, r3, #15 + 80117c8: 3302 adds r3, #2 + 80117ca: 613b str r3, [r7, #16] + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + 80117cc: 4a42 ldr r2, [pc, #264] @ (80118d8 ) + 80117ce: 68fb ldr r3, [r7, #12] + 80117d0: fbb2 f3f3 udiv r3, r2, r3 + 80117d4: 693a ldr r2, [r7, #16] + 80117d6: fb02 f303 mul.w r3, r2, r3 + 80117da: 005b lsls r3, r3, #1 + 80117dc: 623b str r3, [r7, #32] + break; + 80117de: e06b b.n 80118b8 + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) + 80117e0: 4b3a ldr r3, [pc, #232] @ (80118cc ) + 80117e2: 6adb ldr r3, [r3, #44] @ 0x2c + 80117e4: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 80117e8: 2b00 cmp r3, #0 + 80117ea: d103 bne.n 80117f4 + { + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); + 80117ec: f7ff fcec bl 80111c8 + 80117f0: 6238 str r0, [r7, #32] + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + 80117f2: e063 b.n 80118bc + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + 80117f4: 4b35 ldr r3, [pc, #212] @ (80118cc ) + 80117f6: 681b ldr r3, [r3, #0] + 80117f8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80117fc: 2b00 cmp r3, #0 + 80117fe: d05d beq.n 80118bc + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + 8011800: 4b32 ldr r3, [pc, #200] @ (80118cc ) + 8011802: 6adb ldr r3, [r3, #44] @ 0x2c + 8011804: 091b lsrs r3, r3, #4 + 8011806: f003 030f and.w r3, r3, #15 + 801180a: 3301 adds r3, #1 + 801180c: 60fb str r3, [r7, #12] + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + 801180e: 4b2f ldr r3, [pc, #188] @ (80118cc ) + 8011810: 6adb ldr r3, [r3, #44] @ 0x2c + 8011812: 0b1b lsrs r3, r3, #12 + 8011814: f003 030f and.w r3, r3, #15 + 8011818: 3302 adds r3, #2 + 801181a: 613b str r3, [r7, #16] + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + 801181c: 4a2e ldr r2, [pc, #184] @ (80118d8 ) + 801181e: 68fb ldr r3, [r7, #12] + 8011820: fbb2 f3f3 udiv r3, r2, r3 + 8011824: 693a ldr r2, [r7, #16] + 8011826: fb02 f303 mul.w r3, r2, r3 + 801182a: 005b lsls r3, r3, #1 + 801182c: 623b str r3, [r7, #32] + break; + 801182e: e045 b.n 80118bc + } +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + case RCC_PERIPHCLK_RTC: + { + /* Get RCC BDCR configuration ------------------------------------------------------*/ + temp_reg = RCC->BDCR; + 8011830: 4b26 ldr r3, [pc, #152] @ (80118cc ) + 8011832: 6a1b ldr r3, [r3, #32] + 8011834: 60bb str r3, [r7, #8] + + /* Check if LSE is ready if RTC clock selection is LSE */ + if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) + 8011836: 68bb ldr r3, [r7, #8] + 8011838: f403 7340 and.w r3, r3, #768 @ 0x300 + 801183c: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8011840: d108 bne.n 8011854 + 8011842: 68bb ldr r3, [r7, #8] + 8011844: f003 0302 and.w r3, r3, #2 + 8011848: 2b00 cmp r3, #0 + 801184a: d003 beq.n 8011854 + { + frequency = LSE_VALUE; + 801184c: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8011850: 623b str r3, [r7, #32] + 8011852: e01e b.n 8011892 + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + 8011854: 68bb ldr r3, [r7, #8] + 8011856: f403 7340 and.w r3, r3, #768 @ 0x300 + 801185a: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 801185e: d109 bne.n 8011874 + 8011860: 4b1a ldr r3, [pc, #104] @ (80118cc ) + 8011862: 6a5b ldr r3, [r3, #36] @ 0x24 + 8011864: f003 0302 and.w r3, r3, #2 + 8011868: 2b00 cmp r3, #0 + 801186a: d003 beq.n 8011874 + { + frequency = LSI_VALUE; + 801186c: f649 4340 movw r3, #40000 @ 0x9c40 + 8011870: 623b str r3, [r7, #32] + 8011872: e00e b.n 8011892 + } + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + 8011874: 68bb ldr r3, [r7, #8] + 8011876: f403 7340 and.w r3, r3, #768 @ 0x300 + 801187a: f5b3 7f40 cmp.w r3, #768 @ 0x300 + 801187e: d11f bne.n 80118c0 + 8011880: 4b12 ldr r3, [pc, #72] @ (80118cc ) + 8011882: 681b ldr r3, [r3, #0] + 8011884: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8011888: 2b00 cmp r3, #0 + 801188a: d019 beq.n 80118c0 + { + frequency = HSE_VALUE / 128U; + 801188c: 4b15 ldr r3, [pc, #84] @ (80118e4 ) + 801188e: 623b str r3, [r7, #32] + /* Clock not enabled for RTC*/ + else + { + /* nothing to do: frequency already initialized to 0U */ + } + break; + 8011890: e016 b.n 80118c0 + 8011892: e015 b.n 80118c0 + } + case RCC_PERIPHCLK_ADC: + { + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + 8011894: f7ff fd72 bl 801137c + 8011898: 4602 mov r2, r0 + 801189a: 4b0c ldr r3, [pc, #48] @ (80118cc ) + 801189c: 685b ldr r3, [r3, #4] + 801189e: 0b9b lsrs r3, r3, #14 + 80118a0: f003 0303 and.w r3, r3, #3 + 80118a4: 3301 adds r3, #1 + 80118a6: 005b lsls r3, r3, #1 + 80118a8: fbb2 f3f3 udiv r3, r2, r3 + 80118ac: 623b str r3, [r7, #32] + break; + 80118ae: e008 b.n 80118c2 + } + default: + { + break; + 80118b0: bf00 nop + 80118b2: e006 b.n 80118c2 + break; + 80118b4: bf00 nop + 80118b6: e004 b.n 80118c2 + break; + 80118b8: bf00 nop + 80118ba: e002 b.n 80118c2 + break; + 80118bc: bf00 nop + 80118be: e000 b.n 80118c2 + break; + 80118c0: bf00 nop + } + } + return (frequency); + 80118c2: 6a3b ldr r3, [r7, #32] +} + 80118c4: 4618 mov r0, r3 + 80118c6: 3728 adds r7, #40 @ 0x28 + 80118c8: 46bd mov sp, r7 + 80118ca: bd80 pop {r7, pc} + 80118cc: 40021000 .word 0x40021000 + 80118d0: 08016c04 .word 0x08016c04 + 80118d4: 08016c14 .word 0x08016c14 + 80118d8: 017d7840 .word 0x017d7840 + 80118dc: 003d0900 .word 0x003d0900 + 80118e0: aaaaaaab .word 0xaaaaaaab + 80118e4: 0002faf0 .word 0x0002faf0 + +080118e8 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 80118e8: b580 push {r7, lr} + 80118ea: b084 sub sp, #16 + 80118ec: af00 add r7, sp, #0 + 80118ee: 6078 str r0, [r7, #4] + uint32_t prescaler = 0U; + 80118f0: 2300 movs r3, #0 + 80118f2: 60fb str r3, [r7, #12] + /* Check input parameters */ + if (hrtc == NULL) + 80118f4: 687b ldr r3, [r7, #4] + 80118f6: 2b00 cmp r3, #0 + 80118f8: d101 bne.n 80118fe + { + return HAL_ERROR; + 80118fa: 2301 movs r3, #1 + 80118fc: e07a b.n 80119f4 + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + 80118fe: 687b ldr r3, [r7, #4] + 8011900: 7c5b ldrb r3, [r3, #17] + 8011902: b2db uxtb r3, r3 + 8011904: 2b00 cmp r3, #0 + 8011906: d105 bne.n 8011914 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8011908: 687b ldr r3, [r7, #4] + 801190a: 2200 movs r2, #0 + 801190c: 741a strb r2, [r3, #16] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 801190e: 6878 ldr r0, [r7, #4] + 8011910: f7fb fc88 bl 800d224 + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 8011914: 687b ldr r3, [r7, #4] + 8011916: 2202 movs r2, #2 + 8011918: 745a strb r2, [r3, #17] + + /* Waiting for synchro */ + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 801191a: 6878 ldr r0, [r7, #4] + 801191c: f000 f870 bl 8011a00 + 8011920: 4603 mov r3, r0 + 8011922: 2b00 cmp r3, #0 + 8011924: d004 beq.n 8011930 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8011926: 687b ldr r3, [r7, #4] + 8011928: 2204 movs r2, #4 + 801192a: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 801192c: 2301 movs r3, #1 + 801192e: e061 b.n 80119f4 + } + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + 8011930: 6878 ldr r0, [r7, #4] + 8011932: f000 f892 bl 8011a5a + 8011936: 4603 mov r3, r0 + 8011938: 2b00 cmp r3, #0 + 801193a: d004 beq.n 8011946 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 801193c: 687b ldr r3, [r7, #4] + 801193e: 2204 movs r2, #4 + 8011940: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 8011942: 2301 movs r3, #1 + 8011944: e056 b.n 80119f4 + } + else + { + /* Clear Flags Bits */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); + 8011946: 687b ldr r3, [r7, #4] + 8011948: 681b ldr r3, [r3, #0] + 801194a: 685a ldr r2, [r3, #4] + 801194c: 687b ldr r3, [r7, #4] + 801194e: 681b ldr r3, [r3, #0] + 8011950: f022 0207 bic.w r2, r2, #7 + 8011954: 605a str r2, [r3, #4] + + if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) + 8011956: 687b ldr r3, [r7, #4] + 8011958: 689b ldr r3, [r3, #8] + 801195a: 2b00 cmp r3, #0 + 801195c: d005 beq.n 801196a + { + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + 801195e: 4b27 ldr r3, [pc, #156] @ (80119fc ) + 8011960: 6b1b ldr r3, [r3, #48] @ 0x30 + 8011962: 4a26 ldr r2, [pc, #152] @ (80119fc ) + 8011964: f023 0301 bic.w r3, r3, #1 + 8011968: 6313 str r3, [r2, #48] @ 0x30 + } + + /* Set the signal which will be routed to RTC Tamper pin*/ + MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); + 801196a: 4b24 ldr r3, [pc, #144] @ (80119fc ) + 801196c: 6adb ldr r3, [r3, #44] @ 0x2c + 801196e: f423 7260 bic.w r2, r3, #896 @ 0x380 + 8011972: 687b ldr r3, [r7, #4] + 8011974: 689b ldr r3, [r3, #8] + 8011976: 4921 ldr r1, [pc, #132] @ (80119fc ) + 8011978: 4313 orrs r3, r2 + 801197a: 62cb str r3, [r1, #44] @ 0x2c + + if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) + 801197c: 687b ldr r3, [r7, #4] + 801197e: 685b ldr r3, [r3, #4] + 8011980: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8011984: d003 beq.n 801198e + { + /* RTC Prescaler provided directly by end-user*/ + prescaler = hrtc->Init.AsynchPrediv; + 8011986: 687b ldr r3, [r7, #4] + 8011988: 685b ldr r3, [r3, #4] + 801198a: 60fb str r3, [r7, #12] + 801198c: e00e b.n 80119ac + } + else + { + /* RTC Prescaler will be automatically calculated to get 1 second timebase */ + /* Get the RTCCLK frequency */ + prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); + 801198e: 2001 movs r0, #1 + 8011990: f7ff fe58 bl 8011644 + 8011994: 60f8 str r0, [r7, #12] + + /* Check that RTC clock is enabled*/ + if (prescaler == 0U) + 8011996: 68fb ldr r3, [r7, #12] + 8011998: 2b00 cmp r3, #0 + 801199a: d104 bne.n 80119a6 + { + /* Should not happen. Frequency is not available*/ + hrtc->State = HAL_RTC_STATE_ERROR; + 801199c: 687b ldr r3, [r7, #4] + 801199e: 2204 movs r2, #4 + 80119a0: 745a strb r2, [r3, #17] + return HAL_ERROR; + 80119a2: 2301 movs r3, #1 + 80119a4: e026 b.n 80119f4 + } + else + { + /* RTC period = RTCCLK/(RTC_PR + 1) */ + prescaler = prescaler - 1U; + 80119a6: 68fb ldr r3, [r7, #12] + 80119a8: 3b01 subs r3, #1 + 80119aa: 60fb str r3, [r7, #12] + } + } + + /* Configure the RTC_PRLH / RTC_PRLL */ + WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); + 80119ac: 68fb ldr r3, [r7, #12] + 80119ae: 0c1a lsrs r2, r3, #16 + 80119b0: 687b ldr r3, [r7, #4] + 80119b2: 681b ldr r3, [r3, #0] + 80119b4: f002 020f and.w r2, r2, #15 + 80119b8: 609a str r2, [r3, #8] + WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); + 80119ba: 687b ldr r3, [r7, #4] + 80119bc: 681b ldr r3, [r3, #0] + 80119be: 68fa ldr r2, [r7, #12] + 80119c0: b292 uxth r2, r2 + 80119c2: 60da str r2, [r3, #12] + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + 80119c4: 6878 ldr r0, [r7, #4] + 80119c6: f000 f870 bl 8011aaa + 80119ca: 4603 mov r3, r0 + 80119cc: 2b00 cmp r3, #0 + 80119ce: d004 beq.n 80119da + { + hrtc->State = HAL_RTC_STATE_ERROR; + 80119d0: 687b ldr r3, [r7, #4] + 80119d2: 2204 movs r2, #4 + 80119d4: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 80119d6: 2301 movs r3, #1 + 80119d8: e00c b.n 80119f4 + } + + /* Initialize date to 1st of January 2000 */ + hrtc->DateToUpdate.Year = 0x00U; + 80119da: 687b ldr r3, [r7, #4] + 80119dc: 2200 movs r2, #0 + 80119de: 73da strb r2, [r3, #15] + hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; + 80119e0: 687b ldr r3, [r7, #4] + 80119e2: 2201 movs r2, #1 + 80119e4: 735a strb r2, [r3, #13] + hrtc->DateToUpdate.Date = 0x01U; + 80119e6: 687b ldr r3, [r7, #4] + 80119e8: 2201 movs r2, #1 + 80119ea: 739a strb r2, [r3, #14] + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80119ec: 687b ldr r3, [r7, #4] + 80119ee: 2201 movs r2, #1 + 80119f0: 745a strb r2, [r3, #17] + + return HAL_OK; + 80119f2: 2300 movs r3, #0 + } +} + 80119f4: 4618 mov r0, r3 + 80119f6: 3710 adds r7, #16 + 80119f8: 46bd mov sp, r7 + 80119fa: bd80 pop {r7, pc} + 80119fc: 40006c00 .word 0x40006c00 + +08011a00 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 8011a00: b580 push {r7, lr} + 8011a02: b084 sub sp, #16 + 8011a04: af00 add r7, sp, #0 + 8011a06: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8011a08: 2300 movs r3, #0 + 8011a0a: 60fb str r3, [r7, #12] + + /* Check input parameters */ + if (hrtc == NULL) + 8011a0c: 687b ldr r3, [r7, #4] + 8011a0e: 2b00 cmp r3, #0 + 8011a10: d101 bne.n 8011a16 + { + return HAL_ERROR; + 8011a12: 2301 movs r3, #1 + 8011a14: e01d b.n 8011a52 + } + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + 8011a16: 687b ldr r3, [r7, #4] + 8011a18: 681b ldr r3, [r3, #0] + 8011a1a: 685a ldr r2, [r3, #4] + 8011a1c: 687b ldr r3, [r7, #4] + 8011a1e: 681b ldr r3, [r3, #0] + 8011a20: f022 0208 bic.w r2, r2, #8 + 8011a24: 605a str r2, [r3, #4] + + tickstart = HAL_GetTick(); + 8011a26: f7fc fed3 bl 800e7d0 + 8011a2a: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + 8011a2c: e009 b.n 8011a42 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8011a2e: f7fc fecf bl 800e7d0 + 8011a32: 4602 mov r2, r0 + 8011a34: 68fb ldr r3, [r7, #12] + 8011a36: 1ad3 subs r3, r2, r3 + 8011a38: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8011a3c: d901 bls.n 8011a42 + { + return HAL_TIMEOUT; + 8011a3e: 2303 movs r3, #3 + 8011a40: e007 b.n 8011a52 + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + 8011a42: 687b ldr r3, [r7, #4] + 8011a44: 681b ldr r3, [r3, #0] + 8011a46: 685b ldr r3, [r3, #4] + 8011a48: f003 0308 and.w r3, r3, #8 + 8011a4c: 2b00 cmp r3, #0 + 8011a4e: d0ee beq.n 8011a2e + } + } + + return HAL_OK; + 8011a50: 2300 movs r3, #0 +} + 8011a52: 4618 mov r0, r3 + 8011a54: 3710 adds r7, #16 + 8011a56: 46bd mov sp, r7 + 8011a58: bd80 pop {r7, pc} + +08011a5a : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 8011a5a: b580 push {r7, lr} + 8011a5c: b084 sub sp, #16 + 8011a5e: af00 add r7, sp, #0 + 8011a60: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8011a62: 2300 movs r3, #0 + 8011a64: 60fb str r3, [r7, #12] + + tickstart = HAL_GetTick(); + 8011a66: f7fc feb3 bl 800e7d0 + 8011a6a: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 8011a6c: e009 b.n 8011a82 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8011a6e: f7fc feaf bl 800e7d0 + 8011a72: 4602 mov r2, r0 + 8011a74: 68fb ldr r3, [r7, #12] + 8011a76: 1ad3 subs r3, r2, r3 + 8011a78: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8011a7c: d901 bls.n 8011a82 + { + return HAL_TIMEOUT; + 8011a7e: 2303 movs r3, #3 + 8011a80: e00f b.n 8011aa2 + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 8011a82: 687b ldr r3, [r7, #4] + 8011a84: 681b ldr r3, [r3, #0] + 8011a86: 685b ldr r3, [r3, #4] + 8011a88: f003 0320 and.w r3, r3, #32 + 8011a8c: 2b00 cmp r3, #0 + 8011a8e: d0ee beq.n 8011a6e + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8011a90: 687b ldr r3, [r7, #4] + 8011a92: 681b ldr r3, [r3, #0] + 8011a94: 685a ldr r2, [r3, #4] + 8011a96: 687b ldr r3, [r7, #4] + 8011a98: 681b ldr r3, [r3, #0] + 8011a9a: f042 0210 orr.w r2, r2, #16 + 8011a9e: 605a str r2, [r3, #4] + + + return HAL_OK; + 8011aa0: 2300 movs r3, #0 +} + 8011aa2: 4618 mov r0, r3 + 8011aa4: 3710 adds r7, #16 + 8011aa6: 46bd mov sp, r7 + 8011aa8: bd80 pop {r7, pc} + +08011aaa : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 8011aaa: b580 push {r7, lr} + 8011aac: b084 sub sp, #16 + 8011aae: af00 add r7, sp, #0 + 8011ab0: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8011ab2: 2300 movs r3, #0 + 8011ab4: 60fb str r3, [r7, #12] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8011ab6: 687b ldr r3, [r7, #4] + 8011ab8: 681b ldr r3, [r3, #0] + 8011aba: 685a ldr r2, [r3, #4] + 8011abc: 687b ldr r3, [r7, #4] + 8011abe: 681b ldr r3, [r3, #0] + 8011ac0: f022 0210 bic.w r2, r2, #16 + 8011ac4: 605a str r2, [r3, #4] + + tickstart = HAL_GetTick(); + 8011ac6: f7fc fe83 bl 800e7d0 + 8011aca: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 8011acc: e009 b.n 8011ae2 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8011ace: f7fc fe7f bl 800e7d0 + 8011ad2: 4602 mov r2, r0 + 8011ad4: 68fb ldr r3, [r7, #12] + 8011ad6: 1ad3 subs r3, r2, r3 + 8011ad8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 + 8011adc: d901 bls.n 8011ae2 + { + return HAL_TIMEOUT; + 8011ade: 2303 movs r3, #3 + 8011ae0: e007 b.n 8011af2 + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 8011ae2: 687b ldr r3, [r7, #4] + 8011ae4: 681b ldr r3, [r3, #0] + 8011ae6: 685b ldr r3, [r3, #4] + 8011ae8: f003 0320 and.w r3, r3, #32 + 8011aec: 2b00 cmp r3, #0 + 8011aee: d0ee beq.n 8011ace + } + } + + return HAL_OK; + 8011af0: 2300 movs r3, #0 +} + 8011af2: 4618 mov r0, r3 + 8011af4: 3710 adds r7, #16 + 8011af6: 46bd mov sp, r7 + 8011af8: bd80 pop {r7, pc} + +08011afa : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 8011afa: b580 push {r7, lr} + 8011afc: b082 sub sp, #8 + 8011afe: af00 add r7, sp, #0 + 8011b00: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8011b02: 687b ldr r3, [r7, #4] + 8011b04: 2b00 cmp r3, #0 + 8011b06: d101 bne.n 8011b0c + { + return HAL_ERROR; + 8011b08: 2301 movs r3, #1 + 8011b0a: e041 b.n 8011b90 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8011b0c: 687b ldr r3, [r7, #4] + 8011b0e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8011b12: b2db uxtb r3, r3 + 8011b14: 2b00 cmp r3, #0 + 8011b16: d106 bne.n 8011b26 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8011b18: 687b ldr r3, [r7, #4] + 8011b1a: 2200 movs r2, #0 + 8011b1c: f883 203c strb.w r2, [r3, #60] @ 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8011b20: 6878 ldr r0, [r7, #4] + 8011b22: f7fc fb87 bl 800e234 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8011b26: 687b ldr r3, [r7, #4] + 8011b28: 2202 movs r2, #2 + 8011b2a: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8011b2e: 687b ldr r3, [r7, #4] + 8011b30: 681a ldr r2, [r3, #0] + 8011b32: 687b ldr r3, [r7, #4] + 8011b34: 3304 adds r3, #4 + 8011b36: 4619 mov r1, r3 + 8011b38: 4610 mov r0, r2 + 8011b3a: f000 fab9 bl 80120b0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8011b3e: 687b ldr r3, [r7, #4] + 8011b40: 2201 movs r2, #1 + 8011b42: f883 2046 strb.w r2, [r3, #70] @ 0x46 + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8011b46: 687b ldr r3, [r7, #4] + 8011b48: 2201 movs r2, #1 + 8011b4a: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8011b4e: 687b ldr r3, [r7, #4] + 8011b50: 2201 movs r2, #1 + 8011b52: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8011b56: 687b ldr r3, [r7, #4] + 8011b58: 2201 movs r2, #1 + 8011b5a: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8011b5e: 687b ldr r3, [r7, #4] + 8011b60: 2201 movs r2, #1 + 8011b62: f883 2041 strb.w r2, [r3, #65] @ 0x41 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8011b66: 687b ldr r3, [r7, #4] + 8011b68: 2201 movs r2, #1 + 8011b6a: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8011b6e: 687b ldr r3, [r7, #4] + 8011b70: 2201 movs r2, #1 + 8011b72: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8011b76: 687b ldr r3, [r7, #4] + 8011b78: 2201 movs r2, #1 + 8011b7a: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8011b7e: 687b ldr r3, [r7, #4] + 8011b80: 2201 movs r2, #1 + 8011b82: f883 2045 strb.w r2, [r3, #69] @ 0x45 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8011b86: 687b ldr r3, [r7, #4] + 8011b88: 2201 movs r2, #1 + 8011b8a: f883 203d strb.w r2, [r3, #61] @ 0x3d + + return HAL_OK; + 8011b8e: 2300 movs r3, #0 +} + 8011b90: 4618 mov r0, r3 + 8011b92: 3708 adds r7, #8 + 8011b94: 46bd mov sp, r7 + 8011b96: bd80 pop {r7, pc} + +08011b98 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8011b98: b580 push {r7, lr} + 8011b9a: b082 sub sp, #8 + 8011b9c: af00 add r7, sp, #0 + 8011b9e: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8011ba0: 687b ldr r3, [r7, #4] + 8011ba2: 2b00 cmp r3, #0 + 8011ba4: d101 bne.n 8011baa + { + return HAL_ERROR; + 8011ba6: 2301 movs r3, #1 + 8011ba8: e041 b.n 8011c2e + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8011baa: 687b ldr r3, [r7, #4] + 8011bac: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8011bb0: b2db uxtb r3, r3 + 8011bb2: 2b00 cmp r3, #0 + 8011bb4: d106 bne.n 8011bc4 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8011bb6: 687b ldr r3, [r7, #4] + 8011bb8: 2200 movs r2, #0 + 8011bba: f883 203c strb.w r2, [r3, #60] @ 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8011bbe: 6878 ldr r0, [r7, #4] + 8011bc0: f000 f839 bl 8011c36 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8011bc4: 687b ldr r3, [r7, #4] + 8011bc6: 2202 movs r2, #2 + 8011bc8: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8011bcc: 687b ldr r3, [r7, #4] + 8011bce: 681a ldr r2, [r3, #0] + 8011bd0: 687b ldr r3, [r7, #4] + 8011bd2: 3304 adds r3, #4 + 8011bd4: 4619 mov r1, r3 + 8011bd6: 4610 mov r0, r2 + 8011bd8: f000 fa6a bl 80120b0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8011bdc: 687b ldr r3, [r7, #4] + 8011bde: 2201 movs r2, #1 + 8011be0: f883 2046 strb.w r2, [r3, #70] @ 0x46 + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8011be4: 687b ldr r3, [r7, #4] + 8011be6: 2201 movs r2, #1 + 8011be8: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8011bec: 687b ldr r3, [r7, #4] + 8011bee: 2201 movs r2, #1 + 8011bf0: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8011bf4: 687b ldr r3, [r7, #4] + 8011bf6: 2201 movs r2, #1 + 8011bf8: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8011bfc: 687b ldr r3, [r7, #4] + 8011bfe: 2201 movs r2, #1 + 8011c00: f883 2041 strb.w r2, [r3, #65] @ 0x41 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8011c04: 687b ldr r3, [r7, #4] + 8011c06: 2201 movs r2, #1 + 8011c08: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8011c0c: 687b ldr r3, [r7, #4] + 8011c0e: 2201 movs r2, #1 + 8011c10: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8011c14: 687b ldr r3, [r7, #4] + 8011c16: 2201 movs r2, #1 + 8011c18: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8011c1c: 687b ldr r3, [r7, #4] + 8011c1e: 2201 movs r2, #1 + 8011c20: f883 2045 strb.w r2, [r3, #69] @ 0x45 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8011c24: 687b ldr r3, [r7, #4] + 8011c26: 2201 movs r2, #1 + 8011c28: f883 203d strb.w r2, [r3, #61] @ 0x3d + + return HAL_OK; + 8011c2c: 2300 movs r3, #0 +} + 8011c2e: 4618 mov r0, r3 + 8011c30: 3708 adds r7, #8 + 8011c32: 46bd mov sp, r7 + 8011c34: bd80 pop {r7, pc} + +08011c36 : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 8011c36: b480 push {r7} + 8011c38: b083 sub sp, #12 + 8011c3a: af00 add r7, sp, #0 + 8011c3c: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 8011c3e: bf00 nop + 8011c40: 370c adds r7, #12 + 8011c42: 46bd mov sp, r7 + 8011c44: bc80 pop {r7} + 8011c46: 4770 bx lr + +08011c48 : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8011c48: b580 push {r7, lr} + 8011c4a: b084 sub sp, #16 + 8011c4c: af00 add r7, sp, #0 + 8011c4e: 6078 str r0, [r7, #4] + 8011c50: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 8011c52: 683b ldr r3, [r7, #0] + 8011c54: 2b00 cmp r3, #0 + 8011c56: d109 bne.n 8011c6c + 8011c58: 687b ldr r3, [r7, #4] + 8011c5a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e + 8011c5e: b2db uxtb r3, r3 + 8011c60: 2b01 cmp r3, #1 + 8011c62: bf14 ite ne + 8011c64: 2301 movne r3, #1 + 8011c66: 2300 moveq r3, #0 + 8011c68: b2db uxtb r3, r3 + 8011c6a: e022 b.n 8011cb2 + 8011c6c: 683b ldr r3, [r7, #0] + 8011c6e: 2b04 cmp r3, #4 + 8011c70: d109 bne.n 8011c86 + 8011c72: 687b ldr r3, [r7, #4] + 8011c74: f893 303f ldrb.w r3, [r3, #63] @ 0x3f + 8011c78: b2db uxtb r3, r3 + 8011c7a: 2b01 cmp r3, #1 + 8011c7c: bf14 ite ne + 8011c7e: 2301 movne r3, #1 + 8011c80: 2300 moveq r3, #0 + 8011c82: b2db uxtb r3, r3 + 8011c84: e015 b.n 8011cb2 + 8011c86: 683b ldr r3, [r7, #0] + 8011c88: 2b08 cmp r3, #8 + 8011c8a: d109 bne.n 8011ca0 + 8011c8c: 687b ldr r3, [r7, #4] + 8011c8e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 8011c92: b2db uxtb r3, r3 + 8011c94: 2b01 cmp r3, #1 + 8011c96: bf14 ite ne + 8011c98: 2301 movne r3, #1 + 8011c9a: 2300 moveq r3, #0 + 8011c9c: b2db uxtb r3, r3 + 8011c9e: e008 b.n 8011cb2 + 8011ca0: 687b ldr r3, [r7, #4] + 8011ca2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8011ca6: b2db uxtb r3, r3 + 8011ca8: 2b01 cmp r3, #1 + 8011caa: bf14 ite ne + 8011cac: 2301 movne r3, #1 + 8011cae: 2300 moveq r3, #0 + 8011cb0: b2db uxtb r3, r3 + 8011cb2: 2b00 cmp r3, #0 + 8011cb4: d001 beq.n 8011cba + { + return HAL_ERROR; + 8011cb6: 2301 movs r3, #1 + 8011cb8: e063 b.n 8011d82 + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 8011cba: 683b ldr r3, [r7, #0] + 8011cbc: 2b00 cmp r3, #0 + 8011cbe: d104 bne.n 8011cca + 8011cc0: 687b ldr r3, [r7, #4] + 8011cc2: 2202 movs r2, #2 + 8011cc4: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8011cc8: e013 b.n 8011cf2 + 8011cca: 683b ldr r3, [r7, #0] + 8011ccc: 2b04 cmp r3, #4 + 8011cce: d104 bne.n 8011cda + 8011cd0: 687b ldr r3, [r7, #4] + 8011cd2: 2202 movs r2, #2 + 8011cd4: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8011cd8: e00b b.n 8011cf2 + 8011cda: 683b ldr r3, [r7, #0] + 8011cdc: 2b08 cmp r3, #8 + 8011cde: d104 bne.n 8011cea + 8011ce0: 687b ldr r3, [r7, #4] + 8011ce2: 2202 movs r2, #2 + 8011ce4: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8011ce8: e003 b.n 8011cf2 + 8011cea: 687b ldr r3, [r7, #4] + 8011cec: 2202 movs r2, #2 + 8011cee: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 8011cf2: 687b ldr r3, [r7, #4] + 8011cf4: 681b ldr r3, [r3, #0] + 8011cf6: 2201 movs r2, #1 + 8011cf8: 6839 ldr r1, [r7, #0] + 8011cfa: 4618 mov r0, r3 + 8011cfc: f000 fc6e bl 80125dc + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 8011d00: 687b ldr r3, [r7, #4] + 8011d02: 681b ldr r3, [r3, #0] + 8011d04: 4a21 ldr r2, [pc, #132] @ (8011d8c ) + 8011d06: 4293 cmp r3, r2 + 8011d08: d107 bne.n 8011d1a + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + 8011d0a: 687b ldr r3, [r7, #4] + 8011d0c: 681b ldr r3, [r3, #0] + 8011d0e: 6c5a ldr r2, [r3, #68] @ 0x44 + 8011d10: 687b ldr r3, [r7, #4] + 8011d12: 681b ldr r3, [r3, #0] + 8011d14: f442 4200 orr.w r2, r2, #32768 @ 0x8000 + 8011d18: 645a str r2, [r3, #68] @ 0x44 + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8011d1a: 687b ldr r3, [r7, #4] + 8011d1c: 681b ldr r3, [r3, #0] + 8011d1e: 4a1b ldr r2, [pc, #108] @ (8011d8c ) + 8011d20: 4293 cmp r3, r2 + 8011d22: d013 beq.n 8011d4c + 8011d24: 687b ldr r3, [r7, #4] + 8011d26: 681b ldr r3, [r3, #0] + 8011d28: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8011d2c: d00e beq.n 8011d4c + 8011d2e: 687b ldr r3, [r7, #4] + 8011d30: 681b ldr r3, [r3, #0] + 8011d32: 4a17 ldr r2, [pc, #92] @ (8011d90 ) + 8011d34: 4293 cmp r3, r2 + 8011d36: d009 beq.n 8011d4c + 8011d38: 687b ldr r3, [r7, #4] + 8011d3a: 681b ldr r3, [r3, #0] + 8011d3c: 4a15 ldr r2, [pc, #84] @ (8011d94 ) + 8011d3e: 4293 cmp r3, r2 + 8011d40: d004 beq.n 8011d4c + 8011d42: 687b ldr r3, [r7, #4] + 8011d44: 681b ldr r3, [r3, #0] + 8011d46: 4a14 ldr r2, [pc, #80] @ (8011d98 ) + 8011d48: 4293 cmp r3, r2 + 8011d4a: d111 bne.n 8011d70 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8011d4c: 687b ldr r3, [r7, #4] + 8011d4e: 681b ldr r3, [r3, #0] + 8011d50: 689b ldr r3, [r3, #8] + 8011d52: f003 0307 and.w r3, r3, #7 + 8011d56: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8011d58: 68fb ldr r3, [r7, #12] + 8011d5a: 2b06 cmp r3, #6 + 8011d5c: d010 beq.n 8011d80 + { + __HAL_TIM_ENABLE(htim); + 8011d5e: 687b ldr r3, [r7, #4] + 8011d60: 681b ldr r3, [r3, #0] + 8011d62: 681a ldr r2, [r3, #0] + 8011d64: 687b ldr r3, [r7, #4] + 8011d66: 681b ldr r3, [r3, #0] + 8011d68: f042 0201 orr.w r2, r2, #1 + 8011d6c: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8011d6e: e007 b.n 8011d80 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8011d70: 687b ldr r3, [r7, #4] + 8011d72: 681b ldr r3, [r3, #0] + 8011d74: 681a ldr r2, [r3, #0] + 8011d76: 687b ldr r3, [r7, #4] + 8011d78: 681b ldr r3, [r3, #0] + 8011d7a: f042 0201 orr.w r2, r2, #1 + 8011d7e: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8011d80: 2300 movs r3, #0 +} + 8011d82: 4618 mov r0, r3 + 8011d84: 3710 adds r7, #16 + 8011d86: 46bd mov sp, r7 + 8011d88: bd80 pop {r7, pc} + 8011d8a: bf00 nop + 8011d8c: 40012c00 .word 0x40012c00 + 8011d90: 40000400 .word 0x40000400 + 8011d94: 40000800 .word 0x40000800 + 8011d98: 40000c00 .word 0x40000c00 + +08011d9c : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8011d9c: b580 push {r7, lr} + 8011d9e: b086 sub sp, #24 + 8011da0: af00 add r7, sp, #0 + 8011da2: 60f8 str r0, [r7, #12] + 8011da4: 60b9 str r1, [r7, #8] + 8011da6: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8011da8: 2300 movs r3, #0 + 8011daa: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8011dac: 68fb ldr r3, [r7, #12] + 8011dae: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8011db2: 2b01 cmp r3, #1 + 8011db4: d101 bne.n 8011dba + 8011db6: 2302 movs r3, #2 + 8011db8: e0ae b.n 8011f18 + 8011dba: 68fb ldr r3, [r7, #12] + 8011dbc: 2201 movs r2, #1 + 8011dbe: f883 203c strb.w r2, [r3, #60] @ 0x3c + + switch (Channel) + 8011dc2: 687b ldr r3, [r7, #4] + 8011dc4: 2b0c cmp r3, #12 + 8011dc6: f200 809f bhi.w 8011f08 + 8011dca: a201 add r2, pc, #4 @ (adr r2, 8011dd0 ) + 8011dcc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8011dd0: 08011e05 .word 0x08011e05 + 8011dd4: 08011f09 .word 0x08011f09 + 8011dd8: 08011f09 .word 0x08011f09 + 8011ddc: 08011f09 .word 0x08011f09 + 8011de0: 08011e45 .word 0x08011e45 + 8011de4: 08011f09 .word 0x08011f09 + 8011de8: 08011f09 .word 0x08011f09 + 8011dec: 08011f09 .word 0x08011f09 + 8011df0: 08011e87 .word 0x08011e87 + 8011df4: 08011f09 .word 0x08011f09 + 8011df8: 08011f09 .word 0x08011f09 + 8011dfc: 08011f09 .word 0x08011f09 + 8011e00: 08011ec7 .word 0x08011ec7 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8011e04: 68fb ldr r3, [r7, #12] + 8011e06: 681b ldr r3, [r3, #0] + 8011e08: 68b9 ldr r1, [r7, #8] + 8011e0a: 4618 mov r0, r3 + 8011e0c: f000 f9c8 bl 80121a0 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8011e10: 68fb ldr r3, [r7, #12] + 8011e12: 681b ldr r3, [r3, #0] + 8011e14: 699a ldr r2, [r3, #24] + 8011e16: 68fb ldr r3, [r7, #12] + 8011e18: 681b ldr r3, [r3, #0] + 8011e1a: f042 0208 orr.w r2, r2, #8 + 8011e1e: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 8011e20: 68fb ldr r3, [r7, #12] + 8011e22: 681b ldr r3, [r3, #0] + 8011e24: 699a ldr r2, [r3, #24] + 8011e26: 68fb ldr r3, [r7, #12] + 8011e28: 681b ldr r3, [r3, #0] + 8011e2a: f022 0204 bic.w r2, r2, #4 + 8011e2e: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 8011e30: 68fb ldr r3, [r7, #12] + 8011e32: 681b ldr r3, [r3, #0] + 8011e34: 6999 ldr r1, [r3, #24] + 8011e36: 68bb ldr r3, [r7, #8] + 8011e38: 691a ldr r2, [r3, #16] + 8011e3a: 68fb ldr r3, [r7, #12] + 8011e3c: 681b ldr r3, [r3, #0] + 8011e3e: 430a orrs r2, r1 + 8011e40: 619a str r2, [r3, #24] + break; + 8011e42: e064 b.n 8011f0e + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8011e44: 68fb ldr r3, [r7, #12] + 8011e46: 681b ldr r3, [r3, #0] + 8011e48: 68b9 ldr r1, [r7, #8] + 8011e4a: 4618 mov r0, r3 + 8011e4c: f000 fa0e bl 801226c + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8011e50: 68fb ldr r3, [r7, #12] + 8011e52: 681b ldr r3, [r3, #0] + 8011e54: 699a ldr r2, [r3, #24] + 8011e56: 68fb ldr r3, [r7, #12] + 8011e58: 681b ldr r3, [r3, #0] + 8011e5a: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8011e5e: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8011e60: 68fb ldr r3, [r7, #12] + 8011e62: 681b ldr r3, [r3, #0] + 8011e64: 699a ldr r2, [r3, #24] + 8011e66: 68fb ldr r3, [r7, #12] + 8011e68: 681b ldr r3, [r3, #0] + 8011e6a: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8011e6e: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8011e70: 68fb ldr r3, [r7, #12] + 8011e72: 681b ldr r3, [r3, #0] + 8011e74: 6999 ldr r1, [r3, #24] + 8011e76: 68bb ldr r3, [r7, #8] + 8011e78: 691b ldr r3, [r3, #16] + 8011e7a: 021a lsls r2, r3, #8 + 8011e7c: 68fb ldr r3, [r7, #12] + 8011e7e: 681b ldr r3, [r3, #0] + 8011e80: 430a orrs r2, r1 + 8011e82: 619a str r2, [r3, #24] + break; + 8011e84: e043 b.n 8011f0e + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8011e86: 68fb ldr r3, [r7, #12] + 8011e88: 681b ldr r3, [r3, #0] + 8011e8a: 68b9 ldr r1, [r7, #8] + 8011e8c: 4618 mov r0, r3 + 8011e8e: f000 fa57 bl 8012340 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8011e92: 68fb ldr r3, [r7, #12] + 8011e94: 681b ldr r3, [r3, #0] + 8011e96: 69da ldr r2, [r3, #28] + 8011e98: 68fb ldr r3, [r7, #12] + 8011e9a: 681b ldr r3, [r3, #0] + 8011e9c: f042 0208 orr.w r2, r2, #8 + 8011ea0: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8011ea2: 68fb ldr r3, [r7, #12] + 8011ea4: 681b ldr r3, [r3, #0] + 8011ea6: 69da ldr r2, [r3, #28] + 8011ea8: 68fb ldr r3, [r7, #12] + 8011eaa: 681b ldr r3, [r3, #0] + 8011eac: f022 0204 bic.w r2, r2, #4 + 8011eb0: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8011eb2: 68fb ldr r3, [r7, #12] + 8011eb4: 681b ldr r3, [r3, #0] + 8011eb6: 69d9 ldr r1, [r3, #28] + 8011eb8: 68bb ldr r3, [r7, #8] + 8011eba: 691a ldr r2, [r3, #16] + 8011ebc: 68fb ldr r3, [r7, #12] + 8011ebe: 681b ldr r3, [r3, #0] + 8011ec0: 430a orrs r2, r1 + 8011ec2: 61da str r2, [r3, #28] + break; + 8011ec4: e023 b.n 8011f0e + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8011ec6: 68fb ldr r3, [r7, #12] + 8011ec8: 681b ldr r3, [r3, #0] + 8011eca: 68b9 ldr r1, [r7, #8] + 8011ecc: 4618 mov r0, r3 + 8011ece: f000 faa1 bl 8012414 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 8011ed2: 68fb ldr r3, [r7, #12] + 8011ed4: 681b ldr r3, [r3, #0] + 8011ed6: 69da ldr r2, [r3, #28] + 8011ed8: 68fb ldr r3, [r7, #12] + 8011eda: 681b ldr r3, [r3, #0] + 8011edc: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8011ee0: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 8011ee2: 68fb ldr r3, [r7, #12] + 8011ee4: 681b ldr r3, [r3, #0] + 8011ee6: 69da ldr r2, [r3, #28] + 8011ee8: 68fb ldr r3, [r7, #12] + 8011eea: 681b ldr r3, [r3, #0] + 8011eec: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8011ef0: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 8011ef2: 68fb ldr r3, [r7, #12] + 8011ef4: 681b ldr r3, [r3, #0] + 8011ef6: 69d9 ldr r1, [r3, #28] + 8011ef8: 68bb ldr r3, [r7, #8] + 8011efa: 691b ldr r3, [r3, #16] + 8011efc: 021a lsls r2, r3, #8 + 8011efe: 68fb ldr r3, [r7, #12] + 8011f00: 681b ldr r3, [r3, #0] + 8011f02: 430a orrs r2, r1 + 8011f04: 61da str r2, [r3, #28] + break; + 8011f06: e002 b.n 8011f0e + } + + default: + status = HAL_ERROR; + 8011f08: 2301 movs r3, #1 + 8011f0a: 75fb strb r3, [r7, #23] + break; + 8011f0c: bf00 nop + } + + __HAL_UNLOCK(htim); + 8011f0e: 68fb ldr r3, [r7, #12] + 8011f10: 2200 movs r2, #0 + 8011f12: f883 203c strb.w r2, [r3, #60] @ 0x3c + + return status; + 8011f16: 7dfb ldrb r3, [r7, #23] +} + 8011f18: 4618 mov r0, r3 + 8011f1a: 3718 adds r7, #24 + 8011f1c: 46bd mov sp, r7 + 8011f1e: bd80 pop {r7, pc} + +08011f20 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8011f20: b580 push {r7, lr} + 8011f22: b084 sub sp, #16 + 8011f24: af00 add r7, sp, #0 + 8011f26: 6078 str r0, [r7, #4] + 8011f28: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8011f2a: 2300 movs r3, #0 + 8011f2c: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 8011f2e: 687b ldr r3, [r7, #4] + 8011f30: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8011f34: 2b01 cmp r3, #1 + 8011f36: d101 bne.n 8011f3c + 8011f38: 2302 movs r3, #2 + 8011f3a: e0b4 b.n 80120a6 + 8011f3c: 687b ldr r3, [r7, #4] + 8011f3e: 2201 movs r2, #1 + 8011f40: f883 203c strb.w r2, [r3, #60] @ 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8011f44: 687b ldr r3, [r7, #4] + 8011f46: 2202 movs r2, #2 + 8011f48: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8011f4c: 687b ldr r3, [r7, #4] + 8011f4e: 681b ldr r3, [r3, #0] + 8011f50: 689b ldr r3, [r3, #8] + 8011f52: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8011f54: 68bb ldr r3, [r7, #8] + 8011f56: f023 0377 bic.w r3, r3, #119 @ 0x77 + 8011f5a: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8011f5c: 68bb ldr r3, [r7, #8] + 8011f5e: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8011f62: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 8011f64: 687b ldr r3, [r7, #4] + 8011f66: 681b ldr r3, [r3, #0] + 8011f68: 68ba ldr r2, [r7, #8] + 8011f6a: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8011f6c: 683b ldr r3, [r7, #0] + 8011f6e: 681b ldr r3, [r3, #0] + 8011f70: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8011f74: d03e beq.n 8011ff4 + 8011f76: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8011f7a: f200 8087 bhi.w 801208c + 8011f7e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8011f82: f000 8086 beq.w 8012092 + 8011f86: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8011f8a: d87f bhi.n 801208c + 8011f8c: 2b70 cmp r3, #112 @ 0x70 + 8011f8e: d01a beq.n 8011fc6 + 8011f90: 2b70 cmp r3, #112 @ 0x70 + 8011f92: d87b bhi.n 801208c + 8011f94: 2b60 cmp r3, #96 @ 0x60 + 8011f96: d050 beq.n 801203a + 8011f98: 2b60 cmp r3, #96 @ 0x60 + 8011f9a: d877 bhi.n 801208c + 8011f9c: 2b50 cmp r3, #80 @ 0x50 + 8011f9e: d03c beq.n 801201a + 8011fa0: 2b50 cmp r3, #80 @ 0x50 + 8011fa2: d873 bhi.n 801208c + 8011fa4: 2b40 cmp r3, #64 @ 0x40 + 8011fa6: d058 beq.n 801205a + 8011fa8: 2b40 cmp r3, #64 @ 0x40 + 8011faa: d86f bhi.n 801208c + 8011fac: 2b30 cmp r3, #48 @ 0x30 + 8011fae: d064 beq.n 801207a + 8011fb0: 2b30 cmp r3, #48 @ 0x30 + 8011fb2: d86b bhi.n 801208c + 8011fb4: 2b20 cmp r3, #32 + 8011fb6: d060 beq.n 801207a + 8011fb8: 2b20 cmp r3, #32 + 8011fba: d867 bhi.n 801208c + 8011fbc: 2b00 cmp r3, #0 + 8011fbe: d05c beq.n 801207a + 8011fc0: 2b10 cmp r3, #16 + 8011fc2: d05a beq.n 801207a + 8011fc4: e062 b.n 801208c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8011fc6: 687b ldr r3, [r7, #4] + 8011fc8: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8011fca: 683b ldr r3, [r7, #0] + 8011fcc: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8011fce: 683b ldr r3, [r7, #0] + 8011fd0: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8011fd2: 683b ldr r3, [r7, #0] + 8011fd4: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8011fd6: f000 fae2 bl 801259e + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 8011fda: 687b ldr r3, [r7, #4] + 8011fdc: 681b ldr r3, [r3, #0] + 8011fde: 689b ldr r3, [r3, #8] + 8011fe0: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8011fe2: 68bb ldr r3, [r7, #8] + 8011fe4: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8011fe8: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8011fea: 687b ldr r3, [r7, #4] + 8011fec: 681b ldr r3, [r3, #0] + 8011fee: 68ba ldr r2, [r7, #8] + 8011ff0: 609a str r2, [r3, #8] + break; + 8011ff2: e04f b.n 8012094 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8011ff4: 687b ldr r3, [r7, #4] + 8011ff6: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8011ff8: 683b ldr r3, [r7, #0] + 8011ffa: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8011ffc: 683b ldr r3, [r7, #0] + 8011ffe: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8012000: 683b ldr r3, [r7, #0] + 8012002: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8012004: f000 facb bl 801259e + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8012008: 687b ldr r3, [r7, #4] + 801200a: 681b ldr r3, [r3, #0] + 801200c: 689a ldr r2, [r3, #8] + 801200e: 687b ldr r3, [r7, #4] + 8012010: 681b ldr r3, [r3, #0] + 8012012: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8012016: 609a str r2, [r3, #8] + break; + 8012018: e03c b.n 8012094 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 801201a: 687b ldr r3, [r7, #4] + 801201c: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 801201e: 683b ldr r3, [r7, #0] + 8012020: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8012022: 683b ldr r3, [r7, #0] + 8012024: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8012026: 461a mov r2, r3 + 8012028: f000 fa42 bl 80124b0 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 801202c: 687b ldr r3, [r7, #4] + 801202e: 681b ldr r3, [r3, #0] + 8012030: 2150 movs r1, #80 @ 0x50 + 8012032: 4618 mov r0, r3 + 8012034: f000 fa99 bl 801256a + break; + 8012038: e02c b.n 8012094 + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 801203a: 687b ldr r3, [r7, #4] + 801203c: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 801203e: 683b ldr r3, [r7, #0] + 8012040: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8012042: 683b ldr r3, [r7, #0] + 8012044: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 8012046: 461a mov r2, r3 + 8012048: f000 fa60 bl 801250c + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 801204c: 687b ldr r3, [r7, #4] + 801204e: 681b ldr r3, [r3, #0] + 8012050: 2160 movs r1, #96 @ 0x60 + 8012052: 4618 mov r0, r3 + 8012054: f000 fa89 bl 801256a + break; + 8012058: e01c b.n 8012094 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 801205a: 687b ldr r3, [r7, #4] + 801205c: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 801205e: 683b ldr r3, [r7, #0] + 8012060: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8012062: 683b ldr r3, [r7, #0] + 8012064: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8012066: 461a mov r2, r3 + 8012068: f000 fa22 bl 80124b0 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 801206c: 687b ldr r3, [r7, #4] + 801206e: 681b ldr r3, [r3, #0] + 8012070: 2140 movs r1, #64 @ 0x40 + 8012072: 4618 mov r0, r3 + 8012074: f000 fa79 bl 801256a + break; + 8012078: e00c b.n 8012094 + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 801207a: 687b ldr r3, [r7, #4] + 801207c: 681a ldr r2, [r3, #0] + 801207e: 683b ldr r3, [r7, #0] + 8012080: 681b ldr r3, [r3, #0] + 8012082: 4619 mov r1, r3 + 8012084: 4610 mov r0, r2 + 8012086: f000 fa70 bl 801256a + break; + 801208a: e003 b.n 8012094 + } + + default: + status = HAL_ERROR; + 801208c: 2301 movs r3, #1 + 801208e: 73fb strb r3, [r7, #15] + break; + 8012090: e000 b.n 8012094 + break; + 8012092: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8012094: 687b ldr r3, [r7, #4] + 8012096: 2201 movs r2, #1 + 8012098: f883 203d strb.w r2, [r3, #61] @ 0x3d + + __HAL_UNLOCK(htim); + 801209c: 687b ldr r3, [r7, #4] + 801209e: 2200 movs r2, #0 + 80120a0: f883 203c strb.w r2, [r3, #60] @ 0x3c + + return status; + 80120a4: 7bfb ldrb r3, [r7, #15] +} + 80120a6: 4618 mov r0, r3 + 80120a8: 3710 adds r7, #16 + 80120aa: 46bd mov sp, r7 + 80120ac: bd80 pop {r7, pc} + ... + +080120b0 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 80120b0: b480 push {r7} + 80120b2: b085 sub sp, #20 + 80120b4: af00 add r7, sp, #0 + 80120b6: 6078 str r0, [r7, #4] + 80120b8: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 80120ba: 687b ldr r3, [r7, #4] + 80120bc: 681b ldr r3, [r3, #0] + 80120be: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 80120c0: 687b ldr r3, [r7, #4] + 80120c2: 4a33 ldr r2, [pc, #204] @ (8012190 ) + 80120c4: 4293 cmp r3, r2 + 80120c6: d00f beq.n 80120e8 + 80120c8: 687b ldr r3, [r7, #4] + 80120ca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80120ce: d00b beq.n 80120e8 + 80120d0: 687b ldr r3, [r7, #4] + 80120d2: 4a30 ldr r2, [pc, #192] @ (8012194 ) + 80120d4: 4293 cmp r3, r2 + 80120d6: d007 beq.n 80120e8 + 80120d8: 687b ldr r3, [r7, #4] + 80120da: 4a2f ldr r2, [pc, #188] @ (8012198 ) + 80120dc: 4293 cmp r3, r2 + 80120de: d003 beq.n 80120e8 + 80120e0: 687b ldr r3, [r7, #4] + 80120e2: 4a2e ldr r2, [pc, #184] @ (801219c ) + 80120e4: 4293 cmp r3, r2 + 80120e6: d108 bne.n 80120fa + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 80120e8: 68fb ldr r3, [r7, #12] + 80120ea: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80120ee: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 80120f0: 683b ldr r3, [r7, #0] + 80120f2: 685b ldr r3, [r3, #4] + 80120f4: 68fa ldr r2, [r7, #12] + 80120f6: 4313 orrs r3, r2 + 80120f8: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 80120fa: 687b ldr r3, [r7, #4] + 80120fc: 4a24 ldr r2, [pc, #144] @ (8012190 ) + 80120fe: 4293 cmp r3, r2 + 8012100: d00f beq.n 8012122 + 8012102: 687b ldr r3, [r7, #4] + 8012104: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8012108: d00b beq.n 8012122 + 801210a: 687b ldr r3, [r7, #4] + 801210c: 4a21 ldr r2, [pc, #132] @ (8012194 ) + 801210e: 4293 cmp r3, r2 + 8012110: d007 beq.n 8012122 + 8012112: 687b ldr r3, [r7, #4] + 8012114: 4a20 ldr r2, [pc, #128] @ (8012198 ) + 8012116: 4293 cmp r3, r2 + 8012118: d003 beq.n 8012122 + 801211a: 687b ldr r3, [r7, #4] + 801211c: 4a1f ldr r2, [pc, #124] @ (801219c ) + 801211e: 4293 cmp r3, r2 + 8012120: d108 bne.n 8012134 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8012122: 68fb ldr r3, [r7, #12] + 8012124: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8012128: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 801212a: 683b ldr r3, [r7, #0] + 801212c: 68db ldr r3, [r3, #12] + 801212e: 68fa ldr r2, [r7, #12] + 8012130: 4313 orrs r3, r2 + 8012132: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8012134: 68fb ldr r3, [r7, #12] + 8012136: f023 0280 bic.w r2, r3, #128 @ 0x80 + 801213a: 683b ldr r3, [r7, #0] + 801213c: 695b ldr r3, [r3, #20] + 801213e: 4313 orrs r3, r2 + 8012140: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 8012142: 687b ldr r3, [r7, #4] + 8012144: 68fa ldr r2, [r7, #12] + 8012146: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8012148: 683b ldr r3, [r7, #0] + 801214a: 689a ldr r2, [r3, #8] + 801214c: 687b ldr r3, [r7, #4] + 801214e: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8012150: 683b ldr r3, [r7, #0] + 8012152: 681a ldr r2, [r3, #0] + 8012154: 687b ldr r3, [r7, #4] + 8012156: 629a str r2, [r3, #40] @ 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8012158: 687b ldr r3, [r7, #4] + 801215a: 4a0d ldr r2, [pc, #52] @ (8012190 ) + 801215c: 4293 cmp r3, r2 + 801215e: d103 bne.n 8012168 + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8012160: 683b ldr r3, [r7, #0] + 8012162: 691a ldr r2, [r3, #16] + 8012164: 687b ldr r3, [r7, #4] + 8012166: 631a str r2, [r3, #48] @ 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8012168: 687b ldr r3, [r7, #4] + 801216a: 2201 movs r2, #1 + 801216c: 615a str r2, [r3, #20] + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + 801216e: 687b ldr r3, [r7, #4] + 8012170: 691b ldr r3, [r3, #16] + 8012172: f003 0301 and.w r3, r3, #1 + 8012176: 2b00 cmp r3, #0 + 8012178: d005 beq.n 8012186 + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + 801217a: 687b ldr r3, [r7, #4] + 801217c: 691b ldr r3, [r3, #16] + 801217e: f023 0201 bic.w r2, r3, #1 + 8012182: 687b ldr r3, [r7, #4] + 8012184: 611a str r2, [r3, #16] + } +} + 8012186: bf00 nop + 8012188: 3714 adds r7, #20 + 801218a: 46bd mov sp, r7 + 801218c: bc80 pop {r7} + 801218e: 4770 bx lr + 8012190: 40012c00 .word 0x40012c00 + 8012194: 40000400 .word 0x40000400 + 8012198: 40000800 .word 0x40000800 + 801219c: 40000c00 .word 0x40000c00 + +080121a0 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 80121a0: b480 push {r7} + 80121a2: b087 sub sp, #28 + 80121a4: af00 add r7, sp, #0 + 80121a6: 6078 str r0, [r7, #4] + 80121a8: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80121aa: 687b ldr r3, [r7, #4] + 80121ac: 6a1b ldr r3, [r3, #32] + 80121ae: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 80121b0: 687b ldr r3, [r7, #4] + 80121b2: 6a1b ldr r3, [r3, #32] + 80121b4: f023 0201 bic.w r2, r3, #1 + 80121b8: 687b ldr r3, [r7, #4] + 80121ba: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80121bc: 687b ldr r3, [r7, #4] + 80121be: 685b ldr r3, [r3, #4] + 80121c0: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 80121c2: 687b ldr r3, [r7, #4] + 80121c4: 699b ldr r3, [r3, #24] + 80121c6: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 80121c8: 68fb ldr r3, [r7, #12] + 80121ca: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80121ce: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 80121d0: 68fb ldr r3, [r7, #12] + 80121d2: f023 0303 bic.w r3, r3, #3 + 80121d6: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80121d8: 683b ldr r3, [r7, #0] + 80121da: 681b ldr r3, [r3, #0] + 80121dc: 68fa ldr r2, [r7, #12] + 80121de: 4313 orrs r3, r2 + 80121e0: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 80121e2: 697b ldr r3, [r7, #20] + 80121e4: f023 0302 bic.w r3, r3, #2 + 80121e8: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 80121ea: 683b ldr r3, [r7, #0] + 80121ec: 689b ldr r3, [r3, #8] + 80121ee: 697a ldr r2, [r7, #20] + 80121f0: 4313 orrs r3, r2 + 80121f2: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 80121f4: 687b ldr r3, [r7, #4] + 80121f6: 4a1c ldr r2, [pc, #112] @ (8012268 ) + 80121f8: 4293 cmp r3, r2 + 80121fa: d10c bne.n 8012216 + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + 80121fc: 697b ldr r3, [r7, #20] + 80121fe: f023 0308 bic.w r3, r3, #8 + 8012202: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + 8012204: 683b ldr r3, [r7, #0] + 8012206: 68db ldr r3, [r3, #12] + 8012208: 697a ldr r2, [r7, #20] + 801220a: 4313 orrs r3, r2 + 801220c: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + 801220e: 697b ldr r3, [r7, #20] + 8012210: f023 0304 bic.w r3, r3, #4 + 8012214: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8012216: 687b ldr r3, [r7, #4] + 8012218: 4a13 ldr r2, [pc, #76] @ (8012268 ) + 801221a: 4293 cmp r3, r2 + 801221c: d111 bne.n 8012242 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + 801221e: 693b ldr r3, [r7, #16] + 8012220: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8012224: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS1N; + 8012226: 693b ldr r3, [r7, #16] + 8012228: f423 7300 bic.w r3, r3, #512 @ 0x200 + 801222c: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + 801222e: 683b ldr r3, [r7, #0] + 8012230: 695b ldr r3, [r3, #20] + 8012232: 693a ldr r2, [r7, #16] + 8012234: 4313 orrs r3, r2 + 8012236: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + 8012238: 683b ldr r3, [r7, #0] + 801223a: 699b ldr r3, [r3, #24] + 801223c: 693a ldr r2, [r7, #16] + 801223e: 4313 orrs r3, r2 + 8012240: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8012242: 687b ldr r3, [r7, #4] + 8012244: 693a ldr r2, [r7, #16] + 8012246: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8012248: 687b ldr r3, [r7, #4] + 801224a: 68fa ldr r2, [r7, #12] + 801224c: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 801224e: 683b ldr r3, [r7, #0] + 8012250: 685a ldr r2, [r3, #4] + 8012252: 687b ldr r3, [r7, #4] + 8012254: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8012256: 687b ldr r3, [r7, #4] + 8012258: 697a ldr r2, [r7, #20] + 801225a: 621a str r2, [r3, #32] +} + 801225c: bf00 nop + 801225e: 371c adds r7, #28 + 8012260: 46bd mov sp, r7 + 8012262: bc80 pop {r7} + 8012264: 4770 bx lr + 8012266: bf00 nop + 8012268: 40012c00 .word 0x40012c00 + +0801226c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 801226c: b480 push {r7} + 801226e: b087 sub sp, #28 + 8012270: af00 add r7, sp, #0 + 8012272: 6078 str r0, [r7, #4] + 8012274: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8012276: 687b ldr r3, [r7, #4] + 8012278: 6a1b ldr r3, [r3, #32] + 801227a: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 801227c: 687b ldr r3, [r7, #4] + 801227e: 6a1b ldr r3, [r3, #32] + 8012280: f023 0210 bic.w r2, r3, #16 + 8012284: 687b ldr r3, [r7, #4] + 8012286: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8012288: 687b ldr r3, [r7, #4] + 801228a: 685b ldr r3, [r3, #4] + 801228c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 801228e: 687b ldr r3, [r7, #4] + 8012290: 699b ldr r3, [r3, #24] + 8012292: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8012294: 68fb ldr r3, [r7, #12] + 8012296: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 801229a: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 801229c: 68fb ldr r3, [r7, #12] + 801229e: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80122a2: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80122a4: 683b ldr r3, [r7, #0] + 80122a6: 681b ldr r3, [r3, #0] + 80122a8: 021b lsls r3, r3, #8 + 80122aa: 68fa ldr r2, [r7, #12] + 80122ac: 4313 orrs r3, r2 + 80122ae: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 80122b0: 697b ldr r3, [r7, #20] + 80122b2: f023 0320 bic.w r3, r3, #32 + 80122b6: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 80122b8: 683b ldr r3, [r7, #0] + 80122ba: 689b ldr r3, [r3, #8] + 80122bc: 011b lsls r3, r3, #4 + 80122be: 697a ldr r2, [r7, #20] + 80122c0: 4313 orrs r3, r2 + 80122c2: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 80122c4: 687b ldr r3, [r7, #4] + 80122c6: 4a1d ldr r2, [pc, #116] @ (801233c ) + 80122c8: 4293 cmp r3, r2 + 80122ca: d10d bne.n 80122e8 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + 80122cc: 697b ldr r3, [r7, #20] + 80122ce: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80122d2: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + 80122d4: 683b ldr r3, [r7, #0] + 80122d6: 68db ldr r3, [r3, #12] + 80122d8: 011b lsls r3, r3, #4 + 80122da: 697a ldr r2, [r7, #20] + 80122dc: 4313 orrs r3, r2 + 80122de: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + 80122e0: 697b ldr r3, [r7, #20] + 80122e2: f023 0340 bic.w r3, r3, #64 @ 0x40 + 80122e6: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80122e8: 687b ldr r3, [r7, #4] + 80122ea: 4a14 ldr r2, [pc, #80] @ (801233c ) + 80122ec: 4293 cmp r3, r2 + 80122ee: d113 bne.n 8012318 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + 80122f0: 693b ldr r3, [r7, #16] + 80122f2: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 80122f6: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS2N; + 80122f8: 693b ldr r3, [r7, #16] + 80122fa: f423 6300 bic.w r3, r3, #2048 @ 0x800 + 80122fe: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + 8012300: 683b ldr r3, [r7, #0] + 8012302: 695b ldr r3, [r3, #20] + 8012304: 009b lsls r3, r3, #2 + 8012306: 693a ldr r2, [r7, #16] + 8012308: 4313 orrs r3, r2 + 801230a: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 801230c: 683b ldr r3, [r7, #0] + 801230e: 699b ldr r3, [r3, #24] + 8012310: 009b lsls r3, r3, #2 + 8012312: 693a ldr r2, [r7, #16] + 8012314: 4313 orrs r3, r2 + 8012316: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8012318: 687b ldr r3, [r7, #4] + 801231a: 693a ldr r2, [r7, #16] + 801231c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 801231e: 687b ldr r3, [r7, #4] + 8012320: 68fa ldr r2, [r7, #12] + 8012322: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8012324: 683b ldr r3, [r7, #0] + 8012326: 685a ldr r2, [r3, #4] + 8012328: 687b ldr r3, [r7, #4] + 801232a: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 801232c: 687b ldr r3, [r7, #4] + 801232e: 697a ldr r2, [r7, #20] + 8012330: 621a str r2, [r3, #32] +} + 8012332: bf00 nop + 8012334: 371c adds r7, #28 + 8012336: 46bd mov sp, r7 + 8012338: bc80 pop {r7} + 801233a: 4770 bx lr + 801233c: 40012c00 .word 0x40012c00 + +08012340 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8012340: b480 push {r7} + 8012342: b087 sub sp, #28 + 8012344: af00 add r7, sp, #0 + 8012346: 6078 str r0, [r7, #4] + 8012348: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 801234a: 687b ldr r3, [r7, #4] + 801234c: 6a1b ldr r3, [r3, #32] + 801234e: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8012350: 687b ldr r3, [r7, #4] + 8012352: 6a1b ldr r3, [r3, #32] + 8012354: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8012358: 687b ldr r3, [r7, #4] + 801235a: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 801235c: 687b ldr r3, [r7, #4] + 801235e: 685b ldr r3, [r3, #4] + 8012360: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8012362: 687b ldr r3, [r7, #4] + 8012364: 69db ldr r3, [r3, #28] + 8012366: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8012368: 68fb ldr r3, [r7, #12] + 801236a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 801236e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8012370: 68fb ldr r3, [r7, #12] + 8012372: f023 0303 bic.w r3, r3, #3 + 8012376: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8012378: 683b ldr r3, [r7, #0] + 801237a: 681b ldr r3, [r3, #0] + 801237c: 68fa ldr r2, [r7, #12] + 801237e: 4313 orrs r3, r2 + 8012380: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8012382: 697b ldr r3, [r7, #20] + 8012384: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8012388: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 801238a: 683b ldr r3, [r7, #0] + 801238c: 689b ldr r3, [r3, #8] + 801238e: 021b lsls r3, r3, #8 + 8012390: 697a ldr r2, [r7, #20] + 8012392: 4313 orrs r3, r2 + 8012394: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 8012396: 687b ldr r3, [r7, #4] + 8012398: 4a1d ldr r2, [pc, #116] @ (8012410 ) + 801239a: 4293 cmp r3, r2 + 801239c: d10d bne.n 80123ba + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + 801239e: 697b ldr r3, [r7, #20] + 80123a0: f423 6300 bic.w r3, r3, #2048 @ 0x800 + 80123a4: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + 80123a6: 683b ldr r3, [r7, #0] + 80123a8: 68db ldr r3, [r3, #12] + 80123aa: 021b lsls r3, r3, #8 + 80123ac: 697a ldr r2, [r7, #20] + 80123ae: 4313 orrs r3, r2 + 80123b0: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + 80123b2: 697b ldr r3, [r7, #20] + 80123b4: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 80123b8: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80123ba: 687b ldr r3, [r7, #4] + 80123bc: 4a14 ldr r2, [pc, #80] @ (8012410 ) + 80123be: 4293 cmp r3, r2 + 80123c0: d113 bne.n 80123ea + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + 80123c2: 693b ldr r3, [r7, #16] + 80123c4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 + 80123c8: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS3N; + 80123ca: 693b ldr r3, [r7, #16] + 80123cc: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 80123d0: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + 80123d2: 683b ldr r3, [r7, #0] + 80123d4: 695b ldr r3, [r3, #20] + 80123d6: 011b lsls r3, r3, #4 + 80123d8: 693a ldr r2, [r7, #16] + 80123da: 4313 orrs r3, r2 + 80123dc: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 80123de: 683b ldr r3, [r7, #0] + 80123e0: 699b ldr r3, [r3, #24] + 80123e2: 011b lsls r3, r3, #4 + 80123e4: 693a ldr r2, [r7, #16] + 80123e6: 4313 orrs r3, r2 + 80123e8: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80123ea: 687b ldr r3, [r7, #4] + 80123ec: 693a ldr r2, [r7, #16] + 80123ee: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80123f0: 687b ldr r3, [r7, #4] + 80123f2: 68fa ldr r2, [r7, #12] + 80123f4: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 80123f6: 683b ldr r3, [r7, #0] + 80123f8: 685a ldr r2, [r3, #4] + 80123fa: 687b ldr r3, [r7, #4] + 80123fc: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80123fe: 687b ldr r3, [r7, #4] + 8012400: 697a ldr r2, [r7, #20] + 8012402: 621a str r2, [r3, #32] +} + 8012404: bf00 nop + 8012406: 371c adds r7, #28 + 8012408: 46bd mov sp, r7 + 801240a: bc80 pop {r7} + 801240c: 4770 bx lr + 801240e: bf00 nop + 8012410: 40012c00 .word 0x40012c00 + +08012414 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8012414: b480 push {r7} + 8012416: b087 sub sp, #28 + 8012418: af00 add r7, sp, #0 + 801241a: 6078 str r0, [r7, #4] + 801241c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 801241e: 687b ldr r3, [r7, #4] + 8012420: 6a1b ldr r3, [r3, #32] + 8012422: 613b str r3, [r7, #16] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8012424: 687b ldr r3, [r7, #4] + 8012426: 6a1b ldr r3, [r3, #32] + 8012428: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 801242c: 687b ldr r3, [r7, #4] + 801242e: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8012430: 687b ldr r3, [r7, #4] + 8012432: 685b ldr r3, [r3, #4] + 8012434: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8012436: 687b ldr r3, [r7, #4] + 8012438: 69db ldr r3, [r3, #28] + 801243a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 801243c: 68fb ldr r3, [r7, #12] + 801243e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8012442: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8012444: 68fb ldr r3, [r7, #12] + 8012446: f423 7340 bic.w r3, r3, #768 @ 0x300 + 801244a: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 801244c: 683b ldr r3, [r7, #0] + 801244e: 681b ldr r3, [r3, #0] + 8012450: 021b lsls r3, r3, #8 + 8012452: 68fa ldr r2, [r7, #12] + 8012454: 4313 orrs r3, r2 + 8012456: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8012458: 693b ldr r3, [r7, #16] + 801245a: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 801245e: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8012460: 683b ldr r3, [r7, #0] + 8012462: 689b ldr r3, [r3, #8] + 8012464: 031b lsls r3, r3, #12 + 8012466: 693a ldr r2, [r7, #16] + 8012468: 4313 orrs r3, r2 + 801246a: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 801246c: 687b ldr r3, [r7, #4] + 801246e: 4a0f ldr r2, [pc, #60] @ (80124ac ) + 8012470: 4293 cmp r3, r2 + 8012472: d109 bne.n 8012488 + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + 8012474: 697b ldr r3, [r7, #20] + 8012476: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 801247a: 617b str r3, [r7, #20] + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + 801247c: 683b ldr r3, [r7, #0] + 801247e: 695b ldr r3, [r3, #20] + 8012480: 019b lsls r3, r3, #6 + 8012482: 697a ldr r2, [r7, #20] + 8012484: 4313 orrs r3, r2 + 8012486: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8012488: 687b ldr r3, [r7, #4] + 801248a: 697a ldr r2, [r7, #20] + 801248c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 801248e: 687b ldr r3, [r7, #4] + 8012490: 68fa ldr r2, [r7, #12] + 8012492: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8012494: 683b ldr r3, [r7, #0] + 8012496: 685a ldr r2, [r3, #4] + 8012498: 687b ldr r3, [r7, #4] + 801249a: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 801249c: 687b ldr r3, [r7, #4] + 801249e: 693a ldr r2, [r7, #16] + 80124a0: 621a str r2, [r3, #32] +} + 80124a2: bf00 nop + 80124a4: 371c adds r7, #28 + 80124a6: 46bd mov sp, r7 + 80124a8: bc80 pop {r7} + 80124aa: 4770 bx lr + 80124ac: 40012c00 .word 0x40012c00 + +080124b0 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 80124b0: b480 push {r7} + 80124b2: b087 sub sp, #28 + 80124b4: af00 add r7, sp, #0 + 80124b6: 60f8 str r0, [r7, #12] + 80124b8: 60b9 str r1, [r7, #8] + 80124ba: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 80124bc: 68fb ldr r3, [r7, #12] + 80124be: 6a1b ldr r3, [r3, #32] + 80124c0: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 80124c2: 68fb ldr r3, [r7, #12] + 80124c4: 6a1b ldr r3, [r3, #32] + 80124c6: f023 0201 bic.w r2, r3, #1 + 80124ca: 68fb ldr r3, [r7, #12] + 80124cc: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 80124ce: 68fb ldr r3, [r7, #12] + 80124d0: 699b ldr r3, [r3, #24] + 80124d2: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 80124d4: 693b ldr r3, [r7, #16] + 80124d6: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 80124da: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 80124dc: 687b ldr r3, [r7, #4] + 80124de: 011b lsls r3, r3, #4 + 80124e0: 693a ldr r2, [r7, #16] + 80124e2: 4313 orrs r3, r2 + 80124e4: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 80124e6: 697b ldr r3, [r7, #20] + 80124e8: f023 030a bic.w r3, r3, #10 + 80124ec: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 80124ee: 697a ldr r2, [r7, #20] + 80124f0: 68bb ldr r3, [r7, #8] + 80124f2: 4313 orrs r3, r2 + 80124f4: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 80124f6: 68fb ldr r3, [r7, #12] + 80124f8: 693a ldr r2, [r7, #16] + 80124fa: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80124fc: 68fb ldr r3, [r7, #12] + 80124fe: 697a ldr r2, [r7, #20] + 8012500: 621a str r2, [r3, #32] +} + 8012502: bf00 nop + 8012504: 371c adds r7, #28 + 8012506: 46bd mov sp, r7 + 8012508: bc80 pop {r7} + 801250a: 4770 bx lr + +0801250c : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 801250c: b480 push {r7} + 801250e: b087 sub sp, #28 + 8012510: af00 add r7, sp, #0 + 8012512: 60f8 str r0, [r7, #12] + 8012514: 60b9 str r1, [r7, #8] + 8012516: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 8012518: 68fb ldr r3, [r7, #12] + 801251a: 6a1b ldr r3, [r3, #32] + 801251c: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 801251e: 68fb ldr r3, [r7, #12] + 8012520: 6a1b ldr r3, [r3, #32] + 8012522: f023 0210 bic.w r2, r3, #16 + 8012526: 68fb ldr r3, [r7, #12] + 8012528: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 801252a: 68fb ldr r3, [r7, #12] + 801252c: 699b ldr r3, [r3, #24] + 801252e: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8012530: 693b ldr r3, [r7, #16] + 8012532: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 8012536: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8012538: 687b ldr r3, [r7, #4] + 801253a: 031b lsls r3, r3, #12 + 801253c: 693a ldr r2, [r7, #16] + 801253e: 4313 orrs r3, r2 + 8012540: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8012542: 697b ldr r3, [r7, #20] + 8012544: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 8012548: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 801254a: 68bb ldr r3, [r7, #8] + 801254c: 011b lsls r3, r3, #4 + 801254e: 697a ldr r2, [r7, #20] + 8012550: 4313 orrs r3, r2 + 8012552: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8012554: 68fb ldr r3, [r7, #12] + 8012556: 693a ldr r2, [r7, #16] + 8012558: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 801255a: 68fb ldr r3, [r7, #12] + 801255c: 697a ldr r2, [r7, #20] + 801255e: 621a str r2, [r3, #32] +} + 8012560: bf00 nop + 8012562: 371c adds r7, #28 + 8012564: 46bd mov sp, r7 + 8012566: bc80 pop {r7} + 8012568: 4770 bx lr + +0801256a : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 801256a: b480 push {r7} + 801256c: b085 sub sp, #20 + 801256e: af00 add r7, sp, #0 + 8012570: 6078 str r0, [r7, #4] + 8012572: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8012574: 687b ldr r3, [r7, #4] + 8012576: 689b ldr r3, [r3, #8] + 8012578: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 801257a: 68fb ldr r3, [r7, #12] + 801257c: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8012580: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8012582: 683a ldr r2, [r7, #0] + 8012584: 68fb ldr r3, [r7, #12] + 8012586: 4313 orrs r3, r2 + 8012588: f043 0307 orr.w r3, r3, #7 + 801258c: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 801258e: 687b ldr r3, [r7, #4] + 8012590: 68fa ldr r2, [r7, #12] + 8012592: 609a str r2, [r3, #8] +} + 8012594: bf00 nop + 8012596: 3714 adds r7, #20 + 8012598: 46bd mov sp, r7 + 801259a: bc80 pop {r7} + 801259c: 4770 bx lr + +0801259e : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 801259e: b480 push {r7} + 80125a0: b087 sub sp, #28 + 80125a2: af00 add r7, sp, #0 + 80125a4: 60f8 str r0, [r7, #12] + 80125a6: 60b9 str r1, [r7, #8] + 80125a8: 607a str r2, [r7, #4] + 80125aa: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 80125ac: 68fb ldr r3, [r7, #12] + 80125ae: 689b ldr r3, [r3, #8] + 80125b0: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80125b2: 697b ldr r3, [r7, #20] + 80125b4: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 80125b8: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 80125ba: 683b ldr r3, [r7, #0] + 80125bc: 021a lsls r2, r3, #8 + 80125be: 687b ldr r3, [r7, #4] + 80125c0: 431a orrs r2, r3 + 80125c2: 68bb ldr r3, [r7, #8] + 80125c4: 4313 orrs r3, r2 + 80125c6: 697a ldr r2, [r7, #20] + 80125c8: 4313 orrs r3, r2 + 80125ca: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 80125cc: 68fb ldr r3, [r7, #12] + 80125ce: 697a ldr r2, [r7, #20] + 80125d0: 609a str r2, [r3, #8] +} + 80125d2: bf00 nop + 80125d4: 371c adds r7, #28 + 80125d6: 46bd mov sp, r7 + 80125d8: bc80 pop {r7} + 80125da: 4770 bx lr + +080125dc : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 80125dc: b480 push {r7} + 80125de: b087 sub sp, #28 + 80125e0: af00 add r7, sp, #0 + 80125e2: 60f8 str r0, [r7, #12] + 80125e4: 60b9 str r1, [r7, #8] + 80125e6: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 80125e8: 68bb ldr r3, [r7, #8] + 80125ea: f003 031f and.w r3, r3, #31 + 80125ee: 2201 movs r2, #1 + 80125f0: fa02 f303 lsl.w r3, r2, r3 + 80125f4: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 80125f6: 68fb ldr r3, [r7, #12] + 80125f8: 6a1a ldr r2, [r3, #32] + 80125fa: 697b ldr r3, [r7, #20] + 80125fc: 43db mvns r3, r3 + 80125fe: 401a ands r2, r3 + 8012600: 68fb ldr r3, [r7, #12] + 8012602: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8012604: 68fb ldr r3, [r7, #12] + 8012606: 6a1a ldr r2, [r3, #32] + 8012608: 68bb ldr r3, [r7, #8] + 801260a: f003 031f and.w r3, r3, #31 + 801260e: 6879 ldr r1, [r7, #4] + 8012610: fa01 f303 lsl.w r3, r1, r3 + 8012614: 431a orrs r2, r3 + 8012616: 68fb ldr r3, [r7, #12] + 8012618: 621a str r2, [r3, #32] +} + 801261a: bf00 nop + 801261c: 371c adds r7, #28 + 801261e: 46bd mov sp, r7 + 8012620: bc80 pop {r7} + 8012622: 4770 bx lr + +08012624 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8012624: b480 push {r7} + 8012626: b085 sub sp, #20 + 8012628: af00 add r7, sp, #0 + 801262a: 6078 str r0, [r7, #4] + 801262c: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 801262e: 687b ldr r3, [r7, #4] + 8012630: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8012634: 2b01 cmp r3, #1 + 8012636: d101 bne.n 801263c + 8012638: 2302 movs r3, #2 + 801263a: e04b b.n 80126d4 + 801263c: 687b ldr r3, [r7, #4] + 801263e: 2201 movs r2, #1 + 8012640: f883 203c strb.w r2, [r3, #60] @ 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8012644: 687b ldr r3, [r7, #4] + 8012646: 2202 movs r2, #2 + 8012648: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 801264c: 687b ldr r3, [r7, #4] + 801264e: 681b ldr r3, [r3, #0] + 8012650: 685b ldr r3, [r3, #4] + 8012652: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8012654: 687b ldr r3, [r7, #4] + 8012656: 681b ldr r3, [r3, #0] + 8012658: 689b ldr r3, [r3, #8] + 801265a: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 801265c: 68fb ldr r3, [r7, #12] + 801265e: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8012662: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8012664: 683b ldr r3, [r7, #0] + 8012666: 681b ldr r3, [r3, #0] + 8012668: 68fa ldr r2, [r7, #12] + 801266a: 4313 orrs r3, r2 + 801266c: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 801266e: 687b ldr r3, [r7, #4] + 8012670: 681b ldr r3, [r3, #0] + 8012672: 68fa ldr r2, [r7, #12] + 8012674: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8012676: 687b ldr r3, [r7, #4] + 8012678: 681b ldr r3, [r3, #0] + 801267a: 4a19 ldr r2, [pc, #100] @ (80126e0 ) + 801267c: 4293 cmp r3, r2 + 801267e: d013 beq.n 80126a8 + 8012680: 687b ldr r3, [r7, #4] + 8012682: 681b ldr r3, [r3, #0] + 8012684: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8012688: d00e beq.n 80126a8 + 801268a: 687b ldr r3, [r7, #4] + 801268c: 681b ldr r3, [r3, #0] + 801268e: 4a15 ldr r2, [pc, #84] @ (80126e4 ) + 8012690: 4293 cmp r3, r2 + 8012692: d009 beq.n 80126a8 + 8012694: 687b ldr r3, [r7, #4] + 8012696: 681b ldr r3, [r3, #0] + 8012698: 4a13 ldr r2, [pc, #76] @ (80126e8 ) + 801269a: 4293 cmp r3, r2 + 801269c: d004 beq.n 80126a8 + 801269e: 687b ldr r3, [r7, #4] + 80126a0: 681b ldr r3, [r3, #0] + 80126a2: 4a12 ldr r2, [pc, #72] @ (80126ec ) + 80126a4: 4293 cmp r3, r2 + 80126a6: d10c bne.n 80126c2 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 80126a8: 68bb ldr r3, [r7, #8] + 80126aa: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80126ae: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 80126b0: 683b ldr r3, [r7, #0] + 80126b2: 685b ldr r3, [r3, #4] + 80126b4: 68ba ldr r2, [r7, #8] + 80126b6: 4313 orrs r3, r2 + 80126b8: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 80126ba: 687b ldr r3, [r7, #4] + 80126bc: 681b ldr r3, [r3, #0] + 80126be: 68ba ldr r2, [r7, #8] + 80126c0: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 80126c2: 687b ldr r3, [r7, #4] + 80126c4: 2201 movs r2, #1 + 80126c6: f883 203d strb.w r2, [r3, #61] @ 0x3d + + __HAL_UNLOCK(htim); + 80126ca: 687b ldr r3, [r7, #4] + 80126cc: 2200 movs r2, #0 + 80126ce: f883 203c strb.w r2, [r3, #60] @ 0x3c + + return HAL_OK; + 80126d2: 2300 movs r3, #0 +} + 80126d4: 4618 mov r0, r3 + 80126d6: 3714 adds r7, #20 + 80126d8: 46bd mov sp, r7 + 80126da: bc80 pop {r7} + 80126dc: 4770 bx lr + 80126de: bf00 nop + 80126e0: 40012c00 .word 0x40012c00 + 80126e4: 40000400 .word 0x40000400 + 80126e8: 40000800 .word 0x40000800 + 80126ec: 40000c00 .word 0x40000c00 + +080126f0 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 80126f0: b580 push {r7, lr} + 80126f2: b082 sub sp, #8 + 80126f4: af00 add r7, sp, #0 + 80126f6: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 80126f8: 687b ldr r3, [r7, #4] + 80126fa: 2b00 cmp r3, #0 + 80126fc: d101 bne.n 8012702 + { + return HAL_ERROR; + 80126fe: 2301 movs r3, #1 + 8012700: e042 b.n 8012788 + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + 8012702: 687b ldr r3, [r7, #4] + 8012704: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8012708: b2db uxtb r3, r3 + 801270a: 2b00 cmp r3, #0 + 801270c: d106 bne.n 801271c + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 801270e: 687b ldr r3, [r7, #4] + 8012710: 2200 movs r2, #0 + 8012712: f883 2040 strb.w r2, [r3, #64] @ 0x40 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8012716: 6878 ldr r0, [r7, #4] + 8012718: f7fb fe96 bl 800e448 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 801271c: 687b ldr r3, [r7, #4] + 801271e: 2224 movs r2, #36 @ 0x24 + 8012720: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + 8012724: 687b ldr r3, [r7, #4] + 8012726: 681b ldr r3, [r3, #0] + 8012728: 68da ldr r2, [r3, #12] + 801272a: 687b ldr r3, [r7, #4] + 801272c: 681b ldr r3, [r3, #0] + 801272e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 8012732: 60da str r2, [r3, #12] + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + 8012734: 6878 ldr r0, [r7, #4] + 8012736: f000 feb3 bl 80134a0 + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 801273a: 687b ldr r3, [r7, #4] + 801273c: 681b ldr r3, [r3, #0] + 801273e: 691a ldr r2, [r3, #16] + 8012740: 687b ldr r3, [r7, #4] + 8012742: 681b ldr r3, [r3, #0] + 8012744: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 8012748: 611a str r2, [r3, #16] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 801274a: 687b ldr r3, [r7, #4] + 801274c: 681b ldr r3, [r3, #0] + 801274e: 695a ldr r2, [r3, #20] + 8012750: 687b ldr r3, [r7, #4] + 8012752: 681b ldr r3, [r3, #0] + 8012754: f022 022a bic.w r2, r2, #42 @ 0x2a + 8012758: 615a str r2, [r3, #20] + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + 801275a: 687b ldr r3, [r7, #4] + 801275c: 681b ldr r3, [r3, #0] + 801275e: 68da ldr r2, [r3, #12] + 8012760: 687b ldr r3, [r7, #4] + 8012762: 681b ldr r3, [r3, #0] + 8012764: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 8012768: 60da str r2, [r3, #12] + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 801276a: 687b ldr r3, [r7, #4] + 801276c: 2200 movs r2, #0 + 801276e: 645a str r2, [r3, #68] @ 0x44 + huart->gState = HAL_UART_STATE_READY; + 8012770: 687b ldr r3, [r7, #4] + 8012772: 2220 movs r2, #32 + 8012774: f883 2041 strb.w r2, [r3, #65] @ 0x41 + huart->RxState = HAL_UART_STATE_READY; + 8012778: 687b ldr r3, [r7, #4] + 801277a: 2220 movs r2, #32 + 801277c: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8012780: 687b ldr r3, [r7, #4] + 8012782: 2200 movs r2, #0 + 8012784: 635a str r2, [r3, #52] @ 0x34 + + return HAL_OK; + 8012786: 2300 movs r3, #0 +} + 8012788: 4618 mov r0, r3 + 801278a: 3708 adds r7, #8 + 801278c: 46bd mov sp, r7 + 801278e: bd80 pop {r7, pc} + +08012790 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + 8012790: b480 push {r7} + 8012792: b085 sub sp, #20 + 8012794: af00 add r7, sp, #0 + 8012796: 60f8 str r0, [r7, #12] + 8012798: 60b9 str r1, [r7, #8] + 801279a: 4613 mov r3, r2 + 801279c: 80fb strh r3, [r7, #6] + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 801279e: 68fb ldr r3, [r7, #12] + 80127a0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 80127a4: b2db uxtb r3, r3 + 80127a6: 2b20 cmp r3, #32 + 80127a8: d121 bne.n 80127ee + { + if ((pData == NULL) || (Size == 0U)) + 80127aa: 68bb ldr r3, [r7, #8] + 80127ac: 2b00 cmp r3, #0 + 80127ae: d002 beq.n 80127b6 + 80127b0: 88fb ldrh r3, [r7, #6] + 80127b2: 2b00 cmp r3, #0 + 80127b4: d101 bne.n 80127ba + { + return HAL_ERROR; + 80127b6: 2301 movs r3, #1 + 80127b8: e01a b.n 80127f0 + } + + huart->pTxBuffPtr = pData; + 80127ba: 68fb ldr r3, [r7, #12] + 80127bc: 68ba ldr r2, [r7, #8] + 80127be: 621a str r2, [r3, #32] + huart->TxXferSize = Size; + 80127c0: 68fb ldr r3, [r7, #12] + 80127c2: 88fa ldrh r2, [r7, #6] + 80127c4: 849a strh r2, [r3, #36] @ 0x24 + huart->TxXferCount = Size; + 80127c6: 68fb ldr r3, [r7, #12] + 80127c8: 88fa ldrh r2, [r7, #6] + 80127ca: 84da strh r2, [r3, #38] @ 0x26 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80127cc: 68fb ldr r3, [r7, #12] + 80127ce: 2200 movs r2, #0 + 80127d0: 645a str r2, [r3, #68] @ 0x44 + huart->gState = HAL_UART_STATE_BUSY_TX; + 80127d2: 68fb ldr r3, [r7, #12] + 80127d4: 2221 movs r2, #33 @ 0x21 + 80127d6: f883 2041 strb.w r2, [r3, #65] @ 0x41 + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + 80127da: 68fb ldr r3, [r7, #12] + 80127dc: 681b ldr r3, [r3, #0] + 80127de: 68da ldr r2, [r3, #12] + 80127e0: 68fb ldr r3, [r7, #12] + 80127e2: 681b ldr r3, [r3, #0] + 80127e4: f042 0280 orr.w r2, r2, #128 @ 0x80 + 80127e8: 60da str r2, [r3, #12] + + return HAL_OK; + 80127ea: 2300 movs r3, #0 + 80127ec: e000 b.n 80127f0 + } + else + { + return HAL_BUSY; + 80127ee: 2302 movs r3, #2 + } +} + 80127f0: 4618 mov r0, r3 + 80127f2: 3714 adds r7, #20 + 80127f4: 46bd mov sp, r7 + 80127f6: bc80 pop {r7} + 80127f8: 4770 bx lr + +080127fa : + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 80127fa: b580 push {r7, lr} + 80127fc: b08c sub sp, #48 @ 0x30 + 80127fe: af00 add r7, sp, #0 + 8012800: 60f8 str r0, [r7, #12] + 8012802: 60b9 str r1, [r7, #8] + 8012804: 4613 mov r3, r2 + 8012806: 80fb strh r3, [r7, #6] + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8012808: 68fb ldr r3, [r7, #12] + 801280a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 801280e: b2db uxtb r3, r3 + 8012810: 2b20 cmp r3, #32 + 8012812: d14a bne.n 80128aa + { + if ((pData == NULL) || (Size == 0U)) + 8012814: 68bb ldr r3, [r7, #8] + 8012816: 2b00 cmp r3, #0 + 8012818: d002 beq.n 8012820 + 801281a: 88fb ldrh r3, [r7, #6] + 801281c: 2b00 cmp r3, #0 + 801281e: d101 bne.n 8012824 + { + return HAL_ERROR; + 8012820: 2301 movs r3, #1 + 8012822: e043 b.n 80128ac + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 8012824: 68fb ldr r3, [r7, #12] + 8012826: 2201 movs r2, #1 + 8012828: 631a str r2, [r3, #48] @ 0x30 + huart->RxEventType = HAL_UART_RXEVENT_TC; + 801282a: 68fb ldr r3, [r7, #12] + 801282c: 2200 movs r2, #0 + 801282e: 635a str r2, [r3, #52] @ 0x34 + + status = UART_Start_Receive_IT(huart, pData, Size); + 8012830: 88fb ldrh r3, [r7, #6] + 8012832: 461a mov r2, r3 + 8012834: 68b9 ldr r1, [r7, #8] + 8012836: 68f8 ldr r0, [r7, #12] + 8012838: f000 fbfd bl 8013036 + 801283c: 4603 mov r3, r0 + 801283e: f887 302f strb.w r3, [r7, #47] @ 0x2f + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + 8012842: f897 302f ldrb.w r3, [r7, #47] @ 0x2f + 8012846: 2b00 cmp r3, #0 + 8012848: d12c bne.n 80128a4 + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 801284a: 68fb ldr r3, [r7, #12] + 801284c: 6b1b ldr r3, [r3, #48] @ 0x30 + 801284e: 2b01 cmp r3, #1 + 8012850: d125 bne.n 801289e + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + 8012852: 2300 movs r3, #0 + 8012854: 613b str r3, [r7, #16] + 8012856: 68fb ldr r3, [r7, #12] + 8012858: 681b ldr r3, [r3, #0] + 801285a: 681b ldr r3, [r3, #0] + 801285c: 613b str r3, [r7, #16] + 801285e: 68fb ldr r3, [r7, #12] + 8012860: 681b ldr r3, [r3, #0] + 8012862: 685b ldr r3, [r3, #4] + 8012864: 613b str r3, [r7, #16] + 8012866: 693b ldr r3, [r7, #16] + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8012868: 68fb ldr r3, [r7, #12] + 801286a: 681b ldr r3, [r3, #0] + 801286c: 330c adds r3, #12 + 801286e: 61bb str r3, [r7, #24] + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012870: 69bb ldr r3, [r7, #24] + 8012872: e853 3f00 ldrex r3, [r3] + 8012876: 617b str r3, [r7, #20] + return(result); + 8012878: 697b ldr r3, [r7, #20] + 801287a: f043 0310 orr.w r3, r3, #16 + 801287e: 62bb str r3, [r7, #40] @ 0x28 + 8012880: 68fb ldr r3, [r7, #12] + 8012882: 681b ldr r3, [r3, #0] + 8012884: 330c adds r3, #12 + 8012886: 6aba ldr r2, [r7, #40] @ 0x28 + 8012888: 627a str r2, [r7, #36] @ 0x24 + 801288a: 623b str r3, [r7, #32] + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 801288c: 6a39 ldr r1, [r7, #32] + 801288e: 6a7a ldr r2, [r7, #36] @ 0x24 + 8012890: e841 2300 strex r3, r2, [r1] + 8012894: 61fb str r3, [r7, #28] + return(result); + 8012896: 69fb ldr r3, [r7, #28] + 8012898: 2b00 cmp r3, #0 + 801289a: d1e5 bne.n 8012868 + 801289c: e002 b.n 80128a4 + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + 801289e: 2301 movs r3, #1 + 80128a0: f887 302f strb.w r3, [r7, #47] @ 0x2f + } + } + + return status; + 80128a4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f + 80128a8: e000 b.n 80128ac + } + else + { + return HAL_BUSY; + 80128aa: 2302 movs r3, #2 + } +} + 80128ac: 4618 mov r0, r3 + 80128ae: 3730 adds r7, #48 @ 0x30 + 80128b0: 46bd mov sp, r7 + 80128b2: bd80 pop {r7, pc} + +080128b4 : + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + 80128b4: b580 push {r7, lr} + 80128b6: b0a2 sub sp, #136 @ 0x88 + 80128b8: af00 add r7, sp, #0 + 80128ba: 6078 str r0, [r7, #4] + uint32_t AbortCplt = 0x01U; + 80128bc: 2301 movs r3, #1 + 80128be: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + 80128c2: 687b ldr r3, [r7, #4] + 80128c4: 681b ldr r3, [r3, #0] + 80128c6: 330c adds r3, #12 + 80128c8: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80128ca: 6e3b ldr r3, [r7, #96] @ 0x60 + 80128cc: e853 3f00 ldrex r3, [r3] + 80128d0: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 80128d2: 6dfb ldr r3, [r7, #92] @ 0x5c + 80128d4: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 + 80128d8: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 80128dc: 687b ldr r3, [r7, #4] + 80128de: 681b ldr r3, [r3, #0] + 80128e0: 330c adds r3, #12 + 80128e2: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 80128e6: 66fa str r2, [r7, #108] @ 0x6c + 80128e8: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80128ea: 6eb9 ldr r1, [r7, #104] @ 0x68 + 80128ec: 6efa ldr r2, [r7, #108] @ 0x6c + 80128ee: e841 2300 strex r3, r2, [r1] + 80128f2: 667b str r3, [r7, #100] @ 0x64 + return(result); + 80128f4: 6e7b ldr r3, [r7, #100] @ 0x64 + 80128f6: 2b00 cmp r3, #0 + 80128f8: d1e3 bne.n 80128c2 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80128fa: 687b ldr r3, [r7, #4] + 80128fc: 681b ldr r3, [r3, #0] + 80128fe: 3314 adds r3, #20 + 8012900: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012902: 6cfb ldr r3, [r7, #76] @ 0x4c + 8012904: e853 3f00 ldrex r3, [r3] + 8012908: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 801290a: 6cbb ldr r3, [r7, #72] @ 0x48 + 801290c: f023 0301 bic.w r3, r3, #1 + 8012910: 67fb str r3, [r7, #124] @ 0x7c + 8012912: 687b ldr r3, [r7, #4] + 8012914: 681b ldr r3, [r3, #0] + 8012916: 3314 adds r3, #20 + 8012918: 6ffa ldr r2, [r7, #124] @ 0x7c + 801291a: 65ba str r2, [r7, #88] @ 0x58 + 801291c: 657b str r3, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 801291e: 6d79 ldr r1, [r7, #84] @ 0x54 + 8012920: 6dba ldr r2, [r7, #88] @ 0x58 + 8012922: e841 2300 strex r3, r2, [r1] + 8012926: 653b str r3, [r7, #80] @ 0x50 + return(result); + 8012928: 6d3b ldr r3, [r7, #80] @ 0x50 + 801292a: 2b00 cmp r3, #0 + 801292c: d1e5 bne.n 80128fa + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 801292e: 687b ldr r3, [r7, #4] + 8012930: 6b1b ldr r3, [r3, #48] @ 0x30 + 8012932: 2b01 cmp r3, #1 + 8012934: d119 bne.n 801296a + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + 8012936: 687b ldr r3, [r7, #4] + 8012938: 681b ldr r3, [r3, #0] + 801293a: 330c adds r3, #12 + 801293c: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 801293e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8012940: e853 3f00 ldrex r3, [r3] + 8012944: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8012946: 6b7b ldr r3, [r7, #52] @ 0x34 + 8012948: f023 0310 bic.w r3, r3, #16 + 801294c: 67bb str r3, [r7, #120] @ 0x78 + 801294e: 687b ldr r3, [r7, #4] + 8012950: 681b ldr r3, [r3, #0] + 8012952: 330c adds r3, #12 + 8012954: 6fba ldr r2, [r7, #120] @ 0x78 + 8012956: 647a str r2, [r7, #68] @ 0x44 + 8012958: 643b str r3, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 801295a: 6c39 ldr r1, [r7, #64] @ 0x40 + 801295c: 6c7a ldr r2, [r7, #68] @ 0x44 + 801295e: e841 2300 strex r3, r2, [r1] + 8012962: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8012964: 6bfb ldr r3, [r7, #60] @ 0x3c + 8012966: 2b00 cmp r3, #0 + 8012968: d1e5 bne.n 8012936 + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + 801296a: 687b ldr r3, [r7, #4] + 801296c: 6b9b ldr r3, [r3, #56] @ 0x38 + 801296e: 2b00 cmp r3, #0 + 8012970: d00f beq.n 8012992 + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + 8012972: 687b ldr r3, [r7, #4] + 8012974: 681b ldr r3, [r3, #0] + 8012976: 695b ldr r3, [r3, #20] + 8012978: f003 0380 and.w r3, r3, #128 @ 0x80 + 801297c: 2b00 cmp r3, #0 + 801297e: d004 beq.n 801298a + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + 8012980: 687b ldr r3, [r7, #4] + 8012982: 6b9b ldr r3, [r3, #56] @ 0x38 + 8012984: 4a53 ldr r2, [pc, #332] @ (8012ad4 ) + 8012986: 635a str r2, [r3, #52] @ 0x34 + 8012988: e003 b.n 8012992 + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + 801298a: 687b ldr r3, [r7, #4] + 801298c: 6b9b ldr r3, [r3, #56] @ 0x38 + 801298e: 2200 movs r2, #0 + 8012990: 635a str r2, [r3, #52] @ 0x34 + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + 8012992: 687b ldr r3, [r7, #4] + 8012994: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012996: 2b00 cmp r3, #0 + 8012998: d00f beq.n 80129ba + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 801299a: 687b ldr r3, [r7, #4] + 801299c: 681b ldr r3, [r3, #0] + 801299e: 695b ldr r3, [r3, #20] + 80129a0: f003 0340 and.w r3, r3, #64 @ 0x40 + 80129a4: 2b00 cmp r3, #0 + 80129a6: d004 beq.n 80129b2 + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + 80129a8: 687b ldr r3, [r7, #4] + 80129aa: 6bdb ldr r3, [r3, #60] @ 0x3c + 80129ac: 4a4a ldr r2, [pc, #296] @ (8012ad8 ) + 80129ae: 635a str r2, [r3, #52] @ 0x34 + 80129b0: e003 b.n 80129ba + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + 80129b2: 687b ldr r3, [r7, #4] + 80129b4: 6bdb ldr r3, [r3, #60] @ 0x3c + 80129b6: 2200 movs r2, #0 + 80129b8: 635a str r2, [r3, #52] @ 0x34 + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + 80129ba: 687b ldr r3, [r7, #4] + 80129bc: 681b ldr r3, [r3, #0] + 80129be: 695b ldr r3, [r3, #20] + 80129c0: f003 0380 and.w r3, r3, #128 @ 0x80 + 80129c4: 2b00 cmp r3, #0 + 80129c6: d02d beq.n 8012a24 + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 80129c8: 687b ldr r3, [r7, #4] + 80129ca: 681b ldr r3, [r3, #0] + 80129cc: 3314 adds r3, #20 + 80129ce: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80129d0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80129d2: e853 3f00 ldrex r3, [r3] + 80129d6: 623b str r3, [r7, #32] + return(result); + 80129d8: 6a3b ldr r3, [r7, #32] + 80129da: f023 0380 bic.w r3, r3, #128 @ 0x80 + 80129de: 677b str r3, [r7, #116] @ 0x74 + 80129e0: 687b ldr r3, [r7, #4] + 80129e2: 681b ldr r3, [r3, #0] + 80129e4: 3314 adds r3, #20 + 80129e6: 6f7a ldr r2, [r7, #116] @ 0x74 + 80129e8: 633a str r2, [r7, #48] @ 0x30 + 80129ea: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80129ec: 6af9 ldr r1, [r7, #44] @ 0x2c + 80129ee: 6b3a ldr r2, [r7, #48] @ 0x30 + 80129f0: e841 2300 strex r3, r2, [r1] + 80129f4: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 80129f6: 6abb ldr r3, [r7, #40] @ 0x28 + 80129f8: 2b00 cmp r3, #0 + 80129fa: d1e5 bne.n 80129c8 + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + 80129fc: 687b ldr r3, [r7, #4] + 80129fe: 6b9b ldr r3, [r3, #56] @ 0x38 + 8012a00: 2b00 cmp r3, #0 + 8012a02: d00f beq.n 8012a24 + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + 8012a04: 687b ldr r3, [r7, #4] + 8012a06: 6b9b ldr r3, [r3, #56] @ 0x38 + 8012a08: 4618 mov r0, r3 + 8012a0a: f7fd fc45 bl 8010298 + 8012a0e: 4603 mov r3, r0 + 8012a10: 2b00 cmp r3, #0 + 8012a12: d004 beq.n 8012a1e + { + huart->hdmatx->XferAbortCallback = NULL; + 8012a14: 687b ldr r3, [r7, #4] + 8012a16: 6b9b ldr r3, [r3, #56] @ 0x38 + 8012a18: 2200 movs r2, #0 + 8012a1a: 635a str r2, [r3, #52] @ 0x34 + 8012a1c: e002 b.n 8012a24 + } + else + { + AbortCplt = 0x00U; + 8012a1e: 2300 movs r3, #0 + 8012a20: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012a24: 687b ldr r3, [r7, #4] + 8012a26: 681b ldr r3, [r3, #0] + 8012a28: 695b ldr r3, [r3, #20] + 8012a2a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012a2e: 2b00 cmp r3, #0 + 8012a30: d030 beq.n 8012a94 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8012a32: 687b ldr r3, [r7, #4] + 8012a34: 681b ldr r3, [r3, #0] + 8012a36: 3314 adds r3, #20 + 8012a38: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012a3a: 693b ldr r3, [r7, #16] + 8012a3c: e853 3f00 ldrex r3, [r3] + 8012a40: 60fb str r3, [r7, #12] + return(result); + 8012a42: 68fb ldr r3, [r7, #12] + 8012a44: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8012a48: 673b str r3, [r7, #112] @ 0x70 + 8012a4a: 687b ldr r3, [r7, #4] + 8012a4c: 681b ldr r3, [r3, #0] + 8012a4e: 3314 adds r3, #20 + 8012a50: 6f3a ldr r2, [r7, #112] @ 0x70 + 8012a52: 61fa str r2, [r7, #28] + 8012a54: 61bb str r3, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012a56: 69b9 ldr r1, [r7, #24] + 8012a58: 69fa ldr r2, [r7, #28] + 8012a5a: e841 2300 strex r3, r2, [r1] + 8012a5e: 617b str r3, [r7, #20] + return(result); + 8012a60: 697b ldr r3, [r7, #20] + 8012a62: 2b00 cmp r3, #0 + 8012a64: d1e5 bne.n 8012a32 + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + 8012a66: 687b ldr r3, [r7, #4] + 8012a68: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012a6a: 2b00 cmp r3, #0 + 8012a6c: d012 beq.n 8012a94 + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8012a6e: 687b ldr r3, [r7, #4] + 8012a70: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012a72: 4618 mov r0, r3 + 8012a74: f7fd fc10 bl 8010298 + 8012a78: 4603 mov r3, r0 + 8012a7a: 2b00 cmp r3, #0 + 8012a7c: d007 beq.n 8012a8e + { + huart->hdmarx->XferAbortCallback = NULL; + 8012a7e: 687b ldr r3, [r7, #4] + 8012a80: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012a82: 2200 movs r2, #0 + 8012a84: 635a str r2, [r3, #52] @ 0x34 + AbortCplt = 0x01U; + 8012a86: 2301 movs r3, #1 + 8012a88: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 8012a8c: e002 b.n 8012a94 + } + else + { + AbortCplt = 0x00U; + 8012a8e: 2300 movs r3, #0 + 8012a90: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + 8012a94: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8012a98: 2b01 cmp r3, #1 + 8012a9a: d116 bne.n 8012aca + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + 8012a9c: 687b ldr r3, [r7, #4] + 8012a9e: 2200 movs r2, #0 + 8012aa0: 84da strh r2, [r3, #38] @ 0x26 + huart->RxXferCount = 0x00U; + 8012aa2: 687b ldr r3, [r7, #4] + 8012aa4: 2200 movs r2, #0 + 8012aa6: 85da strh r2, [r3, #46] @ 0x2e + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8012aa8: 687b ldr r3, [r7, #4] + 8012aaa: 2200 movs r2, #0 + 8012aac: 645a str r2, [r3, #68] @ 0x44 + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8012aae: 687b ldr r3, [r7, #4] + 8012ab0: 2220 movs r2, #32 + 8012ab2: f883 2041 strb.w r2, [r3, #65] @ 0x41 + huart->RxState = HAL_UART_STATE_READY; + 8012ab6: 687b ldr r3, [r7, #4] + 8012ab8: 2220 movs r2, #32 + 8012aba: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8012abe: 687b ldr r3, [r7, #4] + 8012ac0: 2200 movs r2, #0 + 8012ac2: 631a str r2, [r3, #48] @ 0x30 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); + 8012ac4: 6878 ldr r0, [r7, #4] + 8012ac6: f000 faad bl 8013024 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; + 8012aca: 2300 movs r3, #0 +} + 8012acc: 4618 mov r0, r3 + 8012ace: 3788 adds r7, #136 @ 0x88 + 8012ad0: 46bd mov sp, r7 + 8012ad2: bd80 pop {r7, pc} + 8012ad4: 08013195 .word 0x08013195 + 8012ad8: 080131f5 .word 0x080131f5 + +08012adc : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8012adc: b580 push {r7, lr} + 8012ade: b0ba sub sp, #232 @ 0xe8 + 8012ae0: af00 add r7, sp, #0 + 8012ae2: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->SR); + 8012ae4: 687b ldr r3, [r7, #4] + 8012ae6: 681b ldr r3, [r3, #0] + 8012ae8: 681b ldr r3, [r3, #0] + 8012aea: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8012aee: 687b ldr r3, [r7, #4] + 8012af0: 681b ldr r3, [r3, #0] + 8012af2: 68db ldr r3, [r3, #12] + 8012af4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8012af8: 687b ldr r3, [r7, #4] + 8012afa: 681b ldr r3, [r3, #0] + 8012afc: 695b ldr r3, [r3, #20] + 8012afe: f8c7 30dc str.w r3, [r7, #220] @ 0xdc + uint32_t errorflags = 0x00U; + 8012b02: 2300 movs r3, #0 + 8012b04: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + uint32_t dmarequest = 0x00U; + 8012b08: 2300 movs r3, #0 + 8012b0a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + 8012b0e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012b12: f003 030f and.w r3, r3, #15 + 8012b16: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + if (errorflags == RESET) + 8012b1a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 8012b1e: 2b00 cmp r3, #0 + 8012b20: d10f bne.n 8012b42 + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + 8012b22: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012b26: f003 0320 and.w r3, r3, #32 + 8012b2a: 2b00 cmp r3, #0 + 8012b2c: d009 beq.n 8012b42 + 8012b2e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012b32: f003 0320 and.w r3, r3, #32 + 8012b36: 2b00 cmp r3, #0 + 8012b38: d003 beq.n 8012b42 + { + UART_Receive_IT(huart); + 8012b3a: 6878 ldr r0, [r7, #4] + 8012b3c: f000 fbf1 bl 8013322 + return; + 8012b40: e25b b.n 8012ffa + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + 8012b42: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 8012b46: 2b00 cmp r3, #0 + 8012b48: f000 80de beq.w 8012d08 + 8012b4c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8012b50: f003 0301 and.w r3, r3, #1 + 8012b54: 2b00 cmp r3, #0 + 8012b56: d106 bne.n 8012b66 + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + 8012b58: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012b5c: f403 7390 and.w r3, r3, #288 @ 0x120 + 8012b60: 2b00 cmp r3, #0 + 8012b62: f000 80d1 beq.w 8012d08 + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + 8012b66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012b6a: f003 0301 and.w r3, r3, #1 + 8012b6e: 2b00 cmp r3, #0 + 8012b70: d00b beq.n 8012b8a + 8012b72: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012b76: f403 7380 and.w r3, r3, #256 @ 0x100 + 8012b7a: 2b00 cmp r3, #0 + 8012b7c: d005 beq.n 8012b8a + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8012b7e: 687b ldr r3, [r7, #4] + 8012b80: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012b82: f043 0201 orr.w r2, r3, #1 + 8012b86: 687b ldr r3, [r7, #4] + 8012b88: 645a str r2, [r3, #68] @ 0x44 + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + 8012b8a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012b8e: f003 0304 and.w r3, r3, #4 + 8012b92: 2b00 cmp r3, #0 + 8012b94: d00b beq.n 8012bae + 8012b96: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8012b9a: f003 0301 and.w r3, r3, #1 + 8012b9e: 2b00 cmp r3, #0 + 8012ba0: d005 beq.n 8012bae + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8012ba2: 687b ldr r3, [r7, #4] + 8012ba4: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012ba6: f043 0202 orr.w r2, r3, #2 + 8012baa: 687b ldr r3, [r7, #4] + 8012bac: 645a str r2, [r3, #68] @ 0x44 + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + 8012bae: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012bb2: f003 0302 and.w r3, r3, #2 + 8012bb6: 2b00 cmp r3, #0 + 8012bb8: d00b beq.n 8012bd2 + 8012bba: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8012bbe: f003 0301 and.w r3, r3, #1 + 8012bc2: 2b00 cmp r3, #0 + 8012bc4: d005 beq.n 8012bd2 + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8012bc6: 687b ldr r3, [r7, #4] + 8012bc8: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012bca: f043 0204 orr.w r2, r3, #4 + 8012bce: 687b ldr r3, [r7, #4] + 8012bd0: 645a str r2, [r3, #68] @ 0x44 + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + 8012bd2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012bd6: f003 0308 and.w r3, r3, #8 + 8012bda: 2b00 cmp r3, #0 + 8012bdc: d011 beq.n 8012c02 + 8012bde: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012be2: f003 0320 and.w r3, r3, #32 + 8012be6: 2b00 cmp r3, #0 + 8012be8: d105 bne.n 8012bf6 + || ((cr3its & USART_CR3_EIE) != RESET))) + 8012bea: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8012bee: f003 0301 and.w r3, r3, #1 + 8012bf2: 2b00 cmp r3, #0 + 8012bf4: d005 beq.n 8012c02 + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 8012bf6: 687b ldr r3, [r7, #4] + 8012bf8: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012bfa: f043 0208 orr.w r2, r3, #8 + 8012bfe: 687b ldr r3, [r7, #4] + 8012c00: 645a str r2, [r3, #68] @ 0x44 + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8012c02: 687b ldr r3, [r7, #4] + 8012c04: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012c06: 2b00 cmp r3, #0 + 8012c08: f000 81f2 beq.w 8012ff0 + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + 8012c0c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012c10: f003 0320 and.w r3, r3, #32 + 8012c14: 2b00 cmp r3, #0 + 8012c16: d008 beq.n 8012c2a + 8012c18: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012c1c: f003 0320 and.w r3, r3, #32 + 8012c20: 2b00 cmp r3, #0 + 8012c22: d002 beq.n 8012c2a + { + UART_Receive_IT(huart); + 8012c24: 6878 ldr r0, [r7, #4] + 8012c26: f000 fb7c bl 8013322 + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + 8012c2a: 687b ldr r3, [r7, #4] + 8012c2c: 681b ldr r3, [r3, #0] + 8012c2e: 695b ldr r3, [r3, #20] + 8012c30: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012c34: 2b00 cmp r3, #0 + 8012c36: bf14 ite ne + 8012c38: 2301 movne r3, #1 + 8012c3a: 2300 moveq r3, #0 + 8012c3c: b2db uxtb r3, r3 + 8012c3e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + 8012c42: 687b ldr r3, [r7, #4] + 8012c44: 6c5b ldr r3, [r3, #68] @ 0x44 + 8012c46: f003 0308 and.w r3, r3, #8 + 8012c4a: 2b00 cmp r3, #0 + 8012c4c: d103 bne.n 8012c56 + 8012c4e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 + 8012c52: 2b00 cmp r3, #0 + 8012c54: d04f beq.n 8012cf6 + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 8012c56: 6878 ldr r0, [r7, #4] + 8012c58: f000 fa26 bl 80130a8 + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012c5c: 687b ldr r3, [r7, #4] + 8012c5e: 681b ldr r3, [r3, #0] + 8012c60: 695b ldr r3, [r3, #20] + 8012c62: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012c66: 2b00 cmp r3, #0 + 8012c68: d041 beq.n 8012cee + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8012c6a: 687b ldr r3, [r7, #4] + 8012c6c: 681b ldr r3, [r3, #0] + 8012c6e: 3314 adds r3, #20 + 8012c70: f8c7 309c str.w r3, [r7, #156] @ 0x9c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012c74: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 8012c78: e853 3f00 ldrex r3, [r3] + 8012c7c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + return(result); + 8012c80: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8012c84: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8012c88: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 8012c8c: 687b ldr r3, [r7, #4] + 8012c8e: 681b ldr r3, [r3, #0] + 8012c90: 3314 adds r3, #20 + 8012c92: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 8012c96: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 + 8012c9a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012c9e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 + 8012ca2: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 + 8012ca6: e841 2300 strex r3, r2, [r1] + 8012caa: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + return(result); + 8012cae: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8012cb2: 2b00 cmp r3, #0 + 8012cb4: d1d9 bne.n 8012c6a + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 8012cb6: 687b ldr r3, [r7, #4] + 8012cb8: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012cba: 2b00 cmp r3, #0 + 8012cbc: d013 beq.n 8012ce6 + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 8012cbe: 687b ldr r3, [r7, #4] + 8012cc0: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012cc2: 4a7e ldr r2, [pc, #504] @ (8012ebc ) + 8012cc4: 635a str r2, [r3, #52] @ 0x34 + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8012cc6: 687b ldr r3, [r7, #4] + 8012cc8: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012cca: 4618 mov r0, r3 + 8012ccc: f7fd fae4 bl 8010298 + 8012cd0: 4603 mov r3, r0 + 8012cd2: 2b00 cmp r3, #0 + 8012cd4: d016 beq.n 8012d04 + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8012cd6: 687b ldr r3, [r7, #4] + 8012cd8: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012cda: 6b5b ldr r3, [r3, #52] @ 0x34 + 8012cdc: 687a ldr r2, [r7, #4] + 8012cde: 6bd2 ldr r2, [r2, #60] @ 0x3c + 8012ce0: 4610 mov r0, r2 + 8012ce2: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012ce4: e00e b.n 8012d04 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8012ce6: 6878 ldr r0, [r7, #4] + 8012ce8: f000 f993 bl 8013012 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012cec: e00a b.n 8012d04 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8012cee: 6878 ldr r0, [r7, #4] + 8012cf0: f000 f98f bl 8013012 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012cf4: e006 b.n 8012d04 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8012cf6: 6878 ldr r0, [r7, #4] + 8012cf8: f000 f98b bl 8013012 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8012cfc: 687b ldr r3, [r7, #4] + 8012cfe: 2200 movs r2, #0 + 8012d00: 645a str r2, [r3, #68] @ 0x44 + } + } + return; + 8012d02: e175 b.n 8012ff0 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012d04: bf00 nop + return; + 8012d06: e173 b.n 8012ff0 + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8012d08: 687b ldr r3, [r7, #4] + 8012d0a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8012d0c: 2b01 cmp r3, #1 + 8012d0e: f040 814f bne.w 8012fb0 + && ((isrflags & USART_SR_IDLE) != 0U) + 8012d12: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012d16: f003 0310 and.w r3, r3, #16 + 8012d1a: 2b00 cmp r3, #0 + 8012d1c: f000 8148 beq.w 8012fb0 + && ((cr1its & USART_SR_IDLE) != 0U)) + 8012d20: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012d24: f003 0310 and.w r3, r3, #16 + 8012d28: 2b00 cmp r3, #0 + 8012d2a: f000 8141 beq.w 8012fb0 + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + 8012d2e: 2300 movs r3, #0 + 8012d30: 60bb str r3, [r7, #8] + 8012d32: 687b ldr r3, [r7, #4] + 8012d34: 681b ldr r3, [r3, #0] + 8012d36: 681b ldr r3, [r3, #0] + 8012d38: 60bb str r3, [r7, #8] + 8012d3a: 687b ldr r3, [r7, #4] + 8012d3c: 681b ldr r3, [r3, #0] + 8012d3e: 685b ldr r3, [r3, #4] + 8012d40: 60bb str r3, [r7, #8] + 8012d42: 68bb ldr r3, [r7, #8] + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8012d44: 687b ldr r3, [r7, #4] + 8012d46: 681b ldr r3, [r3, #0] + 8012d48: 695b ldr r3, [r3, #20] + 8012d4a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012d4e: 2b00 cmp r3, #0 + 8012d50: f000 80b6 beq.w 8012ec0 + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + 8012d54: 687b ldr r3, [r7, #4] + 8012d56: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012d58: 681b ldr r3, [r3, #0] + 8012d5a: 685b ldr r3, [r3, #4] + 8012d5c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe + if ((nb_remaining_rx_data > 0U) + 8012d60: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe + 8012d64: 2b00 cmp r3, #0 + 8012d66: f000 8145 beq.w 8012ff4 + && (nb_remaining_rx_data < huart->RxXferSize)) + 8012d6a: 687b ldr r3, [r7, #4] + 8012d6c: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8012d6e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8012d72: 429a cmp r2, r3 + 8012d74: f080 813e bcs.w 8012ff4 + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + 8012d78: 687b ldr r3, [r7, #4] + 8012d7a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8012d7e: 85da strh r2, [r3, #46] @ 0x2e + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + 8012d80: 687b ldr r3, [r7, #4] + 8012d82: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012d84: 699b ldr r3, [r3, #24] + 8012d86: 2b20 cmp r3, #32 + 8012d88: f000 8088 beq.w 8012e9c + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8012d8c: 687b ldr r3, [r7, #4] + 8012d8e: 681b ldr r3, [r3, #0] + 8012d90: 330c adds r3, #12 + 8012d92: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012d96: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 + 8012d9a: e853 3f00 ldrex r3, [r3] + 8012d9e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + return(result); + 8012da2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8012da6: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8012daa: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 8012dae: 687b ldr r3, [r7, #4] + 8012db0: 681b ldr r3, [r3, #0] + 8012db2: 330c adds r3, #12 + 8012db4: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 + 8012db8: f8c7 2094 str.w r2, [r7, #148] @ 0x94 + 8012dbc: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012dc0: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 + 8012dc4: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8012dc8: e841 2300 strex r3, r2, [r1] + 8012dcc: f8c7 308c str.w r3, [r7, #140] @ 0x8c + return(result); + 8012dd0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8012dd4: 2b00 cmp r3, #0 + 8012dd6: d1d9 bne.n 8012d8c + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8012dd8: 687b ldr r3, [r7, #4] + 8012dda: 681b ldr r3, [r3, #0] + 8012ddc: 3314 adds r3, #20 + 8012dde: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012de0: 6f7b ldr r3, [r7, #116] @ 0x74 + 8012de2: e853 3f00 ldrex r3, [r3] + 8012de6: 673b str r3, [r7, #112] @ 0x70 + return(result); + 8012de8: 6f3b ldr r3, [r7, #112] @ 0x70 + 8012dea: f023 0301 bic.w r3, r3, #1 + 8012dee: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8012df2: 687b ldr r3, [r7, #4] + 8012df4: 681b ldr r3, [r3, #0] + 8012df6: 3314 adds r3, #20 + 8012df8: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 8012dfc: f8c7 2080 str.w r2, [r7, #128] @ 0x80 + 8012e00: 67fb str r3, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012e02: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8012e04: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8012e08: e841 2300 strex r3, r2, [r1] + 8012e0c: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 8012e0e: 6fbb ldr r3, [r7, #120] @ 0x78 + 8012e10: 2b00 cmp r3, #0 + 8012e12: d1e1 bne.n 8012dd8 + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8012e14: 687b ldr r3, [r7, #4] + 8012e16: 681b ldr r3, [r3, #0] + 8012e18: 3314 adds r3, #20 + 8012e1a: 663b str r3, [r7, #96] @ 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012e1c: 6e3b ldr r3, [r7, #96] @ 0x60 + 8012e1e: e853 3f00 ldrex r3, [r3] + 8012e22: 65fb str r3, [r7, #92] @ 0x5c + return(result); + 8012e24: 6dfb ldr r3, [r7, #92] @ 0x5c + 8012e26: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8012e2a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8012e2e: 687b ldr r3, [r7, #4] + 8012e30: 681b ldr r3, [r3, #0] + 8012e32: 3314 adds r3, #20 + 8012e34: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 + 8012e38: 66fa str r2, [r7, #108] @ 0x6c + 8012e3a: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012e3c: 6eb9 ldr r1, [r7, #104] @ 0x68 + 8012e3e: 6efa ldr r2, [r7, #108] @ 0x6c + 8012e40: e841 2300 strex r3, r2, [r1] + 8012e44: 667b str r3, [r7, #100] @ 0x64 + return(result); + 8012e46: 6e7b ldr r3, [r7, #100] @ 0x64 + 8012e48: 2b00 cmp r3, #0 + 8012e4a: d1e3 bne.n 8012e14 + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8012e4c: 687b ldr r3, [r7, #4] + 8012e4e: 2220 movs r2, #32 + 8012e50: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8012e54: 687b ldr r3, [r7, #4] + 8012e56: 2200 movs r2, #0 + 8012e58: 631a str r2, [r3, #48] @ 0x30 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8012e5a: 687b ldr r3, [r7, #4] + 8012e5c: 681b ldr r3, [r3, #0] + 8012e5e: 330c adds r3, #12 + 8012e60: 64fb str r3, [r7, #76] @ 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012e62: 6cfb ldr r3, [r7, #76] @ 0x4c + 8012e64: e853 3f00 ldrex r3, [r3] + 8012e68: 64bb str r3, [r7, #72] @ 0x48 + return(result); + 8012e6a: 6cbb ldr r3, [r7, #72] @ 0x48 + 8012e6c: f023 0310 bic.w r3, r3, #16 + 8012e70: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8012e74: 687b ldr r3, [r7, #4] + 8012e76: 681b ldr r3, [r3, #0] + 8012e78: 330c adds r3, #12 + 8012e7a: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac + 8012e7e: 65ba str r2, [r7, #88] @ 0x58 + 8012e80: 657b str r3, [r7, #84] @ 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012e82: 6d79 ldr r1, [r7, #84] @ 0x54 + 8012e84: 6dba ldr r2, [r7, #88] @ 0x58 + 8012e86: e841 2300 strex r3, r2, [r1] + 8012e8a: 653b str r3, [r7, #80] @ 0x50 + return(result); + 8012e8c: 6d3b ldr r3, [r7, #80] @ 0x50 + 8012e8e: 2b00 cmp r3, #0 + 8012e90: d1e3 bne.n 8012e5a + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + 8012e92: 687b ldr r3, [r7, #4] + 8012e94: 6bdb ldr r3, [r3, #60] @ 0x3c + 8012e96: 4618 mov r0, r3 + 8012e98: f7fd f9c3 bl 8010222 + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8012e9c: 687b ldr r3, [r7, #4] + 8012e9e: 2202 movs r2, #2 + 8012ea0: 635a str r2, [r3, #52] @ 0x34 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 8012ea2: 687b ldr r3, [r7, #4] + 8012ea4: 8d9a ldrh r2, [r3, #44] @ 0x2c + 8012ea6: 687b ldr r3, [r7, #4] + 8012ea8: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8012eaa: b29b uxth r3, r3 + 8012eac: 1ad3 subs r3, r2, r3 + 8012eae: b29b uxth r3, r3 + 8012eb0: 4619 mov r1, r3 + 8012eb2: 6878 ldr r0, [r7, #4] + 8012eb4: f7fa fa62 bl 800d37c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + 8012eb8: e09c b.n 8012ff4 + 8012eba: bf00 nop + 8012ebc: 0801316d .word 0x0801316d + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + 8012ec0: 687b ldr r3, [r7, #4] + 8012ec2: 8d9a ldrh r2, [r3, #44] @ 0x2c + 8012ec4: 687b ldr r3, [r7, #4] + 8012ec6: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8012ec8: b29b uxth r3, r3 + 8012eca: 1ad3 subs r3, r2, r3 + 8012ecc: f8a7 30ce strh.w r3, [r7, #206] @ 0xce + if ((huart->RxXferCount > 0U) + 8012ed0: 687b ldr r3, [r7, #4] + 8012ed2: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8012ed4: b29b uxth r3, r3 + 8012ed6: 2b00 cmp r3, #0 + 8012ed8: f000 808e beq.w 8012ff8 + && (nb_rx_data > 0U)) + 8012edc: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8012ee0: 2b00 cmp r3, #0 + 8012ee2: f000 8089 beq.w 8012ff8 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8012ee6: 687b ldr r3, [r7, #4] + 8012ee8: 681b ldr r3, [r3, #0] + 8012eea: 330c adds r3, #12 + 8012eec: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012eee: 6bbb ldr r3, [r7, #56] @ 0x38 + 8012ef0: e853 3f00 ldrex r3, [r3] + 8012ef4: 637b str r3, [r7, #52] @ 0x34 + return(result); + 8012ef6: 6b7b ldr r3, [r7, #52] @ 0x34 + 8012ef8: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8012efc: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 8012f00: 687b ldr r3, [r7, #4] + 8012f02: 681b ldr r3, [r3, #0] + 8012f04: 330c adds r3, #12 + 8012f06: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 + 8012f0a: 647a str r2, [r7, #68] @ 0x44 + 8012f0c: 643b str r3, [r7, #64] @ 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012f0e: 6c39 ldr r1, [r7, #64] @ 0x40 + 8012f10: 6c7a ldr r2, [r7, #68] @ 0x44 + 8012f12: e841 2300 strex r3, r2, [r1] + 8012f16: 63fb str r3, [r7, #60] @ 0x3c + return(result); + 8012f18: 6bfb ldr r3, [r7, #60] @ 0x3c + 8012f1a: 2b00 cmp r3, #0 + 8012f1c: d1e3 bne.n 8012ee6 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8012f1e: 687b ldr r3, [r7, #4] + 8012f20: 681b ldr r3, [r3, #0] + 8012f22: 3314 adds r3, #20 + 8012f24: 627b str r3, [r7, #36] @ 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012f26: 6a7b ldr r3, [r7, #36] @ 0x24 + 8012f28: e853 3f00 ldrex r3, [r3] + 8012f2c: 623b str r3, [r7, #32] + return(result); + 8012f2e: 6a3b ldr r3, [r7, #32] + 8012f30: f023 0301 bic.w r3, r3, #1 + 8012f34: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + 8012f38: 687b ldr r3, [r7, #4] + 8012f3a: 681b ldr r3, [r3, #0] + 8012f3c: 3314 adds r3, #20 + 8012f3e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 + 8012f42: 633a str r2, [r7, #48] @ 0x30 + 8012f44: 62fb str r3, [r7, #44] @ 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012f46: 6af9 ldr r1, [r7, #44] @ 0x2c + 8012f48: 6b3a ldr r2, [r7, #48] @ 0x30 + 8012f4a: e841 2300 strex r3, r2, [r1] + 8012f4e: 62bb str r3, [r7, #40] @ 0x28 + return(result); + 8012f50: 6abb ldr r3, [r7, #40] @ 0x28 + 8012f52: 2b00 cmp r3, #0 + 8012f54: d1e3 bne.n 8012f1e + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8012f56: 687b ldr r3, [r7, #4] + 8012f58: 2220 movs r2, #32 + 8012f5a: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8012f5e: 687b ldr r3, [r7, #4] + 8012f60: 2200 movs r2, #0 + 8012f62: 631a str r2, [r3, #48] @ 0x30 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8012f64: 687b ldr r3, [r7, #4] + 8012f66: 681b ldr r3, [r3, #0] + 8012f68: 330c adds r3, #12 + 8012f6a: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8012f6c: 693b ldr r3, [r7, #16] + 8012f6e: e853 3f00 ldrex r3, [r3] + 8012f72: 60fb str r3, [r7, #12] + return(result); + 8012f74: 68fb ldr r3, [r7, #12] + 8012f76: f023 0310 bic.w r3, r3, #16 + 8012f7a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8012f7e: 687b ldr r3, [r7, #4] + 8012f80: 681b ldr r3, [r3, #0] + 8012f82: 330c adds r3, #12 + 8012f84: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 + 8012f88: 61fa str r2, [r7, #28] + 8012f8a: 61bb str r3, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8012f8c: 69b9 ldr r1, [r7, #24] + 8012f8e: 69fa ldr r2, [r7, #28] + 8012f90: e841 2300 strex r3, r2, [r1] + 8012f94: 617b str r3, [r7, #20] + return(result); + 8012f96: 697b ldr r3, [r7, #20] + 8012f98: 2b00 cmp r3, #0 + 8012f9a: d1e3 bne.n 8012f64 + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 8012f9c: 687b ldr r3, [r7, #4] + 8012f9e: 2202 movs r2, #2 + 8012fa0: 635a str r2, [r3, #52] @ 0x34 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); + 8012fa2: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8012fa6: 4619 mov r1, r3 + 8012fa8: 6878 ldr r0, [r7, #4] + 8012faa: f7fa f9e7 bl 800d37c +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + 8012fae: e023 b.n 8012ff8 + } + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + 8012fb0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012fb4: f003 0380 and.w r3, r3, #128 @ 0x80 + 8012fb8: 2b00 cmp r3, #0 + 8012fba: d009 beq.n 8012fd0 + 8012fbc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012fc0: f003 0380 and.w r3, r3, #128 @ 0x80 + 8012fc4: 2b00 cmp r3, #0 + 8012fc6: d003 beq.n 8012fd0 + { + UART_Transmit_IT(huart); + 8012fc8: 6878 ldr r0, [r7, #4] + 8012fca: f000 f943 bl 8013254 + return; + 8012fce: e014 b.n 8012ffa + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + 8012fd0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8012fd4: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012fd8: 2b00 cmp r3, #0 + 8012fda: d00e beq.n 8012ffa + 8012fdc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8012fe0: f003 0340 and.w r3, r3, #64 @ 0x40 + 8012fe4: 2b00 cmp r3, #0 + 8012fe6: d008 beq.n 8012ffa + { + UART_EndTransmit_IT(huart); + 8012fe8: 6878 ldr r0, [r7, #4] + 8012fea: f000 f982 bl 80132f2 + return; + 8012fee: e004 b.n 8012ffa + return; + 8012ff0: bf00 nop + 8012ff2: e002 b.n 8012ffa + return; + 8012ff4: bf00 nop + 8012ff6: e000 b.n 8012ffa + return; + 8012ff8: bf00 nop + } +} + 8012ffa: 37e8 adds r7, #232 @ 0xe8 + 8012ffc: 46bd mov sp, r7 + 8012ffe: bd80 pop {r7, pc} + +08013000 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + 8013000: b480 push {r7} + 8013002: b083 sub sp, #12 + 8013004: af00 add r7, sp, #0 + 8013006: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + 8013008: bf00 nop + 801300a: 370c adds r7, #12 + 801300c: 46bd mov sp, r7 + 801300e: bc80 pop {r7} + 8013010: 4770 bx lr + +08013012 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8013012: b480 push {r7} + 8013014: b083 sub sp, #12 + 8013016: af00 add r7, sp, #0 + 8013018: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + 801301a: bf00 nop + 801301c: 370c adds r7, #12 + 801301e: 46bd mov sp, r7 + 8013020: bc80 pop {r7} + 8013022: 4770 bx lr + +08013024 : + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + 8013024: b480 push {r7} + 8013026: b083 sub sp, #12 + 8013028: af00 add r7, sp, #0 + 801302a: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + 801302c: bf00 nop + 801302e: 370c adds r7, #12 + 8013030: 46bd mov sp, r7 + 8013032: bc80 pop {r7} + 8013034: 4770 bx lr + +08013036 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8013036: b480 push {r7} + 8013038: b085 sub sp, #20 + 801303a: af00 add r7, sp, #0 + 801303c: 60f8 str r0, [r7, #12] + 801303e: 60b9 str r1, [r7, #8] + 8013040: 4613 mov r3, r2 + 8013042: 80fb strh r3, [r7, #6] + huart->pRxBuffPtr = pData; + 8013044: 68fb ldr r3, [r7, #12] + 8013046: 68ba ldr r2, [r7, #8] + 8013048: 629a str r2, [r3, #40] @ 0x28 + huart->RxXferSize = Size; + 801304a: 68fb ldr r3, [r7, #12] + 801304c: 88fa ldrh r2, [r7, #6] + 801304e: 859a strh r2, [r3, #44] @ 0x2c + huart->RxXferCount = Size; + 8013050: 68fb ldr r3, [r7, #12] + 8013052: 88fa ldrh r2, [r7, #6] + 8013054: 85da strh r2, [r3, #46] @ 0x2e + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8013056: 68fb ldr r3, [r7, #12] + 8013058: 2200 movs r2, #0 + 801305a: 645a str r2, [r3, #68] @ 0x44 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 801305c: 68fb ldr r3, [r7, #12] + 801305e: 2222 movs r2, #34 @ 0x22 + 8013060: f883 2042 strb.w r2, [r3, #66] @ 0x42 + + if (huart->Init.Parity != UART_PARITY_NONE) + 8013064: 68fb ldr r3, [r7, #12] + 8013066: 691b ldr r3, [r3, #16] + 8013068: 2b00 cmp r3, #0 + 801306a: d007 beq.n 801307c + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + 801306c: 68fb ldr r3, [r7, #12] + 801306e: 681b ldr r3, [r3, #0] + 8013070: 68da ldr r2, [r3, #12] + 8013072: 68fb ldr r3, [r7, #12] + 8013074: 681b ldr r3, [r3, #0] + 8013076: f442 7280 orr.w r2, r2, #256 @ 0x100 + 801307a: 60da str r2, [r3, #12] + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + 801307c: 68fb ldr r3, [r7, #12] + 801307e: 681b ldr r3, [r3, #0] + 8013080: 695a ldr r2, [r3, #20] + 8013082: 68fb ldr r3, [r7, #12] + 8013084: 681b ldr r3, [r3, #0] + 8013086: f042 0201 orr.w r2, r2, #1 + 801308a: 615a str r2, [r3, #20] + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + 801308c: 68fb ldr r3, [r7, #12] + 801308e: 681b ldr r3, [r3, #0] + 8013090: 68da ldr r2, [r3, #12] + 8013092: 68fb ldr r3, [r7, #12] + 8013094: 681b ldr r3, [r3, #0] + 8013096: f042 0220 orr.w r2, r2, #32 + 801309a: 60da str r2, [r3, #12] + + return HAL_OK; + 801309c: 2300 movs r3, #0 +} + 801309e: 4618 mov r0, r3 + 80130a0: 3714 adds r7, #20 + 80130a2: 46bd mov sp, r7 + 80130a4: bc80 pop {r7} + 80130a6: 4770 bx lr + +080130a8 : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 80130a8: b480 push {r7} + 80130aa: b095 sub sp, #84 @ 0x54 + 80130ac: af00 add r7, sp, #0 + 80130ae: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 80130b0: 687b ldr r3, [r7, #4] + 80130b2: 681b ldr r3, [r3, #0] + 80130b4: 330c adds r3, #12 + 80130b6: 637b str r3, [r7, #52] @ 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80130b8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80130ba: e853 3f00 ldrex r3, [r3] + 80130be: 633b str r3, [r7, #48] @ 0x30 + return(result); + 80130c0: 6b3b ldr r3, [r7, #48] @ 0x30 + 80130c2: f423 7390 bic.w r3, r3, #288 @ 0x120 + 80130c6: 64fb str r3, [r7, #76] @ 0x4c + 80130c8: 687b ldr r3, [r7, #4] + 80130ca: 681b ldr r3, [r3, #0] + 80130cc: 330c adds r3, #12 + 80130ce: 6cfa ldr r2, [r7, #76] @ 0x4c + 80130d0: 643a str r2, [r7, #64] @ 0x40 + 80130d2: 63fb str r3, [r7, #60] @ 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80130d4: 6bf9 ldr r1, [r7, #60] @ 0x3c + 80130d6: 6c3a ldr r2, [r7, #64] @ 0x40 + 80130d8: e841 2300 strex r3, r2, [r1] + 80130dc: 63bb str r3, [r7, #56] @ 0x38 + return(result); + 80130de: 6bbb ldr r3, [r7, #56] @ 0x38 + 80130e0: 2b00 cmp r3, #0 + 80130e2: d1e5 bne.n 80130b0 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80130e4: 687b ldr r3, [r7, #4] + 80130e6: 681b ldr r3, [r3, #0] + 80130e8: 3314 adds r3, #20 + 80130ea: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80130ec: 6a3b ldr r3, [r7, #32] + 80130ee: e853 3f00 ldrex r3, [r3] + 80130f2: 61fb str r3, [r7, #28] + return(result); + 80130f4: 69fb ldr r3, [r7, #28] + 80130f6: f023 0301 bic.w r3, r3, #1 + 80130fa: 64bb str r3, [r7, #72] @ 0x48 + 80130fc: 687b ldr r3, [r7, #4] + 80130fe: 681b ldr r3, [r3, #0] + 8013100: 3314 adds r3, #20 + 8013102: 6cba ldr r2, [r7, #72] @ 0x48 + 8013104: 62fa str r2, [r7, #44] @ 0x2c + 8013106: 62bb str r3, [r7, #40] @ 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8013108: 6ab9 ldr r1, [r7, #40] @ 0x28 + 801310a: 6afa ldr r2, [r7, #44] @ 0x2c + 801310c: e841 2300 strex r3, r2, [r1] + 8013110: 627b str r3, [r7, #36] @ 0x24 + return(result); + 8013112: 6a7b ldr r3, [r7, #36] @ 0x24 + 8013114: 2b00 cmp r3, #0 + 8013116: d1e5 bne.n 80130e4 + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8013118: 687b ldr r3, [r7, #4] + 801311a: 6b1b ldr r3, [r3, #48] @ 0x30 + 801311c: 2b01 cmp r3, #1 + 801311e: d119 bne.n 8013154 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8013120: 687b ldr r3, [r7, #4] + 8013122: 681b ldr r3, [r3, #0] + 8013124: 330c adds r3, #12 + 8013126: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8013128: 68fb ldr r3, [r7, #12] + 801312a: e853 3f00 ldrex r3, [r3] + 801312e: 60bb str r3, [r7, #8] + return(result); + 8013130: 68bb ldr r3, [r7, #8] + 8013132: f023 0310 bic.w r3, r3, #16 + 8013136: 647b str r3, [r7, #68] @ 0x44 + 8013138: 687b ldr r3, [r7, #4] + 801313a: 681b ldr r3, [r3, #0] + 801313c: 330c adds r3, #12 + 801313e: 6c7a ldr r2, [r7, #68] @ 0x44 + 8013140: 61ba str r2, [r7, #24] + 8013142: 617b str r3, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8013144: 6979 ldr r1, [r7, #20] + 8013146: 69ba ldr r2, [r7, #24] + 8013148: e841 2300 strex r3, r2, [r1] + 801314c: 613b str r3, [r7, #16] + return(result); + 801314e: 693b ldr r3, [r7, #16] + 8013150: 2b00 cmp r3, #0 + 8013152: d1e5 bne.n 8013120 + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8013154: 687b ldr r3, [r7, #4] + 8013156: 2220 movs r2, #32 + 8013158: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 801315c: 687b ldr r3, [r7, #4] + 801315e: 2200 movs r2, #0 + 8013160: 631a str r2, [r3, #48] @ 0x30 +} + 8013162: bf00 nop + 8013164: 3754 adds r7, #84 @ 0x54 + 8013166: 46bd mov sp, r7 + 8013168: bc80 pop {r7} + 801316a: 4770 bx lr + +0801316c : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 801316c: b580 push {r7, lr} + 801316e: b084 sub sp, #16 + 8013170: af00 add r7, sp, #0 + 8013172: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 8013174: 687b ldr r3, [r7, #4] + 8013176: 6a5b ldr r3, [r3, #36] @ 0x24 + 8013178: 60fb str r3, [r7, #12] + huart->RxXferCount = 0x00U; + 801317a: 68fb ldr r3, [r7, #12] + 801317c: 2200 movs r2, #0 + 801317e: 85da strh r2, [r3, #46] @ 0x2e + huart->TxXferCount = 0x00U; + 8013180: 68fb ldr r3, [r7, #12] + 8013182: 2200 movs r2, #0 + 8013184: 84da strh r2, [r3, #38] @ 0x26 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8013186: 68f8 ldr r0, [r7, #12] + 8013188: f7ff ff43 bl 8013012 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 801318c: bf00 nop + 801318e: 3710 adds r7, #16 + 8013190: 46bd mov sp, r7 + 8013192: bd80 pop {r7, pc} + +08013194 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + 8013194: b580 push {r7, lr} + 8013196: b084 sub sp, #16 + 8013198: af00 add r7, sp, #0 + 801319a: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 801319c: 687b ldr r3, [r7, #4] + 801319e: 6a5b ldr r3, [r3, #36] @ 0x24 + 80131a0: 60fb str r3, [r7, #12] + + huart->hdmatx->XferAbortCallback = NULL; + 80131a2: 68fb ldr r3, [r7, #12] + 80131a4: 6b9b ldr r3, [r3, #56] @ 0x38 + 80131a6: 2200 movs r2, #0 + 80131a8: 635a str r2, [r3, #52] @ 0x34 + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + 80131aa: 68fb ldr r3, [r7, #12] + 80131ac: 6bdb ldr r3, [r3, #60] @ 0x3c + 80131ae: 2b00 cmp r3, #0 + 80131b0: d004 beq.n 80131bc + { + if (huart->hdmarx->XferAbortCallback != NULL) + 80131b2: 68fb ldr r3, [r7, #12] + 80131b4: 6bdb ldr r3, [r3, #60] @ 0x3c + 80131b6: 6b5b ldr r3, [r3, #52] @ 0x34 + 80131b8: 2b00 cmp r3, #0 + 80131ba: d117 bne.n 80131ec + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + 80131bc: 68fb ldr r3, [r7, #12] + 80131be: 2200 movs r2, #0 + 80131c0: 84da strh r2, [r3, #38] @ 0x26 + huart->RxXferCount = 0x00U; + 80131c2: 68fb ldr r3, [r7, #12] + 80131c4: 2200 movs r2, #0 + 80131c6: 85da strh r2, [r3, #46] @ 0x2e + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80131c8: 68fb ldr r3, [r7, #12] + 80131ca: 2200 movs r2, #0 + 80131cc: 645a str r2, [r3, #68] @ 0x44 + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 80131ce: 68fb ldr r3, [r7, #12] + 80131d0: 2220 movs r2, #32 + 80131d2: f883 2041 strb.w r2, [r3, #65] @ 0x41 + huart->RxState = HAL_UART_STATE_READY; + 80131d6: 68fb ldr r3, [r7, #12] + 80131d8: 2220 movs r2, #32 + 80131da: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80131de: 68fb ldr r3, [r7, #12] + 80131e0: 2200 movs r2, #0 + 80131e2: 631a str r2, [r3, #48] @ 0x30 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); + 80131e4: 68f8 ldr r0, [r7, #12] + 80131e6: f7ff ff1d bl 8013024 + 80131ea: e000 b.n 80131ee + return; + 80131ec: bf00 nop +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80131ee: 3710 adds r7, #16 + 80131f0: 46bd mov sp, r7 + 80131f2: bd80 pop {r7, pc} + +080131f4 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + 80131f4: b580 push {r7, lr} + 80131f6: b084 sub sp, #16 + 80131f8: af00 add r7, sp, #0 + 80131fa: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 80131fc: 687b ldr r3, [r7, #4] + 80131fe: 6a5b ldr r3, [r3, #36] @ 0x24 + 8013200: 60fb str r3, [r7, #12] + + huart->hdmarx->XferAbortCallback = NULL; + 8013202: 68fb ldr r3, [r7, #12] + 8013204: 6bdb ldr r3, [r3, #60] @ 0x3c + 8013206: 2200 movs r2, #0 + 8013208: 635a str r2, [r3, #52] @ 0x34 + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + 801320a: 68fb ldr r3, [r7, #12] + 801320c: 6b9b ldr r3, [r3, #56] @ 0x38 + 801320e: 2b00 cmp r3, #0 + 8013210: d004 beq.n 801321c + { + if (huart->hdmatx->XferAbortCallback != NULL) + 8013212: 68fb ldr r3, [r7, #12] + 8013214: 6b9b ldr r3, [r3, #56] @ 0x38 + 8013216: 6b5b ldr r3, [r3, #52] @ 0x34 + 8013218: 2b00 cmp r3, #0 + 801321a: d117 bne.n 801324c + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + 801321c: 68fb ldr r3, [r7, #12] + 801321e: 2200 movs r2, #0 + 8013220: 84da strh r2, [r3, #38] @ 0x26 + huart->RxXferCount = 0x00U; + 8013222: 68fb ldr r3, [r7, #12] + 8013224: 2200 movs r2, #0 + 8013226: 85da strh r2, [r3, #46] @ 0x2e + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8013228: 68fb ldr r3, [r7, #12] + 801322a: 2200 movs r2, #0 + 801322c: 645a str r2, [r3, #68] @ 0x44 + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 801322e: 68fb ldr r3, [r7, #12] + 8013230: 2220 movs r2, #32 + 8013232: f883 2041 strb.w r2, [r3, #65] @ 0x41 + huart->RxState = HAL_UART_STATE_READY; + 8013236: 68fb ldr r3, [r7, #12] + 8013238: 2220 movs r2, #32 + 801323a: f883 2042 strb.w r2, [r3, #66] @ 0x42 + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 801323e: 68fb ldr r3, [r7, #12] + 8013240: 2200 movs r2, #0 + 8013242: 631a str r2, [r3, #48] @ 0x30 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); + 8013244: 68f8 ldr r0, [r7, #12] + 8013246: f7ff feed bl 8013024 + 801324a: e000 b.n 801324e + return; + 801324c: bf00 nop +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 801324e: 3710 adds r7, #16 + 8013250: 46bd mov sp, r7 + 8013252: bd80 pop {r7, pc} + +08013254 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + 8013254: b480 push {r7} + 8013256: b085 sub sp, #20 + 8013258: af00 add r7, sp, #0 + 801325a: 6078 str r0, [r7, #4] + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + 801325c: 687b ldr r3, [r7, #4] + 801325e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8013262: b2db uxtb r3, r3 + 8013264: 2b21 cmp r3, #33 @ 0x21 + 8013266: d13e bne.n 80132e6 + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8013268: 687b ldr r3, [r7, #4] + 801326a: 689b ldr r3, [r3, #8] + 801326c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8013270: d114 bne.n 801329c + 8013272: 687b ldr r3, [r7, #4] + 8013274: 691b ldr r3, [r3, #16] + 8013276: 2b00 cmp r3, #0 + 8013278: d110 bne.n 801329c + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + 801327a: 687b ldr r3, [r7, #4] + 801327c: 6a1b ldr r3, [r3, #32] + 801327e: 60fb str r3, [r7, #12] + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + 8013280: 68fb ldr r3, [r7, #12] + 8013282: 881b ldrh r3, [r3, #0] + 8013284: 461a mov r2, r3 + 8013286: 687b ldr r3, [r7, #4] + 8013288: 681b ldr r3, [r3, #0] + 801328a: f3c2 0208 ubfx r2, r2, #0, #9 + 801328e: 605a str r2, [r3, #4] + huart->pTxBuffPtr += 2U; + 8013290: 687b ldr r3, [r7, #4] + 8013292: 6a1b ldr r3, [r3, #32] + 8013294: 1c9a adds r2, r3, #2 + 8013296: 687b ldr r3, [r7, #4] + 8013298: 621a str r2, [r3, #32] + 801329a: e008 b.n 80132ae + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + 801329c: 687b ldr r3, [r7, #4] + 801329e: 6a1b ldr r3, [r3, #32] + 80132a0: 1c59 adds r1, r3, #1 + 80132a2: 687a ldr r2, [r7, #4] + 80132a4: 6211 str r1, [r2, #32] + 80132a6: 781a ldrb r2, [r3, #0] + 80132a8: 687b ldr r3, [r7, #4] + 80132aa: 681b ldr r3, [r3, #0] + 80132ac: 605a str r2, [r3, #4] + } + + if (--huart->TxXferCount == 0U) + 80132ae: 687b ldr r3, [r7, #4] + 80132b0: 8cdb ldrh r3, [r3, #38] @ 0x26 + 80132b2: b29b uxth r3, r3 + 80132b4: 3b01 subs r3, #1 + 80132b6: b29b uxth r3, r3 + 80132b8: 687a ldr r2, [r7, #4] + 80132ba: 4619 mov r1, r3 + 80132bc: 84d1 strh r1, [r2, #38] @ 0x26 + 80132be: 2b00 cmp r3, #0 + 80132c0: d10f bne.n 80132e2 + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + 80132c2: 687b ldr r3, [r7, #4] + 80132c4: 681b ldr r3, [r3, #0] + 80132c6: 68da ldr r2, [r3, #12] + 80132c8: 687b ldr r3, [r7, #4] + 80132ca: 681b ldr r3, [r3, #0] + 80132cc: f022 0280 bic.w r2, r2, #128 @ 0x80 + 80132d0: 60da str r2, [r3, #12] + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + 80132d2: 687b ldr r3, [r7, #4] + 80132d4: 681b ldr r3, [r3, #0] + 80132d6: 68da ldr r2, [r3, #12] + 80132d8: 687b ldr r3, [r7, #4] + 80132da: 681b ldr r3, [r3, #0] + 80132dc: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80132e0: 60da str r2, [r3, #12] + } + return HAL_OK; + 80132e2: 2300 movs r3, #0 + 80132e4: e000 b.n 80132e8 + } + else + { + return HAL_BUSY; + 80132e6: 2302 movs r3, #2 + } +} + 80132e8: 4618 mov r0, r3 + 80132ea: 3714 adds r7, #20 + 80132ec: 46bd mov sp, r7 + 80132ee: bc80 pop {r7} + 80132f0: 4770 bx lr + +080132f2 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 80132f2: b580 push {r7, lr} + 80132f4: b082 sub sp, #8 + 80132f6: af00 add r7, sp, #0 + 80132f8: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + 80132fa: 687b ldr r3, [r7, #4] + 80132fc: 681b ldr r3, [r3, #0] + 80132fe: 68da ldr r2, [r3, #12] + 8013300: 687b ldr r3, [r7, #4] + 8013302: 681b ldr r3, [r3, #0] + 8013304: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8013308: 60da str r2, [r3, #12] + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 801330a: 687b ldr r3, [r7, #4] + 801330c: 2220 movs r2, #32 + 801330e: f883 2041 strb.w r2, [r3, #65] @ 0x41 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 8013312: 6878 ldr r0, [r7, #4] + 8013314: f7fa f854 bl 800d3c0 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; + 8013318: 2300 movs r3, #0 +} + 801331a: 4618 mov r0, r3 + 801331c: 3708 adds r7, #8 + 801331e: 46bd mov sp, r7 + 8013320: bd80 pop {r7, pc} + +08013322 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + 8013322: b580 push {r7, lr} + 8013324: b08c sub sp, #48 @ 0x30 + 8013326: af00 add r7, sp, #0 + 8013328: 6078 str r0, [r7, #4] + uint8_t *pdata8bits; + uint16_t *pdata16bits; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 801332a: 687b ldr r3, [r7, #4] + 801332c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 8013330: b2db uxtb r3, r3 + 8013332: 2b22 cmp r3, #34 @ 0x22 + 8013334: f040 80ae bne.w 8013494 + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8013338: 687b ldr r3, [r7, #4] + 801333a: 689b ldr r3, [r3, #8] + 801333c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8013340: d117 bne.n 8013372 + 8013342: 687b ldr r3, [r7, #4] + 8013344: 691b ldr r3, [r3, #16] + 8013346: 2b00 cmp r3, #0 + 8013348: d113 bne.n 8013372 + { + pdata8bits = NULL; + 801334a: 2300 movs r3, #0 + 801334c: 62fb str r3, [r7, #44] @ 0x2c + pdata16bits = (uint16_t *) huart->pRxBuffPtr; + 801334e: 687b ldr r3, [r7, #4] + 8013350: 6a9b ldr r3, [r3, #40] @ 0x28 + 8013352: 62bb str r3, [r7, #40] @ 0x28 + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + 8013354: 687b ldr r3, [r7, #4] + 8013356: 681b ldr r3, [r3, #0] + 8013358: 685b ldr r3, [r3, #4] + 801335a: b29b uxth r3, r3 + 801335c: f3c3 0308 ubfx r3, r3, #0, #9 + 8013360: b29a uxth r2, r3 + 8013362: 6abb ldr r3, [r7, #40] @ 0x28 + 8013364: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 8013366: 687b ldr r3, [r7, #4] + 8013368: 6a9b ldr r3, [r3, #40] @ 0x28 + 801336a: 1c9a adds r2, r3, #2 + 801336c: 687b ldr r3, [r7, #4] + 801336e: 629a str r2, [r3, #40] @ 0x28 + 8013370: e026 b.n 80133c0 + } + else + { + pdata8bits = (uint8_t *) huart->pRxBuffPtr; + 8013372: 687b ldr r3, [r7, #4] + 8013374: 6a9b ldr r3, [r3, #40] @ 0x28 + 8013376: 62fb str r3, [r7, #44] @ 0x2c + pdata16bits = NULL; + 8013378: 2300 movs r3, #0 + 801337a: 62bb str r3, [r7, #40] @ 0x28 + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + 801337c: 687b ldr r3, [r7, #4] + 801337e: 689b ldr r3, [r3, #8] + 8013380: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8013384: d007 beq.n 8013396 + 8013386: 687b ldr r3, [r7, #4] + 8013388: 689b ldr r3, [r3, #8] + 801338a: 2b00 cmp r3, #0 + 801338c: d10a bne.n 80133a4 + 801338e: 687b ldr r3, [r7, #4] + 8013390: 691b ldr r3, [r3, #16] + 8013392: 2b00 cmp r3, #0 + 8013394: d106 bne.n 80133a4 + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + 8013396: 687b ldr r3, [r7, #4] + 8013398: 681b ldr r3, [r3, #0] + 801339a: 685b ldr r3, [r3, #4] + 801339c: b2da uxtb r2, r3 + 801339e: 6afb ldr r3, [r7, #44] @ 0x2c + 80133a0: 701a strb r2, [r3, #0] + 80133a2: e008 b.n 80133b6 + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + 80133a4: 687b ldr r3, [r7, #4] + 80133a6: 681b ldr r3, [r3, #0] + 80133a8: 685b ldr r3, [r3, #4] + 80133aa: b2db uxtb r3, r3 + 80133ac: f003 037f and.w r3, r3, #127 @ 0x7f + 80133b0: b2da uxtb r2, r3 + 80133b2: 6afb ldr r3, [r7, #44] @ 0x2c + 80133b4: 701a strb r2, [r3, #0] + } + huart->pRxBuffPtr += 1U; + 80133b6: 687b ldr r3, [r7, #4] + 80133b8: 6a9b ldr r3, [r3, #40] @ 0x28 + 80133ba: 1c5a adds r2, r3, #1 + 80133bc: 687b ldr r3, [r7, #4] + 80133be: 629a str r2, [r3, #40] @ 0x28 + } + + if (--huart->RxXferCount == 0U) + 80133c0: 687b ldr r3, [r7, #4] + 80133c2: 8ddb ldrh r3, [r3, #46] @ 0x2e + 80133c4: b29b uxth r3, r3 + 80133c6: 3b01 subs r3, #1 + 80133c8: b29b uxth r3, r3 + 80133ca: 687a ldr r2, [r7, #4] + 80133cc: 4619 mov r1, r3 + 80133ce: 85d1 strh r1, [r2, #46] @ 0x2e + 80133d0: 2b00 cmp r3, #0 + 80133d2: d15d bne.n 8013490 + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + 80133d4: 687b ldr r3, [r7, #4] + 80133d6: 681b ldr r3, [r3, #0] + 80133d8: 68da ldr r2, [r3, #12] + 80133da: 687b ldr r3, [r7, #4] + 80133dc: 681b ldr r3, [r3, #0] + 80133de: f022 0220 bic.w r2, r2, #32 + 80133e2: 60da str r2, [r3, #12] + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + 80133e4: 687b ldr r3, [r7, #4] + 80133e6: 681b ldr r3, [r3, #0] + 80133e8: 68da ldr r2, [r3, #12] + 80133ea: 687b ldr r3, [r7, #4] + 80133ec: 681b ldr r3, [r3, #0] + 80133ee: f422 7280 bic.w r2, r2, #256 @ 0x100 + 80133f2: 60da str r2, [r3, #12] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + 80133f4: 687b ldr r3, [r7, #4] + 80133f6: 681b ldr r3, [r3, #0] + 80133f8: 695a ldr r2, [r3, #20] + 80133fa: 687b ldr r3, [r7, #4] + 80133fc: 681b ldr r3, [r3, #0] + 80133fe: f022 0201 bic.w r2, r2, #1 + 8013402: 615a str r2, [r3, #20] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8013404: 687b ldr r3, [r7, #4] + 8013406: 2220 movs r2, #32 + 8013408: f883 2042 strb.w r2, [r3, #66] @ 0x42 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 801340c: 687b ldr r3, [r7, #4] + 801340e: 2200 movs r2, #0 + 8013410: 635a str r2, [r3, #52] @ 0x34 + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8013412: 687b ldr r3, [r7, #4] + 8013414: 6b1b ldr r3, [r3, #48] @ 0x30 + 8013416: 2b01 cmp r3, #1 + 8013418: d135 bne.n 8013486 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 801341a: 687b ldr r3, [r7, #4] + 801341c: 2200 movs r2, #0 + 801341e: 631a str r2, [r3, #48] @ 0x30 + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8013420: 687b ldr r3, [r7, #4] + 8013422: 681b ldr r3, [r3, #0] + 8013424: 330c adds r3, #12 + 8013426: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8013428: 697b ldr r3, [r7, #20] + 801342a: e853 3f00 ldrex r3, [r3] + 801342e: 613b str r3, [r7, #16] + return(result); + 8013430: 693b ldr r3, [r7, #16] + 8013432: f023 0310 bic.w r3, r3, #16 + 8013436: 627b str r3, [r7, #36] @ 0x24 + 8013438: 687b ldr r3, [r7, #4] + 801343a: 681b ldr r3, [r3, #0] + 801343c: 330c adds r3, #12 + 801343e: 6a7a ldr r2, [r7, #36] @ 0x24 + 8013440: 623a str r2, [r7, #32] + 8013442: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8013444: 69f9 ldr r1, [r7, #28] + 8013446: 6a3a ldr r2, [r7, #32] + 8013448: e841 2300 strex r3, r2, [r1] + 801344c: 61bb str r3, [r7, #24] + return(result); + 801344e: 69bb ldr r3, [r7, #24] + 8013450: 2b00 cmp r3, #0 + 8013452: d1e5 bne.n 8013420 + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + 8013454: 687b ldr r3, [r7, #4] + 8013456: 681b ldr r3, [r3, #0] + 8013458: 681b ldr r3, [r3, #0] + 801345a: f003 0310 and.w r3, r3, #16 + 801345e: 2b10 cmp r3, #16 + 8013460: d10a bne.n 8013478 + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + 8013462: 2300 movs r3, #0 + 8013464: 60fb str r3, [r7, #12] + 8013466: 687b ldr r3, [r7, #4] + 8013468: 681b ldr r3, [r3, #0] + 801346a: 681b ldr r3, [r3, #0] + 801346c: 60fb str r3, [r7, #12] + 801346e: 687b ldr r3, [r7, #4] + 8013470: 681b ldr r3, [r3, #0] + 8013472: 685b ldr r3, [r3, #4] + 8013474: 60fb str r3, [r7, #12] + 8013476: 68fb ldr r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8013478: 687b ldr r3, [r7, #4] + 801347a: 8d9b ldrh r3, [r3, #44] @ 0x2c + 801347c: 4619 mov r1, r3 + 801347e: 6878 ldr r0, [r7, #4] + 8013480: f7f9 ff7c bl 800d37c + 8013484: e002 b.n 801348c +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 8013486: 6878 ldr r0, [r7, #4] + 8013488: f7ff fdba bl 8013000 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; + 801348c: 2300 movs r3, #0 + 801348e: e002 b.n 8013496 + } + return HAL_OK; + 8013490: 2300 movs r3, #0 + 8013492: e000 b.n 8013496 + } + else + { + return HAL_BUSY; + 8013494: 2302 movs r3, #2 + } +} + 8013496: 4618 mov r0, r3 + 8013498: 3730 adds r7, #48 @ 0x30 + 801349a: 46bd mov sp, r7 + 801349c: bd80 pop {r7, pc} + ... + +080134a0 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + 80134a0: b580 push {r7, lr} + 80134a2: b084 sub sp, #16 + 80134a4: af00 add r7, sp, #0 + 80134a6: 6078 str r0, [r7, #4] + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 80134a8: 687b ldr r3, [r7, #4] + 80134aa: 681b ldr r3, [r3, #0] + 80134ac: 691b ldr r3, [r3, #16] + 80134ae: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 80134b2: 687b ldr r3, [r7, #4] + 80134b4: 68da ldr r2, [r3, #12] + 80134b6: 687b ldr r3, [r7, #4] + 80134b8: 681b ldr r3, [r3, #0] + 80134ba: 430a orrs r2, r1 + 80134bc: 611a str r2, [r3, #16] + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); +#else + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; + 80134be: 687b ldr r3, [r7, #4] + 80134c0: 689a ldr r2, [r3, #8] + 80134c2: 687b ldr r3, [r7, #4] + 80134c4: 691b ldr r3, [r3, #16] + 80134c6: 431a orrs r2, r3 + 80134c8: 687b ldr r3, [r7, #4] + 80134ca: 695b ldr r3, [r3, #20] + 80134cc: 4313 orrs r3, r2 + 80134ce: 60bb str r3, [r7, #8] + MODIFY_REG(huart->Instance->CR1, + 80134d0: 687b ldr r3, [r7, #4] + 80134d2: 681b ldr r3, [r3, #0] + 80134d4: 68db ldr r3, [r3, #12] + 80134d6: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 + 80134da: f023 030c bic.w r3, r3, #12 + 80134de: 687a ldr r2, [r7, #4] + 80134e0: 6812 ldr r2, [r2, #0] + 80134e2: 68b9 ldr r1, [r7, #8] + 80134e4: 430b orrs r3, r1 + 80134e6: 60d3 str r3, [r2, #12] + tmpreg); +#endif /* USART_CR1_OVER8 */ + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + 80134e8: 687b ldr r3, [r7, #4] + 80134ea: 681b ldr r3, [r3, #0] + 80134ec: 695b ldr r3, [r3, #20] + 80134ee: f423 7140 bic.w r1, r3, #768 @ 0x300 + 80134f2: 687b ldr r3, [r7, #4] + 80134f4: 699a ldr r2, [r3, #24] + 80134f6: 687b ldr r3, [r7, #4] + 80134f8: 681b ldr r3, [r3, #0] + 80134fa: 430a orrs r2, r1 + 80134fc: 615a str r2, [r3, #20] + + + if(huart->Instance == USART1) + 80134fe: 687b ldr r3, [r7, #4] + 8013500: 681b ldr r3, [r3, #0] + 8013502: 4a2c ldr r2, [pc, #176] @ (80135b4 ) + 8013504: 4293 cmp r3, r2 + 8013506: d103 bne.n 8013510 + { + pclk = HAL_RCC_GetPCLK2Freq(); + 8013508: f7fd ff38 bl 801137c + 801350c: 60f8 str r0, [r7, #12] + 801350e: e002 b.n 8013516 + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + 8013510: f7fd ff20 bl 8011354 + 8013514: 60f8 str r0, [r7, #12] + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#else + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8013516: 68fa ldr r2, [r7, #12] + 8013518: 4613 mov r3, r2 + 801351a: 009b lsls r3, r3, #2 + 801351c: 4413 add r3, r2 + 801351e: 009a lsls r2, r3, #2 + 8013520: 441a add r2, r3 + 8013522: 687b ldr r3, [r7, #4] + 8013524: 685b ldr r3, [r3, #4] + 8013526: 009b lsls r3, r3, #2 + 8013528: fbb2 f3f3 udiv r3, r2, r3 + 801352c: 4a22 ldr r2, [pc, #136] @ (80135b8 ) + 801352e: fba2 2303 umull r2, r3, r2, r3 + 8013532: 095b lsrs r3, r3, #5 + 8013534: 0119 lsls r1, r3, #4 + 8013536: 68fa ldr r2, [r7, #12] + 8013538: 4613 mov r3, r2 + 801353a: 009b lsls r3, r3, #2 + 801353c: 4413 add r3, r2 + 801353e: 009a lsls r2, r3, #2 + 8013540: 441a add r2, r3 + 8013542: 687b ldr r3, [r7, #4] + 8013544: 685b ldr r3, [r3, #4] + 8013546: 009b lsls r3, r3, #2 + 8013548: fbb2 f2f3 udiv r2, r2, r3 + 801354c: 4b1a ldr r3, [pc, #104] @ (80135b8 ) + 801354e: fba3 0302 umull r0, r3, r3, r2 + 8013552: 095b lsrs r3, r3, #5 + 8013554: 2064 movs r0, #100 @ 0x64 + 8013556: fb00 f303 mul.w r3, r0, r3 + 801355a: 1ad3 subs r3, r2, r3 + 801355c: 011b lsls r3, r3, #4 + 801355e: 3332 adds r3, #50 @ 0x32 + 8013560: 4a15 ldr r2, [pc, #84] @ (80135b8 ) + 8013562: fba2 2303 umull r2, r3, r2, r3 + 8013566: 095b lsrs r3, r3, #5 + 8013568: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 801356c: 4419 add r1, r3 + 801356e: 68fa ldr r2, [r7, #12] + 8013570: 4613 mov r3, r2 + 8013572: 009b lsls r3, r3, #2 + 8013574: 4413 add r3, r2 + 8013576: 009a lsls r2, r3, #2 + 8013578: 441a add r2, r3 + 801357a: 687b ldr r3, [r7, #4] + 801357c: 685b ldr r3, [r3, #4] + 801357e: 009b lsls r3, r3, #2 + 8013580: fbb2 f2f3 udiv r2, r2, r3 + 8013584: 4b0c ldr r3, [pc, #48] @ (80135b8 ) + 8013586: fba3 0302 umull r0, r3, r3, r2 + 801358a: 095b lsrs r3, r3, #5 + 801358c: 2064 movs r0, #100 @ 0x64 + 801358e: fb00 f303 mul.w r3, r0, r3 + 8013592: 1ad3 subs r3, r2, r3 + 8013594: 011b lsls r3, r3, #4 + 8013596: 3332 adds r3, #50 @ 0x32 + 8013598: 4a07 ldr r2, [pc, #28] @ (80135b8 ) + 801359a: fba2 2303 umull r2, r3, r2, r3 + 801359e: 095b lsrs r3, r3, #5 + 80135a0: f003 020f and.w r2, r3, #15 + 80135a4: 687b ldr r3, [r7, #4] + 80135a6: 681b ldr r3, [r3, #0] + 80135a8: 440a add r2, r1 + 80135aa: 609a str r2, [r3, #8] +#endif /* USART_CR1_OVER8 */ +} + 80135ac: bf00 nop + 80135ae: 3710 adds r7, #16 + 80135b0: 46bd mov sp, r7 + 80135b2: bd80 pop {r7, pc} + 80135b4: 40013800 .word 0x40013800 + 80135b8: 51eb851f .word 0x51eb851f + +080135bc <__cvt>: + 80135bc: 2b00 cmp r3, #0 + 80135be: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80135c2: 461d mov r5, r3 + 80135c4: bfbb ittet lt + 80135c6: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 + 80135ca: 461d movlt r5, r3 + 80135cc: 2300 movge r3, #0 + 80135ce: 232d movlt r3, #45 @ 0x2d + 80135d0: b088 sub sp, #32 + 80135d2: 4614 mov r4, r2 + 80135d4: bfb8 it lt + 80135d6: 4614 movlt r4, r2 + 80135d8: 9a12 ldr r2, [sp, #72] @ 0x48 + 80135da: 9e10 ldr r6, [sp, #64] @ 0x40 + 80135dc: 7013 strb r3, [r2, #0] + 80135de: 9b14 ldr r3, [sp, #80] @ 0x50 + 80135e0: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c + 80135e4: f023 0820 bic.w r8, r3, #32 + 80135e8: f1b8 0f46 cmp.w r8, #70 @ 0x46 + 80135ec: d005 beq.n 80135fa <__cvt+0x3e> + 80135ee: f1b8 0f45 cmp.w r8, #69 @ 0x45 + 80135f2: d100 bne.n 80135f6 <__cvt+0x3a> + 80135f4: 3601 adds r6, #1 + 80135f6: 2302 movs r3, #2 + 80135f8: e000 b.n 80135fc <__cvt+0x40> + 80135fa: 2303 movs r3, #3 + 80135fc: aa07 add r2, sp, #28 + 80135fe: 9204 str r2, [sp, #16] + 8013600: aa06 add r2, sp, #24 + 8013602: e9cd a202 strd sl, r2, [sp, #8] + 8013606: e9cd 3600 strd r3, r6, [sp] + 801360a: 4622 mov r2, r4 + 801360c: 462b mov r3, r5 + 801360e: f000 ff03 bl 8014418 <_dtoa_r> + 8013612: f1b8 0f47 cmp.w r8, #71 @ 0x47 + 8013616: 4607 mov r7, r0 + 8013618: d119 bne.n 801364e <__cvt+0x92> + 801361a: 9b11 ldr r3, [sp, #68] @ 0x44 + 801361c: 07db lsls r3, r3, #31 + 801361e: d50e bpl.n 801363e <__cvt+0x82> + 8013620: eb00 0906 add.w r9, r0, r6 + 8013624: 2200 movs r2, #0 + 8013626: 2300 movs r3, #0 + 8013628: 4620 mov r0, r4 + 801362a: 4629 mov r1, r5 + 801362c: f7f5 fa28 bl 8008a80 <__aeabi_dcmpeq> + 8013630: b108 cbz r0, 8013636 <__cvt+0x7a> + 8013632: f8cd 901c str.w r9, [sp, #28] + 8013636: 2230 movs r2, #48 @ 0x30 + 8013638: 9b07 ldr r3, [sp, #28] + 801363a: 454b cmp r3, r9 + 801363c: d31e bcc.n 801367c <__cvt+0xc0> + 801363e: 4638 mov r0, r7 + 8013640: 9b07 ldr r3, [sp, #28] + 8013642: 9a15 ldr r2, [sp, #84] @ 0x54 + 8013644: 1bdb subs r3, r3, r7 + 8013646: 6013 str r3, [r2, #0] + 8013648: b008 add sp, #32 + 801364a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801364e: f1b8 0f46 cmp.w r8, #70 @ 0x46 + 8013652: eb00 0906 add.w r9, r0, r6 + 8013656: d1e5 bne.n 8013624 <__cvt+0x68> + 8013658: 7803 ldrb r3, [r0, #0] + 801365a: 2b30 cmp r3, #48 @ 0x30 + 801365c: d10a bne.n 8013674 <__cvt+0xb8> + 801365e: 2200 movs r2, #0 + 8013660: 2300 movs r3, #0 + 8013662: 4620 mov r0, r4 + 8013664: 4629 mov r1, r5 + 8013666: f7f5 fa0b bl 8008a80 <__aeabi_dcmpeq> + 801366a: b918 cbnz r0, 8013674 <__cvt+0xb8> + 801366c: f1c6 0601 rsb r6, r6, #1 + 8013670: f8ca 6000 str.w r6, [sl] + 8013674: f8da 3000 ldr.w r3, [sl] + 8013678: 4499 add r9, r3 + 801367a: e7d3 b.n 8013624 <__cvt+0x68> + 801367c: 1c59 adds r1, r3, #1 + 801367e: 9107 str r1, [sp, #28] + 8013680: 701a strb r2, [r3, #0] + 8013682: e7d9 b.n 8013638 <__cvt+0x7c> + +08013684 <__exponent>: + 8013684: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8013686: 2900 cmp r1, #0 + 8013688: bfb6 itet lt + 801368a: 232d movlt r3, #45 @ 0x2d + 801368c: 232b movge r3, #43 @ 0x2b + 801368e: 4249 neglt r1, r1 + 8013690: 2909 cmp r1, #9 + 8013692: 7002 strb r2, [r0, #0] + 8013694: 7043 strb r3, [r0, #1] + 8013696: dd29 ble.n 80136ec <__exponent+0x68> + 8013698: f10d 0307 add.w r3, sp, #7 + 801369c: 461d mov r5, r3 + 801369e: 270a movs r7, #10 + 80136a0: fbb1 f6f7 udiv r6, r1, r7 + 80136a4: 461a mov r2, r3 + 80136a6: fb07 1416 mls r4, r7, r6, r1 + 80136aa: 3430 adds r4, #48 @ 0x30 + 80136ac: f802 4c01 strb.w r4, [r2, #-1] + 80136b0: 460c mov r4, r1 + 80136b2: 2c63 cmp r4, #99 @ 0x63 + 80136b4: 4631 mov r1, r6 + 80136b6: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff + 80136ba: dcf1 bgt.n 80136a0 <__exponent+0x1c> + 80136bc: 3130 adds r1, #48 @ 0x30 + 80136be: 1e94 subs r4, r2, #2 + 80136c0: f803 1c01 strb.w r1, [r3, #-1] + 80136c4: 4623 mov r3, r4 + 80136c6: 1c41 adds r1, r0, #1 + 80136c8: 42ab cmp r3, r5 + 80136ca: d30a bcc.n 80136e2 <__exponent+0x5e> + 80136cc: f10d 0309 add.w r3, sp, #9 + 80136d0: 1a9b subs r3, r3, r2 + 80136d2: 42ac cmp r4, r5 + 80136d4: bf88 it hi + 80136d6: 2300 movhi r3, #0 + 80136d8: 3302 adds r3, #2 + 80136da: 4403 add r3, r0 + 80136dc: 1a18 subs r0, r3, r0 + 80136de: b003 add sp, #12 + 80136e0: bdf0 pop {r4, r5, r6, r7, pc} + 80136e2: f813 6b01 ldrb.w r6, [r3], #1 + 80136e6: f801 6f01 strb.w r6, [r1, #1]! + 80136ea: e7ed b.n 80136c8 <__exponent+0x44> + 80136ec: 2330 movs r3, #48 @ 0x30 + 80136ee: 3130 adds r1, #48 @ 0x30 + 80136f0: 7083 strb r3, [r0, #2] + 80136f2: 70c1 strb r1, [r0, #3] + 80136f4: 1d03 adds r3, r0, #4 + 80136f6: e7f1 b.n 80136dc <__exponent+0x58> + +080136f8 <_printf_float>: + 80136f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80136fc: b091 sub sp, #68 @ 0x44 + 80136fe: 460c mov r4, r1 + 8013700: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 + 8013704: 4616 mov r6, r2 + 8013706: 461f mov r7, r3 + 8013708: 4605 mov r5, r0 + 801370a: f000 fdbd bl 8014288 <_localeconv_r> + 801370e: 6803 ldr r3, [r0, #0] + 8013710: 4618 mov r0, r3 + 8013712: 9308 str r3, [sp, #32] + 8013714: f7f4 fd88 bl 8008228 + 8013718: 2300 movs r3, #0 + 801371a: 930e str r3, [sp, #56] @ 0x38 + 801371c: f8d8 3000 ldr.w r3, [r8] + 8013720: 9009 str r0, [sp, #36] @ 0x24 + 8013722: 3307 adds r3, #7 + 8013724: f023 0307 bic.w r3, r3, #7 + 8013728: f103 0208 add.w r2, r3, #8 + 801372c: f894 a018 ldrb.w sl, [r4, #24] + 8013730: f8d4 b000 ldr.w fp, [r4] + 8013734: f8c8 2000 str.w r2, [r8] + 8013738: e9d3 8900 ldrd r8, r9, [r3] + 801373c: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 + 8013740: 930b str r3, [sp, #44] @ 0x2c + 8013742: f8cd 8028 str.w r8, [sp, #40] @ 0x28 + 8013746: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 801374a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 + 801374e: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 + 8013752: 4b9c ldr r3, [pc, #624] @ (80139c4 <_printf_float+0x2cc>) + 8013754: f7f5 f9c6 bl 8008ae4 <__aeabi_dcmpun> + 8013758: bb70 cbnz r0, 80137b8 <_printf_float+0xc0> + 801375a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 + 801375e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8013762: 4b98 ldr r3, [pc, #608] @ (80139c4 <_printf_float+0x2cc>) + 8013764: f7f5 f9a0 bl 8008aa8 <__aeabi_dcmple> + 8013768: bb30 cbnz r0, 80137b8 <_printf_float+0xc0> + 801376a: 2200 movs r2, #0 + 801376c: 2300 movs r3, #0 + 801376e: 4640 mov r0, r8 + 8013770: 4649 mov r1, r9 + 8013772: f7f5 f98f bl 8008a94 <__aeabi_dcmplt> + 8013776: b110 cbz r0, 801377e <_printf_float+0x86> + 8013778: 232d movs r3, #45 @ 0x2d + 801377a: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 801377e: 4a92 ldr r2, [pc, #584] @ (80139c8 <_printf_float+0x2d0>) + 8013780: 4b92 ldr r3, [pc, #584] @ (80139cc <_printf_float+0x2d4>) + 8013782: f1ba 0f47 cmp.w sl, #71 @ 0x47 + 8013786: bf8c ite hi + 8013788: 4690 movhi r8, r2 + 801378a: 4698 movls r8, r3 + 801378c: 2303 movs r3, #3 + 801378e: f04f 0900 mov.w r9, #0 + 8013792: 6123 str r3, [r4, #16] + 8013794: f02b 0304 bic.w r3, fp, #4 + 8013798: 6023 str r3, [r4, #0] + 801379a: 4633 mov r3, r6 + 801379c: 4621 mov r1, r4 + 801379e: 4628 mov r0, r5 + 80137a0: 9700 str r7, [sp, #0] + 80137a2: aa0f add r2, sp, #60 @ 0x3c + 80137a4: f000 f9d4 bl 8013b50 <_printf_common> + 80137a8: 3001 adds r0, #1 + 80137aa: f040 8090 bne.w 80138ce <_printf_float+0x1d6> + 80137ae: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80137b2: b011 add sp, #68 @ 0x44 + 80137b4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80137b8: 4642 mov r2, r8 + 80137ba: 464b mov r3, r9 + 80137bc: 4640 mov r0, r8 + 80137be: 4649 mov r1, r9 + 80137c0: f7f5 f990 bl 8008ae4 <__aeabi_dcmpun> + 80137c4: b148 cbz r0, 80137da <_printf_float+0xe2> + 80137c6: 464b mov r3, r9 + 80137c8: 2b00 cmp r3, #0 + 80137ca: bfb8 it lt + 80137cc: 232d movlt r3, #45 @ 0x2d + 80137ce: 4a80 ldr r2, [pc, #512] @ (80139d0 <_printf_float+0x2d8>) + 80137d0: bfb8 it lt + 80137d2: f884 3043 strblt.w r3, [r4, #67] @ 0x43 + 80137d6: 4b7f ldr r3, [pc, #508] @ (80139d4 <_printf_float+0x2dc>) + 80137d8: e7d3 b.n 8013782 <_printf_float+0x8a> + 80137da: 6863 ldr r3, [r4, #4] + 80137dc: f00a 01df and.w r1, sl, #223 @ 0xdf + 80137e0: 1c5a adds r2, r3, #1 + 80137e2: d13f bne.n 8013864 <_printf_float+0x16c> + 80137e4: 2306 movs r3, #6 + 80137e6: 6063 str r3, [r4, #4] + 80137e8: 2200 movs r2, #0 + 80137ea: f44b 6380 orr.w r3, fp, #1024 @ 0x400 + 80137ee: 6023 str r3, [r4, #0] + 80137f0: 9206 str r2, [sp, #24] + 80137f2: aa0e add r2, sp, #56 @ 0x38 + 80137f4: e9cd a204 strd sl, r2, [sp, #16] + 80137f8: aa0d add r2, sp, #52 @ 0x34 + 80137fa: 9203 str r2, [sp, #12] + 80137fc: f10d 0233 add.w r2, sp, #51 @ 0x33 + 8013800: e9cd 3201 strd r3, r2, [sp, #4] + 8013804: 6863 ldr r3, [r4, #4] + 8013806: 4642 mov r2, r8 + 8013808: 9300 str r3, [sp, #0] + 801380a: 4628 mov r0, r5 + 801380c: 464b mov r3, r9 + 801380e: 910a str r1, [sp, #40] @ 0x28 + 8013810: f7ff fed4 bl 80135bc <__cvt> + 8013814: 990a ldr r1, [sp, #40] @ 0x28 + 8013816: 4680 mov r8, r0 + 8013818: 2947 cmp r1, #71 @ 0x47 + 801381a: 990d ldr r1, [sp, #52] @ 0x34 + 801381c: d128 bne.n 8013870 <_printf_float+0x178> + 801381e: 1cc8 adds r0, r1, #3 + 8013820: db02 blt.n 8013828 <_printf_float+0x130> + 8013822: 6863 ldr r3, [r4, #4] + 8013824: 4299 cmp r1, r3 + 8013826: dd40 ble.n 80138aa <_printf_float+0x1b2> + 8013828: f1aa 0a02 sub.w sl, sl, #2 + 801382c: fa5f fa8a uxtb.w sl, sl + 8013830: 4652 mov r2, sl + 8013832: 3901 subs r1, #1 + 8013834: f104 0050 add.w r0, r4, #80 @ 0x50 + 8013838: 910d str r1, [sp, #52] @ 0x34 + 801383a: f7ff ff23 bl 8013684 <__exponent> + 801383e: 9a0e ldr r2, [sp, #56] @ 0x38 + 8013840: 4681 mov r9, r0 + 8013842: 1813 adds r3, r2, r0 + 8013844: 2a01 cmp r2, #1 + 8013846: 6123 str r3, [r4, #16] + 8013848: dc02 bgt.n 8013850 <_printf_float+0x158> + 801384a: 6822 ldr r2, [r4, #0] + 801384c: 07d2 lsls r2, r2, #31 + 801384e: d501 bpl.n 8013854 <_printf_float+0x15c> + 8013850: 3301 adds r3, #1 + 8013852: 6123 str r3, [r4, #16] + 8013854: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 + 8013858: 2b00 cmp r3, #0 + 801385a: d09e beq.n 801379a <_printf_float+0xa2> + 801385c: 232d movs r3, #45 @ 0x2d + 801385e: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 8013862: e79a b.n 801379a <_printf_float+0xa2> + 8013864: 2947 cmp r1, #71 @ 0x47 + 8013866: d1bf bne.n 80137e8 <_printf_float+0xf0> + 8013868: 2b00 cmp r3, #0 + 801386a: d1bd bne.n 80137e8 <_printf_float+0xf0> + 801386c: 2301 movs r3, #1 + 801386e: e7ba b.n 80137e6 <_printf_float+0xee> + 8013870: f1ba 0f65 cmp.w sl, #101 @ 0x65 + 8013874: d9dc bls.n 8013830 <_printf_float+0x138> + 8013876: f1ba 0f66 cmp.w sl, #102 @ 0x66 + 801387a: d118 bne.n 80138ae <_printf_float+0x1b6> + 801387c: 2900 cmp r1, #0 + 801387e: 6863 ldr r3, [r4, #4] + 8013880: dd0b ble.n 801389a <_printf_float+0x1a2> + 8013882: 6121 str r1, [r4, #16] + 8013884: b913 cbnz r3, 801388c <_printf_float+0x194> + 8013886: 6822 ldr r2, [r4, #0] + 8013888: 07d0 lsls r0, r2, #31 + 801388a: d502 bpl.n 8013892 <_printf_float+0x19a> + 801388c: 3301 adds r3, #1 + 801388e: 440b add r3, r1 + 8013890: 6123 str r3, [r4, #16] + 8013892: f04f 0900 mov.w r9, #0 + 8013896: 65a1 str r1, [r4, #88] @ 0x58 + 8013898: e7dc b.n 8013854 <_printf_float+0x15c> + 801389a: b913 cbnz r3, 80138a2 <_printf_float+0x1aa> + 801389c: 6822 ldr r2, [r4, #0] + 801389e: 07d2 lsls r2, r2, #31 + 80138a0: d501 bpl.n 80138a6 <_printf_float+0x1ae> + 80138a2: 3302 adds r3, #2 + 80138a4: e7f4 b.n 8013890 <_printf_float+0x198> + 80138a6: 2301 movs r3, #1 + 80138a8: e7f2 b.n 8013890 <_printf_float+0x198> + 80138aa: f04f 0a67 mov.w sl, #103 @ 0x67 + 80138ae: 9b0e ldr r3, [sp, #56] @ 0x38 + 80138b0: 4299 cmp r1, r3 + 80138b2: db05 blt.n 80138c0 <_printf_float+0x1c8> + 80138b4: 6823 ldr r3, [r4, #0] + 80138b6: 6121 str r1, [r4, #16] + 80138b8: 07d8 lsls r0, r3, #31 + 80138ba: d5ea bpl.n 8013892 <_printf_float+0x19a> + 80138bc: 1c4b adds r3, r1, #1 + 80138be: e7e7 b.n 8013890 <_printf_float+0x198> + 80138c0: 2900 cmp r1, #0 + 80138c2: bfcc ite gt + 80138c4: 2201 movgt r2, #1 + 80138c6: f1c1 0202 rsble r2, r1, #2 + 80138ca: 4413 add r3, r2 + 80138cc: e7e0 b.n 8013890 <_printf_float+0x198> + 80138ce: 6823 ldr r3, [r4, #0] + 80138d0: 055a lsls r2, r3, #21 + 80138d2: d407 bmi.n 80138e4 <_printf_float+0x1ec> + 80138d4: 6923 ldr r3, [r4, #16] + 80138d6: 4642 mov r2, r8 + 80138d8: 4631 mov r1, r6 + 80138da: 4628 mov r0, r5 + 80138dc: 47b8 blx r7 + 80138de: 3001 adds r0, #1 + 80138e0: d12b bne.n 801393a <_printf_float+0x242> + 80138e2: e764 b.n 80137ae <_printf_float+0xb6> + 80138e4: f1ba 0f65 cmp.w sl, #101 @ 0x65 + 80138e8: f240 80dc bls.w 8013aa4 <_printf_float+0x3ac> + 80138ec: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 + 80138f0: 2200 movs r2, #0 + 80138f2: 2300 movs r3, #0 + 80138f4: f7f5 f8c4 bl 8008a80 <__aeabi_dcmpeq> + 80138f8: 2800 cmp r0, #0 + 80138fa: d033 beq.n 8013964 <_printf_float+0x26c> + 80138fc: 2301 movs r3, #1 + 80138fe: 4631 mov r1, r6 + 8013900: 4628 mov r0, r5 + 8013902: 4a35 ldr r2, [pc, #212] @ (80139d8 <_printf_float+0x2e0>) + 8013904: 47b8 blx r7 + 8013906: 3001 adds r0, #1 + 8013908: f43f af51 beq.w 80137ae <_printf_float+0xb6> + 801390c: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 + 8013910: 4543 cmp r3, r8 + 8013912: db02 blt.n 801391a <_printf_float+0x222> + 8013914: 6823 ldr r3, [r4, #0] + 8013916: 07d8 lsls r0, r3, #31 + 8013918: d50f bpl.n 801393a <_printf_float+0x242> + 801391a: e9dd 2308 ldrd r2, r3, [sp, #32] + 801391e: 4631 mov r1, r6 + 8013920: 4628 mov r0, r5 + 8013922: 47b8 blx r7 + 8013924: 3001 adds r0, #1 + 8013926: f43f af42 beq.w 80137ae <_printf_float+0xb6> + 801392a: f04f 0900 mov.w r9, #0 + 801392e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff + 8013932: f104 0a1a add.w sl, r4, #26 + 8013936: 45c8 cmp r8, r9 + 8013938: dc09 bgt.n 801394e <_printf_float+0x256> + 801393a: 6823 ldr r3, [r4, #0] + 801393c: 079b lsls r3, r3, #30 + 801393e: f100 8102 bmi.w 8013b46 <_printf_float+0x44e> + 8013942: 68e0 ldr r0, [r4, #12] + 8013944: 9b0f ldr r3, [sp, #60] @ 0x3c + 8013946: 4298 cmp r0, r3 + 8013948: bfb8 it lt + 801394a: 4618 movlt r0, r3 + 801394c: e731 b.n 80137b2 <_printf_float+0xba> + 801394e: 2301 movs r3, #1 + 8013950: 4652 mov r2, sl + 8013952: 4631 mov r1, r6 + 8013954: 4628 mov r0, r5 + 8013956: 47b8 blx r7 + 8013958: 3001 adds r0, #1 + 801395a: f43f af28 beq.w 80137ae <_printf_float+0xb6> + 801395e: f109 0901 add.w r9, r9, #1 + 8013962: e7e8 b.n 8013936 <_printf_float+0x23e> + 8013964: 9b0d ldr r3, [sp, #52] @ 0x34 + 8013966: 2b00 cmp r3, #0 + 8013968: dc38 bgt.n 80139dc <_printf_float+0x2e4> + 801396a: 2301 movs r3, #1 + 801396c: 4631 mov r1, r6 + 801396e: 4628 mov r0, r5 + 8013970: 4a19 ldr r2, [pc, #100] @ (80139d8 <_printf_float+0x2e0>) + 8013972: 47b8 blx r7 + 8013974: 3001 adds r0, #1 + 8013976: f43f af1a beq.w 80137ae <_printf_float+0xb6> + 801397a: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 + 801397e: ea59 0303 orrs.w r3, r9, r3 + 8013982: d102 bne.n 801398a <_printf_float+0x292> + 8013984: 6823 ldr r3, [r4, #0] + 8013986: 07d9 lsls r1, r3, #31 + 8013988: d5d7 bpl.n 801393a <_printf_float+0x242> + 801398a: e9dd 2308 ldrd r2, r3, [sp, #32] + 801398e: 4631 mov r1, r6 + 8013990: 4628 mov r0, r5 + 8013992: 47b8 blx r7 + 8013994: 3001 adds r0, #1 + 8013996: f43f af0a beq.w 80137ae <_printf_float+0xb6> + 801399a: f04f 0a00 mov.w sl, #0 + 801399e: f104 0b1a add.w fp, r4, #26 + 80139a2: 9b0d ldr r3, [sp, #52] @ 0x34 + 80139a4: 425b negs r3, r3 + 80139a6: 4553 cmp r3, sl + 80139a8: dc01 bgt.n 80139ae <_printf_float+0x2b6> + 80139aa: 464b mov r3, r9 + 80139ac: e793 b.n 80138d6 <_printf_float+0x1de> + 80139ae: 2301 movs r3, #1 + 80139b0: 465a mov r2, fp + 80139b2: 4631 mov r1, r6 + 80139b4: 4628 mov r0, r5 + 80139b6: 47b8 blx r7 + 80139b8: 3001 adds r0, #1 + 80139ba: f43f aef8 beq.w 80137ae <_printf_float+0xb6> + 80139be: f10a 0a01 add.w sl, sl, #1 + 80139c2: e7ee b.n 80139a2 <_printf_float+0x2aa> + 80139c4: 7fefffff .word 0x7fefffff + 80139c8: 08016c28 .word 0x08016c28 + 80139cc: 08016c24 .word 0x08016c24 + 80139d0: 08016c30 .word 0x08016c30 + 80139d4: 08016c2c .word 0x08016c2c + 80139d8: 08016c34 .word 0x08016c34 + 80139dc: 6da3 ldr r3, [r4, #88] @ 0x58 + 80139de: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 + 80139e2: 4553 cmp r3, sl + 80139e4: bfa8 it ge + 80139e6: 4653 movge r3, sl + 80139e8: 2b00 cmp r3, #0 + 80139ea: 4699 mov r9, r3 + 80139ec: dc36 bgt.n 8013a5c <_printf_float+0x364> + 80139ee: f04f 0b00 mov.w fp, #0 + 80139f2: ea29 79e9 bic.w r9, r9, r9, asr #31 + 80139f6: f104 021a add.w r2, r4, #26 + 80139fa: 6da3 ldr r3, [r4, #88] @ 0x58 + 80139fc: 930a str r3, [sp, #40] @ 0x28 + 80139fe: eba3 0309 sub.w r3, r3, r9 + 8013a02: 455b cmp r3, fp + 8013a04: dc31 bgt.n 8013a6a <_printf_float+0x372> + 8013a06: 9b0d ldr r3, [sp, #52] @ 0x34 + 8013a08: 459a cmp sl, r3 + 8013a0a: dc3a bgt.n 8013a82 <_printf_float+0x38a> + 8013a0c: 6823 ldr r3, [r4, #0] + 8013a0e: 07da lsls r2, r3, #31 + 8013a10: d437 bmi.n 8013a82 <_printf_float+0x38a> + 8013a12: 9b0d ldr r3, [sp, #52] @ 0x34 + 8013a14: ebaa 0903 sub.w r9, sl, r3 + 8013a18: 9b0a ldr r3, [sp, #40] @ 0x28 + 8013a1a: ebaa 0303 sub.w r3, sl, r3 + 8013a1e: 4599 cmp r9, r3 + 8013a20: bfa8 it ge + 8013a22: 4699 movge r9, r3 + 8013a24: f1b9 0f00 cmp.w r9, #0 + 8013a28: dc33 bgt.n 8013a92 <_printf_float+0x39a> + 8013a2a: f04f 0800 mov.w r8, #0 + 8013a2e: ea29 79e9 bic.w r9, r9, r9, asr #31 + 8013a32: f104 0b1a add.w fp, r4, #26 + 8013a36: 9b0d ldr r3, [sp, #52] @ 0x34 + 8013a38: ebaa 0303 sub.w r3, sl, r3 + 8013a3c: eba3 0309 sub.w r3, r3, r9 + 8013a40: 4543 cmp r3, r8 + 8013a42: f77f af7a ble.w 801393a <_printf_float+0x242> + 8013a46: 2301 movs r3, #1 + 8013a48: 465a mov r2, fp + 8013a4a: 4631 mov r1, r6 + 8013a4c: 4628 mov r0, r5 + 8013a4e: 47b8 blx r7 + 8013a50: 3001 adds r0, #1 + 8013a52: f43f aeac beq.w 80137ae <_printf_float+0xb6> + 8013a56: f108 0801 add.w r8, r8, #1 + 8013a5a: e7ec b.n 8013a36 <_printf_float+0x33e> + 8013a5c: 4642 mov r2, r8 + 8013a5e: 4631 mov r1, r6 + 8013a60: 4628 mov r0, r5 + 8013a62: 47b8 blx r7 + 8013a64: 3001 adds r0, #1 + 8013a66: d1c2 bne.n 80139ee <_printf_float+0x2f6> + 8013a68: e6a1 b.n 80137ae <_printf_float+0xb6> + 8013a6a: 2301 movs r3, #1 + 8013a6c: 4631 mov r1, r6 + 8013a6e: 4628 mov r0, r5 + 8013a70: 920a str r2, [sp, #40] @ 0x28 + 8013a72: 47b8 blx r7 + 8013a74: 3001 adds r0, #1 + 8013a76: f43f ae9a beq.w 80137ae <_printf_float+0xb6> + 8013a7a: 9a0a ldr r2, [sp, #40] @ 0x28 + 8013a7c: f10b 0b01 add.w fp, fp, #1 + 8013a80: e7bb b.n 80139fa <_printf_float+0x302> + 8013a82: 4631 mov r1, r6 + 8013a84: e9dd 2308 ldrd r2, r3, [sp, #32] + 8013a88: 4628 mov r0, r5 + 8013a8a: 47b8 blx r7 + 8013a8c: 3001 adds r0, #1 + 8013a8e: d1c0 bne.n 8013a12 <_printf_float+0x31a> + 8013a90: e68d b.n 80137ae <_printf_float+0xb6> + 8013a92: 9a0a ldr r2, [sp, #40] @ 0x28 + 8013a94: 464b mov r3, r9 + 8013a96: 4631 mov r1, r6 + 8013a98: 4628 mov r0, r5 + 8013a9a: 4442 add r2, r8 + 8013a9c: 47b8 blx r7 + 8013a9e: 3001 adds r0, #1 + 8013aa0: d1c3 bne.n 8013a2a <_printf_float+0x332> + 8013aa2: e684 b.n 80137ae <_printf_float+0xb6> + 8013aa4: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 + 8013aa8: f1ba 0f01 cmp.w sl, #1 + 8013aac: dc01 bgt.n 8013ab2 <_printf_float+0x3ba> + 8013aae: 07db lsls r3, r3, #31 + 8013ab0: d536 bpl.n 8013b20 <_printf_float+0x428> + 8013ab2: 2301 movs r3, #1 + 8013ab4: 4642 mov r2, r8 + 8013ab6: 4631 mov r1, r6 + 8013ab8: 4628 mov r0, r5 + 8013aba: 47b8 blx r7 + 8013abc: 3001 adds r0, #1 + 8013abe: f43f ae76 beq.w 80137ae <_printf_float+0xb6> + 8013ac2: e9dd 2308 ldrd r2, r3, [sp, #32] + 8013ac6: 4631 mov r1, r6 + 8013ac8: 4628 mov r0, r5 + 8013aca: 47b8 blx r7 + 8013acc: 3001 adds r0, #1 + 8013ace: f43f ae6e beq.w 80137ae <_printf_float+0xb6> + 8013ad2: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 + 8013ad6: 2200 movs r2, #0 + 8013ad8: 2300 movs r3, #0 + 8013ada: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff + 8013ade: f7f4 ffcf bl 8008a80 <__aeabi_dcmpeq> + 8013ae2: b9c0 cbnz r0, 8013b16 <_printf_float+0x41e> + 8013ae4: 4653 mov r3, sl + 8013ae6: f108 0201 add.w r2, r8, #1 + 8013aea: 4631 mov r1, r6 + 8013aec: 4628 mov r0, r5 + 8013aee: 47b8 blx r7 + 8013af0: 3001 adds r0, #1 + 8013af2: d10c bne.n 8013b0e <_printf_float+0x416> + 8013af4: e65b b.n 80137ae <_printf_float+0xb6> + 8013af6: 2301 movs r3, #1 + 8013af8: 465a mov r2, fp + 8013afa: 4631 mov r1, r6 + 8013afc: 4628 mov r0, r5 + 8013afe: 47b8 blx r7 + 8013b00: 3001 adds r0, #1 + 8013b02: f43f ae54 beq.w 80137ae <_printf_float+0xb6> + 8013b06: f108 0801 add.w r8, r8, #1 + 8013b0a: 45d0 cmp r8, sl + 8013b0c: dbf3 blt.n 8013af6 <_printf_float+0x3fe> + 8013b0e: 464b mov r3, r9 + 8013b10: f104 0250 add.w r2, r4, #80 @ 0x50 + 8013b14: e6e0 b.n 80138d8 <_printf_float+0x1e0> + 8013b16: f04f 0800 mov.w r8, #0 + 8013b1a: f104 0b1a add.w fp, r4, #26 + 8013b1e: e7f4 b.n 8013b0a <_printf_float+0x412> + 8013b20: 2301 movs r3, #1 + 8013b22: 4642 mov r2, r8 + 8013b24: e7e1 b.n 8013aea <_printf_float+0x3f2> + 8013b26: 2301 movs r3, #1 + 8013b28: 464a mov r2, r9 + 8013b2a: 4631 mov r1, r6 + 8013b2c: 4628 mov r0, r5 + 8013b2e: 47b8 blx r7 + 8013b30: 3001 adds r0, #1 + 8013b32: f43f ae3c beq.w 80137ae <_printf_float+0xb6> + 8013b36: f108 0801 add.w r8, r8, #1 + 8013b3a: 68e3 ldr r3, [r4, #12] + 8013b3c: 990f ldr r1, [sp, #60] @ 0x3c + 8013b3e: 1a5b subs r3, r3, r1 + 8013b40: 4543 cmp r3, r8 + 8013b42: dcf0 bgt.n 8013b26 <_printf_float+0x42e> + 8013b44: e6fd b.n 8013942 <_printf_float+0x24a> + 8013b46: f04f 0800 mov.w r8, #0 + 8013b4a: f104 0919 add.w r9, r4, #25 + 8013b4e: e7f4 b.n 8013b3a <_printf_float+0x442> + +08013b50 <_printf_common>: + 8013b50: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8013b54: 4616 mov r6, r2 + 8013b56: 4698 mov r8, r3 + 8013b58: 688a ldr r2, [r1, #8] + 8013b5a: 690b ldr r3, [r1, #16] + 8013b5c: 4607 mov r7, r0 + 8013b5e: 4293 cmp r3, r2 + 8013b60: bfb8 it lt + 8013b62: 4613 movlt r3, r2 + 8013b64: 6033 str r3, [r6, #0] + 8013b66: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 + 8013b6a: 460c mov r4, r1 + 8013b6c: f8dd 9020 ldr.w r9, [sp, #32] + 8013b70: b10a cbz r2, 8013b76 <_printf_common+0x26> + 8013b72: 3301 adds r3, #1 + 8013b74: 6033 str r3, [r6, #0] + 8013b76: 6823 ldr r3, [r4, #0] + 8013b78: 0699 lsls r1, r3, #26 + 8013b7a: bf42 ittt mi + 8013b7c: 6833 ldrmi r3, [r6, #0] + 8013b7e: 3302 addmi r3, #2 + 8013b80: 6033 strmi r3, [r6, #0] + 8013b82: 6825 ldr r5, [r4, #0] + 8013b84: f015 0506 ands.w r5, r5, #6 + 8013b88: d106 bne.n 8013b98 <_printf_common+0x48> + 8013b8a: f104 0a19 add.w sl, r4, #25 + 8013b8e: 68e3 ldr r3, [r4, #12] + 8013b90: 6832 ldr r2, [r6, #0] + 8013b92: 1a9b subs r3, r3, r2 + 8013b94: 42ab cmp r3, r5 + 8013b96: dc2b bgt.n 8013bf0 <_printf_common+0xa0> + 8013b98: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 + 8013b9c: 6822 ldr r2, [r4, #0] + 8013b9e: 3b00 subs r3, #0 + 8013ba0: bf18 it ne + 8013ba2: 2301 movne r3, #1 + 8013ba4: 0692 lsls r2, r2, #26 + 8013ba6: d430 bmi.n 8013c0a <_printf_common+0xba> + 8013ba8: 4641 mov r1, r8 + 8013baa: 4638 mov r0, r7 + 8013bac: f104 0243 add.w r2, r4, #67 @ 0x43 + 8013bb0: 47c8 blx r9 + 8013bb2: 3001 adds r0, #1 + 8013bb4: d023 beq.n 8013bfe <_printf_common+0xae> + 8013bb6: 6823 ldr r3, [r4, #0] + 8013bb8: 6922 ldr r2, [r4, #16] + 8013bba: f003 0306 and.w r3, r3, #6 + 8013bbe: 2b04 cmp r3, #4 + 8013bc0: bf14 ite ne + 8013bc2: 2500 movne r5, #0 + 8013bc4: 6833 ldreq r3, [r6, #0] + 8013bc6: f04f 0600 mov.w r6, #0 + 8013bca: bf08 it eq + 8013bcc: 68e5 ldreq r5, [r4, #12] + 8013bce: f104 041a add.w r4, r4, #26 + 8013bd2: bf08 it eq + 8013bd4: 1aed subeq r5, r5, r3 + 8013bd6: f854 3c12 ldr.w r3, [r4, #-18] + 8013bda: bf08 it eq + 8013bdc: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8013be0: 4293 cmp r3, r2 + 8013be2: bfc4 itt gt + 8013be4: 1a9b subgt r3, r3, r2 + 8013be6: 18ed addgt r5, r5, r3 + 8013be8: 42b5 cmp r5, r6 + 8013bea: d11a bne.n 8013c22 <_printf_common+0xd2> + 8013bec: 2000 movs r0, #0 + 8013bee: e008 b.n 8013c02 <_printf_common+0xb2> + 8013bf0: 2301 movs r3, #1 + 8013bf2: 4652 mov r2, sl + 8013bf4: 4641 mov r1, r8 + 8013bf6: 4638 mov r0, r7 + 8013bf8: 47c8 blx r9 + 8013bfa: 3001 adds r0, #1 + 8013bfc: d103 bne.n 8013c06 <_printf_common+0xb6> + 8013bfe: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8013c02: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8013c06: 3501 adds r5, #1 + 8013c08: e7c1 b.n 8013b8e <_printf_common+0x3e> + 8013c0a: 2030 movs r0, #48 @ 0x30 + 8013c0c: 18e1 adds r1, r4, r3 + 8013c0e: f881 0043 strb.w r0, [r1, #67] @ 0x43 + 8013c12: 1c5a adds r2, r3, #1 + 8013c14: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 + 8013c18: 4422 add r2, r4 + 8013c1a: 3302 adds r3, #2 + 8013c1c: f882 1043 strb.w r1, [r2, #67] @ 0x43 + 8013c20: e7c2 b.n 8013ba8 <_printf_common+0x58> + 8013c22: 2301 movs r3, #1 + 8013c24: 4622 mov r2, r4 + 8013c26: 4641 mov r1, r8 + 8013c28: 4638 mov r0, r7 + 8013c2a: 47c8 blx r9 + 8013c2c: 3001 adds r0, #1 + 8013c2e: d0e6 beq.n 8013bfe <_printf_common+0xae> + 8013c30: 3601 adds r6, #1 + 8013c32: e7d9 b.n 8013be8 <_printf_common+0x98> + +08013c34 <_printf_i>: + 8013c34: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8013c38: 7e0f ldrb r7, [r1, #24] + 8013c3a: 4691 mov r9, r2 + 8013c3c: 2f78 cmp r7, #120 @ 0x78 + 8013c3e: 4680 mov r8, r0 + 8013c40: 460c mov r4, r1 + 8013c42: 469a mov sl, r3 + 8013c44: 9e0c ldr r6, [sp, #48] @ 0x30 + 8013c46: f101 0243 add.w r2, r1, #67 @ 0x43 + 8013c4a: d807 bhi.n 8013c5c <_printf_i+0x28> + 8013c4c: 2f62 cmp r7, #98 @ 0x62 + 8013c4e: d80a bhi.n 8013c66 <_printf_i+0x32> + 8013c50: 2f00 cmp r7, #0 + 8013c52: f000 80d1 beq.w 8013df8 <_printf_i+0x1c4> + 8013c56: 2f58 cmp r7, #88 @ 0x58 + 8013c58: f000 80b8 beq.w 8013dcc <_printf_i+0x198> + 8013c5c: f104 0642 add.w r6, r4, #66 @ 0x42 + 8013c60: f884 7042 strb.w r7, [r4, #66] @ 0x42 + 8013c64: e03a b.n 8013cdc <_printf_i+0xa8> + 8013c66: f1a7 0363 sub.w r3, r7, #99 @ 0x63 + 8013c6a: 2b15 cmp r3, #21 + 8013c6c: d8f6 bhi.n 8013c5c <_printf_i+0x28> + 8013c6e: a101 add r1, pc, #4 @ (adr r1, 8013c74 <_printf_i+0x40>) + 8013c70: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 8013c74: 08013ccd .word 0x08013ccd + 8013c78: 08013ce1 .word 0x08013ce1 + 8013c7c: 08013c5d .word 0x08013c5d + 8013c80: 08013c5d .word 0x08013c5d + 8013c84: 08013c5d .word 0x08013c5d + 8013c88: 08013c5d .word 0x08013c5d + 8013c8c: 08013ce1 .word 0x08013ce1 + 8013c90: 08013c5d .word 0x08013c5d + 8013c94: 08013c5d .word 0x08013c5d + 8013c98: 08013c5d .word 0x08013c5d + 8013c9c: 08013c5d .word 0x08013c5d + 8013ca0: 08013ddf .word 0x08013ddf + 8013ca4: 08013d0b .word 0x08013d0b + 8013ca8: 08013d99 .word 0x08013d99 + 8013cac: 08013c5d .word 0x08013c5d + 8013cb0: 08013c5d .word 0x08013c5d + 8013cb4: 08013e01 .word 0x08013e01 + 8013cb8: 08013c5d .word 0x08013c5d + 8013cbc: 08013d0b .word 0x08013d0b + 8013cc0: 08013c5d .word 0x08013c5d + 8013cc4: 08013c5d .word 0x08013c5d + 8013cc8: 08013da1 .word 0x08013da1 + 8013ccc: 6833 ldr r3, [r6, #0] + 8013cce: 1d1a adds r2, r3, #4 + 8013cd0: 681b ldr r3, [r3, #0] + 8013cd2: 6032 str r2, [r6, #0] + 8013cd4: f104 0642 add.w r6, r4, #66 @ 0x42 + 8013cd8: f884 3042 strb.w r3, [r4, #66] @ 0x42 + 8013cdc: 2301 movs r3, #1 + 8013cde: e09c b.n 8013e1a <_printf_i+0x1e6> + 8013ce0: 6833 ldr r3, [r6, #0] + 8013ce2: 6820 ldr r0, [r4, #0] + 8013ce4: 1d19 adds r1, r3, #4 + 8013ce6: 6031 str r1, [r6, #0] + 8013ce8: 0606 lsls r6, r0, #24 + 8013cea: d501 bpl.n 8013cf0 <_printf_i+0xbc> + 8013cec: 681d ldr r5, [r3, #0] + 8013cee: e003 b.n 8013cf8 <_printf_i+0xc4> + 8013cf0: 0645 lsls r5, r0, #25 + 8013cf2: d5fb bpl.n 8013cec <_printf_i+0xb8> + 8013cf4: f9b3 5000 ldrsh.w r5, [r3] + 8013cf8: 2d00 cmp r5, #0 + 8013cfa: da03 bge.n 8013d04 <_printf_i+0xd0> + 8013cfc: 232d movs r3, #45 @ 0x2d + 8013cfe: 426d negs r5, r5 + 8013d00: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 8013d04: 230a movs r3, #10 + 8013d06: 4858 ldr r0, [pc, #352] @ (8013e68 <_printf_i+0x234>) + 8013d08: e011 b.n 8013d2e <_printf_i+0xfa> + 8013d0a: 6821 ldr r1, [r4, #0] + 8013d0c: 6833 ldr r3, [r6, #0] + 8013d0e: 0608 lsls r0, r1, #24 + 8013d10: f853 5b04 ldr.w r5, [r3], #4 + 8013d14: d402 bmi.n 8013d1c <_printf_i+0xe8> + 8013d16: 0649 lsls r1, r1, #25 + 8013d18: bf48 it mi + 8013d1a: b2ad uxthmi r5, r5 + 8013d1c: 2f6f cmp r7, #111 @ 0x6f + 8013d1e: 6033 str r3, [r6, #0] + 8013d20: bf14 ite ne + 8013d22: 230a movne r3, #10 + 8013d24: 2308 moveq r3, #8 + 8013d26: 4850 ldr r0, [pc, #320] @ (8013e68 <_printf_i+0x234>) + 8013d28: 2100 movs r1, #0 + 8013d2a: f884 1043 strb.w r1, [r4, #67] @ 0x43 + 8013d2e: 6866 ldr r6, [r4, #4] + 8013d30: 2e00 cmp r6, #0 + 8013d32: 60a6 str r6, [r4, #8] + 8013d34: db05 blt.n 8013d42 <_printf_i+0x10e> + 8013d36: 6821 ldr r1, [r4, #0] + 8013d38: 432e orrs r6, r5 + 8013d3a: f021 0104 bic.w r1, r1, #4 + 8013d3e: 6021 str r1, [r4, #0] + 8013d40: d04b beq.n 8013dda <_printf_i+0x1a6> + 8013d42: 4616 mov r6, r2 + 8013d44: fbb5 f1f3 udiv r1, r5, r3 + 8013d48: fb03 5711 mls r7, r3, r1, r5 + 8013d4c: 5dc7 ldrb r7, [r0, r7] + 8013d4e: f806 7d01 strb.w r7, [r6, #-1]! + 8013d52: 462f mov r7, r5 + 8013d54: 42bb cmp r3, r7 + 8013d56: 460d mov r5, r1 + 8013d58: d9f4 bls.n 8013d44 <_printf_i+0x110> + 8013d5a: 2b08 cmp r3, #8 + 8013d5c: d10b bne.n 8013d76 <_printf_i+0x142> + 8013d5e: 6823 ldr r3, [r4, #0] + 8013d60: 07df lsls r7, r3, #31 + 8013d62: d508 bpl.n 8013d76 <_printf_i+0x142> + 8013d64: 6923 ldr r3, [r4, #16] + 8013d66: 6861 ldr r1, [r4, #4] + 8013d68: 4299 cmp r1, r3 + 8013d6a: bfde ittt le + 8013d6c: 2330 movle r3, #48 @ 0x30 + 8013d6e: f806 3c01 strble.w r3, [r6, #-1] + 8013d72: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff + 8013d76: 1b92 subs r2, r2, r6 + 8013d78: 6122 str r2, [r4, #16] + 8013d7a: 464b mov r3, r9 + 8013d7c: 4621 mov r1, r4 + 8013d7e: 4640 mov r0, r8 + 8013d80: f8cd a000 str.w sl, [sp] + 8013d84: aa03 add r2, sp, #12 + 8013d86: f7ff fee3 bl 8013b50 <_printf_common> + 8013d8a: 3001 adds r0, #1 + 8013d8c: d14a bne.n 8013e24 <_printf_i+0x1f0> + 8013d8e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8013d92: b004 add sp, #16 + 8013d94: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8013d98: 6823 ldr r3, [r4, #0] + 8013d9a: f043 0320 orr.w r3, r3, #32 + 8013d9e: 6023 str r3, [r4, #0] + 8013da0: 2778 movs r7, #120 @ 0x78 + 8013da2: 4832 ldr r0, [pc, #200] @ (8013e6c <_printf_i+0x238>) + 8013da4: f884 7045 strb.w r7, [r4, #69] @ 0x45 + 8013da8: 6823 ldr r3, [r4, #0] + 8013daa: 6831 ldr r1, [r6, #0] + 8013dac: 061f lsls r7, r3, #24 + 8013dae: f851 5b04 ldr.w r5, [r1], #4 + 8013db2: d402 bmi.n 8013dba <_printf_i+0x186> + 8013db4: 065f lsls r7, r3, #25 + 8013db6: bf48 it mi + 8013db8: b2ad uxthmi r5, r5 + 8013dba: 6031 str r1, [r6, #0] + 8013dbc: 07d9 lsls r1, r3, #31 + 8013dbe: bf44 itt mi + 8013dc0: f043 0320 orrmi.w r3, r3, #32 + 8013dc4: 6023 strmi r3, [r4, #0] + 8013dc6: b11d cbz r5, 8013dd0 <_printf_i+0x19c> + 8013dc8: 2310 movs r3, #16 + 8013dca: e7ad b.n 8013d28 <_printf_i+0xf4> + 8013dcc: 4826 ldr r0, [pc, #152] @ (8013e68 <_printf_i+0x234>) + 8013dce: e7e9 b.n 8013da4 <_printf_i+0x170> + 8013dd0: 6823 ldr r3, [r4, #0] + 8013dd2: f023 0320 bic.w r3, r3, #32 + 8013dd6: 6023 str r3, [r4, #0] + 8013dd8: e7f6 b.n 8013dc8 <_printf_i+0x194> + 8013dda: 4616 mov r6, r2 + 8013ddc: e7bd b.n 8013d5a <_printf_i+0x126> + 8013dde: 6833 ldr r3, [r6, #0] + 8013de0: 6825 ldr r5, [r4, #0] + 8013de2: 1d18 adds r0, r3, #4 + 8013de4: 6961 ldr r1, [r4, #20] + 8013de6: 6030 str r0, [r6, #0] + 8013de8: 062e lsls r6, r5, #24 + 8013dea: 681b ldr r3, [r3, #0] + 8013dec: d501 bpl.n 8013df2 <_printf_i+0x1be> + 8013dee: 6019 str r1, [r3, #0] + 8013df0: e002 b.n 8013df8 <_printf_i+0x1c4> + 8013df2: 0668 lsls r0, r5, #25 + 8013df4: d5fb bpl.n 8013dee <_printf_i+0x1ba> + 8013df6: 8019 strh r1, [r3, #0] + 8013df8: 2300 movs r3, #0 + 8013dfa: 4616 mov r6, r2 + 8013dfc: 6123 str r3, [r4, #16] + 8013dfe: e7bc b.n 8013d7a <_printf_i+0x146> + 8013e00: 6833 ldr r3, [r6, #0] + 8013e02: 2100 movs r1, #0 + 8013e04: 1d1a adds r2, r3, #4 + 8013e06: 6032 str r2, [r6, #0] + 8013e08: 681e ldr r6, [r3, #0] + 8013e0a: 6862 ldr r2, [r4, #4] + 8013e0c: 4630 mov r0, r6 + 8013e0e: f000 fa3f bl 8014290 + 8013e12: b108 cbz r0, 8013e18 <_printf_i+0x1e4> + 8013e14: 1b80 subs r0, r0, r6 + 8013e16: 6060 str r0, [r4, #4] + 8013e18: 6863 ldr r3, [r4, #4] + 8013e1a: 6123 str r3, [r4, #16] + 8013e1c: 2300 movs r3, #0 + 8013e1e: f884 3043 strb.w r3, [r4, #67] @ 0x43 + 8013e22: e7aa b.n 8013d7a <_printf_i+0x146> + 8013e24: 4632 mov r2, r6 + 8013e26: 4649 mov r1, r9 + 8013e28: 4640 mov r0, r8 + 8013e2a: 6923 ldr r3, [r4, #16] + 8013e2c: 47d0 blx sl + 8013e2e: 3001 adds r0, #1 + 8013e30: d0ad beq.n 8013d8e <_printf_i+0x15a> + 8013e32: 6823 ldr r3, [r4, #0] + 8013e34: 079b lsls r3, r3, #30 + 8013e36: d413 bmi.n 8013e60 <_printf_i+0x22c> + 8013e38: 68e0 ldr r0, [r4, #12] + 8013e3a: 9b03 ldr r3, [sp, #12] + 8013e3c: 4298 cmp r0, r3 + 8013e3e: bfb8 it lt + 8013e40: 4618 movlt r0, r3 + 8013e42: e7a6 b.n 8013d92 <_printf_i+0x15e> + 8013e44: 2301 movs r3, #1 + 8013e46: 4632 mov r2, r6 + 8013e48: 4649 mov r1, r9 + 8013e4a: 4640 mov r0, r8 + 8013e4c: 47d0 blx sl + 8013e4e: 3001 adds r0, #1 + 8013e50: d09d beq.n 8013d8e <_printf_i+0x15a> + 8013e52: 3501 adds r5, #1 + 8013e54: 68e3 ldr r3, [r4, #12] + 8013e56: 9903 ldr r1, [sp, #12] + 8013e58: 1a5b subs r3, r3, r1 + 8013e5a: 42ab cmp r3, r5 + 8013e5c: dcf2 bgt.n 8013e44 <_printf_i+0x210> + 8013e5e: e7eb b.n 8013e38 <_printf_i+0x204> + 8013e60: 2500 movs r5, #0 + 8013e62: f104 0619 add.w r6, r4, #25 + 8013e66: e7f5 b.n 8013e54 <_printf_i+0x220> + 8013e68: 08016c36 .word 0x08016c36 + 8013e6c: 08016c47 .word 0x08016c47 + +08013e70 : + 8013e70: 2300 movs r3, #0 + 8013e72: b510 push {r4, lr} + 8013e74: 4604 mov r4, r0 + 8013e76: e9c0 3300 strd r3, r3, [r0] + 8013e7a: e9c0 3304 strd r3, r3, [r0, #16] + 8013e7e: 6083 str r3, [r0, #8] + 8013e80: 8181 strh r1, [r0, #12] + 8013e82: 6643 str r3, [r0, #100] @ 0x64 + 8013e84: 81c2 strh r2, [r0, #14] + 8013e86: 6183 str r3, [r0, #24] + 8013e88: 4619 mov r1, r3 + 8013e8a: 2208 movs r2, #8 + 8013e8c: 305c adds r0, #92 @ 0x5c + 8013e8e: f000 f8ff bl 8014090 + 8013e92: 4b0d ldr r3, [pc, #52] @ (8013ec8 ) + 8013e94: 6224 str r4, [r4, #32] + 8013e96: 6263 str r3, [r4, #36] @ 0x24 + 8013e98: 4b0c ldr r3, [pc, #48] @ (8013ecc ) + 8013e9a: 62a3 str r3, [r4, #40] @ 0x28 + 8013e9c: 4b0c ldr r3, [pc, #48] @ (8013ed0 ) + 8013e9e: 62e3 str r3, [r4, #44] @ 0x2c + 8013ea0: 4b0c ldr r3, [pc, #48] @ (8013ed4 ) + 8013ea2: 6323 str r3, [r4, #48] @ 0x30 + 8013ea4: 4b0c ldr r3, [pc, #48] @ (8013ed8 ) + 8013ea6: 429c cmp r4, r3 + 8013ea8: d006 beq.n 8013eb8 + 8013eaa: f103 0268 add.w r2, r3, #104 @ 0x68 + 8013eae: 4294 cmp r4, r2 + 8013eb0: d002 beq.n 8013eb8 + 8013eb2: 33d0 adds r3, #208 @ 0xd0 + 8013eb4: 429c cmp r4, r3 + 8013eb6: d105 bne.n 8013ec4 + 8013eb8: f104 0058 add.w r0, r4, #88 @ 0x58 + 8013ebc: e8bd 4010 ldmia.w sp!, {r4, lr} + 8013ec0: f000 b9de b.w 8014280 <__retarget_lock_init_recursive> + 8013ec4: bd10 pop {r4, pc} + 8013ec6: bf00 nop + 8013ec8: 08015ea1 .word 0x08015ea1 + 8013ecc: 08015ec3 .word 0x08015ec3 + 8013ed0: 08015efb .word 0x08015efb + 8013ed4: 08015f1f .word 0x08015f1f + 8013ed8: 20000e64 .word 0x20000e64 + +08013edc : + 8013edc: 4a02 ldr r2, [pc, #8] @ (8013ee8 ) + 8013ede: 4903 ldr r1, [pc, #12] @ (8013eec ) + 8013ee0: 4803 ldr r0, [pc, #12] @ (8013ef0 ) + 8013ee2: f000 b8a5 b.w 8014030 <_fwalk_sglue> + 8013ee6: bf00 nop + 8013ee8: 20000078 .word 0x20000078 + 8013eec: 08015745 .word 0x08015745 + 8013ef0: 20000088 .word 0x20000088 + +08013ef4 : + 8013ef4: 6841 ldr r1, [r0, #4] + 8013ef6: 4b0c ldr r3, [pc, #48] @ (8013f28 ) + 8013ef8: b510 push {r4, lr} + 8013efa: 4299 cmp r1, r3 + 8013efc: 4604 mov r4, r0 + 8013efe: d001 beq.n 8013f04 + 8013f00: f001 fc20 bl 8015744 <_fflush_r> + 8013f04: 68a1 ldr r1, [r4, #8] + 8013f06: 4b09 ldr r3, [pc, #36] @ (8013f2c ) + 8013f08: 4299 cmp r1, r3 + 8013f0a: d002 beq.n 8013f12 + 8013f0c: 4620 mov r0, r4 + 8013f0e: f001 fc19 bl 8015744 <_fflush_r> + 8013f12: 68e1 ldr r1, [r4, #12] + 8013f14: 4b06 ldr r3, [pc, #24] @ (8013f30 ) + 8013f16: 4299 cmp r1, r3 + 8013f18: d004 beq.n 8013f24 + 8013f1a: 4620 mov r0, r4 + 8013f1c: e8bd 4010 ldmia.w sp!, {r4, lr} + 8013f20: f001 bc10 b.w 8015744 <_fflush_r> + 8013f24: bd10 pop {r4, pc} + 8013f26: bf00 nop + 8013f28: 20000e64 .word 0x20000e64 + 8013f2c: 20000ecc .word 0x20000ecc + 8013f30: 20000f34 .word 0x20000f34 + +08013f34 : + 8013f34: b510 push {r4, lr} + 8013f36: 4b0b ldr r3, [pc, #44] @ (8013f64 ) + 8013f38: 4c0b ldr r4, [pc, #44] @ (8013f68 ) + 8013f3a: 4a0c ldr r2, [pc, #48] @ (8013f6c ) + 8013f3c: 4620 mov r0, r4 + 8013f3e: 601a str r2, [r3, #0] + 8013f40: 2104 movs r1, #4 + 8013f42: 2200 movs r2, #0 + 8013f44: f7ff ff94 bl 8013e70 + 8013f48: f104 0068 add.w r0, r4, #104 @ 0x68 + 8013f4c: 2201 movs r2, #1 + 8013f4e: 2109 movs r1, #9 + 8013f50: f7ff ff8e bl 8013e70 + 8013f54: f104 00d0 add.w r0, r4, #208 @ 0xd0 + 8013f58: 2202 movs r2, #2 + 8013f5a: e8bd 4010 ldmia.w sp!, {r4, lr} + 8013f5e: 2112 movs r1, #18 + 8013f60: f7ff bf86 b.w 8013e70 + 8013f64: 20000f9c .word 0x20000f9c + 8013f68: 20000e64 .word 0x20000e64 + 8013f6c: 08013edd .word 0x08013edd + +08013f70 <__sfp_lock_acquire>: + 8013f70: 4801 ldr r0, [pc, #4] @ (8013f78 <__sfp_lock_acquire+0x8>) + 8013f72: f000 b986 b.w 8014282 <__retarget_lock_acquire_recursive> + 8013f76: bf00 nop + 8013f78: 20000fa1 .word 0x20000fa1 + +08013f7c <__sfp_lock_release>: + 8013f7c: 4801 ldr r0, [pc, #4] @ (8013f84 <__sfp_lock_release+0x8>) + 8013f7e: f000 b981 b.w 8014284 <__retarget_lock_release_recursive> + 8013f82: bf00 nop + 8013f84: 20000fa1 .word 0x20000fa1 + +08013f88 <__sinit>: + 8013f88: b510 push {r4, lr} + 8013f8a: 4604 mov r4, r0 + 8013f8c: f7ff fff0 bl 8013f70 <__sfp_lock_acquire> + 8013f90: 6a23 ldr r3, [r4, #32] + 8013f92: b11b cbz r3, 8013f9c <__sinit+0x14> + 8013f94: e8bd 4010 ldmia.w sp!, {r4, lr} + 8013f98: f7ff bff0 b.w 8013f7c <__sfp_lock_release> + 8013f9c: 4b04 ldr r3, [pc, #16] @ (8013fb0 <__sinit+0x28>) + 8013f9e: 6223 str r3, [r4, #32] + 8013fa0: 4b04 ldr r3, [pc, #16] @ (8013fb4 <__sinit+0x2c>) + 8013fa2: 681b ldr r3, [r3, #0] + 8013fa4: 2b00 cmp r3, #0 + 8013fa6: d1f5 bne.n 8013f94 <__sinit+0xc> + 8013fa8: f7ff ffc4 bl 8013f34 + 8013fac: e7f2 b.n 8013f94 <__sinit+0xc> + 8013fae: bf00 nop + 8013fb0: 08013ef5 .word 0x08013ef5 + 8013fb4: 20000f9c .word 0x20000f9c + +08013fb8 <_vsniprintf_r>: + 8013fb8: b530 push {r4, r5, lr} + 8013fba: 4614 mov r4, r2 + 8013fbc: 2c00 cmp r4, #0 + 8013fbe: 4605 mov r5, r0 + 8013fc0: 461a mov r2, r3 + 8013fc2: b09b sub sp, #108 @ 0x6c + 8013fc4: da05 bge.n 8013fd2 <_vsniprintf_r+0x1a> + 8013fc6: 238b movs r3, #139 @ 0x8b + 8013fc8: 6003 str r3, [r0, #0] + 8013fca: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8013fce: b01b add sp, #108 @ 0x6c + 8013fd0: bd30 pop {r4, r5, pc} + 8013fd2: f44f 7302 mov.w r3, #520 @ 0x208 + 8013fd6: f8ad 300c strh.w r3, [sp, #12] + 8013fda: f04f 0300 mov.w r3, #0 + 8013fde: 9319 str r3, [sp, #100] @ 0x64 + 8013fe0: bf0c ite eq + 8013fe2: 4623 moveq r3, r4 + 8013fe4: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff + 8013fe8: 9302 str r3, [sp, #8] + 8013fea: 9305 str r3, [sp, #20] + 8013fec: f64f 73ff movw r3, #65535 @ 0xffff + 8013ff0: 9100 str r1, [sp, #0] + 8013ff2: 9104 str r1, [sp, #16] + 8013ff4: f8ad 300e strh.w r3, [sp, #14] + 8013ff8: 4669 mov r1, sp + 8013ffa: 9b1e ldr r3, [sp, #120] @ 0x78 + 8013ffc: f001 f83c bl 8015078 <_svfiprintf_r> + 8014000: 1c43 adds r3, r0, #1 + 8014002: bfbc itt lt + 8014004: 238b movlt r3, #139 @ 0x8b + 8014006: 602b strlt r3, [r5, #0] + 8014008: 2c00 cmp r4, #0 + 801400a: d0e0 beq.n 8013fce <_vsniprintf_r+0x16> + 801400c: 2200 movs r2, #0 + 801400e: 9b00 ldr r3, [sp, #0] + 8014010: 701a strb r2, [r3, #0] + 8014012: e7dc b.n 8013fce <_vsniprintf_r+0x16> + +08014014 : + 8014014: b507 push {r0, r1, r2, lr} + 8014016: 9300 str r3, [sp, #0] + 8014018: 4613 mov r3, r2 + 801401a: 460a mov r2, r1 + 801401c: 4601 mov r1, r0 + 801401e: 4803 ldr r0, [pc, #12] @ (801402c ) + 8014020: 6800 ldr r0, [r0, #0] + 8014022: f7ff ffc9 bl 8013fb8 <_vsniprintf_r> + 8014026: b003 add sp, #12 + 8014028: f85d fb04 ldr.w pc, [sp], #4 + 801402c: 20000084 .word 0x20000084 + +08014030 <_fwalk_sglue>: + 8014030: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8014034: 4607 mov r7, r0 + 8014036: 4688 mov r8, r1 + 8014038: 4614 mov r4, r2 + 801403a: 2600 movs r6, #0 + 801403c: e9d4 9501 ldrd r9, r5, [r4, #4] + 8014040: f1b9 0901 subs.w r9, r9, #1 + 8014044: d505 bpl.n 8014052 <_fwalk_sglue+0x22> + 8014046: 6824 ldr r4, [r4, #0] + 8014048: 2c00 cmp r4, #0 + 801404a: d1f7 bne.n 801403c <_fwalk_sglue+0xc> + 801404c: 4630 mov r0, r6 + 801404e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8014052: 89ab ldrh r3, [r5, #12] + 8014054: 2b01 cmp r3, #1 + 8014056: d907 bls.n 8014068 <_fwalk_sglue+0x38> + 8014058: f9b5 300e ldrsh.w r3, [r5, #14] + 801405c: 3301 adds r3, #1 + 801405e: d003 beq.n 8014068 <_fwalk_sglue+0x38> + 8014060: 4629 mov r1, r5 + 8014062: 4638 mov r0, r7 + 8014064: 47c0 blx r8 + 8014066: 4306 orrs r6, r0 + 8014068: 3568 adds r5, #104 @ 0x68 + 801406a: e7e9 b.n 8014040 <_fwalk_sglue+0x10> + +0801406c : + 801406c: b40f push {r0, r1, r2, r3} + 801406e: b507 push {r0, r1, r2, lr} + 8014070: 4906 ldr r1, [pc, #24] @ (801408c ) + 8014072: ab04 add r3, sp, #16 + 8014074: 6808 ldr r0, [r1, #0] + 8014076: f853 2b04 ldr.w r2, [r3], #4 + 801407a: 6881 ldr r1, [r0, #8] + 801407c: 9301 str r3, [sp, #4] + 801407e: f001 f91f bl 80152c0 <_vfiprintf_r> + 8014082: b003 add sp, #12 + 8014084: f85d eb04 ldr.w lr, [sp], #4 + 8014088: b004 add sp, #16 + 801408a: 4770 bx lr + 801408c: 20000084 .word 0x20000084 + +08014090 : + 8014090: 4603 mov r3, r0 + 8014092: 4402 add r2, r0 + 8014094: 4293 cmp r3, r2 + 8014096: d100 bne.n 801409a + 8014098: 4770 bx lr + 801409a: f803 1b01 strb.w r1, [r3], #1 + 801409e: e7f9 b.n 8014094 + +080140a0 : + 80140a0: b538 push {r3, r4, r5, lr} + 80140a2: 4b0b ldr r3, [pc, #44] @ (80140d0 ) + 80140a4: 4604 mov r4, r0 + 80140a6: 681d ldr r5, [r3, #0] + 80140a8: 6b6b ldr r3, [r5, #52] @ 0x34 + 80140aa: b953 cbnz r3, 80140c2 + 80140ac: 2024 movs r0, #36 @ 0x24 + 80140ae: f001 fa1f bl 80154f0 + 80140b2: 4602 mov r2, r0 + 80140b4: 6368 str r0, [r5, #52] @ 0x34 + 80140b6: b920 cbnz r0, 80140c2 + 80140b8: 213d movs r1, #61 @ 0x3d + 80140ba: 4b06 ldr r3, [pc, #24] @ (80140d4 ) + 80140bc: 4806 ldr r0, [pc, #24] @ (80140d8 ) + 80140be: f000 f903 bl 80142c8 <__assert_func> + 80140c2: 4620 mov r0, r4 + 80140c4: 6b69 ldr r1, [r5, #52] @ 0x34 + 80140c6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 80140ca: f000 b807 b.w 80140dc + 80140ce: bf00 nop + 80140d0: 20000084 .word 0x20000084 + 80140d4: 08016c58 .word 0x08016c58 + 80140d8: 08016c6f .word 0x08016c6f + +080140dc : + 80140dc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80140e0: 2300 movs r3, #0 + 80140e2: 460c mov r4, r1 + 80140e4: e9d0 0100 ldrd r0, r1, [r0] + 80140e8: 4a4c ldr r2, [pc, #304] @ (801421c ) + 80140ea: f7f5 f883 bl 80091f4 <__aeabi_ldivmod> + 80140ee: f44f 6161 mov.w r1, #3600 @ 0xe10 + 80140f2: 2a00 cmp r2, #0 + 80140f4: bfbc itt lt + 80140f6: f502 32a8 addlt.w r2, r2, #86016 @ 0x15000 + 80140fa: f502 72c0 addlt.w r2, r2, #384 @ 0x180 + 80140fe: fbb2 f3f1 udiv r3, r2, r1 + 8014102: fb01 2213 mls r2, r1, r3, r2 + 8014106: f04f 013c mov.w r1, #60 @ 0x3c + 801410a: 60a3 str r3, [r4, #8] + 801410c: fbb2 f3f1 udiv r3, r2, r1 + 8014110: fb01 2213 mls r2, r1, r3, r2 + 8014114: 6022 str r2, [r4, #0] + 8014116: f04f 0207 mov.w r2, #7 + 801411a: f500 202f add.w r0, r0, #716800 @ 0xaf000 + 801411e: bfac ite ge + 8014120: f600 206c addwge r0, r0, #2668 @ 0xa6c + 8014124: f600 206b addwlt r0, r0, #2667 @ 0xa6b + 8014128: 6063 str r3, [r4, #4] + 801412a: 1cc3 adds r3, r0, #3 + 801412c: fb93 f2f2 sdiv r2, r3, r2 + 8014130: ebc2 02c2 rsb r2, r2, r2, lsl #3 + 8014134: 1a9b subs r3, r3, r2 + 8014136: 493a ldr r1, [pc, #232] @ (8014220 ) + 8014138: d555 bpl.n 80141e6 + 801413a: 3307 adds r3, #7 + 801413c: 61a3 str r3, [r4, #24] + 801413e: f5a0 330e sub.w r3, r0, #145408 @ 0x23800 + 8014142: f5a3 732c sub.w r3, r3, #688 @ 0x2b0 + 8014146: fb93 f1f1 sdiv r1, r3, r1 + 801414a: 4b36 ldr r3, [pc, #216] @ (8014224 ) + 801414c: f240 5cb4 movw ip, #1460 @ 0x5b4 + 8014150: fb03 0001 mla r0, r3, r1, r0 + 8014154: f648 63ac movw r3, #36524 @ 0x8eac + 8014158: fbb0 f3f3 udiv r3, r0, r3 + 801415c: fbb0 f2fc udiv r2, r0, ip + 8014160: 4403 add r3, r0 + 8014162: 1a9b subs r3, r3, r2 + 8014164: 4a30 ldr r2, [pc, #192] @ (8014228 ) + 8014166: f240 176d movw r7, #365 @ 0x16d + 801416a: fbb0 f2f2 udiv r2, r0, r2 + 801416e: 1a9b subs r3, r3, r2 + 8014170: fbb3 f2f7 udiv r2, r3, r7 + 8014174: 2664 movs r6, #100 @ 0x64 + 8014176: fbb3 f3fc udiv r3, r3, ip + 801417a: fbb2 f5f6 udiv r5, r2, r6 + 801417e: 1aeb subs r3, r5, r3 + 8014180: 4403 add r3, r0 + 8014182: 2099 movs r0, #153 @ 0x99 + 8014184: fb07 3312 mls r3, r7, r2, r3 + 8014188: eb03 0783 add.w r7, r3, r3, lsl #2 + 801418c: 3702 adds r7, #2 + 801418e: fbb7 fcf0 udiv ip, r7, r0 + 8014192: f04f 0805 mov.w r8, #5 + 8014196: fb00 f00c mul.w r0, r0, ip + 801419a: 3002 adds r0, #2 + 801419c: fbb0 f0f8 udiv r0, r0, r8 + 80141a0: f103 0e01 add.w lr, r3, #1 + 80141a4: ebae 0000 sub.w r0, lr, r0 + 80141a8: f240 5ef9 movw lr, #1529 @ 0x5f9 + 80141ac: 4577 cmp r7, lr + 80141ae: bf8c ite hi + 80141b0: f06f 0709 mvnhi.w r7, #9 + 80141b4: 2702 movls r7, #2 + 80141b6: 4467 add r7, ip + 80141b8: f44f 7cc8 mov.w ip, #400 @ 0x190 + 80141bc: fb0c 2101 mla r1, ip, r1, r2 + 80141c0: 2f01 cmp r7, #1 + 80141c2: bf98 it ls + 80141c4: 3101 addls r1, #1 + 80141c6: f5b3 7f99 cmp.w r3, #306 @ 0x132 + 80141ca: d312 bcc.n 80141f2 + 80141cc: f5a3 7399 sub.w r3, r3, #306 @ 0x132 + 80141d0: 61e3 str r3, [r4, #28] + 80141d2: 2300 movs r3, #0 + 80141d4: f2a1 716c subw r1, r1, #1900 @ 0x76c + 80141d8: 60e0 str r0, [r4, #12] + 80141da: e9c4 7104 strd r7, r1, [r4, #16] + 80141de: 4620 mov r0, r4 + 80141e0: 6223 str r3, [r4, #32] + 80141e2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80141e6: 2800 cmp r0, #0 + 80141e8: 61a3 str r3, [r4, #24] + 80141ea: dba8 blt.n 801413e + 80141ec: fb90 f1f1 sdiv r1, r0, r1 + 80141f0: e7ab b.n 801414a + 80141f2: f012 0f03 tst.w r2, #3 + 80141f6: d102 bne.n 80141fe + 80141f8: fb06 2515 mls r5, r6, r5, r2 + 80141fc: b95d cbnz r5, 8014216 + 80141fe: f44f 75c8 mov.w r5, #400 @ 0x190 + 8014202: fbb2 f6f5 udiv r6, r2, r5 + 8014206: fb05 2216 mls r2, r5, r6, r2 + 801420a: fab2 f282 clz r2, r2 + 801420e: 0952 lsrs r2, r2, #5 + 8014210: 333b adds r3, #59 @ 0x3b + 8014212: 4413 add r3, r2 + 8014214: e7dc b.n 80141d0 + 8014216: 2201 movs r2, #1 + 8014218: e7fa b.n 8014210 + 801421a: bf00 nop + 801421c: 00015180 .word 0x00015180 + 8014220: 00023ab1 .word 0x00023ab1 + 8014224: fffdc54f .word 0xfffdc54f + 8014228: 00023ab0 .word 0x00023ab0 + +0801422c <__errno>: + 801422c: 4b01 ldr r3, [pc, #4] @ (8014234 <__errno+0x8>) + 801422e: 6818 ldr r0, [r3, #0] + 8014230: 4770 bx lr + 8014232: bf00 nop + 8014234: 20000084 .word 0x20000084 + +08014238 <__libc_init_array>: + 8014238: b570 push {r4, r5, r6, lr} + 801423a: 2600 movs r6, #0 + 801423c: 4d0c ldr r5, [pc, #48] @ (8014270 <__libc_init_array+0x38>) + 801423e: 4c0d ldr r4, [pc, #52] @ (8014274 <__libc_init_array+0x3c>) + 8014240: 1b64 subs r4, r4, r5 + 8014242: 10a4 asrs r4, r4, #2 + 8014244: 42a6 cmp r6, r4 + 8014246: d109 bne.n 801425c <__libc_init_array+0x24> + 8014248: f002 f906 bl 8016458 <_init> + 801424c: 2600 movs r6, #0 + 801424e: 4d0a ldr r5, [pc, #40] @ (8014278 <__libc_init_array+0x40>) + 8014250: 4c0a ldr r4, [pc, #40] @ (801427c <__libc_init_array+0x44>) + 8014252: 1b64 subs r4, r4, r5 + 8014254: 10a4 asrs r4, r4, #2 + 8014256: 42a6 cmp r6, r4 + 8014258: d105 bne.n 8014266 <__libc_init_array+0x2e> + 801425a: bd70 pop {r4, r5, r6, pc} + 801425c: f855 3b04 ldr.w r3, [r5], #4 + 8014260: 4798 blx r3 + 8014262: 3601 adds r6, #1 + 8014264: e7ee b.n 8014244 <__libc_init_array+0xc> + 8014266: f855 3b04 ldr.w r3, [r5], #4 + 801426a: 4798 blx r3 + 801426c: 3601 adds r6, #1 + 801426e: e7f2 b.n 8014256 <__libc_init_array+0x1e> + 8014270: 08016ffc .word 0x08016ffc + 8014274: 08016ffc .word 0x08016ffc + 8014278: 08016ffc .word 0x08016ffc + 801427c: 08017000 .word 0x08017000 + +08014280 <__retarget_lock_init_recursive>: + 8014280: 4770 bx lr + +08014282 <__retarget_lock_acquire_recursive>: + 8014282: 4770 bx lr + +08014284 <__retarget_lock_release_recursive>: + 8014284: 4770 bx lr + ... + +08014288 <_localeconv_r>: + 8014288: 4800 ldr r0, [pc, #0] @ (801428c <_localeconv_r+0x4>) + 801428a: 4770 bx lr + 801428c: 200001c4 .word 0x200001c4 + +08014290 : + 8014290: 4603 mov r3, r0 + 8014292: b510 push {r4, lr} + 8014294: b2c9 uxtb r1, r1 + 8014296: 4402 add r2, r0 + 8014298: 4293 cmp r3, r2 + 801429a: 4618 mov r0, r3 + 801429c: d101 bne.n 80142a2 + 801429e: 2000 movs r0, #0 + 80142a0: e003 b.n 80142aa + 80142a2: 7804 ldrb r4, [r0, #0] + 80142a4: 3301 adds r3, #1 + 80142a6: 428c cmp r4, r1 + 80142a8: d1f6 bne.n 8014298 + 80142aa: bd10 pop {r4, pc} + +080142ac : + 80142ac: 440a add r2, r1 + 80142ae: 4291 cmp r1, r2 + 80142b0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 80142b4: d100 bne.n 80142b8 + 80142b6: 4770 bx lr + 80142b8: b510 push {r4, lr} + 80142ba: f811 4b01 ldrb.w r4, [r1], #1 + 80142be: 4291 cmp r1, r2 + 80142c0: f803 4f01 strb.w r4, [r3, #1]! + 80142c4: d1f9 bne.n 80142ba + 80142c6: bd10 pop {r4, pc} + +080142c8 <__assert_func>: + 80142c8: b51f push {r0, r1, r2, r3, r4, lr} + 80142ca: 4614 mov r4, r2 + 80142cc: 461a mov r2, r3 + 80142ce: 4b09 ldr r3, [pc, #36] @ (80142f4 <__assert_func+0x2c>) + 80142d0: 4605 mov r5, r0 + 80142d2: 681b ldr r3, [r3, #0] + 80142d4: 68d8 ldr r0, [r3, #12] + 80142d6: b14c cbz r4, 80142ec <__assert_func+0x24> + 80142d8: 4b07 ldr r3, [pc, #28] @ (80142f8 <__assert_func+0x30>) + 80142da: e9cd 3401 strd r3, r4, [sp, #4] + 80142de: 9100 str r1, [sp, #0] + 80142e0: 462b mov r3, r5 + 80142e2: 4906 ldr r1, [pc, #24] @ (80142fc <__assert_func+0x34>) + 80142e4: f001 fe20 bl 8015f28 + 80142e8: f001 ffe6 bl 80162b8 + 80142ec: 4b04 ldr r3, [pc, #16] @ (8014300 <__assert_func+0x38>) + 80142ee: 461c mov r4, r3 + 80142f0: e7f3 b.n 80142da <__assert_func+0x12> + 80142f2: bf00 nop + 80142f4: 20000084 .word 0x20000084 + 80142f8: 08016cc7 .word 0x08016cc7 + 80142fc: 08016cd4 .word 0x08016cd4 + 8014300: 08016d02 .word 0x08016d02 + +08014304 : + 8014304: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8014308: 6903 ldr r3, [r0, #16] + 801430a: 690c ldr r4, [r1, #16] + 801430c: 4607 mov r7, r0 + 801430e: 42a3 cmp r3, r4 + 8014310: db7e blt.n 8014410 + 8014312: 3c01 subs r4, #1 + 8014314: 00a3 lsls r3, r4, #2 + 8014316: f100 0514 add.w r5, r0, #20 + 801431a: f101 0814 add.w r8, r1, #20 + 801431e: 9300 str r3, [sp, #0] + 8014320: eb05 0384 add.w r3, r5, r4, lsl #2 + 8014324: 9301 str r3, [sp, #4] + 8014326: f858 3024 ldr.w r3, [r8, r4, lsl #2] + 801432a: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 801432e: 3301 adds r3, #1 + 8014330: 429a cmp r2, r3 + 8014332: fbb2 f6f3 udiv r6, r2, r3 + 8014336: eb08 0984 add.w r9, r8, r4, lsl #2 + 801433a: d32e bcc.n 801439a + 801433c: f04f 0a00 mov.w sl, #0 + 8014340: 46c4 mov ip, r8 + 8014342: 46ae mov lr, r5 + 8014344: 46d3 mov fp, sl + 8014346: f85c 3b04 ldr.w r3, [ip], #4 + 801434a: b298 uxth r0, r3 + 801434c: fb06 a000 mla r0, r6, r0, sl + 8014350: 0c1b lsrs r3, r3, #16 + 8014352: 0c02 lsrs r2, r0, #16 + 8014354: fb06 2303 mla r3, r6, r3, r2 + 8014358: f8de 2000 ldr.w r2, [lr] + 801435c: b280 uxth r0, r0 + 801435e: b292 uxth r2, r2 + 8014360: 1a12 subs r2, r2, r0 + 8014362: 445a add r2, fp + 8014364: f8de 0000 ldr.w r0, [lr] + 8014368: ea4f 4a13 mov.w sl, r3, lsr #16 + 801436c: b29b uxth r3, r3 + 801436e: ebc3 4322 rsb r3, r3, r2, asr #16 + 8014372: eb03 4310 add.w r3, r3, r0, lsr #16 + 8014376: b292 uxth r2, r2 + 8014378: ea42 4203 orr.w r2, r2, r3, lsl #16 + 801437c: 45e1 cmp r9, ip + 801437e: ea4f 4b23 mov.w fp, r3, asr #16 + 8014382: f84e 2b04 str.w r2, [lr], #4 + 8014386: d2de bcs.n 8014346 + 8014388: 9b00 ldr r3, [sp, #0] + 801438a: 58eb ldr r3, [r5, r3] + 801438c: b92b cbnz r3, 801439a + 801438e: 9b01 ldr r3, [sp, #4] + 8014390: 3b04 subs r3, #4 + 8014392: 429d cmp r5, r3 + 8014394: 461a mov r2, r3 + 8014396: d32f bcc.n 80143f8 + 8014398: 613c str r4, [r7, #16] + 801439a: 4638 mov r0, r7 + 801439c: f001 fc78 bl 8015c90 <__mcmp> + 80143a0: 2800 cmp r0, #0 + 80143a2: db25 blt.n 80143f0 + 80143a4: 4629 mov r1, r5 + 80143a6: 2000 movs r0, #0 + 80143a8: f858 2b04 ldr.w r2, [r8], #4 + 80143ac: f8d1 c000 ldr.w ip, [r1] + 80143b0: fa1f fe82 uxth.w lr, r2 + 80143b4: fa1f f38c uxth.w r3, ip + 80143b8: eba3 030e sub.w r3, r3, lr + 80143bc: 4403 add r3, r0 + 80143be: 0c12 lsrs r2, r2, #16 + 80143c0: ebc2 4223 rsb r2, r2, r3, asr #16 + 80143c4: eb02 421c add.w r2, r2, ip, lsr #16 + 80143c8: b29b uxth r3, r3 + 80143ca: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80143ce: 45c1 cmp r9, r8 + 80143d0: ea4f 4022 mov.w r0, r2, asr #16 + 80143d4: f841 3b04 str.w r3, [r1], #4 + 80143d8: d2e6 bcs.n 80143a8 + 80143da: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 80143de: eb05 0384 add.w r3, r5, r4, lsl #2 + 80143e2: b922 cbnz r2, 80143ee + 80143e4: 3b04 subs r3, #4 + 80143e6: 429d cmp r5, r3 + 80143e8: 461a mov r2, r3 + 80143ea: d30b bcc.n 8014404 + 80143ec: 613c str r4, [r7, #16] + 80143ee: 3601 adds r6, #1 + 80143f0: 4630 mov r0, r6 + 80143f2: b003 add sp, #12 + 80143f4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80143f8: 6812 ldr r2, [r2, #0] + 80143fa: 3b04 subs r3, #4 + 80143fc: 2a00 cmp r2, #0 + 80143fe: d1cb bne.n 8014398 + 8014400: 3c01 subs r4, #1 + 8014402: e7c6 b.n 8014392 + 8014404: 6812 ldr r2, [r2, #0] + 8014406: 3b04 subs r3, #4 + 8014408: 2a00 cmp r2, #0 + 801440a: d1ef bne.n 80143ec + 801440c: 3c01 subs r4, #1 + 801440e: e7ea b.n 80143e6 + 8014410: 2000 movs r0, #0 + 8014412: e7ee b.n 80143f2 + 8014414: 0000 movs r0, r0 + ... + +08014418 <_dtoa_r>: + 8014418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801441c: 4614 mov r4, r2 + 801441e: 461d mov r5, r3 + 8014420: 69c7 ldr r7, [r0, #28] + 8014422: b097 sub sp, #92 @ 0x5c + 8014424: 4681 mov r9, r0 + 8014426: e9cd 4506 strd r4, r5, [sp, #24] + 801442a: 9e23 ldr r6, [sp, #140] @ 0x8c + 801442c: b97f cbnz r7, 801444e <_dtoa_r+0x36> + 801442e: 2010 movs r0, #16 + 8014430: f001 f85e bl 80154f0 + 8014434: 4602 mov r2, r0 + 8014436: f8c9 001c str.w r0, [r9, #28] + 801443a: b920 cbnz r0, 8014446 <_dtoa_r+0x2e> + 801443c: 21ef movs r1, #239 @ 0xef + 801443e: 4bac ldr r3, [pc, #688] @ (80146f0 <_dtoa_r+0x2d8>) + 8014440: 48ac ldr r0, [pc, #688] @ (80146f4 <_dtoa_r+0x2dc>) + 8014442: f7ff ff41 bl 80142c8 <__assert_func> + 8014446: e9c0 7701 strd r7, r7, [r0, #4] + 801444a: 6007 str r7, [r0, #0] + 801444c: 60c7 str r7, [r0, #12] + 801444e: f8d9 301c ldr.w r3, [r9, #28] + 8014452: 6819 ldr r1, [r3, #0] + 8014454: b159 cbz r1, 801446e <_dtoa_r+0x56> + 8014456: 685a ldr r2, [r3, #4] + 8014458: 2301 movs r3, #1 + 801445a: 4093 lsls r3, r2 + 801445c: 604a str r2, [r1, #4] + 801445e: 608b str r3, [r1, #8] + 8014460: 4648 mov r0, r9 + 8014462: f001 f9e3 bl 801582c <_Bfree> + 8014466: 2200 movs r2, #0 + 8014468: f8d9 301c ldr.w r3, [r9, #28] + 801446c: 601a str r2, [r3, #0] + 801446e: 1e2b subs r3, r5, #0 + 8014470: bfaf iteee ge + 8014472: 2300 movge r3, #0 + 8014474: 2201 movlt r2, #1 + 8014476: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 + 801447a: 9307 strlt r3, [sp, #28] + 801447c: bfa8 it ge + 801447e: 6033 strge r3, [r6, #0] + 8014480: f8dd 801c ldr.w r8, [sp, #28] + 8014484: 4b9c ldr r3, [pc, #624] @ (80146f8 <_dtoa_r+0x2e0>) + 8014486: bfb8 it lt + 8014488: 6032 strlt r2, [r6, #0] + 801448a: ea33 0308 bics.w r3, r3, r8 + 801448e: d112 bne.n 80144b6 <_dtoa_r+0x9e> + 8014490: f242 730f movw r3, #9999 @ 0x270f + 8014494: 9a22 ldr r2, [sp, #136] @ 0x88 + 8014496: 6013 str r3, [r2, #0] + 8014498: f3c8 0313 ubfx r3, r8, #0, #20 + 801449c: 4323 orrs r3, r4 + 801449e: f000 855e beq.w 8014f5e <_dtoa_r+0xb46> + 80144a2: 9b24 ldr r3, [sp, #144] @ 0x90 + 80144a4: f8df a254 ldr.w sl, [pc, #596] @ 80146fc <_dtoa_r+0x2e4> + 80144a8: 2b00 cmp r3, #0 + 80144aa: f000 8560 beq.w 8014f6e <_dtoa_r+0xb56> + 80144ae: f10a 0303 add.w r3, sl, #3 + 80144b2: f000 bd5a b.w 8014f6a <_dtoa_r+0xb52> + 80144b6: e9dd 2306 ldrd r2, r3, [sp, #24] + 80144ba: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 + 80144be: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 + 80144c2: 2200 movs r2, #0 + 80144c4: 2300 movs r3, #0 + 80144c6: f7f4 fadb bl 8008a80 <__aeabi_dcmpeq> + 80144ca: 4607 mov r7, r0 + 80144cc: b158 cbz r0, 80144e6 <_dtoa_r+0xce> + 80144ce: 2301 movs r3, #1 + 80144d0: 9a22 ldr r2, [sp, #136] @ 0x88 + 80144d2: 6013 str r3, [r2, #0] + 80144d4: 9b24 ldr r3, [sp, #144] @ 0x90 + 80144d6: b113 cbz r3, 80144de <_dtoa_r+0xc6> + 80144d8: 4b89 ldr r3, [pc, #548] @ (8014700 <_dtoa_r+0x2e8>) + 80144da: 9a24 ldr r2, [sp, #144] @ 0x90 + 80144dc: 6013 str r3, [r2, #0] + 80144de: f8df a224 ldr.w sl, [pc, #548] @ 8014704 <_dtoa_r+0x2ec> + 80144e2: f000 bd44 b.w 8014f6e <_dtoa_r+0xb56> + 80144e6: ab14 add r3, sp, #80 @ 0x50 + 80144e8: 9301 str r3, [sp, #4] + 80144ea: ab15 add r3, sp, #84 @ 0x54 + 80144ec: 9300 str r3, [sp, #0] + 80144ee: 4648 mov r0, r9 + 80144f0: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 + 80144f4: f001 fc7c bl 8015df0 <__d2b> + 80144f8: f3c8 560a ubfx r6, r8, #20, #11 + 80144fc: 9003 str r0, [sp, #12] + 80144fe: 2e00 cmp r6, #0 + 8014500: d078 beq.n 80145f4 <_dtoa_r+0x1dc> + 8014502: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 + 8014506: 9b0d ldr r3, [sp, #52] @ 0x34 + 8014508: f2a6 36ff subw r6, r6, #1023 @ 0x3ff + 801450c: f3c3 0313 ubfx r3, r3, #0, #20 + 8014510: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 + 8014514: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 + 8014518: 9712 str r7, [sp, #72] @ 0x48 + 801451a: 4619 mov r1, r3 + 801451c: 2200 movs r2, #0 + 801451e: 4b7a ldr r3, [pc, #488] @ (8014708 <_dtoa_r+0x2f0>) + 8014520: f7f3 fe8e bl 8008240 <__aeabi_dsub> + 8014524: a36c add r3, pc, #432 @ (adr r3, 80146d8 <_dtoa_r+0x2c0>) + 8014526: e9d3 2300 ldrd r2, r3, [r3] + 801452a: f7f4 f841 bl 80085b0 <__aeabi_dmul> + 801452e: a36c add r3, pc, #432 @ (adr r3, 80146e0 <_dtoa_r+0x2c8>) + 8014530: e9d3 2300 ldrd r2, r3, [r3] + 8014534: f7f3 fe86 bl 8008244 <__adddf3> + 8014538: 4604 mov r4, r0 + 801453a: 4630 mov r0, r6 + 801453c: 460d mov r5, r1 + 801453e: f7f3 ffcd bl 80084dc <__aeabi_i2d> + 8014542: a369 add r3, pc, #420 @ (adr r3, 80146e8 <_dtoa_r+0x2d0>) + 8014544: e9d3 2300 ldrd r2, r3, [r3] + 8014548: f7f4 f832 bl 80085b0 <__aeabi_dmul> + 801454c: 4602 mov r2, r0 + 801454e: 460b mov r3, r1 + 8014550: 4620 mov r0, r4 + 8014552: 4629 mov r1, r5 + 8014554: f7f3 fe76 bl 8008244 <__adddf3> + 8014558: 4604 mov r4, r0 + 801455a: 460d mov r5, r1 + 801455c: f7f4 fad8 bl 8008b10 <__aeabi_d2iz> + 8014560: 2200 movs r2, #0 + 8014562: 4607 mov r7, r0 + 8014564: 2300 movs r3, #0 + 8014566: 4620 mov r0, r4 + 8014568: 4629 mov r1, r5 + 801456a: f7f4 fa93 bl 8008a94 <__aeabi_dcmplt> + 801456e: b140 cbz r0, 8014582 <_dtoa_r+0x16a> + 8014570: 4638 mov r0, r7 + 8014572: f7f3 ffb3 bl 80084dc <__aeabi_i2d> + 8014576: 4622 mov r2, r4 + 8014578: 462b mov r3, r5 + 801457a: f7f4 fa81 bl 8008a80 <__aeabi_dcmpeq> + 801457e: b900 cbnz r0, 8014582 <_dtoa_r+0x16a> + 8014580: 3f01 subs r7, #1 + 8014582: 2f16 cmp r7, #22 + 8014584: d854 bhi.n 8014630 <_dtoa_r+0x218> + 8014586: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 + 801458a: 4b60 ldr r3, [pc, #384] @ (801470c <_dtoa_r+0x2f4>) + 801458c: eb03 03c7 add.w r3, r3, r7, lsl #3 + 8014590: e9d3 2300 ldrd r2, r3, [r3] + 8014594: f7f4 fa7e bl 8008a94 <__aeabi_dcmplt> + 8014598: 2800 cmp r0, #0 + 801459a: d04b beq.n 8014634 <_dtoa_r+0x21c> + 801459c: 2300 movs r3, #0 + 801459e: 3f01 subs r7, #1 + 80145a0: 930f str r3, [sp, #60] @ 0x3c + 80145a2: 9b14 ldr r3, [sp, #80] @ 0x50 + 80145a4: 1b9b subs r3, r3, r6 + 80145a6: 1e5a subs r2, r3, #1 + 80145a8: bf49 itett mi + 80145aa: f1c3 0301 rsbmi r3, r3, #1 + 80145ae: 2300 movpl r3, #0 + 80145b0: 9304 strmi r3, [sp, #16] + 80145b2: 2300 movmi r3, #0 + 80145b4: 9209 str r2, [sp, #36] @ 0x24 + 80145b6: bf54 ite pl + 80145b8: 9304 strpl r3, [sp, #16] + 80145ba: 9309 strmi r3, [sp, #36] @ 0x24 + 80145bc: 2f00 cmp r7, #0 + 80145be: db3b blt.n 8014638 <_dtoa_r+0x220> + 80145c0: 9b09 ldr r3, [sp, #36] @ 0x24 + 80145c2: 970e str r7, [sp, #56] @ 0x38 + 80145c4: 443b add r3, r7 + 80145c6: 9309 str r3, [sp, #36] @ 0x24 + 80145c8: 2300 movs r3, #0 + 80145ca: 930a str r3, [sp, #40] @ 0x28 + 80145cc: 9b20 ldr r3, [sp, #128] @ 0x80 + 80145ce: 2b09 cmp r3, #9 + 80145d0: d865 bhi.n 801469e <_dtoa_r+0x286> + 80145d2: 2b05 cmp r3, #5 + 80145d4: bfc4 itt gt + 80145d6: 3b04 subgt r3, #4 + 80145d8: 9320 strgt r3, [sp, #128] @ 0x80 + 80145da: 9b20 ldr r3, [sp, #128] @ 0x80 + 80145dc: bfc8 it gt + 80145de: 2400 movgt r4, #0 + 80145e0: f1a3 0302 sub.w r3, r3, #2 + 80145e4: bfd8 it le + 80145e6: 2401 movle r4, #1 + 80145e8: 2b03 cmp r3, #3 + 80145ea: d864 bhi.n 80146b6 <_dtoa_r+0x29e> + 80145ec: e8df f003 tbb [pc, r3] + 80145f0: 2c385553 .word 0x2c385553 + 80145f4: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 + 80145f8: 441e add r6, r3 + 80145fa: f206 4332 addw r3, r6, #1074 @ 0x432 + 80145fe: 2b20 cmp r3, #32 + 8014600: bfc1 itttt gt + 8014602: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 + 8014606: fa08 f803 lslgt.w r8, r8, r3 + 801460a: f206 4312 addwgt r3, r6, #1042 @ 0x412 + 801460e: fa24 f303 lsrgt.w r3, r4, r3 + 8014612: bfd6 itet le + 8014614: f1c3 0320 rsble r3, r3, #32 + 8014618: ea48 0003 orrgt.w r0, r8, r3 + 801461c: fa04 f003 lslle.w r0, r4, r3 + 8014620: f7f3 ff4c bl 80084bc <__aeabi_ui2d> + 8014624: 2201 movs r2, #1 + 8014626: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 + 801462a: 3e01 subs r6, #1 + 801462c: 9212 str r2, [sp, #72] @ 0x48 + 801462e: e774 b.n 801451a <_dtoa_r+0x102> + 8014630: 2301 movs r3, #1 + 8014632: e7b5 b.n 80145a0 <_dtoa_r+0x188> + 8014634: 900f str r0, [sp, #60] @ 0x3c + 8014636: e7b4 b.n 80145a2 <_dtoa_r+0x18a> + 8014638: 9b04 ldr r3, [sp, #16] + 801463a: 1bdb subs r3, r3, r7 + 801463c: 9304 str r3, [sp, #16] + 801463e: 427b negs r3, r7 + 8014640: 930a str r3, [sp, #40] @ 0x28 + 8014642: 2300 movs r3, #0 + 8014644: 930e str r3, [sp, #56] @ 0x38 + 8014646: e7c1 b.n 80145cc <_dtoa_r+0x1b4> + 8014648: 2301 movs r3, #1 + 801464a: 930b str r3, [sp, #44] @ 0x2c + 801464c: 9b21 ldr r3, [sp, #132] @ 0x84 + 801464e: eb07 0b03 add.w fp, r7, r3 + 8014652: f10b 0301 add.w r3, fp, #1 + 8014656: 2b01 cmp r3, #1 + 8014658: 9308 str r3, [sp, #32] + 801465a: bfb8 it lt + 801465c: 2301 movlt r3, #1 + 801465e: e006 b.n 801466e <_dtoa_r+0x256> + 8014660: 2301 movs r3, #1 + 8014662: 930b str r3, [sp, #44] @ 0x2c + 8014664: 9b21 ldr r3, [sp, #132] @ 0x84 + 8014666: 2b00 cmp r3, #0 + 8014668: dd28 ble.n 80146bc <_dtoa_r+0x2a4> + 801466a: 469b mov fp, r3 + 801466c: 9308 str r3, [sp, #32] + 801466e: 2100 movs r1, #0 + 8014670: 2204 movs r2, #4 + 8014672: f8d9 001c ldr.w r0, [r9, #28] + 8014676: f102 0514 add.w r5, r2, #20 + 801467a: 429d cmp r5, r3 + 801467c: d926 bls.n 80146cc <_dtoa_r+0x2b4> + 801467e: 6041 str r1, [r0, #4] + 8014680: 4648 mov r0, r9 + 8014682: f001 f893 bl 80157ac <_Balloc> + 8014686: 4682 mov sl, r0 + 8014688: 2800 cmp r0, #0 + 801468a: d143 bne.n 8014714 <_dtoa_r+0x2fc> + 801468c: 4602 mov r2, r0 + 801468e: f240 11af movw r1, #431 @ 0x1af + 8014692: 4b1f ldr r3, [pc, #124] @ (8014710 <_dtoa_r+0x2f8>) + 8014694: e6d4 b.n 8014440 <_dtoa_r+0x28> + 8014696: 2300 movs r3, #0 + 8014698: e7e3 b.n 8014662 <_dtoa_r+0x24a> + 801469a: 2300 movs r3, #0 + 801469c: e7d5 b.n 801464a <_dtoa_r+0x232> + 801469e: 2401 movs r4, #1 + 80146a0: 2300 movs r3, #0 + 80146a2: 940b str r4, [sp, #44] @ 0x2c + 80146a4: 9320 str r3, [sp, #128] @ 0x80 + 80146a6: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff + 80146aa: 2200 movs r2, #0 + 80146ac: 2312 movs r3, #18 + 80146ae: f8cd b020 str.w fp, [sp, #32] + 80146b2: 9221 str r2, [sp, #132] @ 0x84 + 80146b4: e7db b.n 801466e <_dtoa_r+0x256> + 80146b6: 2301 movs r3, #1 + 80146b8: 930b str r3, [sp, #44] @ 0x2c + 80146ba: e7f4 b.n 80146a6 <_dtoa_r+0x28e> + 80146bc: f04f 0b01 mov.w fp, #1 + 80146c0: 465b mov r3, fp + 80146c2: f8cd b020 str.w fp, [sp, #32] + 80146c6: f8cd b084 str.w fp, [sp, #132] @ 0x84 + 80146ca: e7d0 b.n 801466e <_dtoa_r+0x256> + 80146cc: 3101 adds r1, #1 + 80146ce: 0052 lsls r2, r2, #1 + 80146d0: e7d1 b.n 8014676 <_dtoa_r+0x25e> + 80146d2: bf00 nop + 80146d4: f3af 8000 nop.w + 80146d8: 636f4361 .word 0x636f4361 + 80146dc: 3fd287a7 .word 0x3fd287a7 + 80146e0: 8b60c8b3 .word 0x8b60c8b3 + 80146e4: 3fc68a28 .word 0x3fc68a28 + 80146e8: 509f79fb .word 0x509f79fb + 80146ec: 3fd34413 .word 0x3fd34413 + 80146f0: 08016c58 .word 0x08016c58 + 80146f4: 08016d10 .word 0x08016d10 + 80146f8: 7ff00000 .word 0x7ff00000 + 80146fc: 08016d0c .word 0x08016d0c + 8014700: 08016c35 .word 0x08016c35 + 8014704: 08016c34 .word 0x08016c34 + 8014708: 3ff80000 .word 0x3ff80000 + 801470c: 08016e28 .word 0x08016e28 + 8014710: 08016d68 .word 0x08016d68 + 8014714: f8d9 301c ldr.w r3, [r9, #28] + 8014718: 6018 str r0, [r3, #0] + 801471a: 9b08 ldr r3, [sp, #32] + 801471c: 2b0e cmp r3, #14 + 801471e: f200 80a1 bhi.w 8014864 <_dtoa_r+0x44c> + 8014722: 2c00 cmp r4, #0 + 8014724: f000 809e beq.w 8014864 <_dtoa_r+0x44c> + 8014728: 2f00 cmp r7, #0 + 801472a: dd33 ble.n 8014794 <_dtoa_r+0x37c> + 801472c: 4b9c ldr r3, [pc, #624] @ (80149a0 <_dtoa_r+0x588>) + 801472e: f007 020f and.w r2, r7, #15 + 8014732: eb03 03c2 add.w r3, r3, r2, lsl #3 + 8014736: 05f8 lsls r0, r7, #23 + 8014738: e9d3 3400 ldrd r3, r4, [r3] + 801473c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 + 8014740: ea4f 1427 mov.w r4, r7, asr #4 + 8014744: d516 bpl.n 8014774 <_dtoa_r+0x35c> + 8014746: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 + 801474a: 4b96 ldr r3, [pc, #600] @ (80149a4 <_dtoa_r+0x58c>) + 801474c: 2603 movs r6, #3 + 801474e: e9d3 2308 ldrd r2, r3, [r3, #32] + 8014752: f7f4 f857 bl 8008804 <__aeabi_ddiv> + 8014756: e9cd 0106 strd r0, r1, [sp, #24] + 801475a: f004 040f and.w r4, r4, #15 + 801475e: 4d91 ldr r5, [pc, #580] @ (80149a4 <_dtoa_r+0x58c>) + 8014760: b954 cbnz r4, 8014778 <_dtoa_r+0x360> + 8014762: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 + 8014766: e9dd 0106 ldrd r0, r1, [sp, #24] + 801476a: f7f4 f84b bl 8008804 <__aeabi_ddiv> + 801476e: e9cd 0106 strd r0, r1, [sp, #24] + 8014772: e028 b.n 80147c6 <_dtoa_r+0x3ae> + 8014774: 2602 movs r6, #2 + 8014776: e7f2 b.n 801475e <_dtoa_r+0x346> + 8014778: 07e1 lsls r1, r4, #31 + 801477a: d508 bpl.n 801478e <_dtoa_r+0x376> + 801477c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 + 8014780: e9d5 2300 ldrd r2, r3, [r5] + 8014784: f7f3 ff14 bl 80085b0 <__aeabi_dmul> + 8014788: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 + 801478c: 3601 adds r6, #1 + 801478e: 1064 asrs r4, r4, #1 + 8014790: 3508 adds r5, #8 + 8014792: e7e5 b.n 8014760 <_dtoa_r+0x348> + 8014794: f000 80af beq.w 80148f6 <_dtoa_r+0x4de> + 8014798: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 + 801479c: 427c negs r4, r7 + 801479e: 4b80 ldr r3, [pc, #512] @ (80149a0 <_dtoa_r+0x588>) + 80147a0: f004 020f and.w r2, r4, #15 + 80147a4: eb03 03c2 add.w r3, r3, r2, lsl #3 + 80147a8: e9d3 2300 ldrd r2, r3, [r3] + 80147ac: f7f3 ff00 bl 80085b0 <__aeabi_dmul> + 80147b0: 2602 movs r6, #2 + 80147b2: 2300 movs r3, #0 + 80147b4: e9cd 0106 strd r0, r1, [sp, #24] + 80147b8: 4d7a ldr r5, [pc, #488] @ (80149a4 <_dtoa_r+0x58c>) + 80147ba: 1124 asrs r4, r4, #4 + 80147bc: 2c00 cmp r4, #0 + 80147be: f040 808f bne.w 80148e0 <_dtoa_r+0x4c8> + 80147c2: 2b00 cmp r3, #0 + 80147c4: d1d3 bne.n 801476e <_dtoa_r+0x356> + 80147c6: e9dd 4506 ldrd r4, r5, [sp, #24] + 80147ca: 9b0f ldr r3, [sp, #60] @ 0x3c + 80147cc: 2b00 cmp r3, #0 + 80147ce: f000 8094 beq.w 80148fa <_dtoa_r+0x4e2> + 80147d2: 2200 movs r2, #0 + 80147d4: 4620 mov r0, r4 + 80147d6: 4629 mov r1, r5 + 80147d8: 4b73 ldr r3, [pc, #460] @ (80149a8 <_dtoa_r+0x590>) + 80147da: f7f4 f95b bl 8008a94 <__aeabi_dcmplt> + 80147de: 2800 cmp r0, #0 + 80147e0: f000 808b beq.w 80148fa <_dtoa_r+0x4e2> + 80147e4: 9b08 ldr r3, [sp, #32] + 80147e6: 2b00 cmp r3, #0 + 80147e8: f000 8087 beq.w 80148fa <_dtoa_r+0x4e2> + 80147ec: f1bb 0f00 cmp.w fp, #0 + 80147f0: dd34 ble.n 801485c <_dtoa_r+0x444> + 80147f2: 4620 mov r0, r4 + 80147f4: 2200 movs r2, #0 + 80147f6: 4629 mov r1, r5 + 80147f8: 4b6c ldr r3, [pc, #432] @ (80149ac <_dtoa_r+0x594>) + 80147fa: f7f3 fed9 bl 80085b0 <__aeabi_dmul> + 80147fe: 465c mov r4, fp + 8014800: e9cd 0106 strd r0, r1, [sp, #24] + 8014804: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff + 8014808: 3601 adds r6, #1 + 801480a: 4630 mov r0, r6 + 801480c: f7f3 fe66 bl 80084dc <__aeabi_i2d> + 8014810: e9dd 2306 ldrd r2, r3, [sp, #24] + 8014814: f7f3 fecc bl 80085b0 <__aeabi_dmul> + 8014818: 2200 movs r2, #0 + 801481a: 4b65 ldr r3, [pc, #404] @ (80149b0 <_dtoa_r+0x598>) + 801481c: f7f3 fd12 bl 8008244 <__adddf3> + 8014820: 4605 mov r5, r0 + 8014822: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 + 8014826: 2c00 cmp r4, #0 + 8014828: d16a bne.n 8014900 <_dtoa_r+0x4e8> + 801482a: e9dd 0106 ldrd r0, r1, [sp, #24] + 801482e: 2200 movs r2, #0 + 8014830: 4b60 ldr r3, [pc, #384] @ (80149b4 <_dtoa_r+0x59c>) + 8014832: f7f3 fd05 bl 8008240 <__aeabi_dsub> + 8014836: 4602 mov r2, r0 + 8014838: 460b mov r3, r1 + 801483a: e9cd 2306 strd r2, r3, [sp, #24] + 801483e: 462a mov r2, r5 + 8014840: 4633 mov r3, r6 + 8014842: f7f4 f945 bl 8008ad0 <__aeabi_dcmpgt> + 8014846: 2800 cmp r0, #0 + 8014848: f040 8298 bne.w 8014d7c <_dtoa_r+0x964> + 801484c: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014850: 462a mov r2, r5 + 8014852: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 + 8014856: f7f4 f91d bl 8008a94 <__aeabi_dcmplt> + 801485a: bb38 cbnz r0, 80148ac <_dtoa_r+0x494> + 801485c: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 + 8014860: e9cd 3406 strd r3, r4, [sp, #24] + 8014864: 9b15 ldr r3, [sp, #84] @ 0x54 + 8014866: 2b00 cmp r3, #0 + 8014868: f2c0 8157 blt.w 8014b1a <_dtoa_r+0x702> + 801486c: 2f0e cmp r7, #14 + 801486e: f300 8154 bgt.w 8014b1a <_dtoa_r+0x702> + 8014872: 4b4b ldr r3, [pc, #300] @ (80149a0 <_dtoa_r+0x588>) + 8014874: eb03 03c7 add.w r3, r3, r7, lsl #3 + 8014878: e9d3 3400 ldrd r3, r4, [r3] + 801487c: e9cd 3404 strd r3, r4, [sp, #16] + 8014880: 9b21 ldr r3, [sp, #132] @ 0x84 + 8014882: 2b00 cmp r3, #0 + 8014884: f280 80e5 bge.w 8014a52 <_dtoa_r+0x63a> + 8014888: 9b08 ldr r3, [sp, #32] + 801488a: 2b00 cmp r3, #0 + 801488c: f300 80e1 bgt.w 8014a52 <_dtoa_r+0x63a> + 8014890: d10c bne.n 80148ac <_dtoa_r+0x494> + 8014892: e9dd 0104 ldrd r0, r1, [sp, #16] + 8014896: 2200 movs r2, #0 + 8014898: 4b46 ldr r3, [pc, #280] @ (80149b4 <_dtoa_r+0x59c>) + 801489a: f7f3 fe89 bl 80085b0 <__aeabi_dmul> + 801489e: e9dd 2306 ldrd r2, r3, [sp, #24] + 80148a2: f7f4 f90b bl 8008abc <__aeabi_dcmpge> + 80148a6: 2800 cmp r0, #0 + 80148a8: f000 8266 beq.w 8014d78 <_dtoa_r+0x960> + 80148ac: 2400 movs r4, #0 + 80148ae: 4625 mov r5, r4 + 80148b0: 9b21 ldr r3, [sp, #132] @ 0x84 + 80148b2: 4656 mov r6, sl + 80148b4: ea6f 0803 mvn.w r8, r3 + 80148b8: 2700 movs r7, #0 + 80148ba: 4621 mov r1, r4 + 80148bc: 4648 mov r0, r9 + 80148be: f000 ffb5 bl 801582c <_Bfree> + 80148c2: 2d00 cmp r5, #0 + 80148c4: f000 80bd beq.w 8014a42 <_dtoa_r+0x62a> + 80148c8: b12f cbz r7, 80148d6 <_dtoa_r+0x4be> + 80148ca: 42af cmp r7, r5 + 80148cc: d003 beq.n 80148d6 <_dtoa_r+0x4be> + 80148ce: 4639 mov r1, r7 + 80148d0: 4648 mov r0, r9 + 80148d2: f000 ffab bl 801582c <_Bfree> + 80148d6: 4629 mov r1, r5 + 80148d8: 4648 mov r0, r9 + 80148da: f000 ffa7 bl 801582c <_Bfree> + 80148de: e0b0 b.n 8014a42 <_dtoa_r+0x62a> + 80148e0: 07e2 lsls r2, r4, #31 + 80148e2: d505 bpl.n 80148f0 <_dtoa_r+0x4d8> + 80148e4: e9d5 2300 ldrd r2, r3, [r5] + 80148e8: f7f3 fe62 bl 80085b0 <__aeabi_dmul> + 80148ec: 2301 movs r3, #1 + 80148ee: 3601 adds r6, #1 + 80148f0: 1064 asrs r4, r4, #1 + 80148f2: 3508 adds r5, #8 + 80148f4: e762 b.n 80147bc <_dtoa_r+0x3a4> + 80148f6: 2602 movs r6, #2 + 80148f8: e765 b.n 80147c6 <_dtoa_r+0x3ae> + 80148fa: 46b8 mov r8, r7 + 80148fc: 9c08 ldr r4, [sp, #32] + 80148fe: e784 b.n 801480a <_dtoa_r+0x3f2> + 8014900: 4b27 ldr r3, [pc, #156] @ (80149a0 <_dtoa_r+0x588>) + 8014902: 990b ldr r1, [sp, #44] @ 0x2c + 8014904: eb03 03c4 add.w r3, r3, r4, lsl #3 + 8014908: e953 2302 ldrd r2, r3, [r3, #-8] + 801490c: 4454 add r4, sl + 801490e: 2900 cmp r1, #0 + 8014910: d054 beq.n 80149bc <_dtoa_r+0x5a4> + 8014912: 2000 movs r0, #0 + 8014914: 4928 ldr r1, [pc, #160] @ (80149b8 <_dtoa_r+0x5a0>) + 8014916: f7f3 ff75 bl 8008804 <__aeabi_ddiv> + 801491a: 4633 mov r3, r6 + 801491c: 462a mov r2, r5 + 801491e: f7f3 fc8f bl 8008240 <__aeabi_dsub> + 8014922: 4656 mov r6, sl + 8014924: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 + 8014928: e9dd 0106 ldrd r0, r1, [sp, #24] + 801492c: f7f4 f8f0 bl 8008b10 <__aeabi_d2iz> + 8014930: 4605 mov r5, r0 + 8014932: f7f3 fdd3 bl 80084dc <__aeabi_i2d> + 8014936: 4602 mov r2, r0 + 8014938: 460b mov r3, r1 + 801493a: e9dd 0106 ldrd r0, r1, [sp, #24] + 801493e: f7f3 fc7f bl 8008240 <__aeabi_dsub> + 8014942: 4602 mov r2, r0 + 8014944: 460b mov r3, r1 + 8014946: 3530 adds r5, #48 @ 0x30 + 8014948: e9cd 2306 strd r2, r3, [sp, #24] + 801494c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 + 8014950: f806 5b01 strb.w r5, [r6], #1 + 8014954: f7f4 f89e bl 8008a94 <__aeabi_dcmplt> + 8014958: 2800 cmp r0, #0 + 801495a: d172 bne.n 8014a42 <_dtoa_r+0x62a> + 801495c: e9dd 2306 ldrd r2, r3, [sp, #24] + 8014960: 2000 movs r0, #0 + 8014962: 4911 ldr r1, [pc, #68] @ (80149a8 <_dtoa_r+0x590>) + 8014964: f7f3 fc6c bl 8008240 <__aeabi_dsub> + 8014968: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 + 801496c: f7f4 f892 bl 8008a94 <__aeabi_dcmplt> + 8014970: 2800 cmp r0, #0 + 8014972: f040 80b4 bne.w 8014ade <_dtoa_r+0x6c6> + 8014976: 42a6 cmp r6, r4 + 8014978: f43f af70 beq.w 801485c <_dtoa_r+0x444> + 801497c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 + 8014980: 2200 movs r2, #0 + 8014982: 4b0a ldr r3, [pc, #40] @ (80149ac <_dtoa_r+0x594>) + 8014984: f7f3 fe14 bl 80085b0 <__aeabi_dmul> + 8014988: 2200 movs r2, #0 + 801498a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 + 801498e: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014992: 4b06 ldr r3, [pc, #24] @ (80149ac <_dtoa_r+0x594>) + 8014994: f7f3 fe0c bl 80085b0 <__aeabi_dmul> + 8014998: e9cd 0106 strd r0, r1, [sp, #24] + 801499c: e7c4 b.n 8014928 <_dtoa_r+0x510> + 801499e: bf00 nop + 80149a0: 08016e28 .word 0x08016e28 + 80149a4: 08016e00 .word 0x08016e00 + 80149a8: 3ff00000 .word 0x3ff00000 + 80149ac: 40240000 .word 0x40240000 + 80149b0: 401c0000 .word 0x401c0000 + 80149b4: 40140000 .word 0x40140000 + 80149b8: 3fe00000 .word 0x3fe00000 + 80149bc: 4631 mov r1, r6 + 80149be: 4628 mov r0, r5 + 80149c0: f7f3 fdf6 bl 80085b0 <__aeabi_dmul> + 80149c4: 4656 mov r6, sl + 80149c6: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 + 80149ca: 9413 str r4, [sp, #76] @ 0x4c + 80149cc: e9dd 0106 ldrd r0, r1, [sp, #24] + 80149d0: f7f4 f89e bl 8008b10 <__aeabi_d2iz> + 80149d4: 4605 mov r5, r0 + 80149d6: f7f3 fd81 bl 80084dc <__aeabi_i2d> + 80149da: 4602 mov r2, r0 + 80149dc: 460b mov r3, r1 + 80149de: e9dd 0106 ldrd r0, r1, [sp, #24] + 80149e2: f7f3 fc2d bl 8008240 <__aeabi_dsub> + 80149e6: 4602 mov r2, r0 + 80149e8: 460b mov r3, r1 + 80149ea: 3530 adds r5, #48 @ 0x30 + 80149ec: f806 5b01 strb.w r5, [r6], #1 + 80149f0: 42a6 cmp r6, r4 + 80149f2: e9cd 2306 strd r2, r3, [sp, #24] + 80149f6: f04f 0200 mov.w r2, #0 + 80149fa: d124 bne.n 8014a46 <_dtoa_r+0x62e> + 80149fc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 + 8014a00: 4bae ldr r3, [pc, #696] @ (8014cbc <_dtoa_r+0x8a4>) + 8014a02: f7f3 fc1f bl 8008244 <__adddf3> + 8014a06: 4602 mov r2, r0 + 8014a08: 460b mov r3, r1 + 8014a0a: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014a0e: f7f4 f85f bl 8008ad0 <__aeabi_dcmpgt> + 8014a12: 2800 cmp r0, #0 + 8014a14: d163 bne.n 8014ade <_dtoa_r+0x6c6> + 8014a16: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 + 8014a1a: 2000 movs r0, #0 + 8014a1c: 49a7 ldr r1, [pc, #668] @ (8014cbc <_dtoa_r+0x8a4>) + 8014a1e: f7f3 fc0f bl 8008240 <__aeabi_dsub> + 8014a22: 4602 mov r2, r0 + 8014a24: 460b mov r3, r1 + 8014a26: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014a2a: f7f4 f833 bl 8008a94 <__aeabi_dcmplt> + 8014a2e: 2800 cmp r0, #0 + 8014a30: f43f af14 beq.w 801485c <_dtoa_r+0x444> + 8014a34: 9e13 ldr r6, [sp, #76] @ 0x4c + 8014a36: 1e73 subs r3, r6, #1 + 8014a38: 9313 str r3, [sp, #76] @ 0x4c + 8014a3a: f816 3c01 ldrb.w r3, [r6, #-1] + 8014a3e: 2b30 cmp r3, #48 @ 0x30 + 8014a40: d0f8 beq.n 8014a34 <_dtoa_r+0x61c> + 8014a42: 4647 mov r7, r8 + 8014a44: e03b b.n 8014abe <_dtoa_r+0x6a6> + 8014a46: 4b9e ldr r3, [pc, #632] @ (8014cc0 <_dtoa_r+0x8a8>) + 8014a48: f7f3 fdb2 bl 80085b0 <__aeabi_dmul> + 8014a4c: e9cd 0106 strd r0, r1, [sp, #24] + 8014a50: e7bc b.n 80149cc <_dtoa_r+0x5b4> + 8014a52: 4656 mov r6, sl + 8014a54: e9dd 4506 ldrd r4, r5, [sp, #24] + 8014a58: e9dd 2304 ldrd r2, r3, [sp, #16] + 8014a5c: 4620 mov r0, r4 + 8014a5e: 4629 mov r1, r5 + 8014a60: f7f3 fed0 bl 8008804 <__aeabi_ddiv> + 8014a64: f7f4 f854 bl 8008b10 <__aeabi_d2iz> + 8014a68: 4680 mov r8, r0 + 8014a6a: f7f3 fd37 bl 80084dc <__aeabi_i2d> + 8014a6e: e9dd 2304 ldrd r2, r3, [sp, #16] + 8014a72: f7f3 fd9d bl 80085b0 <__aeabi_dmul> + 8014a76: 4602 mov r2, r0 + 8014a78: 460b mov r3, r1 + 8014a7a: 4620 mov r0, r4 + 8014a7c: 4629 mov r1, r5 + 8014a7e: f7f3 fbdf bl 8008240 <__aeabi_dsub> + 8014a82: f108 0430 add.w r4, r8, #48 @ 0x30 + 8014a86: 9d08 ldr r5, [sp, #32] + 8014a88: f806 4b01 strb.w r4, [r6], #1 + 8014a8c: eba6 040a sub.w r4, r6, sl + 8014a90: 42a5 cmp r5, r4 + 8014a92: 4602 mov r2, r0 + 8014a94: 460b mov r3, r1 + 8014a96: d133 bne.n 8014b00 <_dtoa_r+0x6e8> + 8014a98: f7f3 fbd4 bl 8008244 <__adddf3> + 8014a9c: e9dd 2304 ldrd r2, r3, [sp, #16] + 8014aa0: 4604 mov r4, r0 + 8014aa2: 460d mov r5, r1 + 8014aa4: f7f4 f814 bl 8008ad0 <__aeabi_dcmpgt> + 8014aa8: b9c0 cbnz r0, 8014adc <_dtoa_r+0x6c4> + 8014aaa: e9dd 2304 ldrd r2, r3, [sp, #16] + 8014aae: 4620 mov r0, r4 + 8014ab0: 4629 mov r1, r5 + 8014ab2: f7f3 ffe5 bl 8008a80 <__aeabi_dcmpeq> + 8014ab6: b110 cbz r0, 8014abe <_dtoa_r+0x6a6> + 8014ab8: f018 0f01 tst.w r8, #1 + 8014abc: d10e bne.n 8014adc <_dtoa_r+0x6c4> + 8014abe: 4648 mov r0, r9 + 8014ac0: 9903 ldr r1, [sp, #12] + 8014ac2: f000 feb3 bl 801582c <_Bfree> + 8014ac6: 2300 movs r3, #0 + 8014ac8: 7033 strb r3, [r6, #0] + 8014aca: 9b22 ldr r3, [sp, #136] @ 0x88 + 8014acc: 3701 adds r7, #1 + 8014ace: 601f str r7, [r3, #0] + 8014ad0: 9b24 ldr r3, [sp, #144] @ 0x90 + 8014ad2: 2b00 cmp r3, #0 + 8014ad4: f000 824b beq.w 8014f6e <_dtoa_r+0xb56> + 8014ad8: 601e str r6, [r3, #0] + 8014ada: e248 b.n 8014f6e <_dtoa_r+0xb56> + 8014adc: 46b8 mov r8, r7 + 8014ade: 4633 mov r3, r6 + 8014ae0: 461e mov r6, r3 + 8014ae2: f813 2d01 ldrb.w r2, [r3, #-1]! + 8014ae6: 2a39 cmp r2, #57 @ 0x39 + 8014ae8: d106 bne.n 8014af8 <_dtoa_r+0x6e0> + 8014aea: 459a cmp sl, r3 + 8014aec: d1f8 bne.n 8014ae0 <_dtoa_r+0x6c8> + 8014aee: 2230 movs r2, #48 @ 0x30 + 8014af0: f108 0801 add.w r8, r8, #1 + 8014af4: f88a 2000 strb.w r2, [sl] + 8014af8: 781a ldrb r2, [r3, #0] + 8014afa: 3201 adds r2, #1 + 8014afc: 701a strb r2, [r3, #0] + 8014afe: e7a0 b.n 8014a42 <_dtoa_r+0x62a> + 8014b00: 2200 movs r2, #0 + 8014b02: 4b6f ldr r3, [pc, #444] @ (8014cc0 <_dtoa_r+0x8a8>) + 8014b04: f7f3 fd54 bl 80085b0 <__aeabi_dmul> + 8014b08: 2200 movs r2, #0 + 8014b0a: 2300 movs r3, #0 + 8014b0c: 4604 mov r4, r0 + 8014b0e: 460d mov r5, r1 + 8014b10: f7f3 ffb6 bl 8008a80 <__aeabi_dcmpeq> + 8014b14: 2800 cmp r0, #0 + 8014b16: d09f beq.n 8014a58 <_dtoa_r+0x640> + 8014b18: e7d1 b.n 8014abe <_dtoa_r+0x6a6> + 8014b1a: 9a0b ldr r2, [sp, #44] @ 0x2c + 8014b1c: 2a00 cmp r2, #0 + 8014b1e: f000 80ea beq.w 8014cf6 <_dtoa_r+0x8de> + 8014b22: 9a20 ldr r2, [sp, #128] @ 0x80 + 8014b24: 2a01 cmp r2, #1 + 8014b26: f300 80cd bgt.w 8014cc4 <_dtoa_r+0x8ac> + 8014b2a: 9a12 ldr r2, [sp, #72] @ 0x48 + 8014b2c: 2a00 cmp r2, #0 + 8014b2e: f000 80c1 beq.w 8014cb4 <_dtoa_r+0x89c> + 8014b32: f203 4333 addw r3, r3, #1075 @ 0x433 + 8014b36: 9c0a ldr r4, [sp, #40] @ 0x28 + 8014b38: 9e04 ldr r6, [sp, #16] + 8014b3a: 9a04 ldr r2, [sp, #16] + 8014b3c: 2101 movs r1, #1 + 8014b3e: 441a add r2, r3 + 8014b40: 9204 str r2, [sp, #16] + 8014b42: 9a09 ldr r2, [sp, #36] @ 0x24 + 8014b44: 4648 mov r0, r9 + 8014b46: 441a add r2, r3 + 8014b48: 9209 str r2, [sp, #36] @ 0x24 + 8014b4a: f000 ff23 bl 8015994 <__i2b> + 8014b4e: 4605 mov r5, r0 + 8014b50: b166 cbz r6, 8014b6c <_dtoa_r+0x754> + 8014b52: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014b54: 2b00 cmp r3, #0 + 8014b56: dd09 ble.n 8014b6c <_dtoa_r+0x754> + 8014b58: 42b3 cmp r3, r6 + 8014b5a: bfa8 it ge + 8014b5c: 4633 movge r3, r6 + 8014b5e: 9a04 ldr r2, [sp, #16] + 8014b60: 1af6 subs r6, r6, r3 + 8014b62: 1ad2 subs r2, r2, r3 + 8014b64: 9204 str r2, [sp, #16] + 8014b66: 9a09 ldr r2, [sp, #36] @ 0x24 + 8014b68: 1ad3 subs r3, r2, r3 + 8014b6a: 9309 str r3, [sp, #36] @ 0x24 + 8014b6c: 9b0a ldr r3, [sp, #40] @ 0x28 + 8014b6e: b30b cbz r3, 8014bb4 <_dtoa_r+0x79c> + 8014b70: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014b72: 2b00 cmp r3, #0 + 8014b74: f000 80c6 beq.w 8014d04 <_dtoa_r+0x8ec> + 8014b78: 2c00 cmp r4, #0 + 8014b7a: f000 80c0 beq.w 8014cfe <_dtoa_r+0x8e6> + 8014b7e: 4629 mov r1, r5 + 8014b80: 4622 mov r2, r4 + 8014b82: 4648 mov r0, r9 + 8014b84: f000 ffbe bl 8015b04 <__pow5mult> + 8014b88: 9a03 ldr r2, [sp, #12] + 8014b8a: 4601 mov r1, r0 + 8014b8c: 4605 mov r5, r0 + 8014b8e: 4648 mov r0, r9 + 8014b90: f000 ff16 bl 80159c0 <__multiply> + 8014b94: 9903 ldr r1, [sp, #12] + 8014b96: 4680 mov r8, r0 + 8014b98: 4648 mov r0, r9 + 8014b9a: f000 fe47 bl 801582c <_Bfree> + 8014b9e: 9b0a ldr r3, [sp, #40] @ 0x28 + 8014ba0: 1b1b subs r3, r3, r4 + 8014ba2: 930a str r3, [sp, #40] @ 0x28 + 8014ba4: f000 80b1 beq.w 8014d0a <_dtoa_r+0x8f2> + 8014ba8: 4641 mov r1, r8 + 8014baa: 9a0a ldr r2, [sp, #40] @ 0x28 + 8014bac: 4648 mov r0, r9 + 8014bae: f000 ffa9 bl 8015b04 <__pow5mult> + 8014bb2: 9003 str r0, [sp, #12] + 8014bb4: 2101 movs r1, #1 + 8014bb6: 4648 mov r0, r9 + 8014bb8: f000 feec bl 8015994 <__i2b> + 8014bbc: 9b0e ldr r3, [sp, #56] @ 0x38 + 8014bbe: 4604 mov r4, r0 + 8014bc0: 2b00 cmp r3, #0 + 8014bc2: f000 81d8 beq.w 8014f76 <_dtoa_r+0xb5e> + 8014bc6: 461a mov r2, r3 + 8014bc8: 4601 mov r1, r0 + 8014bca: 4648 mov r0, r9 + 8014bcc: f000 ff9a bl 8015b04 <__pow5mult> + 8014bd0: 9b20 ldr r3, [sp, #128] @ 0x80 + 8014bd2: 4604 mov r4, r0 + 8014bd4: 2b01 cmp r3, #1 + 8014bd6: f300 809f bgt.w 8014d18 <_dtoa_r+0x900> + 8014bda: 9b06 ldr r3, [sp, #24] + 8014bdc: 2b00 cmp r3, #0 + 8014bde: f040 8097 bne.w 8014d10 <_dtoa_r+0x8f8> + 8014be2: 9b07 ldr r3, [sp, #28] + 8014be4: f3c3 0313 ubfx r3, r3, #0, #20 + 8014be8: 2b00 cmp r3, #0 + 8014bea: f040 8093 bne.w 8014d14 <_dtoa_r+0x8fc> + 8014bee: 9b07 ldr r3, [sp, #28] + 8014bf0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8014bf4: 0d1b lsrs r3, r3, #20 + 8014bf6: 051b lsls r3, r3, #20 + 8014bf8: b133 cbz r3, 8014c08 <_dtoa_r+0x7f0> + 8014bfa: 9b04 ldr r3, [sp, #16] + 8014bfc: 3301 adds r3, #1 + 8014bfe: 9304 str r3, [sp, #16] + 8014c00: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014c02: 3301 adds r3, #1 + 8014c04: 9309 str r3, [sp, #36] @ 0x24 + 8014c06: 2301 movs r3, #1 + 8014c08: 930a str r3, [sp, #40] @ 0x28 + 8014c0a: 9b0e ldr r3, [sp, #56] @ 0x38 + 8014c0c: 2b00 cmp r3, #0 + 8014c0e: f000 81b8 beq.w 8014f82 <_dtoa_r+0xb6a> + 8014c12: 6923 ldr r3, [r4, #16] + 8014c14: eb04 0383 add.w r3, r4, r3, lsl #2 + 8014c18: 6918 ldr r0, [r3, #16] + 8014c1a: f000 fe6f bl 80158fc <__hi0bits> + 8014c1e: f1c0 0020 rsb r0, r0, #32 + 8014c22: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014c24: 4418 add r0, r3 + 8014c26: f010 001f ands.w r0, r0, #31 + 8014c2a: f000 8082 beq.w 8014d32 <_dtoa_r+0x91a> + 8014c2e: f1c0 0320 rsb r3, r0, #32 + 8014c32: 2b04 cmp r3, #4 + 8014c34: dd73 ble.n 8014d1e <_dtoa_r+0x906> + 8014c36: 9b04 ldr r3, [sp, #16] + 8014c38: f1c0 001c rsb r0, r0, #28 + 8014c3c: 4403 add r3, r0 + 8014c3e: 9304 str r3, [sp, #16] + 8014c40: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014c42: 4406 add r6, r0 + 8014c44: 4403 add r3, r0 + 8014c46: 9309 str r3, [sp, #36] @ 0x24 + 8014c48: 9b04 ldr r3, [sp, #16] + 8014c4a: 2b00 cmp r3, #0 + 8014c4c: dd05 ble.n 8014c5a <_dtoa_r+0x842> + 8014c4e: 461a mov r2, r3 + 8014c50: 4648 mov r0, r9 + 8014c52: 9903 ldr r1, [sp, #12] + 8014c54: f000 ffb0 bl 8015bb8 <__lshift> + 8014c58: 9003 str r0, [sp, #12] + 8014c5a: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014c5c: 2b00 cmp r3, #0 + 8014c5e: dd05 ble.n 8014c6c <_dtoa_r+0x854> + 8014c60: 4621 mov r1, r4 + 8014c62: 461a mov r2, r3 + 8014c64: 4648 mov r0, r9 + 8014c66: f000 ffa7 bl 8015bb8 <__lshift> + 8014c6a: 4604 mov r4, r0 + 8014c6c: 9b0f ldr r3, [sp, #60] @ 0x3c + 8014c6e: 2b00 cmp r3, #0 + 8014c70: d061 beq.n 8014d36 <_dtoa_r+0x91e> + 8014c72: 4621 mov r1, r4 + 8014c74: 9803 ldr r0, [sp, #12] + 8014c76: f001 f80b bl 8015c90 <__mcmp> + 8014c7a: 2800 cmp r0, #0 + 8014c7c: da5b bge.n 8014d36 <_dtoa_r+0x91e> + 8014c7e: 2300 movs r3, #0 + 8014c80: 220a movs r2, #10 + 8014c82: 4648 mov r0, r9 + 8014c84: 9903 ldr r1, [sp, #12] + 8014c86: f000 fdf3 bl 8015870 <__multadd> + 8014c8a: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014c8c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff + 8014c90: 9003 str r0, [sp, #12] + 8014c92: 2b00 cmp r3, #0 + 8014c94: f000 8177 beq.w 8014f86 <_dtoa_r+0xb6e> + 8014c98: 4629 mov r1, r5 + 8014c9a: 2300 movs r3, #0 + 8014c9c: 220a movs r2, #10 + 8014c9e: 4648 mov r0, r9 + 8014ca0: f000 fde6 bl 8015870 <__multadd> + 8014ca4: f1bb 0f00 cmp.w fp, #0 + 8014ca8: 4605 mov r5, r0 + 8014caa: dc6f bgt.n 8014d8c <_dtoa_r+0x974> + 8014cac: 9b20 ldr r3, [sp, #128] @ 0x80 + 8014cae: 2b02 cmp r3, #2 + 8014cb0: dc49 bgt.n 8014d46 <_dtoa_r+0x92e> + 8014cb2: e06b b.n 8014d8c <_dtoa_r+0x974> + 8014cb4: 9b14 ldr r3, [sp, #80] @ 0x50 + 8014cb6: f1c3 0336 rsb r3, r3, #54 @ 0x36 + 8014cba: e73c b.n 8014b36 <_dtoa_r+0x71e> + 8014cbc: 3fe00000 .word 0x3fe00000 + 8014cc0: 40240000 .word 0x40240000 + 8014cc4: 9b08 ldr r3, [sp, #32] + 8014cc6: 1e5c subs r4, r3, #1 + 8014cc8: 9b0a ldr r3, [sp, #40] @ 0x28 + 8014cca: 42a3 cmp r3, r4 + 8014ccc: db09 blt.n 8014ce2 <_dtoa_r+0x8ca> + 8014cce: 1b1c subs r4, r3, r4 + 8014cd0: 9b08 ldr r3, [sp, #32] + 8014cd2: 2b00 cmp r3, #0 + 8014cd4: f6bf af30 bge.w 8014b38 <_dtoa_r+0x720> + 8014cd8: 9b04 ldr r3, [sp, #16] + 8014cda: 9a08 ldr r2, [sp, #32] + 8014cdc: 1a9e subs r6, r3, r2 + 8014cde: 2300 movs r3, #0 + 8014ce0: e72b b.n 8014b3a <_dtoa_r+0x722> + 8014ce2: 9b0a ldr r3, [sp, #40] @ 0x28 + 8014ce4: 9a0e ldr r2, [sp, #56] @ 0x38 + 8014ce6: 1ae3 subs r3, r4, r3 + 8014ce8: 441a add r2, r3 + 8014cea: 940a str r4, [sp, #40] @ 0x28 + 8014cec: 9e04 ldr r6, [sp, #16] + 8014cee: 2400 movs r4, #0 + 8014cf0: 9b08 ldr r3, [sp, #32] + 8014cf2: 920e str r2, [sp, #56] @ 0x38 + 8014cf4: e721 b.n 8014b3a <_dtoa_r+0x722> + 8014cf6: 9c0a ldr r4, [sp, #40] @ 0x28 + 8014cf8: 9e04 ldr r6, [sp, #16] + 8014cfa: 9d0b ldr r5, [sp, #44] @ 0x2c + 8014cfc: e728 b.n 8014b50 <_dtoa_r+0x738> + 8014cfe: f8dd 800c ldr.w r8, [sp, #12] + 8014d02: e751 b.n 8014ba8 <_dtoa_r+0x790> + 8014d04: 9a0a ldr r2, [sp, #40] @ 0x28 + 8014d06: 9903 ldr r1, [sp, #12] + 8014d08: e750 b.n 8014bac <_dtoa_r+0x794> + 8014d0a: f8cd 800c str.w r8, [sp, #12] + 8014d0e: e751 b.n 8014bb4 <_dtoa_r+0x79c> + 8014d10: 2300 movs r3, #0 + 8014d12: e779 b.n 8014c08 <_dtoa_r+0x7f0> + 8014d14: 9b06 ldr r3, [sp, #24] + 8014d16: e777 b.n 8014c08 <_dtoa_r+0x7f0> + 8014d18: 2300 movs r3, #0 + 8014d1a: 930a str r3, [sp, #40] @ 0x28 + 8014d1c: e779 b.n 8014c12 <_dtoa_r+0x7fa> + 8014d1e: d093 beq.n 8014c48 <_dtoa_r+0x830> + 8014d20: 9a04 ldr r2, [sp, #16] + 8014d22: 331c adds r3, #28 + 8014d24: 441a add r2, r3 + 8014d26: 9204 str r2, [sp, #16] + 8014d28: 9a09 ldr r2, [sp, #36] @ 0x24 + 8014d2a: 441e add r6, r3 + 8014d2c: 441a add r2, r3 + 8014d2e: 9209 str r2, [sp, #36] @ 0x24 + 8014d30: e78a b.n 8014c48 <_dtoa_r+0x830> + 8014d32: 4603 mov r3, r0 + 8014d34: e7f4 b.n 8014d20 <_dtoa_r+0x908> + 8014d36: 9b08 ldr r3, [sp, #32] + 8014d38: 46b8 mov r8, r7 + 8014d3a: 2b00 cmp r3, #0 + 8014d3c: dc20 bgt.n 8014d80 <_dtoa_r+0x968> + 8014d3e: 469b mov fp, r3 + 8014d40: 9b20 ldr r3, [sp, #128] @ 0x80 + 8014d42: 2b02 cmp r3, #2 + 8014d44: dd1e ble.n 8014d84 <_dtoa_r+0x96c> + 8014d46: f1bb 0f00 cmp.w fp, #0 + 8014d4a: f47f adb1 bne.w 80148b0 <_dtoa_r+0x498> + 8014d4e: 4621 mov r1, r4 + 8014d50: 465b mov r3, fp + 8014d52: 2205 movs r2, #5 + 8014d54: 4648 mov r0, r9 + 8014d56: f000 fd8b bl 8015870 <__multadd> + 8014d5a: 4601 mov r1, r0 + 8014d5c: 4604 mov r4, r0 + 8014d5e: 9803 ldr r0, [sp, #12] + 8014d60: f000 ff96 bl 8015c90 <__mcmp> + 8014d64: 2800 cmp r0, #0 + 8014d66: f77f ada3 ble.w 80148b0 <_dtoa_r+0x498> + 8014d6a: 4656 mov r6, sl + 8014d6c: 2331 movs r3, #49 @ 0x31 + 8014d6e: f108 0801 add.w r8, r8, #1 + 8014d72: f806 3b01 strb.w r3, [r6], #1 + 8014d76: e59f b.n 80148b8 <_dtoa_r+0x4a0> + 8014d78: 46b8 mov r8, r7 + 8014d7a: 9c08 ldr r4, [sp, #32] + 8014d7c: 4625 mov r5, r4 + 8014d7e: e7f4 b.n 8014d6a <_dtoa_r+0x952> + 8014d80: f8dd b020 ldr.w fp, [sp, #32] + 8014d84: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014d86: 2b00 cmp r3, #0 + 8014d88: f000 8101 beq.w 8014f8e <_dtoa_r+0xb76> + 8014d8c: 2e00 cmp r6, #0 + 8014d8e: dd05 ble.n 8014d9c <_dtoa_r+0x984> + 8014d90: 4629 mov r1, r5 + 8014d92: 4632 mov r2, r6 + 8014d94: 4648 mov r0, r9 + 8014d96: f000 ff0f bl 8015bb8 <__lshift> + 8014d9a: 4605 mov r5, r0 + 8014d9c: 9b0a ldr r3, [sp, #40] @ 0x28 + 8014d9e: 2b00 cmp r3, #0 + 8014da0: d05c beq.n 8014e5c <_dtoa_r+0xa44> + 8014da2: 4648 mov r0, r9 + 8014da4: 6869 ldr r1, [r5, #4] + 8014da6: f000 fd01 bl 80157ac <_Balloc> + 8014daa: 4606 mov r6, r0 + 8014dac: b928 cbnz r0, 8014dba <_dtoa_r+0x9a2> + 8014dae: 4602 mov r2, r0 + 8014db0: f240 21ef movw r1, #751 @ 0x2ef + 8014db4: 4b80 ldr r3, [pc, #512] @ (8014fb8 <_dtoa_r+0xba0>) + 8014db6: f7ff bb43 b.w 8014440 <_dtoa_r+0x28> + 8014dba: 692a ldr r2, [r5, #16] + 8014dbc: f105 010c add.w r1, r5, #12 + 8014dc0: 3202 adds r2, #2 + 8014dc2: 0092 lsls r2, r2, #2 + 8014dc4: 300c adds r0, #12 + 8014dc6: f7ff fa71 bl 80142ac + 8014dca: 2201 movs r2, #1 + 8014dcc: 4631 mov r1, r6 + 8014dce: 4648 mov r0, r9 + 8014dd0: f000 fef2 bl 8015bb8 <__lshift> + 8014dd4: 462f mov r7, r5 + 8014dd6: 4605 mov r5, r0 + 8014dd8: f10a 0301 add.w r3, sl, #1 + 8014ddc: 9304 str r3, [sp, #16] + 8014dde: eb0a 030b add.w r3, sl, fp + 8014de2: 930a str r3, [sp, #40] @ 0x28 + 8014de4: 9b06 ldr r3, [sp, #24] + 8014de6: f003 0301 and.w r3, r3, #1 + 8014dea: 9309 str r3, [sp, #36] @ 0x24 + 8014dec: 9b04 ldr r3, [sp, #16] + 8014dee: 4621 mov r1, r4 + 8014df0: 9803 ldr r0, [sp, #12] + 8014df2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff + 8014df6: f7ff fa85 bl 8014304 + 8014dfa: 4603 mov r3, r0 + 8014dfc: 4639 mov r1, r7 + 8014dfe: 3330 adds r3, #48 @ 0x30 + 8014e00: 9006 str r0, [sp, #24] + 8014e02: 9803 ldr r0, [sp, #12] + 8014e04: 930b str r3, [sp, #44] @ 0x2c + 8014e06: f000 ff43 bl 8015c90 <__mcmp> + 8014e0a: 462a mov r2, r5 + 8014e0c: 9008 str r0, [sp, #32] + 8014e0e: 4621 mov r1, r4 + 8014e10: 4648 mov r0, r9 + 8014e12: f000 ff59 bl 8015cc8 <__mdiff> + 8014e16: 68c2 ldr r2, [r0, #12] + 8014e18: 4606 mov r6, r0 + 8014e1a: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014e1c: bb02 cbnz r2, 8014e60 <_dtoa_r+0xa48> + 8014e1e: 4601 mov r1, r0 + 8014e20: 9803 ldr r0, [sp, #12] + 8014e22: f000 ff35 bl 8015c90 <__mcmp> + 8014e26: 4602 mov r2, r0 + 8014e28: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014e2a: 4631 mov r1, r6 + 8014e2c: 4648 mov r0, r9 + 8014e2e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c + 8014e32: f000 fcfb bl 801582c <_Bfree> + 8014e36: 9b20 ldr r3, [sp, #128] @ 0x80 + 8014e38: 9a0c ldr r2, [sp, #48] @ 0x30 + 8014e3a: 9e04 ldr r6, [sp, #16] + 8014e3c: ea42 0103 orr.w r1, r2, r3 + 8014e40: 9b09 ldr r3, [sp, #36] @ 0x24 + 8014e42: 4319 orrs r1, r3 + 8014e44: 9b0b ldr r3, [sp, #44] @ 0x2c + 8014e46: d10d bne.n 8014e64 <_dtoa_r+0xa4c> + 8014e48: 2b39 cmp r3, #57 @ 0x39 + 8014e4a: d027 beq.n 8014e9c <_dtoa_r+0xa84> + 8014e4c: 9a08 ldr r2, [sp, #32] + 8014e4e: 2a00 cmp r2, #0 + 8014e50: dd01 ble.n 8014e56 <_dtoa_r+0xa3e> + 8014e52: 9b06 ldr r3, [sp, #24] + 8014e54: 3331 adds r3, #49 @ 0x31 + 8014e56: f88b 3000 strb.w r3, [fp] + 8014e5a: e52e b.n 80148ba <_dtoa_r+0x4a2> + 8014e5c: 4628 mov r0, r5 + 8014e5e: e7b9 b.n 8014dd4 <_dtoa_r+0x9bc> + 8014e60: 2201 movs r2, #1 + 8014e62: e7e2 b.n 8014e2a <_dtoa_r+0xa12> + 8014e64: 9908 ldr r1, [sp, #32] + 8014e66: 2900 cmp r1, #0 + 8014e68: db04 blt.n 8014e74 <_dtoa_r+0xa5c> + 8014e6a: 9820 ldr r0, [sp, #128] @ 0x80 + 8014e6c: 4301 orrs r1, r0 + 8014e6e: 9809 ldr r0, [sp, #36] @ 0x24 + 8014e70: 4301 orrs r1, r0 + 8014e72: d120 bne.n 8014eb6 <_dtoa_r+0xa9e> + 8014e74: 2a00 cmp r2, #0 + 8014e76: ddee ble.n 8014e56 <_dtoa_r+0xa3e> + 8014e78: 2201 movs r2, #1 + 8014e7a: 9903 ldr r1, [sp, #12] + 8014e7c: 4648 mov r0, r9 + 8014e7e: 9304 str r3, [sp, #16] + 8014e80: f000 fe9a bl 8015bb8 <__lshift> + 8014e84: 4621 mov r1, r4 + 8014e86: 9003 str r0, [sp, #12] + 8014e88: f000 ff02 bl 8015c90 <__mcmp> + 8014e8c: 2800 cmp r0, #0 + 8014e8e: 9b04 ldr r3, [sp, #16] + 8014e90: dc02 bgt.n 8014e98 <_dtoa_r+0xa80> + 8014e92: d1e0 bne.n 8014e56 <_dtoa_r+0xa3e> + 8014e94: 07da lsls r2, r3, #31 + 8014e96: d5de bpl.n 8014e56 <_dtoa_r+0xa3e> + 8014e98: 2b39 cmp r3, #57 @ 0x39 + 8014e9a: d1da bne.n 8014e52 <_dtoa_r+0xa3a> + 8014e9c: 2339 movs r3, #57 @ 0x39 + 8014e9e: f88b 3000 strb.w r3, [fp] + 8014ea2: 4633 mov r3, r6 + 8014ea4: 461e mov r6, r3 + 8014ea6: f816 2c01 ldrb.w r2, [r6, #-1] + 8014eaa: 3b01 subs r3, #1 + 8014eac: 2a39 cmp r2, #57 @ 0x39 + 8014eae: d04e beq.n 8014f4e <_dtoa_r+0xb36> + 8014eb0: 3201 adds r2, #1 + 8014eb2: 701a strb r2, [r3, #0] + 8014eb4: e501 b.n 80148ba <_dtoa_r+0x4a2> + 8014eb6: 2a00 cmp r2, #0 + 8014eb8: dd03 ble.n 8014ec2 <_dtoa_r+0xaaa> + 8014eba: 2b39 cmp r3, #57 @ 0x39 + 8014ebc: d0ee beq.n 8014e9c <_dtoa_r+0xa84> + 8014ebe: 3301 adds r3, #1 + 8014ec0: e7c9 b.n 8014e56 <_dtoa_r+0xa3e> + 8014ec2: 9a04 ldr r2, [sp, #16] + 8014ec4: 990a ldr r1, [sp, #40] @ 0x28 + 8014ec6: f802 3c01 strb.w r3, [r2, #-1] + 8014eca: 428a cmp r2, r1 + 8014ecc: d028 beq.n 8014f20 <_dtoa_r+0xb08> + 8014ece: 2300 movs r3, #0 + 8014ed0: 220a movs r2, #10 + 8014ed2: 9903 ldr r1, [sp, #12] + 8014ed4: 4648 mov r0, r9 + 8014ed6: f000 fccb bl 8015870 <__multadd> + 8014eda: 42af cmp r7, r5 + 8014edc: 9003 str r0, [sp, #12] + 8014ede: f04f 0300 mov.w r3, #0 + 8014ee2: f04f 020a mov.w r2, #10 + 8014ee6: 4639 mov r1, r7 + 8014ee8: 4648 mov r0, r9 + 8014eea: d107 bne.n 8014efc <_dtoa_r+0xae4> + 8014eec: f000 fcc0 bl 8015870 <__multadd> + 8014ef0: 4607 mov r7, r0 + 8014ef2: 4605 mov r5, r0 + 8014ef4: 9b04 ldr r3, [sp, #16] + 8014ef6: 3301 adds r3, #1 + 8014ef8: 9304 str r3, [sp, #16] + 8014efa: e777 b.n 8014dec <_dtoa_r+0x9d4> + 8014efc: f000 fcb8 bl 8015870 <__multadd> + 8014f00: 4629 mov r1, r5 + 8014f02: 4607 mov r7, r0 + 8014f04: 2300 movs r3, #0 + 8014f06: 220a movs r2, #10 + 8014f08: 4648 mov r0, r9 + 8014f0a: f000 fcb1 bl 8015870 <__multadd> + 8014f0e: 4605 mov r5, r0 + 8014f10: e7f0 b.n 8014ef4 <_dtoa_r+0xadc> + 8014f12: f1bb 0f00 cmp.w fp, #0 + 8014f16: bfcc ite gt + 8014f18: 465e movgt r6, fp + 8014f1a: 2601 movle r6, #1 + 8014f1c: 2700 movs r7, #0 + 8014f1e: 4456 add r6, sl + 8014f20: 2201 movs r2, #1 + 8014f22: 9903 ldr r1, [sp, #12] + 8014f24: 4648 mov r0, r9 + 8014f26: 9304 str r3, [sp, #16] + 8014f28: f000 fe46 bl 8015bb8 <__lshift> + 8014f2c: 4621 mov r1, r4 + 8014f2e: 9003 str r0, [sp, #12] + 8014f30: f000 feae bl 8015c90 <__mcmp> + 8014f34: 2800 cmp r0, #0 + 8014f36: dcb4 bgt.n 8014ea2 <_dtoa_r+0xa8a> + 8014f38: d102 bne.n 8014f40 <_dtoa_r+0xb28> + 8014f3a: 9b04 ldr r3, [sp, #16] + 8014f3c: 07db lsls r3, r3, #31 + 8014f3e: d4b0 bmi.n 8014ea2 <_dtoa_r+0xa8a> + 8014f40: 4633 mov r3, r6 + 8014f42: 461e mov r6, r3 + 8014f44: f813 2d01 ldrb.w r2, [r3, #-1]! + 8014f48: 2a30 cmp r2, #48 @ 0x30 + 8014f4a: d0fa beq.n 8014f42 <_dtoa_r+0xb2a> + 8014f4c: e4b5 b.n 80148ba <_dtoa_r+0x4a2> + 8014f4e: 459a cmp sl, r3 + 8014f50: d1a8 bne.n 8014ea4 <_dtoa_r+0xa8c> + 8014f52: 2331 movs r3, #49 @ 0x31 + 8014f54: f108 0801 add.w r8, r8, #1 + 8014f58: f88a 3000 strb.w r3, [sl] + 8014f5c: e4ad b.n 80148ba <_dtoa_r+0x4a2> + 8014f5e: 9b24 ldr r3, [sp, #144] @ 0x90 + 8014f60: f8df a058 ldr.w sl, [pc, #88] @ 8014fbc <_dtoa_r+0xba4> + 8014f64: b11b cbz r3, 8014f6e <_dtoa_r+0xb56> + 8014f66: f10a 0308 add.w r3, sl, #8 + 8014f6a: 9a24 ldr r2, [sp, #144] @ 0x90 + 8014f6c: 6013 str r3, [r2, #0] + 8014f6e: 4650 mov r0, sl + 8014f70: b017 add sp, #92 @ 0x5c + 8014f72: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8014f76: 9b20 ldr r3, [sp, #128] @ 0x80 + 8014f78: 2b01 cmp r3, #1 + 8014f7a: f77f ae2e ble.w 8014bda <_dtoa_r+0x7c2> + 8014f7e: 9b0e ldr r3, [sp, #56] @ 0x38 + 8014f80: 930a str r3, [sp, #40] @ 0x28 + 8014f82: 2001 movs r0, #1 + 8014f84: e64d b.n 8014c22 <_dtoa_r+0x80a> + 8014f86: f1bb 0f00 cmp.w fp, #0 + 8014f8a: f77f aed9 ble.w 8014d40 <_dtoa_r+0x928> + 8014f8e: 4656 mov r6, sl + 8014f90: 4621 mov r1, r4 + 8014f92: 9803 ldr r0, [sp, #12] + 8014f94: f7ff f9b6 bl 8014304 + 8014f98: f100 0330 add.w r3, r0, #48 @ 0x30 + 8014f9c: f806 3b01 strb.w r3, [r6], #1 + 8014fa0: eba6 020a sub.w r2, r6, sl + 8014fa4: 4593 cmp fp, r2 + 8014fa6: ddb4 ble.n 8014f12 <_dtoa_r+0xafa> + 8014fa8: 2300 movs r3, #0 + 8014faa: 220a movs r2, #10 + 8014fac: 4648 mov r0, r9 + 8014fae: 9903 ldr r1, [sp, #12] + 8014fb0: f000 fc5e bl 8015870 <__multadd> + 8014fb4: 9003 str r0, [sp, #12] + 8014fb6: e7eb b.n 8014f90 <_dtoa_r+0xb78> + 8014fb8: 08016d68 .word 0x08016d68 + 8014fbc: 08016d03 .word 0x08016d03 + +08014fc0 <__ssputs_r>: + 8014fc0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8014fc4: 461f mov r7, r3 + 8014fc6: 688e ldr r6, [r1, #8] + 8014fc8: 4682 mov sl, r0 + 8014fca: 42be cmp r6, r7 + 8014fcc: 460c mov r4, r1 + 8014fce: 4690 mov r8, r2 + 8014fd0: 680b ldr r3, [r1, #0] + 8014fd2: d82d bhi.n 8015030 <__ssputs_r+0x70> + 8014fd4: f9b1 200c ldrsh.w r2, [r1, #12] + 8014fd8: f412 6f90 tst.w r2, #1152 @ 0x480 + 8014fdc: d026 beq.n 801502c <__ssputs_r+0x6c> + 8014fde: 6965 ldr r5, [r4, #20] + 8014fe0: 6909 ldr r1, [r1, #16] + 8014fe2: eb05 0545 add.w r5, r5, r5, lsl #1 + 8014fe6: eba3 0901 sub.w r9, r3, r1 + 8014fea: eb05 75d5 add.w r5, r5, r5, lsr #31 + 8014fee: 1c7b adds r3, r7, #1 + 8014ff0: 444b add r3, r9 + 8014ff2: 106d asrs r5, r5, #1 + 8014ff4: 429d cmp r5, r3 + 8014ff6: bf38 it cc + 8014ff8: 461d movcc r5, r3 + 8014ffa: 0553 lsls r3, r2, #21 + 8014ffc: d527 bpl.n 801504e <__ssputs_r+0x8e> + 8014ffe: 4629 mov r1, r5 + 8015000: f000 faa0 bl 8015544 <_malloc_r> + 8015004: 4606 mov r6, r0 + 8015006: b360 cbz r0, 8015062 <__ssputs_r+0xa2> + 8015008: 464a mov r2, r9 + 801500a: 6921 ldr r1, [r4, #16] + 801500c: f7ff f94e bl 80142ac + 8015010: 89a3 ldrh r3, [r4, #12] + 8015012: f423 6390 bic.w r3, r3, #1152 @ 0x480 + 8015016: f043 0380 orr.w r3, r3, #128 @ 0x80 + 801501a: 81a3 strh r3, [r4, #12] + 801501c: 6126 str r6, [r4, #16] + 801501e: 444e add r6, r9 + 8015020: 6026 str r6, [r4, #0] + 8015022: 463e mov r6, r7 + 8015024: 6165 str r5, [r4, #20] + 8015026: eba5 0509 sub.w r5, r5, r9 + 801502a: 60a5 str r5, [r4, #8] + 801502c: 42be cmp r6, r7 + 801502e: d900 bls.n 8015032 <__ssputs_r+0x72> + 8015030: 463e mov r6, r7 + 8015032: 4632 mov r2, r6 + 8015034: 4641 mov r1, r8 + 8015036: 6820 ldr r0, [r4, #0] + 8015038: f001 f8ab bl 8016192 + 801503c: 2000 movs r0, #0 + 801503e: 68a3 ldr r3, [r4, #8] + 8015040: 1b9b subs r3, r3, r6 + 8015042: 60a3 str r3, [r4, #8] + 8015044: 6823 ldr r3, [r4, #0] + 8015046: 4433 add r3, r6 + 8015048: 6023 str r3, [r4, #0] + 801504a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801504e: 462a mov r2, r5 + 8015050: f000 ff7c bl 8015f4c <_realloc_r> + 8015054: 4606 mov r6, r0 + 8015056: 2800 cmp r0, #0 + 8015058: d1e0 bne.n 801501c <__ssputs_r+0x5c> + 801505a: 4650 mov r0, sl + 801505c: 6921 ldr r1, [r4, #16] + 801505e: f001 f947 bl 80162f0 <_free_r> + 8015062: 230c movs r3, #12 + 8015064: f8ca 3000 str.w r3, [sl] + 8015068: 89a3 ldrh r3, [r4, #12] + 801506a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 801506e: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8015072: 81a3 strh r3, [r4, #12] + 8015074: e7e9 b.n 801504a <__ssputs_r+0x8a> + ... + +08015078 <_svfiprintf_r>: + 8015078: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801507c: 4698 mov r8, r3 + 801507e: 898b ldrh r3, [r1, #12] + 8015080: 4607 mov r7, r0 + 8015082: 061b lsls r3, r3, #24 + 8015084: 460d mov r5, r1 + 8015086: 4614 mov r4, r2 + 8015088: b09d sub sp, #116 @ 0x74 + 801508a: d510 bpl.n 80150ae <_svfiprintf_r+0x36> + 801508c: 690b ldr r3, [r1, #16] + 801508e: b973 cbnz r3, 80150ae <_svfiprintf_r+0x36> + 8015090: 2140 movs r1, #64 @ 0x40 + 8015092: f000 fa57 bl 8015544 <_malloc_r> + 8015096: 6028 str r0, [r5, #0] + 8015098: 6128 str r0, [r5, #16] + 801509a: b930 cbnz r0, 80150aa <_svfiprintf_r+0x32> + 801509c: 230c movs r3, #12 + 801509e: 603b str r3, [r7, #0] + 80150a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80150a4: b01d add sp, #116 @ 0x74 + 80150a6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80150aa: 2340 movs r3, #64 @ 0x40 + 80150ac: 616b str r3, [r5, #20] + 80150ae: 2300 movs r3, #0 + 80150b0: 9309 str r3, [sp, #36] @ 0x24 + 80150b2: 2320 movs r3, #32 + 80150b4: f88d 3029 strb.w r3, [sp, #41] @ 0x29 + 80150b8: 2330 movs r3, #48 @ 0x30 + 80150ba: f04f 0901 mov.w r9, #1 + 80150be: f8cd 800c str.w r8, [sp, #12] + 80150c2: f8df 8198 ldr.w r8, [pc, #408] @ 801525c <_svfiprintf_r+0x1e4> + 80150c6: f88d 302a strb.w r3, [sp, #42] @ 0x2a + 80150ca: 4623 mov r3, r4 + 80150cc: 469a mov sl, r3 + 80150ce: f813 2b01 ldrb.w r2, [r3], #1 + 80150d2: b10a cbz r2, 80150d8 <_svfiprintf_r+0x60> + 80150d4: 2a25 cmp r2, #37 @ 0x25 + 80150d6: d1f9 bne.n 80150cc <_svfiprintf_r+0x54> + 80150d8: ebba 0b04 subs.w fp, sl, r4 + 80150dc: d00b beq.n 80150f6 <_svfiprintf_r+0x7e> + 80150de: 465b mov r3, fp + 80150e0: 4622 mov r2, r4 + 80150e2: 4629 mov r1, r5 + 80150e4: 4638 mov r0, r7 + 80150e6: f7ff ff6b bl 8014fc0 <__ssputs_r> + 80150ea: 3001 adds r0, #1 + 80150ec: f000 80a7 beq.w 801523e <_svfiprintf_r+0x1c6> + 80150f0: 9a09 ldr r2, [sp, #36] @ 0x24 + 80150f2: 445a add r2, fp + 80150f4: 9209 str r2, [sp, #36] @ 0x24 + 80150f6: f89a 3000 ldrb.w r3, [sl] + 80150fa: 2b00 cmp r3, #0 + 80150fc: f000 809f beq.w 801523e <_svfiprintf_r+0x1c6> + 8015100: 2300 movs r3, #0 + 8015102: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8015106: e9cd 2305 strd r2, r3, [sp, #20] + 801510a: f10a 0a01 add.w sl, sl, #1 + 801510e: 9304 str r3, [sp, #16] + 8015110: 9307 str r3, [sp, #28] + 8015112: f88d 3053 strb.w r3, [sp, #83] @ 0x53 + 8015116: 931a str r3, [sp, #104] @ 0x68 + 8015118: 4654 mov r4, sl + 801511a: 2205 movs r2, #5 + 801511c: f814 1b01 ldrb.w r1, [r4], #1 + 8015120: 484e ldr r0, [pc, #312] @ (801525c <_svfiprintf_r+0x1e4>) + 8015122: f7ff f8b5 bl 8014290 + 8015126: 9a04 ldr r2, [sp, #16] + 8015128: b9d8 cbnz r0, 8015162 <_svfiprintf_r+0xea> + 801512a: 06d0 lsls r0, r2, #27 + 801512c: bf44 itt mi + 801512e: 2320 movmi r3, #32 + 8015130: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 8015134: 0711 lsls r1, r2, #28 + 8015136: bf44 itt mi + 8015138: 232b movmi r3, #43 @ 0x2b + 801513a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 801513e: f89a 3000 ldrb.w r3, [sl] + 8015142: 2b2a cmp r3, #42 @ 0x2a + 8015144: d015 beq.n 8015172 <_svfiprintf_r+0xfa> + 8015146: 4654 mov r4, sl + 8015148: 2000 movs r0, #0 + 801514a: f04f 0c0a mov.w ip, #10 + 801514e: 9a07 ldr r2, [sp, #28] + 8015150: 4621 mov r1, r4 + 8015152: f811 3b01 ldrb.w r3, [r1], #1 + 8015156: 3b30 subs r3, #48 @ 0x30 + 8015158: 2b09 cmp r3, #9 + 801515a: d94b bls.n 80151f4 <_svfiprintf_r+0x17c> + 801515c: b1b0 cbz r0, 801518c <_svfiprintf_r+0x114> + 801515e: 9207 str r2, [sp, #28] + 8015160: e014 b.n 801518c <_svfiprintf_r+0x114> + 8015162: eba0 0308 sub.w r3, r0, r8 + 8015166: fa09 f303 lsl.w r3, r9, r3 + 801516a: 4313 orrs r3, r2 + 801516c: 46a2 mov sl, r4 + 801516e: 9304 str r3, [sp, #16] + 8015170: e7d2 b.n 8015118 <_svfiprintf_r+0xa0> + 8015172: 9b03 ldr r3, [sp, #12] + 8015174: 1d19 adds r1, r3, #4 + 8015176: 681b ldr r3, [r3, #0] + 8015178: 9103 str r1, [sp, #12] + 801517a: 2b00 cmp r3, #0 + 801517c: bfbb ittet lt + 801517e: 425b neglt r3, r3 + 8015180: f042 0202 orrlt.w r2, r2, #2 + 8015184: 9307 strge r3, [sp, #28] + 8015186: 9307 strlt r3, [sp, #28] + 8015188: bfb8 it lt + 801518a: 9204 strlt r2, [sp, #16] + 801518c: 7823 ldrb r3, [r4, #0] + 801518e: 2b2e cmp r3, #46 @ 0x2e + 8015190: d10a bne.n 80151a8 <_svfiprintf_r+0x130> + 8015192: 7863 ldrb r3, [r4, #1] + 8015194: 2b2a cmp r3, #42 @ 0x2a + 8015196: d132 bne.n 80151fe <_svfiprintf_r+0x186> + 8015198: 9b03 ldr r3, [sp, #12] + 801519a: 3402 adds r4, #2 + 801519c: 1d1a adds r2, r3, #4 + 801519e: 681b ldr r3, [r3, #0] + 80151a0: 9203 str r2, [sp, #12] + 80151a2: ea43 73e3 orr.w r3, r3, r3, asr #31 + 80151a6: 9305 str r3, [sp, #20] + 80151a8: f8df a0b4 ldr.w sl, [pc, #180] @ 8015260 <_svfiprintf_r+0x1e8> + 80151ac: 2203 movs r2, #3 + 80151ae: 4650 mov r0, sl + 80151b0: 7821 ldrb r1, [r4, #0] + 80151b2: f7ff f86d bl 8014290 + 80151b6: b138 cbz r0, 80151c8 <_svfiprintf_r+0x150> + 80151b8: 2240 movs r2, #64 @ 0x40 + 80151ba: 9b04 ldr r3, [sp, #16] + 80151bc: eba0 000a sub.w r0, r0, sl + 80151c0: 4082 lsls r2, r0 + 80151c2: 4313 orrs r3, r2 + 80151c4: 3401 adds r4, #1 + 80151c6: 9304 str r3, [sp, #16] + 80151c8: f814 1b01 ldrb.w r1, [r4], #1 + 80151cc: 2206 movs r2, #6 + 80151ce: 4825 ldr r0, [pc, #148] @ (8015264 <_svfiprintf_r+0x1ec>) + 80151d0: f88d 1028 strb.w r1, [sp, #40] @ 0x28 + 80151d4: f7ff f85c bl 8014290 + 80151d8: 2800 cmp r0, #0 + 80151da: d036 beq.n 801524a <_svfiprintf_r+0x1d2> + 80151dc: 4b22 ldr r3, [pc, #136] @ (8015268 <_svfiprintf_r+0x1f0>) + 80151de: bb1b cbnz r3, 8015228 <_svfiprintf_r+0x1b0> + 80151e0: 9b03 ldr r3, [sp, #12] + 80151e2: 3307 adds r3, #7 + 80151e4: f023 0307 bic.w r3, r3, #7 + 80151e8: 3308 adds r3, #8 + 80151ea: 9303 str r3, [sp, #12] + 80151ec: 9b09 ldr r3, [sp, #36] @ 0x24 + 80151ee: 4433 add r3, r6 + 80151f0: 9309 str r3, [sp, #36] @ 0x24 + 80151f2: e76a b.n 80150ca <_svfiprintf_r+0x52> + 80151f4: 460c mov r4, r1 + 80151f6: 2001 movs r0, #1 + 80151f8: fb0c 3202 mla r2, ip, r2, r3 + 80151fc: e7a8 b.n 8015150 <_svfiprintf_r+0xd8> + 80151fe: 2300 movs r3, #0 + 8015200: f04f 0c0a mov.w ip, #10 + 8015204: 4619 mov r1, r3 + 8015206: 3401 adds r4, #1 + 8015208: 9305 str r3, [sp, #20] + 801520a: 4620 mov r0, r4 + 801520c: f810 2b01 ldrb.w r2, [r0], #1 + 8015210: 3a30 subs r2, #48 @ 0x30 + 8015212: 2a09 cmp r2, #9 + 8015214: d903 bls.n 801521e <_svfiprintf_r+0x1a6> + 8015216: 2b00 cmp r3, #0 + 8015218: d0c6 beq.n 80151a8 <_svfiprintf_r+0x130> + 801521a: 9105 str r1, [sp, #20] + 801521c: e7c4 b.n 80151a8 <_svfiprintf_r+0x130> + 801521e: 4604 mov r4, r0 + 8015220: 2301 movs r3, #1 + 8015222: fb0c 2101 mla r1, ip, r1, r2 + 8015226: e7f0 b.n 801520a <_svfiprintf_r+0x192> + 8015228: ab03 add r3, sp, #12 + 801522a: 9300 str r3, [sp, #0] + 801522c: 462a mov r2, r5 + 801522e: 4638 mov r0, r7 + 8015230: 4b0e ldr r3, [pc, #56] @ (801526c <_svfiprintf_r+0x1f4>) + 8015232: a904 add r1, sp, #16 + 8015234: f7fe fa60 bl 80136f8 <_printf_float> + 8015238: 1c42 adds r2, r0, #1 + 801523a: 4606 mov r6, r0 + 801523c: d1d6 bne.n 80151ec <_svfiprintf_r+0x174> + 801523e: 89ab ldrh r3, [r5, #12] + 8015240: 065b lsls r3, r3, #25 + 8015242: f53f af2d bmi.w 80150a0 <_svfiprintf_r+0x28> + 8015246: 9809 ldr r0, [sp, #36] @ 0x24 + 8015248: e72c b.n 80150a4 <_svfiprintf_r+0x2c> + 801524a: ab03 add r3, sp, #12 + 801524c: 9300 str r3, [sp, #0] + 801524e: 462a mov r2, r5 + 8015250: 4638 mov r0, r7 + 8015252: 4b06 ldr r3, [pc, #24] @ (801526c <_svfiprintf_r+0x1f4>) + 8015254: a904 add r1, sp, #16 + 8015256: f7fe fced bl 8013c34 <_printf_i> + 801525a: e7ed b.n 8015238 <_svfiprintf_r+0x1c0> + 801525c: 08016d79 .word 0x08016d79 + 8015260: 08016d7f .word 0x08016d7f + 8015264: 08016d83 .word 0x08016d83 + 8015268: 080136f9 .word 0x080136f9 + 801526c: 08014fc1 .word 0x08014fc1 + +08015270 <__sfputc_r>: + 8015270: 6893 ldr r3, [r2, #8] + 8015272: b410 push {r4} + 8015274: 3b01 subs r3, #1 + 8015276: 2b00 cmp r3, #0 + 8015278: 6093 str r3, [r2, #8] + 801527a: da07 bge.n 801528c <__sfputc_r+0x1c> + 801527c: 6994 ldr r4, [r2, #24] + 801527e: 42a3 cmp r3, r4 + 8015280: db01 blt.n 8015286 <__sfputc_r+0x16> + 8015282: 290a cmp r1, #10 + 8015284: d102 bne.n 801528c <__sfputc_r+0x1c> + 8015286: bc10 pop {r4} + 8015288: f000 be8e b.w 8015fa8 <__swbuf_r> + 801528c: 6813 ldr r3, [r2, #0] + 801528e: 1c58 adds r0, r3, #1 + 8015290: 6010 str r0, [r2, #0] + 8015292: 7019 strb r1, [r3, #0] + 8015294: 4608 mov r0, r1 + 8015296: bc10 pop {r4} + 8015298: 4770 bx lr + +0801529a <__sfputs_r>: + 801529a: b5f8 push {r3, r4, r5, r6, r7, lr} + 801529c: 4606 mov r6, r0 + 801529e: 460f mov r7, r1 + 80152a0: 4614 mov r4, r2 + 80152a2: 18d5 adds r5, r2, r3 + 80152a4: 42ac cmp r4, r5 + 80152a6: d101 bne.n 80152ac <__sfputs_r+0x12> + 80152a8: 2000 movs r0, #0 + 80152aa: e007 b.n 80152bc <__sfputs_r+0x22> + 80152ac: 463a mov r2, r7 + 80152ae: 4630 mov r0, r6 + 80152b0: f814 1b01 ldrb.w r1, [r4], #1 + 80152b4: f7ff ffdc bl 8015270 <__sfputc_r> + 80152b8: 1c43 adds r3, r0, #1 + 80152ba: d1f3 bne.n 80152a4 <__sfputs_r+0xa> + 80152bc: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +080152c0 <_vfiprintf_r>: + 80152c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80152c4: 460d mov r5, r1 + 80152c6: 4614 mov r4, r2 + 80152c8: 4698 mov r8, r3 + 80152ca: 4606 mov r6, r0 + 80152cc: b09d sub sp, #116 @ 0x74 + 80152ce: b118 cbz r0, 80152d8 <_vfiprintf_r+0x18> + 80152d0: 6a03 ldr r3, [r0, #32] + 80152d2: b90b cbnz r3, 80152d8 <_vfiprintf_r+0x18> + 80152d4: f7fe fe58 bl 8013f88 <__sinit> + 80152d8: 6e6b ldr r3, [r5, #100] @ 0x64 + 80152da: 07d9 lsls r1, r3, #31 + 80152dc: d405 bmi.n 80152ea <_vfiprintf_r+0x2a> + 80152de: 89ab ldrh r3, [r5, #12] + 80152e0: 059a lsls r2, r3, #22 + 80152e2: d402 bmi.n 80152ea <_vfiprintf_r+0x2a> + 80152e4: 6da8 ldr r0, [r5, #88] @ 0x58 + 80152e6: f7fe ffcc bl 8014282 <__retarget_lock_acquire_recursive> + 80152ea: 89ab ldrh r3, [r5, #12] + 80152ec: 071b lsls r3, r3, #28 + 80152ee: d501 bpl.n 80152f4 <_vfiprintf_r+0x34> + 80152f0: 692b ldr r3, [r5, #16] + 80152f2: b99b cbnz r3, 801531c <_vfiprintf_r+0x5c> + 80152f4: 4629 mov r1, r5 + 80152f6: 4630 mov r0, r6 + 80152f8: f000 fe94 bl 8016024 <__swsetup_r> + 80152fc: b170 cbz r0, 801531c <_vfiprintf_r+0x5c> + 80152fe: 6e6b ldr r3, [r5, #100] @ 0x64 + 8015300: 07dc lsls r4, r3, #31 + 8015302: d504 bpl.n 801530e <_vfiprintf_r+0x4e> + 8015304: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8015308: b01d add sp, #116 @ 0x74 + 801530a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801530e: 89ab ldrh r3, [r5, #12] + 8015310: 0598 lsls r0, r3, #22 + 8015312: d4f7 bmi.n 8015304 <_vfiprintf_r+0x44> + 8015314: 6da8 ldr r0, [r5, #88] @ 0x58 + 8015316: f7fe ffb5 bl 8014284 <__retarget_lock_release_recursive> + 801531a: e7f3 b.n 8015304 <_vfiprintf_r+0x44> + 801531c: 2300 movs r3, #0 + 801531e: 9309 str r3, [sp, #36] @ 0x24 + 8015320: 2320 movs r3, #32 + 8015322: f88d 3029 strb.w r3, [sp, #41] @ 0x29 + 8015326: 2330 movs r3, #48 @ 0x30 + 8015328: f04f 0901 mov.w r9, #1 + 801532c: f8cd 800c str.w r8, [sp, #12] + 8015330: f8df 81a8 ldr.w r8, [pc, #424] @ 80154dc <_vfiprintf_r+0x21c> + 8015334: f88d 302a strb.w r3, [sp, #42] @ 0x2a + 8015338: 4623 mov r3, r4 + 801533a: 469a mov sl, r3 + 801533c: f813 2b01 ldrb.w r2, [r3], #1 + 8015340: b10a cbz r2, 8015346 <_vfiprintf_r+0x86> + 8015342: 2a25 cmp r2, #37 @ 0x25 + 8015344: d1f9 bne.n 801533a <_vfiprintf_r+0x7a> + 8015346: ebba 0b04 subs.w fp, sl, r4 + 801534a: d00b beq.n 8015364 <_vfiprintf_r+0xa4> + 801534c: 465b mov r3, fp + 801534e: 4622 mov r2, r4 + 8015350: 4629 mov r1, r5 + 8015352: 4630 mov r0, r6 + 8015354: f7ff ffa1 bl 801529a <__sfputs_r> + 8015358: 3001 adds r0, #1 + 801535a: f000 80a7 beq.w 80154ac <_vfiprintf_r+0x1ec> + 801535e: 9a09 ldr r2, [sp, #36] @ 0x24 + 8015360: 445a add r2, fp + 8015362: 9209 str r2, [sp, #36] @ 0x24 + 8015364: f89a 3000 ldrb.w r3, [sl] + 8015368: 2b00 cmp r3, #0 + 801536a: f000 809f beq.w 80154ac <_vfiprintf_r+0x1ec> + 801536e: 2300 movs r3, #0 + 8015370: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8015374: e9cd 2305 strd r2, r3, [sp, #20] + 8015378: f10a 0a01 add.w sl, sl, #1 + 801537c: 9304 str r3, [sp, #16] + 801537e: 9307 str r3, [sp, #28] + 8015380: f88d 3053 strb.w r3, [sp, #83] @ 0x53 + 8015384: 931a str r3, [sp, #104] @ 0x68 + 8015386: 4654 mov r4, sl + 8015388: 2205 movs r2, #5 + 801538a: f814 1b01 ldrb.w r1, [r4], #1 + 801538e: 4853 ldr r0, [pc, #332] @ (80154dc <_vfiprintf_r+0x21c>) + 8015390: f7fe ff7e bl 8014290 + 8015394: 9a04 ldr r2, [sp, #16] + 8015396: b9d8 cbnz r0, 80153d0 <_vfiprintf_r+0x110> + 8015398: 06d1 lsls r1, r2, #27 + 801539a: bf44 itt mi + 801539c: 2320 movmi r3, #32 + 801539e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 80153a2: 0713 lsls r3, r2, #28 + 80153a4: bf44 itt mi + 80153a6: 232b movmi r3, #43 @ 0x2b + 80153a8: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 + 80153ac: f89a 3000 ldrb.w r3, [sl] + 80153b0: 2b2a cmp r3, #42 @ 0x2a + 80153b2: d015 beq.n 80153e0 <_vfiprintf_r+0x120> + 80153b4: 4654 mov r4, sl + 80153b6: 2000 movs r0, #0 + 80153b8: f04f 0c0a mov.w ip, #10 + 80153bc: 9a07 ldr r2, [sp, #28] + 80153be: 4621 mov r1, r4 + 80153c0: f811 3b01 ldrb.w r3, [r1], #1 + 80153c4: 3b30 subs r3, #48 @ 0x30 + 80153c6: 2b09 cmp r3, #9 + 80153c8: d94b bls.n 8015462 <_vfiprintf_r+0x1a2> + 80153ca: b1b0 cbz r0, 80153fa <_vfiprintf_r+0x13a> + 80153cc: 9207 str r2, [sp, #28] + 80153ce: e014 b.n 80153fa <_vfiprintf_r+0x13a> + 80153d0: eba0 0308 sub.w r3, r0, r8 + 80153d4: fa09 f303 lsl.w r3, r9, r3 + 80153d8: 4313 orrs r3, r2 + 80153da: 46a2 mov sl, r4 + 80153dc: 9304 str r3, [sp, #16] + 80153de: e7d2 b.n 8015386 <_vfiprintf_r+0xc6> + 80153e0: 9b03 ldr r3, [sp, #12] + 80153e2: 1d19 adds r1, r3, #4 + 80153e4: 681b ldr r3, [r3, #0] + 80153e6: 9103 str r1, [sp, #12] + 80153e8: 2b00 cmp r3, #0 + 80153ea: bfbb ittet lt + 80153ec: 425b neglt r3, r3 + 80153ee: f042 0202 orrlt.w r2, r2, #2 + 80153f2: 9307 strge r3, [sp, #28] + 80153f4: 9307 strlt r3, [sp, #28] + 80153f6: bfb8 it lt + 80153f8: 9204 strlt r2, [sp, #16] + 80153fa: 7823 ldrb r3, [r4, #0] + 80153fc: 2b2e cmp r3, #46 @ 0x2e + 80153fe: d10a bne.n 8015416 <_vfiprintf_r+0x156> + 8015400: 7863 ldrb r3, [r4, #1] + 8015402: 2b2a cmp r3, #42 @ 0x2a + 8015404: d132 bne.n 801546c <_vfiprintf_r+0x1ac> + 8015406: 9b03 ldr r3, [sp, #12] + 8015408: 3402 adds r4, #2 + 801540a: 1d1a adds r2, r3, #4 + 801540c: 681b ldr r3, [r3, #0] + 801540e: 9203 str r2, [sp, #12] + 8015410: ea43 73e3 orr.w r3, r3, r3, asr #31 + 8015414: 9305 str r3, [sp, #20] + 8015416: f8df a0c8 ldr.w sl, [pc, #200] @ 80154e0 <_vfiprintf_r+0x220> + 801541a: 2203 movs r2, #3 + 801541c: 4650 mov r0, sl + 801541e: 7821 ldrb r1, [r4, #0] + 8015420: f7fe ff36 bl 8014290 + 8015424: b138 cbz r0, 8015436 <_vfiprintf_r+0x176> + 8015426: 2240 movs r2, #64 @ 0x40 + 8015428: 9b04 ldr r3, [sp, #16] + 801542a: eba0 000a sub.w r0, r0, sl + 801542e: 4082 lsls r2, r0 + 8015430: 4313 orrs r3, r2 + 8015432: 3401 adds r4, #1 + 8015434: 9304 str r3, [sp, #16] + 8015436: f814 1b01 ldrb.w r1, [r4], #1 + 801543a: 2206 movs r2, #6 + 801543c: 4829 ldr r0, [pc, #164] @ (80154e4 <_vfiprintf_r+0x224>) + 801543e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 + 8015442: f7fe ff25 bl 8014290 + 8015446: 2800 cmp r0, #0 + 8015448: d03f beq.n 80154ca <_vfiprintf_r+0x20a> + 801544a: 4b27 ldr r3, [pc, #156] @ (80154e8 <_vfiprintf_r+0x228>) + 801544c: bb1b cbnz r3, 8015496 <_vfiprintf_r+0x1d6> + 801544e: 9b03 ldr r3, [sp, #12] + 8015450: 3307 adds r3, #7 + 8015452: f023 0307 bic.w r3, r3, #7 + 8015456: 3308 adds r3, #8 + 8015458: 9303 str r3, [sp, #12] + 801545a: 9b09 ldr r3, [sp, #36] @ 0x24 + 801545c: 443b add r3, r7 + 801545e: 9309 str r3, [sp, #36] @ 0x24 + 8015460: e76a b.n 8015338 <_vfiprintf_r+0x78> + 8015462: 460c mov r4, r1 + 8015464: 2001 movs r0, #1 + 8015466: fb0c 3202 mla r2, ip, r2, r3 + 801546a: e7a8 b.n 80153be <_vfiprintf_r+0xfe> + 801546c: 2300 movs r3, #0 + 801546e: f04f 0c0a mov.w ip, #10 + 8015472: 4619 mov r1, r3 + 8015474: 3401 adds r4, #1 + 8015476: 9305 str r3, [sp, #20] + 8015478: 4620 mov r0, r4 + 801547a: f810 2b01 ldrb.w r2, [r0], #1 + 801547e: 3a30 subs r2, #48 @ 0x30 + 8015480: 2a09 cmp r2, #9 + 8015482: d903 bls.n 801548c <_vfiprintf_r+0x1cc> + 8015484: 2b00 cmp r3, #0 + 8015486: d0c6 beq.n 8015416 <_vfiprintf_r+0x156> + 8015488: 9105 str r1, [sp, #20] + 801548a: e7c4 b.n 8015416 <_vfiprintf_r+0x156> + 801548c: 4604 mov r4, r0 + 801548e: 2301 movs r3, #1 + 8015490: fb0c 2101 mla r1, ip, r1, r2 + 8015494: e7f0 b.n 8015478 <_vfiprintf_r+0x1b8> + 8015496: ab03 add r3, sp, #12 + 8015498: 9300 str r3, [sp, #0] + 801549a: 462a mov r2, r5 + 801549c: 4630 mov r0, r6 + 801549e: 4b13 ldr r3, [pc, #76] @ (80154ec <_vfiprintf_r+0x22c>) + 80154a0: a904 add r1, sp, #16 + 80154a2: f7fe f929 bl 80136f8 <_printf_float> + 80154a6: 4607 mov r7, r0 + 80154a8: 1c78 adds r0, r7, #1 + 80154aa: d1d6 bne.n 801545a <_vfiprintf_r+0x19a> + 80154ac: 6e6b ldr r3, [r5, #100] @ 0x64 + 80154ae: 07d9 lsls r1, r3, #31 + 80154b0: d405 bmi.n 80154be <_vfiprintf_r+0x1fe> + 80154b2: 89ab ldrh r3, [r5, #12] + 80154b4: 059a lsls r2, r3, #22 + 80154b6: d402 bmi.n 80154be <_vfiprintf_r+0x1fe> + 80154b8: 6da8 ldr r0, [r5, #88] @ 0x58 + 80154ba: f7fe fee3 bl 8014284 <__retarget_lock_release_recursive> + 80154be: 89ab ldrh r3, [r5, #12] + 80154c0: 065b lsls r3, r3, #25 + 80154c2: f53f af1f bmi.w 8015304 <_vfiprintf_r+0x44> + 80154c6: 9809 ldr r0, [sp, #36] @ 0x24 + 80154c8: e71e b.n 8015308 <_vfiprintf_r+0x48> + 80154ca: ab03 add r3, sp, #12 + 80154cc: 9300 str r3, [sp, #0] + 80154ce: 462a mov r2, r5 + 80154d0: 4630 mov r0, r6 + 80154d2: 4b06 ldr r3, [pc, #24] @ (80154ec <_vfiprintf_r+0x22c>) + 80154d4: a904 add r1, sp, #16 + 80154d6: f7fe fbad bl 8013c34 <_printf_i> + 80154da: e7e4 b.n 80154a6 <_vfiprintf_r+0x1e6> + 80154dc: 08016d79 .word 0x08016d79 + 80154e0: 08016d7f .word 0x08016d7f + 80154e4: 08016d83 .word 0x08016d83 + 80154e8: 080136f9 .word 0x080136f9 + 80154ec: 0801529b .word 0x0801529b + +080154f0 : + 80154f0: 4b02 ldr r3, [pc, #8] @ (80154fc ) + 80154f2: 4601 mov r1, r0 + 80154f4: 6818 ldr r0, [r3, #0] + 80154f6: f000 b825 b.w 8015544 <_malloc_r> + 80154fa: bf00 nop + 80154fc: 20000084 .word 0x20000084 + +08015500 : + 8015500: b570 push {r4, r5, r6, lr} + 8015502: 4e0f ldr r6, [pc, #60] @ (8015540 ) + 8015504: 460c mov r4, r1 + 8015506: 6831 ldr r1, [r6, #0] + 8015508: 4605 mov r5, r0 + 801550a: b911 cbnz r1, 8015512 + 801550c: f000 fe90 bl 8016230 <_sbrk_r> + 8015510: 6030 str r0, [r6, #0] + 8015512: 4621 mov r1, r4 + 8015514: 4628 mov r0, r5 + 8015516: f000 fe8b bl 8016230 <_sbrk_r> + 801551a: 1c43 adds r3, r0, #1 + 801551c: d103 bne.n 8015526 + 801551e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff + 8015522: 4620 mov r0, r4 + 8015524: bd70 pop {r4, r5, r6, pc} + 8015526: 1cc4 adds r4, r0, #3 + 8015528: f024 0403 bic.w r4, r4, #3 + 801552c: 42a0 cmp r0, r4 + 801552e: d0f8 beq.n 8015522 + 8015530: 1a21 subs r1, r4, r0 + 8015532: 4628 mov r0, r5 + 8015534: f000 fe7c bl 8016230 <_sbrk_r> + 8015538: 3001 adds r0, #1 + 801553a: d1f2 bne.n 8015522 + 801553c: e7ef b.n 801551e + 801553e: bf00 nop + 8015540: 20000fa4 .word 0x20000fa4 + +08015544 <_malloc_r>: + 8015544: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8015548: 1ccd adds r5, r1, #3 + 801554a: f025 0503 bic.w r5, r5, #3 + 801554e: 3508 adds r5, #8 + 8015550: 2d0c cmp r5, #12 + 8015552: bf38 it cc + 8015554: 250c movcc r5, #12 + 8015556: 2d00 cmp r5, #0 + 8015558: 4606 mov r6, r0 + 801555a: db01 blt.n 8015560 <_malloc_r+0x1c> + 801555c: 42a9 cmp r1, r5 + 801555e: d904 bls.n 801556a <_malloc_r+0x26> + 8015560: 230c movs r3, #12 + 8015562: 6033 str r3, [r6, #0] + 8015564: 2000 movs r0, #0 + 8015566: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 801556a: f8df 80d4 ldr.w r8, [pc, #212] @ 8015640 <_malloc_r+0xfc> + 801556e: f000 f911 bl 8015794 <__malloc_lock> + 8015572: f8d8 3000 ldr.w r3, [r8] + 8015576: 461c mov r4, r3 + 8015578: bb44 cbnz r4, 80155cc <_malloc_r+0x88> + 801557a: 4629 mov r1, r5 + 801557c: 4630 mov r0, r6 + 801557e: f7ff ffbf bl 8015500 + 8015582: 1c43 adds r3, r0, #1 + 8015584: 4604 mov r4, r0 + 8015586: d158 bne.n 801563a <_malloc_r+0xf6> + 8015588: f8d8 4000 ldr.w r4, [r8] + 801558c: 4627 mov r7, r4 + 801558e: 2f00 cmp r7, #0 + 8015590: d143 bne.n 801561a <_malloc_r+0xd6> + 8015592: 2c00 cmp r4, #0 + 8015594: d04b beq.n 801562e <_malloc_r+0xea> + 8015596: 6823 ldr r3, [r4, #0] + 8015598: 4639 mov r1, r7 + 801559a: 4630 mov r0, r6 + 801559c: eb04 0903 add.w r9, r4, r3 + 80155a0: f000 fe46 bl 8016230 <_sbrk_r> + 80155a4: 4581 cmp r9, r0 + 80155a6: d142 bne.n 801562e <_malloc_r+0xea> + 80155a8: 6821 ldr r1, [r4, #0] + 80155aa: 4630 mov r0, r6 + 80155ac: 1a6d subs r5, r5, r1 + 80155ae: 4629 mov r1, r5 + 80155b0: f7ff ffa6 bl 8015500 + 80155b4: 3001 adds r0, #1 + 80155b6: d03a beq.n 801562e <_malloc_r+0xea> + 80155b8: 6823 ldr r3, [r4, #0] + 80155ba: 442b add r3, r5 + 80155bc: 6023 str r3, [r4, #0] + 80155be: f8d8 3000 ldr.w r3, [r8] + 80155c2: 685a ldr r2, [r3, #4] + 80155c4: bb62 cbnz r2, 8015620 <_malloc_r+0xdc> + 80155c6: f8c8 7000 str.w r7, [r8] + 80155ca: e00f b.n 80155ec <_malloc_r+0xa8> + 80155cc: 6822 ldr r2, [r4, #0] + 80155ce: 1b52 subs r2, r2, r5 + 80155d0: d420 bmi.n 8015614 <_malloc_r+0xd0> + 80155d2: 2a0b cmp r2, #11 + 80155d4: d917 bls.n 8015606 <_malloc_r+0xc2> + 80155d6: 1961 adds r1, r4, r5 + 80155d8: 42a3 cmp r3, r4 + 80155da: 6025 str r5, [r4, #0] + 80155dc: bf18 it ne + 80155de: 6059 strne r1, [r3, #4] + 80155e0: 6863 ldr r3, [r4, #4] + 80155e2: bf08 it eq + 80155e4: f8c8 1000 streq.w r1, [r8] + 80155e8: 5162 str r2, [r4, r5] + 80155ea: 604b str r3, [r1, #4] + 80155ec: 4630 mov r0, r6 + 80155ee: f000 f8d7 bl 80157a0 <__malloc_unlock> + 80155f2: f104 000b add.w r0, r4, #11 + 80155f6: 1d23 adds r3, r4, #4 + 80155f8: f020 0007 bic.w r0, r0, #7 + 80155fc: 1ac2 subs r2, r0, r3 + 80155fe: bf1c itt ne + 8015600: 1a1b subne r3, r3, r0 + 8015602: 50a3 strne r3, [r4, r2] + 8015604: e7af b.n 8015566 <_malloc_r+0x22> + 8015606: 6862 ldr r2, [r4, #4] + 8015608: 42a3 cmp r3, r4 + 801560a: bf0c ite eq + 801560c: f8c8 2000 streq.w r2, [r8] + 8015610: 605a strne r2, [r3, #4] + 8015612: e7eb b.n 80155ec <_malloc_r+0xa8> + 8015614: 4623 mov r3, r4 + 8015616: 6864 ldr r4, [r4, #4] + 8015618: e7ae b.n 8015578 <_malloc_r+0x34> + 801561a: 463c mov r4, r7 + 801561c: 687f ldr r7, [r7, #4] + 801561e: e7b6 b.n 801558e <_malloc_r+0x4a> + 8015620: 461a mov r2, r3 + 8015622: 685b ldr r3, [r3, #4] + 8015624: 42a3 cmp r3, r4 + 8015626: d1fb bne.n 8015620 <_malloc_r+0xdc> + 8015628: 2300 movs r3, #0 + 801562a: 6053 str r3, [r2, #4] + 801562c: e7de b.n 80155ec <_malloc_r+0xa8> + 801562e: 230c movs r3, #12 + 8015630: 4630 mov r0, r6 + 8015632: 6033 str r3, [r6, #0] + 8015634: f000 f8b4 bl 80157a0 <__malloc_unlock> + 8015638: e794 b.n 8015564 <_malloc_r+0x20> + 801563a: 6005 str r5, [r0, #0] + 801563c: e7d6 b.n 80155ec <_malloc_r+0xa8> + 801563e: bf00 nop + 8015640: 20000fa8 .word 0x20000fa8 + +08015644 <__sflush_r>: + 8015644: f9b1 200c ldrsh.w r2, [r1, #12] + 8015648: b5f8 push {r3, r4, r5, r6, r7, lr} + 801564a: 0716 lsls r6, r2, #28 + 801564c: 4605 mov r5, r0 + 801564e: 460c mov r4, r1 + 8015650: d454 bmi.n 80156fc <__sflush_r+0xb8> + 8015652: 684b ldr r3, [r1, #4] + 8015654: 2b00 cmp r3, #0 + 8015656: dc02 bgt.n 801565e <__sflush_r+0x1a> + 8015658: 6c0b ldr r3, [r1, #64] @ 0x40 + 801565a: 2b00 cmp r3, #0 + 801565c: dd48 ble.n 80156f0 <__sflush_r+0xac> + 801565e: 6ae6 ldr r6, [r4, #44] @ 0x2c + 8015660: 2e00 cmp r6, #0 + 8015662: d045 beq.n 80156f0 <__sflush_r+0xac> + 8015664: 2300 movs r3, #0 + 8015666: f412 5280 ands.w r2, r2, #4096 @ 0x1000 + 801566a: 682f ldr r7, [r5, #0] + 801566c: 6a21 ldr r1, [r4, #32] + 801566e: 602b str r3, [r5, #0] + 8015670: d030 beq.n 80156d4 <__sflush_r+0x90> + 8015672: 6d62 ldr r2, [r4, #84] @ 0x54 + 8015674: 89a3 ldrh r3, [r4, #12] + 8015676: 0759 lsls r1, r3, #29 + 8015678: d505 bpl.n 8015686 <__sflush_r+0x42> + 801567a: 6863 ldr r3, [r4, #4] + 801567c: 1ad2 subs r2, r2, r3 + 801567e: 6b63 ldr r3, [r4, #52] @ 0x34 + 8015680: b10b cbz r3, 8015686 <__sflush_r+0x42> + 8015682: 6c23 ldr r3, [r4, #64] @ 0x40 + 8015684: 1ad2 subs r2, r2, r3 + 8015686: 2300 movs r3, #0 + 8015688: 4628 mov r0, r5 + 801568a: 6ae6 ldr r6, [r4, #44] @ 0x2c + 801568c: 6a21 ldr r1, [r4, #32] + 801568e: 47b0 blx r6 + 8015690: 1c43 adds r3, r0, #1 + 8015692: 89a3 ldrh r3, [r4, #12] + 8015694: d106 bne.n 80156a4 <__sflush_r+0x60> + 8015696: 6829 ldr r1, [r5, #0] + 8015698: 291d cmp r1, #29 + 801569a: d82b bhi.n 80156f4 <__sflush_r+0xb0> + 801569c: 4a28 ldr r2, [pc, #160] @ (8015740 <__sflush_r+0xfc>) + 801569e: 40ca lsrs r2, r1 + 80156a0: 07d6 lsls r6, r2, #31 + 80156a2: d527 bpl.n 80156f4 <__sflush_r+0xb0> + 80156a4: 2200 movs r2, #0 + 80156a6: 6062 str r2, [r4, #4] + 80156a8: 6922 ldr r2, [r4, #16] + 80156aa: 04d9 lsls r1, r3, #19 + 80156ac: 6022 str r2, [r4, #0] + 80156ae: d504 bpl.n 80156ba <__sflush_r+0x76> + 80156b0: 1c42 adds r2, r0, #1 + 80156b2: d101 bne.n 80156b8 <__sflush_r+0x74> + 80156b4: 682b ldr r3, [r5, #0] + 80156b6: b903 cbnz r3, 80156ba <__sflush_r+0x76> + 80156b8: 6560 str r0, [r4, #84] @ 0x54 + 80156ba: 6b61 ldr r1, [r4, #52] @ 0x34 + 80156bc: 602f str r7, [r5, #0] + 80156be: b1b9 cbz r1, 80156f0 <__sflush_r+0xac> + 80156c0: f104 0344 add.w r3, r4, #68 @ 0x44 + 80156c4: 4299 cmp r1, r3 + 80156c6: d002 beq.n 80156ce <__sflush_r+0x8a> + 80156c8: 4628 mov r0, r5 + 80156ca: f000 fe11 bl 80162f0 <_free_r> + 80156ce: 2300 movs r3, #0 + 80156d0: 6363 str r3, [r4, #52] @ 0x34 + 80156d2: e00d b.n 80156f0 <__sflush_r+0xac> + 80156d4: 2301 movs r3, #1 + 80156d6: 4628 mov r0, r5 + 80156d8: 47b0 blx r6 + 80156da: 4602 mov r2, r0 + 80156dc: 1c50 adds r0, r2, #1 + 80156de: d1c9 bne.n 8015674 <__sflush_r+0x30> + 80156e0: 682b ldr r3, [r5, #0] + 80156e2: 2b00 cmp r3, #0 + 80156e4: d0c6 beq.n 8015674 <__sflush_r+0x30> + 80156e6: 2b1d cmp r3, #29 + 80156e8: d001 beq.n 80156ee <__sflush_r+0xaa> + 80156ea: 2b16 cmp r3, #22 + 80156ec: d11d bne.n 801572a <__sflush_r+0xe6> + 80156ee: 602f str r7, [r5, #0] + 80156f0: 2000 movs r0, #0 + 80156f2: e021 b.n 8015738 <__sflush_r+0xf4> + 80156f4: f043 0340 orr.w r3, r3, #64 @ 0x40 + 80156f8: b21b sxth r3, r3 + 80156fa: e01a b.n 8015732 <__sflush_r+0xee> + 80156fc: 690f ldr r7, [r1, #16] + 80156fe: 2f00 cmp r7, #0 + 8015700: d0f6 beq.n 80156f0 <__sflush_r+0xac> + 8015702: 0793 lsls r3, r2, #30 + 8015704: bf18 it ne + 8015706: 2300 movne r3, #0 + 8015708: 680e ldr r6, [r1, #0] + 801570a: bf08 it eq + 801570c: 694b ldreq r3, [r1, #20] + 801570e: 1bf6 subs r6, r6, r7 + 8015710: 600f str r7, [r1, #0] + 8015712: 608b str r3, [r1, #8] + 8015714: 2e00 cmp r6, #0 + 8015716: ddeb ble.n 80156f0 <__sflush_r+0xac> + 8015718: 4633 mov r3, r6 + 801571a: 463a mov r2, r7 + 801571c: 4628 mov r0, r5 + 801571e: 6a21 ldr r1, [r4, #32] + 8015720: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 + 8015724: 47e0 blx ip + 8015726: 2800 cmp r0, #0 + 8015728: dc07 bgt.n 801573a <__sflush_r+0xf6> + 801572a: f9b4 300c ldrsh.w r3, [r4, #12] + 801572e: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8015732: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8015736: 81a3 strh r3, [r4, #12] + 8015738: bdf8 pop {r3, r4, r5, r6, r7, pc} + 801573a: 4407 add r7, r0 + 801573c: 1a36 subs r6, r6, r0 + 801573e: e7e9 b.n 8015714 <__sflush_r+0xd0> + 8015740: 20400001 .word 0x20400001 + +08015744 <_fflush_r>: + 8015744: b538 push {r3, r4, r5, lr} + 8015746: 690b ldr r3, [r1, #16] + 8015748: 4605 mov r5, r0 + 801574a: 460c mov r4, r1 + 801574c: b913 cbnz r3, 8015754 <_fflush_r+0x10> + 801574e: 2500 movs r5, #0 + 8015750: 4628 mov r0, r5 + 8015752: bd38 pop {r3, r4, r5, pc} + 8015754: b118 cbz r0, 801575e <_fflush_r+0x1a> + 8015756: 6a03 ldr r3, [r0, #32] + 8015758: b90b cbnz r3, 801575e <_fflush_r+0x1a> + 801575a: f7fe fc15 bl 8013f88 <__sinit> + 801575e: f9b4 300c ldrsh.w r3, [r4, #12] + 8015762: 2b00 cmp r3, #0 + 8015764: d0f3 beq.n 801574e <_fflush_r+0xa> + 8015766: 6e62 ldr r2, [r4, #100] @ 0x64 + 8015768: 07d0 lsls r0, r2, #31 + 801576a: d404 bmi.n 8015776 <_fflush_r+0x32> + 801576c: 0599 lsls r1, r3, #22 + 801576e: d402 bmi.n 8015776 <_fflush_r+0x32> + 8015770: 6da0 ldr r0, [r4, #88] @ 0x58 + 8015772: f7fe fd86 bl 8014282 <__retarget_lock_acquire_recursive> + 8015776: 4628 mov r0, r5 + 8015778: 4621 mov r1, r4 + 801577a: f7ff ff63 bl 8015644 <__sflush_r> + 801577e: 6e63 ldr r3, [r4, #100] @ 0x64 + 8015780: 4605 mov r5, r0 + 8015782: 07da lsls r2, r3, #31 + 8015784: d4e4 bmi.n 8015750 <_fflush_r+0xc> + 8015786: 89a3 ldrh r3, [r4, #12] + 8015788: 059b lsls r3, r3, #22 + 801578a: d4e1 bmi.n 8015750 <_fflush_r+0xc> + 801578c: 6da0 ldr r0, [r4, #88] @ 0x58 + 801578e: f7fe fd79 bl 8014284 <__retarget_lock_release_recursive> + 8015792: e7dd b.n 8015750 <_fflush_r+0xc> + +08015794 <__malloc_lock>: + 8015794: 4801 ldr r0, [pc, #4] @ (801579c <__malloc_lock+0x8>) + 8015796: f7fe bd74 b.w 8014282 <__retarget_lock_acquire_recursive> + 801579a: bf00 nop + 801579c: 20000fa0 .word 0x20000fa0 + +080157a0 <__malloc_unlock>: + 80157a0: 4801 ldr r0, [pc, #4] @ (80157a8 <__malloc_unlock+0x8>) + 80157a2: f7fe bd6f b.w 8014284 <__retarget_lock_release_recursive> + 80157a6: bf00 nop + 80157a8: 20000fa0 .word 0x20000fa0 + +080157ac <_Balloc>: + 80157ac: b570 push {r4, r5, r6, lr} + 80157ae: 69c6 ldr r6, [r0, #28] + 80157b0: 4604 mov r4, r0 + 80157b2: 460d mov r5, r1 + 80157b4: b976 cbnz r6, 80157d4 <_Balloc+0x28> + 80157b6: 2010 movs r0, #16 + 80157b8: f7ff fe9a bl 80154f0 + 80157bc: 4602 mov r2, r0 + 80157be: 61e0 str r0, [r4, #28] + 80157c0: b920 cbnz r0, 80157cc <_Balloc+0x20> + 80157c2: 216b movs r1, #107 @ 0x6b + 80157c4: 4b17 ldr r3, [pc, #92] @ (8015824 <_Balloc+0x78>) + 80157c6: 4818 ldr r0, [pc, #96] @ (8015828 <_Balloc+0x7c>) + 80157c8: f7fe fd7e bl 80142c8 <__assert_func> + 80157cc: e9c0 6601 strd r6, r6, [r0, #4] + 80157d0: 6006 str r6, [r0, #0] + 80157d2: 60c6 str r6, [r0, #12] + 80157d4: 69e6 ldr r6, [r4, #28] + 80157d6: 68f3 ldr r3, [r6, #12] + 80157d8: b183 cbz r3, 80157fc <_Balloc+0x50> + 80157da: 69e3 ldr r3, [r4, #28] + 80157dc: 68db ldr r3, [r3, #12] + 80157de: f853 0025 ldr.w r0, [r3, r5, lsl #2] + 80157e2: b9b8 cbnz r0, 8015814 <_Balloc+0x68> + 80157e4: 2101 movs r1, #1 + 80157e6: fa01 f605 lsl.w r6, r1, r5 + 80157ea: 1d72 adds r2, r6, #5 + 80157ec: 4620 mov r0, r4 + 80157ee: 0092 lsls r2, r2, #2 + 80157f0: f000 fd69 bl 80162c6 <_calloc_r> + 80157f4: b160 cbz r0, 8015810 <_Balloc+0x64> + 80157f6: e9c0 5601 strd r5, r6, [r0, #4] + 80157fa: e00e b.n 801581a <_Balloc+0x6e> + 80157fc: 2221 movs r2, #33 @ 0x21 + 80157fe: 2104 movs r1, #4 + 8015800: 4620 mov r0, r4 + 8015802: f000 fd60 bl 80162c6 <_calloc_r> + 8015806: 69e3 ldr r3, [r4, #28] + 8015808: 60f0 str r0, [r6, #12] + 801580a: 68db ldr r3, [r3, #12] + 801580c: 2b00 cmp r3, #0 + 801580e: d1e4 bne.n 80157da <_Balloc+0x2e> + 8015810: 2000 movs r0, #0 + 8015812: bd70 pop {r4, r5, r6, pc} + 8015814: 6802 ldr r2, [r0, #0] + 8015816: f843 2025 str.w r2, [r3, r5, lsl #2] + 801581a: 2300 movs r3, #0 + 801581c: e9c0 3303 strd r3, r3, [r0, #12] + 8015820: e7f7 b.n 8015812 <_Balloc+0x66> + 8015822: bf00 nop + 8015824: 08016c58 .word 0x08016c58 + 8015828: 08016d8a .word 0x08016d8a + +0801582c <_Bfree>: + 801582c: b570 push {r4, r5, r6, lr} + 801582e: 69c6 ldr r6, [r0, #28] + 8015830: 4605 mov r5, r0 + 8015832: 460c mov r4, r1 + 8015834: b976 cbnz r6, 8015854 <_Bfree+0x28> + 8015836: 2010 movs r0, #16 + 8015838: f7ff fe5a bl 80154f0 + 801583c: 4602 mov r2, r0 + 801583e: 61e8 str r0, [r5, #28] + 8015840: b920 cbnz r0, 801584c <_Bfree+0x20> + 8015842: 218f movs r1, #143 @ 0x8f + 8015844: 4b08 ldr r3, [pc, #32] @ (8015868 <_Bfree+0x3c>) + 8015846: 4809 ldr r0, [pc, #36] @ (801586c <_Bfree+0x40>) + 8015848: f7fe fd3e bl 80142c8 <__assert_func> + 801584c: e9c0 6601 strd r6, r6, [r0, #4] + 8015850: 6006 str r6, [r0, #0] + 8015852: 60c6 str r6, [r0, #12] + 8015854: b13c cbz r4, 8015866 <_Bfree+0x3a> + 8015856: 69eb ldr r3, [r5, #28] + 8015858: 6862 ldr r2, [r4, #4] + 801585a: 68db ldr r3, [r3, #12] + 801585c: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8015860: 6021 str r1, [r4, #0] + 8015862: f843 4022 str.w r4, [r3, r2, lsl #2] + 8015866: bd70 pop {r4, r5, r6, pc} + 8015868: 08016c58 .word 0x08016c58 + 801586c: 08016d8a .word 0x08016d8a + +08015870 <__multadd>: + 8015870: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8015874: 4607 mov r7, r0 + 8015876: 460c mov r4, r1 + 8015878: 461e mov r6, r3 + 801587a: 2000 movs r0, #0 + 801587c: 690d ldr r5, [r1, #16] + 801587e: f101 0c14 add.w ip, r1, #20 + 8015882: f8dc 3000 ldr.w r3, [ip] + 8015886: 3001 adds r0, #1 + 8015888: b299 uxth r1, r3 + 801588a: fb02 6101 mla r1, r2, r1, r6 + 801588e: 0c1e lsrs r6, r3, #16 + 8015890: 0c0b lsrs r3, r1, #16 + 8015892: fb02 3306 mla r3, r2, r6, r3 + 8015896: b289 uxth r1, r1 + 8015898: eb01 4103 add.w r1, r1, r3, lsl #16 + 801589c: 4285 cmp r5, r0 + 801589e: ea4f 4613 mov.w r6, r3, lsr #16 + 80158a2: f84c 1b04 str.w r1, [ip], #4 + 80158a6: dcec bgt.n 8015882 <__multadd+0x12> + 80158a8: b30e cbz r6, 80158ee <__multadd+0x7e> + 80158aa: 68a3 ldr r3, [r4, #8] + 80158ac: 42ab cmp r3, r5 + 80158ae: dc19 bgt.n 80158e4 <__multadd+0x74> + 80158b0: 6861 ldr r1, [r4, #4] + 80158b2: 4638 mov r0, r7 + 80158b4: 3101 adds r1, #1 + 80158b6: f7ff ff79 bl 80157ac <_Balloc> + 80158ba: 4680 mov r8, r0 + 80158bc: b928 cbnz r0, 80158ca <__multadd+0x5a> + 80158be: 4602 mov r2, r0 + 80158c0: 21ba movs r1, #186 @ 0xba + 80158c2: 4b0c ldr r3, [pc, #48] @ (80158f4 <__multadd+0x84>) + 80158c4: 480c ldr r0, [pc, #48] @ (80158f8 <__multadd+0x88>) + 80158c6: f7fe fcff bl 80142c8 <__assert_func> + 80158ca: 6922 ldr r2, [r4, #16] + 80158cc: f104 010c add.w r1, r4, #12 + 80158d0: 3202 adds r2, #2 + 80158d2: 0092 lsls r2, r2, #2 + 80158d4: 300c adds r0, #12 + 80158d6: f7fe fce9 bl 80142ac + 80158da: 4621 mov r1, r4 + 80158dc: 4638 mov r0, r7 + 80158de: f7ff ffa5 bl 801582c <_Bfree> + 80158e2: 4644 mov r4, r8 + 80158e4: eb04 0385 add.w r3, r4, r5, lsl #2 + 80158e8: 3501 adds r5, #1 + 80158ea: 615e str r6, [r3, #20] + 80158ec: 6125 str r5, [r4, #16] + 80158ee: 4620 mov r0, r4 + 80158f0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80158f4: 08016d68 .word 0x08016d68 + 80158f8: 08016d8a .word 0x08016d8a + +080158fc <__hi0bits>: + 80158fc: 4603 mov r3, r0 + 80158fe: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 + 8015902: bf3a itte cc + 8015904: 0403 lslcc r3, r0, #16 + 8015906: 2010 movcc r0, #16 + 8015908: 2000 movcs r0, #0 + 801590a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 801590e: bf3c itt cc + 8015910: 021b lslcc r3, r3, #8 + 8015912: 3008 addcc r0, #8 + 8015914: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 8015918: bf3c itt cc + 801591a: 011b lslcc r3, r3, #4 + 801591c: 3004 addcc r0, #4 + 801591e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8015922: bf3c itt cc + 8015924: 009b lslcc r3, r3, #2 + 8015926: 3002 addcc r0, #2 + 8015928: 2b00 cmp r3, #0 + 801592a: db05 blt.n 8015938 <__hi0bits+0x3c> + 801592c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 + 8015930: f100 0001 add.w r0, r0, #1 + 8015934: bf08 it eq + 8015936: 2020 moveq r0, #32 + 8015938: 4770 bx lr + +0801593a <__lo0bits>: + 801593a: 6803 ldr r3, [r0, #0] + 801593c: 4602 mov r2, r0 + 801593e: f013 0007 ands.w r0, r3, #7 + 8015942: d00b beq.n 801595c <__lo0bits+0x22> + 8015944: 07d9 lsls r1, r3, #31 + 8015946: d421 bmi.n 801598c <__lo0bits+0x52> + 8015948: 0798 lsls r0, r3, #30 + 801594a: bf49 itett mi + 801594c: 085b lsrmi r3, r3, #1 + 801594e: 089b lsrpl r3, r3, #2 + 8015950: 2001 movmi r0, #1 + 8015952: 6013 strmi r3, [r2, #0] + 8015954: bf5c itt pl + 8015956: 2002 movpl r0, #2 + 8015958: 6013 strpl r3, [r2, #0] + 801595a: 4770 bx lr + 801595c: b299 uxth r1, r3 + 801595e: b909 cbnz r1, 8015964 <__lo0bits+0x2a> + 8015960: 2010 movs r0, #16 + 8015962: 0c1b lsrs r3, r3, #16 + 8015964: b2d9 uxtb r1, r3 + 8015966: b909 cbnz r1, 801596c <__lo0bits+0x32> + 8015968: 3008 adds r0, #8 + 801596a: 0a1b lsrs r3, r3, #8 + 801596c: 0719 lsls r1, r3, #28 + 801596e: bf04 itt eq + 8015970: 091b lsreq r3, r3, #4 + 8015972: 3004 addeq r0, #4 + 8015974: 0799 lsls r1, r3, #30 + 8015976: bf04 itt eq + 8015978: 089b lsreq r3, r3, #2 + 801597a: 3002 addeq r0, #2 + 801597c: 07d9 lsls r1, r3, #31 + 801597e: d403 bmi.n 8015988 <__lo0bits+0x4e> + 8015980: 085b lsrs r3, r3, #1 + 8015982: f100 0001 add.w r0, r0, #1 + 8015986: d003 beq.n 8015990 <__lo0bits+0x56> + 8015988: 6013 str r3, [r2, #0] + 801598a: 4770 bx lr + 801598c: 2000 movs r0, #0 + 801598e: 4770 bx lr + 8015990: 2020 movs r0, #32 + 8015992: 4770 bx lr + +08015994 <__i2b>: + 8015994: b510 push {r4, lr} + 8015996: 460c mov r4, r1 + 8015998: 2101 movs r1, #1 + 801599a: f7ff ff07 bl 80157ac <_Balloc> + 801599e: 4602 mov r2, r0 + 80159a0: b928 cbnz r0, 80159ae <__i2b+0x1a> + 80159a2: f240 1145 movw r1, #325 @ 0x145 + 80159a6: 4b04 ldr r3, [pc, #16] @ (80159b8 <__i2b+0x24>) + 80159a8: 4804 ldr r0, [pc, #16] @ (80159bc <__i2b+0x28>) + 80159aa: f7fe fc8d bl 80142c8 <__assert_func> + 80159ae: 2301 movs r3, #1 + 80159b0: 6144 str r4, [r0, #20] + 80159b2: 6103 str r3, [r0, #16] + 80159b4: bd10 pop {r4, pc} + 80159b6: bf00 nop + 80159b8: 08016d68 .word 0x08016d68 + 80159bc: 08016d8a .word 0x08016d8a + +080159c0 <__multiply>: + 80159c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80159c4: 4617 mov r7, r2 + 80159c6: 690a ldr r2, [r1, #16] + 80159c8: 693b ldr r3, [r7, #16] + 80159ca: 4689 mov r9, r1 + 80159cc: 429a cmp r2, r3 + 80159ce: bfa2 ittt ge + 80159d0: 463b movge r3, r7 + 80159d2: 460f movge r7, r1 + 80159d4: 4699 movge r9, r3 + 80159d6: 693d ldr r5, [r7, #16] + 80159d8: f8d9 a010 ldr.w sl, [r9, #16] + 80159dc: 68bb ldr r3, [r7, #8] + 80159de: 6879 ldr r1, [r7, #4] + 80159e0: eb05 060a add.w r6, r5, sl + 80159e4: 42b3 cmp r3, r6 + 80159e6: b085 sub sp, #20 + 80159e8: bfb8 it lt + 80159ea: 3101 addlt r1, #1 + 80159ec: f7ff fede bl 80157ac <_Balloc> + 80159f0: b930 cbnz r0, 8015a00 <__multiply+0x40> + 80159f2: 4602 mov r2, r0 + 80159f4: f44f 71b1 mov.w r1, #354 @ 0x162 + 80159f8: 4b40 ldr r3, [pc, #256] @ (8015afc <__multiply+0x13c>) + 80159fa: 4841 ldr r0, [pc, #260] @ (8015b00 <__multiply+0x140>) + 80159fc: f7fe fc64 bl 80142c8 <__assert_func> + 8015a00: f100 0414 add.w r4, r0, #20 + 8015a04: 4623 mov r3, r4 + 8015a06: 2200 movs r2, #0 + 8015a08: eb04 0e86 add.w lr, r4, r6, lsl #2 + 8015a0c: 4573 cmp r3, lr + 8015a0e: d320 bcc.n 8015a52 <__multiply+0x92> + 8015a10: f107 0814 add.w r8, r7, #20 + 8015a14: f109 0114 add.w r1, r9, #20 + 8015a18: eb08 0585 add.w r5, r8, r5, lsl #2 + 8015a1c: eb01 038a add.w r3, r1, sl, lsl #2 + 8015a20: 9302 str r3, [sp, #8] + 8015a22: 1beb subs r3, r5, r7 + 8015a24: 3b15 subs r3, #21 + 8015a26: f023 0303 bic.w r3, r3, #3 + 8015a2a: 3304 adds r3, #4 + 8015a2c: 3715 adds r7, #21 + 8015a2e: 42bd cmp r5, r7 + 8015a30: bf38 it cc + 8015a32: 2304 movcc r3, #4 + 8015a34: 9301 str r3, [sp, #4] + 8015a36: 9b02 ldr r3, [sp, #8] + 8015a38: 9103 str r1, [sp, #12] + 8015a3a: 428b cmp r3, r1 + 8015a3c: d80c bhi.n 8015a58 <__multiply+0x98> + 8015a3e: 2e00 cmp r6, #0 + 8015a40: dd03 ble.n 8015a4a <__multiply+0x8a> + 8015a42: f85e 3d04 ldr.w r3, [lr, #-4]! + 8015a46: 2b00 cmp r3, #0 + 8015a48: d055 beq.n 8015af6 <__multiply+0x136> + 8015a4a: 6106 str r6, [r0, #16] + 8015a4c: b005 add sp, #20 + 8015a4e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8015a52: f843 2b04 str.w r2, [r3], #4 + 8015a56: e7d9 b.n 8015a0c <__multiply+0x4c> + 8015a58: f8b1 a000 ldrh.w sl, [r1] + 8015a5c: f1ba 0f00 cmp.w sl, #0 + 8015a60: d01f beq.n 8015aa2 <__multiply+0xe2> + 8015a62: 46c4 mov ip, r8 + 8015a64: 46a1 mov r9, r4 + 8015a66: 2700 movs r7, #0 + 8015a68: f85c 2b04 ldr.w r2, [ip], #4 + 8015a6c: f8d9 3000 ldr.w r3, [r9] + 8015a70: fa1f fb82 uxth.w fp, r2 + 8015a74: b29b uxth r3, r3 + 8015a76: fb0a 330b mla r3, sl, fp, r3 + 8015a7a: 443b add r3, r7 + 8015a7c: f8d9 7000 ldr.w r7, [r9] + 8015a80: 0c12 lsrs r2, r2, #16 + 8015a82: 0c3f lsrs r7, r7, #16 + 8015a84: fb0a 7202 mla r2, sl, r2, r7 + 8015a88: eb02 4213 add.w r2, r2, r3, lsr #16 + 8015a8c: b29b uxth r3, r3 + 8015a8e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8015a92: 4565 cmp r5, ip + 8015a94: ea4f 4712 mov.w r7, r2, lsr #16 + 8015a98: f849 3b04 str.w r3, [r9], #4 + 8015a9c: d8e4 bhi.n 8015a68 <__multiply+0xa8> + 8015a9e: 9b01 ldr r3, [sp, #4] + 8015aa0: 50e7 str r7, [r4, r3] + 8015aa2: 9b03 ldr r3, [sp, #12] + 8015aa4: 3104 adds r1, #4 + 8015aa6: f8b3 9002 ldrh.w r9, [r3, #2] + 8015aaa: f1b9 0f00 cmp.w r9, #0 + 8015aae: d020 beq.n 8015af2 <__multiply+0x132> + 8015ab0: 4647 mov r7, r8 + 8015ab2: 46a4 mov ip, r4 + 8015ab4: f04f 0a00 mov.w sl, #0 + 8015ab8: 6823 ldr r3, [r4, #0] + 8015aba: f8b7 b000 ldrh.w fp, [r7] + 8015abe: f8bc 2002 ldrh.w r2, [ip, #2] + 8015ac2: b29b uxth r3, r3 + 8015ac4: fb09 220b mla r2, r9, fp, r2 + 8015ac8: 4452 add r2, sl + 8015aca: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8015ace: f84c 3b04 str.w r3, [ip], #4 + 8015ad2: f857 3b04 ldr.w r3, [r7], #4 + 8015ad6: ea4f 4a13 mov.w sl, r3, lsr #16 + 8015ada: f8bc 3000 ldrh.w r3, [ip] + 8015ade: 42bd cmp r5, r7 + 8015ae0: fb09 330a mla r3, r9, sl, r3 + 8015ae4: eb03 4312 add.w r3, r3, r2, lsr #16 + 8015ae8: ea4f 4a13 mov.w sl, r3, lsr #16 + 8015aec: d8e5 bhi.n 8015aba <__multiply+0xfa> + 8015aee: 9a01 ldr r2, [sp, #4] + 8015af0: 50a3 str r3, [r4, r2] + 8015af2: 3404 adds r4, #4 + 8015af4: e79f b.n 8015a36 <__multiply+0x76> + 8015af6: 3e01 subs r6, #1 + 8015af8: e7a1 b.n 8015a3e <__multiply+0x7e> + 8015afa: bf00 nop + 8015afc: 08016d68 .word 0x08016d68 + 8015b00: 08016d8a .word 0x08016d8a + +08015b04 <__pow5mult>: + 8015b04: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8015b08: 4615 mov r5, r2 + 8015b0a: f012 0203 ands.w r2, r2, #3 + 8015b0e: 4607 mov r7, r0 + 8015b10: 460e mov r6, r1 + 8015b12: d007 beq.n 8015b24 <__pow5mult+0x20> + 8015b14: 4c25 ldr r4, [pc, #148] @ (8015bac <__pow5mult+0xa8>) + 8015b16: 3a01 subs r2, #1 + 8015b18: 2300 movs r3, #0 + 8015b1a: f854 2022 ldr.w r2, [r4, r2, lsl #2] + 8015b1e: f7ff fea7 bl 8015870 <__multadd> + 8015b22: 4606 mov r6, r0 + 8015b24: 10ad asrs r5, r5, #2 + 8015b26: d03d beq.n 8015ba4 <__pow5mult+0xa0> + 8015b28: 69fc ldr r4, [r7, #28] + 8015b2a: b97c cbnz r4, 8015b4c <__pow5mult+0x48> + 8015b2c: 2010 movs r0, #16 + 8015b2e: f7ff fcdf bl 80154f0 + 8015b32: 4602 mov r2, r0 + 8015b34: 61f8 str r0, [r7, #28] + 8015b36: b928 cbnz r0, 8015b44 <__pow5mult+0x40> + 8015b38: f240 11b3 movw r1, #435 @ 0x1b3 + 8015b3c: 4b1c ldr r3, [pc, #112] @ (8015bb0 <__pow5mult+0xac>) + 8015b3e: 481d ldr r0, [pc, #116] @ (8015bb4 <__pow5mult+0xb0>) + 8015b40: f7fe fbc2 bl 80142c8 <__assert_func> + 8015b44: e9c0 4401 strd r4, r4, [r0, #4] + 8015b48: 6004 str r4, [r0, #0] + 8015b4a: 60c4 str r4, [r0, #12] + 8015b4c: f8d7 801c ldr.w r8, [r7, #28] + 8015b50: f8d8 4008 ldr.w r4, [r8, #8] + 8015b54: b94c cbnz r4, 8015b6a <__pow5mult+0x66> + 8015b56: f240 2171 movw r1, #625 @ 0x271 + 8015b5a: 4638 mov r0, r7 + 8015b5c: f7ff ff1a bl 8015994 <__i2b> + 8015b60: 2300 movs r3, #0 + 8015b62: 4604 mov r4, r0 + 8015b64: f8c8 0008 str.w r0, [r8, #8] + 8015b68: 6003 str r3, [r0, #0] + 8015b6a: f04f 0900 mov.w r9, #0 + 8015b6e: 07eb lsls r3, r5, #31 + 8015b70: d50a bpl.n 8015b88 <__pow5mult+0x84> + 8015b72: 4631 mov r1, r6 + 8015b74: 4622 mov r2, r4 + 8015b76: 4638 mov r0, r7 + 8015b78: f7ff ff22 bl 80159c0 <__multiply> + 8015b7c: 4680 mov r8, r0 + 8015b7e: 4631 mov r1, r6 + 8015b80: 4638 mov r0, r7 + 8015b82: f7ff fe53 bl 801582c <_Bfree> + 8015b86: 4646 mov r6, r8 + 8015b88: 106d asrs r5, r5, #1 + 8015b8a: d00b beq.n 8015ba4 <__pow5mult+0xa0> + 8015b8c: 6820 ldr r0, [r4, #0] + 8015b8e: b938 cbnz r0, 8015ba0 <__pow5mult+0x9c> + 8015b90: 4622 mov r2, r4 + 8015b92: 4621 mov r1, r4 + 8015b94: 4638 mov r0, r7 + 8015b96: f7ff ff13 bl 80159c0 <__multiply> + 8015b9a: 6020 str r0, [r4, #0] + 8015b9c: f8c0 9000 str.w r9, [r0] + 8015ba0: 4604 mov r4, r0 + 8015ba2: e7e4 b.n 8015b6e <__pow5mult+0x6a> + 8015ba4: 4630 mov r0, r6 + 8015ba6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8015baa: bf00 nop + 8015bac: 08016df0 .word 0x08016df0 + 8015bb0: 08016c58 .word 0x08016c58 + 8015bb4: 08016d8a .word 0x08016d8a + +08015bb8 <__lshift>: + 8015bb8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8015bbc: 460c mov r4, r1 + 8015bbe: 4607 mov r7, r0 + 8015bc0: 4691 mov r9, r2 + 8015bc2: 6923 ldr r3, [r4, #16] + 8015bc4: 6849 ldr r1, [r1, #4] + 8015bc6: eb03 1862 add.w r8, r3, r2, asr #5 + 8015bca: 68a3 ldr r3, [r4, #8] + 8015bcc: ea4f 1a62 mov.w sl, r2, asr #5 + 8015bd0: f108 0601 add.w r6, r8, #1 + 8015bd4: 42b3 cmp r3, r6 + 8015bd6: db0b blt.n 8015bf0 <__lshift+0x38> + 8015bd8: 4638 mov r0, r7 + 8015bda: f7ff fde7 bl 80157ac <_Balloc> + 8015bde: 4605 mov r5, r0 + 8015be0: b948 cbnz r0, 8015bf6 <__lshift+0x3e> + 8015be2: 4602 mov r2, r0 + 8015be4: f44f 71ef mov.w r1, #478 @ 0x1de + 8015be8: 4b27 ldr r3, [pc, #156] @ (8015c88 <__lshift+0xd0>) + 8015bea: 4828 ldr r0, [pc, #160] @ (8015c8c <__lshift+0xd4>) + 8015bec: f7fe fb6c bl 80142c8 <__assert_func> + 8015bf0: 3101 adds r1, #1 + 8015bf2: 005b lsls r3, r3, #1 + 8015bf4: e7ee b.n 8015bd4 <__lshift+0x1c> + 8015bf6: 2300 movs r3, #0 + 8015bf8: f100 0114 add.w r1, r0, #20 + 8015bfc: f100 0210 add.w r2, r0, #16 + 8015c00: 4618 mov r0, r3 + 8015c02: 4553 cmp r3, sl + 8015c04: db33 blt.n 8015c6e <__lshift+0xb6> + 8015c06: 6920 ldr r0, [r4, #16] + 8015c08: ea2a 7aea bic.w sl, sl, sl, asr #31 + 8015c0c: f104 0314 add.w r3, r4, #20 + 8015c10: f019 091f ands.w r9, r9, #31 + 8015c14: eb01 018a add.w r1, r1, sl, lsl #2 + 8015c18: eb03 0c80 add.w ip, r3, r0, lsl #2 + 8015c1c: d02b beq.n 8015c76 <__lshift+0xbe> + 8015c1e: 468a mov sl, r1 + 8015c20: 2200 movs r2, #0 + 8015c22: f1c9 0e20 rsb lr, r9, #32 + 8015c26: 6818 ldr r0, [r3, #0] + 8015c28: fa00 f009 lsl.w r0, r0, r9 + 8015c2c: 4310 orrs r0, r2 + 8015c2e: f84a 0b04 str.w r0, [sl], #4 + 8015c32: f853 2b04 ldr.w r2, [r3], #4 + 8015c36: 459c cmp ip, r3 + 8015c38: fa22 f20e lsr.w r2, r2, lr + 8015c3c: d8f3 bhi.n 8015c26 <__lshift+0x6e> + 8015c3e: ebac 0304 sub.w r3, ip, r4 + 8015c42: 3b15 subs r3, #21 + 8015c44: f023 0303 bic.w r3, r3, #3 + 8015c48: 3304 adds r3, #4 + 8015c4a: f104 0015 add.w r0, r4, #21 + 8015c4e: 4560 cmp r0, ip + 8015c50: bf88 it hi + 8015c52: 2304 movhi r3, #4 + 8015c54: 50ca str r2, [r1, r3] + 8015c56: b10a cbz r2, 8015c5c <__lshift+0xa4> + 8015c58: f108 0602 add.w r6, r8, #2 + 8015c5c: 3e01 subs r6, #1 + 8015c5e: 4638 mov r0, r7 + 8015c60: 4621 mov r1, r4 + 8015c62: 612e str r6, [r5, #16] + 8015c64: f7ff fde2 bl 801582c <_Bfree> + 8015c68: 4628 mov r0, r5 + 8015c6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8015c6e: f842 0f04 str.w r0, [r2, #4]! + 8015c72: 3301 adds r3, #1 + 8015c74: e7c5 b.n 8015c02 <__lshift+0x4a> + 8015c76: 3904 subs r1, #4 + 8015c78: f853 2b04 ldr.w r2, [r3], #4 + 8015c7c: 459c cmp ip, r3 + 8015c7e: f841 2f04 str.w r2, [r1, #4]! + 8015c82: d8f9 bhi.n 8015c78 <__lshift+0xc0> + 8015c84: e7ea b.n 8015c5c <__lshift+0xa4> + 8015c86: bf00 nop + 8015c88: 08016d68 .word 0x08016d68 + 8015c8c: 08016d8a .word 0x08016d8a + +08015c90 <__mcmp>: + 8015c90: 4603 mov r3, r0 + 8015c92: 690a ldr r2, [r1, #16] + 8015c94: 6900 ldr r0, [r0, #16] + 8015c96: b530 push {r4, r5, lr} + 8015c98: 1a80 subs r0, r0, r2 + 8015c9a: d10e bne.n 8015cba <__mcmp+0x2a> + 8015c9c: 3314 adds r3, #20 + 8015c9e: 3114 adds r1, #20 + 8015ca0: eb03 0482 add.w r4, r3, r2, lsl #2 + 8015ca4: eb01 0182 add.w r1, r1, r2, lsl #2 + 8015ca8: f854 5d04 ldr.w r5, [r4, #-4]! + 8015cac: f851 2d04 ldr.w r2, [r1, #-4]! + 8015cb0: 4295 cmp r5, r2 + 8015cb2: d003 beq.n 8015cbc <__mcmp+0x2c> + 8015cb4: d205 bcs.n 8015cc2 <__mcmp+0x32> + 8015cb6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8015cba: bd30 pop {r4, r5, pc} + 8015cbc: 42a3 cmp r3, r4 + 8015cbe: d3f3 bcc.n 8015ca8 <__mcmp+0x18> + 8015cc0: e7fb b.n 8015cba <__mcmp+0x2a> + 8015cc2: 2001 movs r0, #1 + 8015cc4: e7f9 b.n 8015cba <__mcmp+0x2a> + ... + +08015cc8 <__mdiff>: + 8015cc8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8015ccc: 4689 mov r9, r1 + 8015cce: 4606 mov r6, r0 + 8015cd0: 4611 mov r1, r2 + 8015cd2: 4648 mov r0, r9 + 8015cd4: 4614 mov r4, r2 + 8015cd6: f7ff ffdb bl 8015c90 <__mcmp> + 8015cda: 1e05 subs r5, r0, #0 + 8015cdc: d112 bne.n 8015d04 <__mdiff+0x3c> + 8015cde: 4629 mov r1, r5 + 8015ce0: 4630 mov r0, r6 + 8015ce2: f7ff fd63 bl 80157ac <_Balloc> + 8015ce6: 4602 mov r2, r0 + 8015ce8: b928 cbnz r0, 8015cf6 <__mdiff+0x2e> + 8015cea: f240 2137 movw r1, #567 @ 0x237 + 8015cee: 4b3e ldr r3, [pc, #248] @ (8015de8 <__mdiff+0x120>) + 8015cf0: 483e ldr r0, [pc, #248] @ (8015dec <__mdiff+0x124>) + 8015cf2: f7fe fae9 bl 80142c8 <__assert_func> + 8015cf6: 2301 movs r3, #1 + 8015cf8: e9c0 3504 strd r3, r5, [r0, #16] + 8015cfc: 4610 mov r0, r2 + 8015cfe: b003 add sp, #12 + 8015d00: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8015d04: bfbc itt lt + 8015d06: 464b movlt r3, r9 + 8015d08: 46a1 movlt r9, r4 + 8015d0a: 4630 mov r0, r6 + 8015d0c: f8d9 1004 ldr.w r1, [r9, #4] + 8015d10: bfba itte lt + 8015d12: 461c movlt r4, r3 + 8015d14: 2501 movlt r5, #1 + 8015d16: 2500 movge r5, #0 + 8015d18: f7ff fd48 bl 80157ac <_Balloc> + 8015d1c: 4602 mov r2, r0 + 8015d1e: b918 cbnz r0, 8015d28 <__mdiff+0x60> + 8015d20: f240 2145 movw r1, #581 @ 0x245 + 8015d24: 4b30 ldr r3, [pc, #192] @ (8015de8 <__mdiff+0x120>) + 8015d26: e7e3 b.n 8015cf0 <__mdiff+0x28> + 8015d28: f100 0b14 add.w fp, r0, #20 + 8015d2c: f8d9 7010 ldr.w r7, [r9, #16] + 8015d30: f109 0310 add.w r3, r9, #16 + 8015d34: 60c5 str r5, [r0, #12] + 8015d36: f04f 0c00 mov.w ip, #0 + 8015d3a: f109 0514 add.w r5, r9, #20 + 8015d3e: 46d9 mov r9, fp + 8015d40: 6926 ldr r6, [r4, #16] + 8015d42: f104 0e14 add.w lr, r4, #20 + 8015d46: eb05 0887 add.w r8, r5, r7, lsl #2 + 8015d4a: eb0e 0686 add.w r6, lr, r6, lsl #2 + 8015d4e: 9301 str r3, [sp, #4] + 8015d50: 9b01 ldr r3, [sp, #4] + 8015d52: f85e 0b04 ldr.w r0, [lr], #4 + 8015d56: f853 af04 ldr.w sl, [r3, #4]! + 8015d5a: b281 uxth r1, r0 + 8015d5c: 9301 str r3, [sp, #4] + 8015d5e: fa1f f38a uxth.w r3, sl + 8015d62: 1a5b subs r3, r3, r1 + 8015d64: 0c00 lsrs r0, r0, #16 + 8015d66: 4463 add r3, ip + 8015d68: ebc0 401a rsb r0, r0, sl, lsr #16 + 8015d6c: eb00 4023 add.w r0, r0, r3, asr #16 + 8015d70: b29b uxth r3, r3 + 8015d72: ea43 4300 orr.w r3, r3, r0, lsl #16 + 8015d76: 4576 cmp r6, lr + 8015d78: ea4f 4c20 mov.w ip, r0, asr #16 + 8015d7c: f849 3b04 str.w r3, [r9], #4 + 8015d80: d8e6 bhi.n 8015d50 <__mdiff+0x88> + 8015d82: 1b33 subs r3, r6, r4 + 8015d84: 3b15 subs r3, #21 + 8015d86: f023 0303 bic.w r3, r3, #3 + 8015d8a: 3415 adds r4, #21 + 8015d8c: 3304 adds r3, #4 + 8015d8e: 42a6 cmp r6, r4 + 8015d90: bf38 it cc + 8015d92: 2304 movcc r3, #4 + 8015d94: 441d add r5, r3 + 8015d96: 445b add r3, fp + 8015d98: 461e mov r6, r3 + 8015d9a: 462c mov r4, r5 + 8015d9c: 4544 cmp r4, r8 + 8015d9e: d30e bcc.n 8015dbe <__mdiff+0xf6> + 8015da0: f108 0103 add.w r1, r8, #3 + 8015da4: 1b49 subs r1, r1, r5 + 8015da6: f021 0103 bic.w r1, r1, #3 + 8015daa: 3d03 subs r5, #3 + 8015dac: 45a8 cmp r8, r5 + 8015dae: bf38 it cc + 8015db0: 2100 movcc r1, #0 + 8015db2: 440b add r3, r1 + 8015db4: f853 1d04 ldr.w r1, [r3, #-4]! + 8015db8: b199 cbz r1, 8015de2 <__mdiff+0x11a> + 8015dba: 6117 str r7, [r2, #16] + 8015dbc: e79e b.n 8015cfc <__mdiff+0x34> + 8015dbe: 46e6 mov lr, ip + 8015dc0: f854 1b04 ldr.w r1, [r4], #4 + 8015dc4: fa1f fc81 uxth.w ip, r1 + 8015dc8: 44f4 add ip, lr + 8015dca: 0c08 lsrs r0, r1, #16 + 8015dcc: 4471 add r1, lr + 8015dce: eb00 402c add.w r0, r0, ip, asr #16 + 8015dd2: b289 uxth r1, r1 + 8015dd4: ea41 4100 orr.w r1, r1, r0, lsl #16 + 8015dd8: ea4f 4c20 mov.w ip, r0, asr #16 + 8015ddc: f846 1b04 str.w r1, [r6], #4 + 8015de0: e7dc b.n 8015d9c <__mdiff+0xd4> + 8015de2: 3f01 subs r7, #1 + 8015de4: e7e6 b.n 8015db4 <__mdiff+0xec> + 8015de6: bf00 nop + 8015de8: 08016d68 .word 0x08016d68 + 8015dec: 08016d8a .word 0x08016d8a + +08015df0 <__d2b>: + 8015df0: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} + 8015df4: 2101 movs r1, #1 + 8015df6: 4690 mov r8, r2 + 8015df8: 4699 mov r9, r3 + 8015dfa: 9e08 ldr r6, [sp, #32] + 8015dfc: f7ff fcd6 bl 80157ac <_Balloc> + 8015e00: 4604 mov r4, r0 + 8015e02: b930 cbnz r0, 8015e12 <__d2b+0x22> + 8015e04: 4602 mov r2, r0 + 8015e06: f240 310f movw r1, #783 @ 0x30f + 8015e0a: 4b23 ldr r3, [pc, #140] @ (8015e98 <__d2b+0xa8>) + 8015e0c: 4823 ldr r0, [pc, #140] @ (8015e9c <__d2b+0xac>) + 8015e0e: f7fe fa5b bl 80142c8 <__assert_func> + 8015e12: f3c9 550a ubfx r5, r9, #20, #11 + 8015e16: f3c9 0313 ubfx r3, r9, #0, #20 + 8015e1a: b10d cbz r5, 8015e20 <__d2b+0x30> + 8015e1c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8015e20: 9301 str r3, [sp, #4] + 8015e22: f1b8 0300 subs.w r3, r8, #0 + 8015e26: d024 beq.n 8015e72 <__d2b+0x82> + 8015e28: 4668 mov r0, sp + 8015e2a: 9300 str r3, [sp, #0] + 8015e2c: f7ff fd85 bl 801593a <__lo0bits> + 8015e30: e9dd 1200 ldrd r1, r2, [sp] + 8015e34: b1d8 cbz r0, 8015e6e <__d2b+0x7e> + 8015e36: f1c0 0320 rsb r3, r0, #32 + 8015e3a: fa02 f303 lsl.w r3, r2, r3 + 8015e3e: 430b orrs r3, r1 + 8015e40: 40c2 lsrs r2, r0 + 8015e42: 6163 str r3, [r4, #20] + 8015e44: 9201 str r2, [sp, #4] + 8015e46: 9b01 ldr r3, [sp, #4] + 8015e48: 2b00 cmp r3, #0 + 8015e4a: bf0c ite eq + 8015e4c: 2201 moveq r2, #1 + 8015e4e: 2202 movne r2, #2 + 8015e50: 61a3 str r3, [r4, #24] + 8015e52: 6122 str r2, [r4, #16] + 8015e54: b1ad cbz r5, 8015e82 <__d2b+0x92> + 8015e56: f2a5 4533 subw r5, r5, #1075 @ 0x433 + 8015e5a: 4405 add r5, r0 + 8015e5c: 6035 str r5, [r6, #0] + 8015e5e: f1c0 0035 rsb r0, r0, #53 @ 0x35 + 8015e62: 9b09 ldr r3, [sp, #36] @ 0x24 + 8015e64: 6018 str r0, [r3, #0] + 8015e66: 4620 mov r0, r4 + 8015e68: b002 add sp, #8 + 8015e6a: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} + 8015e6e: 6161 str r1, [r4, #20] + 8015e70: e7e9 b.n 8015e46 <__d2b+0x56> + 8015e72: a801 add r0, sp, #4 + 8015e74: f7ff fd61 bl 801593a <__lo0bits> + 8015e78: 9b01 ldr r3, [sp, #4] + 8015e7a: 2201 movs r2, #1 + 8015e7c: 6163 str r3, [r4, #20] + 8015e7e: 3020 adds r0, #32 + 8015e80: e7e7 b.n 8015e52 <__d2b+0x62> + 8015e82: f2a0 4032 subw r0, r0, #1074 @ 0x432 + 8015e86: eb04 0382 add.w r3, r4, r2, lsl #2 + 8015e8a: 6030 str r0, [r6, #0] + 8015e8c: 6918 ldr r0, [r3, #16] + 8015e8e: f7ff fd35 bl 80158fc <__hi0bits> + 8015e92: ebc0 1042 rsb r0, r0, r2, lsl #5 + 8015e96: e7e4 b.n 8015e62 <__d2b+0x72> + 8015e98: 08016d68 .word 0x08016d68 + 8015e9c: 08016d8a .word 0x08016d8a + +08015ea0 <__sread>: + 8015ea0: b510 push {r4, lr} + 8015ea2: 460c mov r4, r1 + 8015ea4: f9b1 100e ldrsh.w r1, [r1, #14] + 8015ea8: f000 f9b0 bl 801620c <_read_r> + 8015eac: 2800 cmp r0, #0 + 8015eae: bfab itete ge + 8015eb0: 6d63 ldrge r3, [r4, #84] @ 0x54 + 8015eb2: 89a3 ldrhlt r3, [r4, #12] + 8015eb4: 181b addge r3, r3, r0 + 8015eb6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 + 8015eba: bfac ite ge + 8015ebc: 6563 strge r3, [r4, #84] @ 0x54 + 8015ebe: 81a3 strhlt r3, [r4, #12] + 8015ec0: bd10 pop {r4, pc} + +08015ec2 <__swrite>: + 8015ec2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8015ec6: 461f mov r7, r3 + 8015ec8: 898b ldrh r3, [r1, #12] + 8015eca: 4605 mov r5, r0 + 8015ecc: 05db lsls r3, r3, #23 + 8015ece: 460c mov r4, r1 + 8015ed0: 4616 mov r6, r2 + 8015ed2: d505 bpl.n 8015ee0 <__swrite+0x1e> + 8015ed4: 2302 movs r3, #2 + 8015ed6: 2200 movs r2, #0 + 8015ed8: f9b1 100e ldrsh.w r1, [r1, #14] + 8015edc: f000 f984 bl 80161e8 <_lseek_r> + 8015ee0: 89a3 ldrh r3, [r4, #12] + 8015ee2: 4632 mov r2, r6 + 8015ee4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 + 8015ee8: 81a3 strh r3, [r4, #12] + 8015eea: 4628 mov r0, r5 + 8015eec: 463b mov r3, r7 + 8015eee: f9b4 100e ldrsh.w r1, [r4, #14] + 8015ef2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8015ef6: f000 b9ab b.w 8016250 <_write_r> + +08015efa <__sseek>: + 8015efa: b510 push {r4, lr} + 8015efc: 460c mov r4, r1 + 8015efe: f9b1 100e ldrsh.w r1, [r1, #14] + 8015f02: f000 f971 bl 80161e8 <_lseek_r> + 8015f06: 1c43 adds r3, r0, #1 + 8015f08: 89a3 ldrh r3, [r4, #12] + 8015f0a: bf15 itete ne + 8015f0c: 6560 strne r0, [r4, #84] @ 0x54 + 8015f0e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 + 8015f12: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 + 8015f16: 81a3 strheq r3, [r4, #12] + 8015f18: bf18 it ne + 8015f1a: 81a3 strhne r3, [r4, #12] + 8015f1c: bd10 pop {r4, pc} + +08015f1e <__sclose>: + 8015f1e: f9b1 100e ldrsh.w r1, [r1, #14] + 8015f22: f000 b9a7 b.w 8016274 <_close_r> + ... + +08015f28 : + 8015f28: b40e push {r1, r2, r3} + 8015f2a: b503 push {r0, r1, lr} + 8015f2c: 4601 mov r1, r0 + 8015f2e: ab03 add r3, sp, #12 + 8015f30: 4805 ldr r0, [pc, #20] @ (8015f48 ) + 8015f32: f853 2b04 ldr.w r2, [r3], #4 + 8015f36: 6800 ldr r0, [r0, #0] + 8015f38: 9301 str r3, [sp, #4] + 8015f3a: f7ff f9c1 bl 80152c0 <_vfiprintf_r> + 8015f3e: b002 add sp, #8 + 8015f40: f85d eb04 ldr.w lr, [sp], #4 + 8015f44: b003 add sp, #12 + 8015f46: 4770 bx lr + 8015f48: 20000084 .word 0x20000084 + +08015f4c <_realloc_r>: + 8015f4c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8015f50: 4607 mov r7, r0 + 8015f52: 4614 mov r4, r2 + 8015f54: 460d mov r5, r1 + 8015f56: b921 cbnz r1, 8015f62 <_realloc_r+0x16> + 8015f58: 4611 mov r1, r2 + 8015f5a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8015f5e: f7ff baf1 b.w 8015544 <_malloc_r> + 8015f62: b92a cbnz r2, 8015f70 <_realloc_r+0x24> + 8015f64: f000 f9c4 bl 80162f0 <_free_r> + 8015f68: 4625 mov r5, r4 + 8015f6a: 4628 mov r0, r5 + 8015f6c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8015f70: f000 fa18 bl 80163a4 <_malloc_usable_size_r> + 8015f74: 4284 cmp r4, r0 + 8015f76: 4606 mov r6, r0 + 8015f78: d802 bhi.n 8015f80 <_realloc_r+0x34> + 8015f7a: ebb4 0f50 cmp.w r4, r0, lsr #1 + 8015f7e: d8f4 bhi.n 8015f6a <_realloc_r+0x1e> + 8015f80: 4621 mov r1, r4 + 8015f82: 4638 mov r0, r7 + 8015f84: f7ff fade bl 8015544 <_malloc_r> + 8015f88: 4680 mov r8, r0 + 8015f8a: b908 cbnz r0, 8015f90 <_realloc_r+0x44> + 8015f8c: 4645 mov r5, r8 + 8015f8e: e7ec b.n 8015f6a <_realloc_r+0x1e> + 8015f90: 42b4 cmp r4, r6 + 8015f92: 4622 mov r2, r4 + 8015f94: 4629 mov r1, r5 + 8015f96: bf28 it cs + 8015f98: 4632 movcs r2, r6 + 8015f9a: f7fe f987 bl 80142ac + 8015f9e: 4629 mov r1, r5 + 8015fa0: 4638 mov r0, r7 + 8015fa2: f000 f9a5 bl 80162f0 <_free_r> + 8015fa6: e7f1 b.n 8015f8c <_realloc_r+0x40> + +08015fa8 <__swbuf_r>: + 8015fa8: b5f8 push {r3, r4, r5, r6, r7, lr} + 8015faa: 460e mov r6, r1 + 8015fac: 4614 mov r4, r2 + 8015fae: 4605 mov r5, r0 + 8015fb0: b118 cbz r0, 8015fba <__swbuf_r+0x12> + 8015fb2: 6a03 ldr r3, [r0, #32] + 8015fb4: b90b cbnz r3, 8015fba <__swbuf_r+0x12> + 8015fb6: f7fd ffe7 bl 8013f88 <__sinit> + 8015fba: 69a3 ldr r3, [r4, #24] + 8015fbc: 60a3 str r3, [r4, #8] + 8015fbe: 89a3 ldrh r3, [r4, #12] + 8015fc0: 071a lsls r2, r3, #28 + 8015fc2: d501 bpl.n 8015fc8 <__swbuf_r+0x20> + 8015fc4: 6923 ldr r3, [r4, #16] + 8015fc6: b943 cbnz r3, 8015fda <__swbuf_r+0x32> + 8015fc8: 4621 mov r1, r4 + 8015fca: 4628 mov r0, r5 + 8015fcc: f000 f82a bl 8016024 <__swsetup_r> + 8015fd0: b118 cbz r0, 8015fda <__swbuf_r+0x32> + 8015fd2: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff + 8015fd6: 4638 mov r0, r7 + 8015fd8: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8015fda: 6823 ldr r3, [r4, #0] + 8015fdc: 6922 ldr r2, [r4, #16] + 8015fde: b2f6 uxtb r6, r6 + 8015fe0: 1a98 subs r0, r3, r2 + 8015fe2: 6963 ldr r3, [r4, #20] + 8015fe4: 4637 mov r7, r6 + 8015fe6: 4283 cmp r3, r0 + 8015fe8: dc05 bgt.n 8015ff6 <__swbuf_r+0x4e> + 8015fea: 4621 mov r1, r4 + 8015fec: 4628 mov r0, r5 + 8015fee: f7ff fba9 bl 8015744 <_fflush_r> + 8015ff2: 2800 cmp r0, #0 + 8015ff4: d1ed bne.n 8015fd2 <__swbuf_r+0x2a> + 8015ff6: 68a3 ldr r3, [r4, #8] + 8015ff8: 3b01 subs r3, #1 + 8015ffa: 60a3 str r3, [r4, #8] + 8015ffc: 6823 ldr r3, [r4, #0] + 8015ffe: 1c5a adds r2, r3, #1 + 8016000: 6022 str r2, [r4, #0] + 8016002: 701e strb r6, [r3, #0] + 8016004: 6962 ldr r2, [r4, #20] + 8016006: 1c43 adds r3, r0, #1 + 8016008: 429a cmp r2, r3 + 801600a: d004 beq.n 8016016 <__swbuf_r+0x6e> + 801600c: 89a3 ldrh r3, [r4, #12] + 801600e: 07db lsls r3, r3, #31 + 8016010: d5e1 bpl.n 8015fd6 <__swbuf_r+0x2e> + 8016012: 2e0a cmp r6, #10 + 8016014: d1df bne.n 8015fd6 <__swbuf_r+0x2e> + 8016016: 4621 mov r1, r4 + 8016018: 4628 mov r0, r5 + 801601a: f7ff fb93 bl 8015744 <_fflush_r> + 801601e: 2800 cmp r0, #0 + 8016020: d0d9 beq.n 8015fd6 <__swbuf_r+0x2e> + 8016022: e7d6 b.n 8015fd2 <__swbuf_r+0x2a> + +08016024 <__swsetup_r>: + 8016024: b538 push {r3, r4, r5, lr} + 8016026: 4b29 ldr r3, [pc, #164] @ (80160cc <__swsetup_r+0xa8>) + 8016028: 4605 mov r5, r0 + 801602a: 6818 ldr r0, [r3, #0] + 801602c: 460c mov r4, r1 + 801602e: b118 cbz r0, 8016038 <__swsetup_r+0x14> + 8016030: 6a03 ldr r3, [r0, #32] + 8016032: b90b cbnz r3, 8016038 <__swsetup_r+0x14> + 8016034: f7fd ffa8 bl 8013f88 <__sinit> + 8016038: f9b4 300c ldrsh.w r3, [r4, #12] + 801603c: 0719 lsls r1, r3, #28 + 801603e: d422 bmi.n 8016086 <__swsetup_r+0x62> + 8016040: 06da lsls r2, r3, #27 + 8016042: d407 bmi.n 8016054 <__swsetup_r+0x30> + 8016044: 2209 movs r2, #9 + 8016046: 602a str r2, [r5, #0] + 8016048: f043 0340 orr.w r3, r3, #64 @ 0x40 + 801604c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8016050: 81a3 strh r3, [r4, #12] + 8016052: e033 b.n 80160bc <__swsetup_r+0x98> + 8016054: 0758 lsls r0, r3, #29 + 8016056: d512 bpl.n 801607e <__swsetup_r+0x5a> + 8016058: 6b61 ldr r1, [r4, #52] @ 0x34 + 801605a: b141 cbz r1, 801606e <__swsetup_r+0x4a> + 801605c: f104 0344 add.w r3, r4, #68 @ 0x44 + 8016060: 4299 cmp r1, r3 + 8016062: d002 beq.n 801606a <__swsetup_r+0x46> + 8016064: 4628 mov r0, r5 + 8016066: f000 f943 bl 80162f0 <_free_r> + 801606a: 2300 movs r3, #0 + 801606c: 6363 str r3, [r4, #52] @ 0x34 + 801606e: 89a3 ldrh r3, [r4, #12] + 8016070: f023 0324 bic.w r3, r3, #36 @ 0x24 + 8016074: 81a3 strh r3, [r4, #12] + 8016076: 2300 movs r3, #0 + 8016078: 6063 str r3, [r4, #4] + 801607a: 6923 ldr r3, [r4, #16] + 801607c: 6023 str r3, [r4, #0] + 801607e: 89a3 ldrh r3, [r4, #12] + 8016080: f043 0308 orr.w r3, r3, #8 + 8016084: 81a3 strh r3, [r4, #12] + 8016086: 6923 ldr r3, [r4, #16] + 8016088: b94b cbnz r3, 801609e <__swsetup_r+0x7a> + 801608a: 89a3 ldrh r3, [r4, #12] + 801608c: f403 7320 and.w r3, r3, #640 @ 0x280 + 8016090: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8016094: d003 beq.n 801609e <__swsetup_r+0x7a> + 8016096: 4621 mov r1, r4 + 8016098: 4628 mov r0, r5 + 801609a: f000 f83e bl 801611a <__smakebuf_r> + 801609e: f9b4 300c ldrsh.w r3, [r4, #12] + 80160a2: f013 0201 ands.w r2, r3, #1 + 80160a6: d00a beq.n 80160be <__swsetup_r+0x9a> + 80160a8: 2200 movs r2, #0 + 80160aa: 60a2 str r2, [r4, #8] + 80160ac: 6962 ldr r2, [r4, #20] + 80160ae: 4252 negs r2, r2 + 80160b0: 61a2 str r2, [r4, #24] + 80160b2: 6922 ldr r2, [r4, #16] + 80160b4: b942 cbnz r2, 80160c8 <__swsetup_r+0xa4> + 80160b6: f013 0080 ands.w r0, r3, #128 @ 0x80 + 80160ba: d1c5 bne.n 8016048 <__swsetup_r+0x24> + 80160bc: bd38 pop {r3, r4, r5, pc} + 80160be: 0799 lsls r1, r3, #30 + 80160c0: bf58 it pl + 80160c2: 6962 ldrpl r2, [r4, #20] + 80160c4: 60a2 str r2, [r4, #8] + 80160c6: e7f4 b.n 80160b2 <__swsetup_r+0x8e> + 80160c8: 2000 movs r0, #0 + 80160ca: e7f7 b.n 80160bc <__swsetup_r+0x98> + 80160cc: 20000084 .word 0x20000084 + +080160d0 <__swhatbuf_r>: + 80160d0: b570 push {r4, r5, r6, lr} + 80160d2: 460c mov r4, r1 + 80160d4: f9b1 100e ldrsh.w r1, [r1, #14] + 80160d8: 4615 mov r5, r2 + 80160da: 2900 cmp r1, #0 + 80160dc: 461e mov r6, r3 + 80160de: b096 sub sp, #88 @ 0x58 + 80160e0: da0c bge.n 80160fc <__swhatbuf_r+0x2c> + 80160e2: 89a3 ldrh r3, [r4, #12] + 80160e4: 2100 movs r1, #0 + 80160e6: f013 0f80 tst.w r3, #128 @ 0x80 + 80160ea: bf14 ite ne + 80160ec: 2340 movne r3, #64 @ 0x40 + 80160ee: f44f 6380 moveq.w r3, #1024 @ 0x400 + 80160f2: 2000 movs r0, #0 + 80160f4: 6031 str r1, [r6, #0] + 80160f6: 602b str r3, [r5, #0] + 80160f8: b016 add sp, #88 @ 0x58 + 80160fa: bd70 pop {r4, r5, r6, pc} + 80160fc: 466a mov r2, sp + 80160fe: f000 f8c9 bl 8016294 <_fstat_r> + 8016102: 2800 cmp r0, #0 + 8016104: dbed blt.n 80160e2 <__swhatbuf_r+0x12> + 8016106: 9901 ldr r1, [sp, #4] + 8016108: f401 4170 and.w r1, r1, #61440 @ 0xf000 + 801610c: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 + 8016110: 4259 negs r1, r3 + 8016112: 4159 adcs r1, r3 + 8016114: f44f 6380 mov.w r3, #1024 @ 0x400 + 8016118: e7eb b.n 80160f2 <__swhatbuf_r+0x22> + +0801611a <__smakebuf_r>: + 801611a: 898b ldrh r3, [r1, #12] + 801611c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 801611e: 079d lsls r5, r3, #30 + 8016120: 4606 mov r6, r0 + 8016122: 460c mov r4, r1 + 8016124: d507 bpl.n 8016136 <__smakebuf_r+0x1c> + 8016126: f104 0347 add.w r3, r4, #71 @ 0x47 + 801612a: 6023 str r3, [r4, #0] + 801612c: 6123 str r3, [r4, #16] + 801612e: 2301 movs r3, #1 + 8016130: 6163 str r3, [r4, #20] + 8016132: b003 add sp, #12 + 8016134: bdf0 pop {r4, r5, r6, r7, pc} + 8016136: 466a mov r2, sp + 8016138: ab01 add r3, sp, #4 + 801613a: f7ff ffc9 bl 80160d0 <__swhatbuf_r> + 801613e: 9f00 ldr r7, [sp, #0] + 8016140: 4605 mov r5, r0 + 8016142: 4639 mov r1, r7 + 8016144: 4630 mov r0, r6 + 8016146: f7ff f9fd bl 8015544 <_malloc_r> + 801614a: b948 cbnz r0, 8016160 <__smakebuf_r+0x46> + 801614c: f9b4 300c ldrsh.w r3, [r4, #12] + 8016150: 059a lsls r2, r3, #22 + 8016152: d4ee bmi.n 8016132 <__smakebuf_r+0x18> + 8016154: f023 0303 bic.w r3, r3, #3 + 8016158: f043 0302 orr.w r3, r3, #2 + 801615c: 81a3 strh r3, [r4, #12] + 801615e: e7e2 b.n 8016126 <__smakebuf_r+0xc> + 8016160: 89a3 ldrh r3, [r4, #12] + 8016162: e9c4 0704 strd r0, r7, [r4, #16] + 8016166: f043 0380 orr.w r3, r3, #128 @ 0x80 + 801616a: 81a3 strh r3, [r4, #12] + 801616c: 9b01 ldr r3, [sp, #4] + 801616e: 6020 str r0, [r4, #0] + 8016170: b15b cbz r3, 801618a <__smakebuf_r+0x70> + 8016172: 4630 mov r0, r6 + 8016174: f9b4 100e ldrsh.w r1, [r4, #14] + 8016178: f000 f826 bl 80161c8 <_isatty_r> + 801617c: b128 cbz r0, 801618a <__smakebuf_r+0x70> + 801617e: 89a3 ldrh r3, [r4, #12] + 8016180: f023 0303 bic.w r3, r3, #3 + 8016184: f043 0301 orr.w r3, r3, #1 + 8016188: 81a3 strh r3, [r4, #12] + 801618a: 89a3 ldrh r3, [r4, #12] + 801618c: 431d orrs r5, r3 + 801618e: 81a5 strh r5, [r4, #12] + 8016190: e7cf b.n 8016132 <__smakebuf_r+0x18> + +08016192 : + 8016192: 4288 cmp r0, r1 + 8016194: b510 push {r4, lr} + 8016196: eb01 0402 add.w r4, r1, r2 + 801619a: d902 bls.n 80161a2 + 801619c: 4284 cmp r4, r0 + 801619e: 4623 mov r3, r4 + 80161a0: d807 bhi.n 80161b2 + 80161a2: 1e43 subs r3, r0, #1 + 80161a4: 42a1 cmp r1, r4 + 80161a6: d008 beq.n 80161ba + 80161a8: f811 2b01 ldrb.w r2, [r1], #1 + 80161ac: f803 2f01 strb.w r2, [r3, #1]! + 80161b0: e7f8 b.n 80161a4 + 80161b2: 4601 mov r1, r0 + 80161b4: 4402 add r2, r0 + 80161b6: 428a cmp r2, r1 + 80161b8: d100 bne.n 80161bc + 80161ba: bd10 pop {r4, pc} + 80161bc: f813 4d01 ldrb.w r4, [r3, #-1]! + 80161c0: f802 4d01 strb.w r4, [r2, #-1]! + 80161c4: e7f7 b.n 80161b6 + ... + +080161c8 <_isatty_r>: + 80161c8: b538 push {r3, r4, r5, lr} + 80161ca: 2300 movs r3, #0 + 80161cc: 4d05 ldr r5, [pc, #20] @ (80161e4 <_isatty_r+0x1c>) + 80161ce: 4604 mov r4, r0 + 80161d0: 4608 mov r0, r1 + 80161d2: 602b str r3, [r5, #0] + 80161d4: f7f7 ff4f bl 800e076 <_isatty> + 80161d8: 1c43 adds r3, r0, #1 + 80161da: d102 bne.n 80161e2 <_isatty_r+0x1a> + 80161dc: 682b ldr r3, [r5, #0] + 80161de: b103 cbz r3, 80161e2 <_isatty_r+0x1a> + 80161e0: 6023 str r3, [r4, #0] + 80161e2: bd38 pop {r3, r4, r5, pc} + 80161e4: 20000fac .word 0x20000fac + +080161e8 <_lseek_r>: + 80161e8: b538 push {r3, r4, r5, lr} + 80161ea: 4604 mov r4, r0 + 80161ec: 4608 mov r0, r1 + 80161ee: 4611 mov r1, r2 + 80161f0: 2200 movs r2, #0 + 80161f2: 4d05 ldr r5, [pc, #20] @ (8016208 <_lseek_r+0x20>) + 80161f4: 602a str r2, [r5, #0] + 80161f6: 461a mov r2, r3 + 80161f8: f7f7 ff47 bl 800e08a <_lseek> + 80161fc: 1c43 adds r3, r0, #1 + 80161fe: d102 bne.n 8016206 <_lseek_r+0x1e> + 8016200: 682b ldr r3, [r5, #0] + 8016202: b103 cbz r3, 8016206 <_lseek_r+0x1e> + 8016204: 6023 str r3, [r4, #0] + 8016206: bd38 pop {r3, r4, r5, pc} + 8016208: 20000fac .word 0x20000fac + +0801620c <_read_r>: + 801620c: b538 push {r3, r4, r5, lr} + 801620e: 4604 mov r4, r0 + 8016210: 4608 mov r0, r1 + 8016212: 4611 mov r1, r2 + 8016214: 2200 movs r2, #0 + 8016216: 4d05 ldr r5, [pc, #20] @ (801622c <_read_r+0x20>) + 8016218: 602a str r2, [r5, #0] + 801621a: 461a mov r2, r3 + 801621c: f7f7 fef4 bl 800e008 <_read> + 8016220: 1c43 adds r3, r0, #1 + 8016222: d102 bne.n 801622a <_read_r+0x1e> + 8016224: 682b ldr r3, [r5, #0] + 8016226: b103 cbz r3, 801622a <_read_r+0x1e> + 8016228: 6023 str r3, [r4, #0] + 801622a: bd38 pop {r3, r4, r5, pc} + 801622c: 20000fac .word 0x20000fac + +08016230 <_sbrk_r>: + 8016230: b538 push {r3, r4, r5, lr} + 8016232: 2300 movs r3, #0 + 8016234: 4d05 ldr r5, [pc, #20] @ (801624c <_sbrk_r+0x1c>) + 8016236: 4604 mov r4, r0 + 8016238: 4608 mov r0, r1 + 801623a: 602b str r3, [r5, #0] + 801623c: f7f7 ff32 bl 800e0a4 <_sbrk> + 8016240: 1c43 adds r3, r0, #1 + 8016242: d102 bne.n 801624a <_sbrk_r+0x1a> + 8016244: 682b ldr r3, [r5, #0] + 8016246: b103 cbz r3, 801624a <_sbrk_r+0x1a> + 8016248: 6023 str r3, [r4, #0] + 801624a: bd38 pop {r3, r4, r5, pc} + 801624c: 20000fac .word 0x20000fac + +08016250 <_write_r>: + 8016250: b538 push {r3, r4, r5, lr} + 8016252: 4604 mov r4, r0 + 8016254: 4608 mov r0, r1 + 8016256: 4611 mov r1, r2 + 8016258: 2200 movs r2, #0 + 801625a: 4d05 ldr r5, [pc, #20] @ (8016270 <_write_r+0x20>) + 801625c: 602a str r2, [r5, #0] + 801625e: 461a mov r2, r3 + 8016260: f7f5 f81a bl 800b298 <_write> + 8016264: 1c43 adds r3, r0, #1 + 8016266: d102 bne.n 801626e <_write_r+0x1e> + 8016268: 682b ldr r3, [r5, #0] + 801626a: b103 cbz r3, 801626e <_write_r+0x1e> + 801626c: 6023 str r3, [r4, #0] + 801626e: bd38 pop {r3, r4, r5, pc} + 8016270: 20000fac .word 0x20000fac + +08016274 <_close_r>: + 8016274: b538 push {r3, r4, r5, lr} + 8016276: 2300 movs r3, #0 + 8016278: 4d05 ldr r5, [pc, #20] @ (8016290 <_close_r+0x1c>) + 801627a: 4604 mov r4, r0 + 801627c: 4608 mov r0, r1 + 801627e: 602b str r3, [r5, #0] + 8016280: f7f7 fedf bl 800e042 <_close> + 8016284: 1c43 adds r3, r0, #1 + 8016286: d102 bne.n 801628e <_close_r+0x1a> + 8016288: 682b ldr r3, [r5, #0] + 801628a: b103 cbz r3, 801628e <_close_r+0x1a> + 801628c: 6023 str r3, [r4, #0] + 801628e: bd38 pop {r3, r4, r5, pc} + 8016290: 20000fac .word 0x20000fac + +08016294 <_fstat_r>: + 8016294: b538 push {r3, r4, r5, lr} + 8016296: 2300 movs r3, #0 + 8016298: 4d06 ldr r5, [pc, #24] @ (80162b4 <_fstat_r+0x20>) + 801629a: 4604 mov r4, r0 + 801629c: 4608 mov r0, r1 + 801629e: 4611 mov r1, r2 + 80162a0: 602b str r3, [r5, #0] + 80162a2: f7f7 fed9 bl 800e058 <_fstat> + 80162a6: 1c43 adds r3, r0, #1 + 80162a8: d102 bne.n 80162b0 <_fstat_r+0x1c> + 80162aa: 682b ldr r3, [r5, #0] + 80162ac: b103 cbz r3, 80162b0 <_fstat_r+0x1c> + 80162ae: 6023 str r3, [r4, #0] + 80162b0: bd38 pop {r3, r4, r5, pc} + 80162b2: bf00 nop + 80162b4: 20000fac .word 0x20000fac + +080162b8 : + 80162b8: 2006 movs r0, #6 + 80162ba: b508 push {r3, lr} + 80162bc: f000 f8b0 bl 8016420 + 80162c0: 2001 movs r0, #1 + 80162c2: f7f7 fe96 bl 800dff2 <_exit> + +080162c6 <_calloc_r>: + 80162c6: b570 push {r4, r5, r6, lr} + 80162c8: fba1 5402 umull r5, r4, r1, r2 + 80162cc: b934 cbnz r4, 80162dc <_calloc_r+0x16> + 80162ce: 4629 mov r1, r5 + 80162d0: f7ff f938 bl 8015544 <_malloc_r> + 80162d4: 4606 mov r6, r0 + 80162d6: b928 cbnz r0, 80162e4 <_calloc_r+0x1e> + 80162d8: 4630 mov r0, r6 + 80162da: bd70 pop {r4, r5, r6, pc} + 80162dc: 220c movs r2, #12 + 80162de: 2600 movs r6, #0 + 80162e0: 6002 str r2, [r0, #0] + 80162e2: e7f9 b.n 80162d8 <_calloc_r+0x12> + 80162e4: 462a mov r2, r5 + 80162e6: 4621 mov r1, r4 + 80162e8: f7fd fed2 bl 8014090 + 80162ec: e7f4 b.n 80162d8 <_calloc_r+0x12> + ... + +080162f0 <_free_r>: + 80162f0: b538 push {r3, r4, r5, lr} + 80162f2: 4605 mov r5, r0 + 80162f4: 2900 cmp r1, #0 + 80162f6: d040 beq.n 801637a <_free_r+0x8a> + 80162f8: f851 3c04 ldr.w r3, [r1, #-4] + 80162fc: 1f0c subs r4, r1, #4 + 80162fe: 2b00 cmp r3, #0 + 8016300: bfb8 it lt + 8016302: 18e4 addlt r4, r4, r3 + 8016304: f7ff fa46 bl 8015794 <__malloc_lock> + 8016308: 4a1c ldr r2, [pc, #112] @ (801637c <_free_r+0x8c>) + 801630a: 6813 ldr r3, [r2, #0] + 801630c: b933 cbnz r3, 801631c <_free_r+0x2c> + 801630e: 6063 str r3, [r4, #4] + 8016310: 6014 str r4, [r2, #0] + 8016312: 4628 mov r0, r5 + 8016314: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8016318: f7ff ba42 b.w 80157a0 <__malloc_unlock> + 801631c: 42a3 cmp r3, r4 + 801631e: d908 bls.n 8016332 <_free_r+0x42> + 8016320: 6820 ldr r0, [r4, #0] + 8016322: 1821 adds r1, r4, r0 + 8016324: 428b cmp r3, r1 + 8016326: bf01 itttt eq + 8016328: 6819 ldreq r1, [r3, #0] + 801632a: 685b ldreq r3, [r3, #4] + 801632c: 1809 addeq r1, r1, r0 + 801632e: 6021 streq r1, [r4, #0] + 8016330: e7ed b.n 801630e <_free_r+0x1e> + 8016332: 461a mov r2, r3 + 8016334: 685b ldr r3, [r3, #4] + 8016336: b10b cbz r3, 801633c <_free_r+0x4c> + 8016338: 42a3 cmp r3, r4 + 801633a: d9fa bls.n 8016332 <_free_r+0x42> + 801633c: 6811 ldr r1, [r2, #0] + 801633e: 1850 adds r0, r2, r1 + 8016340: 42a0 cmp r0, r4 + 8016342: d10b bne.n 801635c <_free_r+0x6c> + 8016344: 6820 ldr r0, [r4, #0] + 8016346: 4401 add r1, r0 + 8016348: 1850 adds r0, r2, r1 + 801634a: 4283 cmp r3, r0 + 801634c: 6011 str r1, [r2, #0] + 801634e: d1e0 bne.n 8016312 <_free_r+0x22> + 8016350: 6818 ldr r0, [r3, #0] + 8016352: 685b ldr r3, [r3, #4] + 8016354: 4408 add r0, r1 + 8016356: 6010 str r0, [r2, #0] + 8016358: 6053 str r3, [r2, #4] + 801635a: e7da b.n 8016312 <_free_r+0x22> + 801635c: d902 bls.n 8016364 <_free_r+0x74> + 801635e: 230c movs r3, #12 + 8016360: 602b str r3, [r5, #0] + 8016362: e7d6 b.n 8016312 <_free_r+0x22> + 8016364: 6820 ldr r0, [r4, #0] + 8016366: 1821 adds r1, r4, r0 + 8016368: 428b cmp r3, r1 + 801636a: bf01 itttt eq + 801636c: 6819 ldreq r1, [r3, #0] + 801636e: 685b ldreq r3, [r3, #4] + 8016370: 1809 addeq r1, r1, r0 + 8016372: 6021 streq r1, [r4, #0] + 8016374: 6063 str r3, [r4, #4] + 8016376: 6054 str r4, [r2, #4] + 8016378: e7cb b.n 8016312 <_free_r+0x22> + 801637a: bd38 pop {r3, r4, r5, pc} + 801637c: 20000fa8 .word 0x20000fa8 + +08016380 <__ascii_mbtowc>: + 8016380: b082 sub sp, #8 + 8016382: b901 cbnz r1, 8016386 <__ascii_mbtowc+0x6> + 8016384: a901 add r1, sp, #4 + 8016386: b142 cbz r2, 801639a <__ascii_mbtowc+0x1a> + 8016388: b14b cbz r3, 801639e <__ascii_mbtowc+0x1e> + 801638a: 7813 ldrb r3, [r2, #0] + 801638c: 600b str r3, [r1, #0] + 801638e: 7812 ldrb r2, [r2, #0] + 8016390: 1e10 subs r0, r2, #0 + 8016392: bf18 it ne + 8016394: 2001 movne r0, #1 + 8016396: b002 add sp, #8 + 8016398: 4770 bx lr + 801639a: 4610 mov r0, r2 + 801639c: e7fb b.n 8016396 <__ascii_mbtowc+0x16> + 801639e: f06f 0001 mvn.w r0, #1 + 80163a2: e7f8 b.n 8016396 <__ascii_mbtowc+0x16> + +080163a4 <_malloc_usable_size_r>: + 80163a4: f851 3c04 ldr.w r3, [r1, #-4] + 80163a8: 1f18 subs r0, r3, #4 + 80163aa: 2b00 cmp r3, #0 + 80163ac: bfbc itt lt + 80163ae: 580b ldrlt r3, [r1, r0] + 80163b0: 18c0 addlt r0, r0, r3 + 80163b2: 4770 bx lr + +080163b4 <__ascii_wctomb>: + 80163b4: 4603 mov r3, r0 + 80163b6: 4608 mov r0, r1 + 80163b8: b141 cbz r1, 80163cc <__ascii_wctomb+0x18> + 80163ba: 2aff cmp r2, #255 @ 0xff + 80163bc: d904 bls.n 80163c8 <__ascii_wctomb+0x14> + 80163be: 228a movs r2, #138 @ 0x8a + 80163c0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80163c4: 601a str r2, [r3, #0] + 80163c6: 4770 bx lr + 80163c8: 2001 movs r0, #1 + 80163ca: 700a strb r2, [r1, #0] + 80163cc: 4770 bx lr + +080163ce <_raise_r>: + 80163ce: 291f cmp r1, #31 + 80163d0: b538 push {r3, r4, r5, lr} + 80163d2: 4605 mov r5, r0 + 80163d4: 460c mov r4, r1 + 80163d6: d904 bls.n 80163e2 <_raise_r+0x14> + 80163d8: 2316 movs r3, #22 + 80163da: 6003 str r3, [r0, #0] + 80163dc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80163e0: bd38 pop {r3, r4, r5, pc} + 80163e2: 6bc2 ldr r2, [r0, #60] @ 0x3c + 80163e4: b112 cbz r2, 80163ec <_raise_r+0x1e> + 80163e6: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 80163ea: b94b cbnz r3, 8016400 <_raise_r+0x32> + 80163ec: 4628 mov r0, r5 + 80163ee: f000 f831 bl 8016454 <_getpid_r> + 80163f2: 4622 mov r2, r4 + 80163f4: 4601 mov r1, r0 + 80163f6: 4628 mov r0, r5 + 80163f8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 80163fc: f000 b818 b.w 8016430 <_kill_r> + 8016400: 2b01 cmp r3, #1 + 8016402: d00a beq.n 801641a <_raise_r+0x4c> + 8016404: 1c59 adds r1, r3, #1 + 8016406: d103 bne.n 8016410 <_raise_r+0x42> + 8016408: 2316 movs r3, #22 + 801640a: 6003 str r3, [r0, #0] + 801640c: 2001 movs r0, #1 + 801640e: e7e7 b.n 80163e0 <_raise_r+0x12> + 8016410: 2100 movs r1, #0 + 8016412: 4620 mov r0, r4 + 8016414: f842 1024 str.w r1, [r2, r4, lsl #2] + 8016418: 4798 blx r3 + 801641a: 2000 movs r0, #0 + 801641c: e7e0 b.n 80163e0 <_raise_r+0x12> + ... + +08016420 : + 8016420: 4b02 ldr r3, [pc, #8] @ (801642c ) + 8016422: 4601 mov r1, r0 + 8016424: 6818 ldr r0, [r3, #0] + 8016426: f7ff bfd2 b.w 80163ce <_raise_r> + 801642a: bf00 nop + 801642c: 20000084 .word 0x20000084 + +08016430 <_kill_r>: + 8016430: b538 push {r3, r4, r5, lr} + 8016432: 2300 movs r3, #0 + 8016434: 4d06 ldr r5, [pc, #24] @ (8016450 <_kill_r+0x20>) + 8016436: 4604 mov r4, r0 + 8016438: 4608 mov r0, r1 + 801643a: 4611 mov r1, r2 + 801643c: 602b str r3, [r5, #0] + 801643e: f7f7 fdc8 bl 800dfd2 <_kill> + 8016442: 1c43 adds r3, r0, #1 + 8016444: d102 bne.n 801644c <_kill_r+0x1c> + 8016446: 682b ldr r3, [r5, #0] + 8016448: b103 cbz r3, 801644c <_kill_r+0x1c> + 801644a: 6023 str r3, [r4, #0] + 801644c: bd38 pop {r3, r4, r5, pc} + 801644e: bf00 nop + 8016450: 20000fac .word 0x20000fac + +08016454 <_getpid_r>: + 8016454: f7f7 bdb6 b.w 800dfc4 <_getpid> + +08016458 <_init>: + 8016458: b5f8 push {r3, r4, r5, r6, r7, lr} + 801645a: bf00 nop + 801645c: bcf8 pop {r3, r4, r5, r6, r7} + 801645e: bc08 pop {r3} + 8016460: 469e mov lr, r3 + 8016462: 4770 bx lr + +08016464 <_fini>: + 8016464: b5f8 push {r3, r4, r5, r6, r7, lr} + 8016466: bf00 nop + 8016468: bcf8 pop {r3, r4, r5, r6, r7} + 801646a: bc08 pop {r3} + 801646c: 469e mov lr, r3 + 801646e: 4770 bx lr diff --git a/Debug/GbTModuleSW30Web.srec b/Debug/GbTModuleSW30Web.srec new file mode 100755 index 0000000..07b548c --- /dev/null +++ b/Debug/GbTModuleSW30Web.srec @@ -0,0 +1,3882 @@ +S01800004762544D6F64756C65535733305765622E737265637E +S3150800800000000120CDE60008F5DE0008FDDE0008C8 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+S3150801715400000000430000000000000000000000D9 +S31508017164000000000000000000000000000000000C +S3150801717400000000430000000000000000000000B9 +S3150801718400000000000000000000000000000000EC +S315080171940000000043000000000000000000000099 +S315080171A400000000000000000000000000000000CC +S315080171B400000000B56301088163010800000000AE +S315080171C4F06E0108EB6D0108026D0108026D0108F4 +S315080171D4026D0108026D0108026D0108026D0108BC +S315080171E4026D0108026D0108026D0108FFFFFFFF28 +S315080171F4FFFFFFFFFFFFFFFFFFFF000001004153F1 +S315080172044349490000000000000000000000000096 +S3150801721400000000000000000000000000004153C7 +S315080172244349490000000000000000000000000076 +S31508017234000000000000000000000000000000003B +S7050800E6CD3F diff --git a/Debug/objects.list b/Debug/objects.list index edbb201..adc90af 100755 --- a/Debug/objects.list +++ b/Debug/objects.list @@ -1,22 +1,29 @@ "./Core/Src/adc.o" "./Core/Src/board.o" "./Core/Src/can.o" +"./Core/Src/charger_control.o" "./Core/Src/charger_gbt.o" "./Core/Src/connector.o" +"./Core/Src/crc.o" "./Core/Src/debug.o" -"./Core/Src/edcan_handler_user.o" "./Core/Src/gbt_packet.o" "./Core/Src/gpio.o" "./Core/Src/j1939.o" "./Core/Src/lock.o" "./Core/Src/main.o" +"./Core/Src/meter.o" +"./Core/Src/psu_control.o" +"./Core/Src/rgb_controller.o" "./Core/Src/rtc.o" +"./Core/Src/serial_control.o" +"./Core/Src/serial_handler.o" "./Core/Src/soft_rtc.o" "./Core/Src/stm32f1xx_hal_msp.o" "./Core/Src/stm32f1xx_it.o" "./Core/Src/syscalls.o" "./Core/Src/sysmem.o" "./Core/Src/system_stm32f1xx.o" +"./Core/Src/tim.o" "./Core/Src/usart.o" "./Core/Startup/startup_stm32f107vctx.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o" @@ -24,6 +31,7 @@ "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o" +"./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o" "./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o" diff --git a/Debug/objects.mk b/Debug/objects.mk index 94e86f7..b471e98 100755 --- a/Debug/objects.mk +++ b/Debug/objects.mk @@ -1,6 +1,6 @@ ################################################################################ # Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (12.3.rel1) +# Toolchain: GNU Tools for STM32 (13.3.rel1) ################################################################################ USER_OBJS := diff --git a/Debug/sources.mk b/Debug/sources.mk index 025bbe6..e5cd3a7 100755 --- a/Debug/sources.mk +++ b/Debug/sources.mk @@ -1,6 +1,6 @@ ################################################################################ # Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (12.3.rel1) +# Toolchain: GNU Tools for STM32 (13.3.rel1) ################################################################################ ELF_SRCS := @@ -10,16 +10,18 @@ C_SRCS := S_UPPER_SRCS := O_SRCS := CYCLO_FILES := +OBJDUMP_LIST := +S_DEPS := +OBJCOPY_SREC := +C_DEPS := +OBJCOPY_BIN := OBJCOPY_HEX := SIZE_OUTPUT := -OBJDUMP_LIST := SU_FILES := EXECUTABLES := OBJS := MAP_FILES := -S_DEPS := S_UPPER_DEPS := -C_DEPS := # Every subdirectory with source files must be described here SUBDIRS := \ diff --git a/Drivers/.DS_Store b/Drivers/.DS_Store new file mode 100644 index 0000000..c35178d Binary files /dev/null and b/Drivers/.DS_Store differ diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h index 5fbfa7b..6efdf72 100755 --- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h @@ -1,15255 +1,15253 @@ -/** - ****************************************************************************** - * @file stm32f107xc.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f107xc - * @{ - */ - -#ifndef __STM32F107xC_H -#define __STM32F107xC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ - #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ - __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ - uint32_t RESERVED[16]; - __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ -} ADC_Common_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint32_t DR1; - __IO uint32_t DR2; - __IO uint32_t DR3; - __IO uint32_t DR4; - __IO uint32_t DR5; - __IO uint32_t DR6; - __IO uint32_t DR7; - __IO uint32_t DR8; - __IO uint32_t DR9; - __IO uint32_t DR10; - __IO uint32_t RTCCR; - __IO uint32_t CR; - __IO uint32_t CSR; - uint32_t RESERVED13[2]; - __IO uint32_t DR11; - __IO uint32_t DR12; - __IO uint32_t DR13; - __IO uint32_t DR14; - __IO uint32_t DR15; - __IO uint32_t DR16; - __IO uint32_t DR17; - __IO uint32_t DR18; - __IO uint32_t DR19; - __IO uint32_t DR20; - __IO uint32_t DR21; - __IO uint32_t DR22; - __IO uint32_t DR23; - __IO uint32_t DR24; - __IO uint32_t DR25; - __IO uint32_t DR26; - __IO uint32_t DR27; - __IO uint32_t DR28; - __IO uint32_t DR29; - __IO uint32_t DR30; - __IO uint32_t DR31; - __IO uint32_t DR32; - __IO uint32_t DR33; - __IO uint32_t DR34; - __IO uint32_t DR35; - __IO uint32_t DR36; - __IO uint32_t DR37; - __IO uint32_t DR38; - __IO uint32_t DR39; - __IO uint32_t DR40; - __IO uint32_t DR41; - __IO uint32_t DR42; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[28]; -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - - - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t OAR1; - __IO uint32_t OAR2; - __IO uint32_t DR; - __IO uint32_t SR1; - __IO uint32_t SR2; - __IO uint32_t CCR; - __IO uint32_t TRISE; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t CRH; - __IO uint32_t CRL; - __IO uint32_t PRLH; - __IO uint32_t PRLL; - __IO uint32_t DIVH; - __IO uint32_t DIVL; - __IO uint32_t CNTH; - __IO uint32_t CNTL; - __IO uint32_t ALRH; - __IO uint32_t ALRL; -} RTC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SR; - __IO uint32_t DR; - __IO uint32_t CRCPR; - __IO uint32_t RXCRCR; - __IO uint32_t TXCRCR; - __IO uint32_t I2SCFGR; - __IO uint32_t I2SPR; -} SPI_TypeDef; - -/** - * @brief TIM Timers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -}TIM_TypeDef; - - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - - -/** - * @brief __USB_OTG_Core_register - */ - -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h*/ - __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ - __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ - uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief __device_Registers - */ - -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ - __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ - __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ - uint32_t Reserved0C; /*!< Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ - uint32_t Reserved20; /*!< Reserved 820h*/ - uint32_t Reserved9; /*!< Reserved 824h*/ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ - __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ - uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ -} USB_OTG_DeviceTypeDef; - -/** - * @brief __IN_Endpoint-Specific_Register - */ - -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief __OUT_Endpoint-Specific_Registers - */ - -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief __Host_Mode_Register_Structures - */ - -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /*!< Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ -} USB_OTG_HostTypeDef; - -/** - * @brief __Host_Channel_Specific_Registers - */ - -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} USB_OTG_HostChannelTypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END 0x0803FFFFUL /*!< FLASH END address of bank1 */ -#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ -#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) -#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) -#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) -#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) -#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) -#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) -#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) -#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) -#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) - - -#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) -#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ -#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ -#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ -#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x00008000UL) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x00000100UL) -#define ETH_PTP_BASE (ETH_BASE + 0x00000700UL) -#define ETH_DMA_BASE (ETH_BASE + 0x00001000UL) - - -#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ - - -/*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000UL - -#define USB_OTG_GLOBAL_BASE 0x00000000UL -#define USB_OTG_DEVICE_BASE 0x00000800UL -#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL -#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL -#define USB_OTG_EP_REG_SIZE 0x00000020UL -#define USB_OTG_HOST_BASE 0x00000400UL -#define USB_OTG_HOST_PORT_BASE 0x00000440UL -#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL -#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL -#define USB_OTG_PCGCCTL_BASE 0x00000E00UL -#define USB_OTG_FIFO_BASE 0x00001000UL -#define USB_OTG_FIFO_SIZE 0x00001000UL - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define TIM4 ((TIM_TypeDef *)TIM4_BASE) -#define TIM5 ((TIM_TypeDef *)TIM5_BASE) -#define TIM6 ((TIM_TypeDef *)TIM6_BASE) -#define TIM7 ((TIM_TypeDef *)TIM7_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define WWDG ((WWDG_TypeDef *)WWDG_BASE) -#define IWDG ((IWDG_TypeDef *)IWDG_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define SPI3 ((SPI_TypeDef *)SPI3_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define UART4 ((USART_TypeDef *)UART4_BASE) -#define UART5 ((USART_TypeDef *)UART5_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define CAN2 ((CAN_TypeDef *)CAN2_BASE) -#define BKP ((BKP_TypeDef *)BKP_BASE) -#define PWR ((PWR_TypeDef *)PWR_BASE) -#define DAC1 ((DAC_TypeDef *)DAC_BASE) -#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ -#define AFIO ((AFIO_TypeDef *)AFIO_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define ADC2 ((ADC_TypeDef *)ADC2_BASE) -#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA2 ((DMA_TypeDef *)DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *)RCC_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define OB ((OB_TypeDef *)OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) - -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ - /** - * @} - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) -#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) -#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS_Pos (0U) -#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ -#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS_Pos (1U) -#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ -#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF_Pos (2U) -#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ -#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF_Pos (3U) -#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ -#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ -#define PWR_CR_PVDE_Pos (4U) -#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ -#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS_Pos (5U) -#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ -#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ -#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ -#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ -#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ -#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ -#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ -#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ -#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ -#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ -#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ - -/* Legacy defines */ -#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 -#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 -#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 -#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 -#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 -#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 -#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 -#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 - -#define PWR_CR_DBP_Pos (8U) -#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ -#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF_Pos (0U) -#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ -#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ -#define PWR_CSR_SBF_Pos (1U) -#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ -#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ -#define PWR_CSR_PVDO_Pos (2U) -#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ -#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D_Pos (0U) -#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D_Pos (0U) -#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D_Pos (0U) -#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D_Pos (0U) -#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D_Pos (0U) -#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D_Pos (0U) -#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D_Pos (0U) -#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D_Pos (0U) -#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D_Pos (0U) -#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D_Pos (0U) -#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D_Pos (0U) -#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D_Pos (0U) -#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D_Pos (0U) -#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D_Pos (0U) -#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D_Pos (0U) -#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D_Pos (0U) -#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D_Pos (0U) -#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D_Pos (0U) -#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D_Pos (0U) -#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D_Pos (0U) -#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D_Pos (0U) -#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D_Pos (0U) -#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D_Pos (0U) -#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D_Pos (0U) -#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D_Pos (0U) -#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D_Pos (0U) -#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D_Pos (0U) -#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D_Pos (0U) -#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D_Pos (0U) -#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D_Pos (0U) -#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D_Pos (0U) -#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D_Pos (0U) -#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D_Pos (0U) -#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D_Pos (0U) -#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D_Pos (0U) -#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D_Pos (0U) -#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D_Pos (0U) -#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D_Pos (0U) -#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D_Pos (0U) -#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D_Pos (0U) -#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D_Pos (0U) -#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D_Pos (0U) -#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ -#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ - -#define RTC_BKP_NUMBER 42 - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL_Pos (0U) -#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ -#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ -#define BKP_RTCCR_CCO_Pos (7U) -#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ -#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE_Pos (8U) -#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ -#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS_Pos (9U) -#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ -#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE_Pos (0U) -#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ -#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ -#define BKP_CR_TPAL_Pos (1U) -#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ -#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE_Pos (0U) -#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ -#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ -#define BKP_CSR_CTI_Pos (1U) -#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ -#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE_Pos (2U) -#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ -#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF_Pos (8U) -#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ -#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ -#define BKP_CSR_TIF_Pos (9U) -#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ -#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) - */ -#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ -#define RCC_PLLI2S_SUPPORT - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION_Pos (0U) -#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY_Pos (1U) -#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM_Pos (3U) -#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ -#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL_Pos (8U) -#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ -#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON_Pos (16U) -#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ -#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY_Pos (17U) -#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ -#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP_Pos (18U) -#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ -#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON_Pos (19U) -#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ -#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ -#define RCC_CR_PLLON_Pos (24U) -#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ -#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ -#define RCC_CR_PLLRDY_Pos (25U) -#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ -#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ - -#define RCC_CR_PLL2ON_Pos (26U) -#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ -#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ -#define RCC_CR_PLL2RDY_Pos (27U) -#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ -#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ - -#define RCC_CR_PLL3ON_Pos (28U) -#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ -#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ -#define RCC_CR_PLL3RDY_Pos (29U) -#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ -#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW_Pos (0U) -#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ -#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ -#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ - -#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS_Pos (2U) -#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ -#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ -#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ - -#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE_Pos (4U) -#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ -#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ -#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ -#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ -#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ - -#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_Pos (8U) -#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ -#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ -#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ -#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ - -#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_Pos (11U) -#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ -#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ -#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ -#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ - -#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_Pos (14U) -#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ -#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ -#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ - -#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC_Pos (16U) -#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ -#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE_Pos (17U) -#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ -#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL_Pos (18U) -#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ -#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ - -#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ - -#define RCC_CFGR_PLLMULL4_Pos (19U) -#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ -#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */ -#define RCC_CFGR_PLLMULL5_Pos (18U) -#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ -#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */ -#define RCC_CFGR_PLLMULL6_Pos (20U) -#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */ -#define RCC_CFGR_PLLMULL7_Pos (18U) -#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ -#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */ -#define RCC_CFGR_PLLMULL8_Pos (19U) -#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ -#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */ -#define RCC_CFGR_PLLMULL9_Pos (18U) -#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ -#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */ -#define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */ - -#define RCC_CFGR_OTGFSPRE_Pos (22U) -#define RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */ -#define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ -#define RCC_CFGR_MCO_Pos (24U) -#define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ -#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ -#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ -#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ -#define RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */ - -#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ -#define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/ -#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/ -#define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ -#define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */ - - /* Reference defines */ - #define RCC_CFGR_MCOSEL RCC_CFGR_MCO - #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 - #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 - #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 - #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3 - #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK - #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK - #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI - #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE - #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 - #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK - #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 - #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE - #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF_Pos (0U) -#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF_Pos (1U) -#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF_Pos (2U) -#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF_Pos (3U) -#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF_Pos (4U) -#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ -#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF_Pos (7U) -#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ -#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE_Pos (8U) -#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ -#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE_Pos (9U) -#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ -#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE_Pos (10U) -#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ -#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE_Pos (11U) -#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ -#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE_Pos (12U) -#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ -#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC_Pos (16U) -#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ -#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC_Pos (17U) -#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ -#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC_Pos (18U) -#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ -#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC_Pos (19U) -#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ -#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC_Pos (20U) -#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ -#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC_Pos (23U) -#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ -#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ - -#define RCC_CIR_PLL2RDYF_Pos (5U) -#define RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */ -#define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */ -#define RCC_CIR_PLL3RDYF_Pos (6U) -#define RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */ -#define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */ -#define RCC_CIR_PLL2RDYIE_Pos (13U) -#define RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */ -#define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */ -#define RCC_CIR_PLL3RDYIE_Pos (14U) -#define RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */ -#define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */ -#define RCC_CIR_PLL2RDYC_Pos (21U) -#define RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */ -#define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */ -#define RCC_CIR_PLL3RDYC_Pos (22U) -#define RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */ -#define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST_Pos (0U) -#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST_Pos (2U) -#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ -#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST_Pos (3U) -#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ -#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST_Pos (4U) -#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ -#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST_Pos (5U) -#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ -#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST_Pos (9U) -#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ - -#define RCC_APB2RSTR_ADC2RST_Pos (10U) -#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ -#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ - -#define RCC_APB2RSTR_TIM1RST_Pos (11U) -#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST_Pos (12U) -#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST_Pos (14U) -#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ - - -#define RCC_APB2RSTR_IOPERST_Pos (6U) -#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ -#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ - - - - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST_Pos (0U) -#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST_Pos (1U) -#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST_Pos (11U) -#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST_Pos (17U) -#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST_Pos (21U) -#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ - -#define RCC_APB1RSTR_CAN1RST_Pos (25U) -#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ - -#define RCC_APB1RSTR_BKPRST_Pos (27U) -#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST_Pos (28U) -#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ - -#define RCC_APB1RSTR_TIM4RST_Pos (2U) -#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ -#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ -#define RCC_APB1RSTR_SPI2RST_Pos (14U) -#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ -#define RCC_APB1RSTR_USART3RST_Pos (18U) -#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ -#define RCC_APB1RSTR_I2C2RST_Pos (22U) -#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ - - -#define RCC_APB1RSTR_TIM5RST_Pos (3U) -#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ -#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ -#define RCC_APB1RSTR_TIM6RST_Pos (4U) -#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ -#define RCC_APB1RSTR_TIM7RST_Pos (5U) -#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ -#define RCC_APB1RSTR_SPI3RST_Pos (15U) -#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ -#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ -#define RCC_APB1RSTR_UART4RST_Pos (19U) -#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ -#define RCC_APB1RSTR_UART5RST_Pos (20U) -#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ -#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ - - - -#define RCC_APB1RSTR_CAN2RST_Pos (26U) -#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ -#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */ - -#define RCC_APB1RSTR_DACRST_Pos (29U) -#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN_Pos (0U) -#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ -#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN_Pos (2U) -#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ -#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN_Pos (4U) -#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ -#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN_Pos (6U) -#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ -#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ - -#define RCC_AHBENR_DMA2EN_Pos (1U) -#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ -#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ - - -#define RCC_AHBENR_OTGFSEN_Pos (12U) -#define RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */ -#define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */ -#define RCC_AHBENR_ETHMACEN_Pos (14U) -#define RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos) /*!< 0x00004000 */ -#define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk /*!< ETHERNET MAC clock enable */ -#define RCC_AHBENR_ETHMACTXEN_Pos (15U) -#define RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos) /*!< 0x00008000 */ -#define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk /*!< ETHERNET MAC Tx clock enable */ -#define RCC_AHBENR_ETHMACRXEN_Pos (16U) -#define RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos) /*!< 0x00010000 */ -#define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk /*!< ETHERNET MAC Rx clock enable */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN_Pos (0U) -#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ -#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN_Pos (2U) -#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ -#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN_Pos (3U) -#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ -#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN_Pos (4U) -#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ -#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN_Pos (5U) -#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ -#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN_Pos (9U) -#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ -#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ - -#define RCC_APB2ENR_ADC2EN_Pos (10U) -#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ -#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ - -#define RCC_APB2ENR_TIM1EN_Pos (11U) -#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ -#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN_Pos (12U) -#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ -#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN_Pos (14U) -#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ -#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ - - -#define RCC_APB2ENR_IOPEEN_Pos (6U) -#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ -#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ - - - - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN_Pos (0U) -#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ -#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN_Pos (1U) -#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ -#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN_Pos (11U) -#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ -#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN_Pos (17U) -#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ -#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN_Pos (21U) -#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ -#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ - -#define RCC_APB1ENR_CAN1EN_Pos (25U) -#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ -#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ - -#define RCC_APB1ENR_BKPEN_Pos (27U) -#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ -#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN_Pos (28U) -#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ -#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ - -#define RCC_APB1ENR_TIM4EN_Pos (2U) -#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ -#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ -#define RCC_APB1ENR_SPI2EN_Pos (14U) -#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ -#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ -#define RCC_APB1ENR_USART3EN_Pos (18U) -#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ -#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ -#define RCC_APB1ENR_I2C2EN_Pos (22U) -#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ -#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ - - -#define RCC_APB1ENR_TIM5EN_Pos (3U) -#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ -#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ -#define RCC_APB1ENR_TIM6EN_Pos (4U) -#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ -#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ -#define RCC_APB1ENR_TIM7EN_Pos (5U) -#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ -#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ -#define RCC_APB1ENR_SPI3EN_Pos (15U) -#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ -#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ -#define RCC_APB1ENR_UART4EN_Pos (19U) -#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ -#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ -#define RCC_APB1ENR_UART5EN_Pos (20U) -#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ -#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ - - - -#define RCC_APB1ENR_CAN2EN_Pos (26U) -#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ -#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */ - -#define RCC_APB1ENR_DACEN_Pos (29U) -#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ -#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY_Pos (1U) -#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP_Pos (2U) -#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL_Pos (8U) -#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ -#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN_Pos (15U) -#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ -#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ -#define RCC_BDCR_BDRST_Pos (16U) -#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION_Pos (0U) -#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY_Pos (1U) -#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF_Pos (24U) -#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ -#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF_Pos (26U) -#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ -#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF_Pos (27U) -#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ -#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF_Pos (28U) -#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ -#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF_Pos (29U) -#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ -#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF_Pos (30U) -#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ -#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF_Pos (31U) -#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ -#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ - -/******************* Bit definition for RCC_AHBRSTR register ****************/ -#define RCC_AHBRSTR_OTGFSRST_Pos (12U) -#define RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */ -#define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */ -#define RCC_AHBRSTR_ETHMACRST_Pos (14U) -#define RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos) /*!< 0x00004000 */ -#define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ -#define RCC_CFGR2_PREDIV1_Pos (0U) -#define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ -#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ -#define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ -#define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ -#define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ -#define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ - -#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ -#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ -#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ -#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) -#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ -#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ -#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ -#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ -#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) -#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ -#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ -#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ -#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ -#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) -#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ -#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ -#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ -#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ -#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) -#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ -#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ -#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ -#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ -#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) -#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ -#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ -#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ -#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ -#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) -#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ -#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ -#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ -#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ -#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) -#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ -#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ -#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) -#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ -#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ -#define RCC_CFGR2_PREDIV2_Pos (4U) -#define RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */ -#define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */ -#define RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */ -#define RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */ -#define RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */ -#define RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */ - -#define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */ -#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */ -#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */ -#define RCC_CFGR2_PREDIV2_DIV3_Pos (5U) -#define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */ -#define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */ -#define RCC_CFGR2_PREDIV2_DIV4_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */ -#define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */ -#define RCC_CFGR2_PREDIV2_DIV5_Pos (6U) -#define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */ -#define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */ -#define RCC_CFGR2_PREDIV2_DIV6_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */ -#define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */ -#define RCC_CFGR2_PREDIV2_DIV7_Pos (5U) -#define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */ -#define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */ -#define RCC_CFGR2_PREDIV2_DIV8_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */ -#define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */ -#define RCC_CFGR2_PREDIV2_DIV9_Pos (7U) -#define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */ -#define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */ -#define RCC_CFGR2_PREDIV2_DIV10_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */ -#define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */ -#define RCC_CFGR2_PREDIV2_DIV11_Pos (5U) -#define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */ -#define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */ -#define RCC_CFGR2_PREDIV2_DIV12_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */ -#define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */ -#define RCC_CFGR2_PREDIV2_DIV13_Pos (6U) -#define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */ -#define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */ -#define RCC_CFGR2_PREDIV2_DIV14_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */ -#define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */ -#define RCC_CFGR2_PREDIV2_DIV15_Pos (5U) -#define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */ -#define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */ -#define RCC_CFGR2_PREDIV2_DIV16_Pos (4U) -#define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */ -#define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ -#define RCC_CFGR2_PLL2MUL_Pos (8U) -#define RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */ -#define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */ -#define RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */ -#define RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */ -#define RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */ -#define RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */ - -#define RCC_CFGR2_PLL2MUL8_Pos (9U) -#define RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */ -#define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */ -#define RCC_CFGR2_PLL2MUL9_Pos (8U) -#define RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */ -#define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */ -#define RCC_CFGR2_PLL2MUL10_Pos (11U) -#define RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */ -#define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */ -#define RCC_CFGR2_PLL2MUL11_Pos (8U) -#define RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */ -#define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */ -#define RCC_CFGR2_PLL2MUL12_Pos (9U) -#define RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */ -#define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */ -#define RCC_CFGR2_PLL2MUL13_Pos (8U) -#define RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */ -#define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */ -#define RCC_CFGR2_PLL2MUL14_Pos (10U) -#define RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */ -#define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */ -#define RCC_CFGR2_PLL2MUL16_Pos (9U) -#define RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */ -#define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */ -#define RCC_CFGR2_PLL2MUL20_Pos (8U) -#define RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */ -#define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ -#define RCC_CFGR2_PLL3MUL_Pos (12U) -#define RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */ -#define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */ -#define RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */ -#define RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */ -#define RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */ -#define RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */ - -#define RCC_CFGR2_PLL3MUL8_Pos (13U) -#define RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */ -#define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */ -#define RCC_CFGR2_PLL3MUL9_Pos (12U) -#define RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */ -#define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */ -#define RCC_CFGR2_PLL3MUL10_Pos (15U) -#define RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */ -#define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */ -#define RCC_CFGR2_PLL3MUL11_Pos (12U) -#define RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */ -#define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */ -#define RCC_CFGR2_PLL3MUL12_Pos (13U) -#define RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */ -#define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */ -#define RCC_CFGR2_PLL3MUL13_Pos (12U) -#define RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */ -#define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */ -#define RCC_CFGR2_PLL3MUL14_Pos (14U) -#define RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */ -#define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */ -#define RCC_CFGR2_PLL3MUL16_Pos (13U) -#define RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */ -#define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */ -#define RCC_CFGR2_PLL3MUL20_Pos (12U) -#define RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */ -#define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */ - -#define RCC_CFGR2_PREDIV1SRC_Pos (16U) -#define RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */ -#define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U) -#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */ -#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */ -#define RCC_CFGR2_I2S2SRC_Pos (17U) -#define RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */ -#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */ -#define RCC_CFGR2_I2S3SRC_Pos (18U) -#define RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */ -#define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */ - - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE_Pos (0U) -#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0_Pos (0U) -#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_CRL_MODE1_Pos (4U) -#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ -#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ -#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ - -#define GPIO_CRL_MODE2_Pos (8U) -#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ -#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ -#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ - -#define GPIO_CRL_MODE3_Pos (12U) -#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ -#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ -#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ - -#define GPIO_CRL_MODE4_Pos (16U) -#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ -#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ -#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ - -#define GPIO_CRL_MODE5_Pos (20U) -#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ -#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ -#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ - -#define GPIO_CRL_MODE6_Pos (24U) -#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ -#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ -#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ - -#define GPIO_CRL_MODE7_Pos (28U) -#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ -#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ -#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ - -#define GPIO_CRL_CNF_Pos (2U) -#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0_Pos (2U) -#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ -#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ -#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ - -#define GPIO_CRL_CNF1_Pos (6U) -#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ -#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ -#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ - -#define GPIO_CRL_CNF2_Pos (10U) -#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ -#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ -#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ - -#define GPIO_CRL_CNF3_Pos (14U) -#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ -#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ -#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ - -#define GPIO_CRL_CNF4_Pos (18U) -#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ -#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ -#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ - -#define GPIO_CRL_CNF5_Pos (22U) -#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ -#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ -#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ - -#define GPIO_CRL_CNF6_Pos (26U) -#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ -#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ -#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ - -#define GPIO_CRL_CNF7_Pos (30U) -#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ -#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ -#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE_Pos (0U) -#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ -#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8_Pos (0U) -#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ -#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ -#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ - -#define GPIO_CRH_MODE9_Pos (4U) -#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ -#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ -#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ - -#define GPIO_CRH_MODE10_Pos (8U) -#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ -#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ -#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ - -#define GPIO_CRH_MODE11_Pos (12U) -#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ -#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ -#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ - -#define GPIO_CRH_MODE12_Pos (16U) -#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ -#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ -#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ - -#define GPIO_CRH_MODE13_Pos (20U) -#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ -#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ -#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ - -#define GPIO_CRH_MODE14_Pos (24U) -#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ -#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ -#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ - -#define GPIO_CRH_MODE15_Pos (28U) -#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ -#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ -#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ - -#define GPIO_CRH_CNF_Pos (2U) -#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ -#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8_Pos (2U) -#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ -#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ -#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ - -#define GPIO_CRH_CNF9_Pos (6U) -#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ -#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ -#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ - -#define GPIO_CRH_CNF10_Pos (10U) -#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ -#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ -#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ - -#define GPIO_CRH_CNF11_Pos (14U) -#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ -#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ -#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ - -#define GPIO_CRH_CNF12_Pos (18U) -#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ -#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ -#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ - -#define GPIO_CRH_CNF13_Pos (22U) -#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ -#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ -#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ - -#define GPIO_CRH_CNF14_Pos (26U) -#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ -#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ -#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ - -#define GPIO_CRH_CNF15_Pos (30U) -#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ -#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ -#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0_Pos (0U) -#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1_Pos (1U) -#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2_Pos (2U) -#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3_Pos (3U) -#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4_Pos (4U) -#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5_Pos (5U) -#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6_Pos (6U) -#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7_Pos (7U) -#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8_Pos (8U) -#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9_Pos (9U) -#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10_Pos (10U) -#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11_Pos (11U) -#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12_Pos (12U) -#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13_Pos (13U) -#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14_Pos (14U) -#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15_Pos (15U) -#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0_Pos (0U) -#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1_Pos (1U) -#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2_Pos (2U) -#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3_Pos (3U) -#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4_Pos (4U) -#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5_Pos (5U) -#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6_Pos (6U) -#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7_Pos (7U) -#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8_Pos (8U) -#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9_Pos (9U) -#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10_Pos (10U) -#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11_Pos (11U) -#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12_Pos (12U) -#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13_Pos (13U) -#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14_Pos (14U) -#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15_Pos (15U) -#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0_Pos (0U) -#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ -#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1_Pos (1U) -#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ -#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2_Pos (2U) -#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ -#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3_Pos (3U) -#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ -#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4_Pos (4U) -#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ -#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5_Pos (5U) -#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ -#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6_Pos (6U) -#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ -#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7_Pos (7U) -#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ -#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8_Pos (8U) -#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ -#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9_Pos (9U) -#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ -#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10_Pos (10U) -#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ -#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11_Pos (11U) -#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ -#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12_Pos (12U) -#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ -#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13_Pos (13U) -#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ -#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14_Pos (14U) -#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ -#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15_Pos (15U) -#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ -#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0_Pos (16U) -#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ -#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1_Pos (17U) -#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ -#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2_Pos (18U) -#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ -#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3_Pos (19U) -#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ -#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4_Pos (20U) -#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ -#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5_Pos (21U) -#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ -#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6_Pos (22U) -#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ -#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7_Pos (23U) -#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ -#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8_Pos (24U) -#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ -#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9_Pos (25U) -#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ -#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10_Pos (26U) -#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ -#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11_Pos (27U) -#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ -#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12_Pos (28U) -#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ -#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13_Pos (29U) -#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ -#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14_Pos (30U) -#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ -#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15_Pos (31U) -#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ -#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ -#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ -#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ -#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ -#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ -#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ -#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ -#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ -#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ -#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ -#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ -#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ -#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ -#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ -#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ -#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ -#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0_Pos (0U) -#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ -#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1_Pos (1U) -#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ -#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2_Pos (2U) -#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ -#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3_Pos (3U) -#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ -#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4_Pos (4U) -#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ -#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5_Pos (5U) -#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ -#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6_Pos (6U) -#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ -#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7_Pos (7U) -#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ -#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8_Pos (8U) -#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ -#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9_Pos (9U) -#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ -#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10_Pos (10U) -#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ -#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11_Pos (11U) -#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ -#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12_Pos (12U) -#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ -#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13_Pos (13U) -#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ -#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14_Pos (14U) -#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ -#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15_Pos (15U) -#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ -#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK_Pos (16U) -#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ -#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN_Pos (0U) -#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1_Pos (0U) -#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ -#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2_Pos (1U) -#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ -#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3_Pos (0U) -#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ -#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4_Pos (2U) -#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ -#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5_Pos (0U) -#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ -#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6_Pos (1U) -#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ -#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7_Pos (0U) -#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ -#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8_Pos (3U) -#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ -#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9_Pos (0U) -#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ -#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10_Pos (1U) -#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ -#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11_Pos (0U) -#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ -#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12_Pos (2U) -#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ -#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13_Pos (0U) -#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ -#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14_Pos (1U) -#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ -#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15_Pos (0U) -#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ -#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT_Pos (4U) -#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ -#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB_Pos (4U) -#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC_Pos (5U) -#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD_Pos (4U) -#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE_Pos (6U) -#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ - -#define AFIO_EVCR_EVOE_Pos (7U) -#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ -#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP_Pos (0U) -#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ -#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP_Pos (1U) -#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ -#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP_Pos (2U) -#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ -#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP_Pos (3U) -#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ -#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) -#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ -#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP_Pos (12U) -#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ -#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ -#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) -#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) -#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP_Pos (15U) -#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ -#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) -#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ -#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ -#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ - -#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) -#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ - -/*!< ETH_REMAP configuration */ -#define AFIO_MAPR_ETH_REMAP_Pos (21U) -#define AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */ -#define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ -#define AFIO_MAPR_CAN2_REMAP_Pos (22U) -#define AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */ -#define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ -#define AFIO_MAPR_MII_RMII_SEL_Pos (23U) -#define AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */ -#define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ -#define AFIO_MAPR_SPI3_REMAP_Pos (28U) -#define AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */ -#define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ -#define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U) -#define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */ -#define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ -#define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U) -#define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */ -#define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0_Pos (0U) -#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1_Pos (4U) -#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2_Pos (8U) -#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3_Pos (12U) -#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) -#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) -#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) -#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) -#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) -#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) -#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) -#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) -#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) -#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) -#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) -#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) -#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4_Pos (0U) -#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5_Pos (4U) -#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6_Pos (8U) -#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7_Pos (12U) -#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) -#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) -#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) -#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) -#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) -#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) -#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) -#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) -#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) -#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) -#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) -#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) -#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8_Pos (0U) -#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9_Pos (4U) -#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10_Pos (8U) -#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11_Pos (12U) -#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) -#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) -#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) -#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) -#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) -#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) -#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) -#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) -#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) -#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) -#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) -#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) -#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12_Pos (0U) -#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ -#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13_Pos (4U) -#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ -#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14_Pos (8U) -#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ -#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15_Pos (12U) -#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ -#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ -#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ -#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ -#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) -#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ -#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) -#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ -#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) -#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ -#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ -#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ -#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ -#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) -#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ -#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) -#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ -#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) -#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ -#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ -#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ -#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ -#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) -#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ -#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) -#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ -#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) -#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ -#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ -#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ -#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ -#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) -#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ -#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) -#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ -#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) -#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ -#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ - -/****************** Bit definition for AFIO_MAPR2 register ******************/ - - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0_Pos (0U) -#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1_Pos (1U) -#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2_Pos (2U) -#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3_Pos (3U) -#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4_Pos (4U) -#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5_Pos (5U) -#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6_Pos (6U) -#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7_Pos (7U) -#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8_Pos (8U) -#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9_Pos (9U) -#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10_Pos (10U) -#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11_Pos (11U) -#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12_Pos (12U) -#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13_Pos (13U) -#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14_Pos (14U) -#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15_Pos (15U) -#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16_Pos (16U) -#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17_Pos (17U) -#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) -#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19_Pos (19U) -#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ - -/* References Defines */ -#define EXTI_IMR_IM0 EXTI_IMR_MR0 -#define EXTI_IMR_IM1 EXTI_IMR_MR1 -#define EXTI_IMR_IM2 EXTI_IMR_MR2 -#define EXTI_IMR_IM3 EXTI_IMR_MR3 -#define EXTI_IMR_IM4 EXTI_IMR_MR4 -#define EXTI_IMR_IM5 EXTI_IMR_MR5 -#define EXTI_IMR_IM6 EXTI_IMR_MR6 -#define EXTI_IMR_IM7 EXTI_IMR_MR7 -#define EXTI_IMR_IM8 EXTI_IMR_MR8 -#define EXTI_IMR_IM9 EXTI_IMR_MR9 -#define EXTI_IMR_IM10 EXTI_IMR_MR10 -#define EXTI_IMR_IM11 EXTI_IMR_MR11 -#define EXTI_IMR_IM12 EXTI_IMR_MR12 -#define EXTI_IMR_IM13 EXTI_IMR_MR13 -#define EXTI_IMR_IM14 EXTI_IMR_MR14 -#define EXTI_IMR_IM15 EXTI_IMR_MR15 -#define EXTI_IMR_IM16 EXTI_IMR_MR16 -#define EXTI_IMR_IM17 EXTI_IMR_MR17 -#define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM19 EXTI_IMR_MR19 -#define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0_Pos (0U) -#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ -#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1_Pos (1U) -#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ -#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2_Pos (2U) -#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ -#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3_Pos (3U) -#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ -#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4_Pos (4U) -#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ -#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5_Pos (5U) -#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ -#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6_Pos (6U) -#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ -#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7_Pos (7U) -#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ -#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8_Pos (8U) -#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ -#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9_Pos (9U) -#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ -#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10_Pos (10U) -#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ -#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11_Pos (11U) -#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ -#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12_Pos (12U) -#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ -#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13_Pos (13U) -#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ -#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14_Pos (14U) -#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ -#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15_Pos (15U) -#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ -#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16_Pos (16U) -#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ -#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17_Pos (17U) -#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ -#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) -#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19_Pos (19U) -#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ - -/* References Defines */ -#define EXTI_EMR_EM0 EXTI_EMR_MR0 -#define EXTI_EMR_EM1 EXTI_EMR_MR1 -#define EXTI_EMR_EM2 EXTI_EMR_MR2 -#define EXTI_EMR_EM3 EXTI_EMR_MR3 -#define EXTI_EMR_EM4 EXTI_EMR_MR4 -#define EXTI_EMR_EM5 EXTI_EMR_MR5 -#define EXTI_EMR_EM6 EXTI_EMR_MR6 -#define EXTI_EMR_EM7 EXTI_EMR_MR7 -#define EXTI_EMR_EM8 EXTI_EMR_MR8 -#define EXTI_EMR_EM9 EXTI_EMR_MR9 -#define EXTI_EMR_EM10 EXTI_EMR_MR10 -#define EXTI_EMR_EM11 EXTI_EMR_MR11 -#define EXTI_EMR_EM12 EXTI_EMR_MR12 -#define EXTI_EMR_EM13 EXTI_EMR_MR13 -#define EXTI_EMR_EM14 EXTI_EMR_MR14 -#define EXTI_EMR_EM15 EXTI_EMR_MR15 -#define EXTI_EMR_EM16 EXTI_EMR_MR16 -#define EXTI_EMR_EM17 EXTI_EMR_MR17 -#define EXTI_EMR_EM18 EXTI_EMR_MR18 -#define EXTI_EMR_EM19 EXTI_EMR_MR19 - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0_Pos (0U) -#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1_Pos (1U) -#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2_Pos (2U) -#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3_Pos (3U) -#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4_Pos (4U) -#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5_Pos (5U) -#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6_Pos (6U) -#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7_Pos (7U) -#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8_Pos (8U) -#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9_Pos (9U) -#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10_Pos (10U) -#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11_Pos (11U) -#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12_Pos (12U) -#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13_Pos (13U) -#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14_Pos (14U) -#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15_Pos (15U) -#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16_Pos (16U) -#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17_Pos (17U) -#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) -#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19_Pos (19U) -#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ - -/* References Defines */ -#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 -#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 -#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 -#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 -#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 -#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 -#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 -#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 -#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 -#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 -#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 -#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 -#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 -#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 -#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 -#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 -#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 -#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 -#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 -#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0_Pos (0U) -#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ -#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1_Pos (1U) -#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ -#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2_Pos (2U) -#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ -#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3_Pos (3U) -#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ -#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4_Pos (4U) -#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ -#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5_Pos (5U) -#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ -#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6_Pos (6U) -#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ -#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7_Pos (7U) -#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ -#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8_Pos (8U) -#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ -#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9_Pos (9U) -#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ -#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10_Pos (10U) -#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ -#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11_Pos (11U) -#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ -#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12_Pos (12U) -#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ -#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13_Pos (13U) -#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ -#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14_Pos (14U) -#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ -#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15_Pos (15U) -#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ -#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16_Pos (16U) -#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ -#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17_Pos (17U) -#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ -#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) -#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19_Pos (19U) -#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ - -/* References Defines */ -#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 -#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 -#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 -#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 -#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 -#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 -#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 -#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 -#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 -#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 -#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 -#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 -#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 -#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 -#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 -#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 -#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 -#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 -#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 -#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0_Pos (0U) -#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ -#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1_Pos (1U) -#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ -#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2_Pos (2U) -#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ -#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3_Pos (3U) -#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ -#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4_Pos (4U) -#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ -#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5_Pos (5U) -#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ -#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6_Pos (6U) -#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ -#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7_Pos (7U) -#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ -#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8_Pos (8U) -#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ -#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9_Pos (9U) -#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ -#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10_Pos (10U) -#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ -#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11_Pos (11U) -#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ -#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12_Pos (12U) -#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ -#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13_Pos (13U) -#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ -#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14_Pos (14U) -#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ -#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15_Pos (15U) -#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ -#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16_Pos (16U) -#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ -#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17_Pos (17U) -#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ -#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) -#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ -#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19_Pos (19U) -#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ -#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ - -/* References Defines */ -#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 -#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 -#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 -#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 -#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 -#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 -#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 -#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 -#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 -#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 -#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 -#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 -#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 -#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 -#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 -#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 -#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 -#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 -#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 -#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0_Pos (0U) -#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ -#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1_Pos (1U) -#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ -#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2_Pos (2U) -#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ -#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3_Pos (3U) -#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ -#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4_Pos (4U) -#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ -#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5_Pos (5U) -#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ -#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6_Pos (6U) -#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ -#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7_Pos (7U) -#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ -#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8_Pos (8U) -#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ -#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9_Pos (9U) -#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ -#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10_Pos (10U) -#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ -#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11_Pos (11U) -#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ -#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12_Pos (12U) -#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ -#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13_Pos (13U) -#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ -#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14_Pos (14U) -#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ -#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15_Pos (15U) -#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ -#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16_Pos (16U) -#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ -#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17_Pos (17U) -#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ -#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) -#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ -#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19_Pos (19U) -#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ -#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ - -/* References Defines */ -#define EXTI_PR_PIF0 EXTI_PR_PR0 -#define EXTI_PR_PIF1 EXTI_PR_PR1 -#define EXTI_PR_PIF2 EXTI_PR_PR2 -#define EXTI_PR_PIF3 EXTI_PR_PR3 -#define EXTI_PR_PIF4 EXTI_PR_PR4 -#define EXTI_PR_PIF5 EXTI_PR_PR5 -#define EXTI_PR_PIF6 EXTI_PR_PR6 -#define EXTI_PR_PIF7 EXTI_PR_PR7 -#define EXTI_PR_PIF8 EXTI_PR_PR8 -#define EXTI_PR_PIF9 EXTI_PR_PR9 -#define EXTI_PR_PIF10 EXTI_PR_PR10 -#define EXTI_PR_PIF11 EXTI_PR_PR11 -#define EXTI_PR_PIF12 EXTI_PR_PR12 -#define EXTI_PR_PIF13 EXTI_PR_PR13 -#define EXTI_PR_PIF14 EXTI_PR_PR14 -#define EXTI_PR_PIF15 EXTI_PR_PR15 -#define EXTI_PR_PIF16 EXTI_PR_PR16 -#define EXTI_PR_PIF17 EXTI_PR_PR17 -#define EXTI_PR_PIF18 EXTI_PR_PR18 -#define EXTI_PR_PIF19 EXTI_PR_PR19 - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1_Pos (0U) -#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ -#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1_Pos (1U) -#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ -#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1_Pos (2U) -#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ -#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1_Pos (3U) -#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ -#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2_Pos (4U) -#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ -#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2_Pos (5U) -#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ -#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2_Pos (6U) -#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ -#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2_Pos (7U) -#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ -#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3_Pos (8U) -#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ -#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3_Pos (9U) -#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ -#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3_Pos (10U) -#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ -#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3_Pos (11U) -#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ -#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4_Pos (12U) -#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ -#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4_Pos (13U) -#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ -#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4_Pos (14U) -#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ -#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4_Pos (15U) -#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ -#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5_Pos (16U) -#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ -#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5_Pos (17U) -#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ -#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5_Pos (18U) -#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ -#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5_Pos (19U) -#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ -#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6_Pos (20U) -#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ -#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6_Pos (21U) -#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ -#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6_Pos (22U) -#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ -#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6_Pos (23U) -#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ -#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7_Pos (24U) -#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ -#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7_Pos (25U) -#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ -#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7_Pos (26U) -#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ -#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7_Pos (27U) -#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ -#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1_Pos (0U) -#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ -#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1_Pos (1U) -#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ -#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1_Pos (2U) -#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ -#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1_Pos (3U) -#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ -#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2_Pos (4U) -#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ -#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2_Pos (5U) -#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ -#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2_Pos (6U) -#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ -#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2_Pos (7U) -#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ -#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3_Pos (8U) -#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ -#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3_Pos (9U) -#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ -#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3_Pos (10U) -#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ -#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3_Pos (11U) -#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ -#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) -#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) -#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) -#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) -#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5_Pos (16U) -#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ -#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5_Pos (17U) -#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ -#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5_Pos (18U) -#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ -#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5_Pos (19U) -#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ -#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6_Pos (20U) -#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ -#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6_Pos (21U) -#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ -#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6_Pos (22U) -#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ -#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6_Pos (23U) -#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ -#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7_Pos (24U) -#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ -#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7_Pos (25U) -#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ -#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7_Pos (26U) -#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ -#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7_Pos (27U) -#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ -#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR register *******************/ -#define DMA_CCR_EN_Pos (0U) -#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ -#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_TCIE_Pos (1U) -#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ -#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (2U) -#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ -#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE_Pos (3U) -#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ -#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR_Pos (4U) -#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ -#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ -#define DMA_CCR_CIRC_Pos (5U) -#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ -#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ -#define DMA_CCR_PINC_Pos (6U) -#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ -#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ -#define DMA_CCR_MINC_Pos (7U) -#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ -#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ - -#define DMA_CCR_PSIZE_Pos (8U) -#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ -#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ -#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ - -#define DMA_CCR_MSIZE_Pos (10U) -#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ -#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ -#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ - -#define DMA_CCR_PL_Pos (12U) -#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ -#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ -#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ - -#define DMA_CCR_MEM2MEM_Pos (14U) -#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ -#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CNDTR register ******************/ -#define DMA_CNDTR_NDT_Pos (0U) -#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ -#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR register *******************/ -#define DMA_CPAR_PA_Pos (0U) -#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR register *******************/ -#define DMA_CMAR_MA_Pos (0U) -#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ -#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) - */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) -#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ -#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) -#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ -#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) -#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ -#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) -#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ -#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) -#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ -#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ - -/* Legacy defines */ -#define ADC_SR_EOC (ADC_SR_EOS) -#define ADC_SR_JEOC (ADC_SR_JEOS) - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) -#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ -#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ -#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ -#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ -#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ -#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ - -#define ADC_CR1_EOSIE_Pos (5U) -#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ -#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) -#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ -#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) -#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ -#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) -#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ -#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) -#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ -#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) -#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ -#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) -#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ -#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) -#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ -#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ - -#define ADC_CR1_DISCNUM_Pos (13U) -#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ -#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ -#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ -#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ - -#define ADC_CR1_DUALMOD_Pos (16U) -#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ -#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ -#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ -#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ -#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ -#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ - -#define ADC_CR1_JAWDEN_Pos (22U) -#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ -#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) -#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ -#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ - -/* Legacy defines */ -#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) -#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) -#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ -#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) -#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ -#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) -#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ -#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) -#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ -#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) -#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ -#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) -#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ -#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CR2_JEXTSEL_Pos (12U) -#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ -#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ -#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ -#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ - -#define ADC_CR2_JEXTTRIG_Pos (15U) -#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ - -#define ADC_CR2_EXTSEL_Pos (17U) -#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ -#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ -#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ -#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ - -#define ADC_CR2_EXTTRIG_Pos (20U) -#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ -#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) -#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ -#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) -#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ -#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) -#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ -#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) -#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP11_Pos (3U) -#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP12_Pos (6U) -#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP13_Pos (9U) -#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP14_Pos (12U) -#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP15_Pos (15U) -#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP16_Pos (18U) -#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP17_Pos (21U) -#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) -#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP1_Pos (3U) -#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP2_Pos (6U) -#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP3_Pos (9U) -#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP4_Pos (12U) -#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP5_Pos (15U) -#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP6_Pos (18U) -#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP7_Pos (21U) -#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP8_Pos (24U) -#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP9_Pos (27U) -#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) -#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) -#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) -#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) -#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) -#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ -#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) -#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ -#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) -#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ -#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ - -#define ADC_SQR1_SQ14_Pos (5U) -#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ -#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ -#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ - -#define ADC_SQR1_SQ15_Pos (10U) -#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ -#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ -#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ - -#define ADC_SQR1_SQ16_Pos (15U) -#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ -#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ -#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ - -#define ADC_SQR1_L_Pos (20U) -#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) -#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ8_Pos (5U) -#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ -#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ - -#define ADC_SQR2_SQ9_Pos (10U) -#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ -#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ - -#define ADC_SQR2_SQ10_Pos (15U) -#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ -#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ -#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ - -#define ADC_SQR2_SQ11_Pos (20U) -#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ -#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ -#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ - -#define ADC_SQR2_SQ12_Pos (25U) -#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ -#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ -#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) -#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ2_Pos (5U) -#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ -#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ -#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ - -#define ADC_SQR3_SQ3_Pos (10U) -#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ -#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ - -#define ADC_SQR3_SQ4_Pos (15U) -#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ -#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ -#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ - -#define ADC_SQR3_SQ5_Pos (20U) -#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ -#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ -#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ - -#define ADC_SQR3_SQ6_Pos (25U) -#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ -#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ -#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) -#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ - -#define ADC_JSQR_JSQ2_Pos (5U) -#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ - -#define ADC_JSQR_JSQ3_Pos (10U) -#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ - -#define ADC_JSQR_JSQ4_Pos (15U) -#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JL_Pos (20U) -#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) -#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) -#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ -#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) -#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1_Pos (1U) -#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ -#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1_Pos (2U) -#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ -#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1_Pos (3U) -#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ -#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ -#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ -#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ - -#define DAC_CR_WAVE1_Pos (6U) -#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ -#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ -#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ - -#define DAC_CR_MAMP1_Pos (8U) -#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ -#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ -#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ -#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ -#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ - -#define DAC_CR_DMAEN1_Pos (12U) -#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ -#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2_Pos (17U) -#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ -#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2_Pos (18U) -#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ -#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2_Pos (19U) -#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ -#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ -#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ -#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ - -#define DAC_CR_WAVE2_Pos (22U) -#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ -#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ -#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ - -#define DAC_CR_MAMP2_Pos (24U) -#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ -#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ -#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ -#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ -#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ - -#define DAC_CR_DMAEN2_Pos (28U) -#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ -#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ - - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2_Pos (1U) -#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ -#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR_Pos (0U) -#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR_Pos (4U) -#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR_Pos (0U) -#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR_Pos (0U) -#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR_Pos (4U) -#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR_Pos (0U) -#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR_Pos (0U) -#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ -#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR_Pos (16U) -#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ -#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR_Pos (4U) -#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ -#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR_Pos (20U) -#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ -#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR_Pos (0U) -#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ -#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR_Pos (8U) -#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ -#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR_Pos (0U) -#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ -#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR_Pos (0U) -#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ -#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ - - - -/*****************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/*****************************************************************************/ -/******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) -#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ -#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + uint32_t RESERVED[16]; + __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ +} ADC_Common_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; + uint32_t RESERVED13[2]; + __IO uint32_t DR11; + __IO uint32_t DR12; + __IO uint32_t DR13; + __IO uint32_t DR14; + __IO uint32_t DR15; + __IO uint32_t DR16; + __IO uint32_t DR17; + __IO uint32_t DR18; + __IO uint32_t DR19; + __IO uint32_t DR20; + __IO uint32_t DR21; + __IO uint32_t DR22; + __IO uint32_t DR23; + __IO uint32_t DR24; + __IO uint32_t DR25; + __IO uint32_t DR26; + __IO uint32_t DR27; + __IO uint32_t DR28; + __IO uint32_t DR29; + __IO uint32_t DR30; + __IO uint32_t DR31; + __IO uint32_t DR32; + __IO uint32_t DR33; + __IO uint32_t DR34; + __IO uint32_t DR35; + __IO uint32_t DR36; + __IO uint32_t DR37; + __IO uint32_t DR38; + __IO uint32_t DR39; + __IO uint32_t DR40; + __IO uint32_t DR41; + __IO uint32_t DR42; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; + __IO uint32_t I2SCFGR; + __IO uint32_t I2SPR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + + +/** + * @brief __USB_OTG_Core_register + */ + +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief __device_Registers + */ + +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ + __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ + uint32_t Reserved0C; /*!< Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ + uint32_t Reserved20; /*!< Reserved 820h*/ + uint32_t Reserved9; /*!< Reserved 824h*/ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ + uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief __IN_Endpoint-Specific_Register + */ + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief __Host_Mode_Register_Structures + */ + +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /*!< Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief __Host_Channel_Specific_Registers + */ + +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFUL /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) + + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x00008000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x00000100UL) +#define ETH_PTP_BASE (ETH_BASE + 0x00000700UL) +#define ETH_DMA_BASE (ETH_BASE + 0x00001000UL) + + +#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ + + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x00000000UL +#define USB_OTG_DEVICE_BASE 0x00000800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL +#define USB_OTG_EP_REG_SIZE 0x00000020UL +#define USB_OTG_HOST_BASE 0x00000400UL +#define USB_OTG_HOST_PORT_BASE 0x00000440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL +#define USB_OTG_PCGCCTL_BASE 0x00000E00UL +#define USB_OTG_FIFO_BASE 0x00001000UL +#define USB_OTG_FIFO_SIZE 0x00001000UL + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CAN2 ((CAN_TypeDef *)CAN2_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC1 ((DAC_TypeDef *)DAC_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D_Pos (0U) +#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D_Pos (0U) +#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D_Pos (0U) +#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D_Pos (0U) +#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D_Pos (0U) +#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D_Pos (0U) +#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D_Pos (0U) +#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D_Pos (0U) +#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D_Pos (0U) +#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D_Pos (0U) +#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D_Pos (0U) +#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D_Pos (0U) +#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D_Pos (0U) +#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D_Pos (0U) +#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D_Pos (0U) +#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D_Pos (0U) +#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D_Pos (0U) +#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D_Pos (0U) +#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D_Pos (0U) +#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D_Pos (0U) +#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D_Pos (0U) +#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D_Pos (0U) +#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D_Pos (0U) +#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D_Pos (0U) +#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D_Pos (0U) +#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D_Pos (0U) +#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D_Pos (0U) +#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D_Pos (0U) +#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D_Pos (0U) +#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D_Pos (0U) +#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D_Pos (0U) +#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D_Pos (0U) +#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ + +#define RTC_BKP_NUMBER 42 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ +#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ +#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ +#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ +#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ +#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ +#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ +#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ +#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ +#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ +#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ +#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ +#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ +#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ +#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ +#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 series) + */ +#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ +#define RCC_PLLI2S_SUPPORT + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ + +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ + +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */ +#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ +#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */ +#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */ +#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ +#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */ +#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ +#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */ +#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ +#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */ +#define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */ + +#define RCC_CFGR_OTGFSPRE_Pos (22U) +#define RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */ + +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/ +#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/ +#define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ +#define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */ + + /* Reference defines */ + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK + #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 + #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE + #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ + +#define RCC_CIR_PLL2RDYF_Pos (5U) +#define RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */ +#define RCC_CIR_PLL3RDYF_Pos (6U) +#define RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */ +#define RCC_CIR_PLL2RDYIE_Pos (13U) +#define RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */ +#define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */ +#define RCC_CIR_PLL3RDYIE_Pos (14U) +#define RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */ +#define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */ +#define RCC_CIR_PLL2RDYC_Pos (21U) +#define RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */ +#define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */ +#define RCC_CIR_PLL3RDYC_Pos (22U) +#define RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */ +#define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ + +#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ + +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ + + +#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ + + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ + +#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ + +#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ + + +#define RCC_APB1RSTR_TIM5RST_Pos (3U) +#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST_Pos (5U) +#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ +#define RCC_APB1RSTR_SPI3RST_Pos (15U) +#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ +#define RCC_APB1RSTR_UART4RST_Pos (19U) +#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ +#define RCC_APB1RSTR_UART5RST_Pos (20U) +#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ + + + +#define RCC_APB1RSTR_CAN2RST_Pos (26U) +#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */ + +#define RCC_APB1RSTR_DACRST_Pos (29U) +#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ +#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ + +#define RCC_AHBENR_DMA2EN_Pos (1U) +#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ + + +#define RCC_AHBENR_OTGFSEN_Pos (12U) +#define RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */ +#define RCC_AHBENR_ETHMACEN_Pos (14U) +#define RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos) /*!< 0x00004000 */ +#define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk /*!< ETHERNET MAC clock enable */ +#define RCC_AHBENR_ETHMACTXEN_Pos (15U) +#define RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos) /*!< 0x00008000 */ +#define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk /*!< ETHERNET MAC Tx clock enable */ +#define RCC_AHBENR_ETHMACRXEN_Pos (16U) +#define RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk /*!< ETHERNET MAC Rx clock enable */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ +#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ + +#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ +#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ + +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ + + +#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ + + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ + +#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ + +#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ + + +#define RCC_APB1ENR_TIM5EN_Pos (3U) +#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN_Pos (5U) +#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ +#define RCC_APB1ENR_SPI3EN_Pos (15U) +#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ +#define RCC_APB1ENR_UART4EN_Pos (19U) +#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ +#define RCC_APB1ENR_UART5EN_Pos (20U) +#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ + + + +#define RCC_APB1ENR_CAN2EN_Pos (26U) +#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ +#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */ + +#define RCC_APB1ENR_DACEN_Pos (29U) +#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +/*!< RTC configuration */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ****************/ +#define RCC_AHBRSTR_OTGFSRST_Pos (12U) +#define RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */ +#define RCC_AHBRSTR_ETHMACRST_Pos (14U) +#define RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos) /*!< 0x00004000 */ +#define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ +#define RCC_CFGR2_PREDIV1_Pos (0U) +#define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ +#define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ +#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ +#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) +#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ +#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ +#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ +#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) +#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ +#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ +#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ +#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) +#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ +#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ +#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ +#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) +#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ +#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ +#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ +#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ +#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) +#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ +#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ +#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ +#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ +#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) +#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ +#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ +#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ +#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ +#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) +#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ +#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ +#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) +#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ +#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ +#define RCC_CFGR2_PREDIV2_Pos (4U) +#define RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */ +#define RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */ +#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */ +#define RCC_CFGR2_PREDIV2_DIV3_Pos (5U) +#define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */ +#define RCC_CFGR2_PREDIV2_DIV4_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */ +#define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */ +#define RCC_CFGR2_PREDIV2_DIV5_Pos (6U) +#define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */ +#define RCC_CFGR2_PREDIV2_DIV6_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */ +#define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */ +#define RCC_CFGR2_PREDIV2_DIV7_Pos (5U) +#define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */ +#define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */ +#define RCC_CFGR2_PREDIV2_DIV8_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */ +#define RCC_CFGR2_PREDIV2_DIV9_Pos (7U) +#define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */ +#define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */ +#define RCC_CFGR2_PREDIV2_DIV10_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */ +#define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */ +#define RCC_CFGR2_PREDIV2_DIV11_Pos (5U) +#define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */ +#define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */ +#define RCC_CFGR2_PREDIV2_DIV12_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */ +#define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */ +#define RCC_CFGR2_PREDIV2_DIV13_Pos (6U) +#define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */ +#define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */ +#define RCC_CFGR2_PREDIV2_DIV14_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */ +#define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */ +#define RCC_CFGR2_PREDIV2_DIV15_Pos (5U) +#define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */ +#define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */ +#define RCC_CFGR2_PREDIV2_DIV16_Pos (4U) +#define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ +#define RCC_CFGR2_PLL2MUL_Pos (8U) +#define RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */ +#define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */ +#define RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */ +#define RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */ + +#define RCC_CFGR2_PLL2MUL8_Pos (9U) +#define RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */ +#define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */ +#define RCC_CFGR2_PLL2MUL9_Pos (8U) +#define RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */ +#define RCC_CFGR2_PLL2MUL10_Pos (11U) +#define RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */ +#define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */ +#define RCC_CFGR2_PLL2MUL11_Pos (8U) +#define RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */ +#define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */ +#define RCC_CFGR2_PLL2MUL12_Pos (9U) +#define RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */ +#define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */ +#define RCC_CFGR2_PLL2MUL13_Pos (8U) +#define RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */ +#define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */ +#define RCC_CFGR2_PLL2MUL14_Pos (10U) +#define RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */ +#define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */ +#define RCC_CFGR2_PLL2MUL16_Pos (9U) +#define RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */ +#define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */ +#define RCC_CFGR2_PLL2MUL20_Pos (8U) +#define RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */ +#define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ +#define RCC_CFGR2_PLL3MUL_Pos (12U) +#define RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */ +#define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */ +#define RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR2_PLL3MUL8_Pos (13U) +#define RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */ +#define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */ +#define RCC_CFGR2_PLL3MUL9_Pos (12U) +#define RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */ +#define RCC_CFGR2_PLL3MUL10_Pos (15U) +#define RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */ +#define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */ +#define RCC_CFGR2_PLL3MUL11_Pos (12U) +#define RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */ +#define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */ +#define RCC_CFGR2_PLL3MUL12_Pos (13U) +#define RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */ +#define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */ +#define RCC_CFGR2_PLL3MUL13_Pos (12U) +#define RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */ +#define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */ +#define RCC_CFGR2_PLL3MUL14_Pos (14U) +#define RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */ +#define RCC_CFGR2_PLL3MUL16_Pos (13U) +#define RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */ +#define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */ +#define RCC_CFGR2_PLL3MUL20_Pos (12U) +#define RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */ +#define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */ + +#define RCC_CFGR2_PREDIV1SRC_Pos (16U) +#define RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U) +#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */ +#define RCC_CFGR2_I2S2SRC_Pos (17U) +#define RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */ +#define RCC_CFGR2_I2S3SRC_Pos (18U) +#define RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */ + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ + +#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ +#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ +#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ + +#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ +#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ +#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ + +#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ +#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ +#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ + +#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ +#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ +#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ + +#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ +#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ +#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ + +#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ +#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ +#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ + +#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ +#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ +#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ + +#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ +#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ +#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ + +#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ +#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ +#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ + +#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ +#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ +#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ + +#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ +#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ +#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ + +#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ +#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ +#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ + +#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ +#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ +#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ + +#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ +#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ +#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ + +#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ +#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ +#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ +#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ +#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ + +#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ +#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ +#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ + +#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ +#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ +#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ + +#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ +#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ +#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ + +#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ +#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ +#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ + +#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ +#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ +#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ + +#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ +#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ +#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ + +#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ +#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ +#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ + +#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ +#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ +#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ + +#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ +#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ +#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ + +#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ +#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ +#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ + +#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ +#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ +#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ + +#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ +#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ +#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ + +#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ +#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ +#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ + +#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ +#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ +#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ + +#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ +#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ +#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ +#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ +#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ +#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ +#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ +#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ +#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ +#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ +#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ +#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ +#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ +#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ +#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ + +#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ +#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ +#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ +#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ +#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ +#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ +#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ +#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ +#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) +#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ +#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ +#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ + +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ +#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ + +/*!< ETH_REMAP configuration */ +#define AFIO_MAPR_ETH_REMAP_Pos (21U) +#define AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */ +#define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ +#define AFIO_MAPR_CAN2_REMAP_Pos (22U) +#define AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */ +#define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ +#define AFIO_MAPR_MII_RMII_SEL_Pos (23U) +#define AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */ +#define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ +#define AFIO_MAPR_SPI3_REMAP_Pos (28U) +#define AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */ +#define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ +#define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U) +#define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */ +#define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ +#define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U) +#define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */ +#define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM19 EXTI_IMR_MR19 +#define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 +#define EXTI_EMR_EM19 EXTI_EMR_MR19 + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 +#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 +#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF18 EXTI_PR_PR18 +#define EXTI_PR_PIF19 EXTI_PR_PR19 + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOS) +#define ADC_SR_JEOC (ADC_SR_JEOS) + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ +#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ +#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ +#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ +#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ + +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ + +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ + +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ + +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ + +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2_Pos (17U) +#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ +#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2_Pos (18U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2_Pos (19U) +#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ + +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ +#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ + +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ + +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ + + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2_Pos (1U) +#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ + + + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f1xx - * @{ - */ - -#ifndef __STM32F1XX_H -#define __STM32F1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F1) -#define STM32F1 -#endif /* STM32F1 */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ - !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ - !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) - /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ - /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ - /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ - /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ - /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ - /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ - /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ - /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ - /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ - /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ - /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ - /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ - /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ - /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V4.3.3 - */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F1_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ - |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F1_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F100xB) - #include "stm32f100xb.h" -#elif defined(STM32F100xE) - #include "stm32f100xe.h" -#elif defined(STM32F101x6) - #include "stm32f101x6.h" -#elif defined(STM32F101xB) - #include "stm32f101xb.h" -#elif defined(STM32F101xE) - #include "stm32f101xe.h" -#elif defined(STM32F101xG) - #include "stm32f101xg.h" -#elif defined(STM32F102x6) - #include "stm32f102x6.h" -#elif defined(STM32F102xB) - #include "stm32f102xb.h" -#elif defined(STM32F103x6) - #include "stm32f103x6.h" -#elif defined(STM32F103xB) - #include "stm32f103xb.h" -#elif defined(STM32F103xE) - #include "stm32f103xe.h" -#elif defined(STM32F103xG) - #include "stm32f103xg.h" -#elif defined(STM32F105xC) - #include "stm32f105xc.h" -#elif defined(STM32F107xC) - #include "stm32f107xc.h" -#else - #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - SUCCESS = 0U, - ERROR = !SUCCESS -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - -/* Use of CMSIS compiler intrinsics for register exclusive access */ -/* Atomic 32-bit register access macro to set one or several bits */ -#define ATOMIC_SET_BIT(REG, BIT) \ - do { \ - uint32_t val; \ - do { \ - val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 32-bit register access macro to clear one or several bits */ -#define ATOMIC_CLEAR_BIT(REG, BIT) \ - do { \ - uint32_t val; \ - do { \ - val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 32-bit register access macro to clear and set one or several bits */ -#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ - do { \ - uint32_t val; \ - do { \ - val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to set one or several bits */ -#define ATOMIC_SETH_BIT(REG, BIT) \ - do { \ - uint16_t val; \ - do { \ - val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to clear one or several bits */ -#define ATOMIC_CLEARH_BIT(REG, BIT) \ - do { \ - uint16_t val; \ - do { \ - val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to clear and set one or several bits */ -#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ - do { \ - uint16_t val; \ - do { \ - val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx.h + * @author MCD Application Team + * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32F1xx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) + /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ + /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F1_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h index 8e33366..f8c5304 100755 --- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h @@ -1,98 +1,96 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file system_stm32f1xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 412525a..f71f5c2 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -1,3783 +1,4377 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_HAL_LEGACY -#define STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 - -#if defined(STM32H7) -#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT -#endif /* STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -#if defined(STM32G4) || defined(STM32H7) -#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL -#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL -#endif - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) -#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID -#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID -#endif - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - -#if defined(STM32L4) - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif - -#endif /* STM32L4 */ - -#if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 -#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM -#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM - -#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM -#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM -#endif - -#if defined(STM32H7) - -#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - -#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX -#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 -#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT - -#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT -#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else -#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE -#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE -#endif -#if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) -#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE -#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE -#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET -#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -#if defined(STM32G4) - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster -#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD -#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD -#endif /* STM32G4 */ -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32H7) -#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 -#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 -#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 -#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 -#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 -#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 - -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ - defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) -#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS -#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS -#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ -#endif /* STM32H7 */ - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE - -#if defined(STM32G4) -#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig -#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable -#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable -#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset -#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A -#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B -#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL -#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL -#endif /* STM32G4 */ - -#if defined(STM32H7) -#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 - -#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 -#endif /* STM32H7 */ - -#if defined(STM32F3) -/** @brief Constants defining available sources associated to external events. - */ -#define HRTIM_EVENTSRC_1 (0x00000000U) -#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) -#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) -#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) - -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - -/** @brief Constants defining the DLL calibration periods (in micro seconds) - */ -#define HRTIM_CALIBRATIONRATE_7300 0x00000000U -#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) -#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) -#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - -#endif /* STM32F3 */ -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) -#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID -#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID -#endif - - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS - -#if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP - - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP -#endif - -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -#if defined(STM32H7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT - -#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 -#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 -#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -#if defined(STM32H7) - - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP - - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP - - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -#if defined(STM32L0) -#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO -#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO -#endif - -#if defined(STM32F3) -#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE -#endif - -#if defined(STM32H7) -#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 -#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 -#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 -#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 -#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 -#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 -#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 -#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 -#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 -#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 -#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 -#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 -#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 -#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 -#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 -#endif - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY - -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) - -#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt -#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End -#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT -#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT - -#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt -#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End -#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT -#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT - -#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt -#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End -#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT -#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT - -#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt -#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End -#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT -#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT - -#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) -#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode -#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode -#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode -#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode -#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT -#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT -#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT -#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA -#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA -#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA -#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ - -#if defined(STM32F4) -#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT -#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT -#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT -#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT -#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA -#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA -#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA -#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA -#endif /* STM32F4 */ - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ - -#if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler -#endif -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) -#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro -#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT -#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback -#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent -#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT -#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 -#else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#endif /* STM32H7 */ -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -#if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET - -#if defined(STM32H7) -#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE -#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE - -#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ -#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ - - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED -#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED -#endif - -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET - -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32L1) -#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#endif /* STM32L1 */ - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) || defined(STM32L5) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop -#endif -/** - * @} - */ - -/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif /* STM32L4 || STM32F4 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS */ + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h index 6228edb..a67a3b9 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -1,358 +1,357 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_H -#define __STM32F1xx_HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_conf.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -/** @defgroup HAL_TICK_FREQ Tick Frequency - * @{ - */ -typedef enum -{ - HAL_TICK_FREQ_10HZ = 100U, - HAL_TICK_FREQ_100HZ = 10U, - HAL_TICK_FREQ_1KHZ = 1U, - HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ -} HAL_TickFreqTypeDef; -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern HAL_TickFreqTypeDef uwTickFreq; - -/** - * @} - */ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode - * @brief Freeze/Unfreeze Peripherals in Debug mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @{ - */ - -/* Peripherals on APB1 */ -/** - * @brief TIM2 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) - -/** - * @brief TIM3 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) - -#if defined (DBGMCU_CR_DBG_TIM4_STOP) -/** - * @brief TIM4 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM5_STOP) -/** - * @brief TIM5 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM6_STOP) -/** - * @brief TIM6 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM7_STOP) -/** - * @brief TIM7 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM12_STOP) -/** - * @brief TIM12 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM13_STOP) -/** - * @brief TIM13 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM14_STOP) -/** - * @brief TIM14 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) -#endif - -/** - * @brief WWDG Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) - -/** - * @brief IWDG Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) - -/** - * @brief I2C1 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) - -#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) -/** - * @brief I2C2 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) -#endif - -#if defined (DBGMCU_CR_DBG_CAN1_STOP) -/** - * @brief CAN1 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_CAN2_STOP) -/** - * @brief CAN2 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) -#endif - -/* Peripherals on APB2 */ -#if defined (DBGMCU_CR_DBG_TIM1_STOP) -/** - * @brief TIM1 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM8_STOP) -/** - * @brief TIM8 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM9_STOP) -/** - * @brief TIM9 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM10_STOP) -/** - * @brief TIM10 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM11_STOP) -/** - * @brief TIM11 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) -#endif - - -#if defined (DBGMCU_CR_DBG_TIM15_STOP) -/** - * @brief TIM15 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM16_STOP) -/** - * @brief TIM16 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) -#endif - -#if defined (DBGMCU_CR_DBG_TIM17_STOP) -/** - * @brief TIM17 Peripherals Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) -#endif - -/** - * @} - */ - -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ - ((FREQ) == HAL_TICK_FREQ_100HZ) || \ - ((FREQ) == HAL_TICK_FREQ_1KHZ)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions - * @{ - */ -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); -HAL_TickFreqTypeDef HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_H +#define __STM32F1xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_conf.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @{ + */ + +/* Peripherals on APB1 */ +/** + * @brief TIM2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) + +/** + * @brief TIM3 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) + +#if defined (DBGMCU_CR_DBG_TIM4_STOP) +/** + * @brief TIM4 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM5_STOP) +/** + * @brief TIM5 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM6_STOP) +/** + * @brief TIM6 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM7_STOP) +/** + * @brief TIM7 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM12_STOP) +/** + * @brief TIM12 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM13_STOP) +/** + * @brief TIM13 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM14_STOP) +/** + * @brief TIM14 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#endif + +/** + * @brief WWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) + +/** + * @brief IWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) + +/** + * @brief I2C1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) + +#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +/** + * @brief I2C2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#endif + +#if defined (DBGMCU_CR_DBG_CAN1_STOP) +/** + * @brief CAN1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_CAN2_STOP) +/** + * @brief CAN2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#endif + +/* Peripherals on APB2 */ +#if defined (DBGMCU_CR_DBG_TIM1_STOP) +/** + * @brief TIM1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM8_STOP) +/** + * @brief TIM8 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM9_STOP) +/** + * @brief TIM9 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM10_STOP) +/** + * @brief TIM10 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM11_STOP) +/** + * @brief TIM11 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#endif + + +#if defined (DBGMCU_CR_DBG_TIM15_STOP) +/** + * @brief TIM15 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM16_STOP) +/** + * @brief TIM16 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM17_STOP) +/** + * @brief TIM17 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#endif + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h index b4be080..f5e6d36 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h @@ -1,1004 +1,1000 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_adc.h - * @author MCD Application Team - * @brief Header file containing functions prototypes of ADC HAL library. - ****************************************************************************** - * @attention - * - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_ADC_H -#define __STM32F1xx_HAL_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief Structure definition of ADC and regular group initialization - * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. - * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. - * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. - * ADC can be either disabled or enabled without conversion on going on regular group. - */ -typedef struct -{ - uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) - or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). - This parameter can be a value of @ref ADC_Data_align */ - uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). - If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). - Scan direction is upward: from rank1 to rank 'n'. - This parameter can be a value of @ref ADC_Scan_mode - Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) - or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the - the last conversion of the sequence. All previous conversions would be overwritten by the last one. - Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ - FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, - after the selected trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. - To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ - FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. - If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. - This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ - uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. - If set to ADC_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. - This parameter can be a value of @ref ADC_External_trigger_source_Regular */ -}ADC_InitTypeDef; - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC can be either disabled or enabled without conversion on going on regular group. - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. - Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) - Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. - It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. - Refer to errata sheet of these devices for more details. */ - uint32_t Rank; /*!< Specifies the rank in the regular group sequencer - This parameter can be a value of @ref ADC_regular_rank - Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ -}ADC_ChannelConfTypeDef; - -/** - * @brief ADC Configuration analog watchdog definition - * @note The setting of these parameters with function is conditioned to ADC state. - * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. - */ -typedef struct -{ - uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. - This parameter can be a value of @ref ADC_analog_watchdog_mode. */ - uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. - This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) - This parameter can be a value of @ref ADC_channels. */ - FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. - This parameter can be set to ENABLE or DISABLE */ - uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; - -/** - * @brief HAL ADC state machine: ADC states definition (bitfields) - */ -/* States of ADC global scope */ -#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ - -/* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ - -/* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ - -/* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ - -/* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ - -/* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ - - -/** - * @brief ADC handle Structure definition - */ -typedef struct __ADC_HandleTypeDef -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC required parameters */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ - void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ - void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ - void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ - void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ - void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; - - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ADC Callback ID enumeration definition - */ -typedef enum -{ - HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ - HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ - HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ - HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ - HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ - HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ -} HAL_ADC_CallbackIDTypeDef; - -/** - * @brief HAL ADC Callback pointer definition - */ -typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - - -/** @defgroup ADC_Data_align ADC data alignment - * @{ - */ -#define ADC_DATAALIGN_RIGHT 0x00000000U -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC scan mode - * @{ - */ -/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ -/* compatibility with other STM32 devices having a sequencer with */ -/* additional options. */ -#define ADC_SCAN_DISABLE 0x00000000U -#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) -/** - * @} - */ - -/** @defgroup ADC_channels ADC channels - * @{ - */ -/* Note: Depending on devices, some channels may not be available on package */ -/* pins. Refer to device datasheet for channels availability. */ -#define ADC_CHANNEL_0 0x00000000U -#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) -#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) -#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) -#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) -#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) -#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) -#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) -#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) -#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) -#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) - -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC sampling times - * @{ - */ -#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ -#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ -#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ -#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ -#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ -#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_regular_rank ADC rank into regular group - * @{ - */ -#define ADC_REGULAR_RANK_1 0x00000001U -#define ADC_REGULAR_RANK_2 0x00000002U -#define ADC_REGULAR_RANK_3 0x00000003U -#define ADC_REGULAR_RANK_4 0x00000004U -#define ADC_REGULAR_RANK_5 0x00000005U -#define ADC_REGULAR_RANK_6 0x00000006U -#define ADC_REGULAR_RANK_7 0x00000007U -#define ADC_REGULAR_RANK_8 0x00000008U -#define ADC_REGULAR_RANK_9 0x00000009U -#define ADC_REGULAR_RANK_10 0x0000000AU -#define ADC_REGULAR_RANK_11 0x0000000BU -#define ADC_REGULAR_RANK_12 0x0000000CU -#define ADC_REGULAR_RANK_13 0x0000000DU -#define ADC_REGULAR_RANK_14 0x0000000EU -#define ADC_REGULAR_RANK_15 0x0000000FU -#define ADC_REGULAR_RANK_16 0x00000010U -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE 0x00000000U -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -/** - * @} - */ - -/** @defgroup ADC_conversion_group ADC conversion group - * @{ - */ -#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) -#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) -#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event type - * @{ - */ -#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ - -#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition ADC interrupts definition - * @{ - */ -#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC flags definition - * @{ - */ -#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ -#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ -#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ -#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ -#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ -/** - * @} - */ - - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -/** @defgroup ADC_conversion_cycles ADC conversion cycles - * @{ - */ -/* ADC conversion cycles (unit: ADC clock cycles) */ -/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ -/* resolution 12 bits) */ -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U -/** - * @} - */ - -/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels - * @{ - */ -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ - (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ - ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ - ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ - (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ - ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) - -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ - (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ - ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ - ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ - (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ - ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) - -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ - (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ - ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ - ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ - (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ - ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) - -#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U -#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) -#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) -#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) -#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) -#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) -#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) -#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) - -#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U -#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) -#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) -#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) -#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) -#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) -#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) -#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) -/** - * @} - */ - -/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** - * @brief Enable the ADC peripheral - * @note ADC enable requires a delay for ADC stabilization time - * (refer to device datasheet, parameter tSTAB) - * @note On STM32F1, if ADC is already enabled this macro trigs a conversion - * SW start on regular group. - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_ENABLE(__HANDLE__) \ - (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) - -/** - * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_DISABLE(__HANDLE__) \ - (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) - -/** @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) - -/** @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @retval None - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Get the selected ADC's flag status. - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_STRT: ADC Regular group start flag - * @arg ADC_FLAG_JSTRT: ADC Injected group start flag - * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag - * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag - * @arg ADC_FLAG_AWD: ADC Analog watchdog flag - * @retval None - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the ADC's pending flags - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_STRT: ADC Regular group start flag - * @arg ADC_FLAG_JSTRT: ADC Injected group start flag - * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag - * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag - * @arg ADC_FLAG_AWD: ADC Analog watchdog flag - * @retval None - */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) - -/** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle - * @retval None - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif - -/** - * @} - */ - -/* Private macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define ADC_IS_ENABLE(__HANDLE__) \ - ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ - ) ? SET : RESET) - -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) - -/** - * @brief Test if conversion trigger of injected group is software start - * or external trigger. - * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) - -/** - * @brief Simultaneously clears and sets specific bits of the handle State - * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), - * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. - * @retval None - */ -#define ADC_STATE_CLR_SET MODIFY_REG - -/** - * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle - * @retval None - */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ - ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - -/** - * @brief Set ADC number of conversions into regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length - * @retval None - */ -#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ - (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) - -/** - * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) - -/** - * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) - -/** - * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) - -/** - * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) - -/** - * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) - -/** - * @brief Set the injected sequence length. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ - (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) - -/** - * @brief Set the selected injected channel rank - * Note: on STM32F1 devices, channel rank position in JSQR register - * is depending on total number of ranks selected into - * injected sequencer (ranks sequence starting from 4-JL) - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ - ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. - * @retval None - */ -#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ - ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) - -/** - * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. - * @retval None - */ -#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ - (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) - -/** - * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_: Scan conversion mode. - * @retval None - */ -/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ -/* is equivalent to ADC_SCAN_ENABLE. */ -#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ - (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ - )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ - ) - -/** - * @brief Get the maximum ADC conversion cycles on all channels. - * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) - * Approximation of sampling time within 4 ranges, returns the highest value: - * below 7.5 cycles {1.5 cycle; 7.5 cycles}, - * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} - * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} - * equal to 239.5 cycles - * Unit: ADC clock cycles - * @param __HANDLE__: ADC handle - * @retval ADC conversion cycles on all channels - */ -#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ - (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ - \ - (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ - ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ - : \ - ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ - ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ - ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ - ) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) - -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ - ((SCAN_MODE) == ADC_SCAN_ENABLE) ) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) ) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ - ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) - -#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_10) || \ - ((CHANNEL) == ADC_REGULAR_RANK_11) || \ - ((CHANNEL) == ADC_REGULAR_RANK_12) || \ - ((CHANNEL) == ADC_REGULAR_RANK_13) || \ - ((CHANNEL) == ADC_REGULAR_RANK_14) || \ - ((CHANNEL) == ADC_REGULAR_RANK_15) || \ - ((CHANNEL) == ADC_REGULAR_RANK_16) ) - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) - -#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ - ((CONVERSION) == ADC_INJECTED_GROUP) || \ - ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) - -#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) - - -/** @defgroup ADC_range_verification ADC range verification - * For a unique ADC resolution: 12 bits - * @{ - */ -#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) -/** - * @} - */ - -/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification - * @{ - */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification - * @{ - */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) -/** - * @} - */ - -/** - * @} - */ - -/* Include ADC HAL Extension module */ -#include "stm32f1xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @{ - */ - - -/* Initialization and de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* IO operation functions *****************************************************/ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @{ - */ - - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); - -/* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup ADC_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); -/** - * @} - */ - - -/* Peripheral State functions *************************************************/ -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/** - * @} - */ - - -/* Internal HAL driver functions **********************************************/ -/** @addtogroup ADC_Private_Functions - * @{ - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); -void ADC_StabilizationTime(uint32_t DelayUs); -void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -void ADC_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F1xx_HAL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_adc.h + * @author MCD Application Team + * @brief Header file containing functions prototypes of ADC HAL library. + ****************************************************************************** + * @attention + * + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_ADC_H +#define __STM32F1xx_HAL_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode + Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) + or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the + the last conversion of the sequence. All previous conversions would be overwritten by the last one. + Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ + FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADC_External_trigger_source_Regular */ +}ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. + Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) + Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. + It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. + Refer to errata sheet of these devices for more details. */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer + This parameter can be a value of @ref ADC_regular_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ +}ADC_ChannelConfTypeDef; + +/** + * @brief ADC Configuration analog watchdog definition + * @note The setting of these parameters with function is conditioned to ADC state. + * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) + This parameter can be a value of @ref ADC_channels. */ + FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +}ADC_HandleTypeDef; + + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup ADC_Data_align ADC data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT 0x00000000U +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC scan mode + * @{ + */ +/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ +/* compatibility with other STM32 devices having a sequencer with */ +/* additional options. */ +#define ADC_SCAN_DISABLE 0x00000000U +#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) +/** + * @} + */ + +/** @defgroup ADC_channels ADC channels + * @{ + */ +/* Note: Depending on devices, some channels may not be available on package */ +/* pins. Refer to device datasheet for channels availability. */ +#define ADC_CHANNEL_0 0x00000000U +#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) +#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) +#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) +#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) +#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) +#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) +#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) +#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) +#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) +#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) + +#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ +#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC sampling times + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ +#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ +#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ +#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ +#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ +#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_regular_rank ADC rank into regular group + * @{ + */ +#define ADC_REGULAR_RANK_1 0x00000001U +#define ADC_REGULAR_RANK_2 0x00000002U +#define ADC_REGULAR_RANK_3 0x00000003U +#define ADC_REGULAR_RANK_4 0x00000004U +#define ADC_REGULAR_RANK_5 0x00000005U +#define ADC_REGULAR_RANK_6 0x00000006U +#define ADC_REGULAR_RANK_7 0x00000007U +#define ADC_REGULAR_RANK_8 0x00000008U +#define ADC_REGULAR_RANK_9 0x00000009U +#define ADC_REGULAR_RANK_10 0x0000000AU +#define ADC_REGULAR_RANK_11 0x0000000BU +#define ADC_REGULAR_RANK_12 0x0000000CU +#define ADC_REGULAR_RANK_13 0x0000000DU +#define ADC_REGULAR_RANK_14 0x0000000EU +#define ADC_REGULAR_RANK_15 0x0000000FU +#define ADC_REGULAR_RANK_16 0x00000010U +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE 0x00000000U +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +/** + * @} + */ + +/** @defgroup ADC_conversion_group ADC conversion group + * @{ + */ +#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) +#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) +#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ + +#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ +#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ +#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ +#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ +#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ +/** + * @} + */ + + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/** @defgroup ADC_conversion_cycles ADC conversion cycles + * @{ + */ +/* ADC conversion cycles (unit: ADC clock cycles) */ +/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ +/* resolution 12 bits) */ +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U +/** + * @} + */ + +/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels + * @{ + */ +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ + (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ + ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ + ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ + (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ + ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) + +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ + (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ + ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ + ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ + (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ + ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) + +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ + (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ + ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ + ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ + (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ + ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) + +#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U +#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) +#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) +#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) +#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) +#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) +#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) +#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) + +#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U +#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) +#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) +#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) +#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) +#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) +#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) +#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) +/** + * @} + */ + +/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Enable the ADC peripheral + * @note ADC enable requires a delay for ADC stabilization time + * (refer to device datasheet, parameter tSTAB) + * @note On STM32F1, if ADC is already enabled this macro trigs a conversion + * SW start on regular group. + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) \ + (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) + +/** + * @brief Disable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) + +/** @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) + +/** @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC interrupt source to check + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @retval None + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Get the selected ADC's flag status. + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_STRT: ADC Regular group start flag + * @arg ADC_FLAG_JSTRT: ADC Injected group start flag + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the ADC's pending flags + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_STRT: ADC Regular group start flag + * @arg ADC_FLAG_JSTRT: ADC Injected group start flag + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) + +/** @brief Reset ADC handle state + * @param __HANDLE__: ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif + +/** + * @} + */ + +/* Private macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__: ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** + * @brief Set ADC number of conversions into regular channel sequence length. + * @param _NbrOfConversion_: Regular channel sequence length + * @retval None + */ +#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ + (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 16. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) + +/** + * @brief Set the injected sequence length. + * @param _JSQR_JL_: Sequence length. + * @retval None + */ +#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ + (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) + +/** + * @brief Set the selected injected channel rank + * Note: on STM32F1 devices, channel rank position in JSQR register + * is depending on total number of ranks selected into + * injected sequencer (ranks sequence starting from 4-JL) + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @param _JSQR_JL_: Sequence length. + * @retval None + */ +#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ + ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_: Continuous mode. + * @retval None + */ +#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. + * @retval None + */ +#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ + (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_: Scan conversion mode. + * @retval None + */ +/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ +/* is equivalent to ADC_SCAN_ENABLE. */ +#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ + (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ + )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ + ) + +/** + * @brief Get the maximum ADC conversion cycles on all channels. + * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) + * Approximation of sampling time within 4 ranges, returns the highest value: + * below 7.5 cycles {1.5 cycle; 7.5 cycles}, + * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} + * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} + * equal to 239.5 cycles + * Unit: ADC clock cycles + * @param __HANDLE__: ADC handle + * @retval ADC conversion cycles on all channels + */ +#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ + (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ + \ + (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ + ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ + : \ + ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ + ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ + ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ + ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) + +#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_10) || \ + ((CHANNEL) == ADC_REGULAR_RANK_11) || \ + ((CHANNEL) == ADC_REGULAR_RANK_12) || \ + ((CHANNEL) == ADC_REGULAR_RANK_13) || \ + ((CHANNEL) == ADC_REGULAR_RANK_14) || \ + ((CHANNEL) == ADC_REGULAR_RANK_15) || \ + ((CHANNEL) == ADC_REGULAR_RANK_16) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + +#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ + ((CONVERSION) == ADC_INJECTED_GROUP) || \ + ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) + +#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) + + +/** @defgroup ADC_range_verification ADC range verification + * For a unique ADC resolution: 12 bits + * @{ + */ +#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) +/** + * @} + */ + +/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification + * @{ + */ +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification + * @{ + */ +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f1xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ + + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* IO operation functions *****************************************************/ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ + + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/* Internal HAL driver functions **********************************************/ +/** @addtogroup ADC_Private_Functions + * @{ + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); +void ADC_StabilizationTime(uint32_t DelayUs); +void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_ADC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h index 8133fd6..9e66a2e 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h @@ -1,710 +1,706 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_adc_ex.h - * @author MCD Application Team - * @brief Header file of ADC HAL extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_ADC_EX_H -#define __STM32F1xx_HAL_ADC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Types ADCEx Exported Types - * @{ - */ - -/** - * @brief ADC Configuration injected Channel structure definition - * @note Parameters of this structure are shared within 2 scopes: - * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset - * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, - * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. - * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') - * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. - */ -typedef struct -{ - uint32_t InjectedChannel; /*!< Selection of ADC channel to configure - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. - Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) - Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. - It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. - Refer to errata sheet of these devices for more details. */ - uint32_t InjectedRank; /*!< Rank in the injected group sequencer - This parameter must be a value of @ref ADCEx_injected_rank - Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ - uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ - uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). - Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), - this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. - To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. - Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one - This parameter can be set to ENABLE or DISABLE. - Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) - Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) - Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. - To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. - If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. - This parameter can be a value of @ref ADCEx_External_trigger_source_Injected - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** - * @brief Structure definition of ADC multimode - * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). - * State of ADCs of the common group must be: disabled. - */ -typedef struct -{ - uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. - This parameter can be a value of @ref ADCEx_Common_mode - Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. - Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. - Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. - Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). - The equivalences are: - - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ - - -}ADC_MultiModeTypeDef; -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants - * @{ - */ - -/** @defgroup ADCEx_injected_rank ADCEx rank into injected group - * @{ - */ -#define ADC_INJECTED_RANK_1 0x00000001U -#define ADC_INJECTED_RANK_2 0x00000002U -#define ADC_INJECTED_RANK_3 0x00000003U -#define ADC_INJECTED_RANK_4 0x00000004U -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group - * @{ - */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group - * @{ - */ -/*!< List of external triggers with generic trigger name, independently of */ -/* ADC target, sorted by trigger name: */ - -/*!< External triggers of regular group for ADC1&ADC2 only */ -#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 -#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 -#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 -#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO -#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 -#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 - -#if defined (STM32F103xE) || defined (STM32F103xG) -/*!< External triggers of regular group for ADC3 only */ -#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 -#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 -#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 -#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 -#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 -#endif /* STM32F103xE || defined STM32F103xG */ - -/*!< External triggers of regular group for all ADC instances */ -#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 - -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) -/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -/* To use it on ADC or ADC2, a remap of trigger must be done from */ -/* EXTI line 11 to TIM8_TRGO with macro: */ -/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ -/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ - -/* Note for internal constant value management: If TIM8_TRGO is available, */ -/* its definition is set to value for ADC1&ADC2 by default and changed to */ -/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ -#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO -#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#define ADC_SOFTWARE_START ADC1_2_3_SWSTART -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group - * @{ - */ -/*!< List of external triggers with generic trigger name, independently of */ -/* ADC target, sorted by trigger name: */ - -/*!< External triggers of injected group for ADC1&ADC2 only */ -#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 -#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 -#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO -#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 - -#if defined (STM32F103xE) || defined (STM32F103xG) -/*!< External triggers of injected group for ADC3 only */ -#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 -#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 -#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 -#endif /* STM32F103xE || defined STM32F103xG */ - -/*!< External triggers of injected group for all ADC instances */ -#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 -#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO - -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) -/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -/* To use it on ADC1 or ADC2, a remap of trigger must be done from */ -/* EXTI line 11 to TIM8_CC4 with macro: */ -/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ -/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ - -/* Note for internal constant value management: If TIM8_CC4 is available, */ -/* its definition is set to value for ADC1&ADC2 by default and changed to */ -/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ -#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 -#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART -/** - * @} - */ - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode - * @{ - */ -#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ -#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ -#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ -#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ -#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ -#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ -#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ -#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ -/** - * @} - */ -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants - * @{ - */ - -/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group - * @{ - */ -/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ -/* instance is available on the selected device). */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ - -/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U -#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) -#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) -#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) -#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) -/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 -#endif - -#if defined (STM32F103xE) || defined (STM32F103xG) -/* External triggers of regular group for ADC3 */ -#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 -#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 -#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 -#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO -#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 -#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 -#endif - -/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ -#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) -#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -/** - * @} - */ - -/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group - * @{ - */ -/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ -/* instance is available on the selected device). */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ - -/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ -#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) -#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) -#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) -#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) -/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 -#endif - -#if defined (STM32F103xE) || defined (STM32F103xG) -/* External triggers of injected group for ADC3 */ -#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO -#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 -#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 -#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO -#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 -#endif /* STM32F103xE || defined STM32F103xG */ - -/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ -#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U -#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) -#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Macro ADCEx Private Macro - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - - -/** - * @brief For devices with 3 ADCs: Defines the external trigger source - * for regular group according to ADC into common group ADC1&ADC2 or - * ADC3 (some triggers with same source have different value to - * be programmed into ADC EXTSEL bits of CR2 register). - * For devices with 2 ADCs or less: this macro makes no change. - * @param __HANDLE__: ADC handle - * @param __EXT_TRIG_CONV__: External trigger selected for regular group. - * @retval External trigger to be programmed into EXTSEL bits of CR2 register - */ -#if defined (STM32F103xE) || defined (STM32F103xG) -#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ - (( (((__HANDLE__)->Instance) == ADC3) \ - )? \ - ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ - )? \ - (ADC3_EXTERNALTRIG_T8_TRGO) \ - : \ - (__EXT_TRIG_CONV__) \ - ) \ - : \ - (__EXT_TRIG_CONV__) \ - ) -#else -#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ - (__EXT_TRIG_CONV__) -#endif /* STM32F103xE || STM32F103xG */ - -/** - * @brief For devices with 3 ADCs: Defines the external trigger source - * for injected group according to ADC into common group ADC1&ADC2 or - * ADC3 (some triggers with same source have different value to - * be programmed into ADC JEXTSEL bits of CR2 register). - * For devices with 2 ADCs or less: this macro makes no change. - * @param __HANDLE__: ADC handle - * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. - * @retval External trigger to be programmed into JEXTSEL bits of CR2 register - */ -#if defined (STM32F103xE) || defined (STM32F103xG) -#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ - (( (((__HANDLE__)->Instance) == ADC3) \ - )? \ - ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ - )? \ - (ADC3_EXTERNALTRIGINJEC_T8_CC4) \ - : \ - (__EXT_TRIG_INJECTCONV__) \ - ) \ - : \ - (__EXT_TRIG_INJECTCONV__) \ - ) -#else -#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ - (__EXT_TRIG_INJECTCONV__) -#endif /* STM32F103xE || STM32F103xG */ - - -/** - * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) - * @param __HANDLE__: ADC handle - * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled - */ -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ - (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ - )? \ - (ADC1->CR1 & ADC_CR1_DUALMOD) \ - : \ - (RESET) \ - ) -#else -#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ - (RESET) -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) - * @param __HANDLE__: ADC handle - * @retval None - */ -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ - (( (((__HANDLE__)->Instance) == ADC2) \ - )? \ - ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \ - : \ - (!RESET) \ - ) -#else -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ - (!RESET) -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) - * @param __HANDLE__: ADC handle - * @retval None - */ -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ - (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ - )? \ - (ADC1->CR1 & ADC_CR1_JAUTO) \ - : \ - (RESET) \ - ) -#else -#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ - (RESET) -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** - * @brief Set handle of the other ADC sharing the common multimode settings - * @param __HANDLE__: ADC handle - * @param __HANDLE_OTHER_ADC__: other ADC handle - * @retval None - */ -#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ - ((__HANDLE_OTHER_ADC__)->Instance = ADC2) - -/** - * @brief Set handle of the ADC slave associated to the ADC master - * On STM32F1 devices, ADC slave is always ADC2 (this can be different - * on other STM32 devices) - * @param __HANDLE_MASTER__: ADC master handle - * @param __HANDLE_SLAVE__: ADC slave handle - * @retval None - */ -#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ - ((__HANDLE_SLAVE__)->Instance = ADC2) - -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ - ((CHANNEL) == ADC_INJECTED_RANK_2) || \ - ((CHANNEL) == ADC_INJECTED_RANK_3) || \ - ((CHANNEL) == ADC_INJECTED_RANK_4)) - -#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) - -/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification - * @{ - */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) -/** - * @} - */ - -#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif -#if defined (STM32F101xE) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif -#if defined (STM32F101xG) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif -#if defined (STM32F103xE) || defined (STM32F103xG) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif - -#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) -#endif -#if defined (STM32F101xE) -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) -#endif -#if defined (STM32F101xG) -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) -#endif -#if defined (STM32F103xE) || defined (STM32F103xG) -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) -#endif - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ - ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ - ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ - ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \ - ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \ - ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ - ((MODE) == ADC_DUALMODE_REGSIMULT) || \ - ((MODE) == ADC_DUALMODE_INTERLFAST) || \ - ((MODE) == ADC_DUALMODE_INTERLSLOW) || \ - ((MODE) == ADC_DUALMODE_ALTERTRIG) ) -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @} - */ - - - - - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ - -/* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); -/** - * @} - */ - - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup ADCEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_ADC_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_ADC_EX_H +#define __STM32F1xx_HAL_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADCEx Exported Types + * @{ + */ + +/** + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') + * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. + Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) + Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. + It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. + Refer to errata sheet of these devices for more details. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ +}ADC_InjectionConfTypeDef; + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** + * @brief Structure definition of ADC multimode + * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). + * State of ADCs of the common group must be: disabled. + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. + This parameter can be a value of @ref ADCEx_Common_mode + Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. + Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. + Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. + Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). + The equivalences are: + - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. + - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ + + +}ADC_MultiModeTypeDef; +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants + * @{ + */ + +/** @defgroup ADCEx_injected_rank ADCEx rank into injected group + * @{ + */ +#define ADC_INJECTED_RANK_1 0x00000001U +#define ADC_INJECTED_RANK_2 0x00000002U +#define ADC_INJECTED_RANK_3 0x00000003U +#define ADC_INJECTED_RANK_4 0x00000004U +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group + * @{ + */ +/*!< List of external triggers with generic trigger name, independently of */ +/* ADC target, sorted by trigger name: */ + +/*!< External triggers of regular group for ADC1&ADC2 only */ +#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 +#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 +#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 +#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO +#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 +#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 + +#if defined (STM32F103xE) || defined (STM32F103xG) +/*!< External triggers of regular group for ADC3 only */ +#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 +#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 +#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 +#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 +#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 +#endif /* STM32F103xE || defined STM32F103xG */ + +/*!< External triggers of regular group for all ADC instances */ +#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 + +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* To use it on ADC or ADC2, a remap of trigger must be done from */ +/* EXTI line 11 to TIM8_TRGO with macro: */ +/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ +/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ + +/* Note for internal constant value management: If TIM8_TRGO is available, */ +/* its definition is set to value for ADC1&ADC2 by default and changed to */ +/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ +#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#define ADC_SOFTWARE_START ADC1_2_3_SWSTART +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group + * @{ + */ +/*!< List of external triggers with generic trigger name, independently of */ +/* ADC target, sorted by trigger name: */ + +/*!< External triggers of injected group for ADC1&ADC2 only */ +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 +#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 +#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO +#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 + +#if defined (STM32F103xE) || defined (STM32F103xG) +/*!< External triggers of injected group for ADC3 only */ +#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 +#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 +#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 +#endif /* STM32F103xE || defined STM32F103xG */ + +/*!< External triggers of injected group for all ADC instances */ +#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO + +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* To use it on ADC1 or ADC2, a remap of trigger must be done from */ +/* EXTI line 11 to TIM8_CC4 with macro: */ +/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ +/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ + +/* Note for internal constant value management: If TIM8_CC4 is available, */ +/* its definition is set to value for ADC1&ADC2 by default and changed to */ +/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ +#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART +/** + * @} + */ + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ +#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ +#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ +#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ +#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ +#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ +#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ +#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ +/** + * @} + */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + +/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group + * @{ + */ +/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ +/* instance is available on the selected device). */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ + +/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ +#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U +#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) +#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) +/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 +#endif + +#if defined (STM32F103xE) || defined (STM32F103xG) +/* External triggers of regular group for ADC3 */ +#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 +#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 +#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 +#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO +#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 +#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 +#endif + +/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ +#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) +#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +/** + * @} + */ + +/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group + * @{ + */ +/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ +/* instance is available on the selected device). */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ + +/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ +#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) +#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) +#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) +/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 +#endif + +#if defined (STM32F103xE) || defined (STM32F103xG) +/* External triggers of injected group for ADC3 */ +#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO +#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 +#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 +#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO +#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 +#endif /* STM32F103xE || defined STM32F103xG */ + +/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ +#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U +#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) +#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro ADCEx Private Macro + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + + +/** + * @brief For devices with 3 ADCs: Defines the external trigger source + * for regular group according to ADC into common group ADC1&ADC2 or + * ADC3 (some triggers with same source have different value to + * be programmed into ADC EXTSEL bits of CR2 register). + * For devices with 2 ADCs or less: this macro makes no change. + * @param __HANDLE__: ADC handle + * @param __EXT_TRIG_CONV__: External trigger selected for regular group. + * @retval External trigger to be programmed into EXTSEL bits of CR2 register + */ +#if defined (STM32F103xE) || defined (STM32F103xG) +#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ + (( (((__HANDLE__)->Instance) == ADC3) \ + )? \ + ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ + )? \ + (ADC3_EXTERNALTRIG_T8_TRGO) \ + : \ + (__EXT_TRIG_CONV__) \ + ) \ + : \ + (__EXT_TRIG_CONV__) \ + ) +#else +#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ + (__EXT_TRIG_CONV__) +#endif /* STM32F103xE || STM32F103xG */ + +/** + * @brief For devices with 3 ADCs: Defines the external trigger source + * for injected group according to ADC into common group ADC1&ADC2 or + * ADC3 (some triggers with same source have different value to + * be programmed into ADC JEXTSEL bits of CR2 register). + * For devices with 2 ADCs or less: this macro makes no change. + * @param __HANDLE__: ADC handle + * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. + * @retval External trigger to be programmed into JEXTSEL bits of CR2 register + */ +#if defined (STM32F103xE) || defined (STM32F103xG) +#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ + (( (((__HANDLE__)->Instance) == ADC3) \ + )? \ + ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ + )? \ + (ADC3_EXTERNALTRIGINJEC_T8_CC4) \ + : \ + (__EXT_TRIG_INJECTCONV__) \ + ) \ + : \ + (__EXT_TRIG_INJECTCONV__) \ + ) +#else +#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ + (__EXT_TRIG_INJECTCONV__) +#endif /* STM32F103xE || STM32F103xG */ + + +/** + * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) + * @param __HANDLE__: ADC handle + * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled + */ +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ + (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ + )? \ + (ADC1->CR1 & ADC_CR1_DUALMOD) \ + : \ + (RESET) \ + ) +#else +#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ + (RESET) +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) + * @param __HANDLE__: ADC handle + * @retval None + */ +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ + (( (((__HANDLE__)->Instance) == ADC2) \ + )? \ + ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \ + : \ + (!RESET) \ + ) +#else +#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ + (!RESET) +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) + * @param __HANDLE__: ADC handle + * @retval None + */ +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ + (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ + )? \ + (ADC1->CR1 & ADC_CR1_JAUTO) \ + : \ + (RESET) \ + ) +#else +#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ + (RESET) +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** + * @brief Set handle of the other ADC sharing the common multimode settings + * @param __HANDLE__: ADC handle + * @param __HANDLE_OTHER_ADC__: other ADC handle + * @retval None + */ +#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ + ((__HANDLE_OTHER_ADC__)->Instance = ADC2) + +/** + * @brief Set handle of the ADC slave associated to the ADC master + * On STM32F1 devices, ADC slave is always ADC2 (this can be different + * on other STM32 devices) + * @param __HANDLE_MASTER__: ADC master handle + * @param __HANDLE_SLAVE__: ADC slave handle + * @retval None + */ +#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ + ((__HANDLE_SLAVE__)->Instance = ADC2) + +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ + ((CHANNEL) == ADC_INJECTED_RANK_2) || \ + ((CHANNEL) == ADC_INJECTED_RANK_3) || \ + ((CHANNEL) == ADC_INJECTED_RANK_4)) + +#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) + +/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification + * @{ + */ +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) +/** + * @} + */ + +#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif +#if defined (STM32F101xE) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif +#if defined (STM32F101xG) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif +#if defined (STM32F103xE) || defined (STM32F103xG) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif + +#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) +#endif +#if defined (STM32F101xE) +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) +#endif +#if defined (STM32F101xG) +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) +#endif +#if defined (STM32F103xE) || defined (STM32F103xG) +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) +#endif + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \ + ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \ + ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT) || \ + ((MODE) == ADC_DUALMODE_INTERLFAST) || \ + ((MODE) == ADC_DUALMODE_INTERLSLOW) || \ + ((MODE) == ADC_DUALMODE_ALTERTRIG) ) +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @} + */ + + + + + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/* ADC multimode */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_ADC_EX_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h index 341c044..db8cc92 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h @@ -1,850 +1,859 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_can.h - * @author MCD Application Team - * @brief Header file of CAN HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F1xx_HAL_CAN_H -#define STM32F1xx_HAL_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -#if defined (CAN1) -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CAN_Exported_Types CAN Exported Types - * @{ - */ -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ - HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ - HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ - HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ - -} HAL_CAN_StateTypeDef; - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware - is allowed to lengthen or shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE. */ - -} CAN_InitTypeDef; - -/** - * @brief CAN filter configuration structure definition - */ -typedef struct -{ - uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. - For single CAN instance(14 dedicated filter banks), - this parameter must be a number between Min_Data = 0 and Max_Data = 13. - For dual CAN instances(28 filter banks shared), - this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ - - uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint32_t FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be a value of @ref CAN_filter_activation */ - - uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. - For single CAN instances, this parameter is meaningless. - For dual CAN instances, all filter banks with lower index are assigned to master - CAN instance, whereas all filter banks with greater index are assigned to slave - CAN instance. - This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ - -} CAN_FilterTypeDef; - -/** - * @brief CAN Tx message header structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - - FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start - of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. - @note: Time Triggered Communication Mode must be enabled. - @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. - This parameter can be set to ENABLE or DISABLE. */ - -} CAN_TxHeaderTypeDef; - -/** - * @brief CAN Rx message header structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - - uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. - @note: Time Triggered Communication Mode must be enabled. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - - uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - -} CAN_RxHeaderTypeDef; - -/** - * @brief CAN handle Structure definition - */ -typedef struct __CAN_HandleTypeDef -{ - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - __IO uint32_t ErrorCode; /*!< CAN Error code. - This parameter can be a value of @ref CAN_Error_Code */ - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ - void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ - void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ - void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ - void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ - void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ - void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ - void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ - void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ - void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ - void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ - void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ - void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ - - void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ - void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ - -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ -} CAN_HandleTypeDef; - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/** - * @brief HAL CAN common Callback ID enumeration definition - */ -typedef enum -{ - HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ - HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ - HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ - HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ - HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ - HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ - HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ - HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ - HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ - HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ - HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ - HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ - HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ - - HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ - HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ - -} HAL_CAN_CallbackIDTypeDef; - -/** - * @brief HAL CAN Callback pointer definition - */ -typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ - -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants CAN Exported Constants - * @{ - */ - -/** @defgroup CAN_Error_Code CAN Error Code - * @{ - */ -#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ -#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ -#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ -#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ -#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ -#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ -#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ -#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ -#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ -#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ -#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ -#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ -#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ -#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ -#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ - -/** - * @} - */ - -/** @defgroup CAN_InitStatus CAN InitStatus - * @{ - */ -#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ -/** - * @} - */ - -/** @defgroup CAN_operating_mode CAN Operating Mode - * @{ - */ -#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ -#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ -#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ -/** - * @} - */ - - -/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width - * @{ - */ -#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ -#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ -#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 - * @{ - */ -#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ -#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ -#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ -#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ -#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ -#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ -#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ -#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ -#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ -#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ -#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ -#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ -#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ -#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ -#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 - * @{ - */ -#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ -#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ -#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ -#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ -#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ -#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ -#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode CAN Filter Mode - * @{ - */ -#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ -/** - * @} - */ - -/** @defgroup CAN_filter_scale CAN Filter Scale - * @{ - */ -#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ -/** - * @} - */ - -/** @defgroup CAN_filter_activation CAN Filter Activation - * @{ - */ -#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ -#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO CAN Filter FIFO - * @{ - */ -#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ -/** - * @} - */ - -/** @defgroup CAN_identifier_type CAN Identifier Type - * @{ - */ -#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ -#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request - * @{ - */ -#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ -#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number - * @{ - */ -#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ -#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ -/** - * @} - */ - -/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes - * @{ - */ -#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ -#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ -#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ -/** - * @} - */ - -/** @defgroup CAN_flags CAN Flags - * @{ - */ -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ -#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ -#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ -#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ -#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ -#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ -#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ -#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ -#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ -#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ -#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ -#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ -#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ -#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ -#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ -#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ -#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ - -/* Receive Flags */ -#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ -#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ -#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ -#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ - -/* Error Flags */ -#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ -#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ -#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ -/** - * @} - */ - - -/** @defgroup CAN_Interrupts CAN Interrupts - * @{ - */ -/* Transmit Interrupt */ -#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ - -/* Receive Interrupts */ -#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ - -/* Operating Mode Interrupts */ -#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ - -/* Error Interrupts */ -#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macros CAN Exported Macros - * @{ - */ - -/** @brief Reset CAN handle state - * @param __HANDLE__ CAN handle. - * @retval None - */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) -#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ - -/** - * @brief Enable the specified CAN interrupts. - * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt sources to enable. - * This parameter can be any combination of @arg CAN_Interrupts - * @retval None - */ -#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable the specified CAN interrupts. - * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt sources to disable. - * This parameter can be any combination of @arg CAN_Interrupts - * @retval None - */ -#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the CAN Handle. - * @param __INTERRUPT__ specifies the CAN interrupt source to check. - * This parameter can be a value of @arg CAN_Interrupts - * @retval The state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) - -/** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__ specifies the CAN Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of @arg CAN_flags - * @retval The state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) - -/** @brief Clear the specified CAN pending flag. - * @param __HANDLE__ specifies the CAN Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag - * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag - * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag - * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag - * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag - * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag - * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag - * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag - * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag - * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag - * @retval None - */ -#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); -HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); - -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions - * @{ - */ - -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * @{ - */ - -/* Control functions **********************************************************/ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); -HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * @{ - */ -/* Interrupts management ******************************************************/ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); -HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group5 Callback functions - * @brief Callback functions - * @{ - */ -/* Callbacks functions ********************************************************/ - -void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup CAN_Private_Types CAN Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Variables CAN Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_FLAG_MASK (0x000000FFU) -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ - ((MODE) == CAN_MODE_LOOPBACK)|| \ - ((MODE) == CAN_MODE_SILENT) || \ - ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ - ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ - ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ - ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ - ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ - ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ - ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ - ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ - ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) -#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ - ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ - ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ - ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) -#if defined(CAN2) -#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) -#endif -#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ - ((MODE) == CAN_FILTERMODE_IDLIST)) -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ - ((SCALE) == CAN_FILTERSCALE_32BIT)) -#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ - ((ACTIVATION) == CAN_FILTER_ENABLE)) -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ - ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ - ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ - ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) -#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) -#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= 8U) -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ - ((IDTYPE) == CAN_ID_EXT)) -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) -#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ - CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ - CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ - CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ - CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ - CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ - CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/** - * @} - */ - - -#endif /* CAN1 */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F1xx_HAL_CAN_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_CAN_H +#define STM32F1xx_HAL_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#if defined (CAN1) +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + +} CAN_FilterTypeDef; + +/** + * @brief CAN Tx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ + + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +} CAN_HandleTypeDef; + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number + * @{ + */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#if defined(CAN2) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#endif +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + + +#endif /* CAN1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_CAN_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h index ce96197..7cfefbd 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h @@ -1,410 +1,410 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_CORTEX_H -#define __STM32F1xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types Cortex Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1U) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U -#define SYSTICK_CLKSOURCE_HCLK 0x00000004U - -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U -#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk -#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk -#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) - -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); - -#if (__MPU_PRESENT == 1U) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1U) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CORTEX_H +#define __STM32F1xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_CORTEX_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h new file mode 100755 index 0000000..bf177e4 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_crc.h @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_CRC_H +#define STM32F1xx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_CRC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h index 6ff1109..d4d98f7 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -1,210 +1,211 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_DEF -#define __STM32F1xx_HAL_DEF - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" -#include "Legacy/stm32_hal_legacy.h" -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0U) - -#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ - -/** @brief Reset the Handle's State field. - * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) - -#if (USE_RTOS == 1U) -/* Reserved for future use */ -#error "USE_RTOS should be 0 in the current HAL release" -#else -#define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0U) - -#define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0U) -#endif /* USE_RTOS */ - -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ -#ifndef __weak -#define __weak __attribute__((weak)) -#endif -#ifndef __packed -#define __packed __attribute__((packed)) -#endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ -#ifndef __ALIGN_BEGIN -#define __ALIGN_BEGIN -#endif -#ifndef __ALIGN_END -#define __ALIGN_END __attribute__ ((aligned (4))) -#endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ -#ifndef __ALIGN_END -#define __ALIGN_END __attribute__ ((aligned (4))) -#endif /* __ALIGN_END */ -#ifndef __ALIGN_BEGIN -#define __ALIGN_BEGIN -#endif /* __ALIGN_BEGIN */ -#else -#ifndef __ALIGN_END -#define __ALIGN_END -#endif /* __ALIGN_END */ -#ifndef __ALIGN_BEGIN -#if defined (__CC_ARM) /* ARM Compiler V5*/ -#define __ALIGN_BEGIN __align(4) -#elif defined (__ICCARM__) /* IAR Compiler */ -#define __ALIGN_BEGIN -#endif /* __CC_ARM */ -#endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -/* ARM Compiler V4/V5 and V6 - -------------------------- - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) -/* ARM V4/V5 and V6 & GNU Compiler - ------------------------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F1xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DEF +#define __STM32F1xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error "USE_RTOS should be 0 in the current HAL release" +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler V5*/ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F1xx_HAL_DEF */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h index 7b2304d..2eff9ac 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h @@ -1,457 +1,455 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_DMA_H -#define __STM32F1xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ - -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ - -} DMA_HandleTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ -#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ - -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL 0x00000000U /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ -#define DMA_FLAG_GL1 0x00000001U -#define DMA_FLAG_TC1 0x00000002U -#define DMA_FLAG_HT1 0x00000004U -#define DMA_FLAG_TE1 0x00000008U -#define DMA_FLAG_GL2 0x00000010U -#define DMA_FLAG_TC2 0x00000020U -#define DMA_FLAG_HT2 0x00000040U -#define DMA_FLAG_TE2 0x00000080U -#define DMA_FLAG_GL3 0x00000100U -#define DMA_FLAG_TC3 0x00000200U -#define DMA_FLAG_HT3 0x00000400U -#define DMA_FLAG_TE3 0x00000800U -#define DMA_FLAG_GL4 0x00001000U -#define DMA_FLAG_TC4 0x00002000U -#define DMA_FLAG_HT4 0x00004000U -#define DMA_FLAG_TE4 0x00008000U -#define DMA_FLAG_GL5 0x00010000U -#define DMA_FLAG_TC5 0x00020000U -#define DMA_FLAG_HT5 0x00040000U -#define DMA_FLAG_TE5 0x00080000U -#define DMA_FLAG_GL6 0x00100000U -#define DMA_FLAG_TC6 0x00200000U -#define DMA_FLAG_HT6 0x00400000U -#define DMA_FLAG_TE6 0x00800000U -#define DMA_FLAG_GL7 0x01000000U -#define DMA_FLAG_TC7 0x02000000U -#define DMA_FLAG_HT7 0x04000000U -#define DMA_FLAG_TE7 0x08000000U -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) - - -/* Interrupt & Flag management */ - -/** - * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) - -/** - * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) - -/** - * @brief Check whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Return the number of remaining data units in the current DMA Channel transfer. - * @param __HANDLE__: DMA handle - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -/** - * @} - */ - -/* Include DMA HAL Extension module */ -#include "stm32f1xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_H +#define __STM32F1xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ +#define DMA_FLAG_GL1 0x00000001U +#define DMA_FLAG_TC1 0x00000002U +#define DMA_FLAG_HT1 0x00000004U +#define DMA_FLAG_TE1 0x00000008U +#define DMA_FLAG_GL2 0x00000010U +#define DMA_FLAG_TC2 0x00000020U +#define DMA_FLAG_HT2 0x00000040U +#define DMA_FLAG_TE2 0x00000080U +#define DMA_FLAG_GL3 0x00000100U +#define DMA_FLAG_TC3 0x00000200U +#define DMA_FLAG_HT3 0x00000400U +#define DMA_FLAG_TE3 0x00000800U +#define DMA_FLAG_GL4 0x00001000U +#define DMA_FLAG_TC4 0x00002000U +#define DMA_FLAG_HT4 0x00004000U +#define DMA_FLAG_TE4 0x00008000U +#define DMA_FLAG_GL5 0x00010000U +#define DMA_FLAG_TC5 0x00020000U +#define DMA_FLAG_HT5 0x00040000U +#define DMA_FLAG_TE5 0x00080000U +#define DMA_FLAG_GL6 0x00100000U +#define DMA_FLAG_TC6 0x00200000U +#define DMA_FLAG_HT6 0x00400000U +#define DMA_FLAG_TE6 0x00800000U +#define DMA_FLAG_GL7 0x01000000U +#define DMA_FLAG_TC7 0x02000000U +#define DMA_FLAG_HT7 0x04000000U +#define DMA_FLAG_TE7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Return the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__: DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f1xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_DMA_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h index d861f50..ce31cff 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h @@ -1,277 +1,275 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_DMA_EX_H -#define __STM32F1xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros - * @{ - */ -/* Interrupt & Flag management */ -#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ - defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) -/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices - * @{ - */ - -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ - DMA_FLAG_GL5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ - (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ - (DMA1->IFCR = (__FLAG__))) - -/** - * @} - */ - -#else -/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices - * @{ - */ - -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - DMA_FLAG_GL7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -/** - * @} - */ - -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ - /* STM32F103xG || STM32F105xC || STM32F107xC */ - -#endif /* __STM32F1xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_EX_H +#define __STM32F1xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros + * @{ + */ +/* Interrupt & Flag management */ +#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ + defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +/** + * @} + */ + +#else +/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ + /* STM32F103xG || STM32F105xC || STM32F107xC */ + +#endif /* __STM32F1xx_HAL_DMA_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h index e42e8c0..14baf44 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h @@ -1,320 +1,318 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_exti.h - * @author MCD Application Team - * @brief Header file of EXTI HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F1xx_HAL_EXTI_H -#define STM32F1xx_HAL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup EXTI EXTI - * @brief EXTI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Types EXTI Exported Types - * @{ - */ - -/** - * @brief HAL EXTI common Callback ID enumeration definition - */ -typedef enum -{ - HAL_EXTI_COMMON_CB_ID = 0x00U -} EXTI_CallbackIDTypeDef; - -/** - * @brief EXTI Handle structure definition - */ -typedef struct -{ - uint32_t Line; /*!< Exti line number */ - void (* PendingCallback)(void); /*!< Exti pending callback */ -} EXTI_HandleTypeDef; - -/** - * @brief EXTI Configuration structure definition - */ -typedef struct -{ - uint32_t Line; /*!< The Exti line to be configured. This parameter - can be a value of @ref EXTI_Line */ - uint32_t Mode; /*!< The Exit Mode to be configured for a core. - This parameter can be a combination of @ref EXTI_Mode */ - uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter - can be a value of @ref EXTI_Trigger */ - uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. - This parameter is only possible for line 0 to 15. It - can be a value of @ref EXTI_GPIOSel */ -} EXTI_ConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_Line EXTI Line - * @{ - */ -#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ -#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ -#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ -#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ -#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ -#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ -#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ -#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ -#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ -#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ -#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ -#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ -#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ -#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ -#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ -#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ -#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#if defined(EXTI_IMR_IM18) -#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ -#endif /* EXTI_IMR_IM18 */ -#if defined(EXTI_IMR_IM19) -#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#endif /* EXTI_IMR_IM19 */ - -/** - * @} - */ - -/** @defgroup EXTI_Mode EXTI Mode - * @{ - */ -#define EXTI_MODE_NONE 0x00000000u -#define EXTI_MODE_INTERRUPT 0x00000001u -#define EXTI_MODE_EVENT 0x00000002u -/** - * @} - */ - -/** @defgroup EXTI_Trigger EXTI Trigger - * @{ - */ -#define EXTI_TRIGGER_NONE 0x00000000u -#define EXTI_TRIGGER_RISING 0x00000001u -#define EXTI_TRIGGER_FALLING 0x00000002u -#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) -/** - * @} - */ - -/** @defgroup EXTI_GPIOSel EXTI GPIOSel - * @brief - * @{ - */ -#define EXTI_GPIOA 0x00000000u -#define EXTI_GPIOB 0x00000001u -#define EXTI_GPIOC 0x00000002u -#define EXTI_GPIOD 0x00000003u -#if defined (GPIOE) -#define EXTI_GPIOE 0x00000004u -#endif /* GPIOE */ -#if defined (GPIOF) -#define EXTI_GPIOF 0x00000005u -#endif /* GPIOF */ -#if defined (GPIOG) -#define EXTI_GPIOG 0x00000006u -#endif /* GPIOG */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -/** - * @brief EXTI Line property definition - */ -#define EXTI_PROPERTY_SHIFT 24u -#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) - -/** - * @brief EXTI bit usage - */ -#define EXTI_PIN_MASK 0x0000001Fu - -/** - * @brief EXTI Mask for interrupt & event mode - */ -#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) - -/** - * @brief EXTI Mask for trigger possibilities - */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) - -/** - * @brief EXTI Line number - */ -#if defined(EXTI_IMR_IM19) -#define EXTI_LINE_NB 20UL -#elif defined(EXTI_IMR_IM18) -#define EXTI_LINE_NB 19UL -#else /* EXTI_IMR_IM17 */ -#define EXTI_LINE_NB 18UL -#endif /* EXTI_IMR_IM19 */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Macros EXTI Private Macros - * @{ - */ -#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) - -#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) - -#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) - -#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) - -#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) - -#if defined (GPIOG) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG)) -#elif defined (GPIOF) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF)) -#elif defined (GPIOE) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE)) -#else -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD)) -#endif /* GPIOG */ - -#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Functions EXTI Exported Functions - * @brief EXTI Exported Functions - * @{ - */ - -/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions - * @brief Configuration functions - * @{ - */ -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F1xx_HAL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_EXTI_H +#define STM32F1xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ + +/** + * @brief HAL EXTI common Callback ID enumeration definition + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#endif /* EXTI_IMR_IM19 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_NB 20UL +#elif defined(EXTI_IMR_IM18) +#define EXTI_LINE_NB 19UL +#else /* EXTI_IMR_IM17 */ +#define EXTI_LINE_NB 18UL +#endif /* EXTI_IMR_IM19 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG)) +#elif defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#elif defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD)) +#endif /* GPIOG */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_EXTI_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h index 8cd21b1..2479847 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h @@ -1,328 +1,325 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_FLASH_H -#define __STM32F1xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ -/** - * @} - */ - -/** @addtogroup FLASH_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) - -#if defined(FLASH_ACR_LATENCY) -#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ - ((__LATENCY__) == FLASH_LATENCY_1) || \ - ((__LATENCY__) == FLASH_LATENCY_2)) - -#else -#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) -#endif /* FLASH_ACR_LATENCY */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_PAGEERASE = 1U, - FLASH_PROC_MASSERASE = 2U, - FLASH_PROC_PROGRAMHALFWORD = 3U, - FLASH_PROC_PROGRAMWORD = 4U, - FLASH_PROC_PROGRAMDOUBLEWORD = 5U -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ - - __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ - - __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ - - HAL_LockTypeDef Lock; /*!< FLASH locking object */ - - __IO uint32_t ErrorCode; /*!< FLASH error code - This parameter can be a value of @ref FLASH_Error_Codes */ -} FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Codes FLASH Error Codes - * @{ - */ - -#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ -#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ -#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ - -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) - -/** - * @brief Disable the FLASH half cycle access. - * @note half cycle access can only be used with a low-frequency clock of less than - 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. - * @retval None - */ -#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) - -/** - * @} - */ - -#if defined(FLASH_ACR_LATENCY) -/** @defgroup FLASH_EM_Latency FLASH Latency - * @brief macros to handle FLASH Latency - * @{ - */ - -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency - * The value of this parameter depend on device used within the same series - * @retval None - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) - - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @} - */ - -#endif /* FLASH_ACR_LATENCY */ -/** @defgroup FLASH_Prefetch FLASH Prefetch - * @brief macros to handle FLASH Prefetch buffer - * @{ - */ -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32f1xx_hal_flash_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); - -/* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -void HAL_FLASH_OB_Launch(void); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -uint32_t HAL_FLASH_GetError(void); - -/** - * @} - */ - -/** - * @} - */ - -/* Private function -------------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -#if defined(FLASH_BANK2_END) -HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); -#endif /* FLASH_BANK2_END */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_H +#define __STM32F1xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#if defined(FLASH_ACR_LATENCY) +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1) || \ + ((__LATENCY__) == FLASH_LATENCY_2)) + +#else +#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) +#endif /* FLASH_ACR_LATENCY */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) + +/** + * @brief Disable the FLASH half cycle access. + * @note half cycle access can only be used with a low-frequency clock of less than + 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. + * @retval None + */ +#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) + +/** + * @} + */ + +#if defined(FLASH_ACR_LATENCY) +/** @defgroup FLASH_EM_Latency FLASH Latency + * @brief macros to handle FLASH Latency + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +#endif /* FLASH_ACR_LATENCY */ +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f1xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +void HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +#if defined(FLASH_BANK2_END) +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); +#endif /* FLASH_BANK2_END */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h index 1dcaeed..5283526 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h @@ -1,786 +1,783 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of Flash HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_FLASH_EX_H -#define __STM32F1xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/** @addtogroup FLASHEx_Private_Constants - * @{ - */ - -#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U -#define OBR_REG_INDEX 1U -#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) - -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#if defined(FLASH_BANK2_END) -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) -#endif /* FLASH_BANK2_END */ - -/* Low Density */ -#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) -#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ - -/* Medium Density */ -#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) -#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ - -/* High Density */ -#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) -#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ - -/* XL Density */ -#if defined(FLASH_BANK2_END) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) -#endif /* FLASH_BANK2_END */ - -/* Connectivity Line */ -#if (defined(STM32F105xC) || defined(STM32F107xC)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) -#endif /* STM32F105xC || STM32F107xC */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) - -#if defined(FLASH_BANK2_END) -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) -#else -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) -#endif /* FLASH_BANK2_END */ - -/* Low Density */ -#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) - -#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ - -/* Medium Density */ -#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ - ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ - ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) - -#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ - -/* High Density */ -#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ - ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) - -#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ - -/* XL Density */ -#if defined(FLASH_BANK2_END) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ - ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) - -#endif /* FLASH_BANK2_END */ - -/* Connectivity Line */ -#if (defined(STM32F105xC) || defined(STM32F107xC)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ - ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) - -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ - - uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END - (x = 1 or 2 depending on devices)*/ - - uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. - This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Options bytes program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_OB_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_OB_WRP_State */ - - uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected - This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ - - uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. - This parameter must be a value of @ref FLASHEx_Banks */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ - -#if defined(FLASH_BANK2_END) - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: - IWDG / STOP / STDBY / BOOT1 - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, - @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ -#else - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: - IWDG / STOP / STDBY - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, - @ref FLASHEx_OB_nRST_STDBY */ -#endif /* FLASH_BANK2_END */ - - uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed - This parameter can be a value of @ref FLASHEx_OB_Data_Address */ - - uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ -} FLASH_OBProgramInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Constants FLASH Constants - * @{ - */ - -/** @defgroup FLASHEx_Page_Size Page Size - * @{ - */ -#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define FLASH_PAGE_SIZE 0x400U -#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ - /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - -#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) -#define FLASH_PAGE_SIZE 0x800U -#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - /* STM32F101xG || STM32F103xG */ - /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Type_Erase Type Erase - * @{ - */ -#define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ - /* Enable Bank2 IT */ \ - SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ - } while(0U) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 - * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 - * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 - * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ - /* Disable Bank1 IT */ \ - CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ - /* Disable Bank2 IT */ \ - CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ - } while(0U) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 - * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 - * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 - * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 - * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 - * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 - * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 - * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 - * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ - (FLASH->OBR & FLASH_OBR_OPTERR) : \ - ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ - (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ - (FLASH->SR2 & ((__FLAG__) >> 16U)))) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 - * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 - * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 - * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 - * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 - * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 - * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 - * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 - * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ - /* Clear FLASH_FLAG_OPTVERR flag */ \ - if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ - { \ - CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ - } \ - else { \ - /* Clear Flag in Bank1 */ \ - if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ - { \ - FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ - } \ - /* Clear Flag in Bank2 */ \ - if (((__FLAG__) >> 16U) != RESET) \ - { \ - FLASH->SR2 = ((__FLAG__) >> 16U); \ - } \ - } \ - } while(0U) -#else -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @arg @ref FLASH_FLAG_BSY FLASH Busy flag - * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ - (FLASH->OBR & FLASH_OBR_OPTERR) : \ - (FLASH->SR & (__FLAG__))) -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ - /* Clear FLASH_FLAG_OPTVERR flag */ \ - if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ - { \ - CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ - } \ - else { \ - /* Clear Flag in Bank1 */ \ - FLASH->SR = (__FLAG__); \ - } \ - } while(0U) - -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_EX_H +#define __STM32F1xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ + +#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U +#define OBR_REG_INDEX 1U +#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#if defined(FLASH_BANK2_END) +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) +#endif /* STM32F105xC || STM32F107xC */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#if defined(FLASH_BANK2_END) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#else +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) + +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ + ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) + +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ + ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) + +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ + ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) + +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END + (x = 1 or 2 depending on devices)*/ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + +#if defined(FLASH_BANK2_END) + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ +#else + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY */ +#endif /* FLASH_BANK2_END */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Constants FLASH Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size Page Size + * @{ + */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + /* STM32F101xG || STM32F103xG */ + /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Enable Bank2 IT */ \ + SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 + * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 + * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 + * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ + /* Disable Bank1 IT */ \ + CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Disable Bank2 IT */ \ + CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ + (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ + (FLASH->SR2 & ((__FLAG__) >> 16U)))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ + { \ + FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ + } \ + /* Clear Flag in Bank2 */ \ + if (((__FLAG__) >> 16U) != RESET) \ + { \ + FLASH->SR2 = ((__FLAG__) >> 16U); \ + } \ + } \ + } while(0U) +#else +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + (FLASH->SR & (__FLAG__))) +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + FLASH->SR = (__FLAG__); \ + } \ + } while(0U) + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h index 2973944..fb3ecb2 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -305,4 +304,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* STM32F1xx_HAL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h index 56bcb85..430dad5 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -891,4 +890,3 @@ void HAL_GPIOEx_DisableEventout(void); #endif /* STM32F1xx_HAL_GPIO_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h index 2b1b4ed..41f98af 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h @@ -1,388 +1,385 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_PWR_H -#define __STM32F1xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - - -/** - * @} - */ - - -/* Internal constants --------------------------------------------------------*/ - -/** @addtogroup PWR_Private_Constants - * @{ - */ - -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 - -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ - -/** - * @} - */ - - -/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins - * @{ - */ - -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP - -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON 0x00000000U -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS - -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) - -/** - * @brief Enable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * This parameter can be: - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * This parameter can be: - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - - -/** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD EXTI flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup PWR_Private_Macros PWR Private Macros - * @{ - */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) - -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -/* #define HAL_PWR_ConfigPVD 12*/ -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - - - -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F1xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_PWR_H +#define __STM32F1xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + + +/** + * @} + */ + + +/* Internal constants --------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants + * @{ + */ + +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ + +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP + +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +/* #define HAL_PWR_ConfigPVD 12*/ +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + + + +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_PWR_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h index f0097cb..9814caf 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h @@ -1,1378 +1,1375 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_RCC_H -#define __STM32F1xx_HAL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< PLLState: The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ -} RCC_PLLInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ - -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE 0x00000000U -#define RCC_OSCILLATORTYPE_HSE 0x00000001U -#define RCC_OSCILLATORTYPE_HSI 0x00000002U -#define RCC_OSCILLATORTYPE_LSE 0x00000004U -#define RCC_OSCILLATORTYPE_LSI 0x00000008U -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ - -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ - -/** - * @} - */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ -#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ -#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ -/** - * @} - */ - - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 0x00000000U -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ - -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 0x00000000U - -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: BDCR register - * - 011: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) -#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) -#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) -#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) -#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) -#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) -#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_BKP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) - -#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) -#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) - -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) -#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) - -#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) - -#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) -#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) - -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) -#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) -#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) - -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) - -/** - * @} - */ - -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) -#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) - -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - */ -#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) - -/** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) - -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON turn ON the HSE oscillator - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if ((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - else if ((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) - -/** @brief Macro to disable the main PLL. - * @note The main PLL can not be disabled if it is used as system clock source - */ -#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) - -/** @brief Macro to configure the main PLL clock source and multiplication factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 - * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 - @if STM32F105xC - * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 - @elseif STM32F107xC - * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 - @else - * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 - * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 - * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 - * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 - * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 - * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 - * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 - * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 - * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 - @endif - * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 - * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) - -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -#if defined(RCC_CFGR_MCO_3) -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source - */ -#else -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source - */ -#endif - -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) - - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration -* @{ -*/ - -/** @brief Macro to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** @brief Macro to enable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) - -/** @brief Macro to disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) - -/** @brief Macro to force the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) - -/** @brief Macros to release the Backup domain reset. - */ -#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) - -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - @if STM32F105xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @elsif STM32F107xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @endif - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - @if STM32F105xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @elsif STM32F107xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @endif - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - @if STM32F105xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @elsif STM32F107xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @endif - * @arg @ref RCC_IT_CSS Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - @if STM32F105xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @elsif STM32F107xx - * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. - * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. - @endif - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. - @if STM32F105xx - * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. - * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. - @elsif STM32F107xx - * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. - * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. - @endif - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. - * @arg @ref RCC_FLAG_PINRST Pin reset. - * @arg @ref RCC_FLAG_PORRST POR/PDR reset. - * @arg @ref RCC_FLAG_SFTRST Software reset. - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. - * @arg @ref RCC_FLAG_LPWRRST Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ - ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ - RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32f1xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ - -/* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ -/* LSE state change timeout */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ - -/** - * @} - */ - -/** @defgroup RCC_Register_Offset Register offsets - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00U -#define RCC_CFGR_OFFSET 0x04U -#define RCC_CIR_OFFSET 0x08U -#define RCC_BDCR_OFFSET 0x20U -#define RCC_CSR_OFFSET 0x24U - -/** - * @} - */ - -/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) -#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) -#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) -#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) -#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) - -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos -#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) -/* Alias word address of HSEON bit */ -#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos -#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) -/* Alias word address of CSSON bit */ -#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos -#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) -/* Alias word address of PLLON bit */ -#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos -#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos -#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) - -/* Alias word address of RMVF bit */ -#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos -#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) - -/* --- BDCR Registers ---*/ -/* Alias word address of LSEON bit */ -#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos -#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) - -/* Alias word address of LSEON bit */ -#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos -#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) - -/* Alias word address of RTCEN bit */ -#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos -#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) - -/* Alias word address of BDRST bit */ -#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos -#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) - -/** - * @} - */ - -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) - -/* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1) -#define BDCR_REG_INDEX ((uint8_t)2) -#define CSR_REG_INDEX ((uint8_t)3) - -#define RCC_FLAG_MASK ((uint8_t)0x1F) - -/** - * @} - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -/** - * @} - */ - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) - -#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) -#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_H +#define __STM32F1xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ +} RCC_PLLInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_BKP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) + +#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) +#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) +#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the main PLL clock source and multiplication factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 + * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 + @if STM32F105xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @elseif STM32F107xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @else + * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 + * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 + * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 + * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 + * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 + * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 + * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 + * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 + * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 + @endif + * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 + * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCO_3) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration +* @{ +*/ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + @if STM32F105xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @elsif STM32F107xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f1xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00U +#define RCC_CFGR_OFFSET 0x04U +#define RCC_CIR_OFFSET 0x08U +#define RCC_BDCR_OFFSET 0x20U +#define RCC_CSR_OFFSET 0x24U + +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* --- BDCR Registers ---*/ +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define BDCR_REG_INDEX ((uint8_t)2) +#define CSR_REG_INDEX ((uint8_t)3) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +/** + * @} + */ + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h index d0d0830..049d0ec 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -1,1908 +1,1905 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_RCC_EX_H -#define __STM32F1xx_HAL_RCC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/** @addtogroup RCCEx_Private_Constants - * @{ - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos -#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) -/* Alias word address of PLL2ON bit */ -#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos -#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) - -#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ -#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ - -#endif /* STM32F105xC || STM32F107xC */ - - -#define CR_REG_INDEX ((uint8_t)1) - -/** - * @} - */ - -/** @addtogroup RCCEx_Private_Macros - * @{ - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ - ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) -#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ - ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) - -#else -#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ - ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ - ((__MUL__) == RCC_PLL_MUL6_5)) - -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) - -#else -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ - ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ - ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ - ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ - ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ - ((__MUL__) == RCC_PLL_MUL16)) - -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) - -#endif /* STM32F105xC || STM32F107xC*/ - -#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ - ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) - -#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) - -#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) - -#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ - ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ - ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ - ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ - ((__MUL__) == RCC_PLLI2S_MUL20)) - -#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ - ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) - -#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ - ((__PLL__) == RCC_PLL2_ON)) - -#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ - ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ - ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ - ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ - ((__MUL__) == RCC_PLL2_MUL20)) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) - -#elif defined(STM32F103xE) || defined(STM32F103xG) - -#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) - -#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) - - -#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) - -#else - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) - -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) - -#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) - -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLL2 configuration structure definition - */ -typedef struct -{ - uint32_t PLL2State; /*!< The new state of the PLL2. - This parameter can be a value of @ref RCCEx_PLL2_Config */ - - uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock - This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ - -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. - This parameter can be a value of @ref RCCEx_Prediv2_Factor */ - -#endif /* STM32F105xC || STM32F107xC */ -} RCC_PLL2InitTypeDef; - -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t Prediv1Source; /*!< The Prediv1 source value. - This parameter can be a value of @ref RCCEx_Prediv1_Source */ -#endif /* STM32F105xC || STM32F107xC */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) - This parameter can be a value of @ref RCCEx_Prediv1_Factor */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ -#endif /* STM32F105xC || STM32F107xC */ -} RCC_OscInitTypeDef; - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLLI2S configuration structure definition - */ -typedef struct -{ - uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock - This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ - -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. - This parameter can be a value of @ref RCCEx_Prediv2_Factor */ - -#endif /* STM32F105xC || STM32F107xC */ -} RCC_PLLI2SInitTypeDef; -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< specifies the RTC clock source. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t AdcClockSelection; /*!< ADC clock source - This parameter can be a value of @ref RCCEx_ADC_Prescaler */ - -#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) - uint32_t I2s2ClockSelection; /*!< I2S2 clock source - This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ - - uint32_t I2s3ClockSelection; /*!< I2S3 clock source - This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters - This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ - -#endif /* STM32F105xC || STM32F107xC */ -#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Prescaler */ - -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -} RCC_PeriphCLKInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_RTC 0x00000001U -#define RCC_PERIPHCLK_ADC 0x00000002U -#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_PERIPHCLK_I2S2 0x00000004U -#define RCC_PERIPHCLK_I2S3 0x00000008U -#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_PERIPHCLK_USB 0x00000010U -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler - * @{ - */ -#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 -#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 -#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 -#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 - -/** - * @} - */ - -#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) -/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source - * @{ - */ -#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U -#if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source - * @{ - */ -#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U -#if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) - -/** @defgroup RCCEx_USB_Prescaler USB Prescaler - * @{ - */ -#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE -#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U - -/** - * @} - */ - -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_USB_Prescaler USB Prescaler - * @{ - */ -#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE -#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U - -/** - * @} - */ - -/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor - * @{ - */ - -#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ -#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ -#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ -#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ -#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ -#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ -#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ -#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ -#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ - -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_Prediv1_Source Prediv1 Source - * @{ - */ - -#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE -#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 - -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC */ - -/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor - * @{ - */ - -#define RCC_HSE_PREDIV_DIV1 0x00000000U - -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) -#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 -#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 -#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 -#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 -#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 -#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 -#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 -#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 -#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 -#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 -#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 -#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 -#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 -#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 -#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 -#else -#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor - * @{ - */ - -#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ -#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ -#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ -#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ -#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ -#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ -#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ -#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ -#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ -#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ -#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ -#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ -#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ -#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ -#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ -#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ - -/** - * @} - */ - -/** @defgroup RCCEx_PLL2_Config PLL Config - * @{ - */ -#define RCC_PLL2_NONE 0x00000000U -#define RCC_PLL2_OFF 0x00000001U -#define RCC_PLL2_ON 0x00000002U - -/** - * @} - */ - -/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor - * @{ - */ - -#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ -#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ -#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ -#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ -#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ -#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ -#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ -#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ -#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ - -/** - * @} - */ - -#endif /* STM32F105xC || STM32F107xC */ - -/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor - * @{ - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#else -#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 -#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 -#endif /* STM32F105xC || STM32F107xC */ -#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 -#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 -#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 -#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 -#if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 -#else -#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 -#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 -#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 -#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 -#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) -#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) -#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) -#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) -#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) -#if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) -#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) -#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) -#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) -#endif /* STM32F105xC || STM32F107xC*/ -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_Interrupt RCCEx Interrupt - * @{ - */ -#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) -#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) -/** - * @} - */ - -/** @defgroup RCCEx_Flag RCCEx Flag - * Elements values convention: 0XXYYYYYb - * - YYYYY : Flag position in the register - * - XX : Register index - * - 01: CR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC*/ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ - || defined (STM32F100xE) -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined (STM32F100xE) -#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ - -#if defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) - - -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) -#endif /* STM32F103xE || STM32F103xG */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ - UNUSED(tmpreg); \ - } while(0U) - - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) -#endif /* STM32F105xC || STM32F107xC*/ - -#if defined(STM32F107xC) -#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) -#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) -#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) - -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETHMAC_CLK_ENABLE(); \ - __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ - __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0U) -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETH_CLK_DISABLE() do { \ - __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ - __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ - __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0U) - -#endif /* STM32F107xC*/ - -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ - || defined (STM32F100xE) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined (STM32F100xE) -#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) -#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ -#if defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) -#endif /* STM32F103xE || STM32F103xG */ -#if defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) -#endif /* STM32F105xC || STM32F107xC*/ -#if defined(STM32F107xC) -#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) -#endif /* STM32F107xC*/ - -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ - || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ - || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F100xB) || defined (STM32F100xE) -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#endif /* STM32F100xB || STM32F100xE */ - -#ifdef STM32F100xE -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#endif /* STM32F100xE */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#endif /* STM32F101xG || STM32F103xG*/ - -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ - || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ - || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) -#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ -#if defined(STM32F100xB) || defined (STM32F100xE) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) -#endif /* STM32F100xB || STM32F100xE */ -#ifdef STM32F100xE -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#endif /* STM32F100xE */ -#if defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#endif /* STM32F105xC || STM32F107xC */ -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#endif /* STM32F101xG || STM32F103xG*/ - -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ - || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ - || defined(STM32F103xG) -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ - -#if defined(STM32F100xB) || defined(STM32F100xE) -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) -#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) -#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) -#endif /* STM32F100xB || STM32F100xE */ - -#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ - || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ - || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) -#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ - -#if defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#endif /* STM32F103xE || STM32F103xG */ - -#if defined(STM32F100xE) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) -#endif /* STM32F100xE */ - -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#endif /* STM32F101xG || STM32F103xG */ - -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ - || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ - || defined(STM32F103xG) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ -#if defined(STM32F100xB) || defined(STM32F100xE) -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) -#endif /* STM32F100xB || STM32F100xE */ -#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ - || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ - || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) -#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ -#if defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -#endif /* STM32F103xE || STM32F103xG */ -#if defined(STM32F100xE) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) -#endif /* STM32F100xE */ -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) -#endif /* STM32F101xG || STM32F103xG */ - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) -#if defined(STM32F107xC) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) -#endif /* STM32F107xC */ - -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) -#if defined(STM32F107xC) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) -#endif /* STM32F107xC */ - -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ - -#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ - || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) - -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - -#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ - || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) - -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F100xB) || defined (STM32F100xE) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#endif /* STM32F100xB || STM32F100xE */ - -#if defined (STM32F100xE) -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) - -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#endif /* STM32F100xE */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) - -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) - -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#endif /* STM32F101xG || STM32F103xG */ - -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ - -#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ - || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ - || defined(STM32F103xG) -#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) - -#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) -#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ - -#if defined(STM32F100xB) || defined(STM32F100xE) -#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) -#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) - -#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) -#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) -#endif /* STM32F100xB || STM32F100xE */ - -#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ - || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ - || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) - -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) -#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ - -#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ - || defined(STM32F103xG) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) - -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ - -#if defined(STM32F103xE) || defined(STM32F103xG) -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) - -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) -#endif /* STM32F103xE || STM32F103xG */ - -#if defined(STM32F100xE) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) - -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) -#endif /* STM32F100xE */ - -#if defined(STM32F101xG) || defined(STM32F103xG) -#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) - -#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#endif /* STM32F101xG || STM32F103xG*/ - -/** - * @} - */ - -/** @defgroup RCCEx_HSE_Configuration HSE Configuration - * @{ - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) -/** - * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. - * @note Predivision factor can not be changed if PLL is used as system clock - * In this case, you have to select another source of the system clock, disable the PLL and - * then change the HSE predivision factor. - * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. - * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. - */ -#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) -#else -/** - * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. - * @note Predivision factor can not be changed if PLL is used as system clock - * In this case, you have to select another source of the system clock, disable the PLL and - * then change the HSE predivision factor. - * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. - * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. - */ -#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ - MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) - -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) -/** - * @brief Macro to get prediv1 factor for PLL. - */ -#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) - -#else -/** - * @brief Macro to get prediv1 factor for PLL. - */ -#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) - -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration - * @{ - */ - -/** @brief Macros to enable the main PLLI2S. - * @note After enabling the main PLLI2S, the application software should wait on - * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can - * be used as system clock source. - * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) - -/** @brief Macros to disable the main PLLI2S. - * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) - -/** @brief macros to configure the main PLLI2S multiplication factor. - * @note This function must be used only when the main PLLI2S is disabled. - * - * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock - * This parameter can be one of the following values: - * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 - * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 - * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 - * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 - * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 - * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 - * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 - * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 - * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 - * - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) - -/** - * @} - */ - -#endif /* STM32F105xC || STM32F107xC */ - -/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration - * @brief Macros to configure clock source of different peripherals. - * @{ - */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) -/** @brief Macro to configure the USB clock. - * @param __USBCLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock - */ -#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) - -/** @brief Macro to get the USB clock (USBCLK). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock - */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) - -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - -/** @brief Macro to configure the USB OTSclock. - * @param __USBCLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock - */ -#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) - -/** @brief Macro to get the USB clock (USBCLK). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock - * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock - */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) - -#endif /* STM32F105xC || STM32F107xC */ - -/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). - * @param __ADCCLKSOURCE__ specifies the ADC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock - */ -#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) - -/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock - * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock - */ -#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - -/** @addtogroup RCCEx_HSE_Configuration - * @{ - */ - -/** - * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. - * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock - * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and - * then change the PREDIV2 factor. - * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. - * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. - */ -#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) - -/** - * @brief Macro to get prediv2 factor for PLL2 & PLL3. - */ -#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) - -/** - * @} - */ - -/** @addtogroup RCCEx_PLLI2S_Configuration - * @{ - */ - -/** @brief Macros to enable the main PLL2. - * @note After enabling the main PLL2, the application software should wait on - * PLL2RDY flag to be set indicating that PLL2 clock is stable and can - * be used as system clock source. - * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) - -/** @brief Macros to disable the main PLL2. - * @note The main PLL2 can not be disabled if it is used indirectly as system clock source - * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) - -/** @brief macros to configure the main PLL2 multiplication factor. - * @note This function must be used only when the main PLL2 is disabled. - * - * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock - * This parameter can be one of the following values: - * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 - * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 - * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 - * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 - * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 - * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 - * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 - * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 - * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 - * - */ -#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) - -/** - * @} - */ - -/** @defgroup RCCEx_I2S_Configuration I2S Configuration - * @brief Macros to configure clock source of I2S peripherals. - * @{ - */ - -/** @brief Macro to configure the I2S2 clock. - * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry - * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry - */ -#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) - -/** @brief Macro to get the I2S2 clock (I2S2CLK). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry - * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry - */ -#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) - -/** @brief Macro to configure the I2S3 clock. - * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry - * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry - */ -#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) - -/** @brief Macro to get the I2S3 clock (I2S3CLK). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry - * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry - */ -#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) - -/** - * @} - */ - -#endif /* STM32F105xC || STM32F107xC */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @addtogroup RCCEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); - -/** - * @} - */ - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); - -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_EX_H +#define __STM32F1xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos +#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) +/* Alias word address of PLL2ON bit */ +#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos +#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) + +#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ +#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ + +#endif /* STM32F105xC || STM32F107xC */ + + +#define CR_REG_INDEX ((uint8_t)1) + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ + ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) + +#else +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL6_5)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#else +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#endif /* STM32F105xC || STM32F107xC*/ + +#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ + ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) + +#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ + ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ + ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ + ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ + ((__MUL__) == RCC_PLLI2S_MUL20)) + +#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) + +#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ + ((__PLL__) == RCC_PLL2_ON)) + +#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ + ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ + ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ + ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ + ((__MUL__) == RCC_PLL2_MUL20)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#elif defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + + +#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#else + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLL2 configuration structure definition + */ +typedef struct +{ + uint32_t PLL2State; /*!< The new state of the PLL2. + This parameter can be a value of @ref RCCEx_PLL2_Config */ + + uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock + This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLL2InitTypeDef; + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t Prediv1Source; /*!< The Prediv1 source value. + This parameter can be a value of @ref RCCEx_Prediv1_Source */ +#endif /* STM32F105xC || STM32F107xC */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) + This parameter can be a value of @ref RCCEx_Prediv1_Factor */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ +#endif /* STM32F105xC || STM32F107xC */ +} RCC_OscInitTypeDef; + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLLI2S configuration structure definition + */ +typedef struct +{ + uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock + This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLLI2SInitTypeDef; +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< specifies the RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t AdcClockSelection; /*!< ADC clock source + This parameter can be a value of @ref RCCEx_ADC_Prescaler */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) + uint32_t I2s2ClockSelection; /*!< I2S2 clock source + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ + + uint32_t I2s3ClockSelection; /*!< I2S3 clock source + This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ + +#endif /* STM32F105xC || STM32F107xC */ +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Prescaler */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_RTC 0x00000001U +#define RCC_PERIPHCLK_ADC 0x00000002U +#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PERIPHCLK_I2S2 0x00000004U +#define RCC_PERIPHCLK_I2S3 0x00000008U +#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PERIPHCLK_USB 0x00000010U +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler + * @{ + */ +#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 +#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 +#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 +#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 + +/** + * @} + */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source + * @{ + */ +#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE +#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U + +/** + * @} + */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE +#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U + +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor + * @{ + */ + +#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ +#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ +#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ +#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ +#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ +#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ +#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ +#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ +#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv1_Source Prediv1 Source + * @{ + */ + +#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE +#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor + * @{ + */ + +#define RCC_HSE_PREDIV_DIV1 0x00000000U + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 +#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 +#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 +#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 +#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 +#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 +#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 +#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 +#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 +#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 +#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 +#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 +#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 +#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 +#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 +#else +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor + * @{ + */ + +#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ +#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ +#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ +#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ +#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ +#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ +#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ +#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ +#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ +#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ +#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ +#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ +#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ +#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ +#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ +#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Config PLL Config + * @{ + */ +#define RCC_PLL2_NONE 0x00000000U +#define RCC_PLL2_OFF 0x00000001U +#define RCC_PLL2_ON 0x00000002U + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor + * @{ + */ + +#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ +#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ +#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ +#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ +#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ +#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ +#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ +#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ +#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#else +#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 +#endif /* STM32F105xC || STM32F107xC */ +#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 +#else +#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) +#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) +#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) +#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) +#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) +#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) +#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) +#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) +#endif /* STM32F105xC || STM32F107xC*/ +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Interrupt RCCEx Interrupt + * @{ + */ +#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) +#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) +/** + * @} + */ + +/** @defgroup RCCEx_Flag RCCEx Flag + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - XX : Register index + * - 01: CR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) +#endif /* STM32F105xC || STM32F107xC*/ + +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) + +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) +#endif /* STM32F105xC || STM32F107xC*/ +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F100xB || STM32F100xE */ + +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined (STM32F100xE) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) + +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) + +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) + +#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_HSE_Configuration HSE Configuration + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) +#else +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) + +#else +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) + +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration + * @{ + */ + +/** @brief Macros to enable the main PLLI2S. + * @note After enabling the main PLLI2S, the application software should wait on + * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can + * be used as system clock source. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) + +/** @brief Macros to disable the main PLLI2S. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +/** @brief macros to configure the main PLLI2S multiplication factor. + * @note This function must be used only when the main PLLI2S is disabled. + * + * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 + * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 + * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 + * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 + * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 + * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 + * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 + * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 + * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration + * @brief Macros to configure clock source of different peripherals. + * @{ + */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +/** @brief Macro to configure the USB clock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @brief Macro to configure the USB OTSclock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). + * @param __ADCCLKSOURCE__ specifies the ADC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) + +/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @addtogroup RCCEx_HSE_Configuration + * @{ + */ + +/** + * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. + * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock + * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and + * then change the PREDIV2 factor. + * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. + * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) + +/** + * @brief Macro to get prediv2 factor for PLL2 & PLL3. + */ +#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) + +/** + * @} + */ + +/** @addtogroup RCCEx_PLLI2S_Configuration + * @{ + */ + +/** @brief Macros to enable the main PLL2. + * @note After enabling the main PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as system clock source. + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) + +/** @brief Macros to disable the main PLL2. + * @note The main PLL2 can not be disabled if it is used indirectly as system clock source + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) + +/** @brief macros to configure the main PLL2 multiplication factor. + * @note This function must be used only when the main PLL2 is disabled. + * + * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 + * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 + * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 + * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 + * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 + * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 + * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 + * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 + * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 + * + */ +#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Configuration I2S Configuration + * @brief Macros to configure clock source of I2S peripherals. + * @{ + */ + +/** @brief Macro to configure the I2S2 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S2 clock (I2S2CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) + +/** @brief Macro to configure the I2S3 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S3 clock (I2S3CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_EX_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h index 207d59e..83ee478 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h @@ -1,607 +1,604 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rtc.h - * @author MCD Application Team - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_RTC_H -#define __STM32F1xx_HAL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @addtogroup RTC_Private_Macros - * @{ - */ - -#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) -#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) -#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \ - ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \ - ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \ - ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND)) - - -/** - * @} - */ - -/** @addtogroup RTC_Private_Constants - * @{ - */ -/** @defgroup RTC_Timeout_Value Default Timeout Value - * @{ - */ -#define RTC_TIMEOUT_VALUE 1000U -/** - * @} - */ - -/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event - * @{ - */ -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - -} RTC_TimeTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1). - This parameter can be a value of @ref RTC_Alarms_Definitions */ -} RTC_AlarmTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ - -} HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND - If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin. - This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */ - -} RTC_InitTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate). - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -} RTC_DateTypeDef; - -/** - * @brief Time Handle Structure definition - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -typedef struct __RTC_HandleTypeDef -#else -typedef struct -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - - void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - - void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - - void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ - -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - -} RTC_HandleTypeDef; - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL RTC Callback ID enumeration definition - */ -typedef enum -{ - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ - HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ -} HAL_RTC_CallbackIDTypeDef; - -/** - * @brief HAL RTC Callback pointer definition - */ -typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase - * @{ - */ -#define RTC_AUTO_1_SECOND 0xFFFFFFFFU - -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format - * @{ - */ -#define RTC_FORMAT_BIN 0x000000000U -#define RTC_FORMAT_BCD 0x000000001U - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions Month Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions Alarms Definitions - * @{ - */ -#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */ - -/** - * @} - */ - - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin - * @{ - */ - -#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */ -#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */ -#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */ -#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */ - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions - * @{ - */ -#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */ -#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */ -#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */ -#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions Flags Definitions - * @{ - */ -#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */ -#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */ -#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */ -#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state - * @param __HANDLE__: RTC handle. - * @retval None - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0u) -#else -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__) - -/** - * @brief Enable interrupt on ALARM Exti Line 17. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable interrupt on ALARM Exti Line 17. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Enable event on ALARM Exti Line 17. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable event on ALARM Exti Line 17. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) - - -/** - * @brief ALARM EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) - - -/** - * @brief Disable the ALARM Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) - - -/** - * @brief ALARM EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable the ALARM Extended Interrupt Rising Trigger. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief ALARM EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \ -do{ \ - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \ -do{ \ - __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the specified ALARM EXTI interrupt flag is set or not. - * @retval EXTI ALARM Line Status. - */ -#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Clear the ALARM EXTI flag. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT) -/** - * @} - */ - -/* Include RTC HAL Extension module */ -#include "stm32f1xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions - * @{ - */ - - -/* Initialization and de-initialization functions ****************************/ -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* RTC Time and Date functions ************************************************/ -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/* RTC Alarm functions ********************************************************/ -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Peripheral State functions *************************************************/ -/** @addtogroup RTC_Exported_Functions_Group4 - * @{ - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup RTC_Exported_Functions_Group5 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RTC_H +#define __STM32F1xx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @addtogroup RTC_Private_Macros + * @{ + */ + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) +#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) +#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND)) + + +/** + * @} + */ + +/** @addtogroup RTC_Private_Constants + * @{ + */ +/** @defgroup RTC_Timeout_Value Default Timeout Value + * @{ + */ +#define RTC_TIMEOUT_VALUE 1000U +/** + * @} + */ + +/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event + * @{ + */ +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + +} RTC_TimeTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1). + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND + If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin. + This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */ + +} RTC_InitTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate). + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +} RTC_DateTypeDef; + +/** + * @brief Time Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase + * @{ + */ +#define RTC_AUTO_1_SECOND 0xFFFFFFFFU + +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format + * @{ + */ +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions Month Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions Alarms Definitions + * @{ + */ +#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */ + +/** + * @} + */ + + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin + * @{ + */ + +#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */ + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions + * @{ + */ +#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */ +#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */ +#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */ +#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions Flags Definitions + * @{ + */ +#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */ +#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */ +#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */ +#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__: RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0u) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__) + +/** + * @brief Enable interrupt on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable interrupt on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Enable event on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief ALARM EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief Disable the ALARM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief ALARM EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable the ALARM Extended Interrupt Rising Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief ALARM EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Check whether the specified ALARM EXTI interrupt flag is set or not. + * @retval EXTI ALARM Line Status. + */ +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Clear the ALARM EXTI flag. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT) +/** + * @} + */ + +/* Include RTC HAL Extension module */ +#include "stm32f1xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_Exported_Functions + * @{ + */ + + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* RTC Time and Date functions ************************************************/ +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/* RTC Alarm functions ********************************************************/ +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup RTC_Exported_Functions_Group4 + * @{ + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup RTC_Exported_Functions_Group5 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RTC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h index d130680..4070eda 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h @@ -1,412 +1,409 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rtc_ex.h - * @author MCD Application Team - * @brief Header file of RTC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_RTC_EX_H -#define __STM32F1xx_HAL_RTC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @{ - */ - -/** @addtogroup RTCEx_Private_Macros - * @{ - */ - -/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy - * @{ - */ -#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler - -/** - * @} - */ - -/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters - * @{ - */ -#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1) - -#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#if RTC_BKP_NUMBER > 10U -#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42))) -#else -#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER) -#endif -#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - -} RTC_TamperTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions - * @{ - */ -#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */ - -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ -#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ - -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions - * @{ - */ -#if RTC_BKP_NUMBER > 0U -#define RTC_BKP_DR1 0x00000001U -#define RTC_BKP_DR2 0x00000002U -#define RTC_BKP_DR3 0x00000003U -#define RTC_BKP_DR4 0x00000004U -#define RTC_BKP_DR5 0x00000005U -#define RTC_BKP_DR6 0x00000006U -#define RTC_BKP_DR7 0x00000007U -#define RTC_BKP_DR8 0x00000008U -#define RTC_BKP_DR9 0x00000009U -#define RTC_BKP_DR10 0x0000000AU -#endif /* RTC_BKP_NUMBER > 0 */ - -#if RTC_BKP_NUMBER > 10U -#define RTC_BKP_DR11 0x00000010U -#define RTC_BKP_DR12 0x00000011U -#define RTC_BKP_DR13 0x00000012U -#define RTC_BKP_DR14 0x00000013U -#define RTC_BKP_DR15 0x00000014U -#define RTC_BKP_DR16 0x00000015U -#define RTC_BKP_DR17 0x00000016U -#define RTC_BKP_DR18 0x00000017U -#define RTC_BKP_DR19 0x00000018U -#define RTC_BKP_DR20 0x00000019U -#define RTC_BKP_DR21 0x0000001AU -#define RTC_BKP_DR22 0x0000001BU -#define RTC_BKP_DR23 0x0000001CU -#define RTC_BKP_DR24 0x0000001DU -#define RTC_BKP_DR25 0x0000001EU -#define RTC_BKP_DR26 0x0000001FU -#define RTC_BKP_DR27 0x00000020U -#define RTC_BKP_DR28 0x00000021U -#define RTC_BKP_DR29 0x00000022U -#define RTC_BKP_DR30 0x00000023U -#define RTC_BKP_DR31 0x00000024U -#define RTC_BKP_DR32 0x00000025U -#define RTC_BKP_DR33 0x00000026U -#define RTC_BKP_DR34 0x00000027U -#define RTC_BKP_DR35 0x00000028U -#define RTC_BKP_DR36 0x00000029U -#define RTC_BKP_DR37 0x0000002AU -#define RTC_BKP_DR38 0x0000002BU -#define RTC_BKP_DR39 0x0000002CU -#define RTC_BKP_DR40 0x0000002DU -#define RTC_BKP_DR41 0x0000002EU -#define RTC_BKP_DR42 0x0000002FU -#endif /* RTC_BKP_NUMBER > 10 */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP1: Tamper A interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP1: Tamper A interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. - * This parameter can be: - * @arg RTC_IT_TAMP1 - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. - * This parameter can be: - * @arg RTC_IT_TAMP1 - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI) - -/** - * @brief Enable the RTC Second interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled - * This parameter can be any combination of the following values: - * @arg RTC_IT_SEC: Second A interrupt - * @retval None - */ -#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Disable the RTC Second interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_SEC: Second A interrupt - * @retval None - */ -#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Second interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_SEC: Second A interrupt - * @retval None - */ -#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Second's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_SEC - * @retval None - */ -#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Second's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_SEC - * @retval None - */ -#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__) - -/** - * @brief Enable the RTC Overflow interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow A interrupt - * @retval None - */ -#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Disable the RTC Overflow interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow A interrupt - * @retval None - */ -#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Overflow interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_OW: Overflow A interrupt - * @retval None - */ -#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Overflow's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_OW - * @retval None - */ -#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Overflow's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_OW - * @retval None - */ -#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions - * @{ - */ - -/* RTC Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); - -/** - * @} - */ - -/* RTC Second functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc); - -/** - * @} - */ - -/* Extension Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RTC_EX_H +#define __STM32F1xx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @{ + */ + +/** @addtogroup RTCEx_Private_Macros + * @{ + */ + +/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler + +/** + * @} + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#if RTC_BKP_NUMBER > 10U +#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42))) +#else +#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER) +#endif +#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ +/** + * @brief RTC Tamper structure definition + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + +} RTC_TamperTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions + * @{ + */ +#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions + * @{ + */ +#if RTC_BKP_NUMBER > 0U +#define RTC_BKP_DR1 0x00000001U +#define RTC_BKP_DR2 0x00000002U +#define RTC_BKP_DR3 0x00000003U +#define RTC_BKP_DR4 0x00000004U +#define RTC_BKP_DR5 0x00000005U +#define RTC_BKP_DR6 0x00000006U +#define RTC_BKP_DR7 0x00000007U +#define RTC_BKP_DR8 0x00000008U +#define RTC_BKP_DR9 0x00000009U +#define RTC_BKP_DR10 0x0000000AU +#endif /* RTC_BKP_NUMBER > 0 */ + +#if RTC_BKP_NUMBER > 10U +#define RTC_BKP_DR11 0x00000010U +#define RTC_BKP_DR12 0x00000011U +#define RTC_BKP_DR13 0x00000012U +#define RTC_BKP_DR14 0x00000013U +#define RTC_BKP_DR15 0x00000014U +#define RTC_BKP_DR16 0x00000015U +#define RTC_BKP_DR17 0x00000016U +#define RTC_BKP_DR18 0x00000017U +#define RTC_BKP_DR19 0x00000018U +#define RTC_BKP_DR20 0x00000019U +#define RTC_BKP_DR21 0x0000001AU +#define RTC_BKP_DR22 0x0000001BU +#define RTC_BKP_DR23 0x0000001CU +#define RTC_BKP_DR24 0x0000001DU +#define RTC_BKP_DR25 0x0000001EU +#define RTC_BKP_DR26 0x0000001FU +#define RTC_BKP_DR27 0x00000020U +#define RTC_BKP_DR28 0x00000021U +#define RTC_BKP_DR29 0x00000022U +#define RTC_BKP_DR30 0x00000023U +#define RTC_BKP_DR31 0x00000024U +#define RTC_BKP_DR32 0x00000025U +#define RTC_BKP_DR33 0x00000026U +#define RTC_BKP_DR34 0x00000027U +#define RTC_BKP_DR35 0x00000028U +#define RTC_BKP_DR36 0x00000029U +#define RTC_BKP_DR37 0x0000002AU +#define RTC_BKP_DR38 0x0000002BU +#define RTC_BKP_DR39 0x0000002CU +#define RTC_BKP_DR40 0x0000002DU +#define RTC_BKP_DR41 0x0000002EU +#define RTC_BKP_DR42 0x0000002FU +#endif /* RTC_BKP_NUMBER > 10 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper A interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper A interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI) + +/** + * @brief Enable the RTC Second interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Second interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Second interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Second's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_SEC + * @retval None + */ +#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Second's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_SEC + * @retval None + */ +#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__) + +/** + * @brief Enable the RTC Overflow interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Overflow interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Overflow interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Overflow's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_OW + * @retval None + */ +#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Overflow's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_OW + * @retval None + */ +#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + +/* RTC Tamper functions *****************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); + +/** + * @} + */ + +/* RTC Second functions *****************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/* Extension Control functions ************************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RTC_EX_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h index 999f62e..ac72075 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -1,2129 +1,2153 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F1xx_HAL_TIM_H -#define STM32F1xx_HAL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and - Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and - Max_Data = 0xFFFF. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, - ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct -{ - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode - @note When the Master/slave mode is enabled, the effect of - an event on the trigger input (TRGI) is delayed to allow a - perfect synchronization between the current timer and its - slaves (through TRGO). It is not mandatory in case of timer - synchronization mode. */ -} TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct -{ - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -} TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ - - uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ - - uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ - -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -} HAL_TIM_StateTypeDef; - -/** - * @brief TIM Channel States definition - */ -typedef enum -{ - HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ - HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ - HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ -} HAL_TIM_ChannelStateTypeDef; - -/** - * @brief DMA Burst States definition - */ -typedef enum -{ - HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ - HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ - HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ -} HAL_TIM_DMABurstStateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -} HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -typedef struct __TIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ - __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ - void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ - void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ - void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ - void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ - void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ - void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ - void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ - void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ - void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} TIM_HandleTypeDef; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL TIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ -} HAL_TIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ - -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 0x00000000U -#define TIM_DMABASE_CR2 0x00000001U -#define TIM_DMABASE_SMCR 0x00000002U -#define TIM_DMABASE_DIER 0x00000003U -#define TIM_DMABASE_SR 0x00000004U -#define TIM_DMABASE_EGR 0x00000005U -#define TIM_DMABASE_CCMR1 0x00000006U -#define TIM_DMABASE_CCMR2 0x00000007U -#define TIM_DMABASE_CCER 0x00000008U -#define TIM_DMABASE_CNT 0x00000009U -#define TIM_DMABASE_PSC 0x0000000AU -#define TIM_DMABASE_ARR 0x0000000BU -#define TIM_DMABASE_RCR 0x0000000CU -#define TIM_DMABASE_CCR1 0x0000000DU -#define TIM_DMABASE_CCR2 0x0000000EU -#define TIM_DMABASE_CCR3 0x0000000FU -#define TIM_DMABASE_CCR4 0x00000010U -#define TIM_DMABASE_BDTR 0x00000011U -#define TIM_DMABASE_DCR 0x00000012U -#define TIM_DMABASE_DMAR 0x00000013U -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ -#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ -#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ -#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ - -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ -#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ -#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ -#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ -#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ -#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ -#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity - * @{ - */ -#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ -#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ -#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ -#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ -#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ -#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ -#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ -#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ -#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ -#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ -#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ -#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ -#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ -#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ -#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ -#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ -#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ -#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ -#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ -#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ -#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ -#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ -#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ -#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ -#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ -#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ -#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ -#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ -#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ -#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ -#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ -#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ -#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ -#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ -#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ -#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ -#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ -#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ -#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ -#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ -#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ -#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ -#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ -#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ -#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ -#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ -#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ -#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ -#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been - * disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ - == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode - * or Encoder mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() - * function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__HANDLE__)->Instance->CCR4)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) - -/** - * @brief Enable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is enabled an active edge on the trigger input acts - * like a compare match on CCx output. Delay to sample the trigger - * input and to activate CCx output is reduced to 3 clock cycles. - * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) - -/** - * @brief Disable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is disabled CCx output behaves normally depending - * on counter and CCRx values even when the trigger is ON. The minimum - * delay to activate CCx output when an active edge occurs on the - * trigger input is 5 clock cycles. - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR)) - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) - -#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ - ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) - -#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ - (__HANDLE__)->ChannelState[3]) - -#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) - -#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ - (__HANDLE__)->ChannelNState[3]) - -#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32f1xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -void TIM_ResetCallback(TIM_HandleTypeDef *htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F1xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_H +#define STM32F1xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f1xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_TIM_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h index 6f1b5e5..3edc9d3 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -1,262 +1,261 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F1xx_HAL_TIM_EX_H -#define STM32F1xx_HAL_TIM_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ - -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions - * @{ - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F1xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_EX_H +#define STM32F1xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F1xx_HAL_TIM_EX_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h index 34cca4e..7fe76e3 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h @@ -1,887 +1,915 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_UART_H -#define __STM32F1xx_HAL_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal_def.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UART_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. This feature is only available - on STM32F100xx family, so OverSampling parameter should always be set to 16. */ -} UART_InitTypeDef; - -/** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -} HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Reception type definition - * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : - * HAL_UART_RECEPTION_STANDARD = 0x00U, - * HAL_UART_RECEPTION_TOIDLE = 0x01U, - */ -typedef uint32_t HAL_UART_RxTypeTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ - void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ - void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ - void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ - void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ - void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ - void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ - - void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ - void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -} UART_HandleTypeDef; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL UART Callback ID enumeration definition - */ -typedef enum -{ - HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ - HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ - HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ - HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ - HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ - HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ - HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ - HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ - - HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ - HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ - -} HAL_UART_CallbackIDTypeDef; - -/** - * @brief HAL UART Callback pointer definition - */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_Error_Code UART Error Code - * @{ - */ -#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ -#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ -#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ -#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ -#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup UART_Word_Length UART Word Length - * @{ - */ -#define UART_WORDLENGTH_8B 0x00000000U -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_1 0x00000000U -#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U -#if defined(USART_CR1_OVER8) -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -#endif /* USART_CR1_OVER8 */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -/** - * @} - */ - -/** @defgroup UART_WakeUp_functions UART Wakeup Functions - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) -/** - * @} - */ - -/** @defgroup UART_Flags UART FLags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ -#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) -#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define UART_FLAG_TC ((uint32_t)USART_SR_TC) -#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define UART_FLAG_NE ((uint32_t)USART_SR_NE) -#define UART_FLAG_FE ((uint32_t)USART_SR_FE) -#define UART_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupt Definitions - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask (16 bits) in the Y register - * - Y : Interrupt source register (2bits) - * - 0001: CR1 register - * - 0010: CR2 register - * - 0011: CR3 register - * @{ - */ - -#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) -#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) -#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) -#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) -#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) - -#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) - -#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) -#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) -/** - * @} - */ - -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values - * @{ - */ -#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ -#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle gstate & RxState - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ - -/** @brief Flushes the UART DR register - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - -/** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg UART_FLAG_LBD: LIN Break detection flag - * @arg UART_FLAG_TXE: Transmit data register empty flag - * @arg UART_FLAG_TC: Transmission Complete flag - * @arg UART_FLAG_RXNE: Receive data register not empty flag - * @arg UART_FLAG_IDLE: Idle Line detection flag - * @arg UART_FLAG_ORE: Overrun Error flag - * @arg UART_FLAG_NE: Noise Error flag - * @arg UART_FLAG_FE: Framing Error flag - * @arg UART_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg UART_FLAG_LBD: LIN Break detection flag. - * @arg UART_FLAG_TC: Transmission Complete flag. - * @arg UART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clears the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg = 0x00U; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ - } while(0U) - -/** @brief Clears the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Checks whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __IT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ERR: Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) - -/** @brief Enable CTS flow control - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0U) - -/** @brief Disable CTS flow control - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0U) - -/** @brief Enable RTS flow control - * This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0U) - -/** @brief Disable RTS flow control - * This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0U) -#if defined(USART_CR3_ONEBIT) - -/** @brief Macro to enable the UART's one bit sample method - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Macro to disable the UART's one bit sample method - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) -#endif /* UART_ONE_BIT_SAMPLE_Feature */ - -/** @brief Enable UART - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); - -void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -/** @brief UART interruptions flag mask - * - */ -#define UART_IT_MASK 0x0000FFFFU - -#define UART_CR1_REG_INDEX 1U -#define UART_CR2_REG_INDEX 2U -#define UART_CR3_REG_INDEX 3U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) -#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) -#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) -#if defined(USART_CR1_OVER8) -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) -#endif /* USART_CR1_OVER8 */ -#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) -#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U) -#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) - -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) -#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ -#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) - -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) -#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ -#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ - ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ - (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_UART_H +#define __STM32F1xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. This feature is only available + on STM32F100xx family, so OverSampling parameter should always be set to 16. */ +} UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +} HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_Error_Code UART Error Code + * @{ + */ +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B 0x00000000U +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 0x00000000U +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U +#if defined(USART_CR1_OVER8) +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +#endif /* USART_CR1_OVER8 */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask (16 bits) in the Y register + * - Y : Interrupt source register (2bits) + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register + * @{ + */ + +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) + +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) + +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle gstate & RxState + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flushes the UART DR register + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: Overrun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clears the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + +/** @brief Clears the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __IT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief Enable CTS flow control + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +#if defined(USART_CR3_ONEBIT) + +/** @brief Macro to enable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Macro to disable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#endif /* UART_ONE_BIT_SAMPLE_Feature */ + +/** @brief Enable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU + +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#if defined(USART_CR1_OVER8) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#endif /* USART_CR1_OVER8 */ +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_UART_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h index 01fa578..a3a3592 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h @@ -1,3932 +1,3929 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_adc.h - * @author MCD Application Team - * @brief Header file of ADC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_ADC_H -#define __STM32F1xx_LL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined (ADC1) || defined (ADC2) || defined (ADC3) - -/** @defgroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Constants ADC Private Constants - * @{ - */ - -/* Internal mask for ADC group regular sequencer: */ -/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ -/* - sequencer register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group regular sequencer configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SQR1_REGOFFSET 0x00000000U -#define ADC_SQR2_REGOFFSET 0x00000100U -#define ADC_SQR3_REGOFFSET 0x00000200U -#define ADC_SQR4_REGOFFSET 0x00000300U - -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Definition of ADC group regular sequencer bits information to be inserted */ -/* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ - -/* Internal mask for ADC group injected sequencer: */ -/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ -/* - data register offset */ -/* - offset register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group injected data register */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_JDR1_REGOFFSET 0x00000000U -#define ADC_JDR2_REGOFFSET 0x00000100U -#define ADC_JDR3_REGOFFSET 0x00000200U -#define ADC_JDR4_REGOFFSET 0x00000300U - -/* Internal register offset for ADC group injected offset configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_JOFR1_REGOFFSET 0x00000000U -#define ADC_JOFR2_REGOFFSET 0x00001000U -#define ADC_JOFR3_REGOFFSET 0x00002000U -#define ADC_JOFR4_REGOFFSET 0x00003000U - -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) -#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) -#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Internal mask for ADC channel: */ -/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ -/* - channel identifier defined by number */ -/* - channel differentiation between external channels (connected to */ -/* GPIO pins) and internal channels (connected to internal paths) */ -/* - channel sampling time defined by SMPRx register offset */ -/* and SMPx bits positions into SMPRx register */ -#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) -/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ - -/* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ -#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) - -/* Internal register offset for ADC channel sampling time configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SMPR1_REGOFFSET 0x00000000U -#define ADC_SMPR2_REGOFFSET 0x02000000U -#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) - -#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ - -/* Definition of channels ID number information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER 0x00000000U -#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) -#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) -#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) -#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) - -/* Definition of channels sampling time information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ - -/* Internal mask for ADC analog watchdog: */ -/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ -/* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ -/* - analog watchdog 1: monitored channel defined by number, */ -/* selection of ADC group (ADC groups regular and-or injected). */ - -/* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET 0x00000000U - -#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) - -#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) -#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) - -/* Internal register offset for ADC analog watchdog threshold configuration */ -#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U -#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U -#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) - -/* ADC registers bits positions */ -#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits - */ -#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - -/** - * @brief Driver macro reserved for internal use: set a pointer to - * a register from a register basis from which an offset - * is applied. - * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). - * @retval Pointer to register address - */ -#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of ADC common parameters - * and multimode - * (all ADC instances belonging to the same ADC common instance). - * @note The setting of these parameters by function @ref LL_ADC_CommonInit() - * is conditioned to ADC instances state (all ADC instances - * sharing the same ADC common instance): - * All ADC instances sharing the same ADC common instance must be - * disabled. - */ -typedef struct -{ - uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). - This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ -} LL_ADC_CommonInitTypeDef; -/** - * @brief Structure definition of some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t DataAlignment; /*!< Set ADC conversion data alignment. - This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ - - uint32_t SequencersScanMode; /*!< Set ADC scan selection. - This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ - -} LL_ADC_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_REG_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, external trigger is set with trigger polarity: rising edge - (only trigger polarity available on this STM32 serie). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). - This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ - - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. - This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ - -} LL_ADC_REG_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group injected. - * @note These parameters have an impact on ADC scope: ADC group injected. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "INJ"). - * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, external trigger is set with trigger polarity: rising edge - (only trigger polarity available on this STM32 serie). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH - @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE - @note This parameter has an effect only if group injected sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ - - uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ - -} LL_ADC_INJ_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_LL_EC_FLAG ADC flags - * @brief Flags defines which can be used with LL_ADC_ReadReg function - * @{ - */ -#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ -#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ -#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ -#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ -#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ -#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ -#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ -#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ -#endif -/** - * @} - */ - -/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) - * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions - * @{ - */ -#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ -#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose - * @{ - */ -/* List of ADC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -#endif -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels - * @{ - */ -/* Note: Other measurement paths to internal channels may be available */ -/* (connections to other peripherals). */ -/* If they are not listed below, they do not require any specific */ -/* path enable. In this case, Access to measurement path is done */ -/* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment - * @{ - */ -#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection - * @{ - */ -#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ -#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source - * @{ - */ -/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) -/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ -/* A remap of trigger must be done at top level (refer to */ -/* AFIO peripheral). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/ -#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined (STM32F103xE) || defined (STM32F103xG) -/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#endif -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge - * @{ - */ -#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ -#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data - * @{ - */ -#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ -#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ -#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ -#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ -#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ -#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ -#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ -#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ -#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ -#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source - * @{ - */ -/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ -#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) -/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */ -/* XL-density devices. */ -/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ -/* A remap of trigger must be done at top level (refer to */ -/* AFIO peripheral). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */ -#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined (STM32F103xE) || defined (STM32F103xG) -/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#endif -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge - * @{ - */ -#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ -#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ -#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ -/** - * @} - */ - - -/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length - * @{ - */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ -#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks - * @{ - */ -#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ -#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ -#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ -#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ -#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels - * @{ - */ -#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ -#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ -#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds - * @{ - */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ -/** - * @} - */ - -#if !defined(ADC_MULTIMODE_SUPPORT) -/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode - * @{ - */ -#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ -/** - * @} - */ -#endif -#if defined(ADC_MULTIMODE_SUPPORT) -/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode - * @{ - */ -#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ -#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */ -#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ -#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ -#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave - * @{ - */ -#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */ -#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */ -#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ -/** - * @} - */ - -#endif /* ADC_MULTIMODE_SUPPORT */ - - -/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC IP HW delays are defined in ADC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ -/* not timeout values. */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ -/* - ADC enable time: maximum delay is 1us */ -/* (refer to device datasheet, parameter "tSTAB") */ -/* - ADC conversion time: duration depending on ADC clock and ADC */ -/* configuration. */ -/* (refer to device reference manual, section "Timing") */ - -/* Delay for temperature sensor stabilization time. */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */ - -/* Delay required between ADC disable and ADC calibration start. */ -/* Note: On this STM32 serie, before starting a calibration, */ -/* ADC must be disabled. */ -/* A minimum number of ADC clock cycles are required */ -/* between ADC disable state and calibration start. */ -/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */ -/* Wait time can be computed in user application by waiting for the */ -/* equivalent number of CPU cycles, by taking into account */ -/* ratio of CPU clock versus ADC clock prescalers. */ -/* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */ - -/* Delay required between end of ADC Enable and the start of ADC calibration. */ -/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ -/* are required between the end of ADC enable and the start of ADC */ -/* calibration. */ -/* Wait time can be computed in user application by waiting for the */ -/* equivalent number of CPU cycles, by taking into account */ -/* ratio of CPU clock versus ADC clock prescalers. */ -/* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals LL_ADC_CHANNEL_x. - * @note Example: - * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - -/** - * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9U) \ - ? ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - ) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - */ -#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - (((__ADC_INSTANCE__) == ADC1) \ - ? ( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ - ) \ - : \ - (0U) \ - ) - -/** - * @brief Helper macro to define ADC analog watchdog parameter: - * define a single channel to monitor with analog watchdog - * from sequencer channel and groups definition. - * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). - * Example: - * LL_ADC_SetAnalogWDMonitChannels( - * ADC1, LL_ADC_AWD1, - * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * @param __GROUP__ This parameter can be one of the following values: - * @arg @ref LL_ADC_GROUP_REGULAR - * @arg @ref LL_ADC_GROUP_INJECTED - * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - */ -#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ - (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ - ) - -/** - * @brief Helper macro to set the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to set the value of - * analog watchdog threshold high (on 8 bits): - * LL_ADC_SetAnalogWDThresholds - * (< ADCx param >, - * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ -/* This macro has been kept anyway for compatibility with other */ -/* STM32 families featuring different ADC resolutions. */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - ((__AWD_THRESHOLD__) << (0U)) - -/** - * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to get the value of - * analog watchdog threshold high (on 8 bits): - * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION - * (LL_ADC_RESOLUTION_8B, - * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ -/* This macro has been kept anyway for compatibility with other */ -/* STM32 families featuring different ADC resolutions. */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ - (__AWD_THRESHOLD_12_BITS__) - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Helper macro to get the ADC multimode conversion data of ADC master - * or ADC slave from raw value with both ADC conversion data concatenated. - * @note This macro is intended to be used when multimode transfer by DMA - * is enabled. - * In this case the transferred data need to processed with this macro - * to separate the conversion data of ADC master and ADC slave. - * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA) -#endif - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On STM32F1, there is no common ADC instance. - * However, ADC instance ADC1 has a role of common ADC instance - * for ADC1 and ADC2: - * this instance is used to manage internal channels - * and multimode (these features are managed in ADC common - * instances on some other STM32 devices). - * ADC instance ADC3 (if available on the selected device) - * has no ADC common instance. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#if defined(ADC1) && defined(ADC2) && defined(ADC3) -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ - ? ( \ - (ADC12_COMMON) \ - ) \ - : \ - ( \ - (0U) \ - ) \ - ) -#elif defined(ADC1) && defined(ADC2) -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC12_COMMON) -#else -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC1_COMMON) -#endif - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @note On STM32F1, there is no common ADC instance. - * However, ADC instance ADC1 has a role of common ADC instance - * for ADC1 and ADC2: - * this instance is used to manage internal channels - * and multimode (these features are managed in ADC common - * instances on some other STM32 devices). - * ADC instance ADC3 (if available on the selected device) - * has no ADC common instance. - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#if defined(ADC1) && defined(ADC2) && defined(ADC3) -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (((__ADCXY_COMMON__) == ADC12_COMMON) \ - ? ( \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) \ - ) \ - : \ - ( \ - LL_ADC_IsEnabled(ADC3) \ - ) \ - ) -#elif defined(ADC1) && defined(ADC2) -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) -#else -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - LL_ADC_IsEnabled(ADC1) -#endif - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFU) - - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be known from - * user board environment or can be calculated using ADC measurement. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - ) - - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * If temperature sensor calibration values are available on - * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), - * temperature calculation will be more accurate using - * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be known from - * user board environment or can be calculated using ADC measurement. - * @note ADC measurement data must correspond to a resolution of 12bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). - * On STM32F1, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32F1, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000) \ - - \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000) \ - ) \ - ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ - ) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management - * @{ - */ -/* Note: LL ADC functions to set DMA transfer are located into sections of */ -/* configuration of ADC instance, groups and multimode (if available): */ -/* @ref LL_ADC_REG_SetDMATransfer(), ... */ - -/** - * @brief Function to help to configure DMA transfer from ADC: retrieve the - * ADC register address from ADC instance and a list of ADC registers - * intended to be used (most commonly) with DMA transfer. - * @note These ADC registers are data registers: - * when ADC conversion data is available in ADC data registers, - * ADC generates a DMA transfer request. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), - * (uint32_t)&< array or variable >, - * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); - * @note For devices with several ADC: in multimode, some devices - * use a different data register outside of ADC instance scope - * (common data register). This macro manages this register difference, - * only ADC instance has to be set as parameter. - * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer - * capability, not ADC2 (ADC2 and ADC3 instances not available on - * all devices). - * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. - * Therefore, the corresponding parameter of data transfer - * for multimode can be used only with ADC1 and ADC2. - * (ADC2 and ADC3 instances not available on all devices). - * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr - * @param ADCx ADC instance - * @param Register This parameter can be one of the following values: - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) - * - * (1) Available on devices with several ADC instances. - * @retval ADC register address - */ -#if defined(ADC_MULTIMODE_SUPPORT) -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - uint32_t data_reg_addr = 0U; - - if (Register == LL_ADC_DMA_REG_REGULAR_DATA) - { - /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); - } - else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ - { - /* Retrieve address of register of multimode data */ - data_reg_addr = (uint32_t)&(ADC12_COMMON->DR); - } - - return data_reg_addr; -} -#else -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); -} -#endif - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances - * @{ - */ - -/** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal); -} - -/** - * @brief Get parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Set ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); -} - -/** - * @brief Get ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); -} - -/** - * @brief Set ADC sequencers scan mode, for all ADC groups - * (group regular, group injected). - * @note According to sequencers scan mode : - * - If disabled: ADC conversion is performed in unitary conversion - * mode (one channel converted, that defined in rank 1). - * Configuration of sequencers of all ADC groups - * (sequencer scan length, ...) is discarded: equivalent to - * scan length of 1 rank. - * - If enabled: ADC conversions are performed in sequence conversions - * mode, according to configuration of sequencers of - * each ADC group (sequencer scan length, ...). - * Refer to function @ref LL_ADC_REG_SetSequencerLength() - * and to function @ref LL_ADC_INJ_SetSequencerLength(). - * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode - * @param ADCx ADC instance - * @param ScanMode This parameter can be one of the following values: - * @arg @ref LL_ADC_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_SEQ_SCAN_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); -} - -/** - * @brief Get ADC sequencers scan mode, for all ADC groups - * (group regular, group injected). - * @note According to sequencers scan mode : - * - If disabled: ADC conversion is performed in unitary conversion - * mode (one channel converted, that defined in rank 1). - * Configuration of sequencers of all ADC groups - * (sequencer scan length, ...) is discarded: equivalent to - * scan length of 1 rank. - * - If enabled: ADC conversions are performed in sequence conversions - * mode, according to configuration of sequencers of - * each ADC group (sequencer scan length, ...). - * Refer to function @ref LL_ADC_REG_SetSequencerLength() - * and to function @ref LL_ADC_INJ_SetSequencerLength(). - * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_SEQ_SCAN_ENABLE - */ -__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note On this STM32 serie, external trigger is set with trigger polarity: - * rising edge (only trigger polarity available on this STM32 serie). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) - * - * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n - * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n - * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n - * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ -/* Note: On this STM32 serie, ADC group regular external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_REG_StartConversionExtTrig(). */ - MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); -} - -/** - * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note To determine whether group regular trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") - * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) - * - * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n - * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n - * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n - * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL)); -} - -/** - * @brief Get ADC group regular conversion trigger source internal (SW start) - or external. - * @note In case of group regular trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_REG_GetTriggerSource(). - * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE)); -} - - -/** - * @brief Set ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 serie, group regular sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); -} - -/** - * @brief Get ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 serie, group regular sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); -} - -/** - * @brief Set ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note It is not possible to enable both ADC auto-injected mode - * and ADC group regular sequencer discontinuous mode. - * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n - * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); -} - -/** - * @brief Get ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n - * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); -} - -/** - * @brief Set ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note This function performs configuration of: - * - Channels ordering into each rank of scan sequence: - * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register and register position depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - - return (uint32_t) (READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ); -} - -/** - * @brief Set ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode - * @param ADCx ADC instance - * @param Continuous This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); -} - -/** - * @brief Get ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); -} - -/** - * @brief Set ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer - * @param ADCx ADC instance - * @param DMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer); -} - -/** - * @brief Get ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Set ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note On this STM32 serie, external trigger is set with trigger polarity: - * rising edge (only trigger polarity available on this STM32 serie). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) - * - * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n - * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n - * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n - * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ -/* Note: On this STM32 serie, ADC group injected external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ - MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); -} - -/** - * @brief Get ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note To determine whether group injected trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") - * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) - * - * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n - * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n - * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n - * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL)); -} - -/** - * @brief Get ADC group injected conversion trigger source internal (SW start) - or external - * @note In case of group injected trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_INJ_GetTriggerSource. - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE); -} - -/** - * @brief Set ADC group injected sequencer length and scan direction. - * @note This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 serie, group injected sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); -} - -/** - * @brief Get ADC group injected sequencer length and scan direction. - * @note This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 serie, group injected sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); -} - -/** - * @brief Set ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); -} - -/** - * @brief Get ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); -} - -/** - * @brief Set ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; - - MODIFY_REG(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); -} - -/** - * @brief Get ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; - - return (uint32_t)(READ_BIT(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) - >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) - ); -} - -/** - * @brief Set ADC group injected conversion trigger: - * independent or from ADC group regular. - * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data - * permanently kept (not erased by successive conversions of scan of - * ADC sequencer ranks), up to 5 data registers: - * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. - * @note If ADC group injected injected trigger source is set to an - * external trigger, this feature must be must be set to - * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only - * from ADC group regular. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto - * @param ADCx ADC instance - * @param TrigAuto This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); -} - -/** - * @brief Get ADC group injected conversion trigger: - * independent or from ADC group regular. - * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); -} - -/** - * @brief Set ADC group injected offset. - * @note It sets: - * - ADC group injected rank to which the offset programmed - * will be applied - * - Offset level (offset to be subtracted from the raw - * converted data). - * Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @note Offset cannot be enabled or disabled. - * To emulate offset disabled, set an offset value equal to 0. - * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n - * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n - * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n - * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_JOFR1_JOFFSET1, - OffsetLevel); -} - -/** - * @brief Get ADC group injected offset. - * @note It gives offset level (offset to be subtracted from the raw converted data). - * Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n - * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n - * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n - * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_JOFR1_JOFFSET1) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels - * @{ - */ - -/** - * @brief Set sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 serie. - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) -{ - /* Set bits with content of parameter "SamplingTime" with bits position */ - /* in register and register position depending on parameter "Channel". */ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), - SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); -} - -/** - * @brief Get sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 serie. - * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 - */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) - >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog - * @{ - */ - -/** - * @brief Set ADC analog watchdog monitored channels: - * a single channel or all channels, - * on ADC groups regular and-or injected. - * @note Once monitored channels are selected, analog watchdog - * is enabled. - * @note In case of need to define a single channel to monitor - * with analog watchdog from sequencer channel definition, - * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n - * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n - * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDChannelGroup This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) - * - * (1) On STM32F1, parameter available only on ADC instance: ADC1. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) -{ - MODIFY_REG(ADCx->CR1, - (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), - AWDChannelGroup); -} - -/** - * @brief Get ADC analog watchdog monitored channel. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Applicable only when the analog watchdog is set to monitor - * one channel. - * @note On this STM32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n - * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n - * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); -} - -/** - * @brief Set ADC analog watchdog threshold value of threshold - * high or low. - * @note On this STM32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n - * LTR LT LL_ADC_SetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - - MODIFY_REG(*preg, - ADC_HTR_HT, - AWDThresholdValue); -} - -/** - * @brief Get ADC analog watchdog threshold value of threshold high or - * threshold low. - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n - * LTR LT LL_ADC_GetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF -*/ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - - return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode - * @{ - */ - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Set ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param Multimode This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) -{ - MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode); -} - -/** - * @brief Get ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD)); -} - -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ -/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for - * ADC internal analog stabilization is required before performing a - * ADC conversion start. - * Refer to device datasheet, parameter tSTAB. - * @rmtoll CR2 ADON LL_ADC_Enable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, ADC_CR2_ADON); -} - -/** - * @brief Disable the selected ADC instance. - * @rmtoll CR2 ADON LL_ADC_Disable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); -} - -/** - * @brief Get the selected ADC instance enable state. - * @rmtoll CR2 ADON LL_ADC_IsEnabled - * @param ADCx ADC instance - * @retval 0: ADC is disabled, 1: ADC is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); -} - -/** - * @brief Start ADC calibration in the mode single-ended - * or differential (for devices with differential mode available). - * @note On this STM32 serie, before starting a calibration, - * ADC must be disabled. - * A minimum number of ADC clock cycles are required - * between ADC disable state and calibration start. - * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES. - * @note On this STM32 serie, hardware prerequisite before starting a calibration: - the ADC must have been in power-on state for at least - two ADC clock cycles. - * @rmtoll CR2 CAL LL_ADC_StartCalibration - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, ADC_CR2_CAL); -} - -/** - * @brief Get ADC calibration state. - * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing - * @param ADCx ADC instance - * @retval 0: calibration complete, 1: calibration in progress. - */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant only for - * internal trigger (SW start), not for external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function - * @ref LL_ADC_REG_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other - * settings, ADC conversion would start at trigger event - * as soon as ADC is enabled). - * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); -} - -/** - * @brief Start ADC group regular conversion from external trigger. - * @note ADC conversion will start at next trigger event (on the selected - * trigger edge) following the ADC start conversion command. - * @note On this STM32 serie, this function is relevant for - * ADC conversion start from external trigger. - * If internal trigger (SW start) is needed, perform ADC conversion - * start using function @ref LL_ADC_REG_StartConversionSWStart(). - * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - SET_BIT(ADCx->CR2, ExternalTriggerEdge); -} - -/** - * @brief Stop ADC group regular conversion from external trigger. - * @note No more ADC conversion will start at next trigger event - * following the ADC stop conversion command. - * If a conversion is on-going, it will be completed. - * @note On this STM32 serie, there is no specific command - * to stop a conversion on-going or to stop ADC converting - * in continuous mode. These actions can be performed - * using function @ref LL_ADC_Disable(). - * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Get ADC multimode conversion data of ADC master, ADC slave - * or raw data with ADC master and slave concatenated. - * @note If raw data with ADC master and slave concatenated is retrieved, - * a macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * (however this macro is mainly intended for multimode - * transfer by DMA, because this function can do the same - * by getting multimode conversion data of ADC master or ADC slave - * separately). - * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n - * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32 - * @param ADCx ADC instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ConversionData This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @arg @ref LL_ADC_MULTI_MASTER_SLAVE - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData) -{ - return (uint32_t)(READ_BIT(ADCx->DR, - ADC_DR_ADC2DATA) - >> POSITION_VAL(ConversionData) - ); -} -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant only for - * internal trigger (SW start), not for external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function - * @ref LL_ADC_INJ_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other - * settings, ADC conversion would start at trigger event - * as soon as ADC is enabled). - * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); -} - -/** - * @brief Start ADC group injected conversion from external trigger. - * @note ADC conversion will start at next trigger event (on the selected - * trigger edge) following the ADC start conversion command. - * @note On this STM32 serie, this function is relevant for - * ADC conversion start from external trigger. - * If internal trigger (SW start) is needed, perform ADC conversion - * start using function @ref LL_ADC_INJ_StartConversionSWStart(). - * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - SET_BIT(ADCx->CR2, ExternalTriggerEdge); -} - -/** - * @brief Stop ADC group injected conversion from external trigger. - * @note No more ADC conversion will start at next trigger event - * following the ADC stop conversion command. - * If a conversion is on-going, it will be completed. - * @note On this STM32 serie, there is no specific command - * to stop a conversion on-going or to stop ADC converting - * in continuous mode. These actions can be performed - * using function @ref LL_ADC_Disable(). - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint16_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management - * @{ - */ - -/** - * @brief Get flag ADC group regular end of sequence conversions. - * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); -} - - -/** - * @brief Get flag ADC group injected end of sequence conversions. - * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); -} - -/** - * @brief Get flag ADC analog watchdog 1 flag - * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); -} - -/** - * @brief Clear flag ADC group regular end of sequence conversions. - * @rmtoll SR EOC LL_ADC_ClearFlag_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS); -} - - -/** - * @brief Clear flag ADC group injected end of sequence conversions. - * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); -} - -/** - * @brief Clear flag ADC analog watchdog 1. - * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); -} - -#if defined(ADC_MULTIMODE_SUPPORT) -/** - * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. - * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC)); -} - -/** - * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. - * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); - - return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); -} - - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. - * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC)); -} - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. - * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); - - return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); -} - -/** - * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. - * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); -} - -/** - * @brief Get flag multimode analog watchdog 1 of the ADC slave. - * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); - - return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); -} - -#endif /* ADC_MULTIMODE_SUPPORT */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_IT_Management ADC IT management - * @{ - */ - -/** - * @brief Enable interruption ADC group regular end of sequence conversions. - * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - SET_BIT(ADCx->CR1, ADC_CR1_EOCIE); -} - - -/** - * @brief Enable interruption ADC group injected end of sequence conversions. - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); -} - -/** - * @brief Enable interruption ADC analog watchdog 1. - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); -} - -/** - * @brief Disable interruption ADC group regular end of sequence conversions. - * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE); -} - - -/** - * @brief Disable interruption ADC group injected end of sequence conversions. - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); -} - -/** - * @brief Disable interruption ADC analog watchdog 1. - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); -} - -/** - * @brief Get state of interruption ADC group regular end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group regular */ - /* end of unitary conversion. */ - /* Flag noted as "EOC" is corresponding to flag "EOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); -} - - -/** - * @brief Get state of interruption ADC group injected end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 serie, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); -} - -/** - * @brief Get state of interruption ADC analog watchdog 1 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -/* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); - -/* De-initialization of ADC instance, ADC group regular and ADC group injected */ -/* (availability of ADC group injected depends on STM32 families) */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); - -/* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); - -/* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); - -/* Initialization of some features of ADC instance and ADC group injected */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 || ADC2 || ADC3 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_ADC_H +#define __STM32F1xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET 0x00000000U +#define ADC_SQR2_REGOFFSET 0x00000100U +#define ADC_SQR3_REGOFFSET 0x00000200U +#define ADC_SQR4_REGOFFSET 0x00000300U + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - offset register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET 0x00000000U +#define ADC_JDR2_REGOFFSET 0x00000100U +#define ADC_JDR3_REGOFFSET 0x00000200U +#define ADC_JDR4_REGOFFSET 0x00000300U + +/* Internal register offset for ADC group injected offset configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JOFR1_REGOFFSET 0x00000000U +#define ADC_JOFR2_REGOFFSET 0x00001000U +#define ADC_JOFR3_REGOFFSET 0x00002000U +#define ADC_JOFR4_REGOFFSET 0x00003000U + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET 0x00000000U +#define ADC_SMPR2_REGOFFSET 0x02000000U +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER 0x00000000U +#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) +#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET 0x00000000U + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U +#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) + +/* ADC registers bits positions */ +#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ +} LL_ADC_CommonInitTypeDef; +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t SequencersScanMode; /*!< Set ADC scan selection. + This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, external trigger is set with trigger polarity: rising edge + (only trigger polarity available on this STM32 series). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 series, external trigger is set with trigger polarity: rising edge + (only trigger polarity available on this STM32 series). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ +#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection + * @{ + */ +#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ +#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ +/* A remap of trigger must be done at top level (refer to */ +/* AFIO peripheral). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined (STM32F103xE) || defined (STM32F103xG) +/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ +/* A remap of trigger must be done at top level (refer to */ +/* AFIO peripheral). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined (STM32F103xE) || defined (STM32F103xG) +/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode +* @{ +*/ +#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +#if !defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +/** + * @} + */ +#endif +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC enable time: maximum delay is 1us */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay required between ADC disable and ADC calibration start. */ +/* Note: On this STM32 series, before starting a calibration, */ +/* ADC must be disabled. */ +/* A minimum number of ADC clock cycles are required */ +/* between ADC disable state and calibration start. */ +/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */ + +/* Delay required between end of ADC Enable and the start of ADC calibration. */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ +/* are required between the end of ADC enable and the start of ADC */ +/* calibration. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9U) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + (((__ADC_INSTANCE__) == ADC1) \ + ? ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ + ) \ + : \ + (0U) \ + ) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +/* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */ +/* This macro has been kept anyway for compatibility with other */ +/* STM32 families featuring different ADC resolutions. */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << (0U)) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +/* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */ +/* This macro has been kept anyway for compatibility with other */ +/* STM32 families featuring different ADC resolutions. */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + (__AWD_THRESHOLD_12_BITS__) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled. + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA) +#endif + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On STM32F1, there is no common ADC instance. + * However, ADC instance ADC1 has a role of common ADC instance + * for ADC1 and ADC2: + * this instance is used to manage internal channels + * and multimode (these features are managed in ADC common + * instances on some other STM32 devices). + * ADC instance ADC3 (if available on the selected device) + * has no ADC common instance. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ + ? ( \ + (ADC12_COMMON) \ + ) \ + : \ + ( \ + (0U) \ + ) \ + ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) +#endif + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @note On STM32F1, there is no common ADC instance. + * However, ADC instance ADC1 has a role of common ADC instance + * for ADC1 and ADC2: + * this instance is used to manage internal channels + * and multimode (these features are managed in ADC common + * instances on some other STM32 devices). + * ADC instance ADC3 (if available on the selected device) + * has no ADC common instance. + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (((__ADCXY_COMMON__) == ADC12_COMMON) \ + ? ( \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) \ + ) \ + : \ + ( \ + LL_ADC_IsEnabled(ADC3) \ + ) \ + ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) +#endif + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU) + + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be known from + * user board environment or can be calculated using ADC measurement. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + ) + + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be known from + * user board environment or can be calculated using ADC measurement. + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32F1, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32F1, refer to device datasheet parameter "V25". + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((( ( \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000) \ + - \ + (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000) \ + ) \ + ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer + * capability, not ADC2 (ADC2 and ADC3 instances not available on + * all devices). + * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. + * Therefore, the corresponding parameter of data transfer + * for multimode can be used only with ADC1 and ADC2. + * (ADC2 and ADC3 instances not available on all devices). + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +#if defined(ADC_MULTIMODE_SUPPORT) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + uint32_t data_reg_addr = 0U; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t)&(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register of multimode data */ + data_reg_addr = (uint32_t)&(ADC12_COMMON->DR); + } + + return data_reg_addr; +} +#else +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Retrieve address of register DR */ + return (uint32_t)&(ADCx->DR); +} +#endif + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); +} + +/** + * @brief Set ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode + * @param ADCx ADC instance + * @param ScanMode This parameter can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); +} + +/** + * @brief Get ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, external trigger is set with trigger polarity: + * rising edge (only trigger polarity available on this STM32 series). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group regular external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE)); +} + + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + return (uint32_t) (READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, external trigger is set with trigger polarity: + * rising edge (only trigger polarity available on this STM32 series). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group injected external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + MODIFY_REG(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + return (uint32_t)(READ_BIT(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) + >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); +} + +/** + * @brief Set ADC group injected offset. + * @note It sets: + * - ADC group injected rank to which the offset programmed + * will be applied + * - Offset level (offset to be subtracted from the raw + * converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note Offset cannot be enabled or disabled. + * To emulate offset disabled, set an offset value equal to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_JOFR1_JOFFSET1, + OffsetLevel); +} + +/** + * @brief Get ADC group injected offset. + * @note It gives offset level (offset to be subtracted from the raw converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JOFR1_JOFFSET1) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), + SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) + >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CR1, + (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), + AWDChannelGroup); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n + * LTR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + MODIFY_REG(*preg, + ADC_HTR_HT, + AWDThresholdValue); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high or + * threshold low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n + * LTR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @rmtoll CR2 ADON LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll CR2 ADON LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll CR2 ADON LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 series, before starting a calibration, + * ADC must be disabled. + * A minimum number of ADC clock cycles are required + * between ADC disable state and calibration start. + * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES. + * @note On this STM32 series, hardware prerequisite before starting a calibration: + the ADC must have been in power-on state for at least + two ADC clock cycles. + * @rmtoll CR2 CAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_CAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_REG_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); +} + +/** + * @brief Start ADC group regular conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_REG_StartConversionSWStart(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group regular conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n + * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32 + * @param ADCx ADC instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCx->DR, + ADC_DR_ADC2DATA) + >> POSITION_VAL(ConversionData) + ); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_INJ_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); +} + +/** + * @brief Start ADC group injected conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_INJ_StartConversionSWStart(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group injected conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); +} + + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll SR EOC LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS); +} + + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC)); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); +} + + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_JEOC) == (ADC_SR_JEOC)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave. + * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, ADC_CR1_EOCIE); +} + + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE); +} + + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); +} + + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 families) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_ADC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h index e17f1af..146fd88 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h @@ -1,1015 +1,1012 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_BUS_H -#define __STM32F1xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST) -#define RCC_AHBRSTR_SUPPORT -#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN -#if defined(DMA2) -#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN -#endif /*DMA2*/ -#if defined(ETH) -#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN -#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN -#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN -#endif /*ETH*/ -#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN -#if defined(FSMC_Bank1) -#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN -#endif /*FSMC_Bank1*/ -#if defined(USB_OTG_FS) -#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN -#endif /*USB_OTG_FS*/ -#if defined(SDIO) -#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN -#endif /*SDIO*/ -#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN -#if defined(CAN1) -#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN -#endif /*CAN1*/ -#if defined(CAN2) -#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN -#endif /*CAN2*/ -#if defined(CEC) -#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN -#endif /*CEC*/ -#if defined(DAC) -#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN -#endif /*DAC*/ -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN -#if defined(I2C2) -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN -#endif /*I2C2*/ -#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN -#if defined(SPI2) -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN -#endif /*SPI2*/ -#if defined(SPI3) -#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN -#endif /*SPI3*/ -#if defined(TIM12) -#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN -#endif /*TIM12*/ -#if defined(TIM13) -#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN -#endif /*TIM13*/ -#if defined(TIM14) -#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN -#endif /*TIM14*/ -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN -#if defined(TIM4) -#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN -#endif /*TIM4*/ -#if defined(TIM5) -#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN -#endif /*TIM5*/ -#if defined(TIM6) -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN -#endif /*TIM6*/ -#if defined(TIM7) -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN -#endif /*TIM7*/ -#if defined(UART4) -#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN -#endif /*UART4*/ -#if defined(UART5) -#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN -#endif /*UART5*/ -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN -#if defined(USART3) -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN -#endif /*USART3*/ -#if defined(USB) -#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN -#endif /*USB*/ -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH - * @{ - */ -#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN -#if defined(ADC2) -#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN -#endif /*ADC2*/ -#if defined(ADC3) -#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN -#endif /*ADC3*/ -#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN -#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN -#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN -#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN -#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN -#if defined(GPIOE) -#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN -#endif /*GPIOE*/ -#if defined(GPIOF) -#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN -#endif /*GPIOF*/ -#if defined(GPIOG) -#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN -#endif /*GPIOG*/ -#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#if defined(TIM10) -#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN -#endif /*TIM10*/ -#if defined(TIM11) -#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN -#endif /*TIM11*/ -#if defined(TIM15) -#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN -#endif /*TIM15*/ -#if defined(TIM16) -#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN -#endif /*TIM16*/ -#if defined(TIM17) -#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN -#endif /*TIM17*/ -#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#if defined(TIM8) -#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN -#endif /*TIM8*/ -#if defined(TIM9) -#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN -#endif /*TIM9*/ -#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n - * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n - * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n - * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n - * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n - * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHBENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n - * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n - * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n - * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n - * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n - * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBENR, Periphs); -} - -#if defined(RCC_AHBRSTR_SUPPORT) -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBRSTR, Periphs); -} -#endif /* RCC_AHBRSTR_SUPPORT */ - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1 APB1 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n - * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_BKP - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_BKP - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n - * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_BKP - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_BKP - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_BKP - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB2 APB2 - * @{ - */ - -/** - * @brief Enable APB2 peripherals clock. - * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n - * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n - * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_AFIO - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB2 peripheral clock is enabled or not - * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_AFIO - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB2 peripherals clock. - * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n - * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n - * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_AFIO - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB2 peripherals reset. - * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_AFIO - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB2 peripherals reset. - * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_AFIO - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_BUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_BUS_H +#define __STM32F1xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST) +#define RCC_AHBRSTR_SUPPORT +#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN +#endif /*ETH*/ +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#if defined(FSMC_Bank1) +#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN +#endif /*FSMC_Bank1*/ +#if defined(USB_OTG_FS) +#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN +#endif /*USB_OTG_FS*/ +#if defined(SDIO) +#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN +#endif /*SDIO*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN +#if defined(CAN1) +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#endif /*CAN1*/ +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /*CAN2*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /*DAC*/ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /*SPI3*/ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /*TIM12*/ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /*TIM13*/ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /*TIM14*/ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /*TIM4*/ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#endif /*TIM5*/ +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /*UART4*/ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /*UART5*/ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /*USART3*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /*USB*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(ADC2) +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#endif /*ADC2*/ +#if defined(ADC3) +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#endif /*ADC3*/ +#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN +#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN +#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN +#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN +#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN +#if defined(GPIOE) +#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN +#endif /*GPIOE*/ +#if defined(GPIOF) +#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN +#endif /*GPIOF*/ +#if defined(GPIOG) +#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN +#endif /*GPIOG*/ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(TIM10) +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#endif /*TIM10*/ +#if defined(TIM11) +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#endif /*TIM11*/ +#if defined(TIM15) +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /*TIM15*/ +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#endif /*TIM16*/ +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /*TIM17*/ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /*TIM8*/ +#if defined(TIM9) +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#endif /*TIM9*/ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +#if defined(RCC_AHBRSTR_SUPPORT) +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} +#endif /* RCC_AHBRSTR_SUPPORT */ + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_BUS_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h index 7baf2ac..c1fb2c7 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h @@ -1,640 +1,638 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick - functions - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) MPU API to configure and enable regions - (MPU services provided only on some devices) - (+) API to access to MCU info (CPUID register) - (+) API to enable fault handler (SHCSR accesses) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_CORTEX_H -#define __STM32F1xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type - * @{ - */ -#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ -#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ -#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ -/** - * @} - */ - -#if __MPU_PRESENT - -/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control - * @{ - */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ -#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION MPU Region Number - * @{ - */ -#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ -#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ -#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ -#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ -#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ -#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ -#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ -#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size - * @{ - */ -#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges - * @{ - */ -#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ -#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ -#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ -#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ -#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ -#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level - * @{ - */ -#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ -#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ -#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ -#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access - * @{ - */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access - * @{ - */ -#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ -#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access - * @{ - */ -#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ -#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access - * @{ - */ -#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ -#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ -/** - * @} - */ -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_HANDLER HANDLER - * @{ - */ - -/** - * @brief Enable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) -{ - /* Enable the system handler fault */ - SET_BIT(SCB->SHCSR, Fault); -} - -/** - * @brief Disable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) -{ - /* Disable the system handler fault */ - CLEAR_BIT(SCB->SHCSR, Fault); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Constant number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant - * @retval Value should be equal to 0xF for Cortex-M3 devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC23 for Cortex-M3 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -#if __MPU_PRESENT -/** @defgroup CORTEX_LL_EF_MPU MPU - * @{ - */ - -/** - * @brief Enable MPU with input options - * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable - * @param Options This parameter can be one of the following values: - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE - * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI - * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) -{ - /* Enable the MPU*/ - WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); - /* Ensure MPU settings take effects */ - __DSB(); - /* Sequence instruction fetches using update settings */ - __ISB(); -} - -/** - * @brief Disable MPU - * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable - * @retval None - */ -__STATIC_INLINE void LL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - /* Disable MPU*/ - WRITE_REG(MPU->CTRL, 0U); -} - -/** - * @brief Check if MPU is enabled or not - * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) -{ - return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); -} - -/** - * @brief Enable a MPU region - * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Enable the MPU region */ - SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @brief Configure and enable a region - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR ADDR LL_MPU_ConfigRegion\n - * MPU_RASR XN LL_MPU_ConfigRegion\n - * MPU_RASR AP LL_MPU_ConfigRegion\n - * MPU_RASR S LL_MPU_ConfigRegion\n - * MPU_RASR C LL_MPU_ConfigRegion\n - * MPU_RASR B LL_MPU_ConfigRegion\n - * MPU_RASR SIZE LL_MPU_ConfigRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Address Value of region base address - * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B - * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB - * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB - * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB - * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB - * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB - * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS - * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE - * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE - * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Set base address */ - WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); - /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); -} - -/** - * @brief Disable a region - * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n - * MPU_RASR ENABLE LL_MPU_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Disable the MPU region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @} - */ - -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_CORTEX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (MPU services provided only on some devices) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_CORTEX_H +#define __STM32F1xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M3 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC23 for Cortex-M3 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_CORTEX_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h new file mode 100755 index 0000000..534ba11 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_LL_CRC_H +#define STM32F1xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_LL_CRC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h index 9ebff4e..9c526e8 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h @@ -1,1960 +1,1958 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_DMA_H -#define __STM32F1xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ -static const uint8_t CHANNEL_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) -}; -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_Private_Macros DMA Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note: The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Channel - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ -/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_DMA_WriteReg function - * @{ - */ -#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ -#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ -#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ -#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ -#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ -#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ -#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ -#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ -#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ -#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_DMA_ReadReg function - * @{ - */ -#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ -#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ -#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ -#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ -#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ -#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ -#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ -#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ -#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ -#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions - * @{ - */ -#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ -#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ -#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ -#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ -#if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ -#endif /*USE_FULL_LL_DRIVER*/ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE Transfer mode - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode - * @{ - */ -#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY Memory increment mode - * @{ - */ -#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely - * @{ - */ - -/** - * @brief Convert DMAx_Channely into DMAx - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval DMAx - */ -#if defined(DMA2) -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) -#else -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) -#endif - -/** - * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval LL_DMA_CHANNEL_y - */ -#if defined (DMA2) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#else -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#endif - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely - * @param __DMA_INSTANCE__ DMAx - * @param __CHANNEL__ LL_DMA_CHANNEL_y - * @retval DMAx_Channely - */ -#if defined (DMA2) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA channel. - * @rmtoll CCR EN LL_DMA_EnableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Disable DMA channel. - * @rmtoll CCR EN LL_DMA_DisableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Check if DMA channel is enabled or disabled. - * @rmtoll CCR EN LL_DMA_IsEnabledChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); -} - -/** - * @brief Configure all parameters link to DMA transfer. - * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n - * CCR MEM2MEM LL_DMA_ConfigTransfer\n - * CCR CIRC LL_DMA_ConfigTransfer\n - * CCR PINC LL_DMA_ConfigTransfer\n - * CCR MINC LL_DMA_ConfigTransfer\n - * CCR PSIZE LL_DMA_ConfigTransfer\n - * CCR MSIZE LL_DMA_ConfigTransfer\n - * CCR PL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); -} - -/** - * @brief Set DMA mode circular or normal. - * @note The circular buffer mode cannot be used if the memory-to-memory - * data transfer is configured on the selected Channel. - * @rmtoll CCR CIRC LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, - Mode); -} - -/** - * @brief Get DMA mode circular or normal. - * @rmtoll CCR CIRC LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_CIRC)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, - PeriphOrM2MSrcIncMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, - MemoryOrM2MDstIncMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, - PeriphOrM2MSrcDataSize); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CCR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, - MemoryOrM2MDstDataSize); -} - -/** - * @brief Get Memory size. - * @rmtoll CCR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MSIZE)); -} - -/** - * @brief Set Channel priority level. - * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, - Priority); -} - -/** - * @brief Get Channel priority level. - * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @note This action has no effect if - * channel is enabled. - * @rmtoll CNDTR NDT LL_DMA_SetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @note Once the channel is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @rmtoll CNDTR NDT LL_DMA_GetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT)); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). - * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n - * CMAR MA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, - uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); -} - -/** - * @brief Get Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CMAR MA LL_DMA_GetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @brief Get Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CPAR PA LL_DMA_GetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Get the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Get the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Channel 1 global interrupt flag. - * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); -} - -/** - * @brief Get Channel 2 global interrupt flag. - * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); -} - -/** - * @brief Get Channel 3 global interrupt flag. - * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); -} - -/** - * @brief Get Channel 4 global interrupt flag. - * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); -} - -/** - * @brief Get Channel 5 global interrupt flag. - * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); -} - -/** - * @brief Get Channel 6 global interrupt flag. - * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); -} - -/** - * @brief Get Channel 7 global interrupt flag. - * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); -} - -/** - * @brief Get Channel 1 transfer complete flag. - * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); -} - -/** - * @brief Get Channel 2 transfer complete flag. - * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); -} - -/** - * @brief Get Channel 3 transfer complete flag. - * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); -} - -/** - * @brief Get Channel 4 transfer complete flag. - * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); -} - -/** - * @brief Get Channel 5 transfer complete flag. - * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); -} - -/** - * @brief Get Channel 6 transfer complete flag. - * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); -} - -/** - * @brief Get Channel 7 transfer complete flag. - * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); -} - -/** - * @brief Get Channel 1 half transfer flag. - * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); -} - -/** - * @brief Get Channel 2 half transfer flag. - * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); -} - -/** - * @brief Get Channel 3 half transfer flag. - * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); -} - -/** - * @brief Get Channel 4 half transfer flag. - * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); -} - -/** - * @brief Get Channel 5 half transfer flag. - * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); -} - -/** - * @brief Get Channel 6 half transfer flag. - * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); -} - -/** - * @brief Get Channel 7 half transfer flag. - * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); -} - -/** - * @brief Get Channel 1 transfer error flag. - * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); -} - -/** - * @brief Get Channel 2 transfer error flag. - * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); -} - -/** - * @brief Get Channel 3 transfer error flag. - * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); -} - -/** - * @brief Get Channel 4 transfer error flag. - * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); -} - -/** - * @brief Get Channel 5 transfer error flag. - * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); -} - -/** - * @brief Get Channel 6 transfer error flag. - * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); -} - -/** - * @brief Get Channel 7 transfer error flag. - * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); -} - -/** - * @brief Clear Channel 1 global interrupt flag. - * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); -} - -/** - * @brief Clear Channel 2 global interrupt flag. - * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); -} - -/** - * @brief Clear Channel 3 global interrupt flag. - * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); -} - -/** - * @brief Clear Channel 4 global interrupt flag. - * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); -} - -/** - * @brief Clear Channel 5 global interrupt flag. - * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); -} - -/** - * @brief Clear Channel 6 global interrupt flag. - * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); -} - -/** - * @brief Clear Channel 7 global interrupt flag. - * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); -} - -/** - * @brief Clear Channel 1 transfer complete flag. - * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); -} - -/** - * @brief Clear Channel 2 transfer complete flag. - * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); -} - -/** - * @brief Clear Channel 3 transfer complete flag. - * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); -} - -/** - * @brief Clear Channel 4 transfer complete flag. - * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); -} - -/** - * @brief Clear Channel 5 transfer complete flag. - * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); -} - -/** - * @brief Clear Channel 6 transfer complete flag. - * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); -} - -/** - * @brief Clear Channel 7 transfer complete flag. - * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); -} - -/** - * @brief Clear Channel 1 half transfer flag. - * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); -} - -/** - * @brief Clear Channel 2 half transfer flag. - * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); -} - -/** - * @brief Clear Channel 3 half transfer flag. - * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); -} - -/** - * @brief Clear Channel 4 half transfer flag. - * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); -} - -/** - * @brief Clear Channel 5 half transfer flag. - * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); -} - -/** - * @brief Clear Channel 6 half transfer flag. - * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); -} - -/** - * @brief Clear Channel 7 half transfer flag. - * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); -} - -/** - * @brief Clear Channel 1 transfer error flag. - * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); -} - -/** - * @brief Clear Channel 2 transfer error flag. - * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); -} - -/** - * @brief Clear Channel 3 transfer error flag. - * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); -} - -/** - * @brief Clear Channel 4 transfer error flag. - * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); -} - -/** - * @brief Clear Channel 5 transfer error flag. - * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); -} - -/** - * @brief Clear Channel 6 transfer error flag. - * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); -} - -/** - * @brief Clear Channel 7 transfer error flag. - * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Check if Transfer complete Interrupt is enabled. - * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); -} - -/** - * @brief Check if Half transfer Interrupt is enabled. - * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); -} - -/** - * @brief Check if Transfer error Interrupt is enabled. - * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_DMA_H +#define __STM32F1xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +}; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ + +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_DMA_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h index 612e005..48a42f0 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h @@ -1,888 +1,886 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F1xx_LL_EXTI_H -#define STM32F1xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#if defined(EXTI_IMR_IM16) -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#endif -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#endif -#if defined(EXTI_IMR_IM19) -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#endif -#if defined(EXTI_IMR_IM20) -#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ -#endif -#if defined(EXTI_IMR_IM21) -#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ -#endif -#if defined(EXTI_IMR_IM22) -#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ -#endif -#if defined(EXTI_IMR_IM23) -#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ -#endif -#if defined(EXTI_IMR_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ -#endif -#if defined(EXTI_IMR_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ -#endif -#if defined(EXTI_IMR_IM26) -#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ -#endif -#if defined(EXTI_IMR_IM27) -#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ -#endif -#if defined(EXTI_IMR_IM28) -#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ -#endif -#if defined(EXTI_IMR_IM29) -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ -#endif -#if defined(EXTI_IMR_IM30) -#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ -#endif -#if defined(EXTI_IMR_IM31) -#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ -#endif -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ - - -#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); - -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - - -/** - * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); -} - - -/** - * @brief Clear ExtLine Flags for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F1xx_LL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_LL_EXTI_H +#define STM32F1xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#if defined(EXTI_IMR_IM19) +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#endif +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#if defined(EXTI_IMR_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#endif +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_LL_EXTI_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h index 8cc7832..85749dd 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -898,7 +897,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) } /** - * @brief Check if SPI1 has been remaped or not + * @brief Check if SPI1 has been remapped or not * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 * @retval State of bit (1 or 0). */ @@ -930,7 +929,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) } /** - * @brief Check if I2C1 has been remaped or not + * @brief Check if I2C1 has been remapped or not * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 * @retval State of bit (1 or 0). */ @@ -962,7 +961,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) } /** - * @brief Check if USART1 has been remaped or not + * @brief Check if USART1 has been remapped or not * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 * @retval State of bit (1 or 0). */ @@ -994,7 +993,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) } /** - * @brief Check if USART2 has been remaped or not + * @brief Check if USART2 has been remapped or not * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 * @retval State of bit (1 or 0). */ @@ -1176,7 +1175,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) } /** - * @brief Check if TIM4 has been remaped or not + * @brief Check if TIM4 has been remapped or not * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 * @retval State of bit (1 or 0). */ @@ -1251,7 +1250,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) } /** - * @brief Check if PD01 has been remaped or not + * @brief Check if PD01 has been remapped or not * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 * @retval State of bit (1 or 0). */ @@ -1286,7 +1285,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) } /** - * @brief Check if TIM5CH4 has been remaped or not + * @brief Check if TIM5CH4 has been remapped or not * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 * @retval State of bit (1 or 0). */ @@ -1322,7 +1321,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) } /** - * @brief Check if ETH has been remaped or not + * @brief Check if ETH has been remapped or not * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH * @retval State of bit (1 or 0). */ @@ -1358,7 +1357,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) } /** - * @brief Check if CAN2 has been remaped or not + * @brief Check if CAN2 has been remapped or not * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 * @retval State of bit (1 or 0). */ @@ -1418,7 +1417,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) } /** - * @brief Check if ADC1_ETRGINJ has been remaped or not + * @brief Check if ADC1_ETRGINJ has been remapped or not * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ * @retval State of bit (1 or 0). */ @@ -1452,7 +1451,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) } /** - * @brief Check if ADC1_ETRGREG has been remaped or not + * @brief Check if ADC1_ETRGREG has been remapped or not * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG * @retval State of bit (1 or 0). */ @@ -1487,7 +1486,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) } /** - * @brief Check if ADC2_ETRGINJ has been remaped or not + * @brief Check if ADC2_ETRGINJ has been remapped or not * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ * @retval State of bit (1 or 0). */ @@ -1522,7 +1521,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) } /** - * @brief Check if ADC2_ETRGREG has been remaped or not + * @brief Check if ADC2_ETRGREG has been remapped or not * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG * @retval State of bit (1 or 0). */ @@ -1540,8 +1539,7 @@ __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) */ __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) { - CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); - SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET); } /** @@ -1552,8 +1550,7 @@ __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) */ __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) { - CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); - SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST); } /** @@ -1564,8 +1561,7 @@ __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) */ __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) { - CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); - SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); } /** @@ -1576,8 +1572,7 @@ __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) */ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) { - CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); - SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE); } #if defined(AFIO_MAPR_SPI3_REMAP) @@ -1607,7 +1602,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) } /** - * @brief Check if SPI3 has been remaped or not + * @brief Check if SPI3 has been remapped or not * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP * @retval State of bit (1 or 0). */ @@ -1696,7 +1691,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) } /** - * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not + * @brief Check if TIM9_CH1 and TIM9_CH2 have been remapped or not * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 * @retval State of bit (1 or 0). */ @@ -1731,7 +1726,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) } /** - * @brief Check if TIM10_CH1 has been remaped or not + * @brief Check if TIM10_CH1 has been remapped or not * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 * @retval State of bit (1 or 0). */ @@ -1765,7 +1760,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) } /** - * @brief Check if TIM11_CH1 has been remaped or not + * @brief Check if TIM11_CH1 has been remapped or not * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 * @retval State of bit (1 or 0). */ @@ -1800,7 +1795,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) } /** - * @brief Check if TIM13_CH1 has been remaped or not + * @brief Check if TIM13_CH1 has been remapped or not * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 * @retval State of bit (1 or 0). */ @@ -1835,7 +1830,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) } /** - * @brief Check if TIM14_CH1 has been remaped or not + * @brief Check if TIM14_CH1 has been remapped or not * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 * @retval State of bit (1 or 0). */ @@ -1894,7 +1889,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) } /** - * @brief Check if TIM15_CH1 has been remaped or not + * @brief Check if TIM15_CH1 has been remapped or not * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 * @retval State of bit (1 or 0). */ @@ -1929,7 +1924,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) } /** - * @brief Check if TIM16_CH1 has been remaped or not + * @brief Check if TIM16_CH1 has been remapped or not * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 * @retval State of bit (1 or 0). */ @@ -1964,7 +1959,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) } /** - * @brief Check if TIM17_CH1 has been remaped or not + * @brief Check if TIM17_CH1 has been remapped or not * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 * @retval State of bit (1 or 0). */ @@ -1999,7 +1994,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) } /** - * @brief Check if CEC has been remaped or not + * @brief Check if CEC has been remapped or not * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC * @retval State of bit (1 or 0). */ @@ -2034,7 +2029,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) } /** - * @brief Check if TIM1DMA has been remaped or not + * @brief Check if TIM1DMA has been remapped or not * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA * @retval State of bit (1 or 0). */ @@ -2069,7 +2064,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) } /** - * @brief Check if TIM67DACDMA has been remaped or not + * @brief Check if TIM67DACDMA has been remapped or not * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA * @retval State of bit (1 or 0). */ @@ -2106,7 +2101,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) } /** - * @brief Check if TIM12_CH1 has been remaped or not + * @brief Check if TIM12_CH1 has been remapped or not * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 * @retval State of bit (1 or 0). */ @@ -2151,7 +2146,7 @@ __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) } /** - * @brief Check if MISC has been remaped or not + * @brief Check if MISC has been remapped or not * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC * @retval State of bit (1 or 0). */ @@ -2344,4 +2339,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif /* STM32F1xx_LL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h index cd75914..f912a16 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h @@ -1,440 +1,437 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_PWR_H -#define __STM32F1xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ -#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ -#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ -/** - * @} - */ - - -/** @defgroup PWR_LL_EC_MODE_PWR Mode Power - * @{ - */ -#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode - * @{ - */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level - * @{ - */ -#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ -#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ -#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ -#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ -#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ -#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ -#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ -#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ -/** - * @} - */ -/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins - * @{ - */ -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable access to the backup domain - * @rmtoll CR DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Disable access to the backup domain - * @rmtoll CR DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Check if the backup domain is enabled - * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); -} - -/** - * @brief Set voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_SetRegulModeDS - * @param RegulMode This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) -{ - MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); -} - -/** - * @brief Get voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_GetRegulModeDS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); -} - -/** - * @brief Set Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPDS LL_PWR_SetPowerMode - * @param PDMode This parameter can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) -{ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); -} - -/** - * @brief Get Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPDS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); -} - -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector - * @rmtoll CR PLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); -} - -/** - * @brief Get the voltage threshold detection - * @rmtoll CR PLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); -} - -/** - * @brief Enable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Disable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Check if Power Voltage Detector is enabled - * @rmtoll CR PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); -} - -/** - * @brief Enable the WakeUp PINx functionality - * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Disable the WakeUp PINx functionality - * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Check if the WakeUp PINx functionality is enabled - * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); -} - - -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Wake-up Flag - * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); -} - -/** - * @brief Get Standby Flag - * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); -} - -/** - * @brief Indicate whether VDD voltage is below the selected PVD threshold - * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); -} - -/** - * @brief Clear Standby Flag - * @rmtoll CR CSBF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - SET_BIT(PWR->CR, PWR_CR_CSBF); -} - -/** - * @brief Clear Wake-up Flags - * @rmtoll CR CWUF LL_PWR_ClearFlag_WU - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) -{ - SET_BIT(PWR->CR, PWR_CR_CWUF); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_PWR_H +#define __STM32F1xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} + +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_PWR_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h index 3ca73fe..97a6390 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h @@ -1,2312 +1,2309 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_RCC_H -#define __STM32F1xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ -#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ -#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ -#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ -#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ -/** - * @} - */ - -#if defined(RCC_CFGR2_PREDIV2) -/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor - * @{ - */ -#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ -#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ -#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ -#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ -#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ -#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ -#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ -#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ -#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ -#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ -#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ -#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ -#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ -#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ -#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ -#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ -/** - * @} - */ - -#endif /* RCC_CFGR2_PREDIV2 */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) - * @{ - */ -#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ -#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ -#if defined(RCC_CFGR_MCO_PLL2CLK) -#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ -#endif /* RCC_CFGR_MCO_PLL2CLK */ -#if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) -#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ -#endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ -#if defined(RCC_CFGR_MCO_EXT_HSE) -#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ -#endif /* RCC_CFGR_MCO_EXT_HSE */ -#if defined(RCC_CFGR_MCO_PLL3CLK) -#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ -#endif /* RCC_CFGR_MCO_PLL3CLK */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -#if defined(RCC_CFGR2_I2S2SRC) -/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection - * @{ - */ -#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ -#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ -#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ -#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ -/** - * @} - */ -#endif /* RCC_CFGR2_I2S2SRC */ - -#if defined(USB_OTG_FS) || defined(USB) -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#if defined(RCC_CFGR_USBPRE) -#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ -#endif /*RCC_CFGR_USBPRE*/ -#if defined(RCC_CFGR_OTGFSPRE) -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ -#endif /*RCC_CFGR_OTGFSPRE*/ -/** - * @} - */ -#endif /* USB_OTG_FS || USB */ - -/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection - * @{ - */ -#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ -#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ -#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ -#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ -/** - * @} - */ - -#if defined(RCC_CFGR2_I2S2SRC) -/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source - * @{ - */ -#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ -#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ -/** - * @} - */ - -#endif /* RCC_CFGR2_I2S2SRC */ - -#if defined(USB_OTG_FS) || defined(USB) -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ -/** - * @} - */ - -#endif /* USB_OTG_FS || USB */ - -/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source - * @{ - */ -#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor - * @{ - */ -#if defined(RCC_CFGR_PLLMULL2) -#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ -#endif /*RCC_CFGR_PLLMULL2*/ -#if defined(RCC_CFGR_PLLMULL3) -#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ -#endif /*RCC_CFGR_PLLMULL3*/ -#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ -#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ -#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ -#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ -#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ -#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ -#if defined(RCC_CFGR_PLLMULL6_5) -#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ -#else -#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ -#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ -#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ -#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ -#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ -#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ -#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ -#endif /*RCC_CFGR_PLLMULL6_5*/ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE - * @{ - */ -#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ -#if defined(RCC_CFGR2_PREDIV1SRC) -#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ -#endif /*RCC_CFGR2_PREDIV1SRC*/ - -#if defined(RCC_CFGR2_PREDIV1) -#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ -#if defined(RCC_CFGR2_PREDIV1SRC) -#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ -#endif /*RCC_CFGR2_PREDIV1SRC*/ -#else -#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ -#endif /*RCC_CFGR2_PREDIV1*/ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor - * @{ - */ -#if defined(RCC_CFGR2_PREDIV1) -#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ -#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ -#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ -#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ -#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ -#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ -#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ -#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ -#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ -#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ -#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ -#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ -#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ -#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ -#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ -#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ -#else -#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ -#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ -#endif /*RCC_CFGR2_PREDIV1*/ -/** - * @} - */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL - * @{ - */ -#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ -#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ -#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ -#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ -#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ -#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ -#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ -#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ -#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ -/** - * @} - */ - -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL - * @{ - */ -#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ -#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ -#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ -#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ -#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ -#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ -#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ -#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ -#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ -/** - * @} - */ - -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -#if defined(RCC_CFGR_PLLMULL6_5) -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) - * @param __PLLMUL__: This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_6_5 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ - (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ - ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ - (((__INPUTFREQ__) * 13U) / 2U)) - -#else -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) - * @param __PLLMUL__: This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) -#endif /* RCC_CFGR_PLLMULL6_5 */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Helper macro to calculate the PLLI2S frequency - * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); - * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) - * @param __PLLI2SMUL__: This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2S_MUL_8 - * @arg @ref LL_RCC_PLLI2S_MUL_9 - * @arg @ref LL_RCC_PLLI2S_MUL_10 - * @arg @ref LL_RCC_PLLI2S_MUL_11 - * @arg @ref LL_RCC_PLLI2S_MUL_12 - * @arg @ref LL_RCC_PLLI2S_MUL_13 - * @arg @ref LL_RCC_PLLI2S_MUL_14 - * @arg @ref LL_RCC_PLLI2S_MUL_16 - * @arg @ref LL_RCC_PLLI2S_MUL_20 - * @param __PLLI2SDIV__: This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Helper macro to calculate the PLL2 frequency - * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); - * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) - * @param __PLL2MUL__: This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2_MUL_8 - * @arg @ref LL_RCC_PLL2_MUL_9 - * @arg @ref LL_RCC_PLL2_MUL_10 - * @arg @ref LL_RCC_PLL2_MUL_11 - * @arg @ref LL_RCC_PLL2_MUL_12 - * @arg @ref LL_RCC_PLL2_MUL_13 - * @arg @ref LL_RCC_PLL2_MUL_14 - * @arg @ref LL_RCC_PLL2_MUL_16 - * @arg @ref LL_RCC_PLL2_MUL_20 - * @param __PLL2DIV__: This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 - * @retval PLL2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @brief Helper macro to calculate the HCLK frequency - * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler - * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) - * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__: This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler - * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__: This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) - -/** - * @brief Helper macro to calculate the PCLK2 frequency (ABP2) - * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler - * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB2PRESCALER__: This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval PCLK2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); -} - -#if defined(RCC_CFGR2_PREDIV2) -/** - * @brief Get PREDIV2 division factor - * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); -} -#endif /* RCC_CFGR2_PREDIV2 */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 16, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value between Min_Data = 0x00 and Max_Data = 0x1F - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); -} - -/** - * @brief Set APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); -} - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); -} - -/** - * @brief Get APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCO LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 - * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) - * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -#if defined(RCC_CFGR2_I2S2SRC) -/** - * @brief Configure I2Sx clock source - * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n - * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource - * @param I2SxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO - * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) -{ - MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); -} -#endif /* RCC_CFGR2_I2S2SRC */ - -#if defined(USB_OTG_FS) || defined(USB) -/** - * @brief Configure USB clock source - * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n - * CFGR USBPRE LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ -#if defined(RCC_CFGR_USBPRE) - MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); -#else /*RCC_CFGR_OTGFSPRE*/ - MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); -#endif /*RCC_CFGR_USBPRE*/ -} -#endif /* USB_OTG_FS || USB */ - -/** - * @brief Configure ADC clock source - * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource - * @param ADCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); -} - -#if defined(RCC_CFGR2_I2S2SRC) -/** - * @brief Get I2Sx clock source - * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n - * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource - * @param I2Sx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S2_CLKSOURCE - * @arg @ref LL_RCC_I2S3_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO - * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); -} -#endif /* RCC_CFGR2_I2S2SRC */ - -#if defined(USB_OTG_FS) || defined(USB) -/** - * @brief Get USBx clock source - * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n - * CFGR USBPRE LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); -} -#endif /* USB_OTG_FS || USB */ - -/** - * @brief Get ADCx clock source - * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource - * @param ADCx This parameter can be one of the following values: - * @arg @ref LL_RCC_ADC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 - * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed any more unless - * the Backup domain is reset. The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); -} - -/** - * @brief Configure PLL used for SYSCLK Domain - * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) - * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) - * - * (*) value not defined in all devices - * @param PLLMul This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 (*) - * @arg @ref LL_RCC_PLL_MUL_3 (*) - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_6_5 (*) - * @arg @ref LL_RCC_PLL_MUL_10 (*) - * @arg @ref LL_RCC_PLL_MUL_11 (*) - * @arg @ref LL_RCC_PLL_MUL_12 (*) - * @arg @ref LL_RCC_PLL_MUL_13 (*) - * @arg @ref LL_RCC_PLL_MUL_14 (*) - * @arg @ref LL_RCC_PLL_MUL_15 (*) - * @arg @ref LL_RCC_PLL_MUL_16 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, - (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); -#if defined(RCC_CFGR2_PREDIV1) -#if defined(RCC_CFGR2_PREDIV1SRC) - MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), - (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); -#else - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); -#endif /*RCC_CFGR2_PREDIV1SRC*/ -#endif /*RCC_CFGR2_PREDIV1*/ -} - -/** - * @brief Configure PLL clock source - * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n - * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) -{ -#if defined(RCC_CFGR2_PREDIV1SRC) - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); -#endif /* RCC_CFGR2_PREDIV1SRC */ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n - * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ -#if defined(RCC_CFGR2_PREDIV1SRC) - uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); - uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); - return (uint32_t)(pllsrc | predivsrc); -#else - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); -#endif /*RCC_CFGR2_PREDIV1SRC*/ -} - -/** - * @brief Get PLL multiplication Factor - * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 (*) - * @arg @ref LL_RCC_PLL_MUL_3 (*) - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_6_5 (*) - * @arg @ref LL_RCC_PLL_MUL_10 (*) - * @arg @ref LL_RCC_PLL_MUL_11 (*) - * @arg @ref LL_RCC_PLL_MUL_12 (*) - * @arg @ref LL_RCC_PLL_MUL_13 (*) - * @arg @ref LL_RCC_PLL_MUL_14 (*) - * @arg @ref LL_RCC_PLL_MUL_15 (*) - * @arg @ref LL_RCC_PLL_MUL_16 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); -} - -/** - * @brief Get PREDIV1 division factor for the main PLL - * @note They can be written only when the PLL is disabled - * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n - * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 (*) - * @arg @ref LL_RCC_PREDIV_DIV_4 (*) - * @arg @ref LL_RCC_PREDIV_DIV_5 (*) - * @arg @ref LL_RCC_PREDIV_DIV_6 (*) - * @arg @ref LL_RCC_PREDIV_DIV_7 (*) - * @arg @ref LL_RCC_PREDIV_DIV_8 (*) - * @arg @ref LL_RCC_PREDIV_DIV_9 (*) - * @arg @ref LL_RCC_PREDIV_DIV_10 (*) - * @arg @ref LL_RCC_PREDIV_DIV_11 (*) - * @arg @ref LL_RCC_PREDIV_DIV_12 (*) - * @arg @ref LL_RCC_PREDIV_DIV_13 (*) - * @arg @ref LL_RCC_PREDIV_DIV_14 (*) - * @arg @ref LL_RCC_PREDIV_DIV_15 (*) - * @arg @ref LL_RCC_PREDIV_DIV_16 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) -{ -#if defined(RCC_CFGR2_PREDIV1) - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); -#else - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos); -#endif /*RCC_CFGR2_PREDIV1*/ -} - -/** - * @} - */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** @defgroup RCC_LL_EF_PLLI2S PLLI2S - * @{ - */ - -/** - * @brief Enable PLLI2S - * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLL3ON); -} - -/** - * @brief Disable PLLI2S - * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); -} - -/** - * @brief Check if PLLI2S Ready - * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); -} - -/** - * @brief Configure PLLI2S used for I2S Domain - * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n - * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S - * @param Divider This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 - * @param Multiplicator This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2S_MUL_8 - * @arg @ref LL_RCC_PLLI2S_MUL_9 - * @arg @ref LL_RCC_PLLI2S_MUL_10 - * @arg @ref LL_RCC_PLLI2S_MUL_11 - * @arg @ref LL_RCC_PLLI2S_MUL_12 - * @arg @ref LL_RCC_PLLI2S_MUL_13 - * @arg @ref LL_RCC_PLLI2S_MUL_14 - * @arg @ref LL_RCC_PLLI2S_MUL_16 - * @arg @ref LL_RCC_PLLI2S_MUL_20 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); -} - -/** - * @brief Get PLLI2S Multiplication Factor - * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2S_MUL_8 - * @arg @ref LL_RCC_PLLI2S_MUL_9 - * @arg @ref LL_RCC_PLLI2S_MUL_10 - * @arg @ref LL_RCC_PLLI2S_MUL_11 - * @arg @ref LL_RCC_PLLI2S_MUL_12 - * @arg @ref LL_RCC_PLLI2S_MUL_13 - * @arg @ref LL_RCC_PLLI2S_MUL_14 - * @arg @ref LL_RCC_PLLI2S_MUL_16 - * @arg @ref LL_RCC_PLLI2S_MUL_20 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); -} - -/** - * @} - */ -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** @defgroup RCC_LL_EF_PLL2 PLL2 - * @{ - */ - -/** - * @brief Enable PLL2 - * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLL2ON); -} - -/** - * @brief Disable PLL2 - * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); -} - -/** - * @brief Check if PLL2 Ready - * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); -} - -/** - * @brief Configure PLL2 used for PLL2 Domain - * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n - * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 - * @param Divider This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 - * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 - * @param Multiplicator This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2_MUL_8 - * @arg @ref LL_RCC_PLL2_MUL_9 - * @arg @ref LL_RCC_PLL2_MUL_10 - * @arg @ref LL_RCC_PLL2_MUL_11 - * @arg @ref LL_RCC_PLL2_MUL_12 - * @arg @ref LL_RCC_PLL2_MUL_13 - * @arg @ref LL_RCC_PLL2_MUL_14 - * @arg @ref LL_RCC_PLL2_MUL_16 - * @arg @ref LL_RCC_PLL2_MUL_20 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); -} - -/** - * @brief Get PLL2 Multiplication Factor - * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL2_MUL_8 - * @arg @ref LL_RCC_PLL2_MUL_9 - * @arg @ref LL_RCC_PLL2_MUL_10 - * @arg @ref LL_RCC_PLL2_MUL_11 - * @arg @ref LL_RCC_PLL2_MUL_12 - * @arg @ref LL_RCC_PLL2_MUL_13 - * @arg @ref LL_RCC_PLL2_MUL_14 - * @arg @ref LL_RCC_PLL2_MUL_16 - * @arg @ref LL_RCC_PLL2_MUL_20 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); -} - -/** - * @} - */ -#endif /* RCC_PLL2_SUPPORT */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); -} - -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Clear PLLI2S ready interrupt flag - * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Clear PLL2 ready interrupt flag - * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); -} -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_CSSC); -} - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); -} - -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Check if PLLI2S ready interrupt occurred or not - * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Check if PLL2 ready interrupt occurred or not - * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); -} -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); -} - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); -} - -/** - * @brief Check if RCC flag POR/PDR reset is set or not. - * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); -} - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Enable PLLI2S ready interrupt - * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Enable PLL2 ready interrupt - * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); -} -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Disable PLLI2S ready interrupt - * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Disable PLL2 ready interrupt - * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); -} -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); -} - -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. - * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLL2_SUPPORT) -/** - * @brief Checks if PLL2 ready interrupt source is enabled or disabled. - * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); -} -#endif /* RCC_PLL2_SUPPORT */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -#if defined(RCC_CFGR2_I2S2SRC) -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); -#endif /* RCC_CFGR2_I2S2SRC */ -#if defined(USB_OTG_FS) || defined(USB) -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#endif /* USB_OTG_FS || USB */ -uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RCC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_RCC_H +#define __STM32F1xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ +#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ +#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ +/** + * @} + */ + +#if defined(RCC_CFGR2_PREDIV2) +/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor + * @{ + */ +#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ +#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ +#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ +#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ +#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ +#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ +#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ +#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ +#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ +#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ +#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ +#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ +#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ +#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ +#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ +#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ +/** + * @} + */ + +#endif /* RCC_CFGR2_PREDIV2 */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_MCO_PLL2CLK) +#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ +#endif /* RCC_CFGR_MCO_PLL2CLK */ +#if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) +#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ +#endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ +#if defined(RCC_CFGR_MCO_EXT_HSE) +#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ +#endif /* RCC_CFGR_MCO_EXT_HSE */ +#if defined(RCC_CFGR_MCO_PLL3CLK) +#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ +#endif /* RCC_CFGR_MCO_PLL3CLK */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ +#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ +/** + * @} + */ +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_CFGR_USBPRE) +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ +#endif /*RCC_CFGR_USBPRE*/ +#if defined(RCC_CFGR_OTGFSPRE) +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ +#endif /*RCC_CFGR_OTGFSPRE*/ +/** + * @} + */ +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ +/** + * @} + */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ +#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ +/** + * @} + */ + +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#if defined(RCC_CFGR_PLLMULL2) +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ +#endif /*RCC_CFGR_PLLMULL2*/ +#if defined(RCC_CFGR_PLLMULL3) +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ +#endif /*RCC_CFGR_PLLMULL3*/ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ +#if defined(RCC_CFGR_PLLMULL6_5) +#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ +#else +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ +#endif /*RCC_CFGR_PLLMULL6_5*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ +#if defined(RCC_CFGR2_PREDIV1SRC) +#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ +#endif /*RCC_CFGR2_PREDIV1SRC*/ + +#if defined(RCC_CFGR2_PREDIV1) +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#if defined(RCC_CFGR2_PREDIV1SRC) +#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ +#endif /*RCC_CFGR2_PREDIV1SRC*/ +#else +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ +#endif /*RCC_CFGR2_PREDIV1*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#if defined(RCC_CFGR2_PREDIV1) +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ +#else +#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ +#endif /*RCC_CFGR2_PREDIV1*/ +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL + * @{ + */ +#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ +#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ +#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ +#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ +#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ +#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ +#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ +#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ +#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ +/** + * @} + */ + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL + * @{ + */ +#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ +#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ +#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ +#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ +#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ +#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ +#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ +#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ +#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ +/** + * @} + */ + +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_CFGR_PLLMULL6_5) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) + * @param __PLLMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ + (((__INPUTFREQ__) * 13U) / 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) + * @param __PLLMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) +#endif /* RCC_CFGR_PLLMULL6_5 */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Helper macro to calculate the PLLI2S frequency + * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); + * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) + * @param __PLLI2SMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + * @param __PLLI2SDIV__: This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Helper macro to calculate the PLL2 frequency + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); + * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) + * @param __PLL2MUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + * @param __PLL2DIV__: This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @retval PLL2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +#if defined(RCC_CFGR2_PREDIV2) +/** + * @brief Get PREDIV2 division factor + * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); +} +#endif /* RCC_CFGR2_PREDIV2 */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) + * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** + * @brief Configure I2Sx clock source + * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n + * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO + * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); +} +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n + * CFGR USBPRE LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ +#if defined(RCC_CFGR_USBPRE) + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); +#else /*RCC_CFGR_OTGFSPRE*/ + MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); +#endif /*RCC_CFGR_USBPRE*/ +} +#endif /* USB_OTG_FS || USB */ + +/** + * @brief Configure ADC clock source + * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); +} + +#if defined(RCC_CFGR2_I2S2SRC) +/** + * @brief Get I2Sx clock source + * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n + * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @arg @ref LL_RCC_I2S3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO + * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); +} +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n + * CFGR USBPRE LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); +} +#endif /* USB_OTG_FS || USB */ + +/** + * @brief Get ADCx clock source + * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) + * + * (*) value not defined in all devices + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 (*) + * @arg @ref LL_RCC_PLL_MUL_3 (*) + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 (*) + * @arg @ref LL_RCC_PLL_MUL_10 (*) + * @arg @ref LL_RCC_PLL_MUL_11 (*) + * @arg @ref LL_RCC_PLL_MUL_12 (*) + * @arg @ref LL_RCC_PLL_MUL_13 (*) + * @arg @ref LL_RCC_PLL_MUL_14 (*) + * @arg @ref LL_RCC_PLL_MUL_15 (*) + * @arg @ref LL_RCC_PLL_MUL_16 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, + (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); +#if defined(RCC_CFGR2_PREDIV1) +#if defined(RCC_CFGR2_PREDIV1SRC) + MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), + (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); +#else + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); +#endif /*RCC_CFGR2_PREDIV1SRC*/ +#endif /*RCC_CFGR2_PREDIV1*/ +} + +/** + * @brief Configure PLL clock source + * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n + * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ +#if defined(RCC_CFGR2_PREDIV1SRC) + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); +#endif /* RCC_CFGR2_PREDIV1SRC */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n + * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); + uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); + return (uint32_t)(pllsrc | predivsrc); +#else + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +#endif /*RCC_CFGR2_PREDIV1SRC*/ +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 (*) + * @arg @ref LL_RCC_PLL_MUL_3 (*) + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 (*) + * @arg @ref LL_RCC_PLL_MUL_10 (*) + * @arg @ref LL_RCC_PLL_MUL_11 (*) + * @arg @ref LL_RCC_PLL_MUL_12 (*) + * @arg @ref LL_RCC_PLL_MUL_13 (*) + * @arg @ref LL_RCC_PLL_MUL_14 (*) + * @arg @ref LL_RCC_PLL_MUL_15 (*) + * @arg @ref LL_RCC_PLL_MUL_16 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); +} + +/** + * @brief Get PREDIV1 division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n + * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 (*) + * @arg @ref LL_RCC_PREDIV_DIV_4 (*) + * @arg @ref LL_RCC_PREDIV_DIV_5 (*) + * @arg @ref LL_RCC_PREDIV_DIV_6 (*) + * @arg @ref LL_RCC_PREDIV_DIV_7 (*) + * @arg @ref LL_RCC_PREDIV_DIV_8 (*) + * @arg @ref LL_RCC_PREDIV_DIV_9 (*) + * @arg @ref LL_RCC_PREDIV_DIV_10 (*) + * @arg @ref LL_RCC_PREDIV_DIV_11 (*) + * @arg @ref LL_RCC_PREDIV_DIV_12 (*) + * @arg @ref LL_RCC_PREDIV_DIV_13 (*) + * @arg @ref LL_RCC_PREDIV_DIV_14 (*) + * @arg @ref LL_RCC_PREDIV_DIV_15 (*) + * @arg @ref LL_RCC_PREDIV_DIV_16 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ +#if defined(RCC_CFGR2_PREDIV1) + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); +#else + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos); +#endif /*RCC_CFGR2_PREDIV1*/ +} + +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); +} + +/** + * @brief Configure PLLI2S used for I2S Domain + * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n + * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @param Multiplicator This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); +} + +/** + * @brief Get PLLI2S Multiplication Factor + * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); +} + +/** + * @} + */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** @defgroup RCC_LL_EF_PLL2 PLL2 + * @{ + */ + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); +} + +/** + * @brief Configure PLL2 used for PLL2 Domain + * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n + * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @param Multiplicator This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); +} + +/** + * @brief Get PLL2 Multiplication Factor + * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); +} + +/** + * @} + */ +#endif /* RCC_PLL2_SUPPORT */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(RCC_CFGR2_I2S2SRC) +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#endif /* RCC_CFGR2_I2S2SRC */ +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_RCC_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h index 9b38916..d943686 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h @@ -1,1003 +1,1000 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_rtc.h - * @author MCD Application Team - * @brief Header file of RTC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_RTC_H -#define __STM32F1xx_LL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined(RTC) - -/** @defgroup RTC_LL RTC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_Private_Macros RTC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure - * @{ - */ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetAsynchPrescaler(). */ - - uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin. - This parameter can be a value of @ref LL_RTC_Output_Source - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetOutputSource(). */ - -} LL_RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hours. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ -} LL_RTC_TimeTypeDef; - - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - -} LL_RTC_AlarmTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants - * @{ - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EC_FORMAT FORMAT - * @{ - */ -#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RTC_LL_EC_BKP BACKUP - * @{ - */ -#if RTC_BKP_NUMBER > 0 -#define LL_RTC_BKP_DR1 (0x00000001U) -#define LL_RTC_BKP_DR2 (0x00000002U) -#define LL_RTC_BKP_DR3 (0x00000003U) -#define LL_RTC_BKP_DR4 (0x00000004U) -#define LL_RTC_BKP_DR5 (0x00000005U) -#define LL_RTC_BKP_DR6 (0x00000006U) -#define LL_RTC_BKP_DR7 (0x00000007U) -#define LL_RTC_BKP_DR8 (0x00000008U) -#define LL_RTC_BKP_DR9 (0x00000009U) -#define LL_RTC_BKP_DR10 (0x0000000AU) -#endif /* RTC_BKP_NUMBER > 0 */ -#if RTC_BKP_NUMBER > 10 -#define LL_RTC_BKP_DR11 (0x00000010U) -#define LL_RTC_BKP_DR12 (0x00000011U) -#define LL_RTC_BKP_DR13 (0x00000012U) -#define LL_RTC_BKP_DR14 (0x00000013U) -#define LL_RTC_BKP_DR15 (0x00000014U) -#define LL_RTC_BKP_DR16 (0x00000015U) -#define LL_RTC_BKP_DR17 (0x00000016U) -#define LL_RTC_BKP_DR18 (0x00000017U) -#define LL_RTC_BKP_DR19 (0x00000018U) -#define LL_RTC_BKP_DR20 (0x00000019U) -#define LL_RTC_BKP_DR21 (0x0000001AU) -#define LL_RTC_BKP_DR22 (0x0000001BU) -#define LL_RTC_BKP_DR23 (0x0000001CU) -#define LL_RTC_BKP_DR24 (0x0000001DU) -#define LL_RTC_BKP_DR25 (0x0000001EU) -#define LL_RTC_BKP_DR26 (0x0000001FU) -#define LL_RTC_BKP_DR27 (0x00000020U) -#define LL_RTC_BKP_DR28 (0x00000021U) -#define LL_RTC_BKP_DR29 (0x00000022U) -#define LL_RTC_BKP_DR30 (0x00000023U) -#define LL_RTC_BKP_DR31 (0x00000024U) -#define LL_RTC_BKP_DR32 (0x00000025U) -#define LL_RTC_BKP_DR33 (0x00000026U) -#define LL_RTC_BKP_DR34 (0x00000027U) -#define LL_RTC_BKP_DR35 (0x00000028U) -#define LL_RTC_BKP_DR36 (0x00000029U) -#define LL_RTC_BKP_DR37 (0x0000002AU) -#define LL_RTC_BKP_DR38 (0x0000002BU) -#define LL_RTC_BKP_DR39 (0x0000002CU) -#define LL_RTC_BKP_DR40 (0x0000002DU) -#define LL_RTC_BKP_DR41 (0x0000002EU) -#define LL_RTC_BKP_DR42 (0x0000002FU) -#endif /* RTC_BKP_NUMBER > 10 */ - -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level - * @{ - */ -#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ -#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ - -/** - * @} - */ - -/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin - * @{ - */ -#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */ -#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */ -#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup RTC_LL_EM_Convert Convert helper Macros - * @{ - */ - -/** - * @brief Helper macro to convert a value from 2 digit decimal format to BCD format - * @param __VALUE__ Byte to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) - -/** - * @brief Helper macro to convert a value from BCD format to 2 digit decimal format - * @param __VALUE__ BCD value to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Set Asynchronous prescaler factor - * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n - * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n - * @param RTCx RTC Instance - * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) -{ - MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16)); - MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL)); -} - -/** - * @brief Get Asynchronous prescaler factor - * @rmtoll DIVH DIV LL_RTC_GetDivider\n - * @rmtoll DIVL DIV LL_RTC_GetDivider\n - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx) -{ - register uint16_t Highprescaler = 0, Lowprescaler = 0; - Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV); - Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV); - - return (((uint32_t) Highprescaler << 16U) | Lowprescaler); -} - -/** - * @brief Set Output Source - * @rmtoll RTCCR CCO LL_RTC_SetOutputSource - * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource - * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource - * @param BKPx BKP Instance - * @param OutputSource This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK - * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM - * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource) -{ - MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource); -} - -/** - * @brief Get Output Source - * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource - * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource - * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource - * @param BKPx BKP Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK - * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM - * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND - */ -__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx) -{ - return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS))); -} - -/** - * @brief Enable the write protection for RTC registers. - * @rmtoll CRL CNF LL_RTC_EnableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF); -} - -/** - * @brief Disable the write protection for RTC registers. - * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRL, RTC_CRL_CNF); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Time Time - * @{ - */ - -/** - * @brief Set time counter in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) - * @rmtoll CNTH CNT LL_RTC_TIME_Set\n - * CNTL CNT LL_RTC_TIME_Set\n - * @param RTCx RTC Instance - * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter) -{ - /* Set RTC COUNTER MSB word */ - WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); -} - -/** - * @brief Get time counter in BCD format - * @rmtoll CNTH CNT LL_RTC_TIME_Get\n - * CNTL CNT LL_RTC_TIME_Get\n - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) -{ - register uint16_t high = 0, low = 0; - - high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT); - low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT); - return ((uint32_t)(((uint32_t) high << 16U) | low)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_ALARM ALARM - * @{ - */ - -/** - * @brief Set Alarm Counter - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n - * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n - * @param RTCx RTC Instance - * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter) -{ - /* Set RTC COUNTER MSB word */ - WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); -} - -/** - * @brief Get Alarm Counter - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll ALRH ALR LL_RTC_ALARM_Get\n - * @rmtoll ALRL ALR LL_RTC_ALARM_Get\n - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx) -{ - register uint16_t high = 0, low = 0; - - high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR); - low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR); - - return (((uint32_t) high << 16U) | low); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Tamper Tamper - * @{ - */ - -/** - * @brief Enable RTC_TAMPx input detection - * @rmtoll CR TPE LL_RTC_TAMPER_Enable\n - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx) -{ - SET_BIT(BKPx->CR, BKP_CR_TPE); -} - -/** - * @brief Disable RTC_TAMPx Tamper - * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx) -{ - CLEAR_BIT(BKP->CR, BKP_CR_TPE); -} - -/** - * @brief Enable Active level for Tamper input - * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n - * @param BKPx BKP Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper) -{ - MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper); -} - -/** - * @brief Disable Active level for Tamper input - * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n - * @retval None - */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx) -{ - return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @rmtoll BKPDR DR LL_RTC_BKP_SetRegister - * @param BKPx BKP Instance - * @param BackupRegister This parameter can be one of the following values: - * @arg @ref LL_RTC_BKP_DR1 - * @arg @ref LL_RTC_BKP_DR2 - * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 - * @arg @ref LL_RTC_BKP_DR5 - * @arg @ref LL_RTC_BKP_DR6 - * @arg @ref LL_RTC_BKP_DR7 - * @arg @ref LL_RTC_BKP_DR8 - * @arg @ref LL_RTC_BKP_DR9 - * @arg @ref LL_RTC_BKP_DR10 - * @arg @ref LL_RTC_BKP_DR11 (*) - * @arg @ref LL_RTC_BKP_DR12 (*) - * @arg @ref LL_RTC_BKP_DR13 (*) - * @arg @ref LL_RTC_BKP_DR14 (*) - * @arg @ref LL_RTC_BKP_DR15 (*) - * @arg @ref LL_RTC_BKP_DR16 (*) - * @arg @ref LL_RTC_BKP_DR17 (*) - * @arg @ref LL_RTC_BKP_DR18 (*) - * @arg @ref LL_RTC_BKP_DR19 (*) - * @arg @ref LL_RTC_BKP_DR20 (*) - * @arg @ref LL_RTC_BKP_DR21 (*) - * @arg @ref LL_RTC_BKP_DR22 (*) - * @arg @ref LL_RTC_BKP_DR23 (*) - * @arg @ref LL_RTC_BKP_DR24 (*) - * @arg @ref LL_RTC_BKP_DR25 (*) - * @arg @ref LL_RTC_BKP_DR26 (*) - * @arg @ref LL_RTC_BKP_DR27 (*) - * @arg @ref LL_RTC_BKP_DR28 (*) - * @arg @ref LL_RTC_BKP_DR29 (*) - * @arg @ref LL_RTC_BKP_DR30 (*) - * @arg @ref LL_RTC_BKP_DR31 (*) - * @arg @ref LL_RTC_BKP_DR32 (*) - * @arg @ref LL_RTC_BKP_DR33 (*) - * @arg @ref LL_RTC_BKP_DR34 (*) - * @arg @ref LL_RTC_BKP_DR35 (*) - * @arg @ref LL_RTC_BKP_DR36 (*) - * @arg @ref LL_RTC_BKP_DR37 (*) - * @arg @ref LL_RTC_BKP_DR38 (*) - * @arg @ref LL_RTC_BKP_DR39 (*) - * @arg @ref LL_RTC_BKP_DR40 (*) - * @arg @ref LL_RTC_BKP_DR41 (*) - * @arg @ref LL_RTC_BKP_DR42 (*) - * (*) value not defined in all devices. - * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data) -{ - register uint32_t tmp = 0U; - - tmp = (uint32_t)BKP_BASE; - tmp += (BackupRegister * 4U); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @rmtoll BKPDR DR LL_RTC_BKP_GetRegister - * @param BKPx BKP Instance - * @param BackupRegister This parameter can be one of the following values: - * @arg @ref LL_RTC_BKP_DR1 - * @arg @ref LL_RTC_BKP_DR2 - * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 - * @arg @ref LL_RTC_BKP_DR5 - * @arg @ref LL_RTC_BKP_DR6 - * @arg @ref LL_RTC_BKP_DR7 - * @arg @ref LL_RTC_BKP_DR8 - * @arg @ref LL_RTC_BKP_DR9 - * @arg @ref LL_RTC_BKP_DR10 - * @arg @ref LL_RTC_BKP_DR11 (*) - * @arg @ref LL_RTC_BKP_DR12 (*) - * @arg @ref LL_RTC_BKP_DR13 (*) - * @arg @ref LL_RTC_BKP_DR14 (*) - * @arg @ref LL_RTC_BKP_DR15 (*) - * @arg @ref LL_RTC_BKP_DR16 (*) - * @arg @ref LL_RTC_BKP_DR17 (*) - * @arg @ref LL_RTC_BKP_DR18 (*) - * @arg @ref LL_RTC_BKP_DR19 (*) - * @arg @ref LL_RTC_BKP_DR20 (*) - * @arg @ref LL_RTC_BKP_DR21 (*) - * @arg @ref LL_RTC_BKP_DR22 (*) - * @arg @ref LL_RTC_BKP_DR23 (*) - * @arg @ref LL_RTC_BKP_DR24 (*) - * @arg @ref LL_RTC_BKP_DR25 (*) - * @arg @ref LL_RTC_BKP_DR26 (*) - * @arg @ref LL_RTC_BKP_DR27 (*) - * @arg @ref LL_RTC_BKP_DR28 (*) - * @arg @ref LL_RTC_BKP_DR29 (*) - * @arg @ref LL_RTC_BKP_DR30 (*) - * @arg @ref LL_RTC_BKP_DR31 (*) - * @arg @ref LL_RTC_BKP_DR32 (*) - * @arg @ref LL_RTC_BKP_DR33 (*) - * @arg @ref LL_RTC_BKP_DR34 (*) - * @arg @ref LL_RTC_BKP_DR35 (*) - * @arg @ref LL_RTC_BKP_DR36 (*) - * @arg @ref LL_RTC_BKP_DR37 (*) - * @arg @ref LL_RTC_BKP_DR38 (*) - * @arg @ref LL_RTC_BKP_DR39 (*) - * @arg @ref LL_RTC_BKP_DR40 (*) - * @arg @ref LL_RTC_BKP_DR41 (*) - * @arg @ref LL_RTC_BKP_DR42 (*) - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister) -{ - register uint32_t tmp = 0U; - - tmp = (uint32_t)BKP_BASE; - tmp += (BackupRegister * 4U); - - /* Read the specified register */ - return ((*(__IO uint32_t *)tmp) & BKP_DR1_D); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Calibration Calibration - * @{ - */ - -/** - * @brief Set the coarse digital calibration - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) - * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n - * @param BKPx RTC Instance - * @param Value value of coarse calibration expressed in ppm (coded on 5 bits) - * @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step. - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef *BKPx, uint32_t Value) -{ - MODIFY_REG(BKPx->RTCCR, BKP_RTCCR_CAL, Value); -} - -/** - * @brief Get the coarse digital calibration value - * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n - * @param BKPx BKP Instance - * @retval value of coarse calibration expressed in ppm (coded on 5 bits) - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx) -{ - return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL)); -} -/** - * @} - */ - -/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get RTC_TAMPI Interruption detection flag - * @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI - * @param BKPx BKP Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx) -{ - return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF)); -} - -/** - * @brief Clear RTC_TAMP Interruption detection flag - * @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI - * @param BKPx BKP Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx) -{ - SET_BIT(BKPx->CSR, BKP_CSR_CTI); -} - -/** - * @brief Get RTC_TAMPE Event detection flag - * @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE - * @param BKPx BKP Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx) -{ - return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF)); -} - -/** - * @brief Clear RTC_TAMPE Even detection flag - * @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE - * @param BKPx BKP Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx) -{ - SET_BIT(BKPx->CSR, BKP_CSR_CTE); -} - -/** - * @brief Get Alarm flag - * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF)); -} - -/** - * @brief Clear Alarm flag - * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF); -} - -/** - * @brief Get Registers synchronization flag - * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF)); -} - -/** - * @brief Clear Registers synchronization flag - * @rmtoll CRL RSF LL_RTC_ClearFlag_RS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF); -} - -/** - * @brief Get Registers OverFlow flag - * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF)); -} - -/** - * @brief Clear Registers OverFlow flag - * @rmtoll CRL OWF LL_RTC_ClearFlag_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF); -} - -/** - * @brief Get Registers synchronization flag - * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF)); -} - -/** - * @brief Clear Registers synchronization flag - * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF); -} - -/** - * @brief Get RTC Operation OFF status flag - * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Alarm interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_ALRIE); -} - -/** - * @brief Disable Alarm interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE); -} - -/** - * @brief Check if Alarm interrupt is enabled or not - * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE)); -} - -/** - * @brief Enable Second Interrupt interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_SECIE); -} - -/** - * @brief Disable Second interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE); -} - -/** - * @brief Check if Second interrupt is enabled or not - * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE)); -} - -/** - * @brief Enable OverFlow interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH OWIE LL_RTC_EnableIT_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_OWIE); -} - -/** - * @brief Disable OverFlow interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH OWIE LL_RTC_DisableIT_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE); -} - -/** - * @brief Check if OverFlow interrupt is enabled or not - * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE)); -} - -/** - * @brief Enable Tamper interrupt - * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP - * @param BKPx BKP Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx) -{ - SET_BIT(BKPx->CSR, BKP_CSR_TPIE); -} - -/** - * @brief Disable Tamper interrupt - * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP - * @param BKPx BKP Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx) -{ - CLEAR_BIT(BKPx->CSR, BKP_CSR_TPIE); -} - -/** - * @brief Check if all the TAMPER interrupts are enabled or not - * @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP - * @param BKPx BKP Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx) -{ - return (READ_BIT(BKPx->CSR, BKP_CSR_TPIE) == BKP_CSR_TPIE); -} -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); -void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); -ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); -void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); -ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter); -ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RTC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_RTC_H +#define __STM32F1xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin. + This parameter can be a value of @ref LL_RTC_Output_Source + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetOutputSource(). */ + +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ +} LL_RTC_TimeTypeDef; + + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#if RTC_BKP_NUMBER > 0 +#define LL_RTC_BKP_DR1 (0x00000001U) +#define LL_RTC_BKP_DR2 (0x00000002U) +#define LL_RTC_BKP_DR3 (0x00000003U) +#define LL_RTC_BKP_DR4 (0x00000004U) +#define LL_RTC_BKP_DR5 (0x00000005U) +#define LL_RTC_BKP_DR6 (0x00000006U) +#define LL_RTC_BKP_DR7 (0x00000007U) +#define LL_RTC_BKP_DR8 (0x00000008U) +#define LL_RTC_BKP_DR9 (0x00000009U) +#define LL_RTC_BKP_DR10 (0x0000000AU) +#endif /* RTC_BKP_NUMBER > 0 */ +#if RTC_BKP_NUMBER > 10 +#define LL_RTC_BKP_DR11 (0x00000010U) +#define LL_RTC_BKP_DR12 (0x00000011U) +#define LL_RTC_BKP_DR13 (0x00000012U) +#define LL_RTC_BKP_DR14 (0x00000013U) +#define LL_RTC_BKP_DR15 (0x00000014U) +#define LL_RTC_BKP_DR16 (0x00000015U) +#define LL_RTC_BKP_DR17 (0x00000016U) +#define LL_RTC_BKP_DR18 (0x00000017U) +#define LL_RTC_BKP_DR19 (0x00000018U) +#define LL_RTC_BKP_DR20 (0x00000019U) +#define LL_RTC_BKP_DR21 (0x0000001AU) +#define LL_RTC_BKP_DR22 (0x0000001BU) +#define LL_RTC_BKP_DR23 (0x0000001CU) +#define LL_RTC_BKP_DR24 (0x0000001DU) +#define LL_RTC_BKP_DR25 (0x0000001EU) +#define LL_RTC_BKP_DR26 (0x0000001FU) +#define LL_RTC_BKP_DR27 (0x00000020U) +#define LL_RTC_BKP_DR28 (0x00000021U) +#define LL_RTC_BKP_DR29 (0x00000022U) +#define LL_RTC_BKP_DR30 (0x00000023U) +#define LL_RTC_BKP_DR31 (0x00000024U) +#define LL_RTC_BKP_DR32 (0x00000025U) +#define LL_RTC_BKP_DR33 (0x00000026U) +#define LL_RTC_BKP_DR34 (0x00000027U) +#define LL_RTC_BKP_DR35 (0x00000028U) +#define LL_RTC_BKP_DR36 (0x00000029U) +#define LL_RTC_BKP_DR37 (0x0000002AU) +#define LL_RTC_BKP_DR38 (0x0000002BU) +#define LL_RTC_BKP_DR39 (0x0000002CU) +#define LL_RTC_BKP_DR40 (0x0000002DU) +#define LL_RTC_BKP_DR41 (0x0000002EU) +#define LL_RTC_BKP_DR42 (0x0000002FU) +#endif /* RTC_BKP_NUMBER > 10 */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ +#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ + +/** + * @} + */ + +/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */ +#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */ +#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n + * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16)); + MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL)); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll DIVH DIV LL_RTC_GetDivider\n + * @rmtoll DIVL DIV LL_RTC_GetDivider\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx) +{ + register uint16_t Highprescaler = 0, Lowprescaler = 0; + Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV); + Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV); + + return (((uint32_t) Highprescaler << 16U) | Lowprescaler); +} + +/** + * @brief Set Output Source + * @rmtoll RTCCR CCO LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource + * @param BKPx BKP Instance + * @param OutputSource This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource) +{ + MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource); +} + +/** + * @brief Get Output Source + * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource + * @param BKPx BKP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS))); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll CRL CNF LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time counter in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll CNTH CNT LL_RTC_TIME_Set\n + * CNTL CNT LL_RTC_TIME_Set\n + * @param RTCx RTC Instance + * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); +} + +/** + * @brief Get time counter in BCD format + * @rmtoll CNTH CNT LL_RTC_TIME_Get\n + * CNTL CNT LL_RTC_TIME_Get\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + register uint16_t high = 0, low = 0; + + high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT); + low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT); + return ((uint32_t)(((uint32_t) high << 16U) | low)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARM ALARM + * @{ + */ + +/** + * @brief Set Alarm Counter + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n + * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n + * @param RTCx RTC Instance + * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); +} + +/** + * @brief Get Alarm Counter + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll ALRH ALR LL_RTC_ALARM_Get\n + * @rmtoll ALRL ALR LL_RTC_ALARM_Get\n + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx) +{ + register uint16_t high = 0, low = 0; + + high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR); + low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR); + + return (((uint32_t) high << 16U) | low); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable RTC_TAMPx input detection + * @rmtoll CR TPE LL_RTC_TAMPER_Enable\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CR, BKP_CR_TPE); +} + +/** + * @brief Disable RTC_TAMPx Tamper + * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx) +{ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n + * @param BKPx BKP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper) +{ + MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @rmtoll BKPDR DR LL_RTC_BKP_SetRegister + * @param BKPx BKP Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 (*) + * @arg @ref LL_RTC_BKP_DR12 (*) + * @arg @ref LL_RTC_BKP_DR13 (*) + * @arg @ref LL_RTC_BKP_DR14 (*) + * @arg @ref LL_RTC_BKP_DR15 (*) + * @arg @ref LL_RTC_BKP_DR16 (*) + * @arg @ref LL_RTC_BKP_DR17 (*) + * @arg @ref LL_RTC_BKP_DR18 (*) + * @arg @ref LL_RTC_BKP_DR19 (*) + * @arg @ref LL_RTC_BKP_DR20 (*) + * @arg @ref LL_RTC_BKP_DR21 (*) + * @arg @ref LL_RTC_BKP_DR22 (*) + * @arg @ref LL_RTC_BKP_DR23 (*) + * @arg @ref LL_RTC_BKP_DR24 (*) + * @arg @ref LL_RTC_BKP_DR25 (*) + * @arg @ref LL_RTC_BKP_DR26 (*) + * @arg @ref LL_RTC_BKP_DR27 (*) + * @arg @ref LL_RTC_BKP_DR28 (*) + * @arg @ref LL_RTC_BKP_DR29 (*) + * @arg @ref LL_RTC_BKP_DR30 (*) + * @arg @ref LL_RTC_BKP_DR31 (*) + * @arg @ref LL_RTC_BKP_DR32 (*) + * @arg @ref LL_RTC_BKP_DR33 (*) + * @arg @ref LL_RTC_BKP_DR34 (*) + * @arg @ref LL_RTC_BKP_DR35 (*) + * @arg @ref LL_RTC_BKP_DR36 (*) + * @arg @ref LL_RTC_BKP_DR37 (*) + * @arg @ref LL_RTC_BKP_DR38 (*) + * @arg @ref LL_RTC_BKP_DR39 (*) + * @arg @ref LL_RTC_BKP_DR40 (*) + * @arg @ref LL_RTC_BKP_DR41 (*) + * @arg @ref LL_RTC_BKP_DR42 (*) + * (*) value not defined in all devices. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll BKPDR DR LL_RTC_BKP_GetRegister + * @param BKPx BKP Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 (*) + * @arg @ref LL_RTC_BKP_DR12 (*) + * @arg @ref LL_RTC_BKP_DR13 (*) + * @arg @ref LL_RTC_BKP_DR14 (*) + * @arg @ref LL_RTC_BKP_DR15 (*) + * @arg @ref LL_RTC_BKP_DR16 (*) + * @arg @ref LL_RTC_BKP_DR17 (*) + * @arg @ref LL_RTC_BKP_DR18 (*) + * @arg @ref LL_RTC_BKP_DR19 (*) + * @arg @ref LL_RTC_BKP_DR20 (*) + * @arg @ref LL_RTC_BKP_DR21 (*) + * @arg @ref LL_RTC_BKP_DR22 (*) + * @arg @ref LL_RTC_BKP_DR23 (*) + * @arg @ref LL_RTC_BKP_DR24 (*) + * @arg @ref LL_RTC_BKP_DR25 (*) + * @arg @ref LL_RTC_BKP_DR26 (*) + * @arg @ref LL_RTC_BKP_DR27 (*) + * @arg @ref LL_RTC_BKP_DR28 (*) + * @arg @ref LL_RTC_BKP_DR29 (*) + * @arg @ref LL_RTC_BKP_DR30 (*) + * @arg @ref LL_RTC_BKP_DR31 (*) + * @arg @ref LL_RTC_BKP_DR32 (*) + * @arg @ref LL_RTC_BKP_DR33 (*) + * @arg @ref LL_RTC_BKP_DR34 (*) + * @arg @ref LL_RTC_BKP_DR35 (*) + * @arg @ref LL_RTC_BKP_DR36 (*) + * @arg @ref LL_RTC_BKP_DR37 (*) + * @arg @ref LL_RTC_BKP_DR38 (*) + * @arg @ref LL_RTC_BKP_DR39 (*) + * @arg @ref LL_RTC_BKP_DR40 (*) + * @arg @ref LL_RTC_BKP_DR41 (*) + * @arg @ref LL_RTC_BKP_DR42 (*) + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return ((*(__IO uint32_t *)tmp) & BKP_DR1_D); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set the coarse digital calibration + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param BKPx RTC Instance + * @param Value value of coarse calibration expressed in ppm (coded on 5 bits) + * @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step. + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef *BKPx, uint32_t Value) +{ + MODIFY_REG(BKPx->RTCCR, BKP_RTCCR_CAL, Value); +} + +/** + * @brief Get the coarse digital calibration value + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param BKPx BKP Instance + * @retval value of coarse calibration expressed in ppm (coded on 5 bits) + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL)); +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get RTC_TAMPI Interruption detection flag + * @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF)); +} + +/** + * @brief Clear RTC_TAMP Interruption detection flag + * @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR, BKP_CSR_CTI); +} + +/** + * @brief Get RTC_TAMPE Event detection flag + * @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF)); +} + +/** + * @brief Clear RTC_TAMPE Even detection flag + * @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR, BKP_CSR_CTE); +} + +/** + * @brief Get Alarm flag + * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF)); +} + +/** + * @brief Clear Alarm flag + * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF); +} + +/** + * @brief Get Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF)); +} + +/** + * @brief Clear Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_ClearFlag_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF); +} + +/** + * @brief Get RTC Operation OFF status flag + * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Disable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Check if Alarm interrupt is enabled or not + * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE)); +} + +/** + * @brief Enable Second Interrupt interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Disable Second interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Check if Second interrupt is enabled or not + * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE)); +} + +/** + * @brief Enable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_EnableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Disable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_DisableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Check if OverFlow interrupt is enabled or not + * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE)); +} + +/** + * @brief Enable Tamper interrupt + * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR, BKP_CSR_TPIE); +} + +/** + * @brief Disable Tamper interrupt + * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx) +{ + CLEAR_BIT(BKPx->CSR, BKP_CSR_TPIE); +} + +/** + * @brief Check if all the TAMPER interrupts are enabled or not + * @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR, BKP_CSR_TPIE) == BKP_CSR_TPIE); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter); +ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_RTC_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h index b22f8df..0aba37b 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h @@ -1,574 +1,575 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_SYSTEM_H -#define __STM32F1xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - - - -/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment - * @{ - */ -#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ -#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ -#if defined(DBGMCU_CR_DBG_TIM5_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM5_STOP */ -#if defined(DBGMCU_CR_DBG_TIM6_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM6_STOP */ -#if defined(DBGMCU_CR_DBG_TIM7_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM7_STOP */ -#if defined(DBGMCU_CR_DBG_TIM12_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM12_STOP */ -#if defined(DBGMCU_CR_DBG_TIM13_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM13_STOP */ -#if defined(DBGMCU_CR_DBG_TIM14_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM14_STOP */ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) -#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ -#if defined(DBGMCU_CR_DBG_CAN1_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ -#endif /* DBGMCU_CR_DBG_CAN1_STOP */ -#if defined(DBGMCU_CR_DBG_CAN2_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ -#endif /* DBGMCU_CR_DBG_CAN2_STOP */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#if defined(DBGMCU_CR_DBG_TIM8_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_CAN1_STOP */ -#if defined(DBGMCU_CR_DBG_TIM9_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM9_STOP */ -#if defined(DBGMCU_CR_DBG_TIM10_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM10_STOP */ -#if defined(DBGMCU_CR_DBG_TIM11_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM11_STOP */ -#if defined(DBGMCU_CR_DBG_TIM15_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM15_STOP */ -#if defined(DBGMCU_CR_DBG_TIM16_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM16_STOP */ -#if defined(DBGMCU_CR_DBG_TIM17_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ -#endif /* DBGMCU_CR_DBG_TIM17_STOP */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#if defined(FLASH_ACR_LATENCY) -#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ -#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ -#else -#endif /* FLASH_ACR_LATENCY */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - - - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @note For Low Density devices, the device ID is 0x412 - * @note For Medium Density devices, the device ID is 0x410 - * @note For High Density devices, the device ID is 0x414 - * @note For XL Density devices, the device ID is 0x430 - * @note For Connectivity Line devices, the device ID is 0x418 - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - For example, it is read as revA -> 0x1000,for Low Density devices - For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices - For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices - For example, it is read as revA or 1 -> 0x1003,for XL Density devices - For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Set Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment - * @param PinAssignment This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) -{ - MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); -} - -/** - * @brief Get Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment - * @retval Returned value can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->CR, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->CR, Periphs); -} - -/** - * @brief Freeze APB2 peripherals - * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->CR, Periphs); -} - -/** - * @brief Unfreeze APB2 peripherals - * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->CR, Periphs); -} -/** - * @} - */ - -#if defined(FLASH_ACR_LATENCY) -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Disable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Check if Prefetch buffer is enabled - * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); -} - -#endif /* FLASH_ACR_LATENCY */ -/** - * @brief Enable Flash Half Cycle Access - * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); -} - -/** - * @brief Disable Flash Half Cycle Access - * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); -} - -/** - * @brief Check if Flash Half Cycle Access is enabled or not - * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (FLASH) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_SYSTEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_SYSTEM_H +#define __STM32F1xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + + + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#if defined(DBGMCU_CR_DBG_TIM5_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM5_STOP */ +#if defined(DBGMCU_CR_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM6_STOP */ +#if defined(DBGMCU_CR_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM7_STOP */ +#if defined(DBGMCU_CR_DBG_TIM12_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM12_STOP */ +#if defined(DBGMCU_CR_DBG_TIM13_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM13_STOP */ +#if defined(DBGMCU_CR_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM14_STOP */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ +#if defined(DBGMCU_CR_DBG_CAN1_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#endif /* DBGMCU_CR_DBG_CAN1_STOP */ +#if defined(DBGMCU_CR_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_CR_DBG_CAN2_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_CR_DBG_TIM8_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_CAN1_STOP */ +#if defined(DBGMCU_CR_DBG_TIM9_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM9_STOP */ +#if defined(DBGMCU_CR_DBG_TIM10_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM10_STOP */ +#if defined(DBGMCU_CR_DBG_TIM11_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM11_STOP */ +#if defined(DBGMCU_CR_DBG_TIM15_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM15_STOP */ +#if defined(DBGMCU_CR_DBG_TIM16_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM16_STOP */ +#if defined(DBGMCU_CR_DBG_TIM17_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM17_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#if defined(FLASH_ACR_LATENCY) +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +#else +#endif /* FLASH_ACR_LATENCY */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For Low Density devices, the device ID is 0x412 + * @note For Medium Density devices, the device ID is 0x410 + * @note For High Density devices, the device ID is 0x414 + * @note For XL Density devices, the device ID is 0x430 + * @note For Connectivity Line devices, the device ID is 0x418 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as revA -> 0x1000,for Low Density devices + For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices + For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices + For example, it is read as revA or 1 -> 0x1003,for XL Density devices + For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->CR, Periphs); +} +/** + * @} + */ + +#if defined(FLASH_ACR_LATENCY) +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + +#endif /* FLASH_ACR_LATENCY */ +/** + * @brief Enable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Disable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Check if Flash Half Cycle Access is enabled or not + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_SYSTEM_H */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h new file mode 100755 index 0000000..d54a00e --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h @@ -0,0 +1,3901 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_TIM_H +#define __STM32F1xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U /* 6: TIMx_CH4 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U /* 6: OC4M, OC4FE, OC4PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U /* 6: CC4S, IC4PSC, IC4F */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U /* 6: CC4P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U /* 6: OIS4 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + * @{ + */ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + * @{ + */ +#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS1N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS1N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_TIM_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h index a8a4c23..6d37061 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h @@ -1,2569 +1,2569 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_usart.h - * @author MCD Application Team - * @brief Header file of USART LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_USART_H -#define __STM32F1xx_LL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) - -/** @defgroup USART_LL USART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_Private_Macros USART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_ES_INIT USART Exported Init structures - * @{ - */ - -/** - * @brief LL USART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ - - uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. - This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ - -} LL_USART_InitTypeDef; - -/** - * @brief LL USART Clock Init Structure definition - */ -typedef struct -{ - uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_CLOCK. - - USART HW configuration can be modified afterwards using unitary functions - @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). - For more details, refer to description of this function. */ - - uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_LL_EC_POLARITY. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). - For more details, refer to description of this function. */ - - uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_LL_EC_PHASE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). - For more details, refer to description of this function. */ - - uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). - For more details, refer to description of this function. */ - -} LL_USART_ClockInitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_USART_ReadReg function - * @{ - */ -#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ -#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ -#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ -#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ -#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ -#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ -#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ -#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ -#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */ -#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions - * @{ - */ -#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ -#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DIRECTION Communication Direction - * @{ - */ -#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ -#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling - * @{ - */ -#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#if defined(USART_CR1_OVER8) -#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -#endif /* USART_OverSampling_Feature */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EC_CLOCK Clock Signal - * @{ - */ - -#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ -#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse - * @{ - */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ -#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ -#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ -#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ -#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ -#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power - * @{ - */ -#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ -#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length - * @{ - */ -#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ -#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Macros USART Exported Macros - * @{ - */ - -/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case - */ -#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) -#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ - (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case - */ -#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) -#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100) -/* USART BRR = mantissa + overflow + fraction - = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_LL_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief USART Enable - * @rmtoll CR1 UE LL_USART_Enable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief USART Disable (all USART prescalers and outputs are disabled) - * @note When USART is disabled, USART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the USART is kept, but all the status - * flags, in the USARTx_SR are set to their default values. - * @rmtoll CR1 UE LL_USART_Disable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if USART is enabled - * @rmtoll CR1 UE LL_USART_IsEnabled - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); -} - -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_USART_EnableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_USART_DisableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_USART_EnableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_USART_DisableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_SetTransferDirection\n - * CR1 TE LL_USART_SetTransferDirection - * @param USARTx USART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_GetTransferDirection\n - * CR1 TE LL_USART_GetTransferDirection - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled). - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (9th or 8th bit depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_USART_SetParity\n - * CR1 PCE LL_USART_SetParity - * @param USARTx USART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_USART_GetParity\n - * CR1 PCE LL_USART_GetParity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod - * @param USARTx USART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_USART_SetDataWidth - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_USART_GetDataWidth - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); -} - -#if defined(USART_CR1_OVER8) -/** - * @brief Set Oversampling to 8-bit or 16-bit mode - * @rmtoll CR1 OVER8 LL_USART_SetOverSampling - * @param USARTx USART Instance - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); -} - -/** - * @brief Return Oversampling mode - * @rmtoll CR1 OVER8 LL_USART_GetOverSampling - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); -} - -#endif /* USART_OverSampling_Feature */ -/** - * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput - * @param USARTx USART Instance - * @param LastBitClockPulse This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); -} - -/** - * @brief Retrieve Clock pulse of the last data bit output configuration - * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); -} - -/** - * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_SetClockPhase - * @param USARTx USART Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); -} - -/** - * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_GetClockPhase - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); -} - -/** - * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_SetClockPolarity - * @param USARTx USART Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); -} - -/** - * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_GetClockPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); -} - -/** - * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function - * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function - * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function - * @rmtoll CR2 CPHA LL_USART_ConfigClock\n - * CR2 CPOL LL_USART_ConfigClock\n - * CR2 LBCL LL_USART_ConfigClock - * @param USARTx USART Instance - * @param Phase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @param LBCPOutput This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); -} - -/** - * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_USART_SetStopBitsLength - * @param USARTx USART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_USART_GetStopBitsLength - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_USART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_USART_SetParity() function - * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_USART_ConfigCharacter\n - * CR1 PCE LL_USART_ConfigCharacter\n - * CR1 M LL_USART_ConfigCharacter\n - * CR2 STOP LL_USART_ConfigCharacter - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Set Address of the USART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @rmtoll CR2 ADD LL_USART_SetNodeAddress - * @param USARTx USART Instance - * @param NodeAddress 4 bit Address of the USART node. - * @retval None - */ -__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); -} - -/** - * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. - * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * @rmtoll CR2 ADD LL_USART_GetNodeAddress - * @param USARTx USART Instance - * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); -} - -/** - * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n - * CR3 CTSE LL_USART_SetHWFlowCtrl - * @param USARTx USART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n - * CR3 CTSE LL_USART_GetHWFlowCtrl - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - -#if defined(USART_CR3_ONEBIT) -/** - * @brief Enable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Disable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Indicate if One bit sampling method is enabled - * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); -} -#endif /* USART_OneBitSampling_Feature */ - -#if defined(USART_CR1_OVER8) -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, - uint32_t BaudRate) -{ - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); - } - else - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); - } -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) -{ - uint32_t usartdiv = 0x0U; - uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - if ((usartdiv & 0xFFF7U) != 0U) - { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; - brrresult = (PeriphClk * 2U) / usartdiv; - } - } - else - { - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - } - return (brrresult); -} -#else -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate) -{ - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk) -{ - uint32_t usartdiv = 0x0U; - uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - return (brrresult); -} -#endif /* USART_OverSampling_Feature */ - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature - * @{ - */ - -/** - * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_EnableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_DisableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_IsEnabledIrda - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); -} - -/** - * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode - * @param USARTx USART Instance - * @param PowerMode This parameter can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_IRDA_POWER_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); -} - -/** - * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); -} - -/** - * @brief Set Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); -} - -/** - * @brief Return Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler - * @param USARTx USART Instance - * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature - * @{ - */ - -/** - * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); -} - -/** - * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_EnableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_DisableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); -} - -/** - * @brief Set Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); -} - -/** - * @brief Return Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler - * @param USARTx USART Instance - * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime - * @param USARTx USART Instance - * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); -} - -/** - * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime - * @param USARTx USART Instance - * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature - * @{ - */ - -/** - * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen - * @param USARTx USART Instance - * @param LINBDLength This parameter can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); -} - -/** - * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); -} - -/** - * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_EnableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_DisableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services - * @{ - */ - -/** - * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) - * @note In UART mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Asynchronous Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n - * CR2 CLKEN LL_USART_ConfigAsyncMode\n - * CR3 SCEN LL_USART_ConfigAsyncMode\n - * CR3 IREN LL_USART_ConfigAsyncMode\n - * CR3 HDSEL LL_USART_ConfigAsyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) -{ - /* In Asynchronous mode, the following bits must be kept cleared: - - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Synchronous Mode - * @note In Synchronous mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * @note Other remaining configurations items related to Synchronous Mode - * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n - * CR2 CLKEN LL_USART_ConfigSyncMode\n - * CR3 SCEN LL_USART_ConfigSyncMode\n - * CR3 IREN LL_USART_ConfigSyncMode\n - * CR3 HDSEL LL_USART_ConfigSyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) -{ - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); - /* set the UART/USART in Synchronous mode */ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in LIN Mode - * @note In LIN mode, the following bits must be kept cleared: - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function - * @note Other remaining configurations items related to LIN Mode - * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n - * CR2 STOP LL_USART_ConfigLINMode\n - * CR2 LINEN LL_USART_ConfigLINMode\n - * CR3 IREN LL_USART_ConfigLINMode\n - * CR3 SCEN LL_USART_ConfigLINMode\n - * CR3 HDSEL LL_USART_ConfigLINMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) -{ - /* In LIN mode, the following bits must be kept cleared: - - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); - /* Set the UART/USART in LIN mode */ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode - * @note In Half Duplex mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function - * @note Other remaining configurations items related to Half Duplex Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n - * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n - * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n - * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n - * CR3 IREN LL_USART_ConfigHalfDuplexMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) -{ - /* In Half Duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); - /* set the UART/USART in Half Duplex mode */ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Smartcard Mode - * @note In Smartcard mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also configures Stop bits to 1.5 bits and - * sets the USART in Smartcard mode (SCEN bit). - * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function - * @note Other remaining configurations items related to Smartcard Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n - * CR2 STOP LL_USART_ConfigSmartcardMode\n - * CR2 CLKEN LL_USART_ConfigSmartcardMode\n - * CR3 HDSEL LL_USART_ConfigSmartcardMode\n - * CR3 SCEN LL_USART_ConfigSmartcardMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) -{ - /* In Smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* Configure Stop bits to 1.5 bits */ - /* Synchronous mode is activated by default */ - SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); - /* set the UART/USART in Smartcard mode */ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Irda Mode - * @note In IRDA mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function - * @note Other remaining configurations items related to Irda Mode - * (as Baud Rate, Word length, Power mode, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n - * CR2 CLKEN LL_USART_ConfigIrdaMode\n - * CR2 STOP LL_USART_ConfigIrdaMode\n - * CR3 SCEN LL_USART_ConfigIrdaMode\n - * CR3 HDSEL LL_USART_ConfigIrdaMode\n - * CR3 IREN LL_USART_ConfigIrdaMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) -{ - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); - /* set the UART/USART in IRDA mode */ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Multi processor Mode - * (several USARTs connected in a network, one of the USARTs can be the master, - * its TX output connected to the RX inputs of the other slaves USARTs). - * @note In MultiProcessor mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Multi processor Mode - * (as Baud Rate, Wake Up Method, Node address, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n - * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n - * CR3 SCEN LL_USART_ConfigMultiProcessMode\n - * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n - * CR3 IREN LL_USART_ConfigMultiProcessMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) -{ - /* In Multi Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the USART Parity Error Flag is set or not - * @rmtoll SR PE LL_USART_IsActiveFlag_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); -} - -/** - * @brief Check if the USART Framing Error Flag is set or not - * @rmtoll SR FE LL_USART_IsActiveFlag_FE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); -} - -/** - * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll SR NF LL_USART_IsActiveFlag_NE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); -} - -/** - * @brief Check if the USART OverRun Error Flag is set or not - * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); -} - -/** - * @brief Check if the USART IDLE line detected Flag is set or not - * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); -} - -/** - * @brief Check if the USART Read Data Register Not Empty Flag is set or not - * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); -} - -/** - * @brief Check if the USART Transmission Complete Flag is set or not - * @rmtoll SR TC LL_USART_IsActiveFlag_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); -} - -/** - * @brief Check if the USART Transmit Data Register Empty Flag is set or not - * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); -} - -/** - * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); -} - -/** - * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); -} - -/** - * @brief Check if the USART Send Break Flag is set or not - * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); -} - -/** - * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not - * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); -} - -/** - * @brief Clear Parity Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * NE, FE, ORE, IDLE would also be cleared. - * @rmtoll SR PE LL_USART_ClearFlag_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Framing Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, ORE, IDLE would also be cleared. - * @rmtoll SR FE LL_USART_ClearFlag_FE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Noise detected Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, FE, ORE, IDLE would also be cleared. - * @rmtoll SR NF LL_USART_ClearFlag_NE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear OverRun Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, FE, IDLE would also be cleared. - * @rmtoll SR ORE LL_USART_ClearFlag_ORE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear IDLE line detected Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, FE, ORE would also be cleared. - * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll SR TC LL_USART_ClearFlag_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_TC)); -} - -/** - * @brief Clear RX Not Empty Flag - * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); -} - -/** - * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll SR LBD LL_USART_ClearFlag_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_LBD)); -} - -/** - * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll SR CTS LL_USART_ClearFlag_nCTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Enable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_EnableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Enable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_EnableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. - * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Disable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_DisableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Disable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_DisableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. - * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Check if the USART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); -} - -/** - * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. - * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); -} - -/** - * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); -} - -/** - * @brief Check if the USART TX Empty Interrupt is enabled or disabled. - * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); -} - -/** - * @brief Check if the USART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); -} - -/** - * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); -} - -/** - * @brief Check if the USART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); -} - -/** - * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); -} - -/** - * @brief Enable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll DR DR LL_USART_DMA_GetRegAddr - * @note Address of Data Register is valid for both Transmit and Receive transfers. - * @param USARTx USART Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) -{ - /* return address of DR register */ - return ((uint32_t) & (USARTx->DR)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll DR DR LL_USART_ReceiveData8 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) -{ - return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll DR DR LL_USART_ReceiveData9 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) -{ - return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll DR DR LL_USART_TransmitData8 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) -{ - USARTx->DR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll DR DR LL_USART_TransmitData9 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) -{ - USARTx->DR = Value & 0x1FFU; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request Break sending - * @rmtoll CR1 SBK LL_USART_RequestBreakSending - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_SBK); -} - -/** - * @brief Put USART in Mute mode - * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RWU); -} - -/** - * @brief Put USART in Active mode - * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_USART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_USART_H +#define __STM32F1xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ +#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ +#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ +#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ +#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ +#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ +#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */ +#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#if defined(USART_CR1_OVER8) +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +#endif /* USART_OverSampling_Feature */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8\ + + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\ + + 50) / 100) +/* USART BRR = mantissa + overflow + fraction + = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_SR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +#if defined(USART_CR1_OVER8) +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +#endif /* USART_OverSampling_Feature */ +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @rmtoll CR2 ADD LL_USART_SetNodeAddress + * @param USARTx USART Instance + * @param NodeAddress 4 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); +} + +/** + * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. + * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +#if defined(USART_CR3_ONEBIT) +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +} +#endif /* USART_OneBitSampling_Feature */ + +#if defined(USART_CR1_OVER8) +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} +#else +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate) +{ + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk) +{ + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + return (brrresult); +} +#endif /* USART_OverSampling_Feature */ + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll SR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll SR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll SR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll SR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); +} + +/** + * @brief Clear Parity Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * NE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR PE LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Framing Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, ORE, IDLE would also be cleared. + * @rmtoll SR FE LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Noise detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR NF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear OverRun Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, IDLE would also be cleared. + * @rmtoll SR ORE LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear IDLE line detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, ORE would also be cleared. + * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll SR TC LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_TC)); +} + +/** + * @brief Clear RX Not Empty Flag + * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_LBD)); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_USART_DMA_GetRegAddr + * @note Address of Data Register is valid for both Transmit and Receive transfers. + * @param USARTx USART Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) +{ + /* return address of DR register */ + return ((uint32_t) &(USARTx->DR)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll DR DR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll DR DR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll DR DR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->DR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll DR DR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->DR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll CR1 SBK LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_SBK); +} + +/** + * @brief Put USART in Mute mode + * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @brief Put USART in Active mode + * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_USART_H */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h index edb17d7..69483bd 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h @@ -1,272 +1,270 @@ -/** - ****************************************************************************** - * @file stm32f1xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_LL_UTILS_H -#define __STM32F1xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx.h" - -/** @addtogroup STM32F1xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLL_MUL - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - - uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. - This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB2_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB2Prescaler(). */ - -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); -} - - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -#if defined(FLASH_ACR_LATENCY) -ErrorStatus LL_SetFlashLatency(uint32_t Frequency); -#endif /* FLASH_ACR_LATENCY */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#if defined(RCC_PLL2_SUPPORT) -ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#endif /* RCC_PLL2_SUPPORT */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_UTILS_H +#define __STM32F1xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#if defined(RCC_PLL2_SUPPORT) +ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#endif /* RCC_PLL2_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_UTILS_H */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c index f4824ab..da80972 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -1,606 +1,607 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @brief STM32F1xx HAL Driver version number V1.1.8 - */ -#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ -#define __STM32F1xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ -#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ - |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32F1xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK 0x00000FFFU - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief This function is used to initialize the HAL Library; it must be the first - * instruction to be executed in the main program (before to call any other - * HAL function), it performs the following: - * Configure the Flash prefetch. - * Configures the SysTick to generate an interrupt each 1 millisecond, - * which is clocked by the HSI (at this stage, the clock is not yet - * configured and thus the system is running from the internal HSI at 16 MHz). - * Set NVIC Group Priority to 4. - * Calls the HAL_MspInit() callback function defined in user file - * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization - * - * @note SysTick is used as time base for the HAL_Delay() function, the application - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) -#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ - defined(STM32F102x6) || defined(STM32F102xB) || \ - defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ - defined(STM32F105xC) || defined(STM32F107xC) - - /* Prefetch buffer is not available on value line devices */ - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - -#if defined(STM32F105xC) || defined(STM32F107xC) - __HAL_RCC_AHB_FORCE_RESET(); - __HAL_RCC_AHB_RELEASE_RESET(); -#endif - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += uwTickFreq; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @retval status - */ -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_TickFreqTypeDef prevTickFreq; - - assert_param(IS_TICKFREQ(Freq)); - - if (uwTickFreq != Freq) - { - /* Back up uwTickFreq frequency */ - prevTickFreq = uwTickFreq; - - /* Update uwTickFreq global variable used by HAL_InitTick() */ - uwTickFreq = Freq; - - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - - if (status != HAL_OK) - { - /* Restore previous tick frequency */ - uwTickFreq = prevTickFreq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval tick period in Hz - */ -HAL_TickFreqTypeDef HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)(uwTickFreq); - } - - while ((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Returns the HAL revision - * @retval version 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F1xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Returns the device identifier. - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Returns first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Returns second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Returns third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode - * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup - * the system from Stop mode. - * Workaround: To debug the Stop mode, disable the system tick timer - * interrupt. - * Refer to errata sheet of these devices for more details. - * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode - * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup - * the system from Stop mode. - * Workaround: To debug the Stop mode, disable the system tick timer - * interrupt. - * Refer to errata sheet of these devices for more details. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * Note: On devices STM32F10xx8 and STM32F10xxB, - * STM32F101xC/D/E and STM32F103xC/D/E, - * STM32F101xF/G and STM32F103xF/G - * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in - * debug mode (not accessible by the user software in normal mode). - * Refer to errata sheet of these devices for more details. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F1xx HAL Driver version number + */ +#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F1xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) +#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); +#endif + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F1xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Returns the device identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c index 27eecb6..29d7466 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c @@ -1,2437 +1,2428 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_adc.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Channels configuration on injected group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * Other functions (extended functions) are available in file - * "stm32f1xx_hal_adc_ex.c". - * - @verbatim - ============================================================================== - ##### ADC peripheral features ##### - ============================================================================== - [..] - (+) 12-bit resolution - - (+) Interrupt generation at the end of regular conversion, end of injected - conversion, and in case of analog watchdog or overrun events. - - (+) Single and continuous conversion modes. - - (+) Scan mode for conversion of several channels sequentially. - - (+) Data alignment with in-built data coherency. - - (+) Programmable sampling time (channel wise) - - (+) ADC conversion of regular group and injected group. - - (+) External trigger (timer or EXTI) - for both regular and injected groups. - - (+) DMA request generation for transfer of conversions data of regular group. - - (+) Multimode Dual mode (available on devices with 2 ADCs or more). - - (+) Configurable DMA data storage in Multimode Dual mode (available on devices - with 2 DCs or more). - - (+) Configurable delay between conversions in Dual interleaved mode (available - on devices with 2 DCs or more). - - (+) ADC calibration - - (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - *** Configuration of top level parameters related to ADC *** - ============================================================ - [..] - - (#) Enable the ADC interface - (++) As prerequisite, ADC clock must be configured at RCC top level. - Caution: On STM32F1, ADC clock frequency max is 14MHz (refer - to device datasheet). - Therefore, ADC clock prescaler must be configured in - function of ADC clock source frequency to remain below - this maximum frequency. - (++) One clock setting is mandatory: - ADC clock (core clock, also possibly conversion clock). - (+++) Example: - Into HAL_ADC_MspInit() (recommended code location) or with - other device clock parameters configuration: - (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; - (+++) __ADC1_CLK_ENABLE(); - (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; - (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Configure these ADC pins in analog mode - using function HAL_GPIO_Init() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Configure the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector - ADCx_IRQHandler(). - - (#) Optionally, in case of usage of DMA: - (++) Configure the DMA (DMA channel, mode normal or circular, ...) - using function HAL_DMA_Init(). - (++) Configure the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector - DMAx_Channelx_IRQHandler(). - - *** Configuration of ADC, groups regular/injected, channels parameters *** - ========================================================================== - [..] - - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the injected group parameters (conversion trigger, - sequencer, ..., of injected group) - and the channels for injected group parameters (channel number, - channel rank into sequencer, ..., into injected group) - using function HAL_ADCEx_InjectedConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) - using function HAL_ADC_AnalogWDGConfig(). - - (#) Optionally, for devices with several ADC instances: configure the - multimode parameters - using function HAL_ADCEx_MultiModeConfigChannel(). - - *** Execution of ADC conversions *** - ==================================== - [..] - - (#) Optionally, perform an automatic ADC calibration to improve the - conversion accuracy - using function HAL_ADCEx_Calibration_Start(). - - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - (++) ADC conversion by polling: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion - using function HAL_ADC_PollForConversion() - (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (or for injected group: HAL_ADCEx_InjectedGetValue() ) - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop() - - (++) ADC conversion by interruption: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_IT() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() - (this function must be implemented in user program) - (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (or for injected group: HAL_ADCEx_InjectedGetValue() ) - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_IT() - - (++) ADC conversion with transfer by DMA: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_DMA() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() - (these functions must be implemented in user program) - (+++) Conversion results are automatically transferred by DMA into - destination variable address. - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_DMA() - - (++) For devices with several ADCs: ADC multimode conversion - with transfer by DMA: - (+++) Activate the ADC peripheral (slave) and start conversions - using function HAL_ADC_Start() - (+++) Activate the ADC peripheral (master) and start conversions - using function HAL_ADCEx_MultiModeStart_DMA() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() - (these functions must be implemented in user program) - (+++) Conversion results are automatically transferred by DMA into - destination variable address. - (+++) Stop conversion and disable the ADC peripheral (master) - using function HAL_ADCEx_MultiModeStop_DMA() - (+++) Stop conversion and disable the ADC peripheral (slave) - using function HAL_ADC_Stop_IT() - - [..] - - (@) Callback functions must be implemented in user program: - (+@) HAL_ADC_ErrorCallback() - (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) - (+@) HAL_ADC_ConvCpltCallback() - (+@) HAL_ADC_ConvHalfCpltCallback - (+@) HAL_ADCEx_InjectedConvCpltCallback() - - *** Deinitialization of ADC *** - ============================================================ - [..] - - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). - (++) ADC clock disable - using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC - (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF - (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA - using function HAL_DMA_Init(). - (++) Disable the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - - [..] - - *** Callback registration *** - ============================================= - [..] - - The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, - allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() - to register an interrupt callback. - [..] - - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default - weak function. - [..] - - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - [..] - - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when - these callbacks are null (not registered beforehand). - [..] - - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - [..] - - Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. - [..] - - When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - - /* Timeout values for ADC enable and disable settling time. */ - /* Values defined to be higher than worst cases: low clocks freq, */ - /* maximum prescaler. */ - /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ - /* Unit: ms */ - #define ADC_ENABLE_TIMEOUT 2U - #define ADC_DISABLE_TIMEOUT 2U - - /* Delay for ADC stabilization time. */ - /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ - /* Unit: us */ - #define ADC_STAB_DELAY_US 1U - - /* Delay for temperature sensor stabilization time. */ - /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ - /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US 10U - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the ADC peripheral and regular group according to - * parameters specified in structure "ADC_InitTypeDef". - * @note As prerequisite, ADC clock must be configured at RCC top level - * (clock source APB2). - * See commented example code below that can be copied and uncommented - * into HAL_ADC_MspInit(). - * @note Possibility to update parameters on the fly: - * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when - * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC - * MSP has to be modified again, HAL_ADC_DeInit() must be called - * before HAL_ADC_Init(). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments - * of structure "ADC_InitTypeDef". - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_cr1 = 0U; - uint32_t tmp_cr2 = 0U; - uint32_t tmp_sqr1 = 0U; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - if(hadc->Init.DiscontinuousConvMode != DISABLE) - { - assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); - } - } - - /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ - /* at RCC top level. */ - /* Refer to header of this file for more details on clock enabling */ - /* procedure. */ - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) - { - /* Initialize ADC error code */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Allocate lock resource and initialize it */ - hadc->Lock = HAL_UNLOCKED; - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - /* Init the ADC Callback settings */ - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ - hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ - - if (hadc->MspInitCallback == NULL) - { - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hadc->MspInitCallback(hadc); -#else - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - /* Note: In case of ADC already enabled, precaution to not launch an */ - /* unwanted conversion while modifying register CR2 by writing 1 to */ - /* bit ADON. */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - (tmp_hal_status == HAL_OK) ) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Set ADC parameters */ - - /* Configuration of ADC: */ - /* - data alignment */ - /* - external trigger to start conversion */ - /* - external trigger polarity (always set to 1, because needed for all */ - /* triggers: external trigger of SW start) */ - /* - continuous conversion mode */ - /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ - /* HAL_ADC_Start_xxx functions because if set in this function, */ - /* a conversion on injected group would start a conversion also on */ - /* regular group after ADC enabling. */ - tmp_cr2 |= (hadc->Init.DataAlign | - ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | - ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); - - /* Configuration of ADC: */ - /* - scan mode */ - /* - discontinuous mode disable/enable */ - /* - discontinuous mode number of conversions */ - tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); - - /* Enable discontinuous mode only if continuous mode is disabled */ - /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ - /* discontinuous is set anyway, but will have no effect on ADC HW. */ - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - if (hadc->Init.ContinuousConvMode == DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - /* Set the number of channels to be converted in discontinuous mode */ - SET_BIT(tmp_cr1, ADC_CR1_DISCEN | - ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); - } - else - { - /* ADC regular group settings continuous and sequencer discontinuous*/ - /* cannot be enabled simultaneously. */ - - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - - /* Update ADC configuration register CR1 with previous settings */ - MODIFY_REG(hadc->Instance->CR1, - ADC_CR1_SCAN | - ADC_CR1_DISCEN | - ADC_CR1_DISCNUM , - tmp_cr1 ); - - /* Update ADC configuration register CR2 with previous settings */ - MODIFY_REG(hadc->Instance->CR2, - ADC_CR2_ALIGN | - ADC_CR2_EXTSEL | - ADC_CR2_EXTTRIG | - ADC_CR2_CONT , - tmp_cr2 ); - - /* Configuration of regular group sequencer: */ - /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "NbrOfConversion" is discarded. */ - /* Note: Scan mode is present by hardware on this device and, if */ - /* disabled, discards automatically nb of conversions. Anyway, nb of */ - /* conversions is forced to 0x00 for alignment over all STM32 devices. */ - /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion" */ - if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) - { - tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); - } - - MODIFY_REG(hadc->Instance->SQR1, - ADC_SQR1_L , - tmp_sqr1 ); - - /* Check back that ADC registers have effectively been configured to */ - /* ensure of no potential problem of ADC core IP clocking. */ - /* Check through register CR2 (excluding bits set in other functions: */ - /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ - /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ - /* measurement path bit (TSVREFE). */ - if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | - ADC_CR2_SWSTART | ADC_CR2_JSWSTART | - ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | - ADC_CR2_TSVREFE )) - == tmp_cr2) - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * If needed, the example code can be copied and uncommented into - * function HAL_ADC_MspDeInit(). - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (tmp_hal_status == HAL_OK) - { - /* ========== Reset ADC registers ========== */ - - - - - /* Reset register SR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | - ADC_FLAG_JSTRT | ADC_FLAG_STRT)); - - /* Reset register CR1 */ - CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | - ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | - ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | - ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); - - /* Reset register CR2 */ - CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | - ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | - ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | - ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | - ADC_CR2_ADON )); - - /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | - ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | - ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); - - /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | - ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | - ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | - ADC_SMPR2_SMP0 )); - - /* Reset register JOFR1 */ - CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); - /* Reset register JOFR2 */ - CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); - /* Reset register JOFR3 */ - CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); - /* Reset register JOFR4 */ - CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); - - /* Reset register HTR */ - CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); - /* Reset register LTR */ - CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); - - /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | - ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | - ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); - - /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | - ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | - ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); - - /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | - ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); - - /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | - ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); - - /* Reset register JSQR */ - CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | - ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); - - /* Reset register JSQR */ - CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | - ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset registers JDR1, JDR2, JDR3, JDR4 */ - /* bits in access mode read only, no direct reset applicable*/ - - /* ========== Hard reset ADC peripheral ========== */ - /* Performs a global reset of the entire ADC peripheral: ADC state is */ - /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ - /* */ - /* __HAL_RCC_ADC1_FORCE_RESET() */ - /* __HAL_RCC_ADC1_RELEASE_RESET() */ - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hadc->MspDeInitCallback(hadc); -#else - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Initializes the ADC MSP. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspDeInit must be implemented in the user file. - */ -} - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ADC Callback - * To be used instead of the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if ((hadc->State & HAL_ADC_STATE_READY) != 0) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = pCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = pCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = pCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = pCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a ADC Callback - * ADC callback is redirected to the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if ((hadc->State & HAL_ADC_STATE_READY) != 0) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = HAL_ADC_ErrorCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular group. - (+) Stop conversion of regular group. - (+) Poll for conversion complete on regular group. - (+) Poll for conversion event. - (+) Get result of regular channel conversion. - (+) Start conversion of regular group and enable interruptions. - (+) Stop conversion of regular group and disable interruptions. - (+) Handle ADC interrupt request - (+) Start conversion of regular group and enable DMA transfer. - (+) Stop conversion of regular group and disable ADC DMA transfer. -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC, starts conversion of regular group. - * Interruptions enabled in this function: None. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, - HAL_ADC_STATE_REG_BUSY); - - /* Set group injected state (from auto-injection) and multimode state */ - /* for all cases of multimode: independent mode, multimode ADC master */ - /* or multimode ADC slave (for devices with several ADCs): */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - /* Set ADC state (ADC independent or master) */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - else - { - /* Set ADC state (ADC slave) */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled: */ - /* - if ADC is slave, ADC is enabled only (conversion is not started). */ - /* - if ADC is master, ADC is enabled and conversion is started. */ - /* If ADC is master, ADC is enabled and conversion is started. */ - /* Note: Alternate trigger for single conversion could be to force an */ - /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ - if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - { - /* Start ADC conversion on regular group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); - } - else - { - /* Start ADC conversion on regular group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for regular group conversion to be completed. - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode. - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. - * @note On STM32F1 devices, limitation in case of sequencer enabled - * (several ranks selected): polling cannot be done on each - * conversion inside the sequence. In this case, polling is replaced by - * wait for maximum conversion time. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Variables for polling in case of scan mode enabled and polling for each */ - /* conversion. */ - __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; - uint32_t Conversion_Timeout_CPU_cycles_max = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode */ - if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Polling for end of conversion: differentiation if single/sequence */ - /* conversion. */ - /* - If single conversion for regular group (Scan mode disabled or enabled */ - /* with NbrOfConversion =1), flag EOC is used to determine the */ - /* conversion completion. */ - /* - If sequence conversion for regular group (scan mode enabled and */ - /* NbrOfConversion >=2), flag EOC is set only at the end of the */ - /* sequence. */ - /* To poll for each conversion, the maximum conversion time is computed */ - /* from ADC conversion time (selected sampling time + conversion time of */ - /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ - /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ - /* As flag EOC is not set after each conversion, no timeout status can */ - /* be set. */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && - HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) - { - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - } - else - { - /* Replace polling by wait for maximum conversion time */ - /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ - /* and ADC maximum conversion cycles on all channels. */ - /* - Wait for the expected ADC clock cycles delay */ - Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock - / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) - * ADC_CONVCYCLES_MAX_RANGE(hadc) ); - - while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - Conversion_Timeout_CPU_cycles ++; - } - } - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ - /* (several ranks selected), end of conversion flag is raised */ - /* at the end of the sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Poll for conversion event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. - * This parameter can be one of the following values: - * @arg ADC_AWD_EVENT: ADC Analog watchdog event. - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - /* Analog watchdog (level out of window) event */ - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Enables ADC, starts conversion of regular group with interruption. - * Interruptions enabled in this function: - * - EOC (end of conversion of regular group) - * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Set group injected state (from auto-injection) and multimode state */ - /* for all cases of multimode: independent mode, multimode ADC master */ - /* or multimode ADC slave (for devices with several ADCs): */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - /* Set ADC state (ADC independent or master) */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - else - { - /* Set ADC state (ADC slave) */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable end of conversion interrupt for regular group */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled: */ - /* - if ADC is slave, ADC is enabled only (conversion is not started). */ - /* - if ADC is master, ADC is enabled and conversion is started. */ - if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - { - /* Start ADC conversion on regular group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); - } - else - { - /* Start ADC conversion on regular group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of - * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enables ADC, starts conversion of regular group and transfers result - * through DMA. - * Interruptions enabled in this function: - * - DMA transfer complete - * - DMA half transfer - * Each of these interruptions has its dedicated callback function. - * @note For devices with several ADCs: This function is for single-ADC mode - * only. For multimode, use the dedicated MultimodeStart function. - * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending - * on devices) have DMA capability. - * ADC2 converted data can be transferred in dual ADC mode using DMA - * of ADC1 (ADC master in multimode). - * In case of using ADC1 with DMA on a device featuring 2 ADC - * instances: ADC1 conversion register DR contains ADC1 conversion - * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last - * conversion result (ADC1 register DR bits 16 to 27). Therefore, to - * have DMA transferring the conversion results of ADC1 only, DMA must - * be configured to transfer size: half word. - * @param hadc: ADC handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval None - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); - - /* Verification if multimode is disabled (for devices with several ADC) */ - /* If multimode is enabled, dedicated function multimode conversion */ - /* start DMA must be used. */ - if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Set group injected state (from auto-injection) and multimode state */ - /* for all cases of multimode: independent mode, multimode ADC master */ - /* or multimode ADC slave (for devices with several ADCs): */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - /* Set ADC state (ADC independent or master) */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - else - { - /* Set ADC state (ADC slave) */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable ADC DMA mode */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) - { - /* Start ADC conversion on regular group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); - } - else - { - /* Start ADC conversion on regular group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - } - else - { - tmp_hal_status = HAL_ERROR; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @note For devices with several ADCs: This function is for single-ADC mode - * only. For multimode, use the dedicated MultimodeStop function. - * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending - * on devices) have DMA capability. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC DMA mode */ - CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) - { - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get ADC regular group conversion result. - * @note Reading register DR automatically clears ADC flag EOC - * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS - * (ADC group regular end of sequence conversion). - * Occurrence of flag EOS rising: - * - If sequencer is composed of 1 rank, flag EOS is equivalent - * to flag EOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag EOC only is raised, at the end of the scan sequence - * both flags EOC and EOS are raised. - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle - * @retval ADC group regular conversion data - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Handles ADC interrupt request - * @param hadc: ADC handle - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - - - /* ========== Check End of Conversion flag for regular group ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ - /* (several ranks selected), end of conversion flag is raised */ - /* at the end of the sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Disable ADC end of conversion interrupt on group regular */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - } - } - - /* ========== Check End of Conversion flag for injected group ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - } - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger, scan sequence on going or by automatic injected */ - /* conversion from group regular (same conditions as group regular */ - /* interruption disabling above). */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ - /* (several ranks selected), end of conversion flag is raised */ - /* at the end of the sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) - { - /* Disable ADC end of conversion interrupt on group injected */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); -#else - HAL_ADCEx_InjectedConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); - } - } - - /* ========== Check Analog watchdog flags ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindowCallback(hadc); -#else - HAL_ADC_LevelOutOfWindowCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear the ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - } - } - -} - -/** - * @brief Conversion complete callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Conversion DMA half-transfer callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog callback in non blocking mode. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC error callback in non blocking mode - * (ADC conversion with interruption or transfer by DMA) - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ErrorCallback must be implemented in the user file. - */ -} - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on regular group - (+) Configure the analog watchdog - -@endverbatim - * @{ - */ - -/** - * @brief Configures the the selected channel to be linked to the regular - * group. - * @note In case of usage of internal measurement channels: - * Vbat/VrefInt/TempSensor. - * These internal paths can be be disabled using function - * HAL_ADC_DeInit(). - * @note Possibility to update parameters on the fly: - * This function initializes channel into regular group, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel for regular group. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - - /* Process locked */ - __HAL_LOCK(hadc); - - - /* Regular sequence configuration */ - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7U) - { - MODIFY_REG(hadc->Instance->SQR3 , - ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , - ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13U) - { - MODIFY_REG(hadc->Instance->SQR2 , - ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , - ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 13 to 16 */ - else - { - MODIFY_REG(hadc->Instance->SQR1 , - ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , - ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); - } - - - /* Channel sampling time configuration */ - /* For channels 10 to 17 */ - if (sConfig->Channel >= ADC_CHANNEL_10) - { - MODIFY_REG(hadc->Instance->SMPR1 , - ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , - ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); - } - else /* For channels 0 to 9 */ - { - MODIFY_REG(hadc->Instance->SMPR2 , - ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , - ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); - } - - /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || - (sConfig->Channel == ADC_CHANNEL_VREFINT) ) - { - /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ - /* measurement channels (VrefInt/TempSensor). If these channels are */ - /* intended to be set on other ADC instances, an error is reported. */ - if (hadc->Instance == ADC1) - { - if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) - { - SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Configures the analog watchdog. - * @note Analog watchdog thresholds can be modified while ADC conversion - * is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); - - if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) - { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Analog watchdog configuration */ - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); - } - - /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: regular and/or injected groups, */ - /* one or all channels. */ - /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ - MODIFY_REG(hadc->Instance->CR1 , - ADC_CR1_AWDSGL | - ADC_CR1_JAWDEN | - ADC_CR1_AWDEN | - ADC_CR1_AWDCH , - AnalogWDGConfig->WatchdogMode | - AnalogWDGConfig->Channel ); - - /* Set the high threshold */ - WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); - - /* Set the low threshold */ - WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - - -/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions to get in run-time the status of the - peripheral. - (+) Check the ADC state - (+) Check the ADC error code - -@endverbatim - * @{ - */ - -/** - * @brief return the ADC state - * @param hadc: ADC handle - * @retval HAL state - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) -{ - /* Return ADC state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code - * @param hadc: ADC handle - * @retval ADC Error Code - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Enable the selected ADC. - * @note Prerequisite condition to use this function: ADC must be disabled - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0U; - __IO uint32_t wait_loop_index = 0U; - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (ADC_IS_ENABLE(hadc) == RESET) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait for ADC effectively enabled */ - while(ADC_IS_ENABLE(hadc) == RESET) - { - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if(ADC_IS_ENABLE(hadc) == RESET) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Stop ADC conversion and disable the selected ADC - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped to disable the ADC. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0U; - - /* Verification if ADC is not already disabled */ - if (ADC_IS_ENABLE(hadc) != RESET) - { - /* Disable the ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait for ADC effectively disabled */ - while(ADC_IS_ENABLE(hadc) != RESET) - { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if(ADC_IS_ENABLE(hadc) != RESET) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ - /* (several ranks selected), end of conversion flag is raised */ - /* at the end of the sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Half conversion callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvHalfCpltCallback(hadc); -#else - HAL_ADC_ConvHalfCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback - * @param hdma: pointer to DMA handle. - * @retval None - */ -void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - - /* Set ADC error code to DMA error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - - /* Error callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * Other functions (extended functions) are available in file + * "stm32f1xx_hal_adc_ex.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit resolution + + (+) Interrupt generation at the end of regular conversion, end of injected + conversion, and in case of analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (channel wise) + + (+) ADC conversion of regular group and injected group. + + (+) External trigger (timer or EXTI) + for both regular and injected groups. + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) Multimode Dual mode (available on devices with 2 ADCs or more). + + (+) Configurable DMA data storage in Multimode Dual mode (available on devices + with 2 DCs or more). + + (+) Configurable delay between conversions in Dual interleaved mode (available + on devices with 2 DCs or more). + + (+) ADC calibration + + (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32F1, ADC clock frequency max is 14MHz (refer + to device datasheet). + Therefore, ADC clock prescaler must be configured in + function of ADC clock source frequency to remain below + this maximum frequency. + (++) One clock setting is mandatory: + ADC clock (core clock, also possibly conversion clock). + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; + (+++) __ADC1_CLK_ENABLE(); + (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; + (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, groups regular/injected, channels parameters *** + ========================================================================== + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the injected group parameters (conversion trigger, + sequencer, ..., of injected group) + and the channels for injected group parameters (channel number, + channel rank into sequencer, ..., into injected group) + using function HAL_ADCEx_InjectedConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + (#) Optionally, for devices with several ADC instances: configure the + multimode parameters + using function HAL_ADCEx_MultiModeConfigChannel(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (or for injected group: HAL_ADCEx_InjectedGetValue() ) + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (or for injected group: HAL_ADCEx_InjectedGetValue() ) + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + (++) For devices with several ADCs: ADC multimode conversion + with transfer by DMA: + (+++) Activate the ADC peripheral (slave) and start conversions + using function HAL_ADC_Start() + (+++) Activate the ADC peripheral (master) and start conversions + using function HAL_ADCEx_MultiModeStart_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral (master) + using function HAL_ADCEx_MultiModeStop_DMA() + (+++) Stop conversion and disable the ADC peripheral (slave) + using function HAL_ADC_Stop_IT() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + (+@) HAL_ADCEx_InjectedConvCpltCallback() + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC + (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF + (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + + /* Timeout values for ADC enable and disable settling time. */ + /* Values defined to be higher than worst cases: low clocks freq, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ + /* Unit: ms */ + #define ADC_ENABLE_TIMEOUT 2U + #define ADC_DISABLE_TIMEOUT 2U + + /* Delay for ADC stabilization time. */ + /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ + /* Unit: us */ + #define ADC_STAB_DELAY_US 1U + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US 10U + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (clock source APB2). + * See commented example code below that can be copied and uncommented + * into HAL_ADC_MspInit(). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_cr1 = 0U; + uint32_t tmp_cr2 = 0U; + uint32_t tmp_sqr1 = 0U; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + if(hadc->Init.DiscontinuousConvMode != DISABLE) + { + assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); + } + } + + /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ + /* at RCC top level. */ + /* Refer to header of this file for more details on clock enabling */ + /* procedure. */ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + /* Note: In case of ADC already enabled, precaution to not launch an */ + /* unwanted conversion while modifying register CR2 by writing 1 to */ + /* bit ADON. */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && + (tmp_hal_status == HAL_OK) ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + + /* Configuration of ADC: */ + /* - data alignment */ + /* - external trigger to start conversion */ + /* - external trigger polarity (always set to 1, because needed for all */ + /* triggers: external trigger of SW start) */ + /* - continuous conversion mode */ + /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ + /* HAL_ADC_Start_xxx functions because if set in this function, */ + /* a conversion on injected group would start a conversion also on */ + /* regular group after ADC enabling. */ + tmp_cr2 |= (hadc->Init.DataAlign | + ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | + ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); + + /* Configuration of ADC: */ + /* - scan mode */ + /* - discontinuous mode disable/enable */ + /* - discontinuous mode number of conversions */ + tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); + + /* Enable discontinuous mode only if continuous mode is disabled */ + /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ + /* discontinuous is set anyway, but will have no effect on ADC HW. */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + /* Set the number of channels to be converted in discontinuous mode */ + SET_BIT(tmp_cr1, ADC_CR1_DISCEN | + ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); + } + else + { + /* ADC regular group settings continuous and sequencer discontinuous*/ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Update ADC configuration register CR1 with previous settings */ + MODIFY_REG(hadc->Instance->CR1, + ADC_CR1_SCAN | + ADC_CR1_DISCEN | + ADC_CR1_DISCNUM , + tmp_cr1 ); + + /* Update ADC configuration register CR2 with previous settings */ + MODIFY_REG(hadc->Instance->CR2, + ADC_CR2_ALIGN | + ADC_CR2_EXTSEL | + ADC_CR2_EXTTRIG | + ADC_CR2_CONT , + tmp_cr2 ); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is present by hardware on this device and, if */ + /* disabled, discards automatically nb of conversions. Anyway, nb of */ + /* conversions is forced to 0x00 for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion" */ + if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) + { + tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); + } + + MODIFY_REG(hadc->Instance->SQR1, + ADC_SQR1_L , + tmp_sqr1 ); + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CR2 (excluding bits set in other functions: */ + /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ + /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ + /* measurement path bit (TSVREFE). */ + if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | + ADC_CR2_SWSTART | ADC_CR2_JSWSTART | + ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | + ADC_CR2_TSVREFE )) + == tmp_cr2) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * If needed, the example code can be copied and uncommented into + * function HAL_ADC_MspDeInit(). + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (tmp_hal_status == HAL_OK) + { + /* ========== Reset ADC registers ========== */ + + + + + /* Reset register SR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | + ADC_FLAG_JSTRT | ADC_FLAG_STRT)); + + /* Reset register CR1 */ + CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | + ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | + ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | + ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); + + /* Reset register CR2 */ + CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | + ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | + ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | + ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | + ADC_CR2_ADON )); + + /* Reset register SMPR1 */ + CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | + ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | + ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); + + /* Reset register SMPR2 */ + CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | + ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | + ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | + ADC_SMPR2_SMP0 )); + + /* Reset register JOFR1 */ + CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); + /* Reset register JOFR2 */ + CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); + /* Reset register JOFR3 */ + CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); + /* Reset register JOFR4 */ + CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); + + /* Reset register HTR */ + CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); + /* Reset register LTR */ + CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); + + /* Reset register SQR1 */ + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | + ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | + ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); + + /* Reset register SQR1 */ + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | + ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | + ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); + + /* Reset register SQR2 */ + CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | + ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); + + /* Reset register SQR3 */ + CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | + ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); + + /* Reset register JSQR */ + CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | + ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); + + /* Reset register JSQR */ + CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | + ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable*/ + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ + /* */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of regular group. + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, + HAL_ADC_STATE_REG_BUSY); + + /* Set group injected state (from auto-injection) and multimode state */ + /* for all cases of multimode: independent mode, multimode ADC master */ + /* or multimode ADC slave (for devices with several ADCs): */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + /* Set ADC state (ADC independent or master) */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + else + { + /* Set ADC state (ADC slave) */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled: */ + /* - if ADC is slave, ADC is enabled only (conversion is not started). */ + /* - if ADC is master, ADC is enabled and conversion is started. */ + /* If ADC is master, ADC is enabled and conversion is started. */ + /* Note: Alternate trigger for single conversion could be to force an */ + /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + { + /* Start ADC conversion on regular group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); + } + else + { + /* Start ADC conversion on regular group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. + * @note On STM32F1 devices, limitation in case of sequencer enabled + * (several ranks selected): polling cannot be done on each + * conversion inside the sequence. In this case, polling is replaced by + * wait for maximum conversion time. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Variables for polling in case of scan mode enabled and polling for each */ + /* conversion. */ + __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Polling for end of conversion: differentiation if single/sequence */ + /* conversion. */ + /* - If single conversion for regular group (Scan mode disabled or enabled */ + /* with NbrOfConversion =1), flag EOC is used to determine the */ + /* conversion completion. */ + /* - If sequence conversion for regular group (scan mode enabled and */ + /* NbrOfConversion >=2), flag EOC is set only at the end of the */ + /* sequence. */ + /* To poll for each conversion, the maximum conversion time is computed */ + /* from ADC conversion time (selected sampling time + conversion time of */ + /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ + /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ + /* As flag EOC is not set after each conversion, no timeout status can */ + /* be set. */ + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && + HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) + { + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + } + else + { + /* Replace polling by wait for maximum conversion time */ + /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ + /* and ADC maximum conversion cycles on all channels. */ + /* - Wait for the expected ADC clock cycles delay */ + Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock + / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) + * ADC_CONVCYCLES_MAX_RANGE(hadc) ); + + while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + Conversion_Timeout_CPU_cycles ++; + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* (several ranks selected), end of conversion flag is raised */ + /* at the end of the sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event. + * @param hadc: ADC handle + * @param EventType: the ADC event type. + * This parameter can be one of the following values: + * @arg ADC_AWD_EVENT: ADC Analog watchdog event. + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Analog watchdog (level out of window) event */ + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of regular group with interruption. + * Interruptions enabled in this function: + * - EOC (end of conversion of regular group) + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set group injected state (from auto-injection) and multimode state */ + /* for all cases of multimode: independent mode, multimode ADC master */ + /* or multimode ADC slave (for devices with several ADCs): */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + /* Set ADC state (ADC independent or master) */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + else + { + /* Set ADC state (ADC slave) */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled: */ + /* - if ADC is slave, ADC is enabled only (conversion is not started). */ + /* - if ADC is master, ADC is enabled and conversion is started. */ + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + { + /* Start ADC conversion on regular group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); + } + else + { + /* Start ADC conversion on regular group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enables ADC, starts conversion of regular group and transfers result + * through DMA. + * Interruptions enabled in this function: + * - DMA transfer complete + * - DMA half transfer + * Each of these interruptions has its dedicated callback function. + * @note For devices with several ADCs: This function is for single-ADC mode + * only. For multimode, use the dedicated MultimodeStart function. + * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending + * on devices) have DMA capability. + * ADC2 converted data can be transferred in dual ADC mode using DMA + * of ADC1 (ADC master in multimode). + * In case of using ADC1 with DMA on a device featuring 2 ADC + * instances: ADC1 conversion register DR contains ADC1 conversion + * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last + * conversion result (ADC1 register DR bits 16 to 27). Therefore, to + * have DMA transferring the conversion results of ADC1 only, DMA must + * be configured to transfer size: half word. + * @param hadc: ADC handle + * @param pData: The destination Buffer address. + * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); + + /* Verification if multimode is disabled (for devices with several ADC) */ + /* If multimode is enabled, dedicated function multimode conversion */ + /* start DMA must be used. */ + if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set group injected state (from auto-injection) and multimode state */ + /* for all cases of multimode: independent mode, multimode ADC master */ + /* or multimode ADC slave (for devices with several ADCs): */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + /* Set ADC state (ADC independent or master) */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + else + { + /* Set ADC state (ADC slave) */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) + { + /* Start ADC conversion on regular group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); + } + else + { + /* Start ADC conversion on regular group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + } + else + { + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @note For devices with several ADCs: This function is for single-ADC mode + * only. For multimode, use the dedicated MultimodeStop function. + * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending + * on devices) have DMA capability. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC DMA mode */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc: ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Handles ADC interrupt request + * @param hadc: ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp_sr = hadc->Instance->SR; + uint32_t tmp_cr1 = hadc->Instance->CR1; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + + /* ========== Check End of Conversion flag for regular group ========== */ + if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) + { + if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* (several ranks selected), end of conversion flag is raised */ + /* at the end of the sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Disable ADC end of conversion interrupt on group regular */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + } + + /* ========== Check End of Conversion flag for injected group ========== */ + if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) + { + if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + } + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* (several ranks selected), end of conversion flag is raised */ + /* at the end of the sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Disable ADC end of conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + } + } + + /* ========== Check Analog watchdog flags ========== */ + if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) + { + if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + } + +} + +/** + * @brief Conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non blocking mode + * (ADC conversion with interruption or transfer by DMA) + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the regular + * group. + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into regular group, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_ChannelConfTypeDef". + * @param hadc: ADC handle + * @param sConfig: Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t wait_loop_index = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + + /* Regular sequence configuration */ + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7U) + { + MODIFY_REG(hadc->Instance->SQR3 , + ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , + ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13U) + { + MODIFY_REG(hadc->Instance->SQR2 , + ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , + ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 13 to 16 */ + else + { + MODIFY_REG(hadc->Instance->SQR1 , + ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , + ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); + } + + + /* Channel sampling time configuration */ + /* For channels 10 to 17 */ + if (sConfig->Channel >= ADC_CHANNEL_10) + { + MODIFY_REG(hadc->Instance->SMPR1 , + ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , + ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); + } + else /* For channels 0 to 9 */ + { + MODIFY_REG(hadc->Instance->SMPR2 , + ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , + ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); + } + + /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || + (sConfig->Channel == ADC_CHANNEL_VREFINT) ) + { + /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ + /* measurement channels (VrefInt/TempSensor). If these channels are */ + /* intended to be set on other ADC instances, an error is reported. */ + if (hadc->Instance == ADC1) + { + if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) + { + SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc: ADC handle + * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); + + if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Analog watchdog configuration */ + + /* Configure ADC Analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: regular and/or injected groups, */ + /* one or all channels. */ + /* - Set the Analog watchdog channel (is not used if watchdog */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + MODIFY_REG(hadc->Instance->CR1 , + ADC_CR1_AWDSGL | + ADC_CR1_JAWDEN | + ADC_CR1_AWDEN | + ADC_CR1_AWDCH , + AnalogWDGConfig->WatchdogMode | + AnalogWDGConfig->Channel ); + + /* Set the high threshold */ + WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); + + /* Set the low threshold */ + WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc: ADC handle + * @retval HAL state + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc: ADC handle + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0U; + __IO uint32_t wait_loop_index = 0U; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (ADC_IS_ENABLE(hadc) == RESET) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively enabled */ + while(ADC_IS_ENABLE(hadc) == RESET) + { + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if(ADC_IS_ENABLE(hadc) == RESET) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Stop ADC conversion and disable the selected ADC + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0U; + + /* Verification if ADC is not already disabled */ + if (ADC_IS_ENABLE(hadc) != RESET) + { + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively disabled */ + while(ADC_IS_ENABLE(hadc) != RESET) + { + if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if(ADC_IS_ENABLE(hadc) != RESET) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* (several ranks selected), end of conversion flag is raised */ + /* at the end of the sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma: pointer to DMA handle. + * @retval None + */ +void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c index 57ff195..af85089 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c @@ -1,1337 +1,1325 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_adc_ex.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Operation functions - * ++ Start, stop, get result of conversions of injected - * group, using 2 possible modes: polling, interruption. - * ++ Multimode feature (available on devices with 2 ADCs or more) - * ++ Calibration (ADC automatic self-calibration) - * + Control functions - * ++ Channels configuration on injected group - * Other functions (generic functions) are available in file - * "stm32f1xx_hal_adc.c". - * - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32f1xx_hal_adc.c". - [..] - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC Extension HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Constants ADCEx Private Constants - * @{ - */ - - /* Delay for ADC calibration: */ - /* Hardware prerequisite before starting a calibration: the ADC must have */ - /* been in power-on state for at least two ADC clock cycles. */ - /* Unit: ADC clock cycles */ - #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U - - /* Timeout value for ADC calibration */ - /* Value defined to be higher than worst cases: low clocks freq, */ - /* maximum prescaler. */ - /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ - /* Unit: ms */ - #define ADC_CALIBRATION_TIMEOUT 10U - - /* Delay for temperature sensor stabilization time. */ - /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ - /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US 10U - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions - * @brief Extended Extended Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of injected group. - (+) Stop conversion of injected group. - (+) Poll for conversion complete on injected group. - (+) Get result of injected channel conversion. - (+) Start conversion of injected group and enable interruptions. - (+) Stop conversion of injected group and disable interruptions. - - (+) Start multimode and enable DMA transfer. - (+) Stop multimode and disable ADC DMA transfer. - (+) Get result of multimode conversion. - - (+) Perform the ADC self-calibration for single or differential ending. - (+) Get calibration factors for single or differential ending. - (+) Set calibration factors for single or differential ending. - -@endverbatim - * @{ - */ - -/** - * @brief Perform an ADC automatic self-calibration - * Calibration prerequisite: ADC must be disabled (execute this - * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). - * During calibration process, ADC is enabled. ADC is let enabled at - * the completion of this function. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tickstart; - __IO uint32_t wait_loop_index = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Calibration prerequisite: */ - /* - ADC must be disabled for at least two ADC clock cycles in disable */ - /* mode before ADC enable */ - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Hardware prerequisite: delay before starting the calibration. */ - /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ - /* - Wait for the expected ADC clock cycles delay */ - wait_loop_index = ((SystemCoreClock - / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) - * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); - - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - - /* 2. Enable the ADC peripheral */ - ADC_Enable(hadc); - - /* 3. Resets ADC calibration registers */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); - - tickstart = HAL_GetTick(); - - /* Wait for calibration reset completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) - { - if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - - /* 4. Start ADC calibration */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); - - tickstart = HAL_GetTick(); - - /* Wait for calibration completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) - { - if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enables ADC, starts conversion of injected group. - * Interruptions enabled in this function: None. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Case of independent mode or multimode (for devices with several ADCs): */ - /* Set multimode state. */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Enable conversion of injected group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* If automatic injected conversion is enabled, conversion will start */ - /* after next regular group conversion. */ - /* Case of multimode enabled (for devices with several ADCs): if ADC is */ - /* slave, ADC is enabled only (conversion is not started). If ADC is */ - /* master, ADC is enabled and conversion is started. */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) - { - if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - { - /* Start ADC conversion on injected group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); - } - else - { - /* Start ADC conversion on injected group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for injected group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Variables for polling in case of scan mode enabled and polling for each */ - /* conversion. */ - __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; - uint32_t Conversion_Timeout_CPU_cycles_max = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Polling for end of conversion: differentiation if single/sequence */ - /* conversion. */ - /* For injected group, flag JEOC is set only at the end of the sequence, */ - /* not for each conversion within the sequence. */ - /* - If single conversion for injected group (scan mode disabled or */ - /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ - /* conversion completion. */ - /* - If sequence conversion for injected group (scan mode enabled and */ - /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ - /* sequence. */ - /* To poll for each conversion, the maximum conversion time is computed */ - /* from ADC conversion time (selected sampling time + conversion time of */ - /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ - /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ - /* As flag JEOC is not set after each conversion, no timeout status can */ - /* be set. */ - if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) - { - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - } - else - { - /* Replace polling by wait for maximum conversion time */ - /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ - /* and ADC maximum conversion cycles on all channels. */ - /* - Wait for the expected ADC clock cycles delay */ - Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock - / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) - * ADC_CONVCYCLES_MAX_RANGE(hadc) ); - - while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - Conversion_Timeout_CPU_cycles ++; - } - } - - /* Clear injected group conversion flag */ - /* Note: On STM32F1 ADC, clear regular conversion flag raised */ - /* simultaneously. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger or by automatic injected conversion */ - /* from group regular. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Enables ADC, starts conversion of injected group with interruption. - * - JEOC (end of conversion of injected group) - * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Case of independent mode or multimode (for devices with several ADCs): */ - /* Set multimode state. */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Enable end of conversion interrupt for injected channels */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - - /* Start conversion of injected group if software start has been selected */ - /* and if automatic injected conversion is disabled. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* If automatic injected conversion is enabled, conversion will start */ - /* after next regular group conversion. */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) - { - if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && - ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) - { - /* Start ADC conversion on injected group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); - } - else - { - /* Start ADC conversion on injected group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** - * @brief Enables ADC, starts conversion of regular group and transfers result - * through DMA. - * Multimode must have been previously configured using - * HAL_ADCEx_MultiModeConfigChannel() function. - * Interruptions enabled in this function: - * - DMA transfer complete - * - DMA half transfer - * Each of these interruptions has its dedicated callback function. - * @note: On STM32F1 devices, ADC slave regular group must be configured - * with conversion trigger ADC_SOFTWARE_START. - * @note: ADC slave can be enabled preliminarily using single-mode - * HAL_ADC_Start() function. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_HandleTypeDef tmphadcSlave={0}; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - /* On STM32F1 devices, ADC slave regular group must be configured with */ - /* conversion trigger ADC_SOFTWARE_START. */ - /* Note: External trigger of ADC slave must be enabled, it is already done */ - /* into function "HAL_ADC_Init()". */ - if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Enable the ADC peripherals: master and slave (in case if not already */ - /* enabled previously) */ - tmp_hal_status = ADC_Enable(hadc); - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Enable(&tmphadcSlave); - } - - /* Start conversion if all ADCs of multimode are effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state (ADC master) */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable ADC DMA mode of ADC master */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Start conversion of regular group if software start has been selected. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Note: Alternate trigger for single conversion could be to force an */ - /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ - if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) - { - /* Start ADC conversion on regular group with SW start */ - SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); - } - else - { - /* Start ADC conversion on regular group with external trigger */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @note Multimode is kept enabled after this function. To disable multimode - * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be - * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). - * @note In case of DMA configured in circular mode, function - * HAL_ADC_Stop_DMA must be called after this function with handle of - * ADC slave, to properly disable the DMA channel. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_HandleTypeDef tmphadcSlave={0}; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC master peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if(tmp_hal_status == HAL_OK) - { - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - /* Disable ADC slave peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); - - /* Check if ADC is effectively disabled */ - if(tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Disable ADC DMA mode */ - CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); - - /* Reset configuration of ADC DMA continuous request for dual mode */ - CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Change ADC state (ADC master) */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @brief Get ADC injected group conversion result. - * @note Reading register JDRx automatically clears ADC flag JEOC - * (ADC group injected end of unitary conversion). - * @note This function does not clear ADC flag JEOS - * (ADC group injected end of sequence conversion) - * Occurrence of flag JEOS rising: - * - If sequencer is composed of 1 rank, flag JEOS is equivalent - * to flag JEOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag JEOC only is raised, at the end of the scan sequence - * both flags JEOC and EOS are raised. - * Flag JEOS must not be cleared by this function because - * it would not be compliant with low power features - * (feature low power auto-wait, not available on all STM32 families). - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADCEx_InjectedPollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). - * @param hadc: ADC handle - * @param InjectedRank: the converted ADC injected rank. - * This parameter can be one of the following values: - * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected - * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected - * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected - * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected - * @retval ADC group injected conversion data - */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) -{ - uint32_t tmp_jdr = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Get ADC converted value */ - switch(InjectedRank) - { - case ADC_INJECTED_RANK_4: - tmp_jdr = hadc->Instance->JDR4; - break; - case ADC_INJECTED_RANK_3: - tmp_jdr = hadc->Instance->JDR3; - break; - case ADC_INJECTED_RANK_2: - tmp_jdr = hadc->Instance->JDR2; - break; - case ADC_INJECTED_RANK_1: - default: - tmp_jdr = hadc->Instance->JDR1; - break; - } - - /* Return ADC converted value */ - return tmp_jdr; -} - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** - * @brief Returns the last ADC Master&Slave regular conversions results data - * in the selected multi mode. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) - * @retval The converted data value. - */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) -{ - uint32_t tmpDR = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ - /* only if ADC1 DMA mode is enabled. */ - tmpDR = hadc->Instance->DR; - - if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) - { - tmpDR |= (ADC2->DR << 16U); - } - - /* Return ADC converted value */ - return tmpDR; -} -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ - -/** - * @brief Injected conversion complete callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on injected group - (+) Configure multimode - -@endverbatim - * @{ - */ - -/** - * @brief Configures the ADC injected group and the selected channel to be - * linked to the injected group. - * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this - * function can be used to reconfigure some parameters of structure - * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. - * The setting of these parameters is conditioned to ADC state: - * this function must be called when ADC is not under conversion. - * @param hadc: ADC handle - * @param sConfigInjected: Structure of ADC injected group and ADC channel for - * injected group. - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Configuration of injected group sequencer: */ - /* - if scan mode is disabled, injected channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "InjectedNbrOfConversion" is discarded. */ - /* Note: Scan mode is present by hardware on this device and, if */ - /* disabled, discards automatically nb of conversions. Anyway, nb of */ - /* conversions is forced to 0x00 for alignment over all STM32 devices. */ - /* - if scan mode is enabled, injected channels sequence length is set to */ - /* parameter "InjectedNbrOfConversion". */ - if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) - { - if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) - { - /* Clear the old SQx bits for all injected ranks */ - MODIFY_REG(hadc->Instance->JSQR , - ADC_JSQR_JL | - ADC_JSQR_JSQ4 | - ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | - ADC_JSQR_JSQ1 , - ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, - ADC_INJECTED_RANK_1, - 0x01U)); - } - /* If another injected rank than rank1 was intended to be set, and could */ - /* not due to ScanConvMode disabled, error is reported. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - } - else - { - /* Since injected channels rank conv. order depends on total number of */ - /* injected conversions, selected rank must be below or equal to total */ - /* number of injected conversions to be updated. */ - if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) - { - /* Clear the old SQx bits for the selected rank */ - /* Set the SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , - - ADC_JSQR_JL | - ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , - - ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | - ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) ); - } - else - { - /* Clear the old SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , - - ADC_JSQR_JL | - ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , - - 0x00000000U); - } - } - - /* Configuration of injected group */ - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - external trigger to start conversion */ - /* Parameters update not conditioned to ADC state: */ - /* - Automatic injected conversion */ - /* - Injected discontinuous mode */ - /* Note: In case of ADC already enabled, caution to not launch an unwanted */ - /* conversion while modifying register CR2 by writing 1 to bit ADON. */ - if (ADC_IS_ENABLE(hadc) == RESET) - { - MODIFY_REG(hadc->Instance->CR2 , - ADC_CR2_JEXTSEL | - ADC_CR2_ADON , - ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) ); - } - - - /* Configuration of injected group */ - /* - Automatic injected conversion */ - /* - Injected discontinuous mode */ - - /* Automatic injected conversion can be enabled if injected group */ - /* external triggers are disabled. */ - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - { - SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - } - - /* Injected discontinuous can be enabled only if auto-injected mode is */ - /* disabled. */ - if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) - { - if (sConfigInjected->AutoInjectedConv == DISABLE) - { - SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - } - - - /* InjectedChannel sampling time configuration */ - /* For channels 10 to 17 */ - if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) - { - MODIFY_REG(hadc->Instance->SMPR1 , - ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) , - ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); - } - else /* For channels 0 to 9 */ - { - MODIFY_REG(hadc->Instance->SMPR2 , - ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) , - ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); - } - - /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || - (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) - { - SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); - } - - - /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ - switch(sConfigInjected->InjectedRank) - { - case 1: - /* Set injected channel 1 offset */ - MODIFY_REG(hadc->Instance->JOFR1, - ADC_JOFR1_JOFFSET1, - sConfigInjected->InjectedOffset); - break; - case 2: - /* Set injected channel 2 offset */ - MODIFY_REG(hadc->Instance->JOFR2, - ADC_JOFR2_JOFFSET2, - sConfigInjected->InjectedOffset); - break; - case 3: - /* Set injected channel 3 offset */ - MODIFY_REG(hadc->Instance->JOFR3, - ADC_JOFR3_JOFFSET3, - sConfigInjected->InjectedOffset); - break; - case 4: - default: - MODIFY_REG(hadc->Instance->JOFR4, - ADC_JOFR4_JOFFSET4, - sConfigInjected->InjectedOffset); - break; - } - - /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || - (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) - { - /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ - /* measurement channels (VrefInt/TempSensor). If these channels are */ - /* intended to be set on other ADC instances, an error is reported. */ - if (hadc->Instance == ADC1) - { - if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) - { - SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); - - if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) -/** - * @brief Enable ADC multimode and configure multimode parameters - * @note Possibility to update parameters on the fly: - * This function initializes multimode parameters, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_MultiModeTypeDef" on the fly, without reseting - * the ADCs (both ADCs of the common group). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_MultiModeTypeDef". - * @note To change back configuration from multimode to single mode, ADC must - * be reset (using function HAL_ADC_Init() ). - * @param hadc: ADC handle - * @param multimode: Structure of ADC multimode configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_HandleTypeDef tmphadcSlave={0}; - - /* Check the parameters */ - assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_MODE(multimode->Mode)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Set a temporary handle of the ADC slave associated to the ADC master */ - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - ADC master and ADC slave DMA configuration */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - Multimode mode selection */ - /* To optimize code, all multimode settings can be set when both ADCs of */ - /* the common group are in state: disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && - (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) ) - { - MODIFY_REG(hadc->Instance->CR1, - ADC_CR1_DUALMOD , - multimode->Mode ); - } - /* If one of the ADC sharing the same common group is enabled, no update */ - /* could be done on neither of the multimode structure parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} -#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Peripheral Control functions + * Other functions (generic functions) are available in file + * "stm32f1xx_hal_adc.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32f1xx_hal_adc.c". + [..] + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extension HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + + /* Delay for ADC calibration: */ + /* Hardware prerequisite before starting a calibration: the ADC must have */ + /* been in power-on state for at least two ADC clock cycles. */ + /* Unit: ADC clock cycles */ + #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U + + /* Timeout value for ADC calibration */ + /* Value defined to be higher than worst cases: low clocks freq, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ + /* Unit: ms */ + #define ADC_CALIBRATION_TIMEOUT 10U + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US 10U + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions + * @brief Extended Extended Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of injected group. + (+) Stop conversion of injected group. + (+) Poll for conversion complete on injected group. + (+) Get result of injected channel conversion. + (+) Start conversion of injected group and enable interruptions. + (+) Stop conversion of injected group and disable interruptions. + + (+) Start multimode and enable DMA transfer. + (+) Stop multimode and disable ADC DMA transfer. + (+) Get result of multimode conversion. + + (+) Perform the ADC self-calibration for single or differential ending. + (+) Get calibration factors for single or differential ending. + (+) Set calibration factors for single or differential ending. + +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * During calibration process, ADC is enabled. ADC is let enabled at + * the completion of this function. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* 2. Calibration prerequisite delay before starting the calibration. */ + /* - ADC must be enabled for at least two ADC clock cycles */ + tmp_hal_status = ADC_Enable(hadc); + + /* Check if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Hardware prerequisite: delay before starting the calibration. */ + /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ + /* - Wait for the expected ADC clock cycles delay */ + wait_loop_index = ((SystemCoreClock + / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) + * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); + + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + + /* 3. Resets ADC calibration registers */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); + + tickstart = HAL_GetTick(); + + /* Wait for calibration reset completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + /* 4. Start ADC calibration */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); + + tickstart = HAL_GetTick(); + + /* Wait for calibration completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enables ADC, starts conversion of injected group. + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Case of independent mode or multimode (for devices with several ADCs): */ + /* Set multimode state. */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable conversion of injected group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* If automatic injected conversion is enabled, conversion will start */ + /* after next regular group conversion. */ + /* Case of multimode enabled (for devices with several ADCs): if ADC is */ + /* slave, ADC is enabled only (conversion is not started). If ADC is */ + /* master, ADC is enabled and conversion is started. */ + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) + { + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + { + /* Start ADC conversion on injected group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); + } + else + { + /* Start ADC conversion on injected group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for injected group conversion to be completed. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Variables for polling in case of scan mode enabled and polling for each */ + /* conversion. */ + __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Polling for end of conversion: differentiation if single/sequence */ + /* conversion. */ + /* For injected group, flag JEOC is set only at the end of the sequence, */ + /* not for each conversion within the sequence. */ + /* - If single conversion for injected group (scan mode disabled or */ + /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ + /* conversion completion. */ + /* - If sequence conversion for injected group (scan mode enabled and */ + /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ + /* sequence. */ + /* To poll for each conversion, the maximum conversion time is computed */ + /* from ADC conversion time (selected sampling time + conversion time of */ + /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ + /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ + /* As flag JEOC is not set after each conversion, no timeout status can */ + /* be set. */ + if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) + { + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + } + else + { + /* Replace polling by wait for maximum conversion time */ + /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ + /* and ADC maximum conversion cycles on all channels. */ + /* - Wait for the expected ADC clock cycles delay */ + Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock + / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) + * ADC_CONVCYCLES_MAX_RANGE(hadc) ); + + while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + Conversion_Timeout_CPU_cycles ++; + } + } + + /* Clear injected group conversion flag */ + /* Note: On STM32F1 ADC, clear regular conversion flag raised */ + /* simultaneously. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger or by automatic injected conversion */ + /* from group regular. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of injected group with interruption. + * - JEOC (end of conversion of injected group) + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Case of independent mode or multimode (for devices with several ADCs): */ + /* Set multimode state. */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Start conversion of injected group if software start has been selected */ + /* and if automatic injected conversion is disabled. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* If automatic injected conversion is enabled, conversion will start */ + /* after next regular group conversion. */ + if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) + { + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) + { + /* Start ADC conversion on injected group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); + } + else + { + /* Start ADC conversion on injected group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** + * @brief Enables ADC, starts conversion of regular group and transfers result + * through DMA. + * Multimode must have been previously configured using + * HAL_ADCEx_MultiModeConfigChannel() function. + * Interruptions enabled in this function: + * - DMA transfer complete + * - DMA half transfer + * Each of these interruptions has its dedicated callback function. + * @note: On STM32F1 devices, ADC slave regular group must be configured + * with conversion trigger ADC_SOFTWARE_START. + * @note: ADC slave can be enabled preliminarily using single-mode + * HAL_ADC_Start() function. + * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @param pData: The destination Buffer address. + * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ADC_HandleTypeDef tmphadcSlave={0}; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + + /* On STM32F1 devices, ADC slave regular group must be configured with */ + /* conversion trigger ADC_SOFTWARE_START. */ + /* Note: External trigger of ADC slave must be enabled, it is already done */ + /* into function "HAL_ADC_Init()". */ + if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Enable the ADC peripherals: master and slave (in case if not already */ + /* enabled previously) */ + tmp_hal_status = ADC_Enable(hadc); + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Enable(&tmphadcSlave); + } + + /* Start conversion if all ADCs of multimode are effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state (ADC master) */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC DMA mode of ADC master */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Start conversion of regular group if software start has been selected. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Note: Alternate trigger for single conversion could be to force an */ + /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ + if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) + { + /* Start ADC conversion on regular group with SW start */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); + } + else + { + /* Start ADC conversion on regular group with external trigger */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @note Multimode is kept enabled after this function. To disable multimode + * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be + * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). + * @note In case of DMA configured in circular mode, function + * HAL_ADC_Stop_DMA must be called after this function with handle of + * ADC slave, to properly disable the DMA channel. + * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ADC_HandleTypeDef tmphadcSlave={0}; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC master peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if(tmp_hal_status == HAL_OK) + { + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + + /* Disable ADC slave peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); + + /* Check if ADC is effectively disabled */ + if(tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Disable ADC DMA mode */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); + + /* Reset configuration of ADC DMA continuous request for dual mode */ + CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* while DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Change ADC state (ADC master) */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @brief Get ADC injected group conversion result. + * @note Reading register JDRx automatically clears ADC flag JEOC + * (ADC group injected end of unitary conversion). + * @note This function does not clear ADC flag JEOS + * (ADC group injected end of sequence conversion) + * Occurrence of flag JEOS rising: + * - If sequencer is composed of 1 rank, flag JEOS is equivalent + * to flag JEOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag JEOC only is raised, at the end of the scan sequence + * both flags JEOC and EOS are raised. + * Flag JEOS must not be cleared by this function because + * it would not be compliant with low power features + * (feature low power auto-wait, not available on all STM32 families). + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). + * @param hadc: ADC handle + * @param InjectedRank: the converted ADC injected rank. + * This parameter can be one of the following values: + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + * @retval ADC group injected conversion data + */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + uint32_t tmp_jdr = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Get ADC converted value */ + switch(InjectedRank) + { + case ADC_INJECTED_RANK_4: + tmp_jdr = hadc->Instance->JDR4; + break; + case ADC_INJECTED_RANK_3: + tmp_jdr = hadc->Instance->JDR3; + break; + case ADC_INJECTED_RANK_2: + tmp_jdr = hadc->Instance->JDR2; + break; + case ADC_INJECTED_RANK_1: + default: + tmp_jdr = hadc->Instance->JDR1; + break; + } + + /* Return ADC converted value */ + return tmp_jdr; +} + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** + * @brief Returns the last ADC Master&Slave regular conversions results data + * in the selected multi mode. + * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @retval The converted data value. + */ +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +{ + uint32_t tmpDR = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ + /* only if ADC1 DMA mode is enabled. */ + tmpDR = hadc->Instance->DR; + + if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) + { + tmpDR |= (ADC2->DR << 16U); + } + + /* Return ADC converted value */ + return tmpDR; +} +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + +/** + * @brief Injected conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on injected group + (+) Configure multimode + +@endverbatim + * @{ + */ + +/** + * @brief Configures the ADC injected group and the selected channel to be + * linked to the injected group. + * @note Possibility to update parameters on the fly: + * This function initializes injected group, following calls to this + * function can be used to reconfigure some parameters of structure + * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * this function must be called when ADC is not under conversion. + * @param hadc: ADC handle + * @param sConfigInjected: Structure of ADC injected group and ADC channel for + * injected group. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t wait_loop_index = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Configuration of injected group sequencer: */ + /* - if scan mode is disabled, injected channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "InjectedNbrOfConversion" is discarded. */ + /* Note: Scan mode is present by hardware on this device and, if */ + /* disabled, discards automatically nb of conversions. Anyway, nb of */ + /* conversions is forced to 0x00 for alignment over all STM32 devices. */ + /* - if scan mode is enabled, injected channels sequence length is set to */ + /* parameter "InjectedNbrOfConversion". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) + { + /* Clear the old SQx bits for all injected ranks */ + MODIFY_REG(hadc->Instance->JSQR , + ADC_JSQR_JL | + ADC_JSQR_JSQ4 | + ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | + ADC_JSQR_JSQ1 , + ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, + ADC_INJECTED_RANK_1, + 0x01U)); + } + /* If another injected rank than rank1 was intended to be set, and could */ + /* not due to ScanConvMode disabled, error is reported. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + } + else + { + /* Since injected channels rank conv. order depends on total number of */ + /* injected conversions, selected rank must be below or equal to total */ + /* number of injected conversions to be updated. */ + if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) + { + /* Clear the old SQx bits for the selected rank */ + /* Set the SQx bits for the selected rank */ + MODIFY_REG(hadc->Instance->JSQR , + + ADC_JSQR_JL | + ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , + + ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | + ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) ); + } + else + { + /* Clear the old SQx bits for the selected rank */ + MODIFY_REG(hadc->Instance->JSQR , + + ADC_JSQR_JL | + ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , + + 0x00000000U); + } + } + + /* Configuration of injected group */ + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - external trigger to start conversion */ + /* Parameters update not conditioned to ADC state: */ + /* - Automatic injected conversion */ + /* - Injected discontinuous mode */ + /* Note: In case of ADC already enabled, caution to not launch an unwanted */ + /* conversion while modifying register CR2 by writing 1 to bit ADON. */ + if (ADC_IS_ENABLE(hadc) == RESET) + { + MODIFY_REG(hadc->Instance->CR2 , + ADC_CR2_JEXTSEL | + ADC_CR2_ADON , + ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) ); + } + + + /* Configuration of injected group */ + /* - Automatic injected conversion */ + /* - Injected discontinuous mode */ + + /* Automatic injected conversion can be enabled if injected group */ + /* external triggers are disabled. */ + if (sConfigInjected->AutoInjectedConv == ENABLE) + { + if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) + { + SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + } + + /* Injected discontinuous can be enabled only if auto-injected mode is */ + /* disabled. */ + if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) + { + if (sConfigInjected->AutoInjectedConv == DISABLE) + { + SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + } + + + /* InjectedChannel sampling time configuration */ + /* For channels 10 to 17 */ + if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) + { + MODIFY_REG(hadc->Instance->SMPR1 , + ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) , + ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + } + else /* For channels 0 to 9 */ + { + MODIFY_REG(hadc->Instance->SMPR2 , + ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) , + ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + } + + /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || + (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) + { + SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); + } + + + /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ + switch(sConfigInjected->InjectedRank) + { + case 1: + /* Set injected channel 1 offset */ + MODIFY_REG(hadc->Instance->JOFR1, + ADC_JOFR1_JOFFSET1, + sConfigInjected->InjectedOffset); + break; + case 2: + /* Set injected channel 2 offset */ + MODIFY_REG(hadc->Instance->JOFR2, + ADC_JOFR2_JOFFSET2, + sConfigInjected->InjectedOffset); + break; + case 3: + /* Set injected channel 3 offset */ + MODIFY_REG(hadc->Instance->JOFR3, + ADC_JOFR3_JOFFSET3, + sConfigInjected->InjectedOffset); + break; + case 4: + default: + MODIFY_REG(hadc->Instance->JOFR4, + ADC_JOFR4_JOFFSET4, + sConfigInjected->InjectedOffset); + break; + } + + /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || + (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) + { + /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ + /* measurement channels (VrefInt/TempSensor). If these channels are */ + /* intended to be set on other ADC instances, an error is reported. */ + if (hadc->Instance == ADC1) + { + if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) + { + SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); + + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +/** + * @brief Enable ADC multimode and configure multimode parameters + * @note Possibility to update parameters on the fly: + * This function initializes multimode parameters, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_MultiModeTypeDef" on the fly, without resetting + * the ADCs (both ADCs of the common group). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_MultiModeTypeDef". + * @note To change back configuration from multimode to single mode, ADC must + * be reset (using function HAL_ADC_Init() ). + * @param hadc: ADC handle + * @param multimode: Structure of ADC multimode configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ADC_HandleTypeDef tmphadcSlave={0}; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_MODE(multimode->Mode)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - ADC master and ADC slave DMA configuration */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Multimode mode selection */ + /* To optimize code, all multimode settings can be set when both ADCs of */ + /* the common group are in state: disabled. */ + if ((ADC_IS_ENABLE(hadc) == RESET) && + (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && + (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) ) + { + MODIFY_REG(hadc->Instance->CR1, + ADC_CR1_DUALMOD , + multimode->Mode ); + } + /* If one of the ADC sharing the same common group is enabled, no update */ + /* could be done on neither of the multimode structure parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c index 03d346e..207d196 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c @@ -1,2436 +1,2436 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_can.c - * @author MCD Application Team - * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + Configuration functions - * + Control functions - * + Interrupts management - * + Callbacks functions - * + Peripheral State and Error functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the CAN low level resources by implementing the - HAL_CAN_MspInit(): - (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() - (++) Configure CAN pins - (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function open-drain - (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) - (+++) Configure the CAN interrupt priority using - HAL_NVIC_SetPriority() - (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() - - (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This - function resorts to HAL_CAN_MspInit() for low-level initialization. - - (#) Configure the reception filters using the following configuration - functions: - (++) HAL_CAN_ConfigFilter() - - (#) Start the CAN module using HAL_CAN_Start() function. At this level - the node is active on the bus: it receive messages, and can send - messages. - - (#) To manage messages transmission, the following Tx control functions - can be used: - (++) HAL_CAN_AddTxMessage() to request transmission of a new - message. - (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending - message. - (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx - mailboxes. - (++) HAL_CAN_IsTxMessagePending() to check if a message is pending - in a Tx mailbox. - (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message - sent, if time triggered communication mode is enabled. - - (#) When a message is received into the CAN Rx FIFOs, it can be retrieved - using the HAL_CAN_GetRxMessage() function. The function - HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are - stored in the Rx Fifo. - - (#) Calling the HAL_CAN_Stop() function stops the CAN module. - - (#) The deinitialization is achieved with HAL_CAN_DeInit() function. - - - *** Polling mode operation *** - ============================== - [..] - (#) Reception: - (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() - until at least one message is received. - (++) Then get the message using HAL_CAN_GetRxMessage(). - - (#) Transmission: - (++) Monitor the Tx mailboxes availability until at least one Tx - mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). - (++) Then request transmission of a message using - HAL_CAN_AddTxMessage(). - - - *** Interrupt mode operation *** - ================================ - [..] - (#) Notifications are activated using HAL_CAN_ActivateNotification() - function. Then, the process can be controlled through the - available user callbacks: HAL_CAN_xxxCallback(), using same APIs - HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). - - (#) Notifications can be deactivated using - HAL_CAN_DeactivateNotification() function. - - (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and - CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig - the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and - HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options - here. - (++) Directly get the Rx message in the callback, using - HAL_CAN_GetRxMessage(). - (++) Or deactivate the notification in the callback without - getting the Rx message. The Rx message can then be got later - using HAL_CAN_GetRxMessage(). Once the Rx message have been - read, the notification can be activated again. - - - *** Sleep mode *** - ================== - [..] - (#) The CAN peripheral can be put in sleep mode (low power), using - HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the - current CAN activity (transmission or reception of a CAN frame) will - be completed. - - (#) A notification can be activated to be informed when the sleep mode - will be entered. - - (#) It can be checked if the sleep mode is entered using - HAL_CAN_IsSleepActive(). - Note that the CAN state (accessible from the API HAL_CAN_GetState()) - is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is - submitted (the sleep mode is not yet entered), and become - HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. - - (#) The wake-up from sleep mode can be triggered by two ways: - (++) Using HAL_CAN_WakeUp(). When returning from this function, - the sleep mode is exited (if return status is HAL_OK). - (++) When a start of Rx CAN frame is detected by the CAN peripheral, - if automatic wake up mode is enabled. - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. - - Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - - By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, - all callbacks are set to the corresponding weak functions: - example @ref HAL_CAN_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() - or @ref HAL_CAN_Init() function. - - When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -#if defined(CAN1) - -/** @defgroup CAN CAN - * @brief CAN driver modules - * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_TIMEOUT_VALUE 10U -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Init : Initialize and configure the CAN. - (+) HAL_CAN_DeInit : De-initialize the CAN. - (+) HAL_CAN_MspInit : Initialize the CAN MSP. - (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); - assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); - assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Reset callbacks to legacy functions */ - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ - hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ - hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hcan->MspInitCallback == NULL) - { - hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware: CLOCK, NVIC */ - hcan->MspInitCallback(hcan); - } - -#else - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Init the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspInit(hcan); - } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Set the time triggered communication mode */ - if (hcan->Init.TimeTriggeredMode == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - - /* Set the automatic bus-off management */ - if (hcan->Init.AutoBusOff == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AutoWakeUp == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - - /* Set the automatic retransmission */ - if (hcan->Init.AutoRetransmission == ENABLE) - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - else - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.ReceiveFifoLocked == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TransmitFifoPriority == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - - /* Set the bit timing register */ - WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - hcan->Init.SyncJumpWidth | - hcan->Init.TimeSeg1 | - hcan->Init.TimeSeg2 | - (hcan->Init.Prescaler - 1U))); - - /* Initialize the error code */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the CAN peripheral registers to their default - * reset values. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) -{ - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Stop the CAN module */ - (void)HAL_CAN_Stop(hcan); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->MspDeInitCallback == NULL) - { - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: CLOCK, NVIC */ - hcan->MspDeInitCallback(hcan); - -#else - /* DeInit the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspDeInit(hcan); -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - - /* Reset the CAN peripheral */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_RESET; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspDeInit could be implemented in the user file - */ -} - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/** - * @brief Register a CAN CallBack. - * To be used instead of the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = pCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = pCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = pCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = pCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a CAN CallBack. - * CAN callabck is redirected to the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = HAL_CAN_SleepCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = HAL_CAN_ErrorCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * -@verbatim - ============================================================================== - ##### Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters - -@endverbatim - * @{ - */ - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) -{ - uint32_t filternbrbitpos; - CAN_TypeDef *can_ip = hcan->Instance; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the parameters */ - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); - -#if defined(CAN2) - /* CAN1 and CAN2 are dual instances with 28 common filters banks */ - /* Select master instance to access the filter banks */ - can_ip = CAN1; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); -#else - /* CAN1 is single instance with 14 dedicated filters banks */ - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif - - /* Initialisation mode for the filter */ - SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - -#if defined(CAN2) - /* Select the start filter number of CAN2 slave instance */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); - SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); - -#endif - /* Convert filter number into bit position */ - filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - - /* Filter Deactivation */ - CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - { - /* 16-bit scale for the filter */ - CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - { - /* 32-bit scale for the filter */ - SET_BIT(can_ip->FS1R, filternbrbitpos); - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - { - /* Id/Mask mode for the filter*/ - CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /* Identifier list mode for the filter*/ - SET_BIT(can_ip->FM1R, filternbrbitpos); - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - } - else - { - /* FIFO 1 assignation for the filter */ - SET_BIT(can_ip->FFA1R, filternbrbitpos); - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - { - SET_BIT(can_ip->FA1R, filternbrbitpos); - } - - /* Leave the initialisation mode for the filter */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * -@verbatim - ============================================================================== - ##### Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Start : Start the CAN module - (+) HAL_CAN_Stop : Stop the CAN module - (+) HAL_CAN_RequestSleep : Request sleep mode entry. - (+) HAL_CAN_WakeUp : Wake up from sleep mode. - (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. - (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes - and activate the corresponding - transmission request - (+) HAL_CAN_AbortTxRequest : Abort transmission request - (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level - (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is - pending on the selected Tx mailbox - (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO - (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level - -@endverbatim - * @{ - */ - -/** - * @brief Start the CAN module. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_READY) - { - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_LISTENING; - - /* Request leave initialisation */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - - return HAL_ERROR; - } -} - -/** - * @brief Stop the CAN module and enable access to configuration registers. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_LISTENING) - { - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - - return HAL_ERROR; - } -} - -/** - * @brief Request the sleep mode (low power) entry. - * When returning from this function, Sleep mode will be entered - * as soon as the current CAN activity (transmission or reception - * of a CAN frame) has been completed. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Request Sleep mode */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Wake up from sleep mode. - * When returning with HAL_OK status from this function, Sleep mode - * is exited. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) -{ - __IO uint32_t count = 0; - uint32_t timeout = 1000000U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Wake up request */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Wait sleep mode is exited */ - do - { - /* Increment counter */ - count++; - - /* Check if timeout is reached */ - if (count > timeout) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Check is sleep mode is active. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Status - * - 0 : Sleep mode is not active. - * - 1 : Sleep mode is active. - */ -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Sleep mode */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - status = 1U; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Add a message to the first free Tx mailbox and activate the - * corresponding transmission request. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. - * @param aData array containing the payload of the Tx frame. - * @param pTxMailbox pointer to a variable where the function will return - * the TxMailbox used to store the Tx message. - * This parameter can be a value of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) -{ - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - uint32_t tsr = READ_REG(hcan->Instance->TSR); - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(pHeader->IDE)); - assert_param(IS_CAN_RTR(pHeader->RTR)); - assert_param(IS_CAN_DLC(pHeader->DLC)); - if (pHeader->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(pHeader->StdId)); - } - else - { - assert_param(IS_CAN_EXTID(pHeader->ExtId)); - } - assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check that all the Tx mailboxes are not full */ - if (((tsr & CAN_TSR_TME0) != 0U) || - ((tsr & CAN_TSR_TME1) != 0U) || - ((tsr & CAN_TSR_TME2) != 0U)) - { - /* Select an empty transmit mailbox */ - transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - - /* Check transmit mailbox value */ - if (transmitmailbox > 2U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; - - return HAL_ERROR; - } - - /* Store the Tx mailbox */ - *pTxMailbox = (uint32_t)1 << transmitmailbox; - - /* Set up the Id */ - if (pHeader->IDE == CAN_ID_STD) - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - pHeader->RTR); - } - else - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - pHeader->IDE | - pHeader->RTR); - } - - /* Set up the DLC */ - hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - - /* Set up the Transmit Global Time mode */ - if (pHeader->TransmitGlobalTime == ENABLE) - { - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - } - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | - ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | - ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | - ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); - - /* Request transmission */ - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Abort transmission requests - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of the Tx Mailboxes to abort. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 */ - if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) - { - /* Add cancellation request for Tx Mailbox 0 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); - } - - /* Check Tx Mailbox 1 */ - if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) - { - /* Add cancellation request for Tx Mailbox 1 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); - } - - /* Check Tx Mailbox 2 */ - if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) - { - /* Add cancellation request for Tx Mailbox 2 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Number of free Tx Mailboxes. - */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) -{ - uint32_t freelevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) - { - freelevel++; - } - } - - /* Return Tx Mailboxes free level */ - return freelevel; -} - -/** - * @brief Check if a transmission request is pending on the selected Tx - * Mailboxes. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of Tx Mailboxes to check. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval Status - * - 0 : No pending transmission request on any selected Tx Mailboxes. - * - 1 : Pending transmission request on at least one of the selected - * Tx Mailbox. - */ -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check pending transmission request on the selected Tx Mailboxes */ - if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) - { - status = 1U; - } - } - - /* Return status */ - return status; -} - -/** - * @brief Return timestamp of Tx message sent, if time triggered communication - mode is enabled. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailbox Tx Mailbox where the timestamp of message sent will be - * read. - * This parameter can be one value of @arg CAN_Tx_Mailboxes. - * @retval Timestamp of message sent from Tx Mailbox. - */ -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) -{ - uint32_t timestamp = 0U; - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Select the Tx mailbox */ - transmitmailbox = POSITION_VAL(TxMailbox); - - /* Get timestamp */ - timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; - } - - /* Return the timestamp */ - return timestamp; -} - -/** - * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Fifo number of the received message to be read. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header - * of the Rx frame will be stored. - * @param aData array where the payload of the Rx frame will be stored. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the Rx FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - - /* Get the header */ - pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - if (pHeader->IDE == CAN_ID_STD) - { - pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - } - else - { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; - } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; - pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - - /* Get the data */ - aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - - /* Release the FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Release RX FIFO 0 */ - SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Release RX FIFO 1 */ - SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Rx FIFO fill level. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Rx FIFO. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @retval Number of messages available in Rx FIFO. - */ -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) -{ - uint32_t filllevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - if (RxFifo == CAN_RX_FIFO0) - { - filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; - } - else /* RxFifo == CAN_RX_FIFO1 */ - { - filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; - } - } - - /* Return Rx FIFO fill level */ - return filllevel; -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * -@verbatim - ============================================================================== - ##### Interrupts management ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ActivateNotification : Enable interrupts - (+) HAL_CAN_DeactivateNotification : Disable interrupts - (+) HAL_CAN_IRQHandler : Handles CAN interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Enable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param ActiveITs indicates which interrupts will be enabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(ActiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Enable the selected interrupts */ - __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Disable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param InactiveITs indicates which interrupts will be disabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(InactiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Disable the selected interrupts */ - __HAL_CAN_DISABLE_IT(hcan, InactiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Handles CAN interrupt request - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) -{ - uint32_t errorcode = HAL_CAN_ERROR_NONE; - uint32_t interrupts = READ_REG(hcan->Instance->IER); - uint32_t msrflags = READ_REG(hcan->Instance->MSR); - uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - uint32_t esrflags = READ_REG(hcan->Instance->ESR); - - /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - { - /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - - if ((tsrflags & CAN_TSR_TXOK0) != 0U) - { - /* Transmission Mailbox 0 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST0; - } - else if ((tsrflags & CAN_TSR_TERR0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR0; - } - else - { - /* Transmission Mailbox 0 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - - if ((tsrflags & CAN_TSR_TXOK1) != 0U) - { - /* Transmission Mailbox 1 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST1; - } - else if ((tsrflags & CAN_TSR_TERR1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR1; - } - else - { - /* Transmission Mailbox 1 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - - if ((tsrflags & CAN_TSR_TXOK2) != 0U) - { - /* Transmission Mailbox 2 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST2; - } - else if ((tsrflags & CAN_TSR_TERR2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR2; - } - else - { - /* Transmission Mailbox 2 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - } - - /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - { - if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - { - /* Set CAN error code to Rx Fifo 0 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV0; - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } - } - - /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - { - if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - { - /* Clear FIFO 0 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - - /* Receive FIFO 0 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - { - /* Receive FIFO 0 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - { - if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - { - /* Set CAN error code to Rx Fifo 1 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV1; - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } - } - - /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - { - if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - { - /* Clear FIFO 1 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - - /* Receive FIFO 1 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - { - /* Receive FIFO 1 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - { - if ((msrflags & CAN_MSR_SLAKI) != 0U) - { - /* Clear Sleep interrupt Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - - /* Sleep Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->SleepCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_SleepCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != 0U) - { - if ((msrflags & CAN_MSR_WKUI) != 0U) - { - /* Clear WakeUp Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - - /* WakeUp Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->WakeUpFromRxMsgCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_WakeUpFromRxMsgCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != 0U) - { - if ((msrflags & CAN_MSR_ERRI) != 0U) - { - /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - ((esrflags & CAN_ESR_EWGF) != 0U)) - { - /* Set CAN error code to Error Warning */ - errorcode |= HAL_CAN_ERROR_EWG; - - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - ((esrflags & CAN_ESR_EPVF) != 0U)) - { - /* Set CAN error code to Error Passive */ - errorcode |= HAL_CAN_ERROR_EPV; - - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != 0U) && - ((esrflags & CAN_ESR_BOFF) != 0U)) - { - /* Set CAN error code to Bus-Off */ - errorcode |= HAL_CAN_ERROR_BOF; - - /* No need for clear of Error Bus-Off as read-only */ - } - - /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - ((esrflags & CAN_ESR_LEC) != 0U)) - { - switch (esrflags & CAN_ESR_LEC) - { - case (CAN_ESR_LEC_0): - /* Set CAN error code to Stuff error */ - errorcode |= HAL_CAN_ERROR_STF; - break; - case (CAN_ESR_LEC_1): - /* Set CAN error code to Form error */ - errorcode |= HAL_CAN_ERROR_FOR; - break; - case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to Acknowledgement error */ - errorcode |= HAL_CAN_ERROR_ACK; - break; - case (CAN_ESR_LEC_2): - /* Set CAN error code to Bit recessive error */ - errorcode |= HAL_CAN_ERROR_BR; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to Bit Dominant error */ - errorcode |= HAL_CAN_ERROR_BD; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - errorcode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - } - } - - /* Clear ERRI Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - } - - /* Call the Error call Back in case of Errors */ - if (errorcode != HAL_CAN_ERROR_NONE) - { - /* Update error code in handle */ - hcan->ErrorCode |= errorcode; - - /* Call Error callback function */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->ErrorCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_ErrorCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * -@verbatim - ============================================================================== - ##### Callback functions ##### - ============================================================================== - [..] - This subsection provides the following callback functions: - (+) HAL_CAN_TxMailbox0CompleteCallback - (+) HAL_CAN_TxMailbox1CompleteCallback - (+) HAL_CAN_TxMailbox2CompleteCallback - (+) HAL_CAN_TxMailbox0AbortCallback - (+) HAL_CAN_TxMailbox1AbortCallback - (+) HAL_CAN_TxMailbox2AbortCallback - (+) HAL_CAN_RxFifo0MsgPendingCallback - (+) HAL_CAN_RxFifo0FullCallback - (+) HAL_CAN_RxFifo1MsgPendingCallback - (+) HAL_CAN_RxFifo1FullCallback - (+) HAL_CAN_SleepCallback - (+) HAL_CAN_WakeUpFromRxMsgCallback - (+) HAL_CAN_ErrorCallback - -@endverbatim - * @{ - */ - -/** - * @brief Transmission Mailbox 0 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 0 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Rx FIFO 1 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 1 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Sleep callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_SleepCallback could be implemented in the user file - */ -} - -/** - * @brief WakeUp from Rx message callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the - user file - */ -} - -/** - * @brief Error CAN callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) HAL_CAN_GetState() : Return the CAN state. - (+) HAL_CAN_GetError() : Return the CAN error codes if any. - (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. - -@endverbatim - * @{ - */ - -/** - * @brief Return the CAN state. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL state - */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check sleep mode acknowledge flag */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - /* Sleep mode is active */ - state = HAL_CAN_STATE_SLEEP_ACTIVE; - } - /* Check sleep mode request flag */ - else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) - { - /* Sleep mode request is pending */ - state = HAL_CAN_STATE_SLEEP_PENDING; - } - else - { - /* Neither sleep mode request nor sleep mode acknowledge */ - } - } - - /* Return CAN state */ - return state; -} - -/** - * @brief Return the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval CAN Error Code - */ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) -{ - /* Return CAN error code */ - return hcan->ErrorCode; -} - -/** - * @brief Reset the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Reset CAN error code */ - hcan->ErrorCode = 0U; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - status = HAL_ERROR; - } - - /* Return the status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CAN_MODULE_ENABLED */ - -/** - * @} - */ - -#endif /* CAN1 */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be triggered by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callback is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif /* CAN3 */ + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif /* CAN3 */ + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c index a89150a..9342123 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c @@ -1,505 +1,529 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M3 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest preemption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value 0x0F. - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32f1xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (preemption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00U; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -#if (__MPU_PRESENT == 1U) -/** - * @brief Disables the MPU - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0U; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Ensure MPU setting take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00U; - MPU->RASR = 0x00U; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M3 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f1xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) + * @param PreemptPriority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c new file mode 100755 index 0000000..810ba9b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + __HAL_CRC_SET_IDR(hcrc, 0); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 32-bit CRC value of a 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 32-bit CRC value of a 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 32-bit CRC value of a 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer. + * @param BufferLength input data buffer length (number of uint32_t words). + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 32-bit CRC value of a 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer. + * @param BufferLength input data buffer length (number of uint32_t words). + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c index c9bc061..80b65a4 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -1,899 +1,897 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to the Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Channel, program the required configuration through the following parameters: - Channel request, Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode - using HAL_DMA_Init() function. - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e. a member of DMA handle structure). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - - /* Check the DMA handle allocation */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - -#if defined (DMA2) - /* calculation of the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } -#else - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; -#endif /* DMA2 */ - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - /* Check the DMA handle allocation */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0U; - - /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0U; - - /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0U; - - /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0U; - -#if defined (DMA2) - /* calculation of the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } -#else - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; -#endif /* DMA2 */ - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); - - /* Clean all callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Reset the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Reset the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - /* Enable the transfer Error interrupt */ - if(NULL != hdma->XferHalfCpltCallback) - { - /* Enable the Half transfer complete interrupt as well */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - } - else - { - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - } - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(hdma->State != HAL_DMA_STATE_BUSY) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - } - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0U; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Transfer Complete flag */ - temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); - } - else - { - /* Half Transfer Complete flag */ - temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) - { - if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management **************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Disable ALL DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - return; -} - -/** - * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA hande state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - /* Return DMA handle state */ - return hdma->State; -} - -/** - * @brief Return the DMA error code. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e. a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if(NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + } + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel: Specifies the DMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + } + else + { + /* Half Transfer Complete flag */ + temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + { + if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + return; +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c index 60030e8..ef8e005 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c @@ -1,555 +1,553 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_exti.c - * @author MCD Application Team - * @brief EXTI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### EXTI Peripheral features ##### - ============================================================================== - [..] - (+) Each Exti line can be configured within this driver. - - (+) Exti line can be configured in 3 different modes - (++) Interrupt - (++) Event - (++) Both of them - - (+) Configurable Exti lines can be configured with 3 different triggers - (++) Rising - (++) Falling - (++) Both of them - - (+) When set in interrupt mode, configurable Exti lines have two different - interrupts pending registers which allow to distinguish which transition - occurs: - (++) Rising edge pending interrupt - (++) Falling - - (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can - be selected through multiplexer. - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). - (++) Choose the interrupt line number by setting "Line" member from - EXTI_ConfigTypeDef structure. - (++) Configure the interrupt and/or event mode using "Mode" member from - EXTI_ConfigTypeDef structure. - (++) For configurable lines, configure rising and/or falling trigger - "Trigger" member from EXTI_ConfigTypeDef structure. - (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" - member from GPIO_InitTypeDef structure. - - (#) Get current Exti configuration of a dedicated line using - HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - - (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). - (++) Provide exiting handle as first parameter. - (++) Provide which callback will be registered using one value from - EXTI_CallbackIDTypeDef. - (++) Provide callback function pointer. - - (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rule: - * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out - * of bounds [0,3] in following API : - * HAL_EXTI_SetConfigLine - * HAL_EXTI_GetConfigLine - * HAL_EXTI_ClearConfigLine - */ - -#ifdef HAL_EXTI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup EXTI_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * -@verbatim - =============================================================================== - ##### Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Set configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on EXTI configuration to be set. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_EXTI_LINE(pExtiConfig->Line)); - assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - - /* Assign line number to handle */ - hexti->Line = pExtiConfig->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); - - /* Configure rising trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) - { - EXTI->RTSR |= maskline; - } - else - { - EXTI->RTSR &= ~maskline; - } - - /* Configure falling trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) - { - EXTI->FTSR |= maskline; - } - else - { - EXTI->FTSR &= ~maskline; - } - - - /* Configure gpio port selection in case of gpio exti line */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = AFIO->EXTICR[linepos >> 2u]; - regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - AFIO->EXTICR[linepos >> 2u] = regval; - } - } - - /* Configure interrupt mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) - { - EXTI->IMR |= maskline; - } - else - { - EXTI->IMR &= ~maskline; - } - - /* Configure event mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) - { - EXTI->EMR |= maskline; - } - else - { - EXTI->EMR &= ~maskline; - } - - return HAL_OK; -} - -/** - * @brief Get configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on structure to store Exti configuration. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* Store handle line number to configuration structure */ - pExtiConfig->Line = hexti->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Get core mode : interrupt */ - - /* Check if selected line is enable */ - if ((EXTI->IMR & maskline) != 0x00u) - { - pExtiConfig->Mode = EXTI_MODE_INTERRUPT; - } - else - { - pExtiConfig->Mode = EXTI_MODE_NONE; - } - - /* Get event mode */ - /* Check if selected line is enable */ - if ((EXTI->EMR & maskline) != 0x00u) - { - pExtiConfig->Mode |= EXTI_MODE_EVENT; - } - - /* Get default Trigger and GPIOSel configuration */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; - - /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - /* Check if configuration of selected line is enable */ - if ((EXTI->RTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; - } - - /* Get falling configuration */ - /* Check if configuration of selected line is enable */ - if ((EXTI->FTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; - } - - /* Get Gpio port selection for gpio lines */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = AFIO->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); - } - } - - return HAL_OK; -} - -/** - * @brief Clear whole configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Clear interrupt mode */ - EXTI->IMR = (EXTI->IMR & ~maskline); - - /* 2] Clear event mode */ - EXTI->EMR = (EXTI->EMR & ~maskline); - - /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0x00u) - { - EXTI->RTSR = (EXTI->RTSR & ~maskline); - EXTI->FTSR = (EXTI->FTSR & ~maskline); - - /* Get Gpio port selection for gpio lines */ - if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = AFIO->EXTICR[linepos >> 2u]; - regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - AFIO->EXTICR[linepos >> 2u] = regval; - } - } - - return HAL_OK; -} - -/** - * @brief Register callback for a dedicated Exti line. - * @param hexti Exti handle. - * @param CallbackID User callback identifier. - * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. - * @param pPendingCbfn function pointer to be stored as callback. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_EXTI_COMMON_CB_ID: - hexti->PendingCallback = pPendingCbfn; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Store line number as handle private field. - * @param hexti Exti handle. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - else - { - /* Store line number as handle private field */ - hexti->Line = ExtiLine; - - return HAL_OK; - } -} - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Handle EXTI interrupt request. - * @param hexti Exti handle. - * @retval none. - */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t maskline; - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Get pending bit */ - regval = (EXTI->PR & maskline); - if (regval != 0x00u) - { - /* Clear pending bit */ - EXTI->PR = maskline; - - /* Call callback */ - if (hexti->PendingCallback != NULL) - { - hexti->PendingCallback(); - } - } -} - -/** - * @brief Get interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be checked. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval 1 if interrupt is pending else 0. - */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t regval; - uint32_t maskline; - uint32_t linepos; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Prevent unused argument compilation warning */ - UNUSED(Edge); - - /* Compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* return 1 if bit is set else 0 */ - regval = ((EXTI->PR & maskline) >> linepos); - return regval; -} - -/** - * @brief Clear interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be clear. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval None. - */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Prevent unused argument compilation warning */ - UNUSED(Edge); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Clear Pending bit */ - EXTI->PR = maskline; -} - -/** - * @brief Generate a software interrupt for a dedicated line. - * @param hexti Exti handle. - * @retval None. - */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Generate Software interrupt */ - EXTI->SWIER = maskline; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_EXTI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & AFIO_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t maskline; + uint32_t linepos; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Prevent unused argument compilation warning */ + UNUSED(Edge); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Prevent unused argument compilation warning */ + UNUSED(Edge); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c index 50abf92..fe5e596 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c @@ -1,967 +1,959 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) Option Bytes programming - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F1xx devices. - - (#) FLASH Memory I/O Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase page, erase all pages - (++) Program functions: half word, word and doubleword - (#) FLASH Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Lock and Unlock the Option Bytes - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - (++) Erase Option Bytes - (++) Program the data Option Bytes - (++) Get the Write protection. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group - includes all needed functions to: - (++) Handle FLASH interrupts - (++) Wait for last FLASH operation according to its status - (++) Get error flag status - - [..] In addition to these function, this driver includes a set of macros allowing - to handle the following operations: - - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the half cycle access - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro ---------------------------- ---------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_SetErrorCode(void); -extern void FLASH_PageErase(uint32_t PageAddress); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Program halfword, word or double word at a specified address - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @note FLASH should be previously erased before new programmation (only exception to this - * is when 0x0000 is programmed) - * - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: Specifies the address to be programmed. - * @param Data: Specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint8_t index = 0; - uint8_t nbiterations = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - -#if defined(FLASH_BANK2_END) - if(Address <= FLASH_BANK1_END) - { -#endif /* FLASH_BANK2_END */ - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); -#if defined(FLASH_BANK2_END) - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_BANK2_END */ - - if(status == HAL_OK) - { - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - /* Program halfword (16-bit) at a specified address. */ - nbiterations = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /* Program word (32-bit = 2*16-bit) at a specified address. */ - nbiterations = 2U; - } - else - { - /* Program double word (64-bit = 4*16-bit) at a specified address. */ - nbiterations = 4U; - } - - for (index = 0U; index < nbiterations; index++) - { - FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); - -#if defined(FLASH_BANK2_END) - if(Address <= FLASH_BANK1_END) - { -#endif /* FLASH_BANK2_END */ - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); -#if defined(FLASH_BANK2_END) - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); - } -#endif /* FLASH_BANK2_END */ - /* In case of error, stop programation procedure */ - if (status != HAL_OK) - { - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program halfword, word or double word at a specified address with interrupt enabled. - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: Specifies the address to be programmed. - * @param Data: Specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - -#if defined(FLASH_BANK2_END) - /* If procedure already ongoing, reject the next one */ - if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - return HAL_ERROR; - } - - if(Address <= FLASH_BANK1_END) - { - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); - - }else - { - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); - } -#else - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); -#endif /* FLASH_BANK2_END */ - - pFlash.Address = Address; - pFlash.Data = Data; - - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; - /* Program halfword (16-bit) at a specified address. */ - pFlash.DataRemaining = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; - /* Program word (32-bit : 2*16-bit) at a specified address. */ - pFlash.DataRemaining = 2U; - } - else - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; - /* Program double word (64-bit : 4*16-bit) at a specified address. */ - pFlash.DataRemaining = 4U; - } - - /* Program halfword (16-bit) at a specified address. */ - FLASH_Program_HalfWord(Address, (uint16_t)Data); - - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t addresstmp = 0U; - - /* Check FLASH operation error flags */ -#if defined(FLASH_BANK2_END) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) -#else - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) -#endif /* FLASH_BANK2_END */ - { - /* Return the faulty address */ - addresstmp = pFlash.Address; - /* Reset address */ - pFlash.Address = 0xFFFFFFFFU; - - /* Save the Error code */ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(addresstmp); - - /* Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ -#if defined(FLASH_BANK2_END) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); -#else - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); -#endif /* FLASH_BANK2_END */ - - /* Process can continue only if no error detected */ - if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still pages to erase */ - if(pFlash.DataRemaining != 0U) - { - addresstmp = pFlash.Address; - /*Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - - /*Increment sector number*/ - addresstmp = pFlash.Address + FLASH_PAGE_SIZE; - pFlash.Address = addresstmp; - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - FLASH_PageErase(addresstmp); - } - else - { - /* No more pages to Erase, user callback can be called. */ - /* Reset Sector and stop Erase pages procedure */ - pFlash.Address = addresstmp = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - } - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /* Operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - -#if defined(FLASH_BANK2_END) - /* Stop Mass Erase procedure if no pending mass erase on other bank */ - if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) - { -#endif /* FLASH_BANK2_END */ - /* MassErase ended. Return the selected bank */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0U); - - /* Stop Mass Erase procedure*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } -#if defined(FLASH_BANK2_END) - } -#endif /* FLASH_BANK2_END */ - else - { - /* Nb of 16-bit data to program can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0U) - { - /* Increment address to 16-bit */ - pFlash.Address += 2U; - addresstmp = pFlash.Address; - - /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16U); - - /* Operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); - } - else - { - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); - } - else - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); - } - - /* Reset Address and stop Program procedure */ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - } - } - -#if defined(FLASH_BANK2_END) - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); - - /* Process can continue only if no error detected */ - if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still pages to erase*/ - if(pFlash.DataRemaining != 0U) - { - /* Indicate user which page address has been erased*/ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - - /* Increment page address to next page */ - pFlash.Address += FLASH_PAGE_SIZE; - addresstmp = pFlash.Address; - - /* Operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); - - FLASH_PageErase(addresstmp); - } - else - { - /*No more pages to Erase*/ - - /*Reset Address and stop Erase pages procedure*/ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /* Operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); - - if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) - { - /* MassErase ended. Return the selected bank*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0U); - - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - else - { - /* Nb of 16-bit data to program can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0U) - { - /* Increment address to 16-bit */ - pFlash.Address += 2U; - addresstmp = pFlash.Address; - - /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16U); - - /* Operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); - - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); - } - else - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); - } - else - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); - } - - /* Reset Address and stop Program procedure*/ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - } - } -#endif - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { -#if defined(FLASH_BANK2_END) - /* Operation is completed, disable the PG, PER and MER Bits for both bank */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); - - /* Disable End of FLASH Operation and Error source interrupts for both banks */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); -#else - /* Operation is completed, disable the PG, PER and MER Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - - /* Disable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); -#endif /* FLASH_BANK2_END */ - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which returned an error - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } -#if defined(FLASH_BANK2_END) - if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) - { - /* Authorize the FLASH BANK2 Registers access */ - WRITE_REG(FLASH->KEYR2, FLASH_KEY1); - WRITE_REG(FLASH->KEYR2, FLASH_KEY2); - - /* Verify Flash BANK2 is unlocked */ - if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) - { - status = HAL_ERROR; - } - } -#endif /* FLASH_BANK2_END */ - - return status; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_LOCK); - -#if defined(FLASH_BANK2_END) - /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ - SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); - -#endif /* FLASH_BANK2_END */ - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @note This function will reset automatically the MCU. - * @retval None - */ -void HAL_FLASH_OB_Launch(void) -{ - /* Initiates a system reset request to launch the option byte loading */ - HAL_NVIC_SystemReset(); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions - * @brief Peripheral errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode The returned value can be: - * @ref FLASH_Error_Codes - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @param Address specify the address to be programmed. - * @param Data specify the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - -#if defined(FLASH_BANK2_END) - if(Address <= FLASH_BANK1_END) - { -#endif /* FLASH_BANK2_END */ - /* Proceed to program the new data */ - SET_BIT(FLASH->CR, FLASH_CR_PG); -#if defined(FLASH_BANK2_END) - } - else - { - /* Proceed to program the new data */ - SET_BIT(FLASH->CR2, FLASH_CR2_PG); - } -#endif /* FLASH_BANK2_END */ - - /* Write data in the address */ - *(__IO uint16_t*)Address = Data; -} - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - -#if defined(FLASH_BANK2_END) -/** - * @brief Wait for a FLASH BANK2 operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) -{ - /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. - Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) - { - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* If there is an error flag set */ - return HAL_OK; - -} -#endif /* FLASH_BANK2_END */ - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - uint32_t flags = 0U; - -#if defined(FLASH_BANK2_END) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) -#else - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) -#endif /* FLASH_BANK2_END */ - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; -#if defined(FLASH_BANK2_END) - flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; -#else - flags |= FLASH_FLAG_WRPERR; -#endif /* FLASH_BANK2_END */ - } -#if defined(FLASH_BANK2_END) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) -#else - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) -#endif /* FLASH_BANK2_END */ - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; -#if defined(FLASH_BANK2_END) - flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; -#else - flags |= FLASH_FLAG_PGERR; -#endif /* FLASH_BANK2_END */ - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); - } - - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(flags); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F1xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the half cycle access + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programmation (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0; + uint8_t nbiterations = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_BANK2_END */ + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + /* In case of error, stop programation procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + if(Address <= FLASH_BANK1_END) + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); + + }else + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + } +#else + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); +#endif /* FLASH_BANK2_END */ + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + +#if defined(FLASH_BANK2_END) + /* Stop Mass Erase procedure if no pending mass erase on other bank */ + if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) + { +#endif /* FLASH_BANK2_END */ + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + +#if defined(FLASH_BANK2_END) + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase*/ + if(pFlash.DataRemaining != 0U) + { + /* Indicate user which page address has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Increment page address to next page */ + pFlash.Address += FLASH_PAGE_SIZE; + addresstmp = pFlash.Address; + + /* Operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase*/ + + /*Reset Address and stop Erase pages procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) + { + /* MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); + } + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } +#endif + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined(FLASH_BANK2_END) + /* Operation is completed, disable the PG, PER and MER Bits for both bank */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); + + /* Disable End of FLASH Operation and Error source interrupts for both banks */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); +#else + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#if defined(FLASH_BANK2_END) + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + /* Authorize the FLASH BANK2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash BANK2 is unlocked */ + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#endif /* FLASH_BANK2_END */ + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + +#if defined(FLASH_BANK2_END) + /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); + +#endif /* FLASH_BANK2_END */ + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval None + */ +void HAL_FLASH_OB_Launch(void) +{ + /* Initiates a system reset request to launch the option byte loading */ + HAL_NVIC_SystemReset(); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Proceed to program the new data */ + SET_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + +#if defined(FLASH_BANK2_END) +/** + * @brief Wait for a FLASH BANK2 operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) +{ + /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. + Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is an error flag set */ + return HAL_OK; + +} +#endif /* FLASH_BANK2_END */ + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; +#else + flags |= FLASH_FLAG_WRPERR; +#endif /* FLASH_BANK2_END */ + } +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; +#else + flags |= FLASH_FLAG_PGERR; +#endif /* FLASH_BANK2_END */ + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + } + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c index ebd6f8b..33ae03c 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c @@ -1,1127 +1,1121 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + Extended Initialization/de-initialization functions - * + Extended I/O operation functions - * + Extended Peripheral Control functions - * - @verbatim - ============================================================================== - ##### Flash peripheral extended features ##### - ============================================================================== - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F1xxx devices. It includes - - (++) Set/Reset the write protection - (++) Program the user Option Bytes - (++) Get the Read protection Level - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @addtogroup FLASH - * @{ - */ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants - * @{ - */ -#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos -#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos -#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -/* Erase operations */ -static void FLASH_MassErase(uint32_t Banks); -void FLASH_PageErase(uint32_t PageAddress); - -/* Option bytes control */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); -static uint32_t FLASH_OB_GetWRP(void); -static uint32_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetUser(void); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions - * @brief FLASH Memory Erasing functions - * -@verbatim - ============================================================================== - ##### FLASH Erasing Programming functions ##### - ============================================================================== - - [..] The FLASH Memory Erasing functions, includes the following functions: - (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback - is called with parameter 0xFFFFFFFF - - [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - -@endverbatim - * @{ - */ - - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError pointer to variable that - * contains the configuration information on faulty page in case of error - * (0xFFFFFFFF means that all the pages have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t address = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { -#if defined(FLASH_BANK2_END) - if (pEraseInit->Banks == FLASH_BANK_BOTH) - { - /* Mass Erase requested for Bank1 and Bank2 */ - /* Wait for last operation to be completed */ - if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ - (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) - { - /*Mass erase to be done*/ - FLASH_MassErase(FLASH_BANK_BOTH); - - /* Wait for last operation to be completed */ - if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ - (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) - { - status = HAL_OK; - } - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); - } - } - else if (pEraseInit->Banks == FLASH_BANK_2) - { - /* Mass Erase requested for Bank2 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Mass erase to be done*/ - FLASH_MassErase(FLASH_BANK_2); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); - } - } - else -#endif /* FLASH_BANK2_END */ - { - /* Mass Erase requested for Bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Mass erase to be done*/ - FLASH_MassErase(FLASH_BANK_1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - } - } - } - else - { - /* Page Erase is requested */ - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - -#if defined(FLASH_BANK2_END) - /* Page Erase requested on address located on bank2 */ - if(pEraseInit->PageAddress > FLASH_BANK1_END) - { - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - /* Erase by page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); - address += FLASH_PAGE_SIZE) - { - FLASH_PageErase(address); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; - } - } - } - } - else -#endif /* FLASH_BANK2_END */ - { - /* Page Erase requested on address located on bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - /* Erase page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); - address += FLASH_PAGE_SIZE) - { - FLASH_PageErase(address); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; - } - } - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* If procedure already ongoing, reject the next one */ - if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - -#if defined(FLASH_BANK2_END) - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); - -#endif - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - FLASH_MassErase(pEraseInit->Banks); - } - else - { - /* Erase by page to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - pFlash.DataRemaining = pEraseInit->NbPages; - pFlash.Address = pEraseInit->PageAddress; - - /*Erase 1st page and wait for IT*/ - FLASH_PageErase(pEraseInit->PageAddress); - } - - return status; -} - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - option bytes operations. - -@endverbatim - * @{ - */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) -{ - uint8_t rdptmp = OB_RDP_LEVEL_0; - HAL_StatusTypeDef status = HAL_ERROR; - - /* Get the actual read protection Option Byte value */ - rdptmp = FLASH_OB_GetRDP(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Restore the last read protection Option Byte value */ - status = FLASH_OB_RDP_LevelConfig(rdptmp); - } - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Program option bytes - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /* Enable of Write protection on the selected page */ - status = FLASH_OB_EnableWRP(pOBInit->WRPPage); - } - else - { - /* Disable of Write protection on the selected page */ - status = FLASH_OB_DisableWRP(pOBInit->WRPPage); - } - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* USER configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* DATA configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) - { - status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; - - /*Get WRP*/ - pOBInit->WRPPage = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); -} - -/** - * @brief Get the Option byte user data - * @param DATAAdress Address of the option byte DATA - * This parameter can be one of the following values: - * @arg @ref OB_DATA_ADDRESS_DATA0 - * @arg @ref OB_DATA_ADDRESS_DATA1 - * @retval Value programmed in USER data - */ -uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) -{ - uint32_t value = 0; - - if (DATAAdress == OB_DATA_ADDRESS_DATA0) - { - /* Get value programmed in OB USER Data0 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; - } - else - { - /* Get value programmed in OB USER Data1 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; - } - - return value; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ - -/** - * @brief Full erase of FLASH memory Bank - * @param Banks Banks to be erased - * This parameter can be one of the following values: - * @arg @ref FLASH_BANK_1 Bank1 to be erased - @if STM32F101xG - * @arg @ref FLASH_BANK_2 Bank2 to be erased - * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased - @endif - @if STM32F103xG - * @arg @ref FLASH_BANK_2 Bank2 to be erased - * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased - @endif - * - * @retval None - */ -static void FLASH_MassErase(uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - -#if defined(FLASH_BANK2_END) - if(Banks == FLASH_BANK_BOTH) - { - /* bank1 & bank2 will be erased*/ - SET_BIT(FLASH->CR, FLASH_CR_MER); - SET_BIT(FLASH->CR2, FLASH_CR2_MER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - SET_BIT(FLASH->CR2, FLASH_CR2_STRT); - } - else if(Banks == FLASH_BANK_2) - { - /*Only bank2 will be erased*/ - SET_BIT(FLASH->CR2, FLASH_CR2_MER); - SET_BIT(FLASH->CR2, FLASH_CR2_STRT); - } - else - { -#endif /* FLASH_BANK2_END */ -#if !defined(FLASH_BANK2_END) - /* Prevent unused argument(s) compilation warning */ - UNUSED(Banks); -#endif /* FLASH_BANK2_END */ - /* Only bank1 will be erased*/ - SET_BIT(FLASH->CR, FLASH_CR_MER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -#if defined(FLASH_BANK2_END) - } -#endif /* FLASH_BANK2_END */ -} - -/** - * @brief Enable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write protected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFF; -#if defined(FLASH_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFF; -#endif /* FLASH_WRP1_WRP1 */ -#if defined(FLASH_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFF; -#endif /* FLASH_WRP2_WRP2 */ -#if defined(FLASH_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFF; -#endif /* FLASH_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be protected ******/ - WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES64TO95MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); -#endif /* OB_WRP_PAGES64TO95MASK */ -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES96TO127MASK */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - /* Enable write protection */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(FLASH_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 &= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP0_WRP0 */ - -#if defined(FLASH_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 &= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP1_WRP1 */ - -#if defined(FLASH_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 &= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP2_WRP2 */ - -#if defined(FLASH_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 &= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Disable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write unprotected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFF; -#if defined(FLASH_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFF; -#endif /* FLASH_WRP1_WRP1 */ -#if defined(FLASH_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFF; -#endif /* FLASH_WRP2_WRP2 */ -#if defined(FLASH_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFF; -#endif /* FLASH_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be unprotected ******/ - WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES64TO95MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); -#endif /* OB_WRP_PAGES64TO95MASK */ -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES96TO127MASK */ - - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(FLASH_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 |= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP0_WRP0 */ - -#if defined(FLASH_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 |= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP1_WRP1 */ - -#if defined(FLASH_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 |= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP2_WRP2 */ - -#if defined(FLASH_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 |= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* FLASH_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - return status; -} - -/** - * @brief Set the read protection level. - * @param ReadProtectLevel specifies the read protection level. - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - - WRITE_REG(OB->RDP, ReadProtectLevel); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte. - * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), - * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); - assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); - assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); -#if defined(FLASH_BANK2_END) - assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); -#endif /* FLASH_BANK2_END */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(FLASH_BANK2_END) - OB->USER = (UserConfig | 0xF0U); -#else - OB->USER = (UserConfig | 0x88U); -#endif /* FLASH_BANK2_END */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param Address specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data specifies the data to be programmed. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enables the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval The FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(READ_REG(FLASH->WRPR)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FLASH RDP level - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - uint32_t readstatus = OB_RDP_LEVEL_0; - uint32_t tmp_reg = 0U; - - /* Read RDP level bits */ - tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); - - if (tmp_reg == FLASH_OBR_RDPRT) - { - readstatus = OB_RDP_LEVEL_1; - } - else - { - readstatus = OB_RDP_LEVEL_0; - } - - return readstatus; -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), - * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Erase the specified FLASH memory page - * @param PageAddress FLASH page to erase - * The value of this parameter depend on device used within the same series - * - * @retval None - */ -void FLASH_PageErase(uint32_t PageAddress) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - -#if defined(FLASH_BANK2_END) - if(PageAddress > FLASH_BANK1_END) - { - /* Proceed to erase the page */ - SET_BIT(FLASH->CR2, FLASH_CR2_PER); - WRITE_REG(FLASH->AR2, PageAddress); - SET_BIT(FLASH->CR2, FLASH_CR2_STRT); - } - else - { -#endif /* FLASH_BANK2_END */ - /* Proceed to erase the page */ - SET_BIT(FLASH->CR, FLASH_CR_PER); - WRITE_REG(FLASH->AR, PageAddress); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -#if defined(FLASH_BANK2_END) - } -#endif /* FLASH_BANK2_END */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F1xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos +#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos +#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(uint32_t Banks); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) HAL_FLASHEx_Erase: return only when erase has been done + (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { +#if defined(FLASH_BANK2_END) + if (pEraseInit->Banks == FLASH_BANK_BOTH) + { + /* Mass Erase requested for Bank1 and Bank2 */ + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_BOTH); + + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + status = HAL_OK; + } + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else if (pEraseInit->Banks == FLASH_BANK_2) + { + /* Mass Erase requested for Bank2 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_2); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + +#if defined(FLASH_BANK2_END) + /* Page Erase requested on address located on bank2 */ + if(pEraseInit->PageAddress > FLASH_BANK1_END) + { + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase by page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + +#if defined(FLASH_BANK2_END) + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + +#endif + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg @ref FLASH_BANK_1 Bank1 to be erased + @if STM32F101xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + @if STM32F103xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + * + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ +#if !defined(FLASH_BANK2_END) + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); +#endif /* FLASH_BANK2_END */ + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); +#if defined(FLASH_BANK2_END) + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_BANK2_END) + OB->USER = (UserConfig | 0xF0U); +#else + OB->USER = (UserConfig | 0x88U); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t readstatus = OB_RDP_LEVEL_0; + uint32_t tmp_reg = 0U; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); + + if (tmp_reg == FLASH_OBR_RDPRT) + { + readstatus = OB_RDP_LEVEL_1; + } + else + { + readstatus = OB_RDP_LEVEL_0; + } + + return readstatus; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(PageAddress > FLASH_BANK1_END) + { + /* Proceed to erase the page */ + SET_BIT(FLASH->CR2, FLASH_CR2_PER); + WRITE_REG(FLASH->AR2, PageAddress); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index cd3563a..11e96b6 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -88,17 +99,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -295,26 +295,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) AFIO->EXTICR[position >> 2u] = temp; - /* Configure the interrupt mask */ - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - SET_BIT(EXTI->IMR, iocurrent); - } - else - { - CLEAR_BIT(EXTI->IMR, iocurrent); - } - - /* Configure the event mask */ - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - SET_BIT(EXTI->EMR, iocurrent); - } - else - { - CLEAR_BIT(EXTI->EMR, iocurrent); - } - /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { @@ -334,6 +314,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { CLEAR_BIT(EXTI->FTSR, iocurrent); } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(EXTI->EMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + } + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(EXTI->IMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + } } } @@ -375,16 +375,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= 0x0FuL << (4u * (position & 0x03u)); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { - tmp = 0x0FuL << (4u * (position & 0x03u)); - CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); - /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + + tmp = 0x0FuL << (4u * (position & 0x03u)); + CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); } /*------------------------- GPIO Mode Configuration --------------------*/ /* Check if the current bit belongs to first half or last half of the pin count number @@ -491,7 +491,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - /* get current Ouput Data Register value */ + /* get current Output Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ @@ -505,7 +505,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * the next reset. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) @@ -584,4 +584,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c index c2d810c..adaba4c 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c @@ -7,6 +7,17 @@ * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral extension features ##### @@ -23,17 +34,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -124,4 +124,3 @@ void HAL_GPIOEx_DisableEventout(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c index c757976..16476de 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c @@ -1,621 +1,618 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PWR_Private_Constants PWR Private Constants - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT 0x00010000U -#define PVD_MODE_EVT 0x00020000U -#define PVD_RISING_EDGE 0x00000001U -#define PVD_FALLING_EDGE 0x00000002U -/** - * @} - */ - - -/** @defgroup PWR_register_alias_address PWR Register alias address - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define PWR_CR_OFFSET 0x00U -#define PWR_CSR_OFFSET 0x04U -#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) -#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) -/** - * @} - */ - -/** @defgroup PWR_CR_register_alias PWR CR Register alias address - * @{ - */ -/* --- CR Register ---*/ -/* Alias word address of LPSDSR bit */ -#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos -#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) - -/* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER PWR_CR_DBP_Pos -#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) - -/* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos -#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) - -/** - * @} - */ - -/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address - * @{ - */ - -/* --- CSR Register ---*/ -/* Alias word address of EWUP1 bit */ -#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) -/** - * @} - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup PWR_Private_Functions PWR Private Functions - * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) - * @{ - */ -static void PWR_OverloadWfe(void); - -/* Private functions ---------------------------------------------------------*/ -__NOINLINE -static void PWR_OverloadWfe(void) -{ - __asm volatile( "wfe" ); - __asm volatile( "nop" ); -} - -/** - * @} - */ - - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers ). - * @note If the HSE divided by 128 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers). - * @note If the HSE divided by 128 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There is one WakeUp pin: - WakeUp Pin 1 on PA.00. - - [..] - - *** Low Power modes configuration *** - ===================================== - [..] - The device features 3 low-power modes: - (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like - NVIC, SysTick, etc. are kept running - (+) Stop mode: All clocks are stopped - (+) Standby mode: 1.8V domain powered off - - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) Exit: - (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. - (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) - (+++) Any EXTI Line (Internal or External) configured in Event mode - - *** Stop mode *** - ================= - [..] - The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral - clock gating. The voltage regulator can be configured either in normal or low-power mode. - In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC - oscillators are disabled. SRAM and register contents are preserved. - In Stop mode, all I/O pins keep the same state as in Run mode. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) - function with: - (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. - (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. - (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction - (+) Exit: - (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured - (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based on the - Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is - consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also - switched off. SRAM and register contents are lost except for registers in the Backup domain - and Standby circuitry - - (+) Entry: - (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in - NRSTpin, IWDG Reset - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, - without depending on an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - *** PWR Workarounds linked to Silicon Limitation *** - ==================================================== - [..] - Below the list of all silicon limitations known on STM32F1xx prouct. - - (#)Workarounds Implemented inside PWR HAL Driver - (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - /* Enable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - /* Disable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Enable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Disable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software - * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - /* No check on Regulator because parameter not used in SLEEP mode */ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Regulator); - - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by using an interrupt or a wakeup event, - * HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ - CLEAR_BIT(PWR->CR, PWR_CR_PDDS); - - /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ - MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - PWR_OverloadWfe(); /* WFE redefine locally */ - PWR_OverloadWfe(); /* WFE redefine locally */ - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - TAMPER pin if configured for tamper or calibration out. - * - WKUP pin (PA0) if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - SET_BIT(PWR->CR, PWR_CR_PDDS); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Enables CORTEX M3 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disables CORTEX M3 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of LPSDSR bit */ +#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) + +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ + +/* --- CSR Register ---*/ +/* Alias word address of EWUP1 bit */ +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PWR_Private_Functions PWR Private Functions + * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) + * @{ + */ +static void PWR_OverloadWfe(void); + +/* Private functions ---------------------------------------------------------*/ +__NOINLINE +static void PWR_OverloadWfe(void) +{ + __asm volatile( "wfe" ); + __asm volatile( "nop" ); +} + +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one WakeUp pin: + WakeUp Pin 1 on PA.00. + + [..] + + *** Low Power modes configuration *** + ===================================== + [..] + The device features 3 low-power modes: + (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like + NVIC, SysTick, etc. are kept running + (+) Stop mode: All clocks are stopped + (+) Standby mode: 1.8V domain powered off + + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. + (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) + (+++) Any EXTI Line (Internal or External) configured in Event mode + + *** Stop mode *** + ================= + [..] + The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral + clock gating. The voltage regulator can be configured either in normal or low-power mode. + In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC + oscillators are disabled. SRAM and register contents are preserved. + In Stop mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) + function with: + (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. + (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured + (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based on the + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is + consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also + switched off. SRAM and register contents are lost except for registers in the Backup domain + and Standby circuitry + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in + NRSTpin, IWDG Reset + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + *** PWR Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations known on STM32F1xx prouct. + + (#)Workarounds Implemented inside PWR HAL Driver + (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + /* No check on Regulator because parameter not used in SLEEP mode */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by using an interrupt or a wakeup event, + * HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ + CLEAR_BIT(PWR->CR, PWR_CR_PDDS); + + /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + PWR_OverloadWfe(); /* WFE redefine locally */ + PWR_OverloadWfe(); /* WFE redefine locally */ + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - TAMPER pin if configured for tamper or calibration out. + * - WKUP pin (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c index 95b5568..fe7515b 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c @@ -1,1403 +1,1400 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, - and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; - all peripherals mapped on these buses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB buses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC -* @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -static void RCC_Delay(uint32_t mdelay); - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring different output clocks: - (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M3 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, - HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x - - [..] System, AHB and APB buses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 128. - (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly. This clock is derived of the main PLL through PLL Multiplier. - (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK - (+@) IWDG clock which is always the LSI clock. - - (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. - For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. - @endverbatim - * @{ - */ - -/* - Additional consideration on the SYSCLK based on Latency settings: - +-----------------------------------------------+ - | Latency | SYSCLK clock frequency (MHz) | - |---------------|-------------------------------| - |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - |---------------|-------------------------------| - |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - |---------------|-------------------------------| - |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | - +-----------------------------------------------+ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL, PLL2 and PLL3 are OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS and MCO1 OFF - * - All interrupts disabled - * - All flags are cleared - * @note This function does not modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL_StatusTypeDef - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart; - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION); - - /* Wait till HSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set HSITRIM bits to the reset value */ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Wait till clock switch is ready */ - while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; - - /* Adapt Systick interrupt period */ - if (HAL_InitTick(uwTickPrio) != HAL_OK) - { - return HAL_ERROR; - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Second step is to clear PLLON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); - - /* Wait till PLL is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Ensure to reset PLLSRC and PLLMUL bits */ - CLEAR_REG(RCC->CFGR); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset HSEON & CSSON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); - - /* Wait till HSE is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - -#if defined(RCC_PLL2_SUPPORT) - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear PLL2ON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); - - /* Wait till PLL2 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } -#endif /* RCC_PLL2_SUPPORT */ - -#if defined(RCC_PLLI2S_SUPPORT) - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear PLL3ON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); - - /* Wait till PLL3 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_CFGR2_PREDIV1) - /* Reset CFGR2 register */ - CLEAR_REG(RCC->CFGR2); -#endif /* RCC_CFGR2_PREDIV1 */ - - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - return HAL_OK; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart; - uint32_t pll_config; - - /* Check Null pointer */ - if (RCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - - /* Check the HSE State */ - if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) - { - /* When HSI is used as system clock it will not disabled */ - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* To have a fully stabilized clock in the specified range, a software delay of 1ms - should be added.*/ - RCC_Delay(1); - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Require to disable power clock if necessary */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - -#if defined(RCC_CR_PLL2ON) - /*-------------------------------- PLL2 Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); - if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) - { - /* This bit can not be cleared if the PLL2 clock is used indirectly as system - clock (i.e. it is used as PLL clock entry that is used as system clock). */ - if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ - (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ - ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) - { - return HAL_ERROR; - } - else - { - if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); - assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLLI2S is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ - (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) - { - return HAL_ERROR; - } - - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); - - /* Configure the main PLL2 multiplication factors. */ - __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); - - /* Enable the main PLL2. */ - __HAL_RCC_PLL2_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Set PREDIV1 source to HSE */ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); - - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - -#endif /* RCC_CR_PLL2ON */ - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the HSE prediv factor --------------------------------*/ - /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ - if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) - { - /* Check the parameter */ - assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); -#if defined(RCC_CFGR2_PREDIV1SRC) - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); - - /* Set PREDIV1 source */ - SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); -#endif /* RCC_CFGR2_PREDIV1SRC */ - - /* Set PREDIV1 Value */ - __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); - } - - /* Configure the main PLL clock source and multiplication factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLMUL); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->CFGR; - if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) - { - return HAL_ERROR; - } - } - } - } - - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * start-up from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart; - - /* Check Null pointer */ - if (RCC_ClkInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) of the device. */ - -#if defined(FLASH_ACR_LATENCY) - /* Increasing the number of wait states because of higher CPU frequency */ - if (FLatency > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } -} - -#endif /* FLASH_ACR_LATENCY */ -/*-------------------------- HCLK Configuration --------------------------*/ -if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - /* Set the highest APBx dividers in order to ensure that we do not go through - a non-spec phase whatever we decrease or increase HCLK. */ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - } - - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - } - - /* Set the new HCLK clock divider */ - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - -#if defined(FLASH_ACR_LATENCY) - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } -} -#endif /* FLASH_ACR_LATENCY */ - -/*-------------------------- PCLK1 Configuration ---------------------------*/ -if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick(uwTickPrio); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - - @endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - @if STM32F105xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source - * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source - @endif - @if STM32F107xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source - * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source - @endif - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio = {0U}; - - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(RCC_MCOx); - UNUSED(RCC_MCODiv); - - /* Configure the MCO1 pin in alternate function mode */ - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_FREQ_HIGH; - gpio.Pull = GPIO_NOPULL; - gpio.Pin = MCO1_PIN; - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - - /* Configure the MCO clock source */ - __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; -} - -/** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) - * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. - * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ -#if defined(RCC_CFGR2_PREDIV1SRC) - const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; - const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; -#else - const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; -#if defined(RCC_CFGR2_PREDIV1) - const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; -#else - const uint8_t aPredivFactorTable[2] = {1, 2}; -#endif /*RCC_CFGR2_PREDIV1*/ - -#endif - uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - uint32_t sysclockfreq = 0U; -#if defined(RCC_CFGR2_PREDIV1SRC) - uint32_t prediv2 = 0U, pll2mul = 0U; -#endif /*RCC_CFGR2_PREDIV1SRC*/ - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ - { - pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; - if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) - { -#if defined(RCC_CFGR2_PREDIV1) - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; -#else - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; -#endif /*RCC_CFGR2_PREDIV1*/ -#if defined(RCC_CFGR2_PREDIV1SRC) - - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) - { - /* PLL2 selected as Prediv1 source */ - /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; - pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); - } - else - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); - } - - /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ - /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) - { - pllclk = pllclk / 2; - } -#else - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); -#endif /*RCC_CFGR2_PREDIV1SRC*/ - } - else - { - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); - } - sysclockfreq = pllclk; - break; - } - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - default: /* HSI used as system clock */ - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - -#if defined(RCC_CFGR2_PREDIV1SRC) - /* Get the Prediv1 source --------------------------------------------------*/ - RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); -#endif /* RCC_CFGR2_PREDIV1SRC */ - - /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); - - /* Get the HSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); - - /* Get the LSE configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - - /* Get the PLL configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); -#if defined(RCC_CR_PLL2ON) - /* Get the PLL2 configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) - { - RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; - } - else - { - RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; - } - RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); - RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); -#endif /* RCC_CR_PLL2ON */ -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * contains the current clock configuration. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - -#if defined(FLASH_ACR_LATENCY) - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -#else - /* For VALUE lines devices, only LATENCY_0 can be set*/ - *pFLatency = (uint32_t)FLASH_LATENCY_0; -#endif -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if (__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay: specifies the delay time length, in milliseconds. - * @retval None - */ -static void RCC_Delay(uint32_t mdelay) -{ - __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do - { - __NOP(); - } - while (Delay --); -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +static void RCC_Delay(uint32_t mdelay); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, + HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 128. + (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly. This clock is derived of the main PLL through PLL Multiplier. + (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK + (+@) IWDG clock which is always the LSI clock. + + (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. + For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + |---------------|-------------------------------| + |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLL2 and PLL3 are OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * - All flags are cleared + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM bits to the reset value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Second step is to clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Ensure to reset PLLSRC and PLLMUL bits */ + CLEAR_REG(RCC->CFGR); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset HSEON & CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + +#if defined(RCC_PLL2_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL3ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_CFGR2_PREDIV1) + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); +#endif /* RCC_CFGR2_PREDIV1 */ + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + +#if defined(RCC_CR_PLL2ON) + /*-------------------------------- PLL2 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); + if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) + { + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Set PREDIV1 source to HSE */ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + { + /* Check the parameter */ + assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); +#if defined(RCC_CFGR2_PREDIV1SRC) + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); + + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + @if STM32F105xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + @if STM32F107xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio = {0U}; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + UNUSED(RCC_MCODiv); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ +#if defined(RCC_CFGR2_PREDIV1SRC) + static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; +#if defined(RCC_CFGR2_PREDIV1) + static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + static const uint8_t aPredivFactorTable[2U] = {1, 2}; +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /*RCC_CFGR2_PREDIV1*/ +#if defined(RCC_CFGR2_PREDIV1SRC) + + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + sysclockfreq = pllclk; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + +#if defined(RCC_CFGR2_PREDIV1SRC) + /* Get the Prediv1 source --------------------------------------------------*/ + RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); +#if defined(RCC_CR_PLL2ON) + /* Get the PLL2 configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; + } + else + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; + } + RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); + RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); +#endif /* RCC_CR_PLL2ON */ +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + +#if defined(FLASH_ACR_LATENCY) + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +#else + /* For VALUE lines devices, only LATENCY_0 can be set*/ + *pFLatency = (uint32_t)FLASH_LATENCY_0; +#endif +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c index e6e1b4d..7e789d9 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -1,863 +1,860 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/** @defgroup RCCEx RCCEx - * @brief RCC Extension HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the - * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks(RTC clock). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) are set to their reset values. - * - * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on - * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to - * manually disable it. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U, temp_reg = 0U; -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t pllactive = 0U; -#endif /* STM32F105xC || STM32F107xC */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ - if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) - { - FlagStatus pwrclkchanged = RESET; - - /* check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = temp_reg; - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - - /* Require to disable power clock if necessary */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*------------------------------ ADC clock Configuration ------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - { - /* Check the parameters */ - assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); - - /* Configure the ADC clock source */ - __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - } - -#if defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ I2S2 Configuration ------------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); - - /* Configure the I2S2 clock source */ - __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); - } - - /*------------------------------ I2S3 Configuration ------------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); - - /* Configure the I2S3 clock source */ - __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); - } - - /*------------------------------ PLL I2S Configuration ----------------------*/ - /* Check that PLLI2S need to be enabled */ - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) - { - /* Update flag to indicate that PLL I2S should be active */ - pllactive = 1; - } - - /* Check if PLL I2S need to be enabled */ - if (pllactive == 1) - { - /* Enable PLL I2S only if not active */ - if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); - assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLL2 is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ - (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) - { - return HAL_ERROR; - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); - - /* Configure the main PLLI2S multiplication factors. */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); - - /* Enable the main PLLI2S. */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ - if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) - { - return HAL_ERROR; - } - } - } -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ USB clock Configuration ------------------*/ - if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - { - /* Check the parameters */ - assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); - - /* Configure the USB clock source */ - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - } -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - - return HAL_OK; -} - -/** - * @brief Get the PeriphClkInit according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t srcclk = 0U; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; - - /* Get the RTC configuration -----------------------------------------------*/ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - /* Source clock is LSE or LSI*/ - PeriphClkInit->RTCClockSelection = srcclk; - - /* Get the ADC clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; - PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); - -#if defined(STM32F105xC) || defined(STM32F107xC) - /* Get the I2S2 clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; - PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); - - /* Get the I2S3 clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; - PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); - -#endif /* STM32F105xC || STM32F107xC */ - -#if defined(STM32F103xE) || defined(STM32F103xG) - /* Get the I2S2 clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; - PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; - - /* Get the I2S3 clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; - PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; - -#endif /* STM32F103xE || STM32F103xG */ - -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - /* Get the USB clock configuration -----------------------------------------*/ - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; - PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -} - -/** - * @brief Returns the peripheral clock frequency - * @note Returns 0 if peripheral clock is unknown - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock - @if STM32F103xE - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - @endif - @if STM32F103xG - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - @endif - @if STM32F105xC - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F107xC - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F102xx - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F103xx - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - * @retval Frequency in Hz (0: means that no available frequency for the peripheral) - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ -#if defined(STM32F105xC) || defined(STM32F107xC) - const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; - const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; - - uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; - uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; -#endif /* STM32F105xC || STM32F107xC */ -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ - defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) - const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; - const uint8_t aPredivFactorTable[2] = {1, 2}; - - uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ - uint32_t temp_reg = 0U, frequency = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - switch (PeriphClk) - { -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - case RCC_PERIPHCLK_USB: - { - /* Get RCC configuration ------------------------------------------------------*/ - temp_reg = RCC->CFGR; - - /* Check if PLL is enabled */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) - { - pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; - if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) - { -#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ - || defined(STM32F100xE) - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; -#else - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ - -#if defined(STM32F105xC) || defined(STM32F107xC) - if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) - { - /* PLL2 selected as Prediv1 source */ - /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; - pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); - } - else - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); - } - - /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ - /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) - { - pllclk = pllclk / 2; - } -#else - if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ - pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); - } -#endif /* STM32F105xC || STM32F107xC */ - } - else - { - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); - } - - /* Calcul of the USB frequency*/ -#if defined(STM32F105xC) || defined(STM32F107xC) - /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ - if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) - { - /* Prescaler of 2 selected for USB */ - frequency = pllclk; - } - else - { - /* Prescaler of 3 selected for USB */ - frequency = (2 * pllclk) / 3; - } -#else - /* USBCLK = PLLCLK / USB prescaler */ - if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) - { - /* No prescaler selected for USB */ - frequency = pllclk; - } - else - { - /* Prescaler of 1.5 selected for USB */ - frequency = (pllclk * 2) / 3; - } -#endif - } - break; - } -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) - case RCC_PERIPHCLK_I2S2: - { -#if defined(STM32F103xE) || defined(STM32F103xG) - /* SYSCLK used as source clock for I2S2 */ - frequency = HAL_RCC_GetSysClockFreq(); -#else - if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) - { - /* SYSCLK used as source clock for I2S2 */ - frequency = HAL_RCC_GetSysClockFreq(); - } - else - { - /* Check if PLLI2S is enabled */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) - { - /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - } - } -#endif /* STM32F103xE || STM32F103xG */ - break; - } - case RCC_PERIPHCLK_I2S3: - { -#if defined(STM32F103xE) || defined(STM32F103xG) - /* SYSCLK used as source clock for I2S3 */ - frequency = HAL_RCC_GetSysClockFreq(); -#else - if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) - { - /* SYSCLK used as source clock for I2S3 */ - frequency = HAL_RCC_GetSysClockFreq(); - } - else - { - /* Check if PLLI2S is enabled */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) - { - /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; - frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); - } - } -#endif /* STM32F103xE || STM32F103xG */ - break; - } -#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - case RCC_PERIPHCLK_RTC: - { - /* Get RCC BDCR configuration ------------------------------------------------------*/ - temp_reg = RCC->BDCR; - - /* Check if LSE is ready if RTC clock selection is LSE */ - if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready if RTC clock selection is LSI */ - else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 128U; - } - /* Clock not enabled for RTC*/ - else - { - /* nothing to do: frequency already initialized to 0U */ - } - break; - } - case RCC_PERIPHCLK_ADC: - { - frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); - break; - } - default: - { - break; - } - } - return (frequency); -} - -/** - * @} - */ - -#if defined(STM32F105xC) || defined(STM32F107xC) -/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function - * @brief PLLI2S Management functions - * -@verbatim - =============================================================================== - ##### Extended PLLI2S Management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PLLI2S - activation or deactivation -@endverbatim - * @{ - */ - -/** - * @brief Enable PLLI2S - * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that - * contains the configuration information for the PLLI2S - * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) -{ - uint32_t tickstart = 0U; - - /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ - if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); - assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLL2 is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ - (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) - { - return HAL_ERROR; - } - - /* Disable the main PLLI2S. */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); - - - /* Configure the main PLLI2S multiplication factors. */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); - - /* Enable the main PLLI2S. */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disable PLLI2S - * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) -{ - uint32_t tickstart = 0U; - - /* Disable PLL I2S as not requested by I2S2 or I2S3*/ - if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) - { - /* Disable the main PLLI2S. */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function - * @brief PLL2 Management functions - * -@verbatim - =============================================================================== - ##### Extended PLL2 Management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PLL2 - activation or deactivation -@endverbatim - * @{ - */ - -/** - * @brief Enable PLL2 - * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that - * contains the configuration information for the PLL2 - * @note The PLL2 configuration not modified if used indirectly as system clock. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) -{ - uint32_t tickstart = 0U; - - /* This bit can not be cleared if the PLL2 clock is used indirectly as system - clock (i.e. it is used as PLL clock entry that is used as system clock). */ - if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ - (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ - ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) - { - return HAL_ERROR; - } - else - { - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); - assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); - - /* Prediv2 can be written only when the PLLI2S is disabled. */ - /* Return an error only if new value is different from the programmed value */ - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ - (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) - { - return HAL_ERROR; - } - - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the HSE prediv2 factor --------------------------------*/ - __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); - - /* Configure the main PLL2 multiplication factors. */ - __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); - - /* Enable the main PLL2. */ - __HAL_RCC_PLL2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief Disable PLL2 - * @note PLL2 is not disabled if used indirectly as system clock. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) -{ - uint32_t tickstart = 0U; - - /* This bit can not be cleared if the PLL2 clock is used indirectly as system - clock (i.e. it is used as PLL clock entry that is used as system clock). */ - if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ - (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ - ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) - { - return HAL_ERROR; - } - else - { - /* Disable the main PLL2. */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @} - */ -#endif /* STM32F105xC || STM32F107xC */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(RTC clock). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on + * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to + * manually disable it. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U, temp_reg = 0U; +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t pllactive = 0U; +#endif /* STM32F105xC || STM32F107xC */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + { + FlagStatus pwrclkchanged = RESET; + + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------ ADC clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + +#if defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ I2S2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + } + + /*------------------------------ I2S3 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); + + /* Configure the I2S3 clock source */ + __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); + } + + /*------------------------------ PLL I2S Configuration ----------------------*/ + /* Check that PLLI2S need to be enabled */ + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Update flag to indicate that PLL I2S should be active */ + pllactive = 1; + } + + /* Check if PLL I2S need to be enabled */ + if (pllactive == 1) + { + /* Enable PLL I2S only if not active */ + if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ + if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) + { + return HAL_ERROR; + } + } + } +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ USB clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + + return HAL_OK; +} + +/** + * @brief Get the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t srcclk = 0U; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; + + /* Get the RTC configuration -----------------------------------------------*/ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + /* Source clock is LSE or LSI*/ + PeriphClkInit->RTCClockSelection = srcclk; + + /* Get the ADC clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F103xE) || defined(STM32F103xG) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; + +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /* Get the USB clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + @if STM32F103xE + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + @endif + @if STM32F103xG + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + @endif + @if STM32F105xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F107xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F102xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F103xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ +#if defined(STM32F105xC) || defined(STM32F107xC) + static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ + defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + static const uint8_t aPredivFactorTable[2U] = {1, 2}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_USB: + { + /* Get RCC configuration ------------------------------------------------------*/ + temp_reg = RCC->CFGR; + + /* Check if PLL is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) + { + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } +#endif /* STM32F105xC || STM32F107xC */ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + + /* Calcul of the USB frequency*/ +#if defined(STM32F105xC) || defined(STM32F107xC) + /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) + { + /* Prescaler of 2 selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 3 selected for USB */ + frequency = (2 * pllclk) / 3; + } +#else + /* USBCLK = PLLCLK / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) + { + /* No prescaler selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 1.5 selected for USB */ + frequency = (pllclk * 2) / 3; + } +#endif + } + break; + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_I2S2: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } + case RCC_PERIPHCLK_I2S3: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + case RCC_PERIPHCLK_RTC: + { + /* Get RCC BDCR configuration ------------------------------------------------------*/ + temp_reg = RCC->BDCR; + + /* Check if LSE is ready if RTC clock selection is LSE */ + if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 128U; + } + /* Clock not enabled for RTC*/ + else + { + /* nothing to do: frequency already initialized to 0U */ + } + break; + } + case RCC_PERIPHCLK_ADC: + { + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + break; + } + default: + { + break; + } + } + return (frequency); +} + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function + * @brief PLLI2S Management functions + * +@verbatim + =============================================================================== + ##### Extended PLLI2S Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLLI2S + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart = 0U; + + /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); + + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S + * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart = 0U; + + /* Disable PLL I2S as not requested by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function + * @brief PLL2 Management functions + * +@verbatim + =============================================================================== + ##### Extended PLL2 Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLL2 + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLL2 + * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration information for the PLL2 + * @note The PLL2 configuration not modified if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLL2 + * @note PLL2 is not disabled if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c index 6d04d52..f808ce2 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c @@ -1,1949 +1,1948 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rtc.c - * @author MCD Application Team - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: - * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base) - using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. - (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper Level using the - HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt - mode using HAL_RTCEx_SetTamper_IT() function. - (+) The TAMPER1 alternate function can be mapped to PC13 - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - ##### WARNING: Drivers Restrictions ##### - ================================================================== - [..] RTC version used on STM32F1 families is version V1. All the features supported by V2 - (other families) will be not supported on F1. - [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely - managed by SW. - [..] Then, there are some restrictions compared to other families: - (+) Only format 24 hours supported in HAL (format 12 hours not supported) - (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost. - User should implement a way to save date before entering in low power mode (an - example is provided with firmware package based on backup registers) - (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called. - (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need - to program a new alarm) - - ##### Backup Domain Operating Condition ##### - ============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC operating even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following pins are available: - (+) PC13 can be used as a Tamper pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following pins are available: - (+) PC13 can be used as the Tamper pin - - ##### Backup Domain Reset ##### - ================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - (#) Tamper detection event resets all data backup registers. - - ##### Backup Domain Access ##### - ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for - PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE) - (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE() - - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A), - and RTC tamper event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm. - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. - - [..] - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, - all callbacks are set to the corresponding weak functions : - example @ref AlarmAEventCallback(). - Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null - (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - [..] - Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. - [..] - When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RTC_Private_Constants RTC Private Constants - * @{ - */ -#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF -#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RTC_Private_Macros RTC Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RTC_Private_Functions RTC Private Functions - * @{ - */ -static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc); -static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter); -static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc); -static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter); -static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); -static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); -static uint8_t RTC_IsLeapYear(uint16_t nYear); -static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed); -static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay); - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Asynchronous), disable RTC registers Write protection, - enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by setting the CNF bit in the RTC_CRL register. - (#) To read the calendar after wakeup from low power modes (Standby or Stop) - the software must first wait for the RSF bit (Register Synchronized Flag) - in the RTC_CRL register to be set by hardware. - The HAL_RTC_WaitForSynchro() function implements the above software - sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RTC peripheral - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - uint32_t prescaler = 0U; - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - - if (hrtc->MspInitCallback == NULL) - { - hrtc->MspInitCallback = HAL_RTC_MspInit; - } - /* Init the low level hardware */ - hrtc->MspInitCallback(hrtc); - - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - } -#else - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Waiting for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear Flags Bits */ - CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); - - if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) - { - /* Disable the selected Tamper pin */ - CLEAR_BIT(BKP->CR, BKP_CR_TPE); - } - - /* Set the signal which will be routed to RTC Tamper pin*/ - MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); - - if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) - { - /* RTC Prescaler provided directly by end-user*/ - prescaler = hrtc->Init.AsynchPrediv; - } - else - { - /* RTC Prescaler will be automatically calculated to get 1 second timebase */ - /* Get the RTCCLK frequency */ - prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); - - /* Check that RTC clock is enabled*/ - if (prescaler == 0U) - { - /* Should not happen. Frequency is not available*/ - hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_ERROR; - } - else - { - /* RTC period = RTCCLK/(RTC_PR + 1) */ - prescaler = prescaler - 1U; - } - } - - /* Configure the RTC_PRLH / RTC_PRLL */ - MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); - MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); - - /* Wait for synchro */ - if (RTC_ExitInitMode(hrtc) != HAL_OK) - { - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - /* Initialize date to 1st of January 2000 */ - hrtc->DateToUpdate.Year = 0x00U; - hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; - hrtc->DateToUpdate.Date = 0x01U; - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitializes the RTC peripheral - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function does not reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - CLEAR_REG(hrtc->Instance->CNTL); - CLEAR_REG(hrtc->Instance->CNTH); - WRITE_REG(hrtc->Instance->PRLL, 0x00008000U); - CLEAR_REG(hrtc->Instance->PRLH); - - /* Reset All CRH/CRL bits */ - CLEAR_REG(hrtc->Instance->CRH); - CLEAR_REG(hrtc->Instance->CRL); - - if (RTC_ExitInitMode(hrtc) != HAL_OK) - { - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Wait for synchro*/ - HAL_RTC_WaitForSynchro(hrtc); - - /* Clear RSF flag */ - CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); - -#else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User RTC Callback - * To be used instead of the weak predefined callback - * @param hrtc RTC handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = pCallback; - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = pCallback; - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Unregister an RTC Callback - * RTC callabck is redirected to the weak predefined callback - * @param hrtc RTC handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Initializes the RTC MSP. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the RTC MSP. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Sets RTC current time. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t counter_time = 0U, counter_alarm = 0U; - - /* Check input parameters */ - if ((hrtc == NULL) || (sTime == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_HOUR24(sTime->Hours)); - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ - ((uint32_t)sTime->Minutes * 60U) + \ - ((uint32_t)sTime->Seconds)); - } - else - { - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - - counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ - ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \ - ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds)))); - } - - /* Write time counter in RTC registers */ - if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Clear Second and overflow flags */ - CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW)); - - /* Read current Alarm counter in RTC registers */ - counter_alarm = RTC_ReadAlarmCounter(hrtc); - - /* Set again alarm to match with new time if enabled */ - if (counter_alarm != RTC_ALARM_RESETVALUE) - { - if (counter_alarm < counter_time) - { - /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24U * 3600U); - - /* Write new Alarm counter in RTC registers */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Gets RTC current time. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U; - - /* Check input parameters */ - if ((hrtc == NULL) || (sTime == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Check if counter overflow occurred */ - if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW)) - { - return HAL_ERROR; - } - - /* Read the time counter*/ - counter_time = RTC_ReadTimeCounter(hrtc); - - /* Fill the structure fields with the read parameters */ - hours = counter_time / 3600U; - sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U); - sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U); - - if (hours >= 24U) - { - /* Get number of days elapsed from last calculation */ - days_elapsed = (hours / 24U); - - /* Set Hours in RTC_TimeTypeDef structure*/ - sTime->Hours = (hours % 24U); - - /* Read Alarm counter in RTC registers */ - counter_alarm = RTC_ReadAlarmCounter(hrtc); - - /* Calculate remaining time to reach alarm (only if set and not yet expired)*/ - if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time)) - { - counter_alarm -= counter_time; - } - else - { - /* In case of counter_alarm < counter_time */ - /* Alarm expiration already occurred but alarm not deactivated */ - counter_alarm = RTC_ALARM_RESETVALUE; - } - - /* Set updated time in decreasing counter by number of days elapsed */ - counter_time -= (days_elapsed * 24U * 3600U); - - /* Write time counter in RTC registers */ - if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) - { - return HAL_ERROR; - } - - /* Set updated alarm to be set */ - if (counter_alarm != RTC_ALARM_RESETVALUE) - { - counter_alarm += counter_time; - - /* Write time counter in RTC registers */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - return HAL_ERROR; - } - } - else - { - /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Update date */ - RTC_DateUpdate(hrtc, days_elapsed); - } - else - { - sTime->Hours = hours; - } - - /* Check the input parameters format */ - if (Format != RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to BCD format */ - sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds); - } - - return HAL_OK; -} - - -/** - * @brief Sets RTC current date. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U; - - /* Check input parameters */ - if ((hrtc == NULL) || (sDate == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - /* Change the current date */ - hrtc->DateToUpdate.Year = sDate->Year; - hrtc->DateToUpdate.Month = sDate->Month; - hrtc->DateToUpdate.Date = sDate->Date; - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); - assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - - /* Change the current date */ - hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year); - hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month); - hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date); - } - - /* WeekDay set by user can be ignored because automatically calculated */ - hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date); - sDate->WeekDay = hrtc->DateToUpdate.WeekDay; - - /* Reset time to be aligned on the same day */ - /* Read the time counter*/ - counter_time = RTC_ReadTimeCounter(hrtc); - - /* Fill the structure fields with the read parameters */ - hours = counter_time / 3600U; - if (hours > 24U) - { - /* Set updated time in decreasing counter by number of days elapsed */ - counter_time -= ((hours / 24U) * 24U * 3600U); - /* Write time counter in RTC registers */ - if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Read current Alarm counter in RTC registers */ - counter_alarm = RTC_ReadAlarmCounter(hrtc); - - /* Set again alarm to match with new time if enabled */ - if (counter_alarm != RTC_ALARM_RESETVALUE) - { - if (counter_alarm < counter_time) - { - /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24U * 3600U); - - /* Write new Alarm counter in RTC registers */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - - - } - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets RTC current date. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - RTC_TimeTypeDef stime = {0U}; - - /* Check input parameters */ - if ((hrtc == NULL) || (sDate == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ - if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) - { - return HAL_ERROR; - } - - /* Fill the structure fields with the read parameters */ - sDate->WeekDay = hrtc->DateToUpdate.WeekDay; - sDate->Year = hrtc->DateToUpdate.Year; - sDate->Month = hrtc->DateToUpdate.Month; - sDate->Date = hrtc->DateToUpdate.Date; - - /* Check the input parameters format */ - if (Format != RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to BCD format */ - sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year); - sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month); - sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified RTC Alarm. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t counter_alarm = 0U, counter_time; - RTC_TimeTypeDef stime = {0U}; - - /* Check input parameters */ - if ((hrtc == NULL) || (sAlarm == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ - if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) - { - return HAL_ERROR; - } - - /* Convert time in seconds */ - counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ - ((uint32_t)stime.Minutes * 60U) + \ - ((uint32_t)stime.Seconds)); - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ - ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ - ((uint32_t)sAlarm->AlarmTime.Seconds)); - } - else - { - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ - ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ - ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - } - - /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ - if (counter_alarm < counter_time) - { - /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24U * 3600U); - } - - /* Write Alarm counter in RTC registers */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t counter_alarm = 0U, counter_time; - RTC_TimeTypeDef stime = {0U}; - - /* Check input parameters */ - if ((hrtc == NULL) || (sAlarm == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ - if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) - { - return HAL_ERROR; - } - - /* Convert time in seconds */ - counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ - ((uint32_t)stime.Minutes * 60U) + \ - ((uint32_t)stime.Seconds)); - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ - ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ - ((uint32_t)sAlarm->AlarmTime.Seconds)); - } - else - { - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ - ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ - ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - } - - /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ - if (counter_alarm < counter_time) - { - /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24U * 3600U); - } - - /* Write alarm counter in RTC registers */ - if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Gets the RTC Alarm value and masks. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: Alarm - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t counter_alarm = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(Alarm); - - /* Check input parameters */ - if ((hrtc == NULL) || (sAlarm == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - /* Read Alarm counter in RTC registers */ - counter_alarm = RTC_ReadAlarmCounter(hrtc); - - /* Fill the structure with the read parameters */ - /* Set hours in a day range (between 0 to 24)*/ - sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U); - sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U); - sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U); - - if (Format != RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds); - } - - return HAL_OK; -} - -/** - * @brief Deactive the specified RTC Alarm - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Alarm); - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Set to default values ALRH & ALRL registers */ - WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER); - WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER); - - /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */ - __HAL_RTC_ALARM_EXTI_DISABLE_IT(); - - /* Wait for synchro */ - if (RTC_ExitInitMode(hrtc) != HAL_OK) - { - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles Alarm interrupt request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA)) - { - /* Get the status of the Interrupt */ - if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) - { - /* AlarmA callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->AlarmAEventCallback(hrtc); -#else - HAL_RTC_AlarmAEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - } - } - - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles AlarmA Polling request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) -{ - return hrtc->State; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Clear RSF flag */ - CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); - - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - - -/** - * @} - */ - -/** @addtogroup RTC_Private_Functions - * @{ - */ - - -/** - * @brief Read the time counter available in RTC_CNT registers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Time counter - */ -static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc) -{ - uint16_t high1 = 0U, high2 = 0U, low = 0U; - uint32_t timecounter = 0U; - - high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); - low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); - high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); - - if (high1 != high2) - { - /* In this case the counter roll over during reading of CNTL and CNTH registers, - read again CNTL register then return the counter value */ - timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); - } - else - { - /* No counter roll over during reading of CNTL and CNTH registers, counter - value is equal to first value of CNTL and CNTH */ - timecounter = (((uint32_t) high1 << 16U) | low); - } - - return timecounter; -} - -/** - * @brief Write the time counter in RTC_CNT registers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param TimeCounter: Counter to write in RTC_CNT registers - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - status = HAL_ERROR; - } - else - { - /* Set RTC COUNTER MSB word */ - WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); - - /* Wait for synchro */ - if (RTC_ExitInitMode(hrtc) != HAL_OK) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Read the time counter available in RTC_ALR registers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Time counter - */ -static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc) -{ - uint16_t high1 = 0U, low = 0U; - - high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT); - low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT); - - return (((uint32_t) high1 << 16U) | low); -} - -/** - * @brief Write the time counter in RTC_ALR registers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param AlarmCounter: Counter to write in RTC_ALR registers - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - status = HAL_ERROR; - } - else - { - /* Set RTC COUNTER MSB word */ - WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); - - /* Wait for synchro */ - if (RTC_ExitInitMode(hrtc) != HAL_OK) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Enters the RTC Initialization mode. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - - return HAL_OK; -} - -/** - * @brief Exit the RTC Initialization mode. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0U; - - while (Value >= 10U) - { - bcdhigh++; - Value -= 10U; - } - - return ((uint8_t)(bcdhigh << 4U) | Value); -} - -/** - * @brief Converts from 2 digit BCD to Binary. - * @param Value: BCD value to be converted - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp = 0U; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @brief Updates date when time is 23:59:59. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param DayElapsed: Number of days elapsed from last date update - * @retval None - */ -static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed) -{ - uint32_t year = 0U, month = 0U, day = 0U; - uint32_t loop = 0U; - - /* Get the current year*/ - year = hrtc->DateToUpdate.Year; - - /* Get the current month and day */ - month = hrtc->DateToUpdate.Month; - day = hrtc->DateToUpdate.Date; - - for (loop = 0U; loop < DayElapsed; loop++) - { - if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \ - (month == 8U) || (month == 10U) || (month == 12U)) - { - if (day < 31U) - { - day++; - } - /* Date structure member: day = 31 */ - else - { - if (month != 12U) - { - month++; - day = 1U; - } - /* Date structure member: day = 31 & month =12 */ - else - { - month = 1U; - day = 1U; - year++; - } - } - } - else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U)) - { - if (day < 30U) - { - day++; - } - /* Date structure member: day = 30 */ - else - { - month++; - day = 1U; - } - } - else if (month == 2U) - { - if (day < 28U) - { - day++; - } - else if (day == 28U) - { - /* Leap year */ - if (RTC_IsLeapYear(year)) - { - day++; - } - else - { - month++; - day = 1U; - } - } - else if (day == 29U) - { - month++; - day = 1U; - } - } - } - - /* Update year */ - hrtc->DateToUpdate.Year = year; - - /* Update day and month */ - hrtc->DateToUpdate.Month = month; - hrtc->DateToUpdate.Date = day; - - /* Update day of the week */ - hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day); -} - -/** - * @brief Check whether the passed year is Leap or not. - * @param nYear year to check - * @retval 1: leap year - * 0: not leap year - */ -static uint8_t RTC_IsLeapYear(uint16_t nYear) -{ - if ((nYear % 4U) != 0U) - { - return 0U; - } - - if ((nYear % 100U) != 0U) - { - return 1U; - } - - if ((nYear % 400U) == 0U) - { - return 1U; - } - else - { - return 0U; - } -} - -/** - * @brief Determines the week number, the day number and the week day number. - * @param nYear year to check - * @param nMonth Month to check - * @param nDay Day to check - * @note Day is calculated with hypothesis that year > 2000 - * @retval Value which can take one of the following parameters: - * @arg RTC_WEEKDAY_MONDAY - * @arg RTC_WEEKDAY_TUESDAY - * @arg RTC_WEEKDAY_WEDNESDAY - * @arg RTC_WEEKDAY_THURSDAY - * @arg RTC_WEEKDAY_FRIDAY - * @arg RTC_WEEKDAY_SATURDAY - * @arg RTC_WEEKDAY_SUNDAY - */ -static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay) -{ - uint32_t year = 0U, weekday = 0U; - - year = 2000U + nYear; - - if (nMonth < 3U) - { - /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ - weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U; - } - else - { - /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ - weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U; - } - - return (uint8_t)weekday; -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) peripheral: + * + Initialization and de-initialization functions + * + RTC Time and Date functions + * + RTC Alarm functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base) + using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper Level using the + HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt + mode using HAL_RTCEx_SetTamper_IT() function. + (+) The TAMPER1 alternate function can be mapped to PC13 + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + + ##### WARNING: Drivers Restrictions ##### + ================================================================== + [..] RTC version used on STM32F1 families is version V1. All the features supported by V2 + (other families) will be not supported on F1. + [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely + managed by SW. + [..] Then, there are some restrictions compared to other families: + (+) Only format 24 hours supported in HAL (format 12 hours not supported) + (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost. + User should implement a way to save date before entering in low power mode (an + example is provided with firmware package based on backup registers) + (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called. + (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need + to program a new alarm) + + ##### Backup Domain Operating Condition ##### + ============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC operating even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) The backup SRAM when the low power backup regulator is enabled + (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following pins are available: + (+) PC13 can be used as a Tamper pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following pins are available: + (+) PC13 can be used as the Tamper pin + + ##### Backup Domain Reset ##### + ================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE) + (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE() + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A), + and RTC tamper event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. + + [..] + Function HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + [..] + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + example AlarmAEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. + [..] + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF +#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter); +static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter); +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); +static uint8_t RTC_IsLeapYear(uint16_t nYear); +static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed); +static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay); + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Asynchronous), disable RTC registers Write protection, + enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by setting the CNF bit in the RTC_CRL register. + (#) To read the calendar after wakeup from low power modes (Standby or Stop) + the software must first wait for the RSF bit (Register Synchronized Flag) + in the RTC_CRL register to be set by hardware. + The HAL_RTC_WaitForSynchro() function implements the above software + sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + uint32_t prescaler = 0U; + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Waiting for synchro */ + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Clear Flags Bits */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); + + if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) + { + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + } + + /* Set the signal which will be routed to RTC Tamper pin*/ + MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); + + if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) + { + /* RTC Prescaler provided directly by end-user*/ + prescaler = hrtc->Init.AsynchPrediv; + } + else + { + /* RTC Prescaler will be automatically calculated to get 1 second timebase */ + /* Get the RTCCLK frequency */ + prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); + + /* Check that RTC clock is enabled*/ + if (prescaler == 0U) + { + /* Should not happen. Frequency is not available*/ + hrtc->State = HAL_RTC_STATE_ERROR; + return HAL_ERROR; + } + else + { + /* RTC period = RTCCLK/(RTC_PR + 1) */ + prescaler = prescaler - 1U; + } + } + + /* Configure the RTC_PRLH / RTC_PRLL */ + WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); + WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + /* Initialize date to 1st of January 2000 */ + hrtc->DateToUpdate.Year = 0x00U; + hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; + hrtc->DateToUpdate.Date = 0x01U; + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; + } +} + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This function does not reset the RTC Backup Data registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + CLEAR_REG(hrtc->Instance->CNTL); + CLEAR_REG(hrtc->Instance->CNTH); + WRITE_REG(hrtc->Instance->PRLL, 0x00008000U); + CLEAR_REG(hrtc->Instance->PRLH); + + /* Reset All CRH/CRL bits */ + CLEAR_REG(hrtc->Instance->CRH); + CLEAR_REG(hrtc->Instance->CRL); + + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Wait for synchro*/ + HAL_RTC_WaitForSynchro(hrtc); + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Sets RTC current time. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sTime->Hours)); + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + ((uint32_t)sTime->Minutes * 60U) + \ + ((uint32_t)sTime->Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds)))); + } + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear Second and overflow flags */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW)); + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current time. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Check if counter overflow occurred */ + if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW)) + { + return HAL_ERROR; + } + + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U); + sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U); + + if (hours >= 24U) + { + /* Get number of days elapsed from last calculation */ + days_elapsed = (hours / 24U); + + /* Set Hours in RTC_TimeTypeDef structure*/ + sTime->Hours = (hours % 24U); + + /* Read Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Calculate remaining time to reach alarm (only if set and not yet expired)*/ + if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time)) + { + counter_alarm -= counter_time; + } + else + { + /* In case of counter_alarm < counter_time */ + /* Alarm expiration already occurred but alarm not deactivated */ + counter_alarm = RTC_ALARM_RESETVALUE; + } + + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= (days_elapsed * 24U * 3600U); + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set updated alarm to be set */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + counter_alarm += counter_time; + + /* Write time counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Update date */ + RTC_DateUpdate(hrtc, days_elapsed); + } + else + { + sTime->Hours = hours; + } + + /* Check the input parameters format */ + if (Format != RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to BCD format */ + sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds); + } + + return HAL_OK; +} + + +/** + * @brief Sets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sDate == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + /* Change the current date */ + hrtc->DateToUpdate.Year = sDate->Year; + hrtc->DateToUpdate.Month = sDate->Month; + hrtc->DateToUpdate.Date = sDate->Date; + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + /* Change the current date */ + hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year); + hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month); + hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date); + } + + /* WeekDay set by user can be ignored because automatically calculated */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date); + sDate->WeekDay = hrtc->DateToUpdate.WeekDay; + + /* Reset time to be aligned on the same day */ + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + if (hours > 24U) + { + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= ((hours / 24U) * 24U * 3600U); + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + + + } + + hrtc->State = HAL_RTC_STATE_READY ; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to Date structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sDate == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Fill the structure fields with the read parameters */ + sDate->WeekDay = hrtc->DateToUpdate.WeekDay; + sDate->Year = hrtc->DateToUpdate.Year; + sDate->Month = hrtc->DateToUpdate.Month; + sDate->Date = hrtc->DateToUpdate.Date; + + /* Check the input parameters format */ + if (Format != RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to BCD format */ + sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year); + sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month); + sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 Alarm functions + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified RTC Alarm. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Convert time in seconds */ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ + ((uint32_t)stime.Seconds)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ + ((uint32_t)sAlarm->AlarmTime.Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } + + /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + } + + /* Write Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Sets the specified RTC Alarm with Interrupt + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Convert time in seconds */ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ + ((uint32_t)stime.Seconds)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ + ((uint32_t)sAlarm->AlarmTime.Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } + + /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + } + + /* Write alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets the RTC Alarm value and masks. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Date structure + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: Alarm + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + /* Read Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Fill the structure with the read parameters */ + /* Set hours in a day range (between 0 to 24)*/ + sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U); + sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U); + sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U); + + if (Format != RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds); + } + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Set to default values ALRH & ALRL registers */ + WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER); + WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER); + + /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */ + __HAL_RTC_ALARM_EXTI_DISABLE_IT(); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles Alarm interrupt request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA)) + { + /* Get the status of the Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + { + /* AlarmA callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmA Polling request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ + + +/** + * @brief Read the time counter available in RTC_CNT registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc) +{ + uint16_t high1 = 0U, high2 = 0U, low = 0U; + uint32_t timecounter = 0U; + + high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); + high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + + if (high1 != high2) + { + /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); + } + else + { + /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + timecounter = (((uint32_t) high1 << 16U) | low); + } + + return timecounter; +} + +/** + * @brief Write the time counter in RTC_CNT registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param TimeCounter: Counter to write in RTC_CNT registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Read the time counter available in RTC_ALR registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc) +{ + uint16_t high1 = 0U, low = 0U; + + high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT); + low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT); + + return (((uint32_t) high1 << 16U) | low); +} + +/** + * @brief Write the time counter in RTC_ALR registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param AlarmCounter: Counter to write in RTC_ALR registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Enters the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + + return HAL_OK; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + + while (Value >= 10U) + { + bcdhigh++; + Value -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | Value); +} + +/** + * @brief Converts from 2 digit BCD to Binary. + * @param Value: BCD value to be converted + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp = 0U; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @brief Updates date when time is 23:59:59. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param DayElapsed: Number of days elapsed from last date update + * @retval None + */ +static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed) +{ + uint32_t year = 0U, month = 0U, day = 0U; + uint32_t loop = 0U; + + /* Get the current year*/ + year = hrtc->DateToUpdate.Year; + + /* Get the current month and day */ + month = hrtc->DateToUpdate.Month; + day = hrtc->DateToUpdate.Date; + + for (loop = 0U; loop < DayElapsed; loop++) + { + if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \ + (month == 8U) || (month == 10U) || (month == 12U)) + { + if (day < 31U) + { + day++; + } + /* Date structure member: day = 31 */ + else + { + if (month != 12U) + { + month++; + day = 1U; + } + /* Date structure member: day = 31 & month =12 */ + else + { + month = 1U; + day = 1U; + year++; + } + } + } + else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U)) + { + if (day < 30U) + { + day++; + } + /* Date structure member: day = 30 */ + else + { + month++; + day = 1U; + } + } + else if (month == 2U) + { + if (day < 28U) + { + day++; + } + else if (day == 28U) + { + /* Leap year */ + if (RTC_IsLeapYear(year)) + { + day++; + } + else + { + month++; + day = 1U; + } + } + else if (day == 29U) + { + month++; + day = 1U; + } + } + } + + /* Update year */ + hrtc->DateToUpdate.Year = year; + + /* Update day and month */ + hrtc->DateToUpdate.Month = month; + hrtc->DateToUpdate.Date = day; + + /* Update day of the week */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day); +} + +/** + * @brief Check whether the passed year is Leap or not. + * @param nYear year to check + * @retval 1: leap year + * 0: not leap year + */ +static uint8_t RTC_IsLeapYear(uint16_t nYear) +{ + if ((nYear % 4U) != 0U) + { + return 0U; + } + + if ((nYear % 100U) != 0U) + { + return 1U; + } + + if ((nYear % 400U) == 0U) + { + return 1U; + } + else + { + return 0U; + } +} + +/** + * @brief Determines the week number, the day number and the week day number. + * @param nYear year to check + * @param nMonth Month to check + * @param nDay Day to check + * @note Day is calculated with hypothesis that year > 2000 + * @retval Value which can take one of the following parameters: + * @arg RTC_WEEKDAY_MONDAY + * @arg RTC_WEEKDAY_TUESDAY + * @arg RTC_WEEKDAY_WEDNESDAY + * @arg RTC_WEEKDAY_THURSDAY + * @arg RTC_WEEKDAY_FRIDAY + * @arg RTC_WEEKDAY_SATURDAY + * @arg RTC_WEEKDAY_SUNDAY + */ +static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay) +{ + uint32_t year = 0U, weekday = 0U; + + year = 2000U + nYear; + + if (nMonth < 3U) + { + /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U; + } + else + { + /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U; + } + + return (uint8_t)weekday; +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c index 93029d4..738ee1f 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c @@ -1,579 +1,575 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_rtc_ex.c - * @author MCD Application Team - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC Tamper functions - * + Extension Control functions - * + Extension RTC features functions - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Macros RTCEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - -/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions - * @brief RTC Tamper functions - * -@verbatim - =============================================================================== - ##### RTC Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Tamper feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to Tamper Structure. - * @note Tamper can be enabled only if ASOE and CCO bit are reset - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - /* Check input parameters */ - if ((hrtc == NULL) || (sTamper == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) - { - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. - * @note Tamper can be enabled only if ASOE and CCO bit are reset - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - /* Check input parameters */ - if ((hrtc == NULL) || (sTamper == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) - { - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); - - /* Configure the Tamper Interrupt in the BKP->CSR */ - __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Tamper: Selected tamper pin. - * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - /* Prevent unused argument(s) compilation warning */ - UNUSED(Tamper); - - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - CLEAR_BIT(BKP->CR, BKP_CR_TPE); - - /* Disable the Tamper Interrupt in the BKP->CSR */ - /* Configure the Tamper Interrupt in the BKP->CSR */ - __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - SET_BIT(BKP->CSR, BKP_CSR_CTE); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles Tamper interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the status of the Interrupt */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) - { - /* Tamper callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper1EventCallback(hrtc); -#else - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions - * @brief RTC Second functions - * -@verbatim - =============================================================================== - ##### RTC Second functions ##### - =============================================================================== - - [..] This section provides functions implementing second interupt handlers - -@endverbatim - * @{ - */ - -/** - * @brief Sets Interrupt for second - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc) -{ - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Enable Second interuption */ - __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Second. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc) -{ - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Deactivate Second interuption*/ - __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles second interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if (__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC)) - { - /* Get the status of the Interrupt */ - if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC)) - { - /* Check if Overrun occurred */ - if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW)) - { - /* Second error callback */ - HAL_RTCEx_RTCEventErrorCallback(hrtc); - - /* Clear flag Second */ - __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - } - else - { - /* Second callback */ - HAL_RTCEx_RTCEventCallback(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - } - - /* Clear flag Second */ - __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC); - } - } -} - -/** - * @brief Second event callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_RTCEventCallback could be implemented in the user file - */ -} - -/** - * @brief Second event error callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extension Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Writes a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Sets the Smooth calibration parameters. - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to - * specify the register (depending devices). - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)BKP_BASE; - tmp += (BackupRegister * 4U); - - *(__IO uint32_t *) tmp = (Data & BKP_DR1_D); -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to - * specify the register (depending devices). - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t backupregister = 0U; - uint32_t pvalue = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - backupregister = (uint32_t)BKP_BASE; - backupregister += (BackupRegister * 4U); - - pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D; - - /* Read the specified register */ - return pvalue; -} - - -/** - * @brief Sets the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Not used (only present for compatibility with another families) - * @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families) - * @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) -{ - /* Check input parameters */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - /* Prevent unused argument(s) compilation warning */ - UNUSED(SmoothCalibPeriod); - UNUSED(SmoothCalibPlusPulses); - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Sets RTC Clock Calibration value.*/ - MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc_ex.c + * @author MCD Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extension peripheral: + * + RTC Tamper functions + * + Extension Control functions + * + Extension RTC features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/** @defgroup RTCEx RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions + * @brief RTC Tamper functions + * +@verbatim + =============================================================================== + ##### RTC Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Tamper feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to Tamper Structure. + * @note Tamper can be enabled only if ASOE and CCO bit are reset + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + /* Check input parameters */ + if ((hrtc == NULL) || (sTamper == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to RTC Tamper. + * @note Tamper can be enabled only if ASOE and CCO bit are reset + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + /* Check input parameters */ + if ((hrtc == NULL) || (sTamper == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); + + /* Configure the Tamper Interrupt in the BKP->CSR */ + __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Tamper. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Tamper: Selected tamper pin. + * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + /* Prevent unused argument(s) compilation warning */ + UNUSED(Tamper); + + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + + /* Disable the Tamper Interrupt in the BKP->CSR */ + /* Configure the Tamper Interrupt in the BKP->CSR */ + __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + SET_BIT(BKP->CSR, BKP_CSR_CTE); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles Tamper interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the status of the Interrupt */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) + { + /* Tamper callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Tamper 1 callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles Tamper1 Polling. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Get the status of the Interrupt */ + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions + * @brief RTC Second functions + * +@verbatim + =============================================================================== + ##### RTC Second functions ##### + =============================================================================== + + [..] This section provides functions implementing second interrupt handlers + +@endverbatim + * @{ + */ + +/** + * @brief Sets Interrupt for second + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Enable Second interruption */ + __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Second. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Deactivate Second interruption*/ + __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles second interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC)) + { + /* Get the status of the Interrupt */ + if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC)) + { + /* Check if Overrun occurred */ + if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW)) + { + /* Second error callback */ + HAL_RTCEx_RTCEventErrorCallback(hrtc); + + /* Clear flag Second */ + __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + } + else + { + /* Second callback */ + HAL_RTCEx_RTCEventCallback(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Clear flag Second */ + __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC); + } + } +} + +/** + * @brief Second event callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_RTCEventCallback could be implemented in the user file + */ +} + +/** + * @brief Second event error callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extension Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Writes a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Sets the Smooth calibration parameters. + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to + * specify the register (depending devices). + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + *(__IO uint32_t *) tmp = (Data & BKP_DR1_D); +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to + * specify the register (depending devices). + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t backupregister = 0U; + uint32_t pvalue = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + backupregister = (uint32_t)BKP_BASE; + backupregister += (BackupRegister * 4U); + + pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D; + + /* Read the specified register */ + return pvalue; +} + + +/** + * @brief Sets the Smooth calibration parameters. + * @param hrtc: RTC handle + * @param SmoothCalibPeriod: Not used (only present for compatibility with another families) + * @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families) + * @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + /* Prevent unused argument(s) compilation warning */ + UNUSED(SmoothCalibPeriod); + UNUSED(SmoothCalibPlusPulses); + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Sets RTC Clock Calibration value.*/ + MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c index b32c0bd..c00a9de 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -1,7483 +1,7629 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + TIM Time Base Initialization - * + TIM Time Base Start - * + TIM Time Base Start Interruption - * + TIM Time Base Start DMA - * + TIM Output Compare/PWM Initialization - * + TIM Output Compare/PWM Channel Configuration - * + TIM Output Compare/PWM Start - * + TIM Output Compare/PWM Start Interruption - * + TIM Output Compare/PWM Start DMA - * + TIM Input Capture Initialization - * + TIM Input Capture Channel Configuration - * + TIM Input Capture Start - * + TIM Input Capture Start Interruption - * + TIM Input Capture Start DMA - * + TIM One Pulse Initialization - * + TIM One Pulse Channel Configuration - * + TIM One Pulse Start - * + TIM Encoder Interface Initialization - * + TIM Encoder Interface Start - * + TIM Encoder Interface Start Interruption - * + TIM Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + TIM OCRef clear configuration - * + TIM External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental encoder for positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - - [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - - [..] - These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. - (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. - (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. - (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. - (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. - (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. - (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - (+) CommutationCallback : TIM Commutation Callback. - (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. - (+) BreakCallback : TIM Break Callback. - - [..] -By default, after the Init and when the state is HAL_TIM_STATE_RESET -all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init / DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit - keep and use the user MspInit / MspDeInit callbacks(registered beforehand) - - [..] - Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit / MspDeInit that can be registered / unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Base_MspInitCallback == NULL) - { - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Base_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Base_MspDeInitCallback == NULL) - { - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Base_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - if (htim->State == HAL_TIM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * -@verbatim - ============================================================================== - ##### TIM Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the TIM Output Compare. - (+) Stop the TIM Output Compare. - (+) Start the TIM Output Compare and enable interrupt. - (+) Stop the TIM Output Compare and disable interrupt. - (+) Start the TIM Output Compare and enable DMA transfer. - (+) Stop the TIM Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OC_MspInitCallback == NULL) - { - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OC_MspDeInitCallback == NULL) - { - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * -@verbatim - ============================================================================== - ##### TIM PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM PWM. - (+) De-initialize the TIM PWM. - (+) Start the TIM PWM. - (+) Stop the TIM PWM. - (+) Start the TIM PWM and enable interrupt. - (+) Stop the TIM PWM and disable interrupt. - (+) Start the TIM PWM and enable DMA transfer. - (+) Stop the TIM PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->PWM_MspInitCallback == NULL) - { - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->PWM_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->PWM_MspDeInitCallback == NULL) - { - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - } - /* DeInit the low level hardware */ - htim->PWM_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * -@verbatim - ============================================================================== - ##### TIM Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the TIM Input Capture. - (+) Stop the TIM Input Capture. - (+) Start the TIM Input Capture and enable interrupt. - (+) Stop the TIM Input Capture and disable interrupt. - (+) Start the TIM Input Capture and enable DMA transfer. - (+) Stop the TIM Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->IC_MspInitCallback == NULL) - { - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->IC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->IC_MspDeInitCallback == NULL) - { - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->IC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM Input Capture handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * -@verbatim - ============================================================================== - ##### TIM One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the TIM One Pulse. - (+) Stop the TIM One Pulse. - (+) Start the TIM One Pulse and enable interrupt. - (+) Stop the TIM One Pulse and disable interrupt. - (+) Start the TIM One Pulse and enable DMA transfer. - (+) Stop the TIM One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @note When the timer instance is initialized in One Pulse mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM One Pulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OnePulse_MspInitCallback == NULL) - { - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OnePulse_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OnePulse_MspDeInitCallback == NULL) - { - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OnePulse_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * -@verbatim - ============================================================================== - ##### TIM Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the TIM Encoder. - (+) Stop the TIM Encoder. - (+) Start the TIM Encoder and enable interrupt. - (+) Stop the TIM Encoder and disable interrupt. - (+) Start the TIM Encoder and enable DMA transfer. - (+) Stop the TIM Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together - * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource - * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa - * @note When the timer instance is initialized in Encoder mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Encoder_MspInitCallback == NULL) - { - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Encoder_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS and ECE bits */ - htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Encoder_MspDeInitCallback == NULL) - { - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Encoder_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData1 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData2 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_ALL: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - default: - break; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->BreakCallback(htim); -#else - HAL_TIMEx_BreakCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM output channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM input Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @note To output a waveform with a minimum delay user can enable the fast - * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx - * output is forced in response to the edge detection on TIx input, - * without taking in account the comparison. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if (OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - break; - } - default: - break; - } - - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - break; - } - - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - break; - } - - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @note Basic timers can only generate an update event. - * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. - * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances - * supporting a break input. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - break; - } - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - break; - } - - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) -{ - uint32_t tmpsmcr; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - break; - } - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - break; - } - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - break; - } - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - break; - } - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - break; - } - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - break; - } - - case TIM_CLOCKSOURCE_ITR0: - case TIM_CLOCKSOURCE_ITR1: - case TIM_CLOCKSOURCE_ITR2: - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) TIM Period elapsed callback - (+) TIM Output Compare callback - (+) TIM Input capture callback - (+) TIM Trigger callback - (+) TIM Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Period elapsed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture half complete callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User TIM callback to be used instead of the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = pCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = pCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Unregister a TIM callback - * TIM callback is redirected to the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - /* Legacy weak Period Elapsed Callback */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - /* Legacy weak Period Elapsed half complete Callback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - /* Legacy weak Trigger Callback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - /* Legacy weak Trigger half complete Callback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - /* Legacy weak IC Capture Callback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - /* Legacy weak IC Capture half complete Callback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - /* Legacy weak OC Delay Elapsed Callback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - /* Legacy weak PWM Pulse Finished Callback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - /* Legacy weak PWM Pulse Finished half complete Callback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - /* Legacy weak Error Callback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - /* Legacy weak Commutation Callback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - /* Legacy weak Commutation half complete Callback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - /* Legacy weak Break Callback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Output Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder Interface handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM handle - * @retval Active channel - */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) -{ - return htim->Channel; -} - -/** - * @brief Return actual state of the TIM channel. - * @param htim TIM handle - * @param Channel TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval TIM Channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - return channel_state; -} - -/** - * @brief Return actual state of a DMA burst operation. - * @param htim TIM handle - * @retval DMA burst state - */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - - return htim->DMABurstState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedHalfCpltCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureHalfCpltCallback(htim); -#else - HAL_TIM_IC_CaptureHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Period Elapse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedHalfCpltCallback(htim); -#else - HAL_TIM_PeriodElapsedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerHalfCpltCallback(htim); -#else - HAL_TIM_TriggerHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter (only for advanced timer) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Timer Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Slave Timer configuration function - * @param htim TIM handle - * @param sSlaveConfig Slave timer configuration - * @retval None - */ -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) - { - return HAL_ERROR; - } - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - break; - } - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_ITR0: - case TIM_TS_ITR1: - case TIM_TS_ITR2: - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } - - default: - break; - } - return HAL_OK; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P); - tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P); - tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) -{ - uint32_t tmpsmcr; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param htim pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void TIM_ResetCallback(TIM_HandleTypeDef *htim) -{ - /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - htim->TriggerCallback = HAL_TIM_TriggerCallback; - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - htim->ErrorCallback = HAL_TIM_ErrorCallback; - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - htim->BreakCallback = HAL_TIMEx_BreakCallback; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P); + tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P); + tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c index f15cbbb..8a565a6 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -1,2335 +1,2359 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), - HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), - HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), - HAL_TIMEx_HallSensor_Start_IT(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @note When the timer instance is initialized in Hall Sensor Interface mode, - * timer channels 1 and channel 2 are reserved and cannot be used for - * other purpose. - * @param htim TIM Hall Sensor Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy week callbacks */ - TIM_ResetCallback(htim); - - if (htim->HallSensor_MspInitCallback == NULL) - { - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->HallSensor_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->HallSensor_MspDeInitCallback == NULL) - { - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - } - /* DeInit the low level hardware */ - htim->HallSensor_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer; - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - /* Enable the Commutation Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @note Interrupts can be generated when an active level is detected on the - * break input, the break 2 input or the system break input. Break - * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - /* Keep this variable initialized to 0 as it is used to configure BDTR register */ - uint32_t tmpbdtr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - UNUSED(Remap); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutCallback could be implemented in the user file - */ -} -/** - * @brief Hall commutation changed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return actual state of the TIM complementary channel. - * @param htim TIM handle - * @param ChannelN TIM Complementary channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @retval TIM Complementary channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); - - channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - - return channel_state; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions - * @{ - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Commutation half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationHalfCpltCallback(htim); -#else - HAL_TIMEx_CommutHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - - -/** - * @brief TIM DMA Delay Pulse complete callback (complementary channel). - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA error callback (complementary channel) - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp; - - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + UNUSED(Remap); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c index 88da3ac..b7cf66c 100755 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c @@ -1,3738 +1,3771 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (##) Enable the USARTx interface clock. - (##) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure the UART TX/RX pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle - (used for last byte sending completion detection in DMA non circular mode) - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the huart Init structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - - (#) For the Multi-Processor mode, initialize the UART registers by calling - the HAL_MultiProcessor_Init() API. - - [..] - (@) The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit - and receive process. - - [..] - (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized - HAL_UART_MspInit() API. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - - [..] - For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). - - [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. - - [..] - When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() - (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - - - [..] This subsection also provides a set of additional functions providing enhanced reception - services to user. (For example, these functions allow application to handle use cases - where number of data to be received is unknown). - - (#) Compared to standard reception services which only consider number of received - data elements as reception completion criteria, these functions also consider additional events - as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) - for 1 frame time, after last received byte. - - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, - or till IDLE event occurs. Reception is handled only during function execution. - When function exits, no data reception could occur. HAL status and number of actually received data elements, - are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. - - (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() - - (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() - - (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() - - - *** UART HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in UART HAL driver. - - (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral - (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not - (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag - (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt - (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt - (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not - - [..] - (@) You can refer to the UART HAL driver header file for more useful macros - - @endverbatim - [..] - (@) Additional remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/** @addtogroup STM32F1xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup UART_Private_Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static void UART_SetConfig(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - please refer to Reference manual for possible UART frame formats. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs - follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration - procedures (details for the procedures are available in reference manuals - (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the UART mode according to the specified parameters in - * the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - } - else - { - assert_param(IS_UART_INSTANCE(huart->Instance)); - } - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); -#if defined(USART_CR1_OVER8) - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#endif /* USART_CR1_OVER8 */ - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); -#if defined(USART_CR1_OVER8) - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#endif /* USART_CR1_OVER8 */ - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); -#if defined(USART_CR1_OVER8) - assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); -#endif /* USART_CR1_OVER8 */ - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In LIN mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); - SET_BIT(huart->Instance->CR2, BreakDetectLength); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the Multi-Processor mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Address USART address - * @param WakeUpMethod specifies the USART wake-up method. - * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Check the Address & wake up method parameters */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - assert_param(IS_UART_ADDRESS(Address)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); -#if defined(USART_CR1_OVER8) - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#endif /* USART_CR1_OVER8 */ - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In Multi-Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Set the USART address node */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); - SET_BIT(huart->Instance->CR2, Address); - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); - SET_BIT(huart->Instance->CR1, WakeUpMethod); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the UART peripheral. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - if (huart->MspDeInitCallback == NULL) - { - huart->MspDeInitCallback = HAL_UART_MspDeInit; - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief UART MSP Init. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspInit could be implemented in the user file - */ -} - -/** - * @brief UART MSP DeInit. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User UART Callback - * To be used instead of the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = pCallback; - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = pCallback; - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = pCallback; - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = pCallback; - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = pCallback; - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = pCallback; - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (huart->gState == HAL_UART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(huart); - - if (HAL_UART_STATE_READY == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_UART_STATE_RESET == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Register a User UART Rx Event Callback - * To be used instead of the weak predefined callback - * @param huart Uart handle - * @param pCallback Pointer to the Rx Event Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = pCallback; - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief UnRegister the UART Rx Event Callback - * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback - * @param huart Uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two modes of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, these API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - while (huart->TxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); - pdata16bits++; - } - else - { - huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); - pdata8bits++; - } - huart->TxXferCount--; - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint32_t tickstart = 0U; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Check the remain data to be received */ - while (huart->RxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); - pdata16bits++; - } - else - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - pdata8bits++; - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit data register empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return(UART_Start_Receive_IT(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return(UART_Start_Receive_DMA(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - uint32_t dmarequest = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_UART_CLEAR_OREFLAG(huart); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - uint32_t dmarequest = 0x00U; - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() - */ - - /* Stop UART DMA Tx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) - * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - __HAL_UNLOCK(huart); - - /* Initialize output number of received elements */ - *RxLen = 0U; - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_IDLEFLAG(huart); - - /* If Set, but no data ever received, clear flag without exiting loop */ - /* If Set, and data has already been received, this means Idle Event is valid : End reception */ - if (*RxLen > 0U) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - } - - /* Check if RXNE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) - { - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - pdata16bits++; - } - else - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - - pdata8bits++; - } - /* Increment number of received elements */ - *RxLen += 1U; - huart->RxXferCount--; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Set number of received elements in output parameter : RxLen */ - *RxLen = huart->RxXferSize - huart->RxXferCount; - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - __HAL_LOCK(huart); - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - status = UART_Start_Receive_IT(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - __HAL_LOCK(huart); - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - status = UART_Start_Receive_DMA(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->RxState and huart->gState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->gState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t AbortCplt = 0x01U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - AbortCplt = 0x00U; - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - AbortCplt = 0x01U; - } - else - { - AbortCplt = 0x00U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (AbortCplt == 0x01U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief This function handles UART interrupt request. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->SR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - uint32_t errorflags = 0x00U; - uint32_t dmarequest = 0x00U; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); - if (errorflags == RESET) - { - /* UART in mode Receiver -------------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - return; - } - } - - /* If some errors occur */ - if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) - { - /* UART parity error interrupt occurred ----------------------------------*/ - if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART noise error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART frame error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) - { - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver -----------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - } /* End if some error occurs */ - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_SR_IDLE) != 0U) - &&((cr1its & USART_SR_IDLE) != 0U)) - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - - /* Check if DMA mode is enabled in UART */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* DMA mode enabled */ - /* Check received length : If all expected data are received, do nothing, - (DMA cplt callback will be called). - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) - { - /* Reception is not complete */ - huart->RxXferCount = nb_remaining_rx_data; - - /* In Normal mode, end DMA xfer and HAL UART Rx process*/ - if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Last bytes received, so no need as the abort is immediate */ - (void)HAL_DMA_Abort(huart->hdmarx); - } -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif - } - return; - } - else - { - /* DMA mode not enabled */ - /* Check received length : If all expected data are received, do nothing. - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxEventCallback(huart, nb_rx_data); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif - } - return; - } - } - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - UART_Transmit_IT(huart); - return; - } - - /* UART in mode Transmitter end --------------------------------------------*/ - if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - UART_EndTransmit_IT(huart); - return; - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief UART error callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). - * @param huart UART handle - * @param Size Number of data available in application reception buffer (indicates a position in - * reception buffer until which, data are available) - * @retval None - */ -__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - UNUSED(Size); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxEventCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART: - (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. - (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. - (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. - (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode - (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode - -@endverbatim - * @{ - */ - -/** - * @brief Transmits break characters. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - SET_BIT(huart->Instance->CR1, USART_CR1_SBK); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enters the UART in mute mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RWU); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Exits the UART mute mode: wake up software. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_TE; - - /* Write to USART CR1 */ - WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_RE; - - /* Write to USART CR1 */ - WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief UART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - UART communication process, return Peripheral Errors occurred during communication - process - (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. - (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the UART state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1 = 0x00U, temp2 = 0x00U; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the UART error code - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code - */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param huart UART handle. - * @retval none - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) -{ - /* Init the UART Callback settings */ - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ - -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* DMA Normal mode*/ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - huart->TxXferCount = 0x00U; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART transmit process half complete callback - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxHalfCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* DMA Normal mode*/ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - huart->RxXferCount = 0U; - - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART receive process half complete callback - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Half Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); -#else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - uint32_t dmarequest = 0x00U; - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Stop UART DMA Tx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - huart->TxXferCount = 0x00U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - huart->RxXferCount = 0x00U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief This function handles UART Communication Timeout. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Flag specifies the UART flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Start Receive operation in interrupt mode. - * @note This function could be called by all HAL UART API providing reception in Interrupt mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); - - return HAL_OK; -} - -/** - * @brief Start Receive operation in DMA mode. - * @note This function could be called by all HAL UART API providing reception in DMA mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); - - /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ - __HAL_UART_CLEAR_OREFLAG(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; -} - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0x00U; - huart->TxXferCount = 0x00U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmarx != NULL) - { - if (huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmatx != NULL) - { - if (huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2U; - } - else - { - huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); - } - - if (--huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - return HAL_OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) huart->pRxBuffPtr; - *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - huart->pRxBuffPtr += 2U; - } - else - { - pdata8bits = (uint8_t *) huart->pRxBuffPtr; - pdata16bits = NULL; - - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - huart->pRxBuffPtr += 1U; - } - - if (--huart->RxXferCount == 0U) - { - /* Disable the UART Data Register not empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_IDLEFLAG(huart); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the UART peripheral. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits - according to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the UART Word Length, Parity and mode: - Set the M bits according to huart->Init.WordLength value - Set PCE and PS bits according to huart->Init.Parity value - Set TE and RE bits according to huart->Init.Mode value - Set OVER8 bit according to huart->Init.OverSampling value */ - -#if defined(USART_CR1_OVER8) - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - MODIFY_REG(huart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - tmpreg); -#else - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; - MODIFY_REG(huart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), - tmpreg); -#endif /* USART_CR1_OVER8 */ - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - - - if(huart->Instance == USART1) - { - pclk = HAL_RCC_GetPCLK2Freq(); - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - } - - /*-------------------------- USART BRR Configuration ---------------------*/ -#if defined(USART_CR1_OVER8) - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - } - else - { - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - } -#else - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); -#endif /* USART_CR1_OVER8 */ -} - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file stm32f1xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART TX/RX pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + [..] + (@) Additional remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration + procedures (details for the procedures are available in reference manuals + (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + } + else + { + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); + SET_BIT(huart->Instance->CR2, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Set the USART address node */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); + SET_BIT(huart->Instance->CR2, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); + SET_BIT(huart->Instance->CR1, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), + * HAL_MultiProcessor_Init() to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() to un-register callbacks for HAL_UART_MSPINIT_CB_ID + * and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Check the remain data to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + const uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + tmp = (const uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); + + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_SR_IDLE) != 0U) + && ((cr1its & USART_SR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + } + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + UART_Transmit_IT(huart); + return; + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + UART_EndTransmit_IT(huart); + return; + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART error code + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + huart->TxXferCount = 0x00U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* DMA Normal mode*/ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t dmarequest = 0x00U; + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0x00U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0x00U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag specifies the UART flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + tmp = (uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); + + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0x00U; + huart->TxXferCount = 0x00U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2U; + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if (--huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) huart->pRxBuffPtr; + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; + } + else + { + pdata8bits = (uint8_t *) huart->pRxBuffPtr; + pdata16bits = NULL; + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + huart->pRxBuffPtr += 1U; + } + + if (--huart->RxXferCount == 0U) + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + +#if defined(USART_CR1_OVER8) + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); +#else + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + tmpreg); +#endif /* USART_CR1_OVER8 */ + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + + + if(huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + } + + /*-------------------------- USART BRR Configuration ---------------------*/ +#if defined(USART_CR1_OVER8) + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#else + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); +#endif /* USART_CR1_OVER8 */ +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/GbTModuleSW30Web.code-workspace b/GbTModuleSW30Web.code-workspace new file mode 100644 index 0000000..e663051 --- /dev/null +++ b/GbTModuleSW30Web.code-workspace @@ -0,0 +1,14 @@ +{ + "folders": [ + { + "path": "." + } + ], + "settings": { + "files.associations": { + "charger_config.h": "c", + "connector.h": "c", + "serial_control.h": "c" + } + } +} \ No newline at end of file diff --git a/GbTModuleSW.ioc b/GbTModuleSW30Web.ioc similarity index 58% rename from GbTModuleSW.ioc rename to GbTModuleSW30Web.ioc index 77b24e9..9a9bd72 100755 --- a/GbTModuleSW.ioc +++ b/GbTModuleSW30Web.ioc @@ -15,7 +15,8 @@ CAN1.BS2=CAN_BS2_2TQ CAN1.CalculateBaudRate=250000 CAN1.CalculateTimeBit=4000 CAN1.CalculateTimeQuantum=222.22222222222223 -CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,ABOM,AWUM,TXFP +CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,ABOM,AWUM,TXFP,NART +CAN1.NART=ENABLE CAN1.Prescaler=8 CAN1.TXFP=ENABLE CAN2.ABOM=ENABLE @@ -36,45 +37,75 @@ Mcu.CPN=STM32F107VCT6 Mcu.Family=STM32F1 Mcu.IP0=ADC1 Mcu.IP1=CAN1 +Mcu.IP10=USART1 +Mcu.IP11=USART2 +Mcu.IP12=USART3 Mcu.IP2=CAN2 -Mcu.IP3=NVIC -Mcu.IP4=RCC -Mcu.IP5=RTC -Mcu.IP6=SYS -Mcu.IP7=USART2 -Mcu.IPNb=8 +Mcu.IP3=CRC +Mcu.IP4=NVIC +Mcu.IP5=RCC +Mcu.IP6=RTC +Mcu.IP7=SYS +Mcu.IP8=TIM4 +Mcu.IP9=UART5 +Mcu.IPNb=13 Mcu.Name=STM32F107V(B-C)Tx Mcu.Package=LQFP100 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PE10 -Mcu.Pin11=PE11 -Mcu.Pin12=PE15 -Mcu.Pin13=PA13 -Mcu.Pin14=PA14 -Mcu.Pin15=PD0 -Mcu.Pin16=PD1 -Mcu.Pin17=PD4 -Mcu.Pin18=PD5 -Mcu.Pin19=PD6 +Mcu.Pin10=PB1 +Mcu.Pin11=PE7 +Mcu.Pin12=PE8 +Mcu.Pin13=PE9 +Mcu.Pin14=PE10 +Mcu.Pin15=PE11 +Mcu.Pin16=PE12 +Mcu.Pin17=PE14 +Mcu.Pin18=PD13 +Mcu.Pin19=PD14 Mcu.Pin2=OSC_IN -Mcu.Pin20=PB4 -Mcu.Pin21=PB5 -Mcu.Pin22=PB6 -Mcu.Pin23=VP_RTC_VS_RTC_Activate +Mcu.Pin20=PD15 +Mcu.Pin21=PA9 +Mcu.Pin22=PA10 +Mcu.Pin23=PA13 +Mcu.Pin24=PA14 +Mcu.Pin25=PA15 +Mcu.Pin26=PC10 +Mcu.Pin27=PC11 +Mcu.Pin28=PC12 +Mcu.Pin29=PD0 Mcu.Pin3=OSC_OUT -Mcu.Pin4=PA6 -Mcu.Pin5=PC4 -Mcu.Pin6=PC5 -Mcu.Pin7=PB0 -Mcu.Pin8=PB1 -Mcu.Pin9=PE9 -Mcu.PinsNb=24 +Mcu.Pin30=PD1 +Mcu.Pin31=PD2 +Mcu.Pin32=PD3 +Mcu.Pin33=PD4 +Mcu.Pin34=PD5 +Mcu.Pin35=PD6 +Mcu.Pin36=PD7 +Mcu.Pin37=PB3 +Mcu.Pin38=PB4 +Mcu.Pin39=PB5 +Mcu.Pin4=PA1 +Mcu.Pin40=PB6 +Mcu.Pin41=PB7 +Mcu.Pin42=PB8 +Mcu.Pin43=PB9 +Mcu.Pin44=PE1 +Mcu.Pin45=VP_CRC_VS_CRC +Mcu.Pin46=VP_RTC_VS_RTC_Activate +Mcu.Pin47=VP_SYS_VS_Systick +Mcu.Pin48=VP_TIM4_VS_ClockSourceINT +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PC4 +Mcu.Pin8=PC5 +Mcu.Pin9=PB0 +Mcu.PinsNb=49 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F107VCTx -MxCube.Version=6.8.0 -MxDb.Version=DB.6.0.80 +MxCube.Version=6.15.0 +MxDb.Version=DB.6.0.150 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.CAN2_RX1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true @@ -88,20 +119,39 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=IN_SW0 +PA1.Locked=true +PA1.Signal=GPIO_Input +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA6.GPIOParameters=GPIO_Label -PA6.GPIO_Label=ADC_CC1 -PA6.Locked=true -PA6.Signal=ADCx_IN6 +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=RELAY_CC +PA15.Locked=true +PA15.Signal=GPIO_Output +PA2.GPIOParameters=GPIO_PuPd,GPIO_Label +PA2.GPIO_Label=IN_SW1 +PA2.GPIO_PuPd=GPIO_PULLDOWN +PA2.Locked=true +PA2.Signal=GPIO_Input +PA3.Locked=true +PA3.Signal=ADCx_IN3 +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX PB0.GPIOParameters=GPIO_Label PB0.GPIO_Label=ADC_NTC1 PB0.Locked=true @@ -110,16 +160,36 @@ PB1.GPIOParameters=GPIO_Label PB1.GPIO_Label=ADC_NTC2 PB1.Locked=true PB1.Signal=ADCx_IN9 +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=IN_FB2 +PB3.Locked=true +PB3.Signal=GPIO_Input PB4.GPIOParameters=GPIO_Label -PB4.GPIO_Label=RELAY_AUX +PB4.GPIO_Label=IN_FB1 PB4.Locked=true -PB4.Signal=GPIO_Output +PB4.Signal=GPIO_Input PB5.Locked=true PB5.Mode=CAN_Activate PB5.Signal=CAN2_RX PB6.Locked=true PB6.Mode=CAN_Activate PB6.Signal=CAN2_TX +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=EE_WP +PB7.Locked=true +PB7.Signal=GPIO_Output +PB8.Locked=true +PB8.Signal=I2C1_SCL +PB9.Locked=true +PB9.Signal=I2C1_SDA +PC10.Locked=true +PC10.Mode=Asynchronous +PC10.Signal=USART3_TX +PC11.Locked=true +PC11.Mode=Asynchronous +PC11.Signal=USART3_RX +PC12.Mode=Asynchronous +PC12.Signal=UART5_TX PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator @@ -138,6 +208,19 @@ PD0.Signal=CAN1_RX PD1.Locked=true PD1.Mode=CAN_Activate PD1.Signal=CAN1_TX +PD13.Locked=true +PD13.Signal=S_TIM4_CH2 +PD14.Locked=true +PD14.Signal=S_TIM4_CH3 +PD15.Locked=true +PD15.Signal=S_TIM4_CH4 +PD2.Locked=true +PD2.Mode=Asynchronous +PD2.Signal=UART5_RX +PD3.GPIOParameters=GPIO_Label +PD3.GPIO_Label=RELAY_DC +PD3.Locked=true +PD3.Signal=GPIO_Output PD4.GPIOParameters=GPIO_Label PD4.GPIO_Label=USART2_DIR PD4.Locked=true @@ -148,27 +231,46 @@ PD5.Signal=USART2_TX PD6.Locked=true PD6.Mode=Asynchronous PD6.Signal=USART2_RX -PE10.GPIOParameters=GPIO_PuPd,GPIO_Label -PE10.GPIO_Label=ADDR_0 -PE10.GPIO_PuPd=GPIO_PULLUP +PD7.GPIOParameters=GPIO_Label +PD7.GPIO_Label=IN_ESTOP +PD7.Locked=true +PD7.Signal=GPIO_Input +PE1.GPIOParameters=GPIO_Label +PE1.GPIO_Label=ISO_IN +PE1.Locked=true +PE1.Signal=GPIO_Input +PE10.GPIOParameters=GPIO_Label +PE10.GPIO_Label=RELAY3 PE10.Locked=true -PE10.Signal=GPIO_Input -PE11.GPIOParameters=GPIO_PuPd,GPIO_Label -PE11.GPIO_Label=ADDR_1 -PE11.GPIO_PuPd=GPIO_PULLUP +PE10.Signal=GPIO_Output +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=RELAY4 PE11.Locked=true -PE11.Signal=GPIO_Input -PE15.GPIOParameters=GPIO_Label -PE15.GPIO_Label=RELAY_CC -PE15.Locked=true -PE15.Signal=GPIO_Output +PE11.Signal=GPIO_Output +PE12.GPIOParameters=GPIO_Label +PE12.GPIO_Label=RELAY5 +PE12.Locked=true +PE12.Signal=GPIO_Output +PE14.GPIOParameters=GPIO_Label +PE14.GPIO_Label=AC_OK +PE14.Locked=true +PE14.Signal=GPIO_Input +PE7.GPIOParameters=GPIO_Label +PE7.GPIO_Label=IN0 +PE7.Locked=true +PE7.Signal=GPIO_Input +PE8.GPIOParameters=GPIO_Label +PE8.GPIO_Label=RELAY1 +PE8.Locked=true +PE8.Signal=GPIO_Output PE9.GPIOParameters=GPIO_Label -PE9.GPIO_Label=LOCK_FB +PE9.GPIO_Label=RELAY2 PE9.Locked=true -PE9.Signal=GPIO_Input -PinOutPanel.RotationAngle=0 +PE9.Signal=GPIO_Output +PinOutPanel.RotationAngle=-90 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=true +ProjectManager.CompilerLinker=GCC ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=true @@ -176,26 +278,28 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F107VCTx -ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 +ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.6 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=false +ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=GbTModuleSW.ioc -ProjectManager.ProjectName=GbTModuleSW +ProjectManager.ProjectFileName=GbTModuleSW30Web.ioc +ProjectManager.ProjectName=GbTModuleSW30Web ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true,5-MX_CAN2_Init-CAN2-false-HAL-true,6-MX_USART2_UART_Init-USART2-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true,5-MX_CAN2_Init-CAN2-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_TIM4_Init-TIM4-false-HAL-true,8-MX_USART2_UART_Init-USART2-false-HAL-true,9-MX_CRC_Init-CRC-false-HAL-true,10-MX_UART5_Init-UART5-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_USART3_UART_Init-USART3-false-HAL-true RCC.ADCFreqValue=12000000 RCC.ADCPresc=RCC_ADCPCLK2_DIV6 RCC.AHBFreq_Value=72000000 @@ -230,15 +334,39 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=48000000 RCC.VCOOutput2Freq_Value=8000000 -SH.ADCx_IN6.0=ADC1_IN6,IN6 -SH.ADCx_IN6.ConfNb=1 +SH.ADCx_IN3.0=ADC1_IN3,IN3 +SH.ADCx_IN3.ConfNb=1 SH.ADCx_IN8.0=ADC1_IN8,IN8 SH.ADCx_IN8.ConfNb=1 SH.ADCx_IN9.0=ADC1_IN9,IN9 SH.ADCx_IN9.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 +SH.S_TIM4_CH2.ConfNb=1 +SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 +SH.S_TIM4_CH3.ConfNb=1 +SH.S_TIM4_CH4.0=TIM4_CH4,PWM Generation4 CH4 +SH.S_TIM4_CH4.ConfNb=1 +TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM4.IPParameters=Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Prescaler,Period +TIM4.Period=100 +TIM4.Prescaler=720 +UART5.IPParameters=VirtualMode +UART5.VirtualMode=Asynchronous +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC USART2.IPParameters=VirtualMode USART2.VirtualMode=VM_ASYNC +USART3.IPParameters=VirtualMode +USART3.VirtualMode=VM_ASYNC +VP_CRC_VS_CRC.Mode=CRC_Activate +VP_CRC_VS_CRC.Signal=CRC_VS_CRC VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT board=custom isbadioc=false diff --git a/LOGGING_RECOMMENDATIONS.md b/LOGGING_RECOMMENDATIONS.md new file mode 100644 index 0000000..2fe7bd1 --- /dev/null +++ b/LOGGING_RECOMMENDATIONS.md @@ -0,0 +1,260 @@ +# Рекомендации по добавлению log_printf в проект + +## Обзор +Этот документ содержит рекомендации по добавлению логирования ошибок и информационных сообщений в проект зарядной станции GB/T. + +## 1. Инициализация и конфигурация (main.c, can.c, adc.c, usart.c, tim.c, rtc.c) + +### 1.1 main.c +**Место:** Функция `Error_Handler()` +```c +void Error_Handler(void) { + log_printf(LOG_CRIT, "System error occurred, entering infinite loop\n"); + __disable_irq(); + while (1) { } +} +``` + +**Место:** Функция `SystemClock_Config()` +- После `HAL_RCC_OscConfig()` - добавить логирование успешной инициализации осцилляторов +- После `HAL_RCC_ClockConfig()` - добавить логирование успешной конфигурации тактирования +- После `HAL_RCCEx_PeriphCLKConfig()` - добавить логирование успешной конфигурации периферийных часов + +**Место:** Функция `main()` +- После успешной инициализации каждого периферийного устройства (CAN, ADC, UART, RTC, TIM) +- При установке конфигурации: `log_printf(LOG_INFO, "Config loaded: location=%.3s, charger=%lu\n", config.location, config.chargerNumber);` + +### 1.2 can.c +**Место:** Функции `MX_CAN1_Init()` и `MX_CAN2_Init()` +- После проверки `HAL_CAN_Init()` - логировать ошибку инициализации CAN +- Добавить логирование успешной инициализации: `log_printf(LOG_INFO, "CAN%d initialized\n", can_num);` + +**Место:** Функция `PSU_CAN_FilterInit()` в psu_control.c +- После проверки `HAL_CAN_ConfigFilter()` - логировать ошибку конфигурации фильтра + +### 1.3 adc.c +**Место:** Функция `MX_ADC1_Init()` +- После проверки `HAL_ADC_Init()` - логировать ошибку инициализации ADC +- После проверки `HAL_ADC_ConfigChannel()` - логировать ошибку конфигурации канала +- Добавить логирование успешной инициализации: `log_printf(LOG_INFO, "ADC1 initialized\n");` + +### 1.4 usart.c +**Место:** Функция `MX_USART2_UART_Init()` +- После проверки `HAL_UART_Init()` - логировать ошибку инициализации UART +- Добавить логирование успешной инициализации: `log_printf(LOG_INFO, "USART2 initialized, baudrate=%d\n", 115200);` + +### 1.5 tim.c +**Место:** Функции инициализации таймеров +- После каждой проверки `HAL_TIM_*_Init()` - логировать ошибки инициализации таймеров + +### 1.6 rtc.c / soft_rtc.c +**Место:** Функции работы с RTC +- После проверки `HAL_RTC_Init()` - логировать ошибку инициализации RTC +- В функции `set_Time()` - логировать установку времени: `log_printf(LOG_INFO, "Time set: %lu\n", unix_time);` + +## 2. Управление зарядкой (charger_gbt.c) + +### 2.1 Ошибки протокола GB/T +**Место:** Уже есть логирование таймаутов (BHM, BRM, BCP, BRO, BSD), но можно добавить: +- При получении неожиданных PGN: `log_printf(LOG_WARN, "Unexpected PGN received: 0x%X\n", PGN);` +- При ошибке отправки пакета: `log_printf(LOG_WARN, "Failed to send GBT packet, state=%d\n", GBT_State);` + +### 2.2 Состояния зарядки +**Место:** Функция `GBT_ChargerTask()` +- При переходе в состояние `GBT_S10_CHARGING` - логировать параметры зарядки: + ```c + log_printf(LOG_INFO, "Charging started: V=%dV, I=%dA\n", volt/10, curr/10); + ``` +- При остановке зарядки - логировать причину: + ```c + log_printf(LOG_INFO, "Charging stopped, cause: 0x%X\n", GBT_StopCauseCode); + ``` + +### 2.3 Ошибки изоляции +**Место:** Состояние `GBT_S4_ISOTEST` +- При обнаружении ошибки изоляции: `log_printf(LOG_ERR, "Isolation test failed\n");` + +### 2.4 Перегрев коннектора +**Место:** Уже есть логирование в состоянии `GBT_S10_CHARGING`, но можно улучшить: +- Добавить логирование при восстановлении нормальной температуры + +## 3. Управление PSU (psu_control.c) + +### 3.1 Ошибки CAN связи с PSU +**Место:** Функция `PSU_Loop()` +- При потере связи с PSU (таймаут > 500мс): + ```c + if((HAL_GetTick() - can_lastpacket[psu_n]) > 500) { + if(psu_online[psu_n] == 1) { + log_printf(LOG_WARN, "PSU%d communication lost\n", psu_n); + } + psu_online[psu_n] = 0; + } + ``` +- При восстановлении связи: + ```c + if(psu_online[psu_n] == 0) { + log_printf(LOG_INFO, "PSU%d communication restored\n", psu_n); + } + ``` + +### 3.2 Ошибки отправки команд +**Место:** Функция `PSU_SendCmd()` +- При исчерпании попыток отправки: + ```c + if(retry_counter == 0) { + log_printf(LOG_ERR, "PSU_SendCmd failed: source=0x%02X, dest=0x%02X, cmd=0x%02X\n", + source, destination, cmd); + } + ``` + +### 3.3 Ограничения мощности +**Место:** Функция `PSU_Loop()` +- При ограничении мощности: + ```c + if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > power_limit) { + log_printf(LOG_INFO, "Power limited: %dW -> %dW\n", + (CONN.WantedCurrent/10) * CONN.MeasuredVoltage, + power_limit * 10); + } + ``` + +### 3.4 Переключение HV режима +**Место:** Функция `PSU_Loop()` +- При переключении в HV режим: `log_printf(LOG_INFO, "PSU HV mode enabled (V>490V)\n");` +- При выходе из HV режима: `log_printf(LOG_INFO, "PSU HV mode disabled\n");` + +## 4. Управление коннектором (connector.c) + +### 4.1 Изменение состояния CC +**Место:** Функция `CONN_CC_ReadStateFiltered()` +- При изменении состояния CC: + ```c + if (CC_STATE_FILTERED != prev_state) { + log_printf(LOG_INFO, "CC state changed: %d -> %d (voltage=%.2fV)\n", + prev_state, CC_STATE_FILTERED, CONN_CC_GetAdc()); + } + ``` + +### 4.2 Ошибки ADC +**Место:** Функция `CONN_CC_GetAdc()` +- При ошибке чтения ADC: `log_printf(LOG_ERR, "CC ADC read error\n");` +- При неожиданных значениях напряжения: `log_printf(LOG_WARN, "CC voltage out of range: %.2fV\n", volt);` + +## 5. Управление замком (lock.c) + +### 5.1 Уже есть логирование ошибок замка, но можно добавить: +**Место:** Функция `GBT_ManageLockMotor()` +- При успешном выполнении действия: `log_printf(LOG_INFO, "Lock %s successful\n", state ? "locked" : "unlocked");` +- При начале попытки: `log_printf(LOG_DEBUG, "Lock action: %s, attempt %d\n", state ? "lock" : "unlock", GBT_LockState.retry_count + 1);` + +## 6. Последовательная связь (serial_control.c) + +### 6.1 Ошибки протокола +**Место:** Функция `process_received_packet()` +- При неверном CRC: `log_printf(LOG_WARN, "Serial packet CRC error\n");` +- При неверном формате пакета: `log_printf(LOG_WARN, "Serial packet format error, len=%d\n", packet_len);` + +### 6.2 Таймауты передачи +**Место:** Функция `SerialControl_Task()` +- При таймауте передачи: `log_printf(LOG_WARN, "UART TX timeout, aborting\n");` + +### 6.3 Ошибки команд +**Место:** Функция `process_received_command()` в serial_handler.c +- При неизвестной команде: `log_printf(LOG_WARN, "Unknown command: 0x%02X\n", cmd.command);` +- При неверной длине аргументов: `log_printf(LOG_WARN, "Command 0x%02X: invalid argument length: %d\n", cmd.command, cmd.argument_length);` + +### 6.4 Успешные команды +**Место:** Функция `command_handler()` в serial_handler.c +- При установке конфигурации: `log_printf(LOG_INFO, "Config updated: location=%.3s, charger=%lu\n", config.location, config.chargerNumber);` +- При изменении лимита мощности: `log_printf(LOG_INFO, "Power limit set: %dW\n", power_limit * 1000);` +- При изменении разрешения зарядки: `log_printf(LOG_INFO, "Charge permit: %s\n", CONN.connControl ? "allowed" : "not allowed");` +- При включении тестового режима PSU: `log_printf(LOG_INFO, "PSU test mode: V=%dV, I=%dA\n", PSU_TestMode.voltage, PSU_TestMode.current);` + +## 7. J1939 протокол (j1939.c) + +### 7.1 Ошибки приема +**Место:** Функция `HAL_CAN_RxFifo0MsgPendingCallback()` +- При ошибке получения сообщения: `log_printf(LOG_WARN, "J1939 RX error\n");` +- При неверном PGN: `log_printf(LOG_WARN, "J1939 invalid PGN: 0x%X\n", PGN);` + +### 7.2 Ошибки отправки +**Место:** Функция `J_SendPacket()` +- При ошибке отправки: `log_printf(LOG_WARN, "J1939 TX error: PGN=0x%X\n", PGN);` + +### 7.3 Ошибки протокола передачи данных +**Место:** Обработка длинных пакетов +- При ошибке последовательности пакетов: `log_printf(LOG_WARN, "J1939 packet sequence error: expected %d, got %d\n", expected, received);` +- При таймауте передачи: `log_printf(LOG_WARN, "J1939 transmission timeout: PGN=0x%X\n", j_rx.PGN);` + +### 7.4 Реинициализация CAN +**Место:** Функция `GBT_CAN_ReInit()` +- При успешной реинициализации: `log_printf(LOG_INFO, "CAN1 reinitialized\n");` +- При ошибке: `log_printf(LOG_ERR, "CAN1 reinit failed\n");` + +## 8. Управление реле (CONT_Loop в psu_control.c) + +### 8.1 Ошибки контактора +**Место:** Уже есть логирование ошибки контактора, но можно добавить: +- При восстановлении нормальной работы: `log_printf(LOG_INFO, "Contactor feedback OK\n");` + +### 8.2 Управление реле +**Место:** Функция `CONT_Loop()` +- При включении/выключении реле AC: `log_printf(LOG_DEBUG, "Relay AC: %s\n", state ? "ON" : "OFF");` +- При включении/выключении реле DC: `log_printf(LOG_DEBUG, "Relay DC: %s\n", state ? "ON" : "OFF");` + +## 9. Измерение энергии (meter.c) + +### 9.1 Сброс счетчика +**Место:** Функция `METER_CalculateEnergy()` +- При сбросе смещения энергии: `log_printf(LOG_INFO, "Energy meter reset, offset=%lu Wh\n", METER.EnergyOffset);` + +### 9.2 Ошибки расчета +**Место:** Функция `METER_CalculateEnergy()` +- При переполнении счетчика: `log_printf(LOG_WARN, "Energy meter overflow detected\n");` + +## 10. Общие рекомендации + +### 10.1 Уровни логирования +- `LOG_EMERG` / `LOG_CRIT` - критические ошибки, требующие немедленного внимания (Error_Handler) +- `LOG_ERR` - ошибки, влияющие на функциональность (таймауты протокола, ошибки связи) +- `LOG_WARN` - предупреждения (потеря связи, неверные данные) +- `LOG_INFO` - информационные сообщения (изменение состояний, успешные операции) +- `LOG_DEBUG` - отладочная информация (детали работы алгоритмов) + +### 10.2 Формат сообщений +Рекомендуемый формат: `"[Module] Action: details\n"` +Примеры: +- `log_printf(LOG_INFO, "[PSU] Communication restored: PSU%d\n", psu_n);` +- `log_printf(LOG_ERR, "[GBT] Protocol error: BHM timeout\n");` +- `log_printf(LOG_WARN, "[CAN] TX failed: retries exhausted\n");` + +### 10.3 Частота логирования +- Избегать логирования в циклах с высокой частотой (например, каждые 10мс) +- Использовать флаги для логирования изменений состояния (как `ED_TraceWarning`) +- Логировать только при изменении состояния или при ошибках + +### 10.4 Производительность +- `log_printf` использует буфер, но все равно стоит избегать избыточного логирования +- Для отладочной информации использовать `LOG_DEBUG`, который можно отключить в релизной версии + +## 11. Приоритетные места для добавления логирования + +1. **Критично:** + - Error_Handler() - добавить логирование перед зависанием + - Ошибки инициализации периферии (CAN, ADC, UART, RTC) + - Ошибки связи с PSU + - Ошибки контактора + +2. **Важно:** + - Изменения состояний зарядки + - Параметры начала зарядки + - Причины остановки зарядки + - Ошибки протокола GB/T + +3. **Полезно:** + - Изменения состояния CC + - Управление реле + - Команды через последовательный порт + - Ограничения мощности + diff --git a/STM32F107VCTX_FLASH.ld b/STM32F107VCTX_FLASH.ld index 2012645..3b6598f 100755 --- a/STM32F107VCTX_FLASH.ld +++ b/STM32F107VCTX_FLASH.ld @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K + FLASH (rx) : ORIGIN = 0x8008000, LENGTH = 256K - 32K } /* Sections */ diff --git a/bem.asc b/bem.asc new file mode 100644 index 0000000..3b17241 --- /dev/null +++ b/bem.asc @@ -0,0 +1,24340 @@ +date Sun Nov 02 04:30:19.764 pm 2025 +base hex timestamps absolute +internal events logged +// version 8.5.0 +Begin Triggerblock Sun Nov 02 04:30:19.764 pm 2025 + 0.000000 Start of measurement + 0.000000 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 0.000002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.022026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.038790 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.070738 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.088807 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.122005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.138767 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.172016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.182027 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 0.188844 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.222012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.230000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 0.232041 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.238776 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 0.248787 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 0.250011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.272012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.288782 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.322015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 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= 0 BitCount = 0 ID = 485185268x + 0.500007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.522014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.538799 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.572009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.588774 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.622015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.638817 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.670724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.682027 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 0.688761 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.722042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.730004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 0.732041 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.740001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 0.748794 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 0.750004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.770735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.788763 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.822023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.838823 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.872001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.888779 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.922006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.932001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 0.938784 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 0.970745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 0.980831 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 0.980833 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 0.988804 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 1.000009 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 1.000012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.021996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.038760 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.070745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.088787 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.122021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.138780 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.172028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.182012 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 1.188765 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.221997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.230022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 1.231982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.238769 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 1.248820 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 1.250021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.271998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.288794 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.322025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.338743 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.372016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.388787 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.422027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.432028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 1.438769 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.472000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.480017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 1.482021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.488778 1 1ceb56f4x Rx d 8 01 12 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 1.498768 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 1.499989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.522002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.538744 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.571996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.588753 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.621998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.638789 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.670708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.682007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 1.688773 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.722002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.730015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 1.731992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.738787 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 1.748801 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 1.749995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.772000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.788774 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.822009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.838761 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.870718 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.888746 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.921997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.932002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 1.938741 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 1.972007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 1.980000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 1.982031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 1.988802 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 2.000001 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 2.000003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.021996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.038776 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.071996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.088751 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.122012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.138727 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.172008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.182002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 2.188752 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.222009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.230001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 2.232010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.239996 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 2.248754 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 2.249991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.272005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.288738 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.321996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.338742 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.371992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.388756 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.422025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.431987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 2.438768 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.472015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.480802 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 2.480804 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.488738 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 2.498792 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 2.499995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.521995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.538763 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.572021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.588760 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.622015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.638796 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.671997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.682018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 2.688738 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.721994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.729989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 2.732001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.738779 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 2.748780 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 2.749990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.772001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.788753 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.821999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.838720 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.872024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.888725 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.922000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.930714 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 2.938751 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 2.971992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 2.980021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 2.982001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 2.988745 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 2.998757 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 2.999993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.022002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.038715 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.070675 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.088716 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.122024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.138745 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.172027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.182007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 3.188696 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.222023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.230004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 3.232051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.238714 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 3.248762 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 3.249986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.272025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.288703 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.322005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.338713 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.370669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.388690 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.422025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.431999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 3.438741 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.472008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.480012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 3.482020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.488706 1 1ceb56f4x Rx d 8 01 0D 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 3.500042 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 3.500045 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.522007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.538691 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.572019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.588733 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.622001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.638714 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.672004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.680659 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 3.688724 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.722024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.730004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 3.732010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.740011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 3.748715 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 3.749983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.770640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.788704 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.822056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.838712 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.871998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.888756 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.922032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.932034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 3.938686 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 3.972003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 3.980750 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 3.980752 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 3.988732 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 4.000003 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 4.000006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.022007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.038711 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.072009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.088676 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.122000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.138713 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.172020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.182002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 4.188717 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.222017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.230032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 4.232016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.238720 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 4.248763 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 4.249985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.271996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.288736 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.322017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.338720 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.370682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.388707 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.422027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.430687 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 4.438693 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.472011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.480001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 4.482028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.488733 1 1ceb56f4x Rx d 8 01 1C 11 A2 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 4.498722 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 4.499986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.522001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.538716 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.571990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.588698 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.622014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.638669 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.671998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.680636 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 4.688673 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.720662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.730024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 4.732011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.738730 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 4.748708 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 4.749985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.770611 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.788678 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.820628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.838711 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.870615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.888683 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.920629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.930725 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 4.938691 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 4.970619 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 4.980045 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 4.981993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 4.988660 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 5.000016 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 5.000019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.020634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.038674 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.070649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.088671 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.120647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.138675 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.170625 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.180645 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 5.188659 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.220633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.230013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 5.232025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.240003 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 5.248691 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 5.249990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.270621 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.288656 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.320616 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.338684 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.370633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.388653 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.420623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.430642 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 5.438652 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.470598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.480709 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 5.480711 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.488699 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 5.498659 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 5.500023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.520614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.538678 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.570612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.588687 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.620597 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.638652 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.670630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.680616 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 5.688709 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.720624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.729997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 5.732033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.738688 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 5.748666 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 5.749987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.770618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.788649 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.820603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.838676 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.870608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.888629 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.920612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.930638 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 5.938667 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 5.970606 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 5.980012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 5.982036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 5.988708 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 5.998672 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 5.999983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.020594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.038632 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.070597 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.088646 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.120638 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.138674 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.170588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.180594 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 6.188630 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.220614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.230001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 6.231996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.238655 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 6.248664 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 6.249997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.270626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.288646 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.320618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.338663 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.370612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.388643 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.420607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.430617 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 6.438684 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.470583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.480011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 6.482034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.488638 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 6.499992 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 6.499995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.520574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.538667 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.570585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.588624 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.620583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.638616 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.670615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.680594 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 6.688668 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.720651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.730007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 6.731987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.738645 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 6.748608 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 6.749987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.770599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.788634 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.820600 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.838630 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.870602 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.888643 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.920591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.930568 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 6.938657 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 6.970623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 6.980660 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 6.980662 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 6.988619 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 6.998625 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 7.000006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.020633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.038648 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.070587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.088660 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.120563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.138648 1 1812f456x Rx d 8 08 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.170574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.180622 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 7.188642 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.220608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.230031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 7.231998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.238671 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 7.248642 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 7.249985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.270591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.288614 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.320592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.338638 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.370613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.388622 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.420570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.430598 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 7.438651 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.470621 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.479993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 7.482001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.488620 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 7.498631 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 7.499983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.520628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.538631 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.570613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.588608 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.620572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.638581 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.670617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.680605 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 7.688607 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.720592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.729998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 7.732011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.738617 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 7.748625 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 7.749988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.770610 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.788583 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.820628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.838583 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.870583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.888591 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.920597 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.930614 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 7.938633 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 7.970573 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 7.980030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 7.982030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 7.988601 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 7.998655 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 7.999976 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.020575 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.038618 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.070579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.088634 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.120604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.138673 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.170600 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.180594 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 8.188618 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.220614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.229995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 8.232017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.238606 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 8.248590 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 8.250368 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.270598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.288622 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.320603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.338598 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.370645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.388588 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.420613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.430629 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 8.438606 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.470574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.480683 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 8.480686 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.488595 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 8.498573 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 8.499986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.520633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.538597 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.570587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.588602 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.620621 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.638593 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.670596 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.680598 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 8.688592 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.720584 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.730023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 8.732045 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.738598 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 8.748573 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 8.749987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.770594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.788609 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.820633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.838600 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.870599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.888603 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.920574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.930601 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 8.938636 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 8.970577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 8.979990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 8.982006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 8.988583 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 8.998592 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 8.999993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.020616 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.038611 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.070577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.088591 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.120570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.138588 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.170606 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.180613 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 9.188629 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.220576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.230023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 9.231993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.238603 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 9.248595 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 9.249988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.270608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.288604 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.320579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.338600 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.370591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.388621 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.420576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.430592 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 9.438587 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.470646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.480033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 9.482000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.488622 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 9.498596 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 9.499986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.520512 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.538587 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.570606 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.588616 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.620504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.638599 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.670517 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.680494 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 9.688611 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.720544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.730013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 9.732019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.738623 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 9.748632 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 9.749980 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.770507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.788576 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.820495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.838576 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.870567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.888578 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.920524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.930541 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 9.938597 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 9.970507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 9.980631 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 9.980633 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 9.988609 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 9.998603 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 9.999998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.020537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.038624 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.070540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.088596 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.120536 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.138618 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.170518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.180509 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 10.188611 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.220525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.230035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 10.232031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.238593 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 10.248602 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 10.249980 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.270506 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.288605 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.320485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.338585 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.370524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.388625 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.420529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.430507 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 10.438571 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.470522 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.480050 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 10.482008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.488631 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 10.498586 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 10.499987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.520493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.538632 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.570513 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.588603 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.620520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.638611 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.670522 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.680495 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 10.688610 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.720492 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.730010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 10.731992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.738605 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 10.748635 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 10.749997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.770510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.788590 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.820482 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.838593 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.870502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.888581 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.920507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.930506 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 10.938597 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 10.970513 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 10.979999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 10.982020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 10.988591 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 10.998589 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 10.999992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.020499 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.038005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.070495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.088043 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.120502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.138005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.170483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.180483 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 11.188028 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.220490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.229995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 11.231999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.238529 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 11.248554 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 11.249986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.270463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.288015 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.320475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.338033 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.370478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.388025 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.420483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.430477 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 11.438020 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.470473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.480055 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 11.482018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.488521 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 11.498535 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 11.500015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.520475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.538025 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.570446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.588009 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.620452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.638001 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.670484 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.680485 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 11.688001 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.720478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.729999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 11.732014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.738542 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 11.748514 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 11.749997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.770439 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.788013 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.820443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.838034 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.870489 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.888045 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.920478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.930481 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 11.938015 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 11.970460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 11.979999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 11.981998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 11.988517 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 11.998566 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 11.999993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.020468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.038021 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.070444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.088005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.120498 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.138024 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.170452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.180460 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 12.188026 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.220472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.229998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 12.232001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.238503 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 12.248491 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 12.249999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.270440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.288017 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.320468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.338022 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.370465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.388028 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.420473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.430467 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 12.438011 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.470471 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.480026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 12.482052 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.488488 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 12.498522 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 12.499995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.520446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.538001 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.570490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.588004 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.620490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.638009 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.670472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.680467 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 12.688025 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.720494 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.730039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 12.732035 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.738517 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 12.748499 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 12.749990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.770452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.788004 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.820448 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.838018 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.870450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.888022 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.920481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.930494 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 12.938035 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 12.970468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 12.979993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 12.982034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 12.988556 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 12.998513 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 12.999995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.020478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.038000 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.070462 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.087990 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.120514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.138003 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.170514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.180491 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 13.188026 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.220478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.229999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 13.231997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.238500 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 13.248510 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 13.249987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.270451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.288006 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.320440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.337999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.370493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.388010 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.420463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.430490 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 13.437991 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.470457 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.480002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 13.482005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.488456 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 13.498462 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 13.499994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.520464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.538010 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.570479 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.588002 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.620460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.638009 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.670487 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.680487 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 13.688033 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.720475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.730032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 13.732008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.738471 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 13.748490 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 13.749997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.770443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.788012 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.820450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.838029 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.870472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.888024 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.920486 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.930453 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 13.938024 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 13.970479 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 13.979985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 13.982009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 13.988490 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 13.998454 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 13.999988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.020459 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.038001 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.070458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.087998 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.120464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.138030 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.170461 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.180486 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 14.188000 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.220442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.230023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 14.231999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.238507 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 14.248476 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 14.250019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.270466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.288011 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.320458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.337999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.370446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.388035 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.420465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.430479 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 14.438011 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.470461 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.479985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 14.481987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.488481 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 14.498456 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 14.499992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.520443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.538032 1 1812f456x Rx d 8 12 11 93 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.570532 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.588025 1 1812f456x Rx d 8 12 11 93 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.620441 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.637999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.670455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.680483 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 14.687993 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.720386 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.730036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 14.732031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.738529 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 14.748468 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 14.750003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.770440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.788029 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.820381 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.837999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.870444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.888010 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.920402 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.930396 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 14.938003 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 14.970398 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 14.980019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 14.982029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 14.988478 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 14.998526 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 14.999990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.020377 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.038025 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.070362 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.087997 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.120425 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.138043 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.170358 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.180369 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 15.188019 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.220405 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.230001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 15.232005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.238453 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 15.248455 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 15.250007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.270399 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.287990 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.320409 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.338020 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.370360 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.388008 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.420387 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.430379 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 15.437996 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.470439 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.480010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 15.482010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.488500 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 15.498454 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 15.499988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.520401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.537999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.570367 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.588004 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.620419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.637985 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.670368 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.680376 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 15.688037 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.720343 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.729985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 15.732031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.738457 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 15.748521 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 15.750014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.770376 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.788016 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.820382 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.838005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.870347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.888003 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.920354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.930372 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 15.938002 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 15.970408 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 15.980034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 15.982018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 15.988472 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 15.998442 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 16.000013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.020395 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.038005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.070331 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.088003 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.120370 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.138021 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.170369 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.180359 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 16.188008 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.220373 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.230040 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 16.232023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.238492 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 16.248467 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 16.249998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.270342 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.288035 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.320358 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.338007 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.370361 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.388033 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.420337 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.430366 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 16.438020 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.470347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.480004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 16.482021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.488487 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 16.498383 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 16.499984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.520335 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.538018 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.570333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.588006 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.620340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.638004 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.670357 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.680335 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 16.688025 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.720355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.730002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 16.732004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.738393 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 16.748400 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 16.749995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.770331 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.788018 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.820355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.837998 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.870334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.888013 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.920343 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.930349 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 16.938013 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 16.970355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 16.979998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 16.982010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 16.988409 1 1ceb56f4x Rx d 8 01 21 11 A2 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 16.998424 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 16.999988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.020345 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.037998 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.070350 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.087995 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.120363 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.137999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.170327 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.180361 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 17.188039 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.220330 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.230027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 17.232034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.238367 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 17.248376 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 17.250000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.270344 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.288014 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.320338 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.338005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.370319 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.388009 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.420317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.430320 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 17.437996 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.470317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.480000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 17.482030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.488404 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 17.498376 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 17.499981 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.520318 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.537993 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.570340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.587999 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.620330 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.638000 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.670332 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.680338 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 17.688005 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.720342 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.730003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 17.732001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.738387 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 17.748372 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 17.749988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.770312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.787995 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.820299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.837995 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.870359 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.887997 1 1812f456x Rx d 8 12 11 92 0D 32 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.920335 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.930365 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 17.938000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 17.970342 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 17.980010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 17.982010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 17.988377 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 17.998341 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 17.999997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.020296 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.037997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.070282 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.087996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.120300 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.138041 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.170310 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.180346 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 18.188043 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.220317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.229997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 18.231991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.238369 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 18.248347 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 18.250007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.270293 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.287996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.320361 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.337994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.370285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.387995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.420290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.430317 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 18.438001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.470313 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.480011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 18.482044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.488379 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 18.498336 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 18.499984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.520301 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.538000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.570279 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.588008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.620310 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.637995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.670339 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.680323 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 18.687998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.720319 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.730036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 18.732024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.738344 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 18.748387 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 18.749983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.770297 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.787998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.820302 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.837998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.870319 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.888000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.920279 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.930312 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 18.938035 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 18.970294 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 18.979993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 18.982017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 18.988378 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 18.999994 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 18.999996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.020321 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.037995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.070288 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.088002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.120288 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.138011 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.170311 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.180294 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 19.188036 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.220272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.230021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 19.232020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.238352 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 19.248328 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 19.249984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.270259 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.287997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.320263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.338030 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.370299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.388008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.420347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.430270 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 19.438020 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.470254 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.479995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 19.482003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.488357 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 19.498322 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 19.499984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.520292 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.538012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.570255 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.588012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.620296 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.637985 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.670256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.680275 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 19.687994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.720277 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.729998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 19.732000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.738385 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 19.748302 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 19.749983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.770250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.788024 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.820250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.837999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.870243 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.887996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.920337 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.930310 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 19.937999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 19.970263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 19.980036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 19.981992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 19.988347 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 19.998300 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 20.000008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.020284 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.038001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.070280 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.088008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.120290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.137994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.170246 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.180277 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 20.188006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.220235 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.230004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 20.232003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.238321 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 20.248308 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 20.249981 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.270277 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.288027 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.320271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.338001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.370294 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.387999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.420234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.430277 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 20.438000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.470259 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.480020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 20.482002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.488278 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 20.499997 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 20.500000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.520252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.537995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.570243 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.588019 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.620266 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.637994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.670286 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.680282 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 20.688020 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.720264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.730005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 20.732014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.738309 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 20.748286 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 20.749989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.770221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.787996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.820256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.838000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.870257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.887993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.920272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.930233 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 20.938014 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 20.970270 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 20.979994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 20.981998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 20.988268 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 20.998280 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 20.999980 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.020229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.038005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.070271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.087999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.120247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.138025 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.170247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.180225 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 21.187996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.220220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.230026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 21.231986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.238275 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 21.248271 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 21.249983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.270257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.288000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.320216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.338003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.370232 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.387996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.420204 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.430219 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 21.438007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.470226 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.480021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 21.482032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.488301 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 21.498288 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 21.499986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.520268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.537999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.570248 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.588007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.620212 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.638010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.670204 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.680226 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 21.688024 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.720228 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.730015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 21.732011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.738250 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 21.748232 1 1ceb56f4x Rx d 8 02 7B 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 21.750025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.770221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.788003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.820202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.838013 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.870234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.888029 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.920190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.930238 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 21.937997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 21.970237 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 21.980019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 21.981994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 21.988257 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 21.999981 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 21.999982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.020208 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.038040 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.070202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.087993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.120222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.137997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.170237 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.180236 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 22.188020 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.220234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.230019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 22.232008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.239989 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 22.248308 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 22.250031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.270201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.288000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.320208 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.337997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.370203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.387997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.420191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.430206 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 22.438002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.470186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.480006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 22.481989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.488240 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 22.498245 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 22.499991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.520201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.537993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.570198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.588000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.620205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.637997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.670199 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.680186 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 22.688000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.720231 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.729997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 22.731989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.738238 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 22.748214 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 22.749983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.770213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.787996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.820211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.838001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.870186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.887994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.920181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.930192 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 22.938001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 22.970180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 22.979995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 22.982010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 22.988229 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 22.998226 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 22.999987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.020170 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.037999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.070184 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.088006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.120200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.138030 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.170203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.180166 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 23.188007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.220203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.230011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 23.231986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.238226 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 23.248245 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 23.249988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.270160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.288003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.320164 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.337998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.370176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.387996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.420166 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.430210 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 23.438008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.470215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.480025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 23.481995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.488240 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 23.499995 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 23.499997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.520222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.538029 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.570195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.587998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.620187 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.638004 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.670152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.680180 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 23.688026 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.720196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.730026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 23.731997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.738216 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 23.748197 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 23.749986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.770153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.787998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.820196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.838013 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.870194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.888010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.920194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.930179 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 23.937996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 23.970186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 23.980001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 23.982037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 23.988240 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 23.998209 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 23.999990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.020167 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.038008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.070174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.087996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.120186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.138002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.170149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.180168 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 24.187993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.220164 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.229992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 24.232013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.238193 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 24.248209 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 24.249986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.270149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.288000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.320142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.338024 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.370185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.388020 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.420143 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.430143 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 24.438012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.470157 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.480035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 24.482037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.488224 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 24.498221 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 24.499994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.520144 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.537998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.570167 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.588008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.620162 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.638000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.670148 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.680154 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 24.688005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.720156 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.729124 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 24.730114 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.738185 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 24.748172 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 24.750009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.770158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.787994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.820163 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.838025 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.870154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.887998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.920166 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.930147 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 24.938000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 24.970140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 24.979154 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 24.980112 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 24.988234 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 24.999997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 25.000000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.020114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.037997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.070203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.087126 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.120148 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.137993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.170129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.180152 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 25.188021 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.220127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.230061 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 25.232020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.238204 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 25.248192 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 25.249992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.270135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.287997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.320139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.337995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.370135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.387998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.420174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.430121 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 25.437996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.470143 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.479994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 25.482015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.488182 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 25.498169 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 25.499989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.520108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.538000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.570168 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.588008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.620111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.637112 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.670113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.680109 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 25.687113 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.720139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.729111 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 25.730120 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.738188 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 25.750018 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 25.750021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.770149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.787995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.820140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.837127 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.870093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.887119 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.920134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.930155 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 25.937997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 25.970129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 25.979146 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 25.980103 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 25.988174 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 25.998179 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 26.000028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.020114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.037121 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.070133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.087132 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.120106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.137121 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.170094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.180119 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 26.188030 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.220098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.229106 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 26.230122 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.238166 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 26.248235 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 26.250024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.270130 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.287125 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.320116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.338006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.370120 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.387118 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.420117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.430100 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 26.437084 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.470098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.479096 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 26.480093 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.488146 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 26.498202 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 26.499994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.520128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.537110 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.570076 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.587116 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.620153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.637097 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.670089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.680091 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 26.687090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.720075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.729090 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 26.730070 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.738140 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 26.748161 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 26.750000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.770096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.787088 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.820102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.837098 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.870102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.887995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.920095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.930090 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 26.937087 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 26.970077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 26.979101 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 26.980068 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 26.988139 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 26.998142 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 27.000027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.020078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.037070 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.070100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.087094 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.120099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.137104 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.170064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.180078 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 27.187114 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.220090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.229092 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 27.230081 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.238154 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 27.248122 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 27.250000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.270082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.287108 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.320077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.337092 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.370080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.387101 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.420064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.430151 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 27.437071 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.470096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.479084 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 27.480066 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.488118 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 27.498128 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 27.499998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.520075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.537091 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.570076 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.587097 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.620112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.637093 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.670089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.680054 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 27.687996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.720080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.729090 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 27.730070 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.738132 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 27.748122 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 27.750028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.770079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.787119 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.820102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.837094 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.870060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.887092 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.920047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.930080 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 27.937094 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 27.970072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 27.979106 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 27.980055 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 27.988125 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 27.998170 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 28.000021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.020068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.037102 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.070065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.087060 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.120047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.137055 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.170082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.180099 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 28.187051 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.220053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.229096 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 28.230089 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.238093 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 28.248114 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 28.250052 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.270056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.287090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.320061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.337090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.370087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.387058 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.420068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.430046 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 28.437074 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.470047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.479048 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 28.480016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.488102 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 28.498116 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 28.500022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.520070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.537090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.570056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.587055 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.620060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.637041 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.670070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.680060 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 28.687091 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.720069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.729095 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 28.730021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.738090 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 28.748089 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 28.750018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.770042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.787048 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.820026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.837059 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.870049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.887070 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.920050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.930039 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 28.937060 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 28.970024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 28.979047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 28.980023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 28.988165 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 28.998120 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 28.999993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.020048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.037051 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.070023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.087039 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.120055 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.137068 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.170020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.180021 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 29.187076 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.220026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.229039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 29.229998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.238054 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 29.248067 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 29.250030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.270084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.287071 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.320060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.337058 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.370063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.387039 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.420017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.430034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 29.437044 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.470045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.479999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 29.480001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.488119 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 29.498088 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 29.500052 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.520084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.537037 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.570028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.587068 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.620042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.637046 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.670024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.680054 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 29.687024 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.720023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.729021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 29.729985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.738121 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 29.748053 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 29.750004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.770047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.787049 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.820054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.837038 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.870052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.887037 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.919999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.930005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 29.937026 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 29.970023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 29.979019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 29.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 29.988063 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 29.998035 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 30.000018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.020020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.036071 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.070039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.086050 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.120037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.136065 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.170035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.180048 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 30.186023 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.220078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.229005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 30.230010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.238057 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 30.248050 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 30.250021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.270045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.286001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.320024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.336006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.370013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.386043 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.420005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.430025 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 30.436021 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.469986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.479048 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 30.480020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.488081 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 30.498035 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 30.499991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.520027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.536025 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.570026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.586013 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.620054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.636011 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.670043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.680020 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 30.686016 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.720018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.729018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 30.729987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.738023 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 30.748037 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 30.750019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.769995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.786003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.819995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.836005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.870001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.885998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.919996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.930001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 30.935993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 30.970024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 30.978985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 30.980027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 30.988082 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 30.998042 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 30.999988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.020003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.036001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.069997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.086019 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.120006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.136018 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.170014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.179981 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 31.185999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.220048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.229022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 31.230003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.238017 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 31.248041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 31.250022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.270029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.286038 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.319994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.336110 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.369995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.386002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.420001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.430003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 31.436052 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.470005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.478969 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 31.479991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.488037 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 31.498040 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 31.500012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.520003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.536003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.569998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.586016 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.620005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.636000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.670004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.680026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 31.686007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.720040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.728971 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 31.730019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.738016 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 31.748027 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 31.749998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.770011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.786002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.820003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.836000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.870007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.886029 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.920026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.930016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 31.936000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 31.969998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 31.978990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 31.980038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 31.988042 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 31.998053 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 31.999997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.020005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.036019 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.070047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.086034 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.119997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.135993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.169993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.180029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 32.186001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.220023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.228962 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 32.230013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.238011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 32.248021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 32.249989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.270003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.285995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.319996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.335994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.370014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.385996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.419998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.430014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 32.435999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.470008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.479010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 32.479996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.488031 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 32.498010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 32.500020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.518978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.536021 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.568980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.585993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.619998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.636003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.670032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.679992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 32.686000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.720049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.728974 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 32.729989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.737998 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 32.748011 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 32.750009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.770000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.785994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.818963 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.836000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.870006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.886003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.919993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.930045 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 32.936000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 32.969996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 32.978939 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 32.980019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 32.988043 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 32.998021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 33.000000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.018958 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.036018 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.068990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.086005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.118950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.135989 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.168991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.180009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 33.185994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.218969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.228938 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 33.229983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.238035 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 33.248035 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 33.250016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.268946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.286004 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.318979 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.335997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.368930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.386006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.418979 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.430016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 33.435994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.468964 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.478960 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 33.480006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.487993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 33.498015 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 33.500000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.518954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.535995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.568973 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.586038 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.618905 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.636000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.668952 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.680017 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 33.685992 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.718947 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.728963 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 33.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.738013 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 33.747997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 33.750009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.768933 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.785998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.818952 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.835998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.868962 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.886024 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.918941 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.929997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 33.936036 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 33.968920 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 33.978935 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 33.980034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 33.988002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 33.998013 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 33.999992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.018946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.035996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.068939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.086010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.118898 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.136033 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.168936 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.180026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 34.185997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.218923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.228898 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 34.229993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.237997 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 34.248004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 34.250003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.268903 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.286012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.318935 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.336060 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.368950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.386014 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.418951 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.430030 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 34.435990 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.468911 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.478937 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 34.479983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.488004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 34.498000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 34.500002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.518915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.535996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.568907 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.585991 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.618946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.636009 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.668942 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.680008 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 34.686019 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.718919 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.728917 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 34.730006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.738020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 34.748019 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 34.749989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.768943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.786010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.818885 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.836010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.868886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.886023 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.918890 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.929981 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 34.936012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 34.968933 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 34.978900 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 34.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 34.987993 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 34.998011 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 34.999990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.018892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.036010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.068891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.085993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.118887 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.136033 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.168930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.180036 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 35.185987 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.218893 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.228935 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 35.230011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.238020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 35.248000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 35.249987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.268904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.286013 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.318868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.336003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.368900 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.386006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.418890 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.429981 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 35.436005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.468891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.478881 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 35.480012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.487997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 35.497999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 35.500019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.518896 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.536008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.568893 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.585993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.618885 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.636002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.668892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.680000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 35.686010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.718867 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.728893 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 35.730016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.737998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 35.748047 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 35.749986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.768893 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.786007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.818869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.836009 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.868904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.886012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.918880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.930003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 35.935990 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 35.968876 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 35.978893 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 35.979986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 35.987996 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 35.998007 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 36.000020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.018879 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.036002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.068881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.085996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.118856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.135998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.168871 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.179998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 36.185994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.218848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.228885 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 36.229992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.237994 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 36.248008 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 36.250030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.268861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.286029 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.318861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.335997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.368871 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.386010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.418849 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.429992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 36.436014 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.468866 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.478869 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 36.480036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.488000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 36.498029 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 36.500036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.518872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.535999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.568850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.586006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.618854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.635998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.668873 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.679997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 36.686016 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.718838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.728841 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 36.730051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.738015 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 36.748012 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 36.750033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.768851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.786005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.820007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.836008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.868845 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.886007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.918848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.930028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 36.936006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 36.970021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 36.978832 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 36.980017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 36.987987 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 36.997996 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 37.000004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.018839 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.036050 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.068865 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.086005 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.120000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.135992 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.168832 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.180034 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 37.186031 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.218884 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.228825 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 37.229991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.238011 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 37.248041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 37.249988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.269998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.285994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.318859 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.335984 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.368827 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.385994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.420022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.430033 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 37.436007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.468853 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.478854 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 37.480004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.488004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 37.497998 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 37.500001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.518812 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.535996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.569995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.586000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.618850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.636010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.668862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.680032 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 37.686002 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.720004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.728821 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 37.729980 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.738013 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 37.747992 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 37.750008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.768838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.786036 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.818838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.836010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.869997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.886015 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.918848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.930035 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 37.936026 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 37.968835 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 37.978850 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 37.979980 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 37.988022 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 37.998000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 37.999990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.020024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.035996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.068816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.086000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.118795 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.136007 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.169999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.180029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 38.185998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.218823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.228831 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 38.230000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.238003 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 38.247993 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 38.250049 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.268838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.285999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.318793 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.336027 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.368794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.385992 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.418811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.430016 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 38.436010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.468824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.478801 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 38.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.488021 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 38.497991 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 38.499982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.518801 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.536018 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.568804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.586004 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.618850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.636012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.668798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.680016 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 38.686022 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.718856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.728807 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 38.729997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.737995 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 38.748025 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 38.749996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.768853 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.786009 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.818828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.835993 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.868798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.886001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.918826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.930028 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 38.935994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 38.968792 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 38.978821 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 38.980008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 38.988006 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 38.998002 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 38.999999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.018781 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.035998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.068819 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.086001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.118863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.135995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.168813 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.180023 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 39.185986 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.218821 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.228800 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 39.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.238000 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 39.248004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 39.250025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.268794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.286001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.318782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.336012 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.368823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.386006 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.418768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.430035 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 39.435995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.468828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.478805 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 39.479990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.488010 1 1ceb56f4x Rx d 8 01 26 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 39.498008 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 39.499995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.518817 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.535995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.568802 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.585997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.618773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.636005 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.668775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.680026 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 39.685995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.718799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.728796 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 39.729985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.738000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 39.748024 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 39.750034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.768772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.786011 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.818824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.835996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.868801 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.885999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.918782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.930012 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 39.936001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 39.968805 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 39.978789 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 39.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 39.987990 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 39.998031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 40.000021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.018829 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.035996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.068788 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.086020 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.118781 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.135995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.168771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.180008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 40.186000 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.218777 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.228767 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 40.230010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.238007 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 40.248006 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 40.250024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.268756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.286008 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.318763 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.336001 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.368773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.386005 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.418779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.430022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 40.436016 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.468787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.478793 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 40.480007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.488007 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 40.497998 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 40.499987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.518803 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.535996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.568740 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.585994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.618748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.635994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.668756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.680001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 40.685994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.718779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.728797 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 40.730018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.738004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 40.748028 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 40.748031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.768768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.785995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.818723 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.836014 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.868753 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.886011 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.918798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.930001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 40.935999 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 40.968735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 40.978775 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 40.979993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 40.988030 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 40.998021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 40.999999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.018734 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.035997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.068731 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.086015 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.118773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.135996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.168750 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.179996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 41.186028 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.218765 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.228775 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 41.229999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.238008 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 41.248010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 41.250040 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.268734 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.286031 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.318726 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.335993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.368738 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.386027 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.418735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.430000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 41.435997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.468735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.478756 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 41.479991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.488001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 41.498016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 41.499992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.518745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.536001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.568716 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.586015 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.618742 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.635994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.668765 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.679995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 41.685996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.718713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.728718 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 41.729987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.738007 1 1ceb56f4x Rx d 8 01 12 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 41.748003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 41.748006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.768727 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.785997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.818717 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.836006 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.868686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.885991 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.918725 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.930000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 41.935997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 41.968765 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 41.978710 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 41.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 41.988015 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 41.998000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 41.999981 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.018716 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.036001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.068704 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.086006 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.118720 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.136001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.168734 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.180025 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 42.186004 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.218718 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.228736 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 42.229992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.238030 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 42.248012 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 42.248015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.268701 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.285998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.318729 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.335996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.368722 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.386007 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.418735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.430001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 42.435997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.468735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.478716 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 42.480001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.488012 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 42.498012 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 42.499989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.518713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.536000 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.568759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.586029 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.618760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.636021 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.668708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.680010 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 42.685997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.718713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.728714 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 42.730002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.738005 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 42.748043 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 42.749996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.768705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.785995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.818708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.836002 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.868685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.885995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.918681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.930021 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 42.935993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 42.968748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 42.978711 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 42.980000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 42.988002 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 42.998004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 43.000002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.018724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.036024 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.068719 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.085999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.118695 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.135996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.168664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.179995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 43.185999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.218682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.228738 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 43.229985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.237999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 43.248004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 43.248007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.268706 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.286014 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.318670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.336024 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.368708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.385996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.418691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.430016 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 43.435998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.468684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.478703 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 43.480006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.488000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 43.497999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 43.500027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.518676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.535993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.568708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.586015 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.618713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.636006 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.668684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.680003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 43.685996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.718675 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.728687 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 43.730006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.738023 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 43.748034 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 43.748036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.768673 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.786009 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.818689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.836025 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.868697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.885999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.918671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.930002 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 43.935993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 43.968707 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 43.978679 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 43.979994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 43.988025 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 43.998003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 44.000038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.018683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.036000 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.068657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.085998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.118713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.136003 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.168686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.179993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 44.185996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.218671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.228658 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 44.230021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.238001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 44.248034 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 44.248037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.268686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.285997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.318664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.335999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.368686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.385997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.418685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.430006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 44.436025 1 1812f456x Rx d 8 12 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.468687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.478652 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 44.479990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.488027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 44.497999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 44.500025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.518679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.536000 1 1812f456x Rx d 8 12 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.568653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.585997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.618666 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.636002 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.668652 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.680015 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 44.685994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.718638 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.728659 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 44.729989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.738008 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 44.748035 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 44.748036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.768645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.785995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.818638 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.835999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.868662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.885998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.918669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.930012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 44.935997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 44.968658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 44.978710 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 44.979987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 44.988013 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 44.998006 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 45.000054 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.018666 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.036003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.068658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.086000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.118669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.135992 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.168691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.180000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 45.185997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.218700 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.228653 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 45.230012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.237998 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 45.248013 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 45.248015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.268649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.285998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.318680 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.336007 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.368668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.385996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.418674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.430026 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 45.435996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.468663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.478631 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 45.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.488016 1 1ceb56f4x Rx d 8 01 17 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 45.497999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 45.500046 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.518622 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.535996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.568644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.585998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.618629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.635996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.668637 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.678641 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 45.685995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.718627 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.728647 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 45.729994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.738033 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 45.748028 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 45.748031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.768668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.786007 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.818622 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.835993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.868617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.886000 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.918656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.930022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 45.936014 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 45.968647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 45.978618 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 45.979995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 45.988042 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 45.998038 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 46.000018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.018612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.036026 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.068642 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.085998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.118608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.135997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.168635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.178650 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 46.186026 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.218616 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.228621 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 46.229996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.238023 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 46.248026 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 46.248028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.268667 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.285999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.318591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.336029 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.368624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.385997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.418628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.428656 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 46.435991 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.468635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.478690 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 46.480002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.488020 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 46.498001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 46.500018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.518618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.535996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.568598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.585996 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.618611 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.636001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.668635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.678624 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 46.685997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.718635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.728604 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 46.729987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.737994 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 46.747999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 46.748001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.768604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.785995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.818640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.835998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.868595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.886005 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.918612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.928628 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 46.935994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 46.968592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 46.978628 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 46.980001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 46.988026 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 46.998052 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 47.000019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.018628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.036002 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.068607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.085995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.118639 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.135995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.168619 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.178605 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 47.185997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.218601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.228600 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 47.229986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.238018 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 47.248036 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 47.248039 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.250036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 47.250038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.258635 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 47.268020 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 47.268022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.269987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.285995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.318626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.335994 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.368567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.385997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.418567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.428599 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 47.436000 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.468592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.478595 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 47.479988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.487998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 80 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 47.498005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 47.499991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.518591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.535998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.568608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.585995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.618594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.636001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.668600 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.678578 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 47.685998 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.718573 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.728606 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 47.730026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.738009 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 47.748007 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 47.748009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.768608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.785994 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.818585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.835997 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.868605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.885999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.918575 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.928591 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 47.936001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 47.968576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 47.978589 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 47.979994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 47.988026 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 47.998000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 48.000008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.018570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.036000 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.068598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.085995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.118579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.136004 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.168589 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.178606 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 48.186001 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.218589 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.228611 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 48.229998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.238030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 48.248016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 48.248019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.268593 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.286014 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.318590 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.335998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.368573 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.385998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.418573 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.428590 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 48.436005 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.468578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.478580 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 48.479992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.488010 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 48.497998 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 48.498001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.518542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.536013 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.568575 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.585995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.618575 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.636026 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.668555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.678566 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 48.686010 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.718596 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.728562 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 48.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.738042 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 48.747979 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 48.747980 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.768563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.785996 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.818542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.835997 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.868515 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.885995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.918580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.928548 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 48.935995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 48.968568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 48.978547 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 48.979992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 48.988015 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 48.998013 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 48.999997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.018552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.036003 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.068557 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.086004 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.118576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.134590 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.168570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.178532 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 49.184571 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.218563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.228531 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 49.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.237997 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 49.247988 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 49.247989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.268542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.284553 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.318561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.334567 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.368537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.384601 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.418559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.428536 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 49.434538 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.468530 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.478540 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 49.480013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.488018 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 49.498010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 49.499993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.518552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.534558 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.568537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.584549 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.618574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.634543 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.668545 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.678554 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 49.684573 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.718555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.728552 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 49.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.737996 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 49.748007 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 49.748010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.768529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.784539 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.818568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.834595 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.868556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.884548 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.918546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.928537 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 49.934587 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 49.968564 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 49.978523 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 49.980009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 49.988004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 49.998014 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 49.998016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.018551 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.034536 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.068520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.084566 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.118558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.134565 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.168545 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.178523 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 50.184539 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.218559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.228536 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 50.229994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.238007 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 50.248023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 50.248026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.268585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.284545 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.318558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.334537 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.368540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.384546 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.418543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.428524 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 50.434533 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.468530 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.478637 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 50.480008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.487997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 50.498001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 50.499999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.518554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.534532 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.568568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.584565 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.618560 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.634554 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.668514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.678540 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 50.684550 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.718552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.728551 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 50.730025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.738012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 50.747995 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 50.747997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.768540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.784520 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.818535 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.834539 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.868540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.884519 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.918570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.928516 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 50.934540 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 50.968593 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 50.978539 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 50.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 50.988008 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 50.997991 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 50.997992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.018590 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.034530 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.068549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.084538 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.118557 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.134534 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.168549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.178534 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 51.184536 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.218591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.228575 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 51.229985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.238035 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 51.248016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 51.248017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.268537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.284539 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.318537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.334561 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.368553 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.384541 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.418540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.428537 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 51.434554 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.468537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.478503 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 51.479994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.488027 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 51.498016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 51.498019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.518538 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.534545 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.568583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.584547 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.618524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.634538 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.668535 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.678531 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 51.684540 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.718549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.728517 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 51.729989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.737997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 51.748015 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 51.748018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.768565 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.784535 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.818557 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.834553 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.868521 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.884542 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.918544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.928550 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 51.934550 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 51.968570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 51.978567 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 51.979998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 51.988024 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 51.998016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 51.998018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.018519 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.034574 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.068534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.084536 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.118532 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.134532 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.168567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.178556 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 52.184538 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.218559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.228545 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 52.229995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.238037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 52.248001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 52.248004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.268527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.284541 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.318561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.334535 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.368554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.384540 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.418527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.428581 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 52.434553 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.468554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.478539 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 52.480002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.488035 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 52.498004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 52.498007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.518547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.534531 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.568518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.584543 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.618447 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.634543 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.668479 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.678459 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 52.684585 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.718500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.728464 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 52.730013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.738028 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 52.748010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 52.748012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.768492 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.784504 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.818498 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.834465 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.868461 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.884477 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.918512 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.928536 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 52.934460 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 52.968467 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 52.978462 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 52.979984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 52.988000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 52.998005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 52.998007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.018462 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.034459 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.068481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.084495 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.118460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.134469 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.168458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.178469 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 53.184488 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.218469 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.228449 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 53.229996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.238019 1 1ceb56f4x Rx d 8 01 26 11 A2 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 53.248003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 53.248006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.268479 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.284466 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.318442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.334462 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.368443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.384457 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.418457 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.428432 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 53.434449 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.468432 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.478482 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 53.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.488009 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 53.498035 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 53.498037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.518481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.534497 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.568419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.584449 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.618481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.634448 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.668422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.678443 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 53.684437 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.718465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.728429 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 53.730005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.738009 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 53.748026 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 53.748028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.768455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.784477 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.818446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.834450 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.868423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.884444 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.918413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.928427 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 53.934437 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 53.968438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 53.978441 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 53.979999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 53.988055 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 53.998015 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 53.998017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.018430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.034493 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.068419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.084424 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.118417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.134410 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.168425 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.178410 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 54.184441 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.218432 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.228441 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 54.229996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.238015 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 54.248001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 54.248004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.268429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.284421 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.318419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.334469 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.368416 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.384421 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.418449 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.428431 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 54.434435 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.468450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.478432 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 54.480031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.487997 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 54.498031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 54.498033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.518424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.534464 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.568420 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.584439 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.618440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.634429 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.668415 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.678408 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 54.684428 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.718418 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.728453 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 54.730003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.738000 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 54.747995 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 54.747997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.768393 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.784436 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.818396 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.834430 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.868413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.884411 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.918441 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.928413 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 54.934424 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 54.968417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 54.978448 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 54.979992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 54.987985 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 54.998015 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 54.998018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.018417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.034420 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.068430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.084396 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.118416 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.134401 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.168414 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.178462 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 55.184414 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.218396 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.228413 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 55.229988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.238025 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 55.248021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 55.248026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.268409 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.284414 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.318418 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.334472 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.368429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.384402 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.418429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.428410 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 55.434431 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.468410 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.478423 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 55.479996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.488010 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 55.498002 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 55.500018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.518440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.534409 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.568436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.584411 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.618415 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.634414 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.668436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.678399 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 55.684410 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.718378 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.728419 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 55.730001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.738026 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 55.747999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 55.748001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.768423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.784409 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.818395 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.834439 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.868424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.884439 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.918438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.928391 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 55.934446 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 55.968420 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 55.978423 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 55.979988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 55.988022 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 55.998031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 56.000009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.018390 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.034405 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.068421 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.084443 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.118417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.134417 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.168411 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.178381 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 56.184412 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.218427 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.228418 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 56.229999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.238041 1 1ceb56f4x Rx d 8 01 30 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 56.248041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 56.248043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.268412 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.284432 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.318427 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.334408 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.368434 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.384427 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.418393 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.430020 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 56.434430 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.468405 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.478455 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 56.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.488000 1 1ceb56f4x Rx d 8 01 35 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 56.497981 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 56.497982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.518442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.534427 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.568404 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.584428 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.618410 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.634440 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.668424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.678375 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 56.684408 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.718426 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.728424 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 56.730010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.738009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 56.748017 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 56.748020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.768431 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.784425 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.818413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.834426 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.868411 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.884437 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.918409 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.928409 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 56.934438 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 56.968424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 56.978410 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 56.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 56.988019 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 56.998023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 56.998025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.018424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.034398 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.068383 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.084424 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.118406 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.134431 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.168420 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.178398 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 57.184406 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.218437 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.228397 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 57.230043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.237985 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 57.248011 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 57.248014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.268415 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.284399 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.318384 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.334401 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.368423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.384401 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.418446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.428440 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 57.434435 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.468407 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.478393 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 57.479986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.487995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 57.498000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 57.499999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.518403 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.534431 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.568405 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.584439 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.618359 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.634424 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.668364 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.678409 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 57.684458 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.718409 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.728434 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 57.730031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.737999 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 57.747999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 57.748001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.768347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.784375 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.818397 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.834408 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.868323 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.884347 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.918353 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.928400 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 57.934354 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 57.968331 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 57.978351 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 57.980036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 57.988022 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 57.998001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 57.998004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.018317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.034341 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.068367 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.084345 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.118334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.134454 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.168306 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.178308 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 58.184329 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.218333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.228393 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 58.229991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.238000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 58.247997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 58.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.268315 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.284334 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.318338 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.334331 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.368335 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.384351 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.418346 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.428320 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 58.434333 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.468294 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.478335 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 58.480008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.488018 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 58.497996 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 58.497998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.518320 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.534331 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.568369 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.584321 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.618300 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.634343 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.668303 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.678321 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 58.684317 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.718322 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.728324 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 58.730011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.737997 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 58.748004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 58.748007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.768309 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.784299 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.818290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.834321 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.868278 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.884350 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.918313 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.928302 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 58.934333 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 58.968288 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 58.978340 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 58.979996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 58.988010 1 1ceb56f4x Rx d 8 01 30 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 58.998004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 58.998007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.018334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.034329 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.068299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.084295 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.118303 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.134333 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.168322 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.178300 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 59.184327 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.218291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.228415 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 59.228417 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.237997 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 59.248005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 59.248007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.268294 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.284324 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.318303 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.334296 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.368307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.384325 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.418352 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.428315 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 59.434305 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.468293 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.478298 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 59.479988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.487989 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 59.498002 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 59.498004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.518276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.534314 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.568312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.584329 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.618316 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.634329 1 1812f456x Rx d 8 08 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.668312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.678292 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 59.684306 1 1812f456x Rx d 8 08 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.718268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.728317 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 59.729983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.738011 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 59.748014 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 59.748017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.768314 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.784321 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.818290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.834307 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.868287 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.884329 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.918278 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.928254 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 59.934279 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 59.968264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 59.978309 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 59.980029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 59.988027 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 59.997997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 59.997999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.018308 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.034285 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.068287 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.084299 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.118291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.134307 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.168280 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.178258 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 60.184285 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.218284 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.228298 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 60.230036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.238002 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 60.248033 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 60.248036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.268285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.284294 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.318290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.334291 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.368312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.384303 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.418252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.428264 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 60.434279 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.468290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.478260 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 60.480013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.487999 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 60.498016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 60.500015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.518290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.534293 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.568252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.584280 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.618285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.634257 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.668263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.678257 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 60.684270 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.718273 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.728262 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 60.729991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.738002 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 60.748016 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 60.748019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.768275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.784245 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.818256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.834278 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.868256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.884262 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.918276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.928240 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 60.934286 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 60.968250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 60.978241 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 60.980035 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 60.988009 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 60.998041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 60.998043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.018261 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.034308 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.068298 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.084249 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.118268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.134259 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.168270 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.178259 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 61.184276 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.218242 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.228307 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 61.230002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.238015 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 61.248000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 61.250023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.268250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.284249 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.318250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.334274 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.368237 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.384275 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.418253 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.428250 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 61.434256 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.468267 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.478265 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 61.479995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.488008 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 61.498005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 61.498007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.518264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.534281 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.568291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.584279 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.618254 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.634244 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.668255 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.678246 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 61.684267 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.718252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.728224 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 61.729993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.737998 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 61.748027 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 61.748029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.768267 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.784254 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.818231 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.834244 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.868269 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.884254 1 1812f456x Rx d 8 08 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.918271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.928232 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 61.934257 1 1812f456x Rx d 8 08 11 91 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 61.968246 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 61.978230 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 61.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 61.987989 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 61.998004 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 62.000012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.018240 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.034236 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.068264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.084252 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.118220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.134225 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.168240 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.178207 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 62.184240 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.218252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.228220 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 62.229995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.237993 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 62.248002 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 62.248004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.268230 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.284256 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.318230 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.334231 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.368227 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.384228 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.418229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.428232 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 62.434220 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.468213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.478197 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 62.479990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.488017 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 62.498003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 62.498005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.518237 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.534214 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.568226 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.584266 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.618221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.634255 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.668220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.678212 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 62.684217 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.718209 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.728278 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 62.729991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.738037 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 62.747996 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 62.747998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.768254 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.784246 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.818222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.834227 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.868242 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.884222 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.918232 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.928198 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 62.934216 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 62.968232 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 62.978214 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 62.979987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 62.988002 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 62.998031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 62.998033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.018215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.034233 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.068200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.084284 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.118209 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.134235 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.168243 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.178190 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 63.184221 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.218222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.228194 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 63.230002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.238007 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 63.247995 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 63.247997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.268220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.284238 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.318217 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.334211 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.368264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.384199 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.418240 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.428176 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 63.434232 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.468205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.478196 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 63.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.488035 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 63.498036 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 63.498038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.518195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.534210 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.568221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.584193 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.618180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.634224 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.668202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.678180 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 63.684199 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.718182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.728282 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 63.728283 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.738006 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 63.748023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 63.748025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.768183 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.784183 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.818208 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.834207 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.868214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.884188 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.918190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.928176 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 63.934190 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 63.968178 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 63.978212 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 63.979997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 63.988008 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 63.998031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 63.998035 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.018184 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.034222 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.068180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.084173 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.118209 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.134206 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.168189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.178192 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 64.184230 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.218237 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.228192 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 64.230009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.238001 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 64.248060 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 64.248062 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.268165 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.284179 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.318171 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.334172 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.368160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.384179 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.418226 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.428174 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 64.434183 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.468199 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.478199 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 64.480009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.488021 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 64.498019 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 64.498027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.518172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.534168 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.568214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.584193 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.618154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.634184 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.668194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.678188 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 64.684209 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.718194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.728164 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 64.730025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.738006 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 64.748001 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 64.748003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.768140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.784171 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.818203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.834179 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.868176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.884183 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.918201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.928148 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 64.934175 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 64.968181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 64.978278 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 64.978280 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 64.987999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 64.998037 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 64.998039 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.018171 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.034199 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.068180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.084163 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.118190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.134176 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.168138 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.178196 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 65.184166 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.218164 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.228266 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 65.228268 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.238011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 65.248019 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 65.248021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.268140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.284176 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.318175 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.334160 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.368180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.384189 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.418150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.428144 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 65.434178 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.468182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.478128 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 65.479988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.487998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 65.498002 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 65.498004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.518166 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.534161 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.568185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.584179 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.618158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.634147 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.668183 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.678182 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 65.684212 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.718122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.728166 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 65.729990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.738020 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 65.748058 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 65.748063 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.768176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.784167 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.818138 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.834133 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.868165 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.884175 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.918142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.928169 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 65.934162 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 65.968122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 65.978280 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 65.978282 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 65.987999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 65.998028 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 65.998030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.018136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.034146 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.068135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.084138 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.118131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.134139 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.168151 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.178133 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 66.184150 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.218156 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.228174 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 66.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.238024 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 66.248007 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 66.248011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.268129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.284167 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.318101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.334126 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.368128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.384134 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.418118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.428112 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 66.434134 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.468112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.478220 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 66.478221 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.487996 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 66.497993 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 66.497995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.518145 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.534131 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.568116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.584121 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.618110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.634142 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.668131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.678106 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 66.684137 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.718121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.728138 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 66.730008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.738004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 66.748023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 66.748025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.768127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.784122 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.818137 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.834142 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.868136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.884112 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.918129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.928121 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 66.934127 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 66.968127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 66.978082 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 66.979990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 66.987992 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 66.998023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 66.998026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.018116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.034124 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.068102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.084116 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.118151 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.134137 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.168094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.178118 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 67.184098 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.218100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.228142 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 67.229996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.238028 1 1ceb56f4x Rx d 8 01 0D 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 67.247998 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 67.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.268080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.284141 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.318125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.334126 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.368103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.384134 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.418111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.428113 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 67.434098 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.468122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.478199 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 67.478201 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.487999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 67.498003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 67.498006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.518115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.534101 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.568088 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.584093 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.618130 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.634124 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.668099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.678102 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 67.684090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.718081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.728065 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 67.730029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.737998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 67.747987 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 67.747989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.768096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.784097 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.818102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.834102 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.868115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.884113 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.918086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.928089 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 67.934114 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 67.968083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 67.978175 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 67.978177 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 67.988027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 67.998039 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 67.998041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.018074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.034108 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.068113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.084076 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.118082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.134110 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.168128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.178083 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 68.184081 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.218096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.228156 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 68.228158 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.238027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 68.248005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 68.248007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.268067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.283104 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.318121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.333092 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.368096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.383090 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.418066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.428085 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 68.433090 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.468083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.478052 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 68.479996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.487111 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 68.498011 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 68.498013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.518083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.533129 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.568056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.583101 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.618053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.633074 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.668065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.678089 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 68.683097 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.718092 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.728192 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 68.728194 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.737123 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 68.748039 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 68.748041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.768044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.783078 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.818059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.833096 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.868052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.883062 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.918046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.928064 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 68.933074 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 68.968040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 68.978166 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 68.978168 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 68.987104 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 68.998003 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 68.998005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.018081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.033116 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.068036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.083080 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.118058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.133071 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.168060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.178031 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 69.183048 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.218052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.228032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 69.230027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.237127 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 69.248013 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 69.248015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.268047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.283077 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.318062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.333081 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.368048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.383062 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.418062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.428039 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 69.433079 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.468046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.478176 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 69.478177 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.487099 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 69.498010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 69.498013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.518034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.533042 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.568053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.583078 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.618038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.633079 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.668029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.678038 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 69.683079 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.718052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.728025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 69.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.737114 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 69.748010 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 69.748014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.768071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.783082 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.818056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.833047 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.868071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.883067 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.918044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.928017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 69.933073 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 69.968024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 69.978042 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 69.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 69.987107 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 69.998030 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 69.998032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.018071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.033082 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.068036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.083073 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.118021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.133083 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.168019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.178042 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 70.183075 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.218062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.228150 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 70.228152 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.237107 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 70.248012 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 70.248015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.268017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.283037 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.318033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.333028 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.368018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.383025 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.418053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.428043 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 70.433050 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.468026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.478151 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 70.478153 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.487091 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 70.498020 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 70.498022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.518057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.533028 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.568027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.583031 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.618008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.633023 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.668029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.678008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 70.683022 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.718024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.728034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 70.729993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.737075 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 70.747998 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 70.748000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.768003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.783024 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.818023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.833030 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.868016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.883027 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.918014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.928081 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 70.933045 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 70.968025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 70.978130 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 70.978131 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 70.987099 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 70.998006 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 70.998008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.018004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.033011 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.068034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.083066 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.118012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.133061 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.168113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.177988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 71.183011 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.217992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.228049 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 71.230005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.237096 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 71.247997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 71.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.268044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.283008 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.318018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.333030 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.368019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.383025 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.418004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.428009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 71.433030 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.468064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.477990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 71.480003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.487042 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 71.498000 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 71.498003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.517993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.532999 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.568044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.583051 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.618029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.633019 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.668008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.678036 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 71.683014 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.717998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.728106 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 71.728108 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.737066 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 71.748015 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 71.748017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.768006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.783014 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.818005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.833053 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.867988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.883018 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.918008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.928040 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 71.933025 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 71.968001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 71.978075 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 71.978076 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 71.987054 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 71.997172 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 71.997175 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.018028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.032973 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.067997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.082998 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.118014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.133022 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.167998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.178019 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 72.183020 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.218000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.228078 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 72.228080 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.237033 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 72.247021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 72.248050 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.268030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.283004 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.317995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.332982 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.368004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.382989 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.417995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.428007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 72.433003 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.467994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.478091 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 72.478093 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.487011 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 72.498021 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 72.498023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.517994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.532983 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.567996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.583009 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.618002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.633008 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.668000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.678000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 72.683026 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.718008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.727986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 72.729990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.737068 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 72.747127 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 72.747129 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.768003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.783023 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.818070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.832990 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.867992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.882980 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.917997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.927994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 72.932982 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 72.968007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 72.978028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 72.978030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 72.987032 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 72.997140 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 72.997143 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.018003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.032967 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.068083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.082995 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.117997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.132980 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.167997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.178014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 73.182975 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.217996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.227992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 73.230003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.236989 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 73.247031 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 73.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.267997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.282990 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.318003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.333015 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.367992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.382960 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.418036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.427990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 73.432993 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.467997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.478015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 73.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.486996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 73.497102 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 73.497104 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.517998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.532968 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.567996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.582949 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.617996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.632973 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.668002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.677994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 73.682952 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.717996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.728099 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 73.728101 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.736994 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 73.747074 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 73.747076 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.768001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.782952 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.817999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.832995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.867999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.882974 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.917997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.928061 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 73.932968 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 73.968001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 73.978047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 73.978051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 73.986995 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 73.997090 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 73.997096 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.017996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.032965 1 1812f456x Rx d 8 08 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.068003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.082955 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.118056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.132942 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.168001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.177990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 74.182945 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.217997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.228041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 74.228043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.236967 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 74.247080 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 74.247082 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.268020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.282950 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.318030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.332934 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.368000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.382926 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.417990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.428027 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 74.432968 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.468031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.478025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 74.478031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.487017 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 74.497143 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 74.497146 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.518001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.532946 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.567998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.582959 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.617995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.632927 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.667999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.677997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 74.682928 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.718000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.727991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 74.729997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.737003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 74.747075 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 74.747077 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.768001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.782928 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.818005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.832929 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.868003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.882929 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.918001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.927992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 74.932943 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 74.968008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 74.978025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 74.980043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 74.986993 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 74.997078 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 74.997080 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.018020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.032929 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.068022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.082995 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.118024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.132947 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.167999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.177991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 75.182917 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.217997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.228014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 75.228016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.236956 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 75.247117 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 75.247119 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.267998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.282909 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.317997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.332931 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.368001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.382943 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.418028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.427987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 75.432967 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.467996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.477991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 75.477992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.486933 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 75.497057 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 75.497059 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.518008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.532958 1 1812f456x Rx d 8 12 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.567997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.582893 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.618034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.632910 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.668026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.678918 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 75.682950 1 1812f456x Rx d 8 1C 11 92 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.717997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.728003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 75.729987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.736944 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 75.747041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 75.747043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.768000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.782915 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.817996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.832928 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.868007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.882901 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.918006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.927989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 75.932938 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 75.967997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 75.978018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 75.978020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 75.986934 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 75.996951 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 75.997996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.017996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.032932 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.067995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.082919 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.118004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.132932 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.168001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.177985 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 76.182918 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.217997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.227983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 76.227984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.236956 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 76.247023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 76.247025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.267996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.282943 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.318032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.332939 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.368003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.382886 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.418041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.428003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 76.432925 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.467994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.478013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 76.480005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.486966 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 76.496999 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 76.497001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.518033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.532921 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.567998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.582897 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.617999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.632935 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.668035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.678003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 76.682941 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.717994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.728052 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 76.728054 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.736912 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 76.747049 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 76.747051 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.767998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.782921 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.817987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.832877 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.868012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.882914 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.918001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.927990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 76.932914 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 76.968004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 76.977999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 76.978001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 76.986910 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 76.997041 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 76.997043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.017996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.032864 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.067995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.082928 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.117994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.132855 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.168031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.177990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 77.182888 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.217992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.227991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 77.227992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.236908 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 77.247030 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 77.247032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.267998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.282897 1 1812f456x Rx d 8 1C 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.318029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.332950 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.367996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.382864 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.418008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.428013 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 77.432914 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.468000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.477993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 77.477994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.486932 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 77.496956 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 77.498029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.518016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.532927 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.568002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.582853 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.618009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.632893 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.667999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.678001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 77.682847 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.717999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.728032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 77.728034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.736918 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 77.747023 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 77.747029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.767997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.782872 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.817996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.832885 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.867997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.882856 1 1812f456x Rx d 8 12 11 93 0D 33 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.918009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.928016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 77.932887 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 77.967997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 77.977989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 77.980037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 77.986897 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 77.997026 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 77.997029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.018004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.032828 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.067989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.082850 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.117992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.132890 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.168000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.177988 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 78.182873 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.218029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.227993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 78.227994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.236883 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 78.246997 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 78.247000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.267998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.282888 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.317994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.332864 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.367996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.382878 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.418001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.428001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 78.432865 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.468000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.477987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 78.477989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.486892 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 78.496966 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 78.496969 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.518030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.532846 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.567995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.582843 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.618044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.632875 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.668036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.678041 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 78.682855 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.718005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.728024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 78.728026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.736873 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 78.747014 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 78.747017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.767991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.782851 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.818001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.832816 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.868024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.882809 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.917994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.927999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 78.932838 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 78.967990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 78.977990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 78.977992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 78.986866 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 78.996886 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 78.997994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.017994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.032822 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.068007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.082843 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.117998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.132837 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.168009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.177992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 79.182874 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.218038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.227996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 79.227997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.236866 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 79.246863 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 79.247992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.267992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.282838 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.318021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.332804 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.367996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.382800 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.417993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.427996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 79.432820 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.468000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.478003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 79.479989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.486869 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 79.496934 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 79.496935 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.517996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.532864 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.568027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.582795 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.618003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.632815 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.668052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.678008 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 79.682828 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.717999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.727995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 79.727997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.736859 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 79.746988 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 79.746991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.768007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.782829 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.818029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.832826 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.867998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.882865 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.918028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.927989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 79.932807 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 79.968001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 79.978010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 79.978014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 79.986844 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 79.997005 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 79.997007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.017995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.032810 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.068004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.082791 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.117997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.132834 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.168000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.177999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 80.182848 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.218013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.227987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 80.227989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.236825 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 80.246952 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 80.246955 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.268010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.282813 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.318026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.332807 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.368009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.382799 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.418001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.427996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 80.432802 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.468003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.477987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 80.477988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.486856 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 80.496836 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 80.498000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.517994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.532849 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.568033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.582834 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.618028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.632802 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.668000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.677996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 80.682769 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.718005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.727999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 80.729990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.736851 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 80.746933 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 80.746936 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.767999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.782804 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.818003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.832815 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.867991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.882802 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.918005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.927990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 80.932797 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 80.967995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 80.977993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 80.977995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 80.986782 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 80.996858 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 80.997989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.018029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.032758 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.068009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.082759 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.118043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.132759 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.168015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.178003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 81.182769 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.218006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.228025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 81.228027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.236835 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 81.246906 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 81.247994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.268000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.282801 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.318014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.332790 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.367997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.382845 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.417995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.427993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 81.432787 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.467998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.478019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 81.478021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.486811 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 81.496953 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 81.496955 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.518039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.532762 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.568039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.582796 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.617986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.632781 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.667991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.677996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 81.682779 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.718027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.728023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 81.728025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.736777 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 81.746909 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 81.746912 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.768020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.782764 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.817997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.832756 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.868011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.882788 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.917996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.927988 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 81.932764 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 81.968056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 81.977989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 81.977990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 81.986793 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 81.996783 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 81.997988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.017994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.032765 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.067998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.082739 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.117996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.132766 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.168010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.177988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 82.182763 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.217995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.227990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 82.227992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.236841 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 82.246902 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 82.246904 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.267996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.282754 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.317996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.332764 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.368002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.382762 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.417997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.428027 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 82.432736 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.467995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.478826 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 82.478827 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.486788 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 82.496932 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 82.496934 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.517995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.532763 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.567995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.582742 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.617994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.632740 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.668012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.677988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 82.682721 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.717990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.727990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 82.727992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.736785 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 82.746911 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 82.746914 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.767993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.782762 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.817986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.832749 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.867997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.882714 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.918003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.927989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 82.932709 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 82.968003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 82.977987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 82.977988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 82.986759 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 82.996794 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 82.998014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.017996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.032720 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.068017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.082767 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.118005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.132727 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.167995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.178021 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 83.182746 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.218003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.227995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 83.230001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.236800 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 83.246861 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 83.246863 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.268008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.282729 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.317996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.332721 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.367995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.382733 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.418035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.428016 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 83.432723 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.467996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.477993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 83.477995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.486735 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 83.496742 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 83.498030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.518005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.532705 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.567999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.582691 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.617999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.632730 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.667994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.677989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 83.682732 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.717998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.728022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 83.728024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.736750 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 83.746889 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 83.746892 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.778043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.782706 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.818000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.832694 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.867996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.882766 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.917999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.928000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 83.932778 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 83.967997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 83.978807 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 83.978809 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 83.986758 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 83.996721 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 83.998000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.018014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.032744 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.067995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.082721 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.118020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.132710 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.167998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.177987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 84.182676 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.218011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.227987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 84.227989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.236722 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 84.246909 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 84.246912 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.268005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.282675 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.317993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.332698 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.367994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.382687 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.417997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.428022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 84.432685 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.467998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.477995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 84.479991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.486758 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 84.496714 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 84.497985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.518000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.532683 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.567997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.582694 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.617998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.632734 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.667991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.677992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 84.682701 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.717990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.728016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 84.730024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.736716 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 84.746847 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 84.746853 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.768009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.782703 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.817995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.832675 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.868005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.882710 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.917992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.927997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 84.932681 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 84.968008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 84.978023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 84.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 84.986717 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 84.996704 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 84.997987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.018008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.032707 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.068040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.082670 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.127998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.132639 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.168007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.177996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 85.182709 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.217993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.227996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 85.227998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.236700 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 85.246728 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 85.248031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.268002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.282665 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.317994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.332684 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.368002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.382664 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.428003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.428006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 85.432654 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.468003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.478692 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 85.480026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.486734 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 85.496745 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 85.498005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.517996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.532678 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.567996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.582667 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.618016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.632665 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.667996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.678039 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 85.682686 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.728044 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 85.728050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.730020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.736722 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 85.746837 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 85.746840 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.768003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.782653 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.818003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.832657 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.868013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.882652 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.918002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.927998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 85.932688 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 85.967999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 85.977995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 85.980013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 85.986685 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 85.996694 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 85.998039 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.027992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.032633 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.068009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.082708 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.118025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.132705 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.177995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.177998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 86.182616 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.217996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.227992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 86.230009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.236719 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 86.246677 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 86.247992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.268002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.282678 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.328002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.332628 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.367999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.382651 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.418003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.427987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 86.432638 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.478034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.479999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 86.480000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.486679 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 86.496673 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 86.497991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.518025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.532634 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.568017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.582669 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.627996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.632635 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.668006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.678017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.678019 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 86.682640 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.718005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.728720 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 86.728721 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.736675 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 86.746685 1 1ceb56f4x Rx d 8 02 7A 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 86.747992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.778029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.782632 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.817997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.832650 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.867994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.882694 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.927996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.928029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 86.932604 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 86.977996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 86.980009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 86.980010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 86.986643 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 86.996653 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 86.997989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.017994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.032649 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.077996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.082619 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.127989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.132630 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.168010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.177994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 87.182655 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.227994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.230004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 87.230005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.236634 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 87.246664 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 87.247989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.277998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.282032 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.317995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.332004 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.367998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.381998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.427996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.427998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 87.432031 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.467997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.478642 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 87.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.486685 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 87.496664 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 87.497997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.527999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.532002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.577989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.582018 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.618007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.631982 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.667999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.678007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 87.682008 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.727998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.729997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 87.729998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.736647 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 87.746651 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 87.747991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.767999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.782024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.828002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.831983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.877995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.882026 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.917994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.928033 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 87.932028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 87.978047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 87.978049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 87.980023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 87.986623 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 87.996665 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 87.997989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.027998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.032037 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.068013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.081988 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.127995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.131994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.177996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.177998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 88.181988 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.227996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.229991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 88.229992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.236633 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 88.246656 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 88.247992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.267998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.281998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.327997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.331991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.368003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.382002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.418012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.428007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 88.432017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.477994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.479994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 88.479995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.486639 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 88.496665 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 88.498036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.517996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.532044 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.577997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.582017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.627998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.631998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.667989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.677990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 88.682004 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.728024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.729995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 88.729996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.736646 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 88.746645 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 88.748016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.778000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.781995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.818019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.832007 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.868037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.882010 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.927994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.927996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 88.932018 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 88.977997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 88.979985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 88.979986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 88.986601 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 88.996629 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 88.997991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.028030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.031988 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.077996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.081990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.127986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.131983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.177995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.177998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 89.181995 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.227998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.229985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 89.229986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.236580 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 89.246630 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 89.247997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.268003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.282026 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.317992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.332020 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.367994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.382017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.418038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.427990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 89.432029 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.477997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.480003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 89.480004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.486617 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 89.496614 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 89.497999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.517998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.531989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.568001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.582006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.617992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.632006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.668000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.677989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 89.682003 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.727995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.730010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 89.730011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.736599 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 89.746628 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 89.747991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.778001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.781991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.817987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.832000 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.867992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.882028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.917995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.927997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 89.932017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 89.977992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 89.977994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 89.979988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 89.986589 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 89.996598 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 89.997984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.018016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.032001 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.068000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.082023 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.117992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.132040 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.168006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.177993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 90.182005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.228017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.229988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 90.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.236604 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 90.246583 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 90.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.278013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.281986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.327999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.332011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.368037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.382006 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.417997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.427999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 90.432032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.478000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.479987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 90.479988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.486554 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 90.496612 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 90.497991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.528007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.531995 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.567999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.581988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.617990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.631991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.677992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.680004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 90.681999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.728017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.729993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 90.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.736585 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 90.746562 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 90.748083 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.777999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.782015 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.817997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.832023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.877994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.881999 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.928004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.929985 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 90.931998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 90.978002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 90.978005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 90.980070 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 90.986541 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 90.996587 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 90.997995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.018003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.032016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.068008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.082024 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.118004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.132026 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.168005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.177993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 91.182026 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.217990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.228494 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 91.230003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.236558 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 91.246551 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 91.247983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.277998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.282002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.318003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.332022 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.378002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.381996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.418027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.428004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 91.432036 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.478005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.480022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 91.480023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.486547 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 91.496611 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 91.497987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.527993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.531996 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.577998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.581996 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.618000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.632030 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.667997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.677990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 91.682029 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.727994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.729995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 91.729998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.736568 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 91.746554 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 91.748025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.778000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.782022 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.818008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.832002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.878020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.881993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.928004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.929993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 91.932053 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 91.978004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 91.979990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 91.979991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 91.986550 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 91.996579 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 91.997992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.018005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.032002 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.078006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.082033 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.117995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.132009 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.178001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.178004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 92.182000 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.227997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.230021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 92.230022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.236547 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 92.246550 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 92.248000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.267991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.282013 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.327986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.332030 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.377993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.381999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.417997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.428002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 92.432024 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.478000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.479986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 92.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.486539 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 92.496502 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 92.497984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.528000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.532003 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.568004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.581985 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.627997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.632027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.678026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.678029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 92.682028 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.717992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.728513 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 92.730017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.736518 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 92.746541 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 92.747989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.777999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.781997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.827996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.831995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.868012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.882023 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.928019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.928025 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 92.931998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 92.977998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 92.980028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 92.980029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 92.986523 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 92.996533 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 92.997999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.018002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.031991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.078011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.081989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.118011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.131996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.168000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.177991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 93.182014 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.228025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 93.228032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.230004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.236493 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 93.246536 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 93.248025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.278003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.282029 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.328010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.332027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.378003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.382006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.428019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.430024 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 93.431986 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.467997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.478496 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 93.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.486491 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 93.496527 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 93.497994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.517995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.532041 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.578011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.582040 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.617999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.632013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.668001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.678015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 93.682032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.727995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.729987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 93.729988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.736538 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 93.748009 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 93.748013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.768017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.781999 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.817993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.832008 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.878032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.882009 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.927990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.927993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 93.932030 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 93.978005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 93.978010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 93.979987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 93.986524 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 93.996515 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 93.997993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.018005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.027995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.032008 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.078001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.081999 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.117991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.132004 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.177996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.179997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 94.181983 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.218036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.228478 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 94.229984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.236534 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 94.246519 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 94.247978 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.267996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.281999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.328030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.331992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.378028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.381991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.417994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.427997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 94.432006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.477996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.479988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 94.479989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.486513 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 94.496507 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 94.497995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.517993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.532004 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.578048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.581996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.617999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.632018 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.668035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.678012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 94.682024 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.718006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.728503 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 94.730103 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.736470 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 94.746493 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 94.748016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.778008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.781989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.817997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.831996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.877999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.881989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.927995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.927997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 94.932009 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 94.978003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 94.979987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 94.979988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 94.986501 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 94.996481 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 94.998008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.018022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.032059 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.078030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.081991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.117994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.132032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.167994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.178013 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 95.182042 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.227997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.229986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 95.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.236509 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 95.248008 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 95.248011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.267996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.282017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.317993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.332020 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.378022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.381991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.418026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.428011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 95.432032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.468029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.478545 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 95.478547 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.486524 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 95.496513 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 95.497998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.527996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.531988 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.568037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.582007 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.618031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.631983 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.678016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.678023 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 95.681999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.728005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.729984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 95.729985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.736496 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 95.746514 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 95.747987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.768009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.782021 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.828004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.831998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.868000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.882028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.927994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.927996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 95.932001 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 95.978063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 95.979995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 95.979996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 95.986483 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 95.996479 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 95.998001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.017999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.031994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.067997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.082018 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.128016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.132019 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.178001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.178003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 96.182017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.218004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.228530 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 96.228532 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.236476 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 96.246482 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 96.247984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.267997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.282012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.318022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.331998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.377992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.381997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.427998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.428000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 96.432030 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.477996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.480022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 96.480023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.486458 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 96.496489 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 96.497993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.528029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.531984 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.578012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.582030 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.617996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.632025 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.678000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.678002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 96.681989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.727992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.730023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 96.730024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.736452 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 96.746491 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 96.748063 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.777997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.782017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.828041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.831993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.877998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.882011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.918007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.927998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 96.932001 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 96.977992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 96.979985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 96.979986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 96.986500 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 96.998025 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 96.998027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.028017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.031992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.067999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.082019 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.128003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.131994 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.178007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.178011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 97.181991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.227998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.229987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 97.229989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.236404 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 97.247992 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 97.247994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.277995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.282008 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.328045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.332031 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.378043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.382011 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.427991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.427994 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 97.432005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.478005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.480000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 97.480001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.486381 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 97.496511 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 97.498007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.528000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.531985 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.578003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.582038 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.628042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.632005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.677995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.677998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 97.682010 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.727994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.730012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 97.730013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.736408 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 97.746427 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 97.747988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.777999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.782010 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.827994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.831996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.878001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.882075 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.928001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.928003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 97.932002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 97.977998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 97.980026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 97.980027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 97.986357 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 97.996417 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 97.998022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.018017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.032005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.078034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.082012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.128008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.132016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.177997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.177999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 98.182016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.228003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.229995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 98.229996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.236380 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 98.247995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 98.247997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.277997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.281990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.327991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.331986 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.377999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.381984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.428024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.428026 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 98.432028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.478006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.479986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 98.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.486376 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 98.496404 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 98.497983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.528022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.532016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.577995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.581987 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.627997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.631996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.678001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.678004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 98.682011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.728024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.730033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 98.730034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.736371 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 98.746375 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 98.747987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.777998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.782010 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.828019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.832015 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.877997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.881998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.928009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.928012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 98.932012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 98.978001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 98.980021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 98.980022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 98.986368 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 98.997986 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 98.997988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.028003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.031994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.078025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.082000 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.128010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.131987 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.177995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.177997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 99.181993 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.228000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.229987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 99.229988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.236385 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 99.246402 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 99.247988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.278001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.282030 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.327998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.331990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.378005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.382026 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.427995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.427997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 99.431995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.478006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.479991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 99.479992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.486345 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 99.496392 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 99.497987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.527998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.532012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.578018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.582031 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.617998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.632013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.678024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.678027 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 99.682011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.728009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.729993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 99.729994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.736387 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 99.746379 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 99.747989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.778004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.781996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.828001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.831999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.878002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.881990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.927997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.927999 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 99.932006 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 99.978009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 99.979988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 99.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 99.986353 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 99.996369 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 99.998030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.027998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.032032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.078001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.081996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.128019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.132008 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.178003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.178008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 100.181990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.227983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.229986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 100.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.236360 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 100.246411 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 100.248011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.278022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.281998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.328007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.332018 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.377997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.381997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.427998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.428000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 100.431994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.478001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.480023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 100.480024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.486362 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 100.498015 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 100.498018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.527997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.531985 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.577992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.582022 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.627994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.631998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.677999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.678002 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 100.682003 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.728001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.730009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 100.730010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.736361 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 100.746354 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 100.747985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.777981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.782009 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.828000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.832005 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.877995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.882028 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.927995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.927997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 100.932005 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 100.978040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 100.979995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 100.979996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 100.986346 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 100.996371 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 100.998012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.028006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.032016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.078040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.081998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.127988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.131989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.177996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.177998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 101.182011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.228000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.229988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 101.229989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.236368 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 101.248066 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 101.248074 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.278029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.282012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.328025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.332013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.378035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.381991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.427995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.427997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 101.432004 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.477999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.479999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 101.480004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.488018 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 101.496348 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 101.498028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.527991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.531993 1 1812f456x Rx d 8 1C 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.577994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.581994 1 1812f456x Rx d 8 1C 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.628026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.631998 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.678036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.678038 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 101.682037 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.728001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.729990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 101.729991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.737986 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 101.746348 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 101.747974 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.778008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.781996 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.828009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.832017 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.878002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.881997 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.927994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.927997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 101.931995 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 101.978012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 101.979991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 101.979992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 101.986325 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 101.998005 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 101.998008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.027998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.032005 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.077998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.081984 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.128001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.131992 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.178017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.178022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 102.182001 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.228035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.230046 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 102.230047 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.237995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 102.247996 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 102.247998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.278008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.281986 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.328020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.332042 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.378017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.382033 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.428012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.428014 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 102.432033 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.478050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.479996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 102.479997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.486343 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 102.496397 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 102.497998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.527994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.532015 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.577990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.583465 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.628018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.631992 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.678008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.678010 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 102.682040 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.727998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.730023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 102.730025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.736266 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 102.748012 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 102.748021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.777999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.782013 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.828001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.831993 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.878001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.881986 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.927996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.927998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 102.931991 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 102.977992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 102.979992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 102.979993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 102.986257 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 102.998035 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 102.998037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.027992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.031992 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.078000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.082021 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.128014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.132022 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.178029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.178031 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 103.181995 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.228021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.229986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 103.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.238031 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 103.248005 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 103.248008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.278010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.282031 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.327996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.331987 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.377995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.381999 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.428001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.428003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 103.432025 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.477992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.479990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 103.479992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.486254 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 103.498002 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 103.498004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.528028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.532016 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.577992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.582047 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.628006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.631995 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.678005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.678007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 103.682049 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.727992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.729990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 103.729991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.738001 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 103.748021 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 103.748023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.777996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.782033 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.828019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.831990 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.878006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.881999 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.928003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.928005 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 103.932022 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 103.977993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 103.979997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 103.979998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 103.986230 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 103.996252 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 103.998002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.028001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.032010 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.078039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.082034 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.128033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.131991 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.177998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.178002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 104.181987 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.228003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.230007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 104.230008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.236246 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 104.248041 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 104.248043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.277998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.282063 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.328015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.332003 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.378007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.382024 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.427998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.428000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 104.432030 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.478033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.480013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 104.480014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.486232 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 104.496250 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 104.497991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.527996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.532027 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.578030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.581992 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.628005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.631999 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.677996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.677998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 104.681998 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.727995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.729994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 104.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.736227 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 104.746261 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 104.748028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.777995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.781996 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.828001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.831994 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.878002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.881997 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.927998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.928000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 104.932011 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 104.978005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 104.979987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 104.979989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 104.988015 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 104.998012 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 104.998014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.028013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.031987 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.077997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.081986 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.127993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.132018 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.178028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.178031 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 105.181134 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.227994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.229995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 105.229998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.237991 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 105.248004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 105.248007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.278027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.281990 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.328019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.331124 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.378008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.381993 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.427995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.427997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 105.431996 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.478012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.479994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 105.479995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.488023 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 105.496219 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 105.497984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.528012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.531125 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.577996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.581993 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.627998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.631115 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.677994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.677996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 105.681992 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.728007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.730025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 105.730026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.736201 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 105.747994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 105.747996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.778005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.781991 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.828020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.831113 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.878000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.881118 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.928005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.928008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 105.931986 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 105.978008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 105.980029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 105.980031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 105.988024 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 105.998003 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 105.998005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.028004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.032012 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.078003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.081992 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.127990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.131987 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.178008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.178011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 106.181994 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.227998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.229990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 106.229991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.238027 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 106.248030 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 106.248032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.277121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.280202 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.327995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.330119 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.377997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.380140 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.428029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.428031 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 106.430132 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.477113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.478113 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 106.479986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.487128 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 106.498015 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 106.498018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.527994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.530111 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.577123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.580120 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.628036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.630126 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.678000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.678003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 106.680113 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.728030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.729994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 106.729995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.738004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 106.747986 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 106.747988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.777998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.780107 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.827116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.830105 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.877124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.880096 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.928007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.928009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 106.930114 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 106.977995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 106.979989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 106.979990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 106.986165 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 106.998005 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 106.998008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.028008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.030109 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.077158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.080102 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.127997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.130102 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.177998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.178000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 107.180114 1 1812f456x Rx d 8 1C 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.227119 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.228091 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 107.229983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.237118 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 107.248015 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 107.248017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.277133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.280101 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.327134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.330092 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.377998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.380082 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.427993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.427995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 107.430071 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.477136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.478081 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 107.480017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.487141 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 107.497986 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 107.497987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.527101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.530066 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.577109 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.580091 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.627095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.630069 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.677993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.677995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 107.680101 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.727109 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.728097 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 107.729996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.736161 1 1ceb56f4x Rx d 8 01 30 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 107.748010 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 107.748013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.777098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.780083 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.827091 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.830117 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.877101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.880061 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.928022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.928027 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 107.930067 1 1812f456x Rx d 8 12 11 93 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 107.977128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 107.978104 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 107.979994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 107.987091 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 107.998037 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 107.998039 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.027104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.030062 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.077137 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.080065 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.127090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.130064 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.178052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.178057 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 108.180102 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.227096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.228034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 108.229991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.237097 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 108.247987 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 108.247988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.277095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.280074 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.327100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.330078 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.377100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.380069 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.428005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.428010 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 108.430081 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.477096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.478071 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 108.479999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.487078 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 108.496151 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 108.497989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.527084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.530075 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.577082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.580095 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.627077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.630078 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.678001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.678003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 108.680062 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.727087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.730005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 108.730006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.736158 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 108.748044 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 108.748047 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.777094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.780092 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.827128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.830118 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.877101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.880040 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.927995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.927997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 108.930062 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 108.977075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 108.978087 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 108.980026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 108.987066 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 108.997982 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 108.997983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.027066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.030033 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.077101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.080049 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.127069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.130065 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.177993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.177995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 109.180078 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.227090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.228024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 109.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.237103 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 109.248006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 109.248008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.277098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.280065 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.327058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.330057 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.377068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.380032 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.428009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.428012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 109.430014 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.477051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.479105 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 109.479106 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.486134 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 109.497996 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 109.497998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.527081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.530039 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.577061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.580020 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.627067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.630019 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.677998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.678000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 109.680021 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.727083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.728042 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 109.729980 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.737076 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 109.748028 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 109.748030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.777075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.780016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.827098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.830047 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.877068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.880021 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.928065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.928068 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 109.930045 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 109.977101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 109.978008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 109.979995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 109.987060 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 109.998002 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 109.998004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.027089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.030047 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.077073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.080027 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.127081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.130010 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.177112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.177115 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 110.180009 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.227110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.227993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 110.230043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.237065 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 110.248009 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 110.248012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.277068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.280021 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.327047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.330016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.377068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.380006 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.428048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.428051 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 110.430046 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.477072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.478008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 110.480030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.487073 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 110.497981 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 110.497982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.527030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.530020 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.577072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.580001 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.627039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.630049 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.677998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.678001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 110.679992 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.727046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.728016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 110.729996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.737081 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 110.748010 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 110.748012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.777062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.780011 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.827071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.830044 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.877017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.880072 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.927083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.927086 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 110.930073 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 110.977042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 110.979118 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 110.979120 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 110.986088 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 110.997126 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 110.997129 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.027083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.030008 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.077001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.080059 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.127049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.130013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.177138 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.177141 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 111.179995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.227014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.227991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 111.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.237017 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 111.247138 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 111.247140 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.277007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.280013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.327009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.330029 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.377004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.379993 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.427110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.427112 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 111.430004 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.477054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.479072 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 111.479073 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.486040 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 111.497132 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 111.497135 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.526997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.530018 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.577035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.579995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.627013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.630024 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.677117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.677120 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 111.680003 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.726987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.727999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 111.729989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.736054 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 111.746145 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 111.746148 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.777029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.780000 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.827006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.829994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.877030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.879991 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.927130 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.927137 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 111.929993 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 111.977039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 111.977981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 111.979998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 111.986034 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 111.996044 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 111.997985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.027023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.030041 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.076993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.079997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.127024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.130054 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.177074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.177078 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 112.179997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.226966 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.229047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 112.229049 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.236029 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 112.247103 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 112.247106 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.276990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.280020 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.327004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.330005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.376982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.380035 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.427078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.427083 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 112.429993 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.477023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.479048 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 112.479049 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.487025 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 112.496064 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 112.498004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.526959 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.530021 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.576967 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.580028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.626965 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.630023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.677107 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.677110 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 112.679999 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.726985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.729098 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 112.729100 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.736017 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 112.746162 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 112.746165 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.777020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.779987 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.827011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.829989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.877014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.880035 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.927051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.927053 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 112.930038 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 112.976963 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 112.978012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 112.979982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 112.985999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 112.997012 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 112.997990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.026943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.030007 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.076968 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.080044 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.126984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.129998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.177082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.177087 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 113.180016 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.226964 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.227986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 113.230022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.236995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 113.246153 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 113.246157 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.276998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.280023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.326996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.329983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.376974 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.380018 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.427053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.427056 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 113.430007 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.476930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.479011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 113.479012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.485995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 113.496040 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 113.498032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.526940 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.530034 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.576986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.579981 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.626952 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.629994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.677059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.677061 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 113.679990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.726949 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.727987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 113.730010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.735997 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 113.746010 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 113.748029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.776947 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.779988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.826972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.829992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.877033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.879984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.927999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.928002 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 113.930008 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 113.976977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 113.979030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 113.979031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 113.986004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 113.996085 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 113.996088 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.026924 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.029988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.076933 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.080024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.126980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.129991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.177026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.177029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 114.180042 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.226956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.227982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 114.230017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.235997 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 114.246081 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 114.246083 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.276921 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.279987 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.326944 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.329991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.376907 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.379988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.427024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.427027 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 114.430022 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.476923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.477989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 114.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.486000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 114.496007 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 114.497985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.526959 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.529987 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.576944 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.579993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.626912 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.629995 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.677032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.677036 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 114.680023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.726953 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.727981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 114.729987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.735988 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 114.746056 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 114.746057 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.776972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.779989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.826946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.830024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.876920 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.880016 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.927019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.927022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 114.929986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 114.976911 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 114.977982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 114.979983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 114.986003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 114.996085 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 114.996088 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.026932 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.029998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.076917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.079982 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.126922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.129987 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.176997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.176999 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 115.180029 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.226916 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.227987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 115.229984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.236028 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 115.246081 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 115.246083 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.276915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.279985 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.326918 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.330017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.376910 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.379980 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.427010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.427013 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 115.429990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.476896 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.477992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 115.479987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.486017 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 115.496044 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 115.496046 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.526897 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.530030 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.576919 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.579986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.626954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.630012 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.677027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.677030 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 115.679995 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.726920 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.727994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 115.730005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.735990 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 115.746050 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 115.746053 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.776904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.779984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.826876 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.830034 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.876881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.879997 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.926969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.926972 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 115.929987 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 115.976904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 115.977989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 115.979995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 115.985986 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 115.996006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 115.997996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.026904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.030027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.076903 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.079987 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.126889 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.130008 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.176994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.177001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 116.179991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.226905 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.227987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 116.230005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.235994 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 116.246050 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 116.246052 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.276899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.279988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.326884 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.330039 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.376884 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.379993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.427020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.427023 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 116.429990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.476876 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.478928 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 116.478929 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.485992 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 116.496038 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 116.496041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.526871 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.530014 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.576880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.580011 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.626887 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.630036 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.676982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.676984 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 116.679994 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.726891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.727985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 116.730031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.735989 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 116.746020 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 116.746023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.776899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.780014 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.826903 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.830022 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.876856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.879986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.927023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.927026 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 116.929996 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 116.976922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 116.977982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 116.979991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 116.985999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 116.996035 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 116.996037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.026851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.029990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.076881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.080004 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.126863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.130003 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.176956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.176961 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 117.180015 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.226861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.227986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 117.230021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.236030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 117.246054 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 117.246057 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.276856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.279998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.326857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.330008 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.376870 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.380000 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.426963 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.426965 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 117.430037 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.476886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.478945 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 117.478947 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.485996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 117.496017 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 117.497999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.526878 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.530014 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.576875 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.579990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.626905 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.630023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.676960 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.676964 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 117.680016 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.726876 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.727981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 117.729992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.735997 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 117.745996 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 117.745998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.776881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.780027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.826850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.829989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.876870 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.880028 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.926963 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.926965 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 117.930006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 117.976844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 117.978016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 117.980007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 117.985990 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 117.996007 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 117.996011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.026833 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.029992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.076869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.079992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.126844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.129988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.176955 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.176958 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 118.180002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.226849 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.228925 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 118.228926 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.235990 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 118.246004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 118.246007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.276869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.280018 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.326861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.330024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.376868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.380002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.426899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.426902 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 118.429988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.476835 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.478021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 118.480031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.484844 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 118.496013 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 118.496016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.526848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.529986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.576851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.580016 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.626866 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.629994 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.676945 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.676948 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 118.680017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.726815 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.727990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 118.729983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.735994 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 118.746000 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 118.746002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.776826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.780047 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.826832 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.829995 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.876866 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.880017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.926941 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.926946 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 118.929989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 118.976868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 118.977989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 118.979985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 118.986014 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 118.996034 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 118.998017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.026820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.029990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.076859 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.079994 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.126861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.129984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.176951 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.176953 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 119.180027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.226895 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.228031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 119.230025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.235991 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 119.246014 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 119.246016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.276864 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.280012 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.326858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.330019 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.376819 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.379990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.426998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.427001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 119.430003 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.476849 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.478893 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 119.478895 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.484854 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 119.496004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 119.496006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.526837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.530024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.576785 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.579985 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.626793 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.630032 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.676898 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.676900 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 119.679990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.726820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.727997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 119.729990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.735993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 119.746013 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 119.746016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.776829 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.779990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.826828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.830027 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.876832 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.879992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.926885 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.926887 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 119.929989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 119.976819 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 119.978016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 119.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 119.985994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 119.996013 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 119.996015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.026823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.030023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.076812 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.079989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.126804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.130030 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.176879 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.176882 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 120.180031 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.226824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.227988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 120.230017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.235994 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 120.246003 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 120.246006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.276837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.280029 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.326803 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.330012 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.376828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.380000 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.426887 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.426890 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 120.429993 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.476793 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.478871 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 120.478873 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.485992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 120.495992 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 120.495995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.526846 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.530021 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.576848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.580046 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.626815 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.630007 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.676880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.676883 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 120.679986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.726815 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.727987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 120.730000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.735986 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 120.745999 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 120.746001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.776810 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.780001 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.826783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.830001 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.876822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.879999 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.926901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.926904 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 120.930022 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 120.976768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 120.978855 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 120.978859 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 120.984800 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 120.995993 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 120.995996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.026766 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.029984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.076842 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.080017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.126796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.129988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.176854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.176856 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 121.179994 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.226766 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.228005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 121.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.235991 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 121.246030 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 121.246033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.276772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.280042 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.326809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.330021 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.376760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.379996 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.426861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.426863 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 121.429989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.476762 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.478847 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 121.478848 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.484761 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 121.495989 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 121.495992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.526741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.530000 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.576789 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.580020 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.626827 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.630017 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.676836 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.676838 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 121.680020 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.726797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.727978 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 121.730026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.735990 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 121.746006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 121.746009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.776772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.779993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.826760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.829992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.876768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.879997 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.926862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.926864 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 121.930024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 121.976782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 121.977984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 121.979995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 121.984780 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 121.996004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 121.996007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.026759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.030038 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.076737 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.080025 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.126753 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.129990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.176891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.176894 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 122.180034 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.226745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.227987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 122.230037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.235994 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 122.246004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 122.246006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.276761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.279984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.326765 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.330000 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.376754 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.380016 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.426820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.426825 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 122.430030 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.476745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.478847 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 122.478848 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.484778 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 122.495997 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 122.495999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.526752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.530012 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.576787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.579983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.626779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.629991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.676824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.676827 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 122.679983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.726741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.727984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 122.729981 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.736001 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 122.746007 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 122.746010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.776728 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.780026 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.826753 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.829986 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.876732 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.879987 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.926809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.926812 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 122.930019 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 122.976724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 122.977999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 122.980019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 122.984803 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 122.996015 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 122.996017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.026777 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.030015 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.076724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.080002 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.126725 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.130019 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.176835 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.176837 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 123.179996 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.226707 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.227992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 123.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.236002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 123.246019 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 123.246021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.276712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.279990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.326704 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.330005 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.376724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.379988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.426897 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.426899 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 123.430032 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.476720 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.478803 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 123.478807 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.484724 1 1ceb56f4x Rx d 8 01 2B 11 A2 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 123.495998 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 123.496000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.526707 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.529981 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.576733 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.580002 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.626687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.629983 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.676840 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.676847 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 123.680041 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.726711 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.727982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 123.729992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.735991 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 123.745998 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 123.746001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.776712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.780016 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.826749 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.829997 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.876695 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.880006 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.926783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.926786 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 123.929991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 123.976752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 123.977985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 123.979986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 123.984708 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 123.996010 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 123.996014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.026767 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.030010 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.076696 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.079989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.126713 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.130042 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.176791 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.176794 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 124.180039 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.226717 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.227997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 124.229989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.235993 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 124.246013 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 124.246016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.276695 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.280047 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.326691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.329982 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.376692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.379991 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.426811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.426813 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 124.430024 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.476696 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.478745 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 124.478746 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.484697 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 124.496030 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 124.496033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.526694 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.529998 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.576687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.580034 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.626712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.629988 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.676775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.676778 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 124.679993 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.726684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.727983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 124.730000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.735991 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 124.745998 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 124.746001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.776694 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.779985 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.826687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.829989 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.876689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.879992 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.926785 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.926792 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 124.929986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 124.976705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 124.977998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 124.979992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 124.984676 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 124.996014 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 124.996017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.026707 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.030023 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.076672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.079984 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.126673 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.130011 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.176762 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.176765 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 125.179986 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.226682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.227989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 125.230026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.235991 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 125.246002 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 125.246004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.276692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.279990 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.326682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.328675 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.376683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.378656 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.426750 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.426753 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 125.428675 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.476659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.478793 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 125.478796 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.484673 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 125.496021 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 125.496025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.526694 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.528653 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.576666 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.578648 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.626669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.628662 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.676777 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.676785 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 125.678636 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.726697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.728008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 125.730002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.735993 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 125.745994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 125.745997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.776668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.778646 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.826662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.828635 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.876653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.878657 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.926750 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.926752 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 125.928625 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 125.976653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 125.978037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 125.979994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 125.984668 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 125.996005 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 125.996008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.026664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.028648 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.076659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.078657 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.126654 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.128608 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.176738 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.176740 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 126.178643 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.226643 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.227981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 126.229989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.236001 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 126.244661 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 126.246000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.276675 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.278647 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.326676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.328639 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.376646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.378633 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.426710 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.426713 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 126.428621 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.476669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.477981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 126.480020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.484660 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 126.496022 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 126.496025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.526621 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.528589 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.576644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.578604 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.626669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.628603 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.676717 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.676720 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 126.678607 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.726660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.727989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 126.730019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.736008 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 126.746016 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 126.746018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.776655 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.778598 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.826660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.828602 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.876633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.878626 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.926726 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.926728 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 126.928615 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 126.976647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 126.977987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 126.980036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 126.984612 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 126.996016 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 126.996019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.026618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.028606 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.076618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.078627 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.126654 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.128608 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.176745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.176748 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 127.178592 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.226605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.228008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 127.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.235996 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 127.244652 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 127.246009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.276613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.278592 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.326601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.328596 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.376626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.378615 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.426735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.426738 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 127.428614 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.476641 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.477978 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 127.480028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.484605 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 127.496006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 127.496013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.526648 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.528598 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.576639 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.578581 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.626595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.628612 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.676692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.676694 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 127.678597 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.726647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.727993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 127.729990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.735996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 127.746016 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 127.746019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.776638 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.778581 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.826647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.828596 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.876618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.878580 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.926725 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.926728 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 127.928618 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 127.976634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 127.978039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 127.980025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 127.984583 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 127.996029 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 127.996032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.026580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.028592 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.076585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.078604 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.126599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.128599 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.176683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.176686 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 128.178587 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.226615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.227992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 128.229998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.235993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 128.244627 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 128.246026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.276645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.278615 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.326633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.328601 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.376647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.378660 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.426685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.426688 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 128.428625 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.476607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.477997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 128.480007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.484602 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 128.496002 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 128.496005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.526599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.528575 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.576588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.578590 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.626579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.628609 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.676681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.676693 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 128.678614 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.726584 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.727993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 128.730003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.736006 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 128.744601 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 128.745980 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.776564 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.778634 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.826587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.828560 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.876562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.878577 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.926664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.926666 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 128.928596 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 128.976605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 128.977985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 128.980017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 128.984609 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 128.996027 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 128.996030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.026576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.028546 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.076566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.078588 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.126570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.128560 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.176727 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.176733 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 129.178537 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.226552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.227992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 129.229993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.235992 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 129.244567 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 129.245988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.276577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.278546 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.326588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.328566 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.376563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.378573 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.426665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.426668 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 129.428563 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.476537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.477990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 129.479990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.484544 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 129.496018 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 129.496026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.526562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.528550 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.576549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.578554 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.626582 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.628531 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.676661 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.676664 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 129.678525 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.726555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.727987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 129.730026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.735996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 129.745987 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 129.745989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.776568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.778532 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.826564 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.828542 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.876595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.878533 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.926669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.926672 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 129.928538 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 129.976543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 129.977999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 129.980021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 129.984622 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 129.996051 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 129.996054 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.026543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.028527 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.076531 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.078549 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.126551 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.128534 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.176670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.176677 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 130.178552 1 1812f456x Rx d 8 08 11 91 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.226565 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.227995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 130.230011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.236003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 130.244561 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 130.246014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.276594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.278542 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.326565 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.328520 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.376549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.378503 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.426591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.426593 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 130.428522 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.476536 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.477986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 130.480040 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.484553 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 130.496036 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 130.496040 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.526567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.528520 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.576583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.578511 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.626536 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.628521 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.676649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.676652 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 130.678503 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.726563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.727987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 130.730007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.735989 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 130.746033 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 130.746041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.776543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.778508 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.826525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.828513 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.876567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.878508 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.926655 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.926658 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 130.928534 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 130.976566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 130.977985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 130.980001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 130.984569 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 130.996004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 130.996007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.026574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.028522 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.076552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.078509 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.126566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.128515 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.176634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.176637 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 131.178542 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.226572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.227988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 131.230036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.236001 1 1ceb56f4x Rx d 8 01 44 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 131.244516 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 131.245998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.276550 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.278536 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.326510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.328519 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.376549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.378528 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.426610 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.426613 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 131.428514 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.476520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.477989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 131.479991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.484501 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 131.496001 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 131.496004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.526515 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.528513 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.576562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.578525 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.626508 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.628520 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.676640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.676643 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 131.678519 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.726523 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.728030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 131.729988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.735995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 131.744570 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 131.745988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.776505 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.778501 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.826530 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.828492 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.876516 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.878478 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.926609 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.926612 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 131.928464 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 131.976496 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 131.978008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 131.980012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 131.984505 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 131.995995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 131.995997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.026524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.028495 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.076526 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.078489 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.126501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.128487 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.176591 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.176593 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 132.178501 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.226541 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.227989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 132.229990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.234489 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 132.246011 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 132.246014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.276491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.278506 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.326492 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.328475 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.376495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.378461 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.426553 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.426555 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 132.428454 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.476498 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.477983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 132.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.484515 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 132.496022 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 132.496024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.526487 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.528466 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.576484 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.578457 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.626477 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.628495 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.676564 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.676566 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 132.678434 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.726499 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.727984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 132.730012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.734484 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 132.744502 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 132.746009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.776531 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.778506 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.826520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.828470 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.876516 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.878475 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.926601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.926606 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 132.928481 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 132.976510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 132.977984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 132.979983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 132.984501 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 132.996023 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 132.996027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.026509 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.028471 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.076506 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.078433 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.126485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.128467 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.176568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.176570 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 133.178449 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.226476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.227986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 133.227987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.235995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 133.244501 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 133.246070 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.276510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.278454 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.326456 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.328468 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.376473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.378468 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.426550 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.426552 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 133.428481 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.476478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.477992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 133.480022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.484481 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 133.496030 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 133.496033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.526483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.528464 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.576474 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.578453 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.626467 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.628447 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.676553 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.676556 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 133.678456 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.726466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.727979 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 133.729983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.734459 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 133.746007 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 133.746010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.776504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.778446 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.826483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.828464 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.876453 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.878448 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.926534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.926537 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 133.928424 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 133.976448 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 133.977985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 133.979987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 133.984474 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 133.996023 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 133.996026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.026443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.028452 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.076470 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.078445 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.126463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.128439 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.176566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.176568 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 134.178436 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.226445 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.227990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 134.229992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.234433 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 134.244480 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 134.245993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.276431 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.278441 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.326491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.328468 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.376449 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.378437 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.426561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.426564 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 134.428428 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.476460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.477970 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 134.480029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.484425 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 134.496003 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 134.496006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.526470 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.528429 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.576428 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.578445 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.626475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.628397 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.676546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.676548 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 134.678439 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.726464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.727990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 134.729991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.735987 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 134.744471 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 134.746003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.776453 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.778412 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.826478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.828409 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.876451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.878408 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.926524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.926527 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 134.928432 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.976416 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 134.977986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 134.980003 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 134.980004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 134.984431 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 134.994476 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 134.996012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.026413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.028425 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.076452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.078445 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.126423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.128437 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.176521 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.176528 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 135.178417 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.226445 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.227994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 135.229987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.234400 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 135.244473 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 135.245997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.276455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.278397 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.326413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.328394 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.376413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.378423 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.426556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.426559 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 135.428432 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.476434 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.477984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 135.479993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.484440 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 135.496006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 135.496009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.526448 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.528372 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.576450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.578391 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.626447 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.628375 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.676496 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.676498 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 135.678395 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.726447 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.727985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 135.730001 1 1812f456x Rx d 8 08 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.730002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.734419 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 135.744411 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 135.745995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.776422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.778393 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.826442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.828371 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.876443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.878399 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.926527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.926530 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 135.928416 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 135.976435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 135.977995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 135.980028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 135.984452 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 135.996034 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 135.996037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.026455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.030050 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.076424 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.078404 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.137361 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.137364 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.176501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.176504 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 136.178482 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.233695 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.233749 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 136.233750 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.235459 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 136.245232 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 136.247267 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.277001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.278993 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.326992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.328997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.377000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.378998 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.426984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.426987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 136.428984 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.476990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.478989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 136.478990 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.478991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.484999 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 136.495615 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 136.495618 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.526994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.528982 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.576992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.578980 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.627000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.628986 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.676988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.676991 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 136.678981 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.726998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.728984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 136.728985 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.728985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.735007 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 136.745628 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 136.745631 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.777015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.779031 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.826996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.829005 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.876997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.879013 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.926998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.927000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 136.928994 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 136.976997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 136.979018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 136.979019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 136.985003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 136.994994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 136.996991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.027014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.028989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.077029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.079005 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.127030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.129022 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.176996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.176998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 137.178992 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.227002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.229024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 137.229025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.235016 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 137.245002 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 137.246988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.276997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.279017 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.327003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.329033 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.376997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.379012 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.427000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.427003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 137.428997 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.477001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.479000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 137.479002 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.479003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.485001 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 137.495506 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 137.495509 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.526996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.528989 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.577040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.578995 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.626991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.629014 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.676999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.677001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 137.679007 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.726997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.728989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 137.728990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.735400 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 137.745043 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 137.747012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.777008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.779027 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.827008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.829000 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.876995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.878983 1 1812f456x Rx d 8 12 11 92 0D 34 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.927011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.927015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 137.929021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.976994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 137.978990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 137.978992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 137.978992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 137.985019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 137.995006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 137.996996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.027005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.029001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.077024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.079023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.127031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.128995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.177002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.177005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 138.178982 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.226999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.228986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 138.228987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.235016 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 138.245008 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 138.246998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.276990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.278990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.327023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.329006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.377022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.379011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.427000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.427002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 138.429028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.476994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.478987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 138.478988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.478989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.485019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 138.494995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 138.496986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.526997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.528991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.576995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.578998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.626996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.628990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.677011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.677019 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 138.678982 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.727006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.729006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 138.729007 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.729008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.734994 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 138.745037 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 138.746998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.776995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.778993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.827003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.829021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.877006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.878991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.926992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.926995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 138.928984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 138.976995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 138.978986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 138.978988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 138.985010 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 138.995490 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 138.995492 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.026990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.028985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.077026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.078998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.127016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.129026 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.177002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.177004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 139.178992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.227022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.229007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 139.229012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.235003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 139.245001 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 139.246988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.276994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.278988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.327005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.329022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.377035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.378984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.426991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.426993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 139.429029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.477001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.479019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 139.479020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.479021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.485000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 139.494995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 139.497043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.526993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.528999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.576992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.579020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.627040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.629007 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.677000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.677002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 139.679021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.727056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.729036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 139.729038 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.729038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.735025 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 139.745000 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 139.746997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.777045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.778996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.827003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.828989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.877000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.878996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.927018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.927021 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 139.928992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 139.976992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 139.978990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 139.978991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 139.984985 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 139.995023 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 139.996983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.027015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.028992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.076997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.078989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.126993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.128991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.177009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.177012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 140.178984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.227023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.228995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 140.228996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.228997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.235026 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 140.244994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 140.246994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.277003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.279031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.326992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.329001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.376996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.379022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.426999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.427002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 140.429007 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.477023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.478995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 140.478996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.478997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.484998 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 140.495476 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 140.495478 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.527013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.529015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.577008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.578996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.627013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.629009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.677012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.677015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 140.678984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.727017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.728989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 140.728990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.735029 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 140.744997 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 140.746996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.776997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.779010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.826994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.829009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.877007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.878988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.927038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.927041 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 140.929017 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.976994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 140.978983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 140.978984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 140.978985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 140.985024 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 140.995004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 140.997001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.026995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.028979 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.076998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.078991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.127037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.128987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.176996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.176998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 141.179022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.226995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.229023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 141.229024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.235021 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 141.245007 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 141.246986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.277005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.279025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.327018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.329001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.376997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.379029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.426997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.427000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 141.429010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.477005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.479041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 141.479042 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.479043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.485030 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 141.494994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 141.496987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.527000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.528988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.576992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.579040 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.627000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.628985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.677024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.677027 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 141.678994 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.727000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.729019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 141.729020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.729021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.735035 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 141.745004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 141.746987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.777015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.778990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.827007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.829021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.877024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.879035 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.927015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.927018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 141.929028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.976991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 141.978991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 141.978992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 141.978993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 141.985009 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 141.994992 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 141.997005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.027004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.029000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.077010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.079034 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.127014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.128998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.176999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.177002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 142.179038 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.226997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.228990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 142.228991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.235001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 142.245004 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 142.246991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.277001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.279027 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.327001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.329034 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.377033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.378996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.426995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.426997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 142.429036 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.477001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.479027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 142.479028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.479029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.485027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 142.494995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 142.497000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.527012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.529031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.577002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.578990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.627007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.628997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.677005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.677008 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 142.678988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.727025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.729019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 142.729020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.729021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.735021 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 142.745025 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 142.747020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.777012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.778986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.826998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.828987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.877036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.879011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.927034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.927037 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 142.929016 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.976998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 142.978988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 142.978990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 142.978990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 142.985008 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 142.995000 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 142.996993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.026989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.028996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.076994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.078997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.127000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.129022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.176993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.176995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 143.178983 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.227026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.229028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 143.229030 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.229030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.235020 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 143.244995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 143.247031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.277039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.279023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.327009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.329018 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.377010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.379002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.427043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.427045 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 143.428997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.476997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.479010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 143.479014 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.479014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.484990 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 143.495006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 143.497020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.527001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.528987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.576985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.578986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.627019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.628991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.677002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.677006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 143.678991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.727002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.728987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 143.728988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.728988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.735004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 143.745024 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 143.746991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.777031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.779001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.827031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.828993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.877027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.878993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.926996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.926998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 143.929023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.977003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 143.978987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 143.978989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 143.978989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 143.985004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 143.995015 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 143.996991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.027005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.029001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.077006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.078999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.127009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.129031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.176995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.176998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 144.179029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.226995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.229027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 144.229028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.234994 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 144.244994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 144.246998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.276999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.278999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.326993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.328987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.377003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.378988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.426994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.426996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 144.428987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.476996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.479034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 144.479035 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.479036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.485006 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 144.495372 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 144.495374 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.526995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.528996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.577002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.578990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.627002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.629003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.676992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.676994 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 144.679018 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.727003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.729017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 144.729019 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.729019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.735024 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 81 F1 3C Length = 0 BitCount = 0 ID = 485185268x + 144.744998 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 144.746985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.776995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.779008 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.826993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.828993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.877014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.878998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.927015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.927018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 144.928997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.976994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 144.978995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 144.978996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 144.978997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 144.985035 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 144.994999 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 144.996998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.027009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.029011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.076999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.078999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.127006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.129003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.177000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.177006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 145.179017 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.227011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.229032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 145.229033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.234998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 145.244995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 145.246986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.277013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.278992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.326997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.328987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.377000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.379020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.426996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.426998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 145.428983 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.476991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.478996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 145.478997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.478998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.484987 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 145.495006 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 145.496989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.526992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.528993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.577002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.579029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.627000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.629039 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.677012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.677014 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 145.678997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.727014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.728998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 145.728999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.728999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.735021 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 145.745001 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 145.747012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.776994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.778988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.827019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.828995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.876990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.878983 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.926999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.927001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 145.929004 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.977006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 145.978989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 145.978990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 145.978991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 145.985046 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 145.994999 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 145.996995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.026997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.028987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.076993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.078997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.126995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.128981 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.176999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.177002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 146.178987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.227003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.229035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 146.229036 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.229037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.235030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 146.244996 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 146.246989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.276992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.278984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.326996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.328984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.376993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.379015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.427007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.427010 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 146.428983 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.476996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.478990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 146.478992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.478992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.485033 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 146.494994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 146.496997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.527000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.529004 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.576991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.578989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.626999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.629009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.676994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.676997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 146.679023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.727011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.728990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 146.728992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.735020 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 146.744994 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 146.746993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.776995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.778988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.827003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.829000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.876997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.879013 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.927006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.927009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 146.928986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.976993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 146.978986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 146.978987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 146.978988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 146.985032 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 146.994995 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 146.996996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.026139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.027147 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.076995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.079021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.126114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.127125 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.176991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.176994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 147.178993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.226994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.228988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 147.228989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.228990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.234994 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 147.244997 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 147.246995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.277020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.278991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.326102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.327117 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.377021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.379018 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.426991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.426994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 147.428987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.476102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.477196 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 147.477197 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.479000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.484983 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 147.494125 1 1ceb56f4x Rx d 8 02 79 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 147.495123 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.526110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.527081 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.576991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.578993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.626140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.627072 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.677033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.677036 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 147.678996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.726993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.729032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 147.729033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.729034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.734163 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 147.744128 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 147.745124 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.776106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.777100 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.826158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.827107 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.876095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.877070 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.927007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.927012 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 147.929018 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.976160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 147.977191 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 147.977193 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 147.978998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 147.984119 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 147.994107 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 147.995118 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.026093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.027088 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.076114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.077095 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.126091 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.127080 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.177008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.177021 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 148.178990 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.226105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.227241 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 148.227243 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.229005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.235005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 148.244117 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 148.245114 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.276112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.277073 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.326092 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.327101 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.376111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.377062 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.427033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.427036 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 148.428994 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.477026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.479020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 148.479022 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.479023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.484111 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 148.494081 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 148.495146 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.526098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.527058 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.576106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.577059 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.626082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.627090 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.676991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.676993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 148.678983 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.726073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.727193 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 148.727194 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.728992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.734082 1 1ceb56f4x Rx d 8 01 2B 11 A2 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 148.744107 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 148.745123 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.776111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.777057 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.826095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.827045 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.876102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.877064 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.927048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.927051 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 148.928989 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.976106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 148.977110 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 148.978992 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 148.978993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 148.984141 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 148.994089 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 148.995157 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.026094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.027070 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.076087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.077051 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.126086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.127046 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.177020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.177022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 149.179011 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.226085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.227192 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 149.227193 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.228997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.234077 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 149.244072 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 149.245087 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.276073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.277083 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.326062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.327061 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.376131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.377065 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.426246 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.426253 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 149.427080 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.476138 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.477104 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 149.479182 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.479190 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.484103 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 149.494106 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 149.495083 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.526063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.527034 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.576099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.577067 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.626140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.627090 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.676316 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.676325 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 149.726139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.727146 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 149.727148 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.729266 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.734090 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 149.744123 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 149.745072 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.776082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.777015 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.826092 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.827015 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.876152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.878010 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.926194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.926197 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 149.928014 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.976049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 149.977985 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 149.979992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 149.979993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 149.984063 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 149.996012 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 149.996015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.026053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.028020 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.076069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.078020 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.126075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.128005 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.176211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.176214 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 150.177989 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.226062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.228092 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 150.228093 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.228094 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.235129 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 150.244054 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 150.246030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.276048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.278016 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.326061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.328032 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.376086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.377985 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.426172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.426177 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 150.427986 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.476056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.477986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 150.480033 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.480034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.484060 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 150.494077 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 150.496005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.526057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.527994 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.576058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.578021 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.626068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.628027 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.676158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.676161 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 150.678066 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.726023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.727993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 150.727994 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.727995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.734039 1 1ceb56f4x Rx d 8 01 30 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 150.745997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 150.746000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.776045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.777989 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.826050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.828023 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.876032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.877988 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.926151 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.926153 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 150.928011 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.976040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 150.977991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 150.977993 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 150.980001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 150.984065 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 150.994038 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 150.995988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.026073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.027982 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.076090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.078015 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.126039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.127994 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.176132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.176135 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 151.178034 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.226054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.228021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 151.228022 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.228023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.234060 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 151.244022 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 151.246000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.276049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.278012 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.326039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.327990 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.376030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.377988 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.426131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.426134 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 151.428009 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.476048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.478008 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.478009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 151.478009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.484049 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 151.495992 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 151.495994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.526006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.527989 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.576015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.577986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.626037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.627987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.676146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.676151 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 151.677989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.726017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.728006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 151.728010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.728011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.734039 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 151.744041 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 151.745994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.776027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.777989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.826012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.828035 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.876068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.877989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.926095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.926098 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 151.976055 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 151.978021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 151.978022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 151.978023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 151.984020 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 151.994047 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 151.996005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.026041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.028031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.075999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.077993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.125998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.127985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.176145 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.176148 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 152.177990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.226002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.227993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 152.227994 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.227994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.234013 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 152.244057 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 152.246005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.276023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.277989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.326026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.327989 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.376040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.377999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.426065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.426067 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 152.427982 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.476032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.477997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 152.477999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.477999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.484036 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 152.494004 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 152.496003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.525998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.528026 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.576036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.577998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.626002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.627985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.676098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.676100 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 152.677988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.726002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.727992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 152.727993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.727994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.734007 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 152.743996 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 152.746009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.776000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.778003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.825997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.827986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.876005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.877985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.926072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.926075 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 152.975999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 152.978025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 152.978026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 152.978027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 152.984035 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 152.996003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 152.996005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.026011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.028007 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.076032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.077991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.126005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.128032 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.176061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.176063 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 153.226036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.228033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 153.228038 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.228039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.235037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 153.244018 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 153.245994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.276006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.277984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.325997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.328020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.376016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.378009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.426018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.428022 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 153.428023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.475988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.477987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.477988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 153.477989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.484039 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 153.494024 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 153.496004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.525998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.527984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.575993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.578037 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.626003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.628043 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.676216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.676218 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 153.726216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.728030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 153.728031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.729984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.734265 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 153.744282 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 153.746034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.776328 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.777986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.826381 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.828028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.876545 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.878000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.926679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.926682 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 153.928001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.976686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 153.978008 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 153.978009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 153.980029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 153.984723 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 153.994733 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 153.995986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.026805 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.027987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.076868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.078017 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.127004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.127992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.177998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.178000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 154.228017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.230033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.230034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 154.230035 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.236032 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 154.245996 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 154.247989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.278003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.280004 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.327997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.329986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.377998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.379986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.427995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.427997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 154.429986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.478036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.480014 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.480015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 154.480015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.485983 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 154.496882 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 154.496884 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.527994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.530033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.578000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.579985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.628001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.630020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.678137 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.678140 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 154.728144 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.730018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 154.730019 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.732001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.736173 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 154.746214 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 154.747989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.778241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.779986 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.828368 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.830012 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.878451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.879984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.928588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.928593 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 154.929988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.978633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 154.979981 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 154.979983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 154.981983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 154.986636 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 154.996686 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 154.997992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.028719 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.029987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.078788 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.079997 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.128907 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.129985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.179077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.179080 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 155.179996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.229096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.230139 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.230140 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 155.232016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.237086 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 155.247105 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 155.248119 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.279994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.281987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.329998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.332011 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.379995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.381988 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.430001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.430003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 155.432052 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.479986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.481991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.481992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 155.481993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.488024 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 155.498048 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 155.499998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.530002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.531990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.579994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.581994 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.629996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.631987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.680050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.680053 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 155.681996 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.729999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.731990 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.731996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 155.731996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.738037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 155.748001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 155.749990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.780095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.781982 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.830207 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.832021 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.880262 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.881984 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.930412 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.930414 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 155.931982 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.980453 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 155.981991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 155.981992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 155.984018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 155.988459 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 156.000009 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 156.000011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.030549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.031989 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.080585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.081991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.130702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.131986 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.180857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.180860 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 156.181983 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.230860 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.232003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 156.232007 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.233991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.238926 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 156.248896 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 156.249986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.280933 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.282022 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.331024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.332001 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.381109 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.382090 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.432004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.432009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 156.433984 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.481989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.484013 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.484014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 156.484015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.490004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 156.499993 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 156.502013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.532019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.533993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.582000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.583989 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.632027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.633981 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.681991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.681993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 156.684022 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.732000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.734006 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.734007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 156.734008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.740027 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 156.749999 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 156.751988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.782000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.783988 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.832006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.834030 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.882009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.883985 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.932178 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.932181 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 156.933991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.982100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 156.983990 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 156.983991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 156.985994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 156.990113 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 157.000130 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 157.001991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.032236 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.033989 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.082285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.083988 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.132346 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.133991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.182527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.182530 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 157.183983 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.232540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.233992 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.233994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 157.235995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.240577 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 157.250536 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 157.251987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.282606 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.283986 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.332702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.333982 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.382797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.383991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.432932 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.432934 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 157.433983 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.482931 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.484015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.484016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 157.486009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.490921 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 157.502085 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 157.502087 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.533001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.533995 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.583072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.584040 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.634014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.636020 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.684006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.684009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 157.685993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.734023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.736034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 157.736035 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.736036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.742019 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 157.752002 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 157.753998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.784017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.786022 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.833997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.835994 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.883994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.885987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.934006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.934009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 157.935988 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.983996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 157.986003 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 157.986004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 157.986005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 157.991995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 158.001997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 158.003993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.034030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.035992 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.084029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.085997 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.134004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.136024 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.184142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.184147 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 158.185982 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.234064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.236019 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.236020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 158.237994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.242152 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 158.252159 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 158.253988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.284156 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.286029 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.334242 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.336006 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.384285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.386020 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.434543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.434546 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 158.435986 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.484473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.486014 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.486015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 158.488024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.492467 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 158.502485 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 158.503996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.534521 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.536036 1 1812f456x Rx d 8 08 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.584605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.585981 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.634724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.684878 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.684881 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 158.685986 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.734822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.735994 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.735994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 158.738037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.742883 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 158.752856 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 158.754015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.784927 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.786015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.834972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.835984 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.885031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.885999 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.935993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.935996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 158.937996 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.985997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 158.987987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 158.987988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 158.987988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 158.994010 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 159.004003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 159.005994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.035994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.086004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.087987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.136000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.137996 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.185996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.185998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 159.187993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.235995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.238018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 159.238019 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.238019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.244019 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 159.253994 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 159.255987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.285998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.336001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.386032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.388003 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.436007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.436010 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 159.486048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.487993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.487994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 159.487995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.494006 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 159.504023 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 159.505984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.536059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.537992 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.586044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.588029 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.636120 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.637981 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.686196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.687992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 159.736251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.737988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 159.737989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.744261 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 159.754272 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 159.756000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.786319 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.787988 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.836384 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.838027 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.886441 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.936481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.937987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 159.986585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 159.988026 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 159.988027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 159.990018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 159.994618 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 160.004650 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 160.005988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.036622 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.086738 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.087998 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.136792 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.137987 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.186937 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.186939 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 160.236940 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.238009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 160.238011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.244965 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 160.254956 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 160.255988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.286981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.287981 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.337034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.337988 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.387093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.388088 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.437993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.437996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 160.440013 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.488001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.489988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 160.489989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.496018 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 160.506013 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 160.507994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.537996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.537999 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.587996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.638003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.638005 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.687996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.687998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 160.738007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.740004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 160.740005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.746021 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 160.756016 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 160.757986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.788000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.838005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.887998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.889981 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.938029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.938031 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 160.939991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.988027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 160.989989 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 160.989991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 160.989992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 160.995983 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 161.006026 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 161.007993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.038018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.039991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.088003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.089985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.138049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.139984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.178099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.188149 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 161.189998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.238239 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.239984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 161.239985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.246202 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 161.256233 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 161.257982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.288263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.289987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.338341 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.339986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.388411 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.438462 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.440029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.440030 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 161.488502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.489986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 161.489987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.496537 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 161.506512 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 161.507983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.538572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.539991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.588612 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.638716 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.639997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.688943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.688948 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 161.738816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.740024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.740025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 161.741995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.746832 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 161.756849 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 161.757990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.778852 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.790010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.838917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.840000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.889011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.889985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.939064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.940101 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.940103 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 161.989134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 161.989992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 161.991988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 161.991990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 161.997101 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 162.007132 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 162.008121 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.040014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.040019 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.089997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.089999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.140013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.180001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.190004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 162.190006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.240018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.241995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 162.241996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.248030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 162.258002 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 162.259990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.289995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.289997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.340008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.340011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.379996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.390615 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.439997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.440000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.441989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 162.489994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.489996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.492006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 162.492007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.498005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 162.507993 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 162.509993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.540000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.590001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.590003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.640005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.642024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.690005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.692002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.692003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 162.740023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.741998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.741999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 162.742000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.747995 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 162.758003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 162.759991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.780048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.791048 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.840080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.890136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.892029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.940299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.940302 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 162.941983 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 162.990259 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 162.991989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 162.991990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 162.998263 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 163.008270 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 163.009975 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.040438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.040441 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.080339 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.092035 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.140429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.142025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.190480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.191985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.191986 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 163.240567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.241992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.241993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 163.244025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.248533 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 163.258543 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 163.259984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.280583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.292015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.340680 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.341993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.380939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.391121 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.441005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.443052 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.443053 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 163.491232 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.491238 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.495364 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 163.495385 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.500816 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 163.509728 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 163.511826 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.541003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.543031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.580995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.591119 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.640997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.642995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.680997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.691019 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 163.693024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.740123 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 163.741131 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.741132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.749084 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 163.759074 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 163.760998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.791111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.792992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.841189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.842991 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.881211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.891206 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.941244 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.942988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.942989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 163.981277 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.991331 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 163.993000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 163.993001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 163.995002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 163.999330 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 164.009330 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 164.010987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.041547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.041550 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.091398 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.092986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.141473 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.142993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.181491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.191528 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 164.193041 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.241020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 164.242990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.242991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.249584 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 164.259580 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 164.260996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.281603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.291628 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.341681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.342993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.381699 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.391728 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.441794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.442980 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.442981 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 164.481850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.491830 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.492996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 164.492997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.499877 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 164.509841 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 164.510987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.541862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.543016 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.581915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.591982 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.641981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.643016 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.682010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.692060 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 164.693002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.741161 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 164.743028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.743029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.750115 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 164.760104 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 164.761102 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 164.782112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.792121 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.832998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.842999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.883023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.893011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.942997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.944985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.944986 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 164.983003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 164.993011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 164.995009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 164.995011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.001001 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 165.011048 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 165.013037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.043047 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.044988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.082997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.092999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.143003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.144989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.182999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.193000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 165.195015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.241616 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 165.242998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.242999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.251016 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 165.260995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 165.262995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.282998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.293002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.333027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.343006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.345025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.383003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.393000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.432996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.443036 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.444991 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 165.482996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.493028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.495001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 165.495002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.501026 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 165.511002 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 165.512985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.543012 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.544991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.582996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.593020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.632999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.643009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.682995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.693004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 165.695004 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.742575 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 165.743420 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.743421 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.755495 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 165.763737 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 165.772040 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 165.785307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.793196 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.843159 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.845024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.883175 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.893200 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.943208 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.944983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.944984 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 165.983245 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 165.993265 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 165.995012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 165.995014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.001271 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 166.011296 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 166.013012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.033273 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.043336 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.083306 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.093367 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.143401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.144988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.183422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.193432 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 166.195002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.233466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.243003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 166.243005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.251516 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 166.261486 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 166.263006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.283524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.293524 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.343588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.344996 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.383615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.393624 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.433661 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.443654 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 166.444990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.483715 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.493729 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.494996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 166.494997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.501743 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 166.511719 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 166.512986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.543747 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.544983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.583795 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.593798 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.633825 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.643874 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.683857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.693883 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.695004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 166.743008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 166.744984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.744985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.751940 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 166.761963 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 166.762984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 166.783967 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.793974 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.833987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.844019 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.884051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.894059 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.934071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.944093 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.945052 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 166.984105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 166.994995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 166.997033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 166.997035 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.003017 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 167.013000 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 167.014995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.034998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.045008 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.084994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.095017 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.135048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.145010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.185000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.195009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 167.196992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.243375 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 167.244987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.244988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.253011 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 167.263008 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 167.265001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.285003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.295018 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.334999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.345000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.385038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.395021 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.435010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.445043 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.446999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 167.484999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.495002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.496992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 167.496994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.503020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 167.513008 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 167.515014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.534997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.545002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.584988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.595015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.634999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.645024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.685006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.695022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.697017 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 167.743802 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 167.744988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.744989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.753024 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 167.763014 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 167.765030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 167.784998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.795010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.835007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.845025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.885040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.895009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.935000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.945000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.947029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 167.985001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 167.995003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 167.996999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 167.997000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.002999 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 168.012997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 168.015021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.035011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.045032 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.085043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.095097 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.135043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.145085 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.185141 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.195126 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.197005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 168.244994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 168.246997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.246998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.253207 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 168.263179 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 168.264991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.285219 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.295238 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.335234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.345249 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.385283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.395316 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.435347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.445332 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.447018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 168.485340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.494994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 168.496981 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.503393 1 1ceb56f4x Rx d 8 01 26 11 A2 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 168.513409 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 168.514984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.535392 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.545431 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.586993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.595434 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.635452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.645483 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.685518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.695513 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.697014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 168.745037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 168.746987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.746988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.753562 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 168.763604 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 168.764987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 168.785563 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.795585 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.835603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.845634 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.885646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.895661 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.945692 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.946989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.946990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 168.985774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 168.995727 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 168.997022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 168.997023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.003725 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 169.013738 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 169.014989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.035738 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.045762 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.085838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.095812 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.135851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.145857 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.185872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.195917 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.197024 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 169.245043 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 169.246989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.246990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.253944 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 169.263944 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 169.265006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.285917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.295942 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.335977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.345988 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.386017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.396021 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.436068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.446081 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.447056 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 169.486152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.495113 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 169.496993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.504093 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 169.514993 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 169.516994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.546993 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.546996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.586995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.596997 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.636993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.647018 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.686999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.697002 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.699026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 169.737045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.745343 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 169.747019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.755015 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 169.764996 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 169.766998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 169.787043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.796996 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.837016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.847021 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.887004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.897029 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.937396 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.947001 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 169.947003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 169.986997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 169.995481 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 169.996983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.005001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 170.014995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 170.016990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.037007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.047002 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.086997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.097002 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.147003 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.147006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.186981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.197001 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.197003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 170.237614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.245652 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 170.247023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.255022 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 170.264998 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 170.266990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.287033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.297004 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.337016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.347025 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.387000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.397018 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.436990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.447001 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.447004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.449017 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 170.487012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.497025 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.499015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 170.499016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.505049 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 170.515001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 170.516989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.537799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.547012 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.586994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.597001 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.636995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.647013 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.686998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.697043 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.699016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 170.745997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 170.746985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.746989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.755003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 170.765001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 170.767055 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 170.787004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.797009 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.837017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.847047 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.887016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.897065 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.937094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.947107 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 170.949026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 170.987107 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 170.997010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 170.998996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.005171 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 171.015138 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 171.016983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.037150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.047144 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.087205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.097176 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.138993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.147226 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.187238 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.197261 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.199034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 171.237251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.247027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 171.248986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.255356 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 171.265283 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 171.266993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.289000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.297331 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.337327 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.347348 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.387346 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.397397 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.437393 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.447446 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.448996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 171.487451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.497016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 171.499021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.505440 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 171.515469 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 171.516986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.537501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.547473 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.587502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.597530 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.637569 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.647559 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.687543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.697613 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.699024 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 171.739009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.746997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 171.746998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.755600 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 171.765621 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 171.766991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 171.787608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.797650 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.837629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.847683 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.887661 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.897680 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.937712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.947891 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.947893 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 171.987728 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 171.997751 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 171.999014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 171.999015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.005802 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 172.015764 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 172.017006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.037751 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.047778 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.087790 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.097798 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.137822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.147836 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.187901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.198054 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.198059 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 172.237923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.247001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 172.249030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.255918 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 172.265918 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 172.266989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.287958 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.297946 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.338989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.348033 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.388014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.398016 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.438028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.449013 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.449015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 172.488041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.497076 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 172.498989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.506071 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 172.516999 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 172.519023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.538073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.548090 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.588117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.598092 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.638117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.649022 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.688996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.698997 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.698999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 172.739002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.747233 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 172.749026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.756998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 172.767001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 172.769037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 172.788990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.798999 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.838995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.849008 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.888999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.899002 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.938998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.949003 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 172.949005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 172.989005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 172.997361 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 172.999019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.006986 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 173.016997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 173.018992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.038995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.049016 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.089009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.099022 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.139018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.148998 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.188991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.199030 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.199032 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 173.239469 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.247539 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 173.248988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.257011 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 173.266998 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 173.268983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.288998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.299001 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.339037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.349036 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.389003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.399001 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.438995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.449014 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.449020 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 173.488998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.497649 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 173.498983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.507035 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 173.517004 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 173.518990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.539665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.549036 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.588998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.599013 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.638991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.648980 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.688994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.699001 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.699004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 173.739021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.747833 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 173.749022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.757006 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 173.766991 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 173.768987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 173.788998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.799017 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.839841 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.849039 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.888995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.899020 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.938994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.949014 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 173.949017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 173.989018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 173.997942 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 173.999002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.007036 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 174.017007 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 174.019028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.038995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.049029 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.089012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.099019 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.139968 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.148997 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.189022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.199028 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.200980 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 174.239015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.248095 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 174.249031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.257005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 174.267016 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 174.269008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.289051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.299044 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.340104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.349079 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.389085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.399143 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.439142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.449214 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.449216 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 174.489143 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.499010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 174.501023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.507169 1 1ceb56f4x Rx d 8 01 26 11 A2 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 174.517184 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 174.518996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.539194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.549210 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.591028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.599232 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.639263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.649220 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.689279 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.699399 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.699401 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 174.741010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.748994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 174.748995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.757276 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 174.767301 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 174.769018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 174.789309 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.799324 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.839302 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.849394 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.890999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.899357 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.939360 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.949433 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 174.951032 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 174.989402 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 174.999435 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.001000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 175.001001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.007426 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 175.017427 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 175.018993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.040997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.049471 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.089471 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.099451 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.141001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.149504 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.191005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.199594 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.200995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 175.239564 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.248984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 175.248985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.257548 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 175.267556 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 175.268998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.289573 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.299595 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.339602 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.349598 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.389634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.399628 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.439656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.449619 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.450987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 175.489658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.499019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 175.501001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.507753 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 175.517698 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 175.519010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.541001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.549725 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.589702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.599706 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.639712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.649726 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.689763 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.699777 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.700992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 175.739771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.749014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 175.751000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.757803 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 175.767779 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 175.769026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 175.791005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.799818 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.841005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.849823 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.889855 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.899854 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.941006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.949988 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 175.949990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 175.989885 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 175.999016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 176.000997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.007899 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 176.017911 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 176.019013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.039907 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.049967 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.091030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.099985 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.139972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.150003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.189970 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.200092 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.200095 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 176.240997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.249033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 176.251003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.258068 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 176.268046 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 176.269019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.290016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.301018 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.340073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.350086 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.390067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.400080 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.440121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.451040 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.451042 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 176.490134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.499160 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 176.501014 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.501015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.509004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 176.519003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 176.521019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.541138 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.551002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.591174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.601025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.640999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.651033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.690995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.701006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.701009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 176.741031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.749275 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 176.751000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.759020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 176.768995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 176.771025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 176.791045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.801022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.841002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.850997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.890995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.901000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.941329 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.951015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 176.951018 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 176.990996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 176.999404 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 177.000987 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.000989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.008996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 177.018997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 177.021020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.041022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.051033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.090998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.100981 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.141392 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.151006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.190996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.201025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.203005 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 177.241471 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.249519 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 177.250984 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.250985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.259002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 177.268997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 177.270984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.290995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.301019 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.340989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.351028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.390992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.400998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.440995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.451040 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.451042 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 177.490996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.499583 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 177.501047 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.501049 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.509011 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 177.518998 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 177.520992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.541000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.550998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.590993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.600998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.641020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.651008 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.691637 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.701027 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.701029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 177.741674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.749679 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 177.751009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.759020 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 177.769009 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 177.770995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 177.791728 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.801033 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.841676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.851002 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.890983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.900994 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.941763 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.951000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 177.953003 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 177.991747 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 177.999798 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 178.001012 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.001016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.009013 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 178.019003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 178.021020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.041838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.051009 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.091816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.101030 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.140995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.151032 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.191852 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.201030 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.201032 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 178.241017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.249938 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 178.250994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.259020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 178.269012 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 178.271017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.290987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.301022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.341939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.351015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.391989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.401023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.441001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.451064 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.451066 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 178.491989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.500041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 178.501031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.501037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.509001 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 178.519010 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 178.520998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.541990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.551012 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.591040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.601071 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.642036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.651045 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.691041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.701076 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.703005 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 178.742085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.751045 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 178.753034 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.753036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.759114 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 178.769082 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 178.770984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 178.791100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.801099 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.841122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.851128 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.891160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.901149 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.940994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 178.951252 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 178.951254 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 178.991202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.001000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 179.002993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.002995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.009210 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 179.019185 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 179.020993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.041188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.051211 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.092997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.101221 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.142993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.151290 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.193002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.201258 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.203018 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 179.241305 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.251008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 179.253023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.259279 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 179.269288 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 179.271001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.291290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.301301 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.341325 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.351340 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.391354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.401404 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.441394 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.451450 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.451452 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 179.491422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.501019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 179.502986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.502987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.509391 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 179.519398 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 179.520997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.541397 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.551418 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.591411 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.601398 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.641439 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.651467 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.691448 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.701474 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.702995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 179.743016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.751018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 179.751020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.752996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.759560 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 179.769506 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 179.771031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 179.792997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.801481 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.841509 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.851540 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.891532 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.901540 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.941582 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 179.951597 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 179.952989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 179.991592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.001003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 180.003001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.003002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.009575 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 180.019583 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 180.021013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.042993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.051641 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.091615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.101625 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.143005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.151625 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.190996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.201698 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 180.201700 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.241023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.251004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 180.253006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.253007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.259686 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 180.269696 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 180.270984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.290990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.301729 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.341000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.351736 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.391011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.401709 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.441043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.451787 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 180.451789 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.491004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.501003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 180.502986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.502987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.509754 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 180.519775 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 180.520990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.540996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.551790 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.590995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.601846 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.641034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.651808 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.691010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.701869 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.701871 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 180.741016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.751022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 180.751024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.759850 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 180.769868 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 180.770996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 180.791018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.801912 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.841026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.851898 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.891000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.901921 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.940996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 180.951980 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 180.951982 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 180.991009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.001000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 181.002999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.003000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.009988 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 181.019946 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 181.020984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.040993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.052028 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.091003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.102010 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.141015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.152035 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.191036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.202049 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.202051 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 181.241060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.251038 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 181.253011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.260048 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 181.270026 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 181.271044 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.291021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.301997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.341064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.352013 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.391114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.402057 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.441103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.452993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.452995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 181.491144 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.501111 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 181.503009 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.503011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.510063 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 181.520085 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 181.521080 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.541103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.552077 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.591188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.601150 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.641182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.652090 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.691195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.701169 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.702997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 181.741216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.751182 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 181.752997 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.752999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.761004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 181.770134 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 181.771167 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 181.791233 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.801232 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.841231 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.851274 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.891251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.901246 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.941306 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 181.951275 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 181.952986 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 181.991304 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.001268 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 182.003009 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.003010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.011009 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 182.020997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 182.022995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.041311 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.051372 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.091291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.101323 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.141336 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.151353 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.191329 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.201378 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.202987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 182.241360 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.251474 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 182.251476 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.253011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.261019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 182.270998 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 182.272995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.291384 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.301435 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.341396 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.351409 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.391417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.401447 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.441436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.451439 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.452993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 182.491446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.501471 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 182.502997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.502998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.510986 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 182.520994 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 182.522988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.541460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.551465 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.591392 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.601525 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.641432 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.651489 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.691444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.701515 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.702985 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 182.741446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.751600 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 182.751602 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.752990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.761031 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 182.771001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 182.772994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 182.791483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.801623 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.841481 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.851504 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.891524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.901546 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.941518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 182.951540 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 182.952993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 182.991540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.001591 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 183.002986 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.002987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.011001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 183.020995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 183.022989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.041545 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.051567 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.091552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.101547 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.141604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.151586 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.191588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.201592 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.202996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 183.241588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.251606 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 183.252993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.252995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.261017 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 183.270996 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 183.272998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.291618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.301596 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.341636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.351642 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.391642 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.401656 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.441672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.451668 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.452999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 183.491669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.501686 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 183.502993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.502995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.511003 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 183.520997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 183.523022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.541693 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.551709 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.591704 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.601731 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.641733 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.651734 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.691745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.701785 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.702995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 183.741745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.751866 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 183.751868 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.753003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.761023 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 183.771023 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 183.771026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 183.791780 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.801777 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.841778 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.851753 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.891772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.901823 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.941804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 183.951842 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 183.953018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 183.991809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.001845 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 184.002993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.002994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.011023 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 184.020989 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 184.023021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.041803 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.051829 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.091847 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.101934 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.141858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.151847 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.191874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.201890 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.203005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 184.241863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.252030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 184.252033 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.252980 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.261010 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 184.271021 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 184.271023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.291863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.301879 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.341922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.351931 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.391909 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.401943 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.441921 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.451991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.452989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 184.491965 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.501969 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 184.503025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.503026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.510997 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 184.521001 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 184.523014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.541976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.551980 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.591978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.601962 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.642027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.652051 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.691994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.702000 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.702998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 184.742011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.752998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 184.753000 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.753001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.761017 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 184.771030 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 184.773015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 184.792039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.802064 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.842025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.852074 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.892053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.902069 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.942087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 184.952079 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 184.953046 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 184.992105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.003013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 185.003015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.005054 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.011083 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 185.021096 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 185.023022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.042086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.052116 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.093013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.102118 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.142095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.153003 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.193002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.202993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.205004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 185.242998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.253002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 185.253004 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.254997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.261180 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 185.271144 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 185.272990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.293012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.302999 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.342999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.353004 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.392995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.403000 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.442998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.453026 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.454985 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 185.492994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.503007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 185.503009 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.505015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.511278 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 185.521228 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 185.523019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.543007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.553024 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.593024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.603020 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.643010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.653007 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.692998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.703017 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.705001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 185.742986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.752991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 185.752993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.754994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.761347 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 185.771279 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 185.772998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 185.793018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.803020 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.842996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.853023 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.893001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.903002 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.943005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 185.953004 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 185.954986 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 185.993002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.002994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 186.002996 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.005037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.011392 1 1ceb56f4x Rx d 8 01 12 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 186.021354 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 186.022992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.043011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.053004 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.093020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.102998 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.142995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.153026 1 1812f456x Rx d 8 12 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.192996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.202992 1 1812f456x Rx d 8 12 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.204997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 186.242994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.252998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 186.253000 1 1812f456x Rx d 8 12 11 91 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.254992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.261432 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 186.271413 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 186.272996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.293023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.303036 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.342998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.353017 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.392996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.403011 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.442997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.453024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.454986 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 186.492999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.503000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 186.503001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.504998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.511431 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 186.521411 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 186.522987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.543014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.553031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.593015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.603011 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.642996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.653022 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.692997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.703012 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.705035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 186.743030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.753001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 186.753003 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.754988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.761458 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 186.771451 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 186.772999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 186.792998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.803004 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.843001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.853017 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.892998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.903022 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.943000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 186.952985 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 186.954979 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 186.993020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.003012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 187.003014 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.004993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.011527 1 1ceb56f4x Rx d 8 01 12 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 187.021544 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 187.022996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.042994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.052996 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.093013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.102995 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.143025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.153025 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.192999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.203021 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.204991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 187.242996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.253041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 187.253043 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.255003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.261607 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 187.271585 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 187.272990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.292998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.303002 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.343005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.353001 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.392998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.402998 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.443010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.453015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.453017 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 187.493012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.503015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.505001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 187.505002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.511638 1 1ceb56f4x Rx d 8 01 12 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 187.521633 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 187.523001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.542996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.553008 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.593028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.602993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.642996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.653019 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.692999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.703009 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.703018 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 187.743000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.753031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 187.753033 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.755016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.761687 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 187.771706 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 187.772987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 187.792999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.802993 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.843007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.852991 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.893000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.903008 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.942993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 187.953002 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 187.953004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 187.992996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.002997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 188.002998 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.005005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.011739 1 1ceb56f4x Rx d 8 01 12 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 188.021761 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 188.022985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.042993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.053016 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.092989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.103025 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.143001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.153018 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.193014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.202999 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.205030 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 188.242988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.253022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 188.253024 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.254997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.261807 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 188.271788 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 188.272984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.293015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.303015 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.342998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.352995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.393003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.403012 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.442992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.453033 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.454997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 188.492998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.503002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 188.505010 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.505011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.511850 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 188.521853 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 188.523007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.542990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.552992 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.592999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.603029 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.643020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.653039 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.692992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.702994 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.704989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 188.742997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.753030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 188.753032 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.754988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.761915 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 188.771929 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 188.772982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 188.793002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.803025 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.843010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.852998 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.892999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.903003 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.943032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 188.953038 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 188.954997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 188.993002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.002990 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.005037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 189.005038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.011987 1 1ceb56f4x Rx d 8 01 1C 11 A2 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 189.021943 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 189.022988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.043002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.053031 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.093014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.103035 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.142999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.153027 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.193028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.202992 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.204981 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 189.243010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.253141 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 189.253143 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.254982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.261988 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 189.271964 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 189.272983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.293092 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.303015 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.343045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.353020 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.393032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.403052 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.443050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.453049 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.454991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 189.493031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.503065 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 189.504990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.504991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.512018 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 189.522016 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 189.523018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.543060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.553044 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.593081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.603095 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.643087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.653078 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.693066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.703135 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.705009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 189.743125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.753148 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 189.755026 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.755027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.762099 1 1ceb56f4x Rx d 8 01 17 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 189.772069 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 189.772987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 189.793109 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.803157 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.843122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.853118 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.893116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.903165 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.943150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 189.953132 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 189.955041 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 189.993152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.003147 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.004996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 190.004998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.012121 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 190.022096 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 190.023129 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.043134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.053145 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.093153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.103173 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.143193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.153194 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.193204 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.203232 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.205034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 190.243182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.253339 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 190.253341 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.254998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.262997 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 190.272997 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 190.273000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.293191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.303216 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.343188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.353234 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.393244 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.403250 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.443238 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.453372 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.453374 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 190.493214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.503277 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.505032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 190.505033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.513005 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 190.522994 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 190.524995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.543228 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.553232 1 1812f456x Rx d 8 08 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.593263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.603253 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.643264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.653232 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.693251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.703424 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.703426 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 190.743268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.753427 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 190.753429 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.754994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.762981 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 190.773032 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 190.774998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 190.793276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.803269 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.843325 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.853338 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.893304 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.903344 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.943329 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 190.953498 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 190.953500 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 190.993319 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.003500 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.003502 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 191.004989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.013024 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 191.022994 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 191.024996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.043332 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.053334 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.093340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.103364 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.143339 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.153352 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.193331 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.203513 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.203514 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 191.243387 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.253531 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.253533 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 191.254994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.263023 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 191.273000 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 191.274991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.293364 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.303351 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.343363 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.353368 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.393372 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.403369 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.443380 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.453545 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.453547 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 191.493380 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.503535 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.503536 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 191.504994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.513005 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 191.523003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 191.524991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.543403 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.553401 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.593423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.603449 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.643421 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.653421 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.693423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.703527 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.703529 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 191.743438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.753564 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 191.753566 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.754990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.763013 1 1ceb56f4x Rx d 8 01 21 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 191.773004 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 191.773006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 191.793412 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.803476 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.843476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.853478 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.893473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.903460 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.943485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 191.953593 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 191.953595 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 191.993464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.003677 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.003680 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 192.004992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.013015 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 192.022998 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 192.025002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.043501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.053518 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.093511 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.103517 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.143478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.153506 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.193547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.203651 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.203655 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 192.243568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.253655 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 192.253657 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.254994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.263043 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 192.273002 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 192.275031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.293522 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.303521 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.343531 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.353541 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.393527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.403538 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.443558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.453660 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.453662 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 192.493582 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.503722 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.503725 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 192.505002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.513004 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 192.523000 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 192.525033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.543542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.553564 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.593562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.603577 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.643578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.653575 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.693569 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.703727 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.703730 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 192.743587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.753703 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.753706 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 192.755017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.763001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 192.773003 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 192.773005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 192.793619 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.803634 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.843681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.853646 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.893617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.903642 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.943609 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 192.953717 1 1812f456x Rx d 8 1C 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 192.953719 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 192.993622 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.003737 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.003740 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 193.004994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.013027 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 193.022995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 193.024992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.043630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.053655 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.093671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.103660 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.143623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.153633 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.193640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.203746 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.203748 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 193.243645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.253748 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.253750 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 193.254994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.263001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 193.273032 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 193.273038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.293648 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.303647 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.343662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.353670 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.393678 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.403687 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.443687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.453799 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.453801 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 193.493685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.503819 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.503824 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 193.505007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.512999 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 193.523045 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 193.524993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.543731 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.553703 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.593742 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.603695 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.643734 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.653726 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.693730 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.703803 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.703805 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 193.743724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.753813 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.753815 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 193.755000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.762994 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 193.773009 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 193.773011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 193.793771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.803715 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.843737 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.853740 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.893757 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.903760 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.943762 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 193.953861 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 193.953863 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 193.993784 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.003849 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.003851 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 194.005011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.013008 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 194.023011 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 194.024993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.043764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.053787 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.093832 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.103785 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.143790 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.153778 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.193778 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.203869 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.203871 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 194.243774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.253923 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.253926 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 194.255036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.263003 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 194.273022 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 194.273025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.293796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.303790 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.343825 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.353826 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.393796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.403821 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.443833 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.453893 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.453895 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 194.493838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.503906 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.503908 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 194.504987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.513005 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 194.523007 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 194.525000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.543838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.553812 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.593841 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.603824 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.643842 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.653854 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.693844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.703955 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.703957 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 194.743885 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.753976 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.753978 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 194.754997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.763002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 194.772995 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 194.775013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 194.793891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.803865 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.843854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.853905 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.893886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.903902 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.943903 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 194.953953 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 194.953955 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 194.993865 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.003982 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.003985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 195.005019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.013010 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 195.022999 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 195.025000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.043911 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.053888 1 1812f456x Rx d 8 1C 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.093895 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.103890 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.143922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.153916 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.193913 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.203982 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.203984 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 195.243943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.254051 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.254053 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 195.255006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.263003 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 195.273012 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 195.275041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.293950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.303907 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.343938 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.353918 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.393952 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.403967 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.443959 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.454030 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.454032 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 195.493941 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.504072 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.504074 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 195.504993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.513006 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 195.523005 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 195.524997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.543972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.553999 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.593961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.603955 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.643982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.653960 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.693981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.704092 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.704097 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 195.743976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.754103 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.754105 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 195.754989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.763000 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 81 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 195.773000 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 195.774991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 195.793976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.804025 1 1812f456x Rx d 8 12 11 93 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.843969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.854030 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.894016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.903999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.944040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 195.954097 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 195.954099 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 195.994023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.004117 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.004119 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 196.005027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.013012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 196.023015 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 196.025032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.044019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.054010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.094037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.104029 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.144024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.154020 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.194018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.205051 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.205055 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 196.244018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.254993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.254995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 196.254996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.263000 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 196.273025 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 196.275023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.294048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.304040 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.344061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.354062 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.394085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.404037 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.444074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.454128 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.454130 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 196.494067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.505012 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.505014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 196.507020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.513057 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 196.523038 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 196.524991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.544077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.554080 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.594093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.604070 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.644050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.654117 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.694063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.705005 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.705011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 196.744087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.755004 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.755006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 196.757024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.763079 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 196.773048 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 196.774990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 196.794115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.804113 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.844991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.854110 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.894116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.904119 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.944107 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 196.955023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 196.955025 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 196.994097 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.005040 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.005042 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 197.007019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.013106 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 197.023107 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 197.025002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.044997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.054999 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.094136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.105017 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.145005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.154997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.194131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.205001 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.205003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 197.244997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.255010 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.255023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 197.257015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.263150 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 197.273121 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 197.274991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.294125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.305000 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.344997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.355011 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.395001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.405006 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.445016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.454997 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.454999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 197.495006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.504995 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.504997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 197.506998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.513135 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 197.523125 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 197.524994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.545001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.555031 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.595007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.605023 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.645017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.655022 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.695023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.704993 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.704995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 197.745045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.754998 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.755000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 197.756995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.763156 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 197.773214 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 197.774989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 197.795021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.805014 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.845014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.855003 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.895000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.904990 1 1812f456x Rx d 8 12 11 92 0D 35 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.945001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 197.955033 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 197.955035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 197.994992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.005022 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.005024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 198.006993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.013203 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 198.023187 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 198.024985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.045006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.055014 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.094995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.104991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.145002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.155022 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.194996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.205007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.205009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 198.244996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.255034 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.255037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 198.256999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.263209 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 198.273222 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 198.274994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.295014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.304995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.344992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.354991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.395006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.404992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.444995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.454998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.455000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 198.494995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.504996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.504998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 198.506995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.513254 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 198.523253 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 198.524990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.544998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.555010 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.595008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.604992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.645045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.655011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.695003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.705020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.705022 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 198.744999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.755025 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.755027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 198.756989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.763308 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 198.773270 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 198.774994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 198.795012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.804999 1 1812f456x Rx d 8 12 11 93 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.844997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.855023 1 1812f456x Rx d 8 12 11 93 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.894998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.905009 1 1812f456x Rx d 8 12 11 93 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.944997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 198.955027 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 198.955028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 198.994992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.005020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.005022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 199.005022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.013335 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 199.023303 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 199.024986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.044999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.055014 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.095019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.105005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.144999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.154991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.195008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.204994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.204996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 199.245030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.254998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.254999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 199.255000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.263385 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 199.273325 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 199.275031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.295046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.304998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.344998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.355006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.394996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.405021 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.445017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.455009 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.455011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 199.495002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.504995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.504997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 199.507015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.513342 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 199.523369 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 199.524982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.545002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.554992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.595006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.605014 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.644999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.655006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.695029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.704990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.704993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 199.744996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.755019 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.755021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 199.755022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.763365 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 199.773408 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 199.775007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 199.794994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.805015 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.845001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.855030 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.895013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.905004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.944998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 199.954998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 199.955000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 199.994994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.004998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.005000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 200.005001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.013389 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 200.023380 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 200.025024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.045001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.055022 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.095015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.105004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.144996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.155029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.195017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.205024 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.205026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 200.245002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.255026 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.255028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 200.257002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.263418 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 200.273393 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 200.274988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.294999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.304998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.345017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.355002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.395008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.405007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.444995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.454998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.455000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 200.495007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.504999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.505001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 200.505001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.513461 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 200.523428 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 200.525007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.545002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.555039 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.595022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.604996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.645013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.654996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.694992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.705029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.705031 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 200.744998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.755030 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.755032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 200.755032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.763463 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 200.773485 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 200.774987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 200.794997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.805022 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.845034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.854995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.894996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.904998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.944997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 200.955022 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 200.955024 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 200.995021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.005023 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.005026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 201.007002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.013511 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 201.023495 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 201.024991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.044996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.054998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.095001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.105000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.144997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.154992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.195007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.205024 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.205026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 201.244990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.255037 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.255039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 201.255039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.263506 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 201.273496 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 201.275017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.295004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.304997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.345005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.355016 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.394998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.405021 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.445000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.454996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.454998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 201.494999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.503484 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.504989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 201.507030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.513498 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 201.523506 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 201.525007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.544997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.554986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.594993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.603508 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.645026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.653506 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.694993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.703499 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.704995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 201.744994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.753512 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.754998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 201.754999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.763559 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 201.773533 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 201.774987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 201.795021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.803517 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.845032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.853505 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.895027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.903502 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.945010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 201.953499 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 201.954989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 201.994999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.003518 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.005001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 202.007017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.013527 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 202.023528 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 202.025017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.045004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.053489 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.095006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.103539 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.145006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.153503 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.194997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.203517 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.205004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 202.244995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.253512 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.254999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 202.255000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.263585 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 202.273603 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 202.274996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.295005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.303545 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.345010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.353551 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.395003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.403549 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.445007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.453546 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.454989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 202.495005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.503571 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.505004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 202.507056 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.513588 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 202.523558 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 202.525027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.544996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.553551 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.595014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.603547 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.645038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.653597 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.694997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.703598 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.705019 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 202.744997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.753553 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.755030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 202.755032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.763610 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 202.773624 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 202.775014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 202.795005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.803589 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.845007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.853612 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.894992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.903570 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.945005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 202.953604 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 202.955029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 202.995003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.003580 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.004998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 203.007004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.013657 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 203.023654 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 203.024997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.045011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.053618 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.095024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.103595 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.145024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.153609 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.195016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.203600 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.205001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 203.245007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.253626 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.255017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 203.256995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.263641 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 203.273628 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 203.274995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.294995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.303606 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.345014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.353602 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.394995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.403640 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.445018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.453635 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.454991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 203.494995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.503617 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.504990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 203.507001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.513621 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 203.523627 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 203.524991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.545015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.553625 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.594996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.603630 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.644994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.653614 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.695027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.703624 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.705019 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 203.745008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.753686 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.755134 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 203.755140 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.763684 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 203.773668 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 203.774992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 203.795010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.803636 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.845009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.853667 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.895010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.903650 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.944997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 203.953642 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 203.955031 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 203.995005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.003672 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.005772 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 204.005774 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.013724 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 204.023696 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 204.025013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.045003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.053633 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.095002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.103654 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.144994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.153657 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.195001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.203661 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.204993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 204.245000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.253667 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.254996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 204.254998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.263693 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 204.273702 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 204.275034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.295001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.303655 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.345022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.353663 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.395007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.403682 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.444995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.453671 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.455009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 204.495011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.503710 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.505043 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 204.506984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.513707 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 204.523673 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 204.524997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.545004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.553685 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.594997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.603696 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.644997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.653702 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.695009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.703706 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.705006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 204.745003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.753689 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.755013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 204.755017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.763721 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 204.773700 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 204.775000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 204.794999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.803693 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.845032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.853715 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.894995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.903723 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.944995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 204.953711 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 204.955034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 204.995048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.003720 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.005003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 205.007039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.013762 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 205.023743 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 205.025024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.044995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.053721 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.094998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.103759 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.145022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.153748 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.195000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.203741 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.204985 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 205.245035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.253731 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.254988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 205.254989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.263739 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 205.273740 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 205.274996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.295020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.303731 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.345031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.353781 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.395000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.403742 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.444998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.453731 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.454990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 205.495000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.503706 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.505815 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 205.505816 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.513792 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 205.523748 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 205.525004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.545006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.553779 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.594993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.603749 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.645001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.653748 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.695002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.703768 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.705011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 205.744996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.753777 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.754997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 205.754998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.763758 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 205.773807 1 1ceb56f4x Rx d 8 02 78 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 205.774992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 205.794996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.803812 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.845017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.853765 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.895016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.903775 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.945003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 205.953755 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 205.954996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 205.994996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.003783 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.005005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 206.007028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.013817 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 206.023782 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 206.024991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.044997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.053786 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.095000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.103776 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.145008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.153802 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.195020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.203786 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.204990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 206.244997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.253782 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.254996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 206.254997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.263801 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 206.273818 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 206.274996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.295002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.303796 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.345007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.353753 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.394998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.403777 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.445012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.453838 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.454987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 206.495000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.503790 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.505016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 206.507037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.513803 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 206.523786 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 206.524987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.545012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.553830 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.594998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.603814 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.644995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.653798 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.694995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.703819 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.704996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 206.744996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.753818 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.755004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 206.755005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.763891 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 206.773871 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 206.774987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 206.795009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.803828 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.845045 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.853835 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.894999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.903807 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.944988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 206.953833 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 206.954990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 206.995002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.003829 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.005006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 207.007001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.013837 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 207.023809 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 207.024993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.044998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.053851 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.094999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.103836 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.145002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.153846 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.195006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.203828 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.204998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 207.245028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.253812 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.255047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 207.255051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.263864 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 207.273834 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 207.275037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.294999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.303840 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.345039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.353844 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.394996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.403846 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.445001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.453835 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.455008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 207.494995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.503847 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.504995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 207.507052 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.513855 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 207.523875 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 207.525024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.545010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.553871 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.594995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.603841 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.645020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.653863 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.695007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.703856 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.705024 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 207.745029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.753864 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.755043 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 207.755044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.763863 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 207.773933 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 207.774991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 207.794998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.803826 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.844997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.853846 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.894995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.903859 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.945016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 207.953850 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 207.955014 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 207.994998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.003858 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.005003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 208.006992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.013875 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 208.023910 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 208.025128 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.045000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.053838 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.094984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.103881 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.145000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.153882 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.195035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.203901 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.205016 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 208.244997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.253893 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.255005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 208.256989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.263895 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 208.273909 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 208.274983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.295011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.303838 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.344997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.353860 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.395015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.403902 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.445008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.453890 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.455004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 208.494997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.503871 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.505064 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 208.507039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.513893 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 208.523916 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 208.524989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.545005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.553870 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.594995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.603910 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.644995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.653892 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.695030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.703879 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.704992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 208.745009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.753913 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.755017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 208.756995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.763888 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 208.773900 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 208.774987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 208.795002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.803914 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.845006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.853894 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.894992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.903882 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.945015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 208.953916 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 208.954991 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 208.995003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.003907 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.005004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 209.007024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.013942 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 209.023908 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 209.024985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.045000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.053929 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.094997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.103888 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.145000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.153891 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.195005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.203919 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.204988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 209.245040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.253917 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.255021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 209.257019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.263925 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 209.273951 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 209.274984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.294996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.303909 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.345006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.353913 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.395033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.403922 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.445002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.453909 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.455029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 209.494995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.503918 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.505029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 209.507038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.513980 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 209.523948 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 209.525001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.544996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.553938 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.594998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.603939 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.645011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.653903 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.694998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.703996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.705002 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 209.744982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.753915 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.754986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 209.757012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.763941 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 209.773982 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 209.775003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 209.794998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.803919 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.844991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.853944 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.895002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.903955 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.945026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 209.953915 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 209.955001 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 209.995003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.003927 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.005008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 210.007027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.013956 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 210.023956 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 210.024994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.045005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.053936 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.095040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.103944 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.144987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.153938 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.195020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.203947 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.204988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 210.244995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.253965 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.254992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 210.256996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.264003 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 210.274106 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 210.274108 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.295021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.303946 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.344997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.353960 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.395017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.403949 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.444997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.453980 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.455019 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 210.494998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.503947 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.505017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 210.507034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.514019 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 210.523974 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 210.525034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.545006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.553939 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.595023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.603965 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.645035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.653976 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.695004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.703949 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.704982 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 210.745031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.754011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.755117 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 210.755118 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.763976 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 210.774013 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 210.774990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 210.795046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.803968 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.845023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.853970 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.894998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.903988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.945010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 210.953955 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 210.955004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 210.995013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.003982 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.004990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 211.007007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.013981 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 211.023972 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 211.024986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.045010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.054031 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.095009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.103992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.145054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.153989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.195042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.203966 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.204985 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 211.245043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.253999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.255021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 211.257033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.264029 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 211.274102 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 211.274104 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.295024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.303975 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.345044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.353997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.395007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.403959 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.445047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.454030 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.455000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 211.495026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.504004 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.504990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 211.507034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.514027 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 211.524048 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 211.525021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.545026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.553995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.595028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.604016 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.645023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.653996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.695027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.703992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.705019 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 211.745030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.753988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.755017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 211.757022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.764000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 211.775020 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 211.775023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 211.795020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.803989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.845011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.854012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.895033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.904026 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.945059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 211.953991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 211.955003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 211.995072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.003990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.006113 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 212.006114 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.014049 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 212.024037 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 212.025015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.045018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.053991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.095028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.103990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.145048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.153997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.195072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.204007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.205013 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 212.245037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.254008 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.255153 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 212.255154 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.264017 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 212.274001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 212.274982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.295020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.304028 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.345071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.354014 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.395103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.404015 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.445040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.453992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.454995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 212.495086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.504007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.505013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 212.507025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.514045 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 212.524029 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 212.524994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.545035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.554006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.595087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.604046 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.645037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.654017 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.695078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.703994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.705017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 212.745047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.754045 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.755030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 212.757006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.764029 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 212.775042 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 212.775044 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 212.795057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.804045 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.845047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.854021 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.895074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.904031 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.945075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 212.954044 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 212.955049 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 212.995070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.004034 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.005046 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 213.007037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.014076 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 213.024086 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 213.025025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.045059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.054012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.095065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.104035 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.145070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.154051 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.195077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.204050 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.205050 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 213.245052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.254054 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.255162 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 213.255163 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.264048 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 213.275010 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 213.275013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.295056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.304038 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.345053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.354006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.395094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.404026 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.445066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.454013 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.455053 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 213.495096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.504084 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.505069 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 213.507022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.514045 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 213.524081 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 213.525067 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.545064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.554041 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.595104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.604063 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.645076 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.654052 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.695082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.704032 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.705067 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 213.745085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.754038 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.755176 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 213.755180 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.764044 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 213.774119 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 213.774979 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 213.795069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.804025 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.845102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.854027 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.895083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.904051 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.945059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 213.954043 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 213.955106 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 213.995052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.004044 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.005057 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 214.006990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.014112 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 214.024107 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 214.025067 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.045127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.054059 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.095095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.104065 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.145073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.154046 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.195135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.204048 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.205057 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 214.245080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.254034 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.255068 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 214.257005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.264079 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 214.274999 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 214.275001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.295096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.304054 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.345072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.354079 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.395123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.404059 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.445118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.454085 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.455089 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 214.495122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.504095 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.505072 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 214.507008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.514098 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 214.524078 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 214.525057 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.545125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.554069 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.595101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.604063 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.645131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.654069 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.695100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.704059 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.705105 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 214.745133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.754063 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.755216 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 214.755220 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.764129 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 214.775001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 214.775004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 214.795112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.804079 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.845097 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.854073 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.895123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.904079 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.945134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 214.954055 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 214.955041 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 214.995149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.004103 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.005096 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 215.007002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.014108 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 215.024096 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 215.024971 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.045109 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.054058 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.095115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.104077 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.145091 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.154075 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.195158 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.204092 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.205123 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 215.245139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.254108 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.255250 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 215.255251 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.264116 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 215.275032 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 215.275034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.295142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.304070 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.345134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.354081 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.395125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.404101 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.445153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.454076 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.455101 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 215.495125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.504098 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.505102 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 215.507026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.514123 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 215.524086 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 215.524986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.545121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.554082 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.595120 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.604062 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.645141 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.654094 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.695146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.704100 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.705108 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 215.745162 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.754086 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.755096 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 215.756986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.764106 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 215.774991 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 215.774992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 215.795122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.804078 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.845115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.854107 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.895149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.904088 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.945148 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 215.954115 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 215.955105 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 215.995155 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.004089 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.005119 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 216.006995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.014133 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 216.024111 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 216.024988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.045126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.054087 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.095170 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.104108 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.145132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.154092 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.195127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.204064 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.205160 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 216.245129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.254994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.257063 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 216.257065 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.265004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 216.274993 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 216.274996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.295124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.304104 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.345133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.354101 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.395160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.404093 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.445119 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.454077 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.455091 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 216.495124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.504088 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.505094 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 216.507014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.514103 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 216.524118 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 216.524997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.545123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.554112 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.595147 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.604106 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.645136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.654089 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.695134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.704106 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.705104 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 216.745224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.754140 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.755227 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 216.755230 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.764139 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 216.774997 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 216.774999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 216.795144 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.804097 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.845154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.854114 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.895189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.904149 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.945169 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 216.954093 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 216.955126 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 216.995195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.004121 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.005112 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 217.006994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.015058 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 217.025001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 217.027033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.045171 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.054995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.095164 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.105001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.145132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.154112 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.195163 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.204113 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.205110 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 217.245127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.254117 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.255154 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 217.257025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.265025 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 217.275006 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 217.275009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.295170 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.304117 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.345182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.354108 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.395122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.404085 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.445193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.454100 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.455121 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 217.495142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.504094 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.505114 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 217.507004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.514240 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 217.524129 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 217.524999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.527026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 217.527028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.534989 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 217.544998 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 217.545000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.546986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.554132 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.595196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.604103 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.645150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.654092 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.695205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.704998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.707001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 217.745152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.755004 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.756994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 217.756995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.764120 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 217.775000 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 217.775003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 217.795192 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.804093 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.845194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.854109 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.895179 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.904096 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.945169 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 217.954148 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 217.955148 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 217.995174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.004110 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.007040 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 218.007042 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.015007 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 218.024152 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 218.024989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.045166 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.054996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.095175 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.104116 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.145139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.154990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.195140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.204110 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.205137 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 218.245178 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.254993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.257036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 218.257037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.265031 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 218.275009 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 218.275011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.295167 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.304109 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.345173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.354122 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.395176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.404102 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.445176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.454119 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.455157 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 218.495180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.505021 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.506998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 218.507000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.515008 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 218.525013 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 218.525015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.545152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.554115 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.595173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.605001 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.645146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.654998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.695191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.704125 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.705138 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 218.745186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.754989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.757004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 218.757006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.765037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 218.775010 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 218.775012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 218.795167 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.804994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.845182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.854991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.895219 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.905014 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.945155 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 218.954110 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 218.955149 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 218.995159 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.004130 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.005160 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 219.007029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.015004 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 219.025006 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 219.025009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.045163 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.055017 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.095173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.104991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.145149 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.154986 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.195168 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.204999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.207000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 219.245160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.254988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.256989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 219.256990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.265030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 219.275003 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 219.275005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.295203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.305005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.345171 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.355038 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.395179 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.405030 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.445174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.454996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.457002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 219.495155 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.505054 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.507007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 219.507009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.515020 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 219.525014 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 219.525016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.545144 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.554994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.595172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.605027 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.645172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.655003 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.695152 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.705007 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.707006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 219.745161 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.754999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.757003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 219.757005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.765008 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 219.774982 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 219.774984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 219.795217 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.804998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.845177 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.855005 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.895157 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.904108 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.945172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 219.955011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 219.956993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 219.995193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.004987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.007037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 220.007038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.015006 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 220.025018 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 220.025021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.045209 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.054121 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.095198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.105002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.145197 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.154993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.195195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.205015 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.207007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 220.245203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.255009 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.257019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 220.257020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.264997 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 220.275020 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 220.275023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.295223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.304998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.345208 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.355008 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.395181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.404994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.445227 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.455004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.456998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 220.495175 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.505029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.507009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 220.507011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.515002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 220.525014 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 220.525016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.545229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.553177 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.595191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.603180 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.645196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.653152 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.695194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.703160 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.705152 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 220.745173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.753181 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.755241 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 220.755242 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.765020 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 220.775014 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 220.775016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 220.795177 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.803165 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.845173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.853177 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.895202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.903137 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.945183 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 220.953150 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 220.955149 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 220.995176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.003178 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.005164 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 221.007024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.015022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 221.025026 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 221.027036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.045225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.053152 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.095180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.103164 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.145165 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.153171 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.195228 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.203220 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.205162 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 221.245210 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.253152 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.255266 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 221.255267 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.264985 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 221.274997 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 221.274999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.295191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.303150 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.345193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.353208 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.395205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.403164 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.445257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.453204 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.455151 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 221.495194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.503162 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.505189 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 221.507007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.515019 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 221.525027 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 221.525029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.545222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.553148 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.595188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.603185 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.645217 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.653163 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.695191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.703187 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.705227 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 221.745173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.753177 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.755208 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 221.757003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.765022 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 221.775008 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 221.775011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 221.795219 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.803177 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.845213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.853223 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.895192 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.903207 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.945200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 221.953230 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 221.955161 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 221.995214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.003193 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.005208 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 222.006997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.015026 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 222.025011 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 222.025014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.045183 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.053187 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.095203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.103211 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.145194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.153195 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.195207 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.203211 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.205206 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 222.245213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.253186 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.255285 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 222.255286 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.265025 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 222.275043 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 222.275045 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.295210 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.303221 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.345194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.353208 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.395233 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.403211 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.445221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.453177 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.455209 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 222.495210 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.503214 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.505201 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 222.507032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.515004 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 222.525014 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 222.525016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.545234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.553229 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.595225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.603192 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.646016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.653997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.696010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.703986 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.706004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 222.746003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.754010 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.755994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 222.755996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.764275 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 222.774277 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 222.774279 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 222.796019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.804039 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.846001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.853994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.896023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.903990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.946017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 222.954025 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 222.955984 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 222.996012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.003999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.006006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 223.006007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.014281 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 223.024277 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 223.024280 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.046013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.053993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.095997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.103993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.146001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.154031 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.196001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.204019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.206038 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 223.246014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.254029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.256007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 223.256009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.264273 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 223.274287 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 223.274290 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.296016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.303992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.346001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.354005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.396019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.404121 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.445388 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.454005 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.456007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 223.496020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.504012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.506066 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 223.506068 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.514274 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 223.524314 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 223.524317 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.546037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.553993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.596002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.603999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.646021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.653998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.696009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.703986 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.705987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 223.746005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.753995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.756008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 223.756010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.764307 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 223.774291 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 223.774293 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 223.795995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.803991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.845997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.854038 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.895993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.903990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.946019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 223.954001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 223.956023 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 223.995998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.003991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.006240 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 224.006242 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.014230 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 224.024311 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 224.024314 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.046026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.053989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.096002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.103990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.146041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.154023 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.196004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.203993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.206007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 224.246010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.254012 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.256011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 224.256013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.264227 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 224.274280 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 224.274283 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.296015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.303999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.345996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.353993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.396002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.404000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.446033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.454029 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.455987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 224.495998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.503992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.505993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 224.505995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.514183 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 224.524344 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 224.524347 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.545999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.554006 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.596014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.604005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.646009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.654006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.696003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.704000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.705990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 224.746004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.754035 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.756031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 224.756033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.764186 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 224.774280 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 224.774282 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 224.795997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.803993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.846003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.854008 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.896002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.903994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.945988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 224.953993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 224.956022 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 224.996031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.004000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.006015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 225.006023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.014184 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 225.024291 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 225.024294 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.046007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.054015 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.095995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.103997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.145998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.154018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.196010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.203990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.206018 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 225.246039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.253988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.255997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 225.255998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.264201 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 225.274292 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 225.274295 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.296007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.303991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.345998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.353996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.395996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.403989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.446007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.453988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.455998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 225.496013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.503985 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.506010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 225.506011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.514212 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 225.524218 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 225.526041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.546025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.554025 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.595989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.603999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.646003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.653997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.696011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.703998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.706017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 225.746047 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.754011 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.756021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 225.756023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.764205 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 225.774318 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 225.774321 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 225.796049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.804011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.846043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.854017 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.896004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.903990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.945999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 225.954019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 225.955993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 225.996017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.003992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.006020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 226.008018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.014200 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 226.024307 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 226.024310 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.046021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.053994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.096006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.103999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.146020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.154016 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.196000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.204005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.206004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 226.245999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.253994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.256004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 226.256006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.264196 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 226.274337 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 226.274339 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.296001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.303992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.345991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.353988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.395997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.404013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.446006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.454010 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.455998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 226.496000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.504016 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.506035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 226.506037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.514217 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 226.524349 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 226.524351 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.546002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.553999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.596001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.603992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.645996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.654020 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.696000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.703989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.705999 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 226.746002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.754031 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.755984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 226.755985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.764226 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 226.774343 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 226.774345 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 226.796004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.804010 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.846015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.854011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.896001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.903990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.945993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 226.954001 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 226.955993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 226.995992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.003992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.006024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 227.006025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.014227 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 227.024223 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 227.025985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.045992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.053989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.096005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.104002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.146014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.153993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.196003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.203992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.206029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 227.246003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.253992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.255990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 227.255991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.264229 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 227.274303 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 227.274306 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.296015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.303998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.346001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.353991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.395998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.403993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.446025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.453987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.456032 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 227.496000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.503999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.505998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 227.508001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.514264 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 227.524304 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 227.524311 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.546021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.554000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.596022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.603992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.646002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.653992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.696011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.703993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.705998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 227.746037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.753994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.756028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 227.756034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.764215 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 227.774390 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 227.774392 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 227.795997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.804007 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.845997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.853987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.896000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.903994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.945998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 227.953991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 227.956008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 227.995997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.003994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.006030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 228.006031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.014247 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 228.024289 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 228.024292 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.046010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.053995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.096007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.104009 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.145995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.153999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.195997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.204017 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.205987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 228.246000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.254048 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.255983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 228.255984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.264260 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 228.274315 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 228.274317 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.296000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.303995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.346005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.353997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.395998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.404018 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.446008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.454018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.455995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 228.495995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.503997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.506023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 228.506024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.514253 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 228.524289 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 228.526018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.546010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.553989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.596022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.603996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.646027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.653993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.695994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.703986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.706002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 228.745988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.753989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.756021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 228.756023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.764237 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 228.774293 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 228.774296 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 228.795999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.803987 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.846030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.853995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.896017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.904003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.945998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 228.953987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 228.956030 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 228.995987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.003982 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.006268 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 229.006270 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.014245 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 229.024347 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 229.024350 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.045999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.053990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.096042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.104012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.146039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.153989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.196001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.203996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.206026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 229.245998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.254020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.256014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 229.256019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.264176 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 229.274299 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 229.274302 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.296012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.303987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.346024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.354033 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.396001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.403997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.446001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.453994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.455992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 229.496022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.503999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.506038 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 229.506039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.514215 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 229.524288 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 229.524290 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.545999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.553992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.595992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.603980 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.645999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.653991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.696018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.703986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.706026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 229.746000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.753990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.755985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 229.755988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.764179 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 229.774292 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 229.774295 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 229.795998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.803989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.845998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.853990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.895995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.903986 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.946054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 229.954035 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 229.956005 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 229.995991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.003989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 230.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.014199 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 230.024180 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 230.026028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.045999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.054029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.095997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.103985 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.146002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.153989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.196000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.203994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.205991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 230.246043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.254018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.255985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 230.255986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.264219 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 230.274309 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 230.274317 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.295998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.303993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.345995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.353999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.395998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.403992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.446014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.454005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.455997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 230.496004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.503994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.506008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 230.506010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.514181 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 230.524291 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 230.524293 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.545998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.553991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.595998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.603990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.645988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.654013 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.695997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.704004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.706066 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 230.745995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.753995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.756004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 230.756005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.764151 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 230.774326 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 230.774329 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 230.796015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.803994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.846038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.854015 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.895992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.904018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.946001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 230.954000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 230.955988 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 230.996023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.003993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.006003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 231.006004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.014202 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 231.024335 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 231.024338 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.046003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.053988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.096011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.104013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.146033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.153996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.196004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.204012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.206024 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 231.246054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.253996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.255985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 231.255986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.264194 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 231.274311 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 231.274313 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.295998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.304005 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.345990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.353992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.396006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.404000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.445999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.453998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.456011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 231.496010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.503991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.505991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 231.505992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.514199 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 231.524337 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 231.524339 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.546002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.553992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.596001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.603993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.646003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.653990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.696015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.703997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.705990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 231.746007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.753997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.756023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 231.756024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.764156 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 231.774341 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 231.774343 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 231.796004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.803994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.845996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.854005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.896022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.903995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.946031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 231.953995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 231.955986 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 231.996034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.003991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.006032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 232.008004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.014176 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 232.024392 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 232.024394 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.046034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.054002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.096016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.103992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.146043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.153996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.196010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.203994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.206015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 232.246022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.254024 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 232.255988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.264156 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 232.274293 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 232.274295 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.295998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.304003 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.346003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.354023 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.395995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.404003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.445998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.453989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.455997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 232.495999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.504025 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.505998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 232.506000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.514191 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 232.524285 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 232.524287 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.546036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.554023 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.595996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.603991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.646005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.653998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.695998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.703996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.706000 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 232.746012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.753993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.756023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 232.756025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.764166 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 232.774251 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 232.774254 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 232.796002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.803994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.846032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.854000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.895999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.903987 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.945998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 232.953995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 232.956003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 232.996015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.004001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.005985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 233.005986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.014205 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 233.024279 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 233.024282 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.046002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.053991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.096015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.104000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.145994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.153122 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.195998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.203120 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.206017 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 233.245997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.253996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.256029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 233.256033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.264145 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 233.274255 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 233.274258 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.296011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.304001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.346005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.353996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.395999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.403994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.446005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.453991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.455997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 233.496002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.503129 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.506005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 233.506006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.514183 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 233.524269 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 233.524272 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.546013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.554002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.596009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.604001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.645999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.653991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.695998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.703993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.706026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 233.745997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.754003 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.755989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 233.755991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.764143 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 233.774280 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 233.774285 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 233.796006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.804021 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.845989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.853991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.896018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.903149 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.945996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 233.953987 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 233.955990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 233.995994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.003990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.005985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 234.005986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.014166 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 234.024260 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 234.024263 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.046010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.053991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.096001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.103999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.145996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.153993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.195999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.203993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.205987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 234.246011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.253127 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.255993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 234.255995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.264143 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 234.274256 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 234.274259 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.296022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.303989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.346019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.353989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.396009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.403999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.446001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.453114 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.456001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 234.496002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.503986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.506004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 234.506005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.514157 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 234.524272 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 234.524275 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.546026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.553995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.596003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.603993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.646006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.653987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.696012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.703998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.706033 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 234.745994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.754003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.755996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 234.755997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.764157 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 234.774334 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 234.774337 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 234.795989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.803987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.846048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.853992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.896001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.903997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.946039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 234.953995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 234.955989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 234.995994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.003986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.006002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 235.006004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.014154 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 235.024255 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 235.024257 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.046003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.053993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.095995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.104017 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.146013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.153114 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.196026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.203993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.205990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 235.245999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.254007 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.255985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 235.255987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.264176 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 235.274254 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 235.274257 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.296002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.303996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.345997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.353109 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.395993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.403128 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.445997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.453989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.455991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 235.495993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.503110 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.506063 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 235.506067 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.514165 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 235.524258 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 235.524260 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.545993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.554025 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.596000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.603985 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.645994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.653158 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.695997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.703990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.706030 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 235.745999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.753104 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.755992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 235.755994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.764129 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 235.774240 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 235.774243 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 235.795995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.803116 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.846001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.853118 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.895995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.903995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.946001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 235.954038 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 235.955982 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 235.995997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.003992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.006030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 236.006031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.014144 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 236.024228 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 236.024230 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.046005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.053130 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.096006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.103102 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.146005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.153123 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.196001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.203112 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.205119 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 236.245995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.254004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.256028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 236.256030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.264157 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 236.274246 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 236.274249 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.295996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.303989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.345990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.353122 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.396002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.403123 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.445131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.453115 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.455107 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 236.495996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.503999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.506211 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 236.506212 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.514128 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 236.524252 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 236.524254 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.545993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.554030 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.596000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.603996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.646005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.653110 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.695995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.703122 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.705110 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 236.745999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.753127 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 236.755993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.764151 1 1ceb56f4x Rx d 8 01 12 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 236.774238 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 236.774241 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 236.795991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.803103 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.846011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.853994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.895143 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.903996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.945996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 236.953142 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 236.955993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 236.995997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.003104 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.005989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 237.005991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.014181 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 237.024255 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 237.024258 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.046030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.053110 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.096000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.103996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.145994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.153991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.195998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.203100 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.206000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 237.245998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.253109 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.255999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 237.256001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.264151 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 237.274207 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 237.274210 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.295150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.303092 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.346003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.353120 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.395996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.403115 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.445133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.453098 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.455095 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 237.496042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.503132 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.506005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 237.506007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.514121 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 237.524219 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 237.524221 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.545999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.553991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.595999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.603092 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.645114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.653119 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.695993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.703094 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.705120 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 237.746006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.753114 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.756003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 237.756004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.764117 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 237.774240 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 237.774243 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 237.796002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.804028 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.845129 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.853108 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.896008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.903089 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.946006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 237.953105 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 237.955995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 237.995131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.003075 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.005105 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 238.005995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.014124 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 238.024189 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 238.024192 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.045986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.053118 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.095132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.103117 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.146006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.153093 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.195997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.203141 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.206009 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 238.245999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.253121 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.255999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 238.256001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.264113 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 238.274248 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 238.274250 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.296019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.303099 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.345999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.353113 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.395995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.403066 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.445997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.453112 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.456024 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 238.496005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.503094 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.506000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 238.506001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.514107 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 238.524215 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 238.524218 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.545998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.553111 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.595130 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.604001 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.645124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.653079 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.695139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.703104 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.706017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 238.745115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.753109 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.755997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 238.755998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.764126 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 238.774233 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 238.774236 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 238.796005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.803098 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.845993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.853101 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.895127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.903105 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.945121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 238.953096 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 238.955082 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 238.995128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.003095 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.006019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 239.006021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.014131 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 239.024196 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 239.024199 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.046001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.053073 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.095126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.103088 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.145125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.153120 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.195133 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.203086 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.205145 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 239.245131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.254011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.255986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 239.255988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.264138 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 239.274204 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 239.274206 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.296000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.303104 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.345128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.353071 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.396008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.403077 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.445110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.453078 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.455097 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 239.496003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.503089 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.505992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 239.505993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.514140 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 239.524233 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 239.524236 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.545994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.552141 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.595125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.602109 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.645093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.652105 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.695995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.702130 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.705136 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 239.746004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.752108 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.755997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 239.755998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.764112 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 239.774237 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 239.774240 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 239.795119 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.802089 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.845139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.852073 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.895127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.902081 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.945113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 239.952101 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 239.955111 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 239.996000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.002084 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.006001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 240.006003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.014086 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 240.024220 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 240.024223 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.045123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.052097 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.095106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.102088 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.145098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.152090 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.195110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.202063 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.205153 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 240.246006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.252087 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.256049 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 240.256051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.264093 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 240.274192 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 240.274195 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.295105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.302067 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.345121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.352087 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.395118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.402116 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.445140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.452074 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.455105 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 240.495115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.502076 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.506081 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 240.506083 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.514096 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 240.524175 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 240.524177 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.545110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.552076 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.595089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.602090 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.645112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.652060 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.695103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.702052 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.705084 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 240.745995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.752115 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.755988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 240.755989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.764093 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 240.774183 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 240.774186 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 240.795143 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.802117 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.846004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.852077 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.895100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.902058 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.945128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 240.952079 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 240.955112 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 240.995096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.002090 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.006019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 241.006020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.014078 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 241.024184 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 241.024187 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.045123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.052098 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.095121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.102080 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.146009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.152080 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.195139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.202072 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.205074 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 241.245099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.252103 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.256036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 241.256038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.264111 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 241.274191 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 241.274194 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.295126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.302065 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.345127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.352105 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.395103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.402048 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.445101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.452087 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.455080 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 241.495089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.502052 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.506022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 241.506029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.514102 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 241.524177 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 241.524180 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.545108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.552065 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.595118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.602094 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.645117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.652077 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.695118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.702096 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.705090 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 241.745101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.752053 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.755990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 241.755992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.764055 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 241.774193 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 241.774198 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 241.795086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.802082 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.845105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.852041 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.895126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.902078 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.945111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 241.952051 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 241.955061 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 241.995104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.002054 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.005992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 242.005994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.014059 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 242.024200 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 242.024202 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.045108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.052058 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.095122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.102105 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.145114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.152066 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.196000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.202084 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.205077 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 242.245107 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.252098 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.256014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 242.256016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.264122 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 242.274152 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 242.274155 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.295087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.302079 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.345115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.352058 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.395128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.402072 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.445098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.452046 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.455085 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 242.495100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.502018 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.506025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 242.506026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.514077 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 242.524164 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 242.524167 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.545112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.552081 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.595099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.602052 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.645097 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.652033 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.695084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.702047 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.705051 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 242.745142 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.752044 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.756025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 242.756027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.764052 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 242.774160 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 242.774162 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 242.795987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.802048 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.845116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.852016 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.895122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.902044 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.945072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 242.952026 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 242.955076 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 242.995094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.002066 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 243.005990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.014075 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 243.024166 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 243.024169 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.045079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.052034 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.095118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.102070 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.145086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.152050 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.195056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.202030 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.205074 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 243.245079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.252036 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.255995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 243.255997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.264057 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 243.274171 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 243.274173 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.295082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.302031 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.345073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.352040 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.395090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.402030 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.445101 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.452037 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.455074 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 243.495105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.502027 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.505991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 243.505992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.514057 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 243.524156 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 243.524159 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.545079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.552005 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.595079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.602034 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.645080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.652050 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.695065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.702049 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.705047 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 243.745100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.752060 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.756002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 243.756003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.764072 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 243.774138 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 243.774141 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 243.795070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.802020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.845040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.852033 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.895136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.902054 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.945054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 243.952039 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 243.955060 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 243.995066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.002044 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.005134 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 244.005136 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.014062 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 244.024166 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 244.024168 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.045073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.052050 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.095094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.102000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.145096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.152018 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.195069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.202042 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.205086 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 244.245067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.252019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.256012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 244.256014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.264037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 244.274170 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 244.274173 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.295061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.302049 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.345060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.352026 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.395073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.402031 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.445080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.452027 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.455035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 244.495057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.502060 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.506024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 244.506026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.514056 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 244.524145 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 244.524148 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.545063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.552026 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.595094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.602043 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.645070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.652047 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.695112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.702013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.705014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 244.745067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.752059 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.755119 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 244.755120 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.764052 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 244.774157 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 244.774160 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 244.795081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.802040 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.845114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.852055 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.895065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.902012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.945056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 244.952018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 244.955051 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 244.995063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.001997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.006025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 245.006027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.014041 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 245.024127 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 245.024130 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.045051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.052020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.095080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.102005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.145055 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.152019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.195065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.202046 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.205020 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 245.245079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.252062 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.256010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 245.256012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.264001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 245.274109 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 245.274112 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.295082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.301989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.345053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.352008 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.395079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.402020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.445057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.452029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.455028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 245.495064 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.502038 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.505107 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 245.505108 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.514049 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 245.524127 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 245.524130 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.545060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.552044 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.595039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.602012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.645063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.652047 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.695074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.701996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.705049 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 245.745067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.752005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.755112 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 245.755113 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.764040 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 245.774096 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 245.774098 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 245.795058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.802013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.845078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.852048 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.895080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.902023 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.945028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 245.952032 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 245.955016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 245.995052 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.002015 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.005114 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 246.005115 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.014022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 246.024096 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 246.024098 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.045057 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.052041 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.095039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.102046 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.145054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.152034 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.195035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.202028 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.205015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 246.245032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.252035 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.255110 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 246.255111 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.264062 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 246.274103 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 246.274105 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.295075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.302015 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.345035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.352012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.395062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.401988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.445044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.451992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.455010 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 246.495055 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.502002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.505106 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 246.505107 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.514037 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 246.524115 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 246.524117 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.545038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.551988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.595046 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.601986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.645033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.652006 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.695067 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.702003 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.705051 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 246.745015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.752008 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.755088 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 246.755089 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.764048 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 246.774125 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 246.774128 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 246.795030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.801995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.845070 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.852000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.895066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.902006 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.945021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 246.952021 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 246.955029 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 246.995060 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.002029 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.005110 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 247.005111 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.014045 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 247.024125 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 247.024128 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.045025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.052024 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.095054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.102017 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.145043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.152005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.195022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.202005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.205019 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 247.245027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.252002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.255120 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 247.255121 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.263999 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 247.274112 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 247.274114 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.295029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.302019 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.345056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.351996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.395030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.401997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.445069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.451989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.455004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 247.495031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.502018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.505114 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 247.505115 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.514029 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 247.524122 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 247.524124 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.545076 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.552007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.595043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.602012 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.645037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.652001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.695036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.702023 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.705006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 247.745033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.751990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.755117 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 247.755119 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.764028 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 247.774112 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 247.774114 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 247.795018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.802022 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.845031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.852021 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.894994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.902007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.945003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 247.952015 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 247.955023 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 247.995016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.001998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.006060 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 248.006062 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.014006 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 248.024077 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 248.024080 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.045008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.051990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.095030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.102048 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.145048 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.152013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.195087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.202001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.205014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 248.245053 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.252002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.255110 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 248.255111 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.264002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 248.274103 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 248.274105 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.295036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.302003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.344991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.352015 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.395035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.401992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.445038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.452002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.454958 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 248.495011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.502046 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.505109 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 248.505111 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.514019 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 248.524120 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 248.524122 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.545023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.551999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.594999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.601992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.645028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.652008 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.695006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.702011 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.704972 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 248.745038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.752012 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.755070 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 248.755071 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.764017 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 248.774103 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 248.774106 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 248.794994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.802007 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.844996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.852018 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.895008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.902019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.945063 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 248.952001 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 248.954988 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 248.995012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.001990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.005078 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 249.005079 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.014009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 249.024070 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 249.024073 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.045002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.051989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.094999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.101999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.145021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.152003 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.195013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.202002 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.204983 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 249.245028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.251990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.255109 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 249.255110 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.264030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 249.274077 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 249.274080 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.295009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.302023 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.345020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.351999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.394998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.401993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.445008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.451993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.454990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 249.495033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.501990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.505073 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 249.505074 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.514029 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 249.524057 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 249.524061 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.545020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.551997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.595008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.602004 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.645050 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.652002 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.694973 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.702034 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.705006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 249.745032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.752000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.755050 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 249.755051 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.764007 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 249.774042 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 249.774045 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 249.794988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.801990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.844977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.851992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.895010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.901995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.944984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 249.951991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 249.954958 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 249.995001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.001997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.005077 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 250.005078 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.014005 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 250.024051 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 250.024054 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.045014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.051991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.095016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.101994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.145013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.151994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.195006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.202018 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.205005 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 250.245001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.252008 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.255042 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 250.255044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.264023 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 250.274024 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 250.274027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.294979 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.302031 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.344973 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.351990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.394962 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.401988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.445010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.451998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.454980 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 250.494986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.502000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.505031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 250.505033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.514023 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 250.524068 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 250.524071 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.545051 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.551998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.594977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.601987 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.645014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.651996 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.694972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.701986 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.704968 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 250.744975 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.751998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.755053 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 250.755058 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.764006 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 250.774113 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 250.774116 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 250.794968 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.801991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.844981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.852018 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.895006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.901990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.944990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 250.952000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 250.954930 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 250.994990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.001989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.005061 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 251.005062 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.014001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 251.024084 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 251.024086 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.044975 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.052031 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.094961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.101991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.144976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.152000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.195008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.201998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.204951 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 251.244965 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.251997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.255048 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 251.255050 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.264007 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 251.274047 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 251.274049 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.294984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.302019 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.344969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.351998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.394986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.402043 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.444980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.451998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.454952 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 251.495032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.501994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.505047 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 251.505048 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.514007 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 251.524039 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 251.524041 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.544948 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.552006 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.594990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.602004 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.644964 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.651996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.695006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.701995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.704972 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 251.744999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.751992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.755067 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 251.755068 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.764028 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 251.774034 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 251.774036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 251.794980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.801990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.844943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.851998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.894991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.901983 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.944954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 251.951988 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 251.954948 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 251.994954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.001990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.006017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 252.006018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.014008 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 252.024034 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 252.024036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.044963 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.052000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.094985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.102003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.144937 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.151999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.194953 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.201990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.204906 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 252.244972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.251994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.254994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 252.254995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.264003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 252.274048 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 252.274051 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.295001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.301990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.344986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.351990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.394977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.402003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.444928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.451989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.454896 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 252.494958 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.502002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.505057 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 252.505058 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.514003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 252.524029 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 252.524032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.544956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.551995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.594956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.601996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.644975 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.652000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.694948 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.701991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.704922 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 252.744959 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.752000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.755040 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 252.755041 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.764003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 252.774043 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 252.774046 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 252.794928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.802003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.844978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.851992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.894961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.901995 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.944944 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 252.951999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 252.954903 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 252.994974 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.001985 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.005056 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 253.005057 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.014012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 253.024040 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 253.024043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.044943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.051999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.094986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.101998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.144956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.152029 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.194980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.201987 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.204907 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 253.244939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.252005 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.254996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 253.254997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.263998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 253.274026 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 253.274028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.294938 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.301989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.344955 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.351992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.394943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.401991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.444946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.451990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.454882 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 253.494928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.501998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.505013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 253.505014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.514047 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 253.523998 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 253.524000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.544978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.552009 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.594971 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.602002 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.644976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.651990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.694921 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.701992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.704913 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 253.744944 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.752000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.755033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 253.755036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.764006 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 253.774043 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 253.774046 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 253.794973 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.801990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.844961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.852004 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.894926 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.902019 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.944946 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 253.951995 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 253.954912 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 253.994937 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.002003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.004995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 254.004997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.014000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 254.024025 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 254.024027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.044962 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.051994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.094954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.101997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.144914 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.151997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.194936 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.201990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.204936 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 254.244932 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.252001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.254988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 254.254989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.264007 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 254.274018 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 254.274021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.294935 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.302002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.344915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.351999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.394927 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.401993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.444929 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.451991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.454895 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 254.494894 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.502021 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.504971 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 254.504972 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.514010 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 254.524011 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 254.524013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.544931 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.551992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.594943 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.601992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.644928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.651990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.694923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.701989 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.704896 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 254.744930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.752002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.754981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 254.754982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.764033 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 254.773995 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 254.773998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 254.794898 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.801988 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.844923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.851991 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.894939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.902038 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.944961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 254.951993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 254.954887 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 254.994898 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.001994 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.004983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 255.004985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.014010 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 255.024012 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 255.024014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.044915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.051992 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.094894 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.102017 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.144927 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.152019 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.194912 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.201993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.204923 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 255.244921 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.251985 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.254989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 255.254990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.264021 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 255.274009 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 255.274011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.294920 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.302010 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.344954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.352005 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.394945 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.401990 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.444930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.451996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.454905 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 255.494915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.501989 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.504990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 255.504991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.512921 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 255.523999 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 255.524002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.544878 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.551992 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.594903 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.602024 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.644896 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.651991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.694915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.701999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.704858 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 255.744909 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.752036 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.754960 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 255.754962 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.763996 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 255.774011 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 255.774013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 255.794880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.801993 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.844893 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.852034 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.894906 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.901987 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.944899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 255.951998 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 255.954902 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 255.994886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.001993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.005004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 256.005005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.014035 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 256.024032 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 256.024034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.044939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.052001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.094889 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.102040 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.144930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.152009 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.194892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.201996 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.204881 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 256.244901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.252037 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.256033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 256.256035 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.264008 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 256.274006 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 256.274009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.294912 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.302025 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.344886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.352003 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.394974 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.402000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.444900 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.452020 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.454922 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 256.494909 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.502001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.504986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 256.504990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.514024 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 256.524001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 256.524004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.544892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.552002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.594909 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.601999 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.644941 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.652002 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.694910 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.702010 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.704879 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 256.744908 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.751997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.754997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 256.755000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.764039 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 256.774001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 256.774004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 256.794881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.802000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.844949 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.851993 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.894880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.902034 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.944911 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 256.952013 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 256.954909 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 256.994869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.002019 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.005015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 257.005017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.014013 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 257.024002 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 257.024005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.044924 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.051994 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.094912 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.102001 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.144899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.151999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.194874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.201998 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.204872 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 257.244902 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.252024 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.254981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 257.254982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.263998 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 257.274003 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 257.274005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.294872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.302001 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.344902 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.352008 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.394856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.401997 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.444899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.452000 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.454864 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 257.494874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.502012 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.504965 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 257.504967 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.514010 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 257.524001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 257.524004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.544893 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.551990 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.594863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.602017 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.644866 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.651991 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.694855 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.702012 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.704860 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 257.744894 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.752024 1 1812f456x Rx d 8 12 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.754998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 257.755000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.764002 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 257.774037 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 257.774039 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 257.794881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.801997 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.844867 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.851999 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.894864 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.902000 1 1812f456x Rx d 8 08 11 92 0D 36 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.944913 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 257.952002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 257.954923 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 257.994859 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.001986 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.004925 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 258.004926 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.014006 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 258.024001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 258.024004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.044929 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.052018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.094837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.101996 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.144862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.151988 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.194869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.201997 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.204833 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 258.244859 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.252005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.254918 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 258.254920 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.264018 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 258.274007 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 258.274009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.294857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.302032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.344860 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.351986 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.394874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.401994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.444854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.451988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.454835 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 258.494880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.502004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.504956 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 258.504957 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.514002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 258.524018 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 258.524021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.544851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.551991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.594873 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.601996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.644872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.650864 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.694881 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.700874 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.704888 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 258.744863 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.750864 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.754913 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 258.754915 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.763996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 258.774000 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 258.774033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 258.794873 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.800848 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.844845 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.850813 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.894874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.900804 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.944883 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 258.950793 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 258.954858 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 258.994836 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.000806 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.004941 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 259.004942 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.014013 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 259.024003 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 259.024006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.044858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.050782 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.094858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.100795 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.144828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.150795 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.194868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.200833 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.204812 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 259.244888 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.250822 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.254945 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 259.254946 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.264024 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 259.274033 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 259.274038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.294853 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.300794 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.344835 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.350804 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.394859 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.400802 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.444890 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.450772 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.454833 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 259.494842 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.500795 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.504975 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 259.504976 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.513993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 259.524028 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 259.524030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.544824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.550789 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.594837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.600774 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.644845 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.650829 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.694833 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.700798 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.704815 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 259.744821 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.750814 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.754924 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 259.754926 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.763998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 259.774011 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 259.774013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 259.794845 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.800783 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.844877 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.850778 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.894844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.900780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.944802 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 259.950775 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 259.954804 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 259.994850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.000763 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.005995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 260.005997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.014004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 260.024023 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 260.024026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.044830 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.050772 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.094837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.100830 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.144836 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.150787 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.194827 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.200781 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.204792 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 260.244846 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.250843 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.256000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 260.256001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.264002 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 260.274012 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 260.274015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.294869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.300828 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.344851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.350803 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.394823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.400820 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.444839 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.450788 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.454784 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 260.494823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.500772 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.504916 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 260.504924 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.514024 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 260.524021 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 260.524024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.544840 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.550773 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.594848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.600767 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.644838 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.650762 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.694857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.700795 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.704793 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 260.744856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.750781 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.754879 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 260.754881 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.764001 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 260.774040 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 260.774042 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 260.794834 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.800817 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.844824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.850765 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.894828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.900746 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.944798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 260.950776 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 260.954765 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 260.994797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.000816 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.004950 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 261.004952 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.013999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 261.024004 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 261.024007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.044837 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.050790 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.094822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.100780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.144806 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.150765 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.194822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.200743 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.204773 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 261.244826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.250754 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.254871 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 261.254872 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.264004 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 261.274002 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 261.274004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.294816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.300791 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.344806 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.350782 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.394806 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.400776 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.444807 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.450792 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.454777 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 261.494807 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.500784 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.504910 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 261.504911 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.514000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 261.523997 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 261.523999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.544800 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.550755 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.594798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.600750 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.644817 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.650751 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.694812 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.700760 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.704780 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 261.750795 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.755007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 261.755009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.755991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.763992 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 261.774018 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 261.774020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 261.794797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.800750 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.844810 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.850766 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.894794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.900755 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.944821 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 261.950763 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 261.954789 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 261.994768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.000753 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.004866 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 262.004867 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.013999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 262.024026 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 262.024033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.044803 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.050764 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.094775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.100732 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.144807 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.150785 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.194797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.200756 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.204775 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 262.244826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.250793 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.256031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 262.256033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.263992 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 262.274001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 262.274003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.294778 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.300739 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.344809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.350775 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.394812 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.400759 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.444814 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.450738 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.454765 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 262.494811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.500753 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.505990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 262.505991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.513998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 262.524040 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 262.524043 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.544771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.550756 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.594788 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.600739 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.644769 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.650742 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.694801 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.700730 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.704762 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 262.744818 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.750745 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.754863 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 262.754865 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.764003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 262.774020 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 262.774023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 262.794787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.800722 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.844777 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.850713 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.894792 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.900804 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.944800 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 262.950752 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 262.954749 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 263.000764 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.004761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.006017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 263.006018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.014008 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 263.024000 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 263.024002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.044775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.050743 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.100755 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.104747 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.144798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.150747 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.194805 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.200733 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.204761 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 263.244783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.250742 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.254840 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 263.254842 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.256030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.264007 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 263.274001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 263.274003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.294790 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.300723 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.344774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.350756 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.394776 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.400713 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.444805 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.450753 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.454776 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 263.500747 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.504848 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 263.504850 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.506001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.513989 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 263.523987 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 263.523989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.544783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.550753 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.594766 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.600731 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.644809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.650766 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.694782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.700706 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.704736 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 263.744755 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.750754 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.754826 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 263.754830 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.763998 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 263.774020 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 263.774023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 263.794789 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.800771 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.844787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.850739 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.894748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.900726 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.944764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 263.950695 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 263.954740 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 263.994775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.000786 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 264.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.014002 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 264.024023 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 264.024026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.044804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.050717 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.094783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.100729 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.144743 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.150726 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.194771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.200726 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.204744 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 264.244774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.250766 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.254828 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 264.254830 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.263996 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 264.274001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 264.274004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.294759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.300760 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.344770 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.350793 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.394786 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.400738 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.444768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.450748 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.454740 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 264.494750 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.500737 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.505990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 264.505992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.514006 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 264.524005 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 264.524008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.544775 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.550754 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.594779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.600727 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.644774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.650733 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.694764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.700733 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.704724 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 264.744795 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.750796 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.754874 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 264.754875 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.763996 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 264.774033 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 264.774037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 264.800763 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.804752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.844782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.850712 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.894796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.900759 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.944757 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 264.950741 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 264.954754 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 264.994774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.000741 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.006023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 265.006024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.014014 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 265.024004 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 265.024006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.050756 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.054711 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.094741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.100731 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.144754 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.150729 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.194773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.200761 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.204765 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 265.244768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.250768 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.256024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 265.256026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.263994 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 265.273995 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 265.273997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.294756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.300751 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.344732 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.350741 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.394768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.400753 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.444745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.450738 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.454717 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 265.500806 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.504829 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 265.504830 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.505991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.513990 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 265.524045 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 265.524048 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.544768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.550785 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.594745 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.600757 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.650755 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.654735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.694795 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.700760 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.704765 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 265.744753 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.750752 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.756013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 265.756015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.763990 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 265.774001 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 265.774003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 265.800761 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.804722 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.844773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.850738 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.894773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.900780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.944819 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 265.950751 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 265.954743 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 265.994749 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.000734 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.005995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 266.005997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.014002 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 266.024019 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 266.024022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.044752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.050724 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.094769 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.100762 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.144797 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.150758 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.194785 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.200741 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.204788 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 266.250788 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.254789 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 266.254791 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.256033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.263992 1 1ceb56f4x Rx d 8 01 26 11 A2 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 266.273995 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 266.273997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.294794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.300739 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.344791 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.350790 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.394773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.400747 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.444762 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.450770 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.454742 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 266.500677 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.504805 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 266.504807 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.506009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.513997 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 266.524027 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 266.524031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.544773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.550680 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.594758 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.600670 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.644741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.650650 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.694756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.700683 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.704752 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 266.744773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.750685 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.754802 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 266.754803 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.763997 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 266.773997 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 266.776055 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 266.794768 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.800687 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.844754 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.850678 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.900713 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.904748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.944764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 266.950666 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 266.954718 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 266.994766 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.000656 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.006006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 267.006010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.014001 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 267.024027 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 267.024029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.044760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.050686 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.100672 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.104761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.144752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.150657 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.194751 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.200652 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.204735 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 267.244790 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.250659 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.255992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 267.255994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.264008 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 267.274018 1 1ceb56f4x Rx d 8 02 77 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 267.274026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.300682 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.304758 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.344794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.350700 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.394786 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.400637 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.444804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.450657 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.454743 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 267.494799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.500643 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.506016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 267.506018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.514012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 267.524001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 267.524003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.544773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.550665 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.600680 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.604726 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.644780 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.650659 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.694790 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.700682 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.704738 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 267.750683 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.754803 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 267.754804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.756004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.763995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 267.774001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 267.774004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 267.794774 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.800677 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.844697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.850692 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.894693 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.900642 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.944698 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 267.950649 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 267.954670 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 267.994727 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.000661 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 268.005999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.013996 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 268.024001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 268.024004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.050648 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.054660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.094721 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.100652 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.144693 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.150700 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.200705 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.204782 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.204783 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 268.250676 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.254677 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.255988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 268.255990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.264017 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 268.274000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 268.274002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.294687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.300665 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.344683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.350662 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.394682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.400655 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.444730 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.450690 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.454705 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 268.500687 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.504663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.506015 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 268.506016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.514000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 268.524027 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 268.525986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.544664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.550616 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.600690 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.604673 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.650688 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.654656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.700666 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.704796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.704800 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 268.744691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.750664 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.756001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 268.756003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.763992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 268.774006 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 268.774009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 268.800678 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.804679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.844681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.850655 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.900670 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.904657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.944674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.950641 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 268.954759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 268.954761 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 269.000636 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.004657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.006002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 269.006003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.014017 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 269.024005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 269.024008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.044702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.050662 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.100668 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.104629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.144669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.150636 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.194683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.200643 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.204640 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 269.244669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.250670 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.256025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 269.256026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.264012 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 269.274024 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 269.276000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.300655 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.304650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.344690 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.350654 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.400654 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.404670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.444702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.450654 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.454671 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 269.500664 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.504758 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 269.504759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.505991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.513997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 269.524002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 269.524005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.544658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.550620 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.600658 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.604664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.644689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.650657 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.700700 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.704788 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.704789 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 269.744665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.750621 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.756035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 269.756037 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.764000 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 269.773996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 269.775990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 269.794657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.800662 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.850712 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.854619 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.900660 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.904632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.944663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 269.950642 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 269.954698 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 270.000673 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.004647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.005999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 270.006001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.014020 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 270.023990 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 270.025986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.044644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.050683 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.100664 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.104614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.150698 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.154632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.200667 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.204777 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.204779 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 270.250696 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.254617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.256024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 270.256025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.263989 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 270.273996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 270.276028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.300672 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.304628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.344668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.350667 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.394665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.400663 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.450659 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.454760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.454762 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 270.494695 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.500633 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.506007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 270.506010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.513999 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 270.523995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 270.523997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.544658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.550647 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.594668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.600642 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.644692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.650652 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.694660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.700662 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.704718 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 270.750683 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.754774 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 270.754776 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.755995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.764025 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 270.774000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 270.774003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 270.794686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.800666 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.844670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.850665 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.900705 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.904634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.944669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 270.950657 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 270.954684 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 270.994684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.000651 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.006023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 271.006025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.014034 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 271.023992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 271.023994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.050673 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.054670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.094651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.100681 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.144661 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.150669 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.200684 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.204691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.204693 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 271.250676 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.254652 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.256006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 271.256007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.263999 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 271.273998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 271.274000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.294697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.300668 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.350691 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.354699 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.400688 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.404657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.444685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.450670 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.454664 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 271.500630 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.504664 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.505982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 271.505983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.514036 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 271.524005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 271.525994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.544681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.550696 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.600609 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.604624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.650612 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.654680 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.700681 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.704686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.704688 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 271.750660 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.754628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.756010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 271.756011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.763994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 271.774000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 271.776027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 271.800682 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.804636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.844702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.850558 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.894692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.900575 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.950634 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 271.954717 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 271.954718 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 272.000580 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.004668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.005992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 272.005994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.014004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 272.024000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 272.024002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.044692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.050553 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.100610 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.104640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.150607 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.154649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.200598 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.204670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.204672 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 272.250597 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.254674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.256026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 272.256027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.264025 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 272.273994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 272.276012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.300601 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.304648 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.350624 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.354723 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.394687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.400575 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.444655 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.450566 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.454681 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 272.500592 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.504642 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.505993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 272.505994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.513993 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 272.524002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 272.524004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.550596 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.554656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.600570 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.604651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.644665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.650567 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.700616 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.704724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.704725 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 272.750592 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.754653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.755994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 272.756000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.764038 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 272.773997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 272.773999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 272.794583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.800588 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.850598 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.854663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.900585 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.904578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.944617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 272.950589 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 272.954620 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 273.000602 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.004679 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 273.004680 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.006016 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.013995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 273.024008 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 273.024012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.044680 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.050571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.094693 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.100605 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.150578 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.154576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.194574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.200561 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.204585 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 273.244594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.250571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.256005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 273.256008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.264011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 273.274016 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 273.276011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.300604 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.304580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.344595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.350563 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.394577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.400566 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.450580 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.454683 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.454684 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 273.500546 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.504631 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.505998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 273.505999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.514028 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 273.524023 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 273.524026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.544585 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.550561 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.600542 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.604544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.650572 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.654636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.700566 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.704665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.704672 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 273.750559 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.754578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.756012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 273.756017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.764034 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 273.773999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 273.775994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 273.800614 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.804556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.844607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.850558 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.900618 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.904579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.944595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 273.950521 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 273.954574 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 274.000560 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.004583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.006004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 274.006005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.014004 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 274.023995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 274.025992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.050564 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.054561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.100591 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.104558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.150594 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.154571 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.200558 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.204682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.204684 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 274.250561 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.254532 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.256023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 274.256023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.264017 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 274.274035 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 274.276018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.300576 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.304567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.350573 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.354556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.400549 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.404543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.444608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.450546 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.454641 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 274.500571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.504579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.506020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 274.506021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.514024 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 274.524001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 274.524003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.550553 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.554537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.600571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.604566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.650580 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.654528 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.700560 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.704650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.704651 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 274.750559 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.754536 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.755995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 274.755997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.764045 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 274.773998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 274.776022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 274.800571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.804560 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.844617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.850512 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.900521 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.904572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.950519 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 274.954676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 274.954682 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 275.000548 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.004571 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.005982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 275.005983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.014051 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 275.023997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 275.023999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.044568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.050522 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.100601 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.104543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.144590 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.150516 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.200551 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.204657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.204659 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 275.250545 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.254546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.256027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 275.256028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.264025 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 275.274002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 275.276014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.300590 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.304524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.344600 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.350558 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.400557 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.404572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.450545 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.454670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.454671 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 275.500536 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.504559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.506031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 275.506033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.514027 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 275.524033 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 275.526006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.550536 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.554544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.600554 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.604534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.650543 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.654524 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.700529 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.704699 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.704700 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 275.744545 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.750502 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.756074 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 275.756077 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.764007 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 275.774050 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 275.776024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 275.800516 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.804506 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.850571 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.854554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.900545 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.904537 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.950610 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 275.954648 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 275.954650 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 276.000511 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.004518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.006020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 276.006023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.013983 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 276.024000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 276.026033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.044630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.050535 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.100537 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.104528 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.150526 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.154540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.200532 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.204607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.204609 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 276.250499 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.254549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 276.257991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.264001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 276.274000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 276.276033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.300575 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.304523 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.350557 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.354562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.400516 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.404516 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.450499 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.454646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.454647 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 276.500508 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.504525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.505996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 276.505997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.514017 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 276.524007 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 276.526025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.550509 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.554527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.600525 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.604501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.650504 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.654491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.700526 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.704649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.704651 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 276.750537 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.754504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 276.755993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.764019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 276.773998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 276.776002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 276.800530 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.804534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.850508 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.854490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.900508 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.904493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.950513 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 276.954617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 276.954623 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 277.000528 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.004495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.005985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 277.005986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.013993 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 277.024018 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 277.025988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.050516 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.054521 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.100526 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.104513 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.150498 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.154504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.200489 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.204638 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.204639 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 277.250542 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.254482 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.256018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 277.256019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.263989 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 277.274002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 277.276002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.300504 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.304544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.350513 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.354517 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.400531 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.404556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.450500 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.454644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.454649 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 277.500513 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.504519 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.506031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 277.506032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.514022 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 277.523991 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 277.526004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.550490 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.554522 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.600510 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.604511 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.650509 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.654502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.700028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.704601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.704602 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 277.750029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.754504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.756024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 277.756025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.763991 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 277.773993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 277.775998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 277.799994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.804520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.849991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.854472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.899995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.904497 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.950013 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 277.954596 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 277.954598 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 277.999995 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.004502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.005989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 278.007995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.013996 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 278.023995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 278.026003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.044502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.049998 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.099993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.104493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.149985 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.154475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.200029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.204623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.204625 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 278.249995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.254476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.255983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 278.258008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.264019 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 278.274053 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 278.276019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.300018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.304521 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.344510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.350003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.400047 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.404477 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.450003 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.454584 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.454588 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 278.500034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.504542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.505991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 278.505992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.514058 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 278.524004 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 278.526015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.549991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.554502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.599989 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.604464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.650024 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.654534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.700013 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.704587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.704589 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 278.749993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.754509 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.756016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 278.756017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.764039 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 278.773999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 278.775995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 278.800016 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.804497 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.850036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.854500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.900019 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.904490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.950037 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 278.954599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 278.954601 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 279.000038 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.004504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.006027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 279.006028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.013995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 279.024005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 279.025989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.049996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.054483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.099991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.104488 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.149998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.154452 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.199992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.204572 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.204573 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 279.250049 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.254476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.256018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 279.258013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.264014 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 279.274003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 279.274006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.300008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.304504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.350001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.354483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.399996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.404500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.449993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.454559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.454560 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 279.499993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.504467 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.506013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 279.506015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.514010 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 279.523992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 279.525984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.550021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.554489 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.599996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.604446 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.650035 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.654458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.699998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.704547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.704548 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 279.750033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.754470 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.755983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 279.755985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.764064 1 1ceb56f4x Rx d 8 01 17 11 A2 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 279.774001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 279.776076 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 279.800016 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.804506 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.850036 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.854478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.900035 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.904505 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.950038 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 279.954568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 279.954570 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 280.000006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.004469 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 280.007988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.014053 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 280.023990 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 280.026008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.050003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.054429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.099993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.104491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.150012 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.154443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.199998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.204543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.204545 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 280.249997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.254447 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 280.257985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.264007 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 280.274564 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 280.274567 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.299987 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.304458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.350029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.354449 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.400021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.404502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.450016 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.454514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.454515 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 280.500026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.504450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.505995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 280.505996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.514465 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 280.524002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 280.525991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.549992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.554438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.599985 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.604475 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.649999 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.654470 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.699991 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.704525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.704527 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 280.749989 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.754476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.755982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 280.757998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.764010 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 280.773992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 280.776001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 280.799995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.804441 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.850005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.854448 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.900028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.904466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.949998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 280.954528 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 280.954534 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 281.000040 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.004443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.005991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 281.007987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.014009 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 281.024010 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 281.026009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.049998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.054428 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.099993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.104464 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.150004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.154421 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.199995 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.204550 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.204551 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 281.249993 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.254429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.256033 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 281.258015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.263991 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 281.273999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 281.274001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.299997 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.304428 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.349993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.354414 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.400010 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.404435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.449991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.454534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.454535 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 281.500026 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.504490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.505986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 281.507995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.514001 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 281.524000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 281.525986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.549996 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.554438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.599994 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.604440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.650016 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.654434 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.699993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.704523 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.704524 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 281.749988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.754413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.755994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 281.755995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.764018 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 281.774567 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 281.774570 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 281.799996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.804422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.849998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.854445 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.899993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.904417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.949994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 281.954527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 281.954529 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 282.000029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.004414 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.006030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 282.008020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.014435 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 282.023998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 282.025995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.049996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.054413 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.100002 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.104403 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.150003 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.154450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.199999 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.204506 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.204509 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 282.249995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.254422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.255982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 282.257984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.264007 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 282.273995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 282.276008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.299994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.304463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.349991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.354401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.400021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.404456 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.450008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.454478 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.454480 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 282.499992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.504406 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.505985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 282.505986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.514033 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 282.523997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 282.525987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.549998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.554392 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.599996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.604417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.649994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.654397 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.700011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.704510 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.704512 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 282.749992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.754419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.755996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 282.757991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.764029 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 282.774561 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 282.774563 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 282.799991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.804441 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.849994 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.854414 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.900000 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.904405 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.949994 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 282.954499 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 282.954501 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 282.999998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.004402 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.005996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 283.007987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.014019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 283.023999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 283.026020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.050000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.054374 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.100032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.104377 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.150006 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.154386 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.200026 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.204519 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.204521 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 283.250035 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.254402 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.255992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 283.257990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.264015 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 283.273994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 283.276005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.300001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.304427 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.349998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.354404 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.399996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.404417 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.449993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.454494 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.454496 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 283.500007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.504426 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.506023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 283.506024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.514472 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 283.524039 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 283.525990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.550021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.554420 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.600005 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.604422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.650021 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.654443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.700026 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.704482 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.704483 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 283.750024 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.754401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.756004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 283.757995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.764048 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 283.774507 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 283.774509 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 283.800006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.804403 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.849990 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.854383 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.900014 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.904395 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.949992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 283.954497 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 283.954498 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 284.000045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.004365 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.005998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 284.008021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.014039 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 284.023997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 284.025998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.049998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.054401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.100000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.104369 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.150025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.154410 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.200007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.204493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.204500 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 284.249998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.254401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 284.258007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.263991 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 284.274496 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 284.274499 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.299997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.304418 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.349995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.354366 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.400013 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.404440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.450001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.454451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.454452 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 284.500005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.504358 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.505987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 284.508017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.513993 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 284.523992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 284.526015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.549998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.554422 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.599994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.604370 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.649997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.654357 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.700008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.704468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.704470 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 284.750036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.754377 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.756017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 284.758023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.764033 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 284.774479 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 284.774482 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 284.799999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.804363 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.849994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.854388 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.899986 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.904386 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.949995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 284.954491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 284.954493 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 285.000045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.004389 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.005994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 285.005996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.014438 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 285.024003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 285.026018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.050000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.054390 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.100025 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.104357 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.150003 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.154355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.199988 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.204474 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.204475 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 285.250001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.254364 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 285.258017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.264039 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 285.273998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 285.276015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.299997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.304337 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.350001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.354352 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.400009 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.404364 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.449994 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.454465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.454466 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 285.500008 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.504361 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.506026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 285.507990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.514008 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 285.524011 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 285.525987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.549997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.554344 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.600024 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.604354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.650029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.654360 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.700025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.704440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.704441 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 285.749989 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.754350 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.756001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 285.757987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.764005 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 285.774465 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 285.774468 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 285.800003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.804362 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.850009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.854358 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.899995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.904347 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.950040 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 285.954436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 285.954438 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 286.000039 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.004358 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 286.007979 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.014391 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 286.023996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 286.026000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.050015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.054373 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.100002 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.104382 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.150008 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.154374 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.200012 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.204423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.204424 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 286.249993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.254344 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.256027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 286.257985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.264052 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 286.274452 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 286.274455 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.300005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.304333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.350011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.354373 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.400002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.404336 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.449996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.454425 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.454426 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 286.500014 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.504370 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.505984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 286.508032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.514375 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 286.524001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 286.525984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.550001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.554348 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.599993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.604343 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.650001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.654354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.700004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.704445 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.704446 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 286.750011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.754354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.756010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 286.758021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.764054 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 286.774455 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 286.774458 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 286.799999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.804315 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.850003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.854333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.899995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.904346 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.950032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 286.954412 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 286.954413 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 286.999997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.004340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 287.007988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.014000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 287.024000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 287.026014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.050003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.054321 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.099998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.104326 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.150037 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.154333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.200022 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.204421 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.204423 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 287.249992 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.254321 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.256026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 287.257985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.263996 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 287.273998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 287.276009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.299994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.304312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.349993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.354341 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.399995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.404316 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.449995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.454405 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.454406 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 287.500037 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.504312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.506036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 287.508018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.514038 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 287.524005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 287.526027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.550000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.554306 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.599992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.604312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.650034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.654333 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.699992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.704430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.704431 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 287.749999 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.754339 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.755986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 287.758015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.764006 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 287.774433 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 287.774436 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 287.799995 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.804318 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.849996 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.854332 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.900001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.904322 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.949999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 287.954410 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 287.954411 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 288.000002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.004336 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 288.007987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.014342 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 288.024000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 288.025974 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.050015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.054305 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.099995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.104320 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.150004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.154289 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.199995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.204396 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.204397 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 288.250026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.254300 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.256027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 288.257982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.263999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 288.274403 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 288.274405 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.299995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.304313 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.350035 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.354315 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.400000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.404322 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.449999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.454403 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.454404 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 288.500005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.504340 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.505994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 288.507990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.513990 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 288.523993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 288.525985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.549996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.554302 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.599992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.604299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.649998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.654291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.700008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.704397 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.704398 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 288.749998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.754316 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 288.758023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.764348 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 288.772300 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 288.774025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 288.800007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.804283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.850024 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.854285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.900000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.904282 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.950016 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 288.954384 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 288.954388 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 288.999998 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.004285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.006010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 289.007997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.012304 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 289.024004 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 289.026021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.049997 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.054307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.100008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.104283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.149992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.154272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.199998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.204387 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.204393 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 289.249997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.254289 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.255993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 289.257994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.264004 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 289.274416 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 289.274419 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.299992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.304275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.349994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.354270 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.399995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.404276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.449996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.454376 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.454377 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 289.499999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.504323 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.505993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 289.507987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.512259 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 289.523996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 289.523998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.550000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.554287 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.600004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.604291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.650012 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.654389 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.700007 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.704349 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.704350 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 289.750000 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.754262 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.756034 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 289.757987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.764016 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 289.772271 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 289.774018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 289.799997 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.804262 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.849996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.854290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.900000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.904255 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.950042 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 289.954357 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 289.954358 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 289.999997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.004286 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.005986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 290.007983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.012285 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 290.024001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 290.024004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.049998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.054299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.099997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.104282 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.149995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.154299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.200018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.204380 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.204381 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 290.249997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.254303 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.255989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 290.257988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.262251 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 290.272252 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 290.274022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.299998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.304290 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.350004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.354311 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.400026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.404257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.450007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.454368 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.454370 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 290.499997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.504249 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.506000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 290.508003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.512252 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 290.524002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 290.524005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.550000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.554263 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.600014 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.604306 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.650006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.654257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.700011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.704353 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.704354 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 290.750004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.754292 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.755987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 290.757992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.762249 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 290.772270 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 290.774019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 290.800026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.804267 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.849997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.854244 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.899984 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.904276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.950009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 290.954353 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 290.954354 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 290.999993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.004285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.005991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 291.007998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.012261 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 291.023998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 291.024000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.050023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.054250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.099995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.104302 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.150009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.154251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.199999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.204357 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.204358 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 291.250006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.254261 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.255990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 291.258036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.262301 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 291.272299 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 291.273976 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.300014 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.304266 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.350001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.354258 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.400000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.404252 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.449999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.454330 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.454332 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 291.500034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.504299 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.506030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 291.507979 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.512257 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 291.524009 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 291.524012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.549998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.554260 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.599992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.604285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.650025 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.654228 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.699990 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.704323 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.704324 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 291.749998 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.754241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.756018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 291.758015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.762252 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 291.772255 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 291.774010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 291.800011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.804260 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.850018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.854218 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.900001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.904236 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.950028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 291.954355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 291.954356 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 292.000005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.004286 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.006031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 292.007993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.012242 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 292.023998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 292.024001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.049986 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.054247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.099996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.104216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.150028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.154254 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.200009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.204335 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.204340 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 292.250032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.254213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.256026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 292.258024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.262233 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 292.272220 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 292.274021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.299991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.304266 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.349998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.354243 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.400023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.404229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.449996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.454330 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.454332 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 292.499996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.504268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.505982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 292.507995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.512238 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 292.522214 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 292.523989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.549995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.554215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.600036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.604258 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.649998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.654205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.699999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.704309 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.704310 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 292.749996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.754207 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.755988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 292.757985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.762219 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 292.772220 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 292.773988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 292.800012 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.804223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.849999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.854198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.899995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.904216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.950002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 292.954295 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 292.954296 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 293.000006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.004247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.006007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 293.007990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.012260 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 293.023994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 293.023996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.049997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.054217 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.100010 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.104206 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.150004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.154223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.199996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.204291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.204293 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 293.250003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.254218 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.255990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 293.257987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.262186 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 293.272206 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 293.273987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.299993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.304238 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.350030 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.354215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.399996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.404206 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.450001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.454329 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.454331 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 293.500027 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.504223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.505988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 293.507993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.512254 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 293.524002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 293.524005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.549995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.554203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.600021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.604227 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.650001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.654215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.699992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.704293 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.704294 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 293.749995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.754200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.756004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 293.756010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.762260 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 293.772214 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 293.774003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 293.799998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.804229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.850001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.854190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.899997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.904210 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.950021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 293.954307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 293.954309 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 294.000027 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.004197 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.006024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 294.007997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.012226 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 294.022249 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 294.024018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.049989 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.054187 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.100025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.104200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.150003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.154202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.200031 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.204274 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.204276 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 294.249994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.254180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.256027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 294.258005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.262198 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 294.272197 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 294.273984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.299996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.304168 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.350021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.354202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.400023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.404207 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.449995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.454334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.454336 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 294.500005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.504214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.505986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 294.505987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.512156 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 294.522189 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 294.523986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.550020 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.554189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.600046 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.604212 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.649990 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.654193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.699996 1 1812f456x Rx d 8 08 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.704246 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.704247 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 294.749993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.754197 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.756020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 294.758073 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.762202 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 294.772192 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 294.773985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 294.800000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.804154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.849992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.854204 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.899995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.904202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.950022 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 294.954275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 294.954276 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 294.999992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.004177 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.005994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 295.008020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.012181 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 295.022174 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 295.023984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.049987 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.054176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.099996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.104161 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.150032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.154179 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.199999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.204256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.204257 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 295.250033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.254173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.255997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 295.257989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.262146 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 295.272193 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 295.273992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.299990 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.304201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.349998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.354200 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.399999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.404241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.450021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.454262 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.454264 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 295.500004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.504188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.505992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 295.505993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.512180 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 295.522160 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 295.523991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.549998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.554190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.599996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.604193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.649995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.654150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.700016 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.704266 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.704267 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 295.750003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.754146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.756004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 295.757981 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.762155 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 295.772162 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 295.773979 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 295.800048 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.804194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.850002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.854165 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.899998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.904164 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.949999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 295.954287 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 295.954290 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 295.999999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.004146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.005994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 296.008014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.012181 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 296.022183 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 296.024023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.049996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.054191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.100011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.104214 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.150015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.154201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.199991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.204254 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.204256 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 296.249986 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.254125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.255988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 296.257989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.262167 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 296.272157 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 296.273986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.300005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.304136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.350032 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.354206 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.400004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.404147 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.450002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.454228 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.454229 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 296.499988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.504147 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.505989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 296.507998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.512183 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 296.522150 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 296.523997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.549998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.554127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.599994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.604224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.649994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.654146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.699984 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.704236 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.704237 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 296.749991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.754126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.756029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 296.757991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.762180 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 296.772159 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 296.774017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 296.798149 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.804134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.848196 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.854150 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.898185 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.904114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.948156 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 296.954241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 296.954242 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 296.998130 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.004139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.005984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 297.005985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.012139 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 297.022126 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 297.023983 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.048145 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.054174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.098171 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.104154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.148161 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.154140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.198176 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.204215 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.204217 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 297.248157 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.254111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.255990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 297.258010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.262114 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 297.272172 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 297.274007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.298149 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.304148 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.348130 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.354134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.398151 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.404155 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.448145 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.454261 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.454262 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 297.498135 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.504124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.505994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 297.505999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.512120 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 297.522137 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 297.524001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.548123 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.554123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.598122 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.604128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.648144 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.654113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.698148 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.704250 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.704251 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 297.748120 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.754161 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.755998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 297.758018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.762138 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 297.772133 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 297.773994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 297.798156 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.804161 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.848144 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.854120 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.898126 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.904163 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.948159 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 297.954207 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 297.954208 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 297.998127 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.004116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.006038 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 298.007990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.012092 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 298.022148 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 298.023987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.048114 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.054117 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.098139 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.104139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.148130 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.154123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.198122 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.204223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.204224 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 298.248167 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.254168 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.256023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 298.256025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.262117 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 298.272100 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 298.274019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.298128 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.304146 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.348134 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.354098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.398130 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.404132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.448093 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.454221 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.454222 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 298.498115 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.504126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.505984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 298.505985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.512123 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 298.522110 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 298.524009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.548108 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.554121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.598141 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.604131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.648123 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.654135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.698155 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.704205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.704206 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 298.748132 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.754113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.756045 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 298.757995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.762149 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 298.772121 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 298.773987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 298.798096 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.804127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.848094 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.854137 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.898113 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.904131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.948121 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 298.954225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 298.954227 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 298.998124 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.004093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.005986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 299.005987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.012090 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 299.022146 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 299.023989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.048118 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.054102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.098105 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.104103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.148140 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.154118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.198086 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.204223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.204224 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 299.248087 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.254098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.255986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 299.257999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.262088 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 299.272090 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 299.273997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.298121 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.304124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.348091 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.354136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.398106 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.404114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.448133 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.454190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.454197 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 299.498162 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.504108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.505992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 299.507982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.512111 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 299.522092 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 299.523991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.548129 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.554125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.598087 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.604118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.648119 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.654111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.698125 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.704182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.704183 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 299.748088 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.754114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.755984 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 299.755985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.762092 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 299.772081 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 299.773995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 299.798111 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.804124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.848105 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.854099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.898076 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.904071 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.948098 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 299.954175 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 299.954176 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 299.998084 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.004073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.006010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 300.007987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.012109 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 300.022098 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 300.023987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.048075 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.054108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.098098 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.104099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.148112 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.154126 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.198115 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.204177 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.204178 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 300.248066 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.254093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.256013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 300.257984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.262089 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 300.272067 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 300.273992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.298113 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.304124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.348117 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.354079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.398069 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.404114 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.448116 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.454155 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.454157 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 300.498090 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.504068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.505990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 300.505991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.512064 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 300.522119 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 300.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.548054 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.554110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.598062 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.604086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.648084 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.654111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.698093 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.704157 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.704158 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 300.748071 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.754049 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.755993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 300.758004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.762108 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 300.772059 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 300.773988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 300.798067 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.804066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.848104 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.854093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.898076 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.904081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.948037 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 300.954185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 300.954187 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 300.998056 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.004078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.005995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 301.008014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.012056 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 301.024024 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 301.024026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.048042 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.054079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.098054 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.104091 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.148062 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.154061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.198071 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.204185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.204186 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 301.248072 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.254069 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.255990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 301.255991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.262063 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 301.272051 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 301.273988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.298099 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.304090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.348041 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.354058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.398045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.404075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.448034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.454131 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.454140 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 301.498045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.504058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.506005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 301.508036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.512073 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 301.522053 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 301.523989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.548043 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.554035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.598053 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.604058 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.648045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.654059 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.698041 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.704154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.704155 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 301.748062 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.754083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.755994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 301.755995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.762044 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 301.772030 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 301.773989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 301.798052 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.804083 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.848035 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.854073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.898039 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.904037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.948022 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 301.954180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 301.954182 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 301.998041 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.004072 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.006028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 302.006029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.012047 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 302.022040 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 302.023996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.048060 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.054073 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.098066 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.104094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.148022 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.154054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.198025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.204160 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.204162 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 302.248056 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.254026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.256006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 302.256007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.262042 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 302.272040 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 302.273991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.298033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.304040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.348040 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.354061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.398069 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.404044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.448052 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.454153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.454155 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 302.498061 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.504054 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.505995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 302.507981 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.512046 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 302.523996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 302.523998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.548049 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.554034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.598011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.604035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.648030 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.654029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.698042 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.704141 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.704143 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 302.748020 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.754043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.756004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 302.756006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.763080 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 302.772031 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 302.773995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 302.798044 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.804040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.848015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.854034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.898060 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.904027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.948040 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 302.954127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 302.954128 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 302.998009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.004039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.005999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 303.006001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.012056 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 303.022043 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 303.023989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.048052 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.054024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.098046 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.104038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.148015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.154042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.198011 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.204105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.204107 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 303.248071 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.254042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.256018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 303.256020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.262082 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 303.272045 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 303.274005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.298049 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.304062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.348035 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.354021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.398025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.404039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.448024 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.454106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.454107 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 303.498017 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.504022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.505996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 303.506001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.512016 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 303.522034 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 303.523988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.548021 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.554033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.598018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.604021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.648007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.653999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.698036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.704140 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.704148 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 303.747996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.754003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.755987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 303.755988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.762073 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 303.771994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 303.773988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 303.798005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.804002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.848052 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.854031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.898049 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.904039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.948005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 303.954082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 303.954084 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 303.998020 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.004013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 304.005989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.012021 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 304.023112 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 304.023114 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.047996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.054009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.098050 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.104019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.148010 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.154036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.198026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.204108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.204109 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 304.248068 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.254009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.255988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 304.255990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.262000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 304.272021 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 304.274031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.298029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.303999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.348028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.353997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.398053 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.403998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.448025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.454115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.454117 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 304.497987 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.504056 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.506005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 304.506006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.512002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 304.522026 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 304.524020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.548005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.554021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.598006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.603998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.648013 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.654009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.698053 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.704135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.704138 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 304.748004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.754003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.755989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 304.755990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.761989 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 304.771997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 304.773988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 304.798017 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.804026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.848036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.853999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.898027 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.904011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.948023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 304.954136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 304.954140 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 304.998047 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.004011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.005993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 305.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.012030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 305.022013 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 305.023984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.048008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.054004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.097990 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.104002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.148033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.154011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.197997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.204099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.204100 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 305.248002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.253992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.256022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 305.256023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.262002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 305.272019 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 305.273988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.298008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.303992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.348009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.353992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.398003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.404007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.448008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.454077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.454078 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 305.498051 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.504027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.505989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 305.505990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.512021 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 305.523067 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 305.523069 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.547999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.553991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.598036 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.603993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.648000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.653991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.697981 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.704061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.704063 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 305.747999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.753996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.756030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 305.756031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.762007 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 305.771996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 305.774002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 305.797995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.803994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.848002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.854009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.898001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.903994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.948009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 305.954079 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 305.954080 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 305.998020 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.003988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 306.005989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.011999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 306.021988 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 306.023990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.047999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.054009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.097988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.104030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.148001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.154009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.198008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.204061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.204063 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 306.248002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.253986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.256022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 306.256023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.262021 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 306.271994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 306.273996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.297996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.304003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.347999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.353992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.398026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.403992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.448002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.454061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.454063 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 306.498012 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.504021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.506012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 306.506017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.512015 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 306.521998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 306.523988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.547998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.553989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.597995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.604013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.648018 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.654003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.697998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.704115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.704117 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 306.748043 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.754027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.755999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 306.756000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.761999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 306.772069 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 306.773987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 306.798004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.803997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.848004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.853993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.898000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.903999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.947992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 306.954068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 306.954070 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 306.998013 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.003992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.006013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 307.006015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.012022 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 307.023061 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 307.023063 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.047991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.053988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.098010 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.104001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.147995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.153994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.198001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.204042 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.204043 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 307.247993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.253997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.255988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 307.255990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.261993 1 1ceb56f4x Rx d 8 01 1C 11 A2 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 307.272030 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 307.273998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.297991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.303992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.347996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.353990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.398025 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.403999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.448028 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.454030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.454034 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 307.497997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.504002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.505986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 307.505987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.512019 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 307.522000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 307.524021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.548022 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.553991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.597993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.603994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.647992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.653998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.698000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.704043 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.704044 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 307.747996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.753992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.755985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 307.755986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.762002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 307.771998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 307.773985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 307.798002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.803994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.847996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.853991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.898074 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.903993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.948003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 307.954036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 307.954038 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 307.997996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.003992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.006006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 308.006007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.012009 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 308.021999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 308.023991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.048079 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.053987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.097996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.104021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.148046 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.154007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.197996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.204034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.204035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 308.247993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.253986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.256018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 308.256019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.262031 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 308.272033 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 308.274003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.298013 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.303985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.348005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.353990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.398009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.403993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.448045 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.454062 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.454065 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 308.497997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.503990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.505986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 308.505987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.512037 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 308.522010 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 308.524001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.547994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.553989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.598006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.603994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.648008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.653997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.697995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.704041 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.704042 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 308.747996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.754023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.755992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 308.755993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.762008 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 308.771992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 308.773991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 308.798007 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.804030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.847990 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.853999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.898086 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.904001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.947992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 308.954044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 308.954045 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 308.998009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.004006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.006030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 309.006031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.012012 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 309.021995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 309.023989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.047991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.053993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.098033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.103993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.147997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.153996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.198002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.204008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.204009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 309.247995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.253995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.255986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 309.255987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.262009 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 309.271995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 309.273990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.298019 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.303991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.347992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.353987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.398003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.404022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.447999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.453999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.454003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 309.498000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.504000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.505985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 309.505986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.512000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 309.522030 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 309.524073 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.547999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.554000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.598027 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.604000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.648031 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.654038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.697997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.704009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.704011 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 309.747994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.754000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.755985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 309.755986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.761987 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 309.771995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 309.773984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 309.798001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.803999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.847994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.853999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.897995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.904020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.948001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 309.953990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 309.953991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 309.997998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.003993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.006002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 310.006003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.012023 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 310.021996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 310.023995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.047996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.053993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.097994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.104000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.148026 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.153992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.198037 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.204006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.204007 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 310.248002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.253994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.256021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 310.256022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.262020 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 310.272024 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 310.273996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.298017 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.304001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.348015 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.353996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.398033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.403995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.447999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.454005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.454006 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 310.497985 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.503986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.506029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 310.506031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.512008 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 310.521995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 310.523987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.548003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.554003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.597988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.603989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.648005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.654005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.698006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.703992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.703993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 310.747994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.753988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.756001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 310.756002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.762005 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 310.771992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 310.773991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 310.798001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.804034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.848030 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.853995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.897996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.903999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.947996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 310.954006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 310.954007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 310.997996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.003986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.005985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 311.005986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.012036 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 311.022033 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 311.024019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.047996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.053996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.097992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.103992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.148001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.154000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.197991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.203986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.203987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 311.248000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.253987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.256030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 311.256031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.262036 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 311.272020 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 311.274005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.297998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.303990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.347994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.353998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.398041 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.403992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.448034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.453996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.453997 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 311.498004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.504001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.505989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 311.505990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.512003 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 311.522003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 311.523992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.547994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.553992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.597999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.603989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.647993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.653999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.698051 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.704005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.704006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 311.748008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.753988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.755997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 311.755998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.761997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 311.772017 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 311.774019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 311.797997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.803986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.848009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.853996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.898009 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.904013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.947997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 311.953996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 311.953998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 311.997996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.003995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.006007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 312.006008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.012000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 312.021999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 312.023989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.047994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.054020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.098004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.103993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.148029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.154003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.197997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.204021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.204023 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 312.248008 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.253986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.256001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 312.256002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.262008 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 312.271996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 312.273989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.297997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.303994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.347997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.353998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.398033 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.403990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.448002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.453994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.453995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 312.498029 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.503995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.505985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 312.505986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.512022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 312.522036 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 312.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.547999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.554027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.597995 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.603992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.647997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.653995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.697998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.704007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.704008 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 312.748004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.753991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.755988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 312.755990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.762024 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 312.772002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 312.773995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 312.797993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.803986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.847999 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.854040 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.897994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.904008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.947996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 312.954003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 312.954004 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 312.997997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.004008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.005988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 313.005989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.012000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 313.022001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 313.023993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.047993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.053990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.097992 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.103997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.148004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.154000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.197998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.204030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.204032 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 313.248023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.255989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 313.255990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.262009 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 313.272018 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 313.273982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.298000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.303989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.348019 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.353988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.398001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.403994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.448004 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.453987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.453989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 313.497993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.503990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.505993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 313.505994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.512023 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 313.522007 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 313.523989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.547988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.553991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.598003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.603991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.647984 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.653988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.698000 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.703993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.703995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 313.747993 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.753993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 313.755992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.761995 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 313.772014 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 313.773990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 313.797997 1 1812f456x Rx d 8 12 11 93 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.803988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.848003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.853994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.898001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.903987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.947996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 313.953993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 313.953994 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 313.998003 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.003988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.006020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 314.006021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.012002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 314.022001 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 314.023989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.048000 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.053987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.098001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.104002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.148005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.153994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.198005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.203987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.203989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 314.248048 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.253986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 314.255988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.261997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 314.271992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 314.273988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.298006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.303991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.348034 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.354002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.397996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.403993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.447989 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.454028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.454029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 314.497998 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.504006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.506001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 314.506003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.511999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 314.522002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 314.524012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.547990 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.553992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.597994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.603998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.647991 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.653987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.698023 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.703988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.703989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 314.748040 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.753997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.755983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 314.755984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.761994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 314.771993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 314.773981 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 314.798041 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.803989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.848005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.853990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.898006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.903999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.947993 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 314.954019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 314.954023 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 314.997988 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.004016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.005996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 315.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.012002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 315.022026 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 315.023997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.048001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.053994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.097997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.104002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.147996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.153997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.197997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.203997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.203998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 315.248005 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.254021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.255992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 315.255993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.261981 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 315.271994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 315.273991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.298002 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.303982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.348001 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.354003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.397987 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.404006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.448017 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.453991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.453992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 315.498012 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.503995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.505989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 315.505990 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.512026 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 315.521995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 315.523986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.547994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.553989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.597996 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.603993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.647997 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.654004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.697994 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.703992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.703993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 315.748006 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.754011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 315.755992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.761982 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 315.771996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 315.773986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 315.796837 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.803989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.846821 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.853991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.896813 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.903989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.946799 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 315.953993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 315.953994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 315.996820 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.003988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.005987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 316.005988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.012009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 316.022006 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 316.023991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.046805 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.054006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.096794 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.104004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.146830 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.153987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.196791 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.203992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.203993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 316.246774 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.256006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 316.256007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.262024 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 316.271994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 316.273989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.296760 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.304005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.346793 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.353992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.396773 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.403989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.446788 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.453986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.453987 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 316.496760 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.503988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.506002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 316.506004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.512016 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 316.522035 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 316.523995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.546784 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.553986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.596809 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.603997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.646806 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.653993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.696784 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.703997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.704002 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 316.746833 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.753987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.755983 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 316.755984 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.762030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 316.771993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 316.773996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 316.796780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.803990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.846792 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.853992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.896804 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.903993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.946756 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 316.953983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 316.953984 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 316.996797 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.003990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.005997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 317.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.012019 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 317.022013 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 317.024023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.046774 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.053993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.096780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.103991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.146768 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.153987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.196780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.203998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.203999 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 317.246777 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.256008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 317.256009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.261996 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 317.271992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 317.273993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.296784 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.303987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.346792 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.353995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.396739 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.403991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.446769 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.453990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.453991 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 317.496744 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.504025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.506023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 317.506024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.511998 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 317.522010 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 317.523999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.546780 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.553992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.596802 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.603985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.646781 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.653994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.696770 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.703989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.703990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 317.746740 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.753988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.756017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 317.756018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.762051 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 317.771995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 317.773997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 317.796768 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.803996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.846749 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.853995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.896787 1 1812f456x Rx d 8 12 11 92 0D 37 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.903996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.946747 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 317.953996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 317.953997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 317.996743 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.003986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.005994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 318.005995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.012026 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 318.021991 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 318.023985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.046783 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.054002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.096746 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.102742 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.146783 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.153994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.196756 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.202756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.203989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 318.246732 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.253993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.256022 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 318.256024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.262030 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 318.271992 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 318.274021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.296761 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.303993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.346721 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.353992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.396769 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.402732 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.446786 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.453991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.453993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 318.496755 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.502740 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.504793 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 318.504798 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.511998 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 318.521994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 318.523988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.546768 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.553989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.596746 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.603992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.646733 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.653991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.696741 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.702757 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.703979 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 318.746718 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.753993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.755986 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 318.755987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.762005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 318.771995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 318.773993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 318.796737 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.802732 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.846733 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.853987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.896747 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.904000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.946730 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 318.952721 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 318.953986 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 318.996716 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.002700 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.004834 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 319.004835 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.012013 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 319.021996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 319.024002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.046705 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.053991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.096750 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.102710 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.146718 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.153997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.196725 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.203988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.203990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 319.246725 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.255999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 319.256004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.262035 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 319.271994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 319.274006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.296760 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.302725 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.346730 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.353991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.396724 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.402714 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.446714 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.453997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.454001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 319.496707 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.503991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.505992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 319.505995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.512007 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 319.522007 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 319.523993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.546717 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.553982 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.596727 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.602735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.646720 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.652709 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.696742 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.702701 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.703980 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 319.746723 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.752681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.754771 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 319.754772 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.762013 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 319.771995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 319.773988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 319.796733 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.802735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.846705 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.853992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.896721 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.902698 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.946692 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 319.953997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 319.953998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 319.996745 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.002718 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.004826 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 320.004828 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.012013 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 320.022026 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 320.023994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.046689 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.053999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.096711 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.102672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.146724 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.153994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.196720 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.202674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.203987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 320.246704 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.254006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.255991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 320.255993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.262025 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 320.272064 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 320.274031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.296709 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.302682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.346758 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.354013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.396743 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.402754 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.446711 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.454033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.454035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 320.496740 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.502710 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.504799 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 320.504800 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.512009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 320.521997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 320.523999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.546729 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.554006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.596718 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.602708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.646720 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.654006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.696718 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.702693 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.703990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 320.746715 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.754011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.756032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 320.756033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.762005 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 320.771994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 320.773985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 320.796700 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.802681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.846698 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.853998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.896700 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.902687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.946732 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 320.952688 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 320.954033 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 320.996692 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.003994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.006019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 321.006020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.011996 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 321.022029 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 321.023999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.046719 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.054006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.096707 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.102663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.146697 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.153986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.196677 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.202666 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.203978 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 321.246681 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.256021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 321.256022 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.262041 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 321.272004 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 321.273989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.296701 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.302704 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.346684 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.353981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.396719 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.403993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.446677 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.453991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.453992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 321.496675 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.502653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.504746 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 321.504751 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.511995 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 321.522009 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 321.523991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.546712 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.554011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.596705 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.604022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.646708 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.653989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.696707 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.702677 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.704014 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 321.746713 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.752688 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.754766 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 321.754767 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.761994 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 321.771991 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 321.773987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 321.796689 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.802668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.846676 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.853994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.896705 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.902696 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.946671 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 321.953991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 321.953993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 321.996741 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.003991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.005992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 322.005993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.012009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 322.021995 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 322.023991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.046686 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.053991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.096689 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.102645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.146709 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.153984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.196696 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.203999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.204001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 322.246655 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.253994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.255992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 322.255993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.261999 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 322.272041 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 322.272044 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.296687 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.302656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.346666 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.353990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.396664 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.402645 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.446744 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.454006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.454007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 322.496702 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.502649 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.504749 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 322.504750 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.512019 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 322.522009 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 322.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.546716 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.553998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.596682 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.602659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.646681 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.653998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.696678 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.702650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.703989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 322.746704 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.753989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.755991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 322.755992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.761997 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 322.771997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 322.773987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 322.796715 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.802691 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.846698 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.853997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.896665 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.902668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.946698 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 322.954008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 322.954009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 322.996678 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.002661 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.004748 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 323.004749 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.012032 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 323.022019 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 323.024032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.046645 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.053991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.096648 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.102659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.146667 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.153985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.196660 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.202629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.203987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 323.246680 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.253996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.255994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 323.255995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.261999 1 1ceb56f4x Rx d 8 01 35 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 323.271999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 323.273999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.296668 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.302635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.346644 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.353989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.396663 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.402642 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.446655 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.453988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.453989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 323.496665 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.502633 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.504692 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 323.504693 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.512019 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 323.522014 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 323.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.546670 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.553986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.596640 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.602672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.646674 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.653994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.696642 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.702639 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.704003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 323.746640 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.753990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.756000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 323.756001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.761992 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 323.771986 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 323.773982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 323.796683 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.802631 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.846676 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.854038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.896639 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.902624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.946659 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 323.953994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 323.953995 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 323.996623 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.002653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.004630 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 324.006006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.011993 1 1ceb56f4x Rx d 8 01 2B 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 324.022005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 324.024028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.046619 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.052655 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.096638 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.102575 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.146650 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.152597 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.196641 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.202611 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.203992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 324.246641 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.252640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.254686 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 324.254687 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.261992 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 324.271999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 324.273996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.296649 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.302618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.346666 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.352604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.396642 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.402616 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.446656 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.452657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.453990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 324.496623 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.502601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.504683 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 324.504684 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.512002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 324.521994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 324.524037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.546617 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.552610 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.596646 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.602640 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.646644 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.652604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.696646 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.702609 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.703994 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 324.746641 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.752647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.754656 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 324.754657 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.762002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 324.771999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 324.772001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 324.796591 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.802631 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.846649 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.853992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.896653 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.902587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.946622 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 324.952590 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 324.953989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 324.996640 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.002615 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.004683 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 325.004684 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.012010 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 325.021999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 325.024002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.046610 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.052601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.096660 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.102594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.146611 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.152605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.196641 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.202598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.203987 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 325.246654 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.252580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.254692 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 325.254693 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.262009 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 325.271996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 325.273989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.296640 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.302632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.346650 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.354018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.396643 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.402599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.446635 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.452618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.453982 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 325.496610 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.502569 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.504648 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 325.504649 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.512012 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 325.521990 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 325.523995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.546613 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.553995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.596633 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.602614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.646629 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.653990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.696597 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.702588 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.703982 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 325.746663 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.753999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.754000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 325.755991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.761999 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 325.771996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 325.773989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 325.796630 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.802607 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.846602 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.853999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.896649 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.902554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.946588 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 325.952619 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 325.954004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 325.996614 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.002589 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.004675 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 326.004676 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.012009 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 326.022017 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 326.023995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.046600 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.052578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.096600 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.102570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.146598 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.154022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.196596 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.202570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.204008 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 326.246581 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.253990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.255987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 326.255988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.262016 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 326.272006 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 326.274022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.296615 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.302577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.346590 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.352599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.396598 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.403986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.446586 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.453993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.453994 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 326.496613 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.503989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.505999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 326.506000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.512003 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 326.522022 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 326.524014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.546626 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.552577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.596580 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.603991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.646589 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.653988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.696592 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.702566 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.703990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 326.746596 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.754010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.755995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 326.755997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.762011 1 1ceb56f4x Rx d 8 01 30 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 326.772016 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 326.772018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 326.796639 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.803988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.846566 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.854022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.896585 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.904016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.946588 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 326.952533 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 326.953983 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 326.996565 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.003990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.006014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 327.006015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.012015 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 327.022034 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 327.024011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.046584 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.053990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.096579 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.104016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.146569 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.154016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.196586 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.203991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.203993 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 327.246577 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.253995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.253996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 327.255998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.262022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 327.272026 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 327.273995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.296590 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.303993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.346600 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.353994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.396589 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.403996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.446579 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.453987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.453988 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 327.496611 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.503997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.505991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 327.505992 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.512020 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 327.522003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 327.524009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.546574 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.553990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.596559 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.603995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.646581 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.654029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.696556 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.703991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.703992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 327.746570 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.752547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.754602 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 327.754603 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.761995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 327.771994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 327.771996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 327.796592 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.803999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.846566 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.853989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.896583 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.904005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.946556 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 327.954005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 327.954006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 327.996560 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.004002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.004004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 328.006056 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.011986 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 328.021994 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 328.024023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.046568 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.053992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.096556 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.103991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.146551 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.152543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.196585 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.204016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.204017 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 328.246563 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.254027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.256026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 328.256027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.262033 1 1ceb56f4x Rx d 8 01 30 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 328.272036 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 328.274006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.296556 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.303996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.346602 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.352536 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.396558 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.404007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.446577 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.453996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.453998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 328.496587 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.504019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.505994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 328.505994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.512013 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 328.522041 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 328.524024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.546554 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.553990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.596544 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.603990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.646585 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.653992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.696582 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.703991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.703992 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 328.746572 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.754009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.754010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 328.756008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.762020 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 328.771993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 328.771995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 328.796528 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.803997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.846564 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.854010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.896528 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.903984 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.946547 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 328.952502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 328.953990 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 328.996553 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.003991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.005990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 329.005991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.012028 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 329.022003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 329.023997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.046571 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.054001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.096553 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.104000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.146569 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.153995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.196539 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.203990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.203992 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 329.246560 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.253988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.255989 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 329.255991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.262005 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 329.271998 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 329.273992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.296540 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.303986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.346539 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.354029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.396530 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.404003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.446540 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.453999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.454000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 329.496589 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.504028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.504029 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 329.505997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.512020 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 329.521991 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 329.524002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.546535 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.554032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.596531 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.603992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.646559 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.653993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.696536 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.703995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.703996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 329.746526 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.753997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.755988 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 329.755989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.762002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 329.772003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 329.772005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 329.796531 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.803991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.846583 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.853992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.896534 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.903991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.946559 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 329.953995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 329.953997 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 329.996564 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.003995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.006017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 330.006018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.011995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 330.022013 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 330.023992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.046548 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.054015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.096559 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.103994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.146526 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.154008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.196534 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.203992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.203994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 330.246531 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.254005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.254014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 330.255991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.262030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 330.272009 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 330.272012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.296516 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.303989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.346521 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.353991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.396529 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.403995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.446520 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.454037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.454039 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 330.496542 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.504024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.505980 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 330.505982 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.512010 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 330.521993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 330.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.546504 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.553994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.596532 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.603993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.646518 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.653988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.696520 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.704011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.704015 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 330.746520 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.753993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.753994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 330.755986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.762025 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 330.772007 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 330.772010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 330.796515 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.803989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.846514 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.853990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.896556 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.904028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.946515 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 330.953987 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 330.953989 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 330.996524 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.003991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.005990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 331.005991 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.012008 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 331.021996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 331.023988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.046495 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.053993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.096511 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.104000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.146525 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.153992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.196522 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.204002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.204003 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 331.246512 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.254028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.254030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 331.255993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.262025 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 331.271997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 331.271999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.296538 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.303991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.346509 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.354044 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.396537 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.404001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.446532 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.454005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.454007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 331.496503 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.503988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.505992 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 331.505993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.512038 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 331.521997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 331.523993 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.546499 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.554001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.596519 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.604037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.646511 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.654015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.696514 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.703989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.703990 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 331.746494 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.754030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.754031 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 331.756030 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.762004 1 1ceb56f4x Rx d 8 01 21 11 A2 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 331.772023 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 331.772026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 331.796499 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.804029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.846549 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.853994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.896505 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.903995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.946517 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 331.954027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 331.954029 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 331.996496 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.004009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.006030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 332.006034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.012000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 332.021997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 332.023990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.046497 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.054021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.096472 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.104016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.146481 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.153996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.196521 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.203991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.203993 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 332.246483 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.254036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.254038 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 332.256027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.261993 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 332.272000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 332.272002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.296473 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.304002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.346499 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.353990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.396497 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.404031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.446498 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.454038 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.454040 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 332.496518 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.504001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.506010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 332.506014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.512000 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 332.521987 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 332.524030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.546478 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.553999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.596480 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.603991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.646481 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.653990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.696519 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.703992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.703994 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 332.746503 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.754002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.754006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 332.755989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.762018 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 332.772017 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 332.772020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 332.796547 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.803991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.846517 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.854000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.896471 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.903999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.946456 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 332.954026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 332.954028 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 332.996454 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.003988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.005996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 333.005998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.012030 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 333.022000 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 333.024017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.046466 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.054001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.096469 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.103991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.146524 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.154037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.196506 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.204000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.204001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 333.246478 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.254000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.254001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 333.255997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.261982 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 333.271993 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 333.271995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.296444 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.303989 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.346462 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.353983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.396485 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.403993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.446482 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.454011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.454013 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 333.496447 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.504009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.505993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 333.505994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.511999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 333.522054 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 333.524025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.546446 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.553991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.596458 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.603995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.646480 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.654005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.696449 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.704024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.704027 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 333.746492 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.753981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.753982 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 333.756014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.762007 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 333.771996 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 333.771998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 333.796490 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.804026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.846481 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.853994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.896478 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.904001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.946460 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 333.954026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 333.954028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 333.996484 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.004039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.004041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 334.006000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.011996 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 334.021990 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 334.023988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.046445 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.054018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.096459 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.103998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.146465 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.153997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.196475 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.203998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.203999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 334.246451 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.254036 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.254038 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 334.255998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.261984 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 334.272018 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 334.272021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.296469 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.303993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.346477 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.354003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.396470 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.403999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.446447 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.453997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.453998 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 334.496468 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.503994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.503996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 334.505985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.512000 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 334.522035 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 334.523990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.546452 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.553993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.596456 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.604039 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.646421 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.654034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.696455 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.704023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.704025 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 334.746471 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.754019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.754021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 334.756044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.762002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 334.772020 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 334.772022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 334.796491 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.803990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.846458 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.854031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.896002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.904005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.946441 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 334.954007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 334.954009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 334.996447 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.003999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.006009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 335.006010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.012029 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 335.022019 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 335.024010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.046461 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.053992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.096013 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.104033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.146004 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.153997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.196031 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.204010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.204012 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 335.245998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.253994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.253996 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 335.256032 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.262017 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 335.272058 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 335.272073 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.296017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.304001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.346001 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.354028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.395998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.404010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.445997 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.454023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.454025 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 335.496004 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.504035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.504039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 335.506033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.512002 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 335.522025 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 335.524037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.546000 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.554010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.596014 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.604003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.645995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.654014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.695998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.704002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.704006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 335.746000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.754018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.754020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 335.756017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.762010 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 335.772011 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 335.772015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 335.796000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.804025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.845993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.854002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.896042 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.904001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.946034 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 335.954029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 335.954035 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 335.996014 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.004030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.006035 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 336.006036 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.011993 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 336.021999 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 336.023999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.045999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.054005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.095996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.104037 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.146000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.154024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.196015 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.204019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.204025 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 336.246031 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.254033 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.254036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 336.256008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.262038 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 336.272003 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 336.272005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.294027 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.296017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.304008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.345997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.354001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.396011 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.404000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.445996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.454014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.454016 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 336.496022 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.504015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.505998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 336.505999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.511995 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 336.522018 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 336.523998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.545996 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.553996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.596053 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.604013 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.646025 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.654035 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.696000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.704003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.704004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 336.745992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.754005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.754007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 336.756026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.761993 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 336.771997 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 336.772000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 336.796008 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.804026 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.846024 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.853985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.893996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.895986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.945999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 336.954006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 336.954007 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 336.996007 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.004024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.004027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 337.006013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.011997 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 337.022022 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 337.023981 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.045998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.054006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.096036 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.104007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.146000 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.154000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.196006 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.203997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.203999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 337.246014 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.253988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.253990 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 337.255995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.262031 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 337.272027 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 337.272028 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.294009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.296008 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.345999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.353996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.396003 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.404004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.446003 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.454007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.454009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 337.496033 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.503998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.504000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 337.505989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.512017 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3D Length = 0 BitCount = 0 ID = 485185268x + 337.522019 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 337.524022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.546001 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.553992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.595998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.604001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.645998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.654022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.695988 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.704007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.704009 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 337.746033 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.754009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.754012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 337.755980 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.761986 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 337.772002 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 337.772004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 337.794006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.795996 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.846009 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.854006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.895986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.904002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.946001 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 337.953998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 337.953999 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 337.996037 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.004034 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.006010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 338.006015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.012068 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 338.022005 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 338.024011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.046009 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.053992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.093997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.096018 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.146002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.154010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.194000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.195998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.204028 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 338.245995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.253993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.253994 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 338.256004 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.262032 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 338.272004 1 1ceb56f4x Rx d 8 02 76 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 338.272006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.296029 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.304019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.345992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.354011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.395997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.403978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.445997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.453990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.453991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 338.495996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.502355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.504453 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 338.504454 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.512029 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 338.522001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 338.523997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.546023 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.554004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.595994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.604001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.645991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.654028 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.694008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.695984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.703996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 338.745991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.752450 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 338.752452 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.754007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.761991 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 338.771996 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 338.773998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 338.794012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.795987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.845998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.854008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.896004 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.904023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.945996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 338.952384 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.954022 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 338.993994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 338.995985 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.004443 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 339.004445 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.012013 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 339.022009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 339.023974 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.046027 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.053998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.094007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.096028 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.146004 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.153991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.196020 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.204019 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.204021 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 339.245999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.254023 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.255998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 339.255999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.261995 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 339.272010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 339.272013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.293999 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.296010 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.346001 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.353993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.394003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.396024 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.445992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.452372 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.454011 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 339.495993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.504024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.506019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 339.506020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.511996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 339.521993 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 339.524032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.546000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.554015 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.593995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.595990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.646051 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.654029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.693998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.696010 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.704001 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 339.745998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.752445 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 339.752447 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.754001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.762006 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 339.772008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 339.772011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 339.795996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.804012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.846018 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.854020 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.893995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.895999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.946039 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 339.954017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 339.954018 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 339.995997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.004006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.005987 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 340.005988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.012025 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 340.022014 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 340.024011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.045997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.052305 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.096002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.104011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.145995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.152314 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.194006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.195989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.202360 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 340.246034 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.252453 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 340.252455 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.253993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.262028 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 340.272033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 340.274010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.294024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.295995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.345998 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.353996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.395998 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.403998 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.446017 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.454009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.454015 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 340.494008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.496019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.504442 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 340.504448 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.512008 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 340.522018 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 340.524015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.546027 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.554014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.593997 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.595998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.645996 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.654025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.696004 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.704003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.704004 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 340.746006 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.754018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.754020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 340.756024 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.762005 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 340.772020 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 340.772024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 340.794005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.796022 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.846002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.854000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.893996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.895987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.946005 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 340.954021 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 340.954026 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 340.996002 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.003995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.006027 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 341.006029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.011997 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 341.022026 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 341.024004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.046030 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.054010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.093996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.095991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.146010 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.153995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.193993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.195988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.204006 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 341.245995 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.252398 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 341.252400 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.254011 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.261999 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 341.272007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 341.272018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.295996 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.304025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.345989 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.354010 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.393996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.395988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.446005 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.453990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.453991 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 341.494009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.495991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.504419 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 341.504421 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.512022 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 341.522000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 341.523984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.545996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.554029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.594018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.596002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.646020 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.654003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.693994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.696020 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.703995 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 341.746011 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.752390 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 341.752392 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.754024 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.761999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 341.772002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 341.773995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 341.794032 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.795997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.846002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.854029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.895999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.902284 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.946017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 341.954017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.954019 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 341.993996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 341.995987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.004403 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 342.004404 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.012014 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 342.022021 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 342.024020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.045994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.052272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.094031 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.095990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.146031 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.154014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.195989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.202281 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.203998 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 342.245984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.252283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.253981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 342.256008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.262018 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 342.271986 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 342.271987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.296025 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.303991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.346001 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.354000 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.393996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.395993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.443995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.445988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.454018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.454020 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 342.495992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.502270 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.504365 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 342.504366 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.512001 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 342.522010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 342.523986 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.546017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.554007 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.593995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.595986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.645298 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.653354 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.693325 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.695244 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.703314 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 342.745299 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.753041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 342.753044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.755017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.761304 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 342.771397 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 342.771399 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 342.795289 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.803009 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.843334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.845275 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.893317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.895258 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.945332 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 342.953005 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.955005 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 342.993293 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 342.995263 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.005016 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 343.005019 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.011294 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 343.021296 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 343.022982 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.043310 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.045255 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.053310 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.093289 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.095253 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.143337 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.145244 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.193346 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.195291 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.203318 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 343.245285 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.253008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 343.253015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.254993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.261317 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 343.271396 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 343.271400 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.293300 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.295290 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.345279 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.353334 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.393289 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.395264 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.443324 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.445300 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.453307 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 343.493295 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.495225 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.505017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 343.505021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.511293 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 343.521300 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 343.522989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.545303 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.553293 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.593313 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.595243 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.643297 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.645256 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.693324 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.695247 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.703318 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 343.745308 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.753005 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 343.753007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.755004 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.761306 1 1ceb56f4x Rx d 8 01 12 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 343.771385 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 343.771388 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 343.793307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.795242 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.845253 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.853312 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.893313 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.895261 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.943327 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.945252 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 343.953291 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 343.993295 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 343.995234 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.005009 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 344.005012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.011297 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 344.021232 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 344.023012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.043268 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.045219 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.093314 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.095241 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.145256 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.153283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.193324 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.195245 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.203340 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 344.243302 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.245233 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.253014 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 344.253017 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.254990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.261242 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 344.271358 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 344.271360 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.293291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.295230 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.343317 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.345270 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.393276 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.395227 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.445249 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.453400 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.453402 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 344.493284 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.495254 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.505007 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 344.505010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.511253 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 344.521258 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 344.522989 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.543307 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.545240 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.593316 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.595226 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.643310 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.645231 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.693355 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.695246 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.703319 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 344.745251 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.753028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 344.753031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.754995 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.761267 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 344.771355 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 344.771358 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 344.793292 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.795230 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.843328 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.845244 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.893259 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.895236 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.943283 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.945226 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 344.953268 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 344.993297 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 344.995210 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.003030 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 345.003033 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.011264 1 1ceb56f4x Rx d 8 01 21 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 345.021225 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 345.022984 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.045311 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.053289 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.093281 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.095243 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.143275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.145209 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.193300 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.195194 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.203271 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 345.243261 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.245240 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.253019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 345.253021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.261267 1 1ceb56f4x Rx d 8 01 26 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 345.271334 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 345.271336 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.293315 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.295206 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.345231 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.353324 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.393291 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.395204 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.443285 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.445234 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.453266 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 345.493260 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.495205 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.504999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 345.505001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.511218 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 345.521258 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 345.522985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.543249 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.545201 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.593275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.595195 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.645252 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.653251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.693281 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.695203 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.703283 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 345.743273 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.745189 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.752991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 345.752993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.761247 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 345.771344 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 345.771347 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 345.793270 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.795203 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.843272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.845227 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.893274 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.895231 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.945229 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 345.953327 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.953329 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 345.993245 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 345.995237 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.005000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 346.005003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.011234 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 346.021251 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 346.023037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.043272 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.045195 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.093229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.095186 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.143256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.145212 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.193248 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.195238 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.203304 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 346.245251 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.253010 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 346.253012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.255001 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.261283 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 346.271313 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 346.271315 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.293224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.295191 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.343256 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.345225 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.393251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.395224 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.443244 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.445218 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.453323 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 346.493262 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.495199 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.504999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 346.505002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.511240 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 346.521223 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 346.522987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.545214 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.553234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.593253 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.595199 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.643248 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.645202 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.693271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.695206 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.703237 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 346.743232 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.745199 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.753037 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 346.753039 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.761223 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 346.771328 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 346.771331 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 346.793257 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.795185 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.843242 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.845164 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.893233 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.895208 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.943247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.945181 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 346.953239 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 346.993227 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 346.995186 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.003018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 347.003020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.011211 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 347.021234 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 347.023026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.043241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.045209 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.093229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.095206 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.143253 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.145154 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.193236 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.195198 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.203262 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 347.243229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.245173 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.253025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 347.253026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.261202 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 347.271307 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 347.271309 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.293217 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.295164 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.343271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.345159 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.393275 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.395215 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.443235 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.445155 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.453229 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 347.493216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.495164 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.505006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 347.505009 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.511242 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 347.521203 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 347.522992 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.543225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.545200 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.593225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.595167 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.643273 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.645157 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.693251 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.695173 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.703207 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 347.745204 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.752998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 347.753000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.755006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.761198 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 347.771277 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 347.771279 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 347.793216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.795178 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.843220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.845146 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.893222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.895175 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.943224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.945169 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 347.953203 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 347.993271 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 347.995183 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.003028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 348.003031 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.011176 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 348.021196 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 348.023006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.043240 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.045151 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.093264 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.095153 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.143206 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.145139 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.193213 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.195180 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.203233 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 348.243229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.245155 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.253000 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 348.253002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.261226 1 1ceb56f4x Rx d 8 01 17 11 98 0D 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 348.271286 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 348.271289 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.293224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.295184 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.343243 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.345165 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.393238 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.395158 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.443198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.445162 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.453223 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 348.493181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.495157 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.503023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 348.503025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.511172 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 348.521158 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 348.522994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.543203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.545149 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.593182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.595143 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.643222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.645154 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.693220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.695177 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.703215 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 348.743226 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.745122 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.752993 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 348.752995 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.761195 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 348.771332 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 348.771335 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 348.793220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.795149 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.843216 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.845169 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.893187 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.895150 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.943230 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.945156 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 348.953180 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 348.993247 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 348.995162 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.005008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 349.005011 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.011166 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 349.021210 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 349.022997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.043198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.045145 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.093241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.095152 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.143181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.145157 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.193203 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.195171 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.203202 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 349.243224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.245165 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.253025 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 349.253027 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.261203 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 349.271251 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 349.271253 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.293193 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.295129 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.343190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.345153 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.393211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.395158 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.443234 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.445126 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.453190 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 349.493174 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.495160 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.502991 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 349.502993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.511181 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 349.521172 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 349.523023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.543189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.545163 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.593205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.595170 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.643201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.645195 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.693198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.695153 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.703205 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 349.743267 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.745133 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.753002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 349.753003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.761215 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 349.771266 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 349.771269 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 349.793182 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.795156 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.843225 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.845145 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.893184 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.895131 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.943186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.945151 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 349.953193 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 349.993163 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 349.995140 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.003024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 350.003026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.011185 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 350.021170 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 350.022988 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.043165 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.045155 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.093185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.095156 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.143196 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.145194 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.193185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.195157 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.203182 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 350.243154 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.245177 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.253001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 350.253003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.261213 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 350.271310 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 350.271312 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.293202 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.295139 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.343231 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.345142 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.393188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.395178 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.443169 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.445156 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.453212 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 350.493198 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.495160 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.503020 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 350.504999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.511178 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 350.521162 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 350.523023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.543209 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.545182 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.593204 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.595158 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.643176 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.645188 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.693191 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.695179 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.703207 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 350.743229 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.745161 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.753001 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 350.753002 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.755016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.761235 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 350.771243 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 350.771246 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 350.793181 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.795205 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.843223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.845143 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.893171 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.895131 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.943240 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.945154 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 350.953170 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 350.993222 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 350.995167 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.003011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 351.003013 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.011218 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 351.021170 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 351.022997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.043201 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.045168 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.093224 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.095168 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.143162 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.145140 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.193211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.195156 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.203254 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 351.243187 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.245167 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.252999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 351.253001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.261218 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 351.271203 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 351.271205 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.293177 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.295141 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.343179 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.345154 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.393210 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.395186 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.443168 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.445167 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.453168 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 351.493205 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.495161 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.502995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 351.502997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.511215 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 351.521173 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 351.523001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.543186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.545212 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.593227 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.595178 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.643189 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.645185 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.693241 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.695148 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.703176 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 351.743190 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.745076 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.753023 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 351.753025 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.761184 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 351.771224 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 351.771225 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 351.793188 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.795116 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.843223 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.845106 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.893211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.895078 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.943211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.945099 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 351.953210 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 351.993185 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 351.995078 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.005018 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 352.005021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.011110 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 352.021119 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 352.022995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.043218 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.045140 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.093220 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.095074 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.143192 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.145107 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.193199 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.195082 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.203212 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 352.243206 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.245107 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.252999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 352.253001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.261112 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 352.271254 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 352.271257 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.293218 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.295083 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.343194 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.345121 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.393197 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.395089 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.443278 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.445110 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.453204 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 352.493187 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.495108 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.503006 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 352.503008 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.511173 1 1ceb56f4x Rx d 8 01 12 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 352.521209 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 352.522985 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.543253 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.545061 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.593173 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.595091 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.643186 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.645129 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.693195 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.695054 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.703197 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 352.743180 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.745083 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.753017 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 352.753020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.761117 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 352.771222 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 352.771224 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 352.793211 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.795091 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.843172 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.845056 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.893235 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.895066 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.943139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.945074 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 352.953181 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 352.993147 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 352.995114 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.002995 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 353.002996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.011113 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 353.021091 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 353.023037 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.043124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.045073 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.093116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.095063 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.143105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.145102 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.193123 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.195056 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.203130 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 353.243153 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.245058 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.252998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 353.253000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.261137 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 353.271211 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 353.271214 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.293134 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.295104 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.343137 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.345074 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.393103 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.395050 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.443111 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.445044 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.453155 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 353.493121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.495065 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.502096 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 353.502993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.511074 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 353.521105 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 353.522999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.543110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.545064 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.593116 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.595047 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.643110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.645056 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.693124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.695095 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.703147 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 353.743141 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.745093 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.753012 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 353.753014 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.761105 1 1ceb56f4x Rx d 8 01 12 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 353.771202 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 353.771204 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 353.793124 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.795061 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.843135 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.845040 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.893100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.895098 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.943098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.945071 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 353.953113 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 353.993132 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 353.995054 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.003028 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 354.003029 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.011057 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 354.021091 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 354.023024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.043113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.045052 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.093122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.095018 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.143106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.144985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.193115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.194992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.203151 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 354.243106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.244991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.253039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 354.253041 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.261071 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 354.271202 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 354.271205 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.293125 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.294988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.343085 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.344997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.393102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.394993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.443097 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.445000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.453100 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 354.493089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.494983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.503003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 354.503005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.511069 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 354.521102 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 354.523005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.543077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.545022 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.593095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.594986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.643104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.645033 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.693076 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.694993 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.703104 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 354.743094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.744998 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.753008 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 354.753010 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.761109 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 354.771158 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 354.771160 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 354.793090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.794983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.843104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.845024 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.893094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.895006 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.942061 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.944040 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 354.953094 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 354.993115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 354.995006 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.003002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 355.003003 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.011088 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 355.021118 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 355.023023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.043110 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.044991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.092090 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.094041 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.143089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.144989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.193088 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.195026 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.203117 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 355.242075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.244083 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.252985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 355.252987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.261103 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 355.271221 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 355.271224 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.293099 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.294992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.343086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.344986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.392074 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.394090 1 1812f456x Rx d 8 08 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.443087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.445020 1 1812f456x Rx d 8 08 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.452142 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 355.493068 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.494988 1 1812f456x Rx d 8 08 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.502081 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 355.503012 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.511092 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 355.521098 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 355.522991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.542095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.544038 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.593084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.594989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.643075 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.645025 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.692094 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.694035 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.703136 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 355.743102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.744990 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.753003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 355.753005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.761087 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 355.771207 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 355.771209 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 355.793097 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.794988 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.843029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.844992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.893086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.894989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.943080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.944991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 355.953102 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 355.992112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 355.994050 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.003011 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 356.003018 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.011108 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 356.021106 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 356.023007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.043127 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.044982 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.093065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.094986 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.143098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.144988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.193095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.194997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.203103 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 356.243092 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.245002 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.253013 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 356.253015 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.261090 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 356.271156 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 356.271159 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.293080 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.295004 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.343104 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.344988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.393082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.394987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.443082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.444993 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.453081 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 356.493089 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.494988 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.502999 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 356.503001 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.511093 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 356.521122 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 356.522994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.543082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.544983 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.593139 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.594994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.643122 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.645020 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.693098 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.694991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.703083 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 356.743078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.745036 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.753004 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 356.753006 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.761039 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 356.771115 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 356.771117 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 356.793105 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.794991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.843081 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.845023 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.893084 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.895012 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.943106 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.945023 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 356.953118 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 356.993093 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 356.994989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.002039 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 357.002986 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.011048 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 357.021142 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 357.023023 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.043066 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.044993 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.093102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.094983 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.143118 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.144987 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.193136 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.194994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.203077 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 357.243112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.244999 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.252128 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 357.252130 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.261026 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 357.271010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 357.273000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.293082 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.295017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.343115 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.344985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.393086 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.394988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.442029 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.444008 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.453093 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 357.493102 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.494992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.502094 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 357.503007 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.511018 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 357.521032 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 357.523008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.543112 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.544990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.593087 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.594988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.643100 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.644988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.693077 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.694992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.703114 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 357.743121 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.744995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.752100 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 357.752102 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.761048 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 357.771119 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 357.771121 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 357.793113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.794986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.843120 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.845009 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.893113 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.894990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.943095 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.944982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 357.953108 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 357.993128 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 357.994984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.002105 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 358.002107 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.011040 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 358.021007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 358.023032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.043022 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.044989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.093096 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.094986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.143012 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.144988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.193065 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.194995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.203087 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 358.243008 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.244991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.252116 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 358.252118 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.261028 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 358.271165 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 358.271167 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.293017 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.295005 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.343108 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.345022 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.393078 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.394986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.443018 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.444987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.454053 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 358.493014 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.494988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.502002 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 358.503113 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.511020 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 358.521037 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 358.522987 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.541994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.544027 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.592003 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.593963 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.641978 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.643953 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.691992 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.693964 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.702002 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 358.741986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.743964 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.752122 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 358.752124 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.761014 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 358.770994 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 358.772991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 358.791994 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.794013 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.841983 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.843945 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.891990 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.893962 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.941976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.943979 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 358.951996 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 358.991972 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 358.993958 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.002136 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 359.002149 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.011053 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 359.021024 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 359.022991 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.041986 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.044000 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.091996 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.093963 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.141988 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.143943 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.192006 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.193960 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.201991 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 359.242030 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.243947 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.253003 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 359.253005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.261009 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 359.271133 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 359.271135 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.291969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.293967 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.342002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.343951 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.391981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.393964 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.441957 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.443973 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.451968 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 359.491985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.493998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.503021 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 359.503023 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.511030 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 359.521010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 359.523030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.541973 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.543993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.591993 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.593969 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.641981 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.643959 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.691959 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.693926 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.701989 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 359.742025 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.743941 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.752149 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 359.752151 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.760999 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 359.771122 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 359.771124 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 359.791970 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.793930 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.842002 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.843921 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.891948 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.893951 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.941969 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.943941 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 359.952052 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 359.991954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 359.993974 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.001985 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 360.002999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.011002 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 360.021000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 360.023025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.041991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.043933 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.092016 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.093979 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.141950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.143954 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.191985 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.193923 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.201969 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 360.241956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.243974 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.252041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 360.252047 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.260989 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 360.271004 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 360.273014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.291939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.293964 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.341953 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.343915 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.391991 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.393956 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.441980 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.443949 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.451941 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 360.491962 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.493913 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.502130 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 360.502136 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.511013 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 360.521009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 360.523000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.541934 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.543915 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.591961 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.593929 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.641976 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.643952 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.691957 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.693982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.702000 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 360.741925 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.743927 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.752065 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 360.752070 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.761014 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 360.771037 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 360.771040 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 360.791939 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.793933 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.841956 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.843927 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.891919 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.893926 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.941977 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.943959 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 360.951950 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 360.991950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 360.993916 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.002056 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 361.002057 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.011014 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 361.021029 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 361.023020 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.041935 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.043926 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.091937 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.093915 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.141954 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.143948 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.191975 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.193914 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.201926 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 361.241928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.243953 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.252024 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 361.252026 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.260992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 361.271023 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 361.271026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.291945 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.293936 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.341974 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.343927 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.391958 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.393912 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.441926 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.443905 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.451913 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 361.491950 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.493914 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.501929 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 361.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.510998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 361.521022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 361.523024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.541938 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.543930 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.591915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.593941 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.641944 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.643979 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.691923 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.693921 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.701960 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 361.741930 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.743933 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.752026 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 361.752028 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.761028 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 361.770996 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 361.773007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 361.791917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.793926 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.841945 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.843887 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.891927 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.893893 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.941912 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.943911 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 361.951913 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 361.991952 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 361.993936 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.002036 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 362.002038 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.011000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 362.021012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 362.023017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.041904 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.043899 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.091937 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.093898 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.141908 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.143911 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.191917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.193946 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.201902 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 362.241916 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.243923 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.252041 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 362.252043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.261033 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 362.271018 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 362.271021 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.291922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.293866 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.341965 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.343918 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.391901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.393918 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.441886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.443909 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.451929 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 362.491899 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.493880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.502040 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 362.502043 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.511008 1 1ceb56f4x Rx d 8 01 1C 11 A2 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 362.521018 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 362.522998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.541901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.543907 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.591902 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.593897 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.641929 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.643877 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.691917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.693899 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.701932 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 362.741920 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.743870 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.752019 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 362.752021 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.761012 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 362.771045 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 362.771047 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 362.791915 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.793891 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.841908 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.843894 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.891906 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.893893 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.941925 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.943889 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 362.951919 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 362.991917 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 362.993871 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.001917 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 363.002988 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.011030 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 363.021006 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 363.023000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.041905 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.043880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.091974 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.093885 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.141905 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.143879 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.191929 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.193923 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.201908 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 363.241911 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.243885 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.251997 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 363.251999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.261001 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 363.270994 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 363.270996 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.291883 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.293907 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.341924 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.343880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.391894 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.393905 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.441892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.443891 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.451904 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 363.491892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.493872 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.501909 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 363.502993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.511025 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 363.521044 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 363.521047 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.541924 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.543898 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.591909 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.593868 1 1812f456x Rx d 8 12 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.641919 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.643881 1 1812f456x Rx d 8 12 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.691928 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.693916 1 1812f456x Rx d 8 12 11 93 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.701928 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 363.741906 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.743880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.751981 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 363.751983 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.761003 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 363.771020 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 363.771022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 363.791872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.793931 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.841894 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.843919 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.891913 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.893928 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.941882 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.943861 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 363.951883 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 363.991924 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 363.993882 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.002032 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 364.002034 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.011007 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 364.021054 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 364.021057 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.041901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.043880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.091874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.093878 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.141878 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.143865 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.191874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.193864 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.201875 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 364.241875 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.243866 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.251971 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 364.251972 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.260990 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 364.271000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 364.271002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.291898 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.293846 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.341876 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.343914 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.391886 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.393838 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.441896 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.443854 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.451912 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 364.491875 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.493877 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.501880 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 364.502996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.510996 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 364.521023 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 364.521025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.541913 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.543849 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.591869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.593872 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.641922 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.643881 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.691888 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.693855 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.701897 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 364.741868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.743849 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.751961 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 364.751963 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.761024 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 364.771003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 364.771005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 364.791872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.793851 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.841883 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.843880 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.891882 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.893882 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.941926 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.943839 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 364.951858 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 364.991871 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 364.993855 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.001998 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 365.002000 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.011003 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 365.021005 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 365.021007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.041874 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.043833 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.091891 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.093838 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.141901 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.143844 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.191848 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.193850 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.201878 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 365.241872 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.243866 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.251956 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 365.251957 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.261006 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 365.271002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 365.271004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.291879 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.293849 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.341864 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.343851 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.391862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.393839 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.441862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.443874 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.451868 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 365.491888 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.493840 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.501955 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 365.501957 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.511028 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 365.521006 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 365.521008 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.541860 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.543836 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.591858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.593827 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.641878 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.643816 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.691864 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.693842 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.701847 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 365.741857 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.743814 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.751942 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 365.751944 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.760997 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 365.771008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 365.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 365.791892 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.793849 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.841883 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.843829 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.891858 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.893831 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.941868 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.943827 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 365.951840 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 365.991880 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 365.993848 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.001862 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 366.003005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.011001 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 366.021030 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 366.021032 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.041856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.043837 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.091869 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.093852 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.141810 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.143851 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.191828 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.193800 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.201890 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 366.241847 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.243820 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.251926 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 366.251928 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.261008 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 366.271032 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 366.271034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.291841 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.293853 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.341861 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.343841 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.391865 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.393820 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.441811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.443845 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.451826 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 366.491856 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.493822 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.501925 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 366.501927 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.511004 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 366.521012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 366.521014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.541844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.543834 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.591831 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.593859 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.641817 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.643813 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.691829 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.693832 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.701836 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 366.741843 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.743803 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.751940 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 366.751944 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.760998 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 366.771003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 366.771005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 366.791854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.793811 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.841854 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.843840 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.891810 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.893806 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.941844 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.943819 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 366.951826 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 366.991824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 366.993818 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.001960 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 367.001966 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.010994 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 367.020997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 367.020999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.041860 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.043818 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.091862 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.093811 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.141851 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.143778 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.191843 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.193841 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.201815 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 367.241845 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.243799 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.251912 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 367.251913 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.261000 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 367.271013 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 367.271016 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.291822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.293815 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.341815 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.343796 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.391847 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.393822 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.441835 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.443808 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.451818 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 367.491843 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.493783 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.501836 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 367.502989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.511019 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 367.520995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 367.520997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.541820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.543804 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.591829 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.593826 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.641832 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.643780 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.691827 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.693874 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.701821 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 367.741811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.743817 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.751944 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 367.751946 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.761010 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 367.771022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 367.771024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 367.791818 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.793805 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.841819 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.843803 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.891822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.893790 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.941822 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.943820 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 367.951813 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 367.991820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 367.993784 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.001939 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 368.001941 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.011005 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 368.021009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 368.021012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.041825 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.043780 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.091816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.093829 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.141825 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.143802 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.191799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.193825 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.201834 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 368.241791 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.243778 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.251881 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 368.251883 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.261000 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 368.271027 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 368.271030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.291826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.293799 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.341821 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.343809 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.391812 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.393805 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.441826 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.443805 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.451825 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 368.491824 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.493786 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.501932 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 368.501934 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.510994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 368.521009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 368.521011 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.541793 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.543812 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.591778 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.593791 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.641815 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.643805 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.691820 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.693819 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.701807 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 368.741801 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.743752 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.751893 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 368.751900 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.761000 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 368.771031 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 368.771034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 368.791799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.793776 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.841816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.843751 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.891836 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.893782 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.941798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.943769 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 368.951800 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 368.991770 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 368.993825 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.001792 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 369.003020 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.011012 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 369.020996 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 369.020998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.041798 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.043779 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.091799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.093767 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.141781 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.143753 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.191818 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.193793 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.201768 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 369.241799 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.243771 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.251854 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 369.251856 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.261040 1 1ceb56f4x Rx d 8 01 17 11 A2 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 369.271000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 369.271003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.291801 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.293742 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.341781 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.343768 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.391760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.393751 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.441802 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.443769 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.451810 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 369.491787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.493773 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.501869 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 369.501871 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.510995 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 369.521007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 369.521010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.541783 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.543765 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.591786 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.593750 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.641802 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.643768 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.691816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.693786 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.701787 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 369.741793 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.743786 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.751901 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 369.751903 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.761028 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 369.771034 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 369.771036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 369.791803 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.793786 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.841776 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.843744 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.891781 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.893776 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.941796 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.943771 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 369.951763 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 369.991809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 369.993747 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.001925 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 370.001927 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.011021 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 370.021025 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 370.021027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.041823 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.043736 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.091779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.093769 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.141804 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.143770 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.191788 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.193761 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.201770 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 370.241770 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.243766 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.251887 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 370.251889 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.260994 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 370.271002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 370.271004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.291758 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.293725 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.341773 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.343744 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.391758 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.393724 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.441758 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.443788 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.451778 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 370.491761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.493750 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.501808 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 370.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.511019 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 370.520998 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 370.521000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.541764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.543759 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.591752 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.593728 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.641760 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.643762 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.691779 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.693781 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.701787 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 370.741794 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.743764 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.751850 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 370.751852 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.761020 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 370.771000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 370.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 370.791763 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.793744 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.841780 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.843743 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.891761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.893751 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.941811 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.943710 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 370.951760 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 370.991751 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 370.993787 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.001878 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 371.001880 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.011027 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 371.021016 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 371.021018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.041776 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.043737 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.091740 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.093750 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.141816 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.143761 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.191772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.193738 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.201739 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 371.241757 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.243724 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.251829 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 371.251831 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.261006 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 371.271031 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 371.271034 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.291770 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.293746 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.341787 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.343752 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.391764 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.393717 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.441742 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.443736 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.451755 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 371.491759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.493739 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.501869 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 371.501871 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.511012 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 371.520991 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 371.520994 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.541747 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.543701 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.591741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.593718 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.641755 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.643730 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.691737 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.693728 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.701818 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 371.741731 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.743727 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.751865 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 371.751867 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.761010 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 371.771015 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 371.771017 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 371.791772 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.793757 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.841809 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.843736 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.891727 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.893765 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.941739 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.943739 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 371.951721 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 371.991729 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 371.993692 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.001827 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 372.001829 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.011022 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 372.021034 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 372.021036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.041755 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.043749 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.091746 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.093743 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.141767 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.143694 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.191728 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.193713 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.201727 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 372.241753 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.243766 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.251832 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 372.251834 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.261007 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 372.270997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 372.270999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.291759 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.293740 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.341729 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.343701 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.391731 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.392982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.441756 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.442985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.451723 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 372.491729 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.492997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.501835 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 372.501841 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.511015 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 372.521003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 372.521005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.541718 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.543006 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.591741 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.592987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.641771 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.642982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.691727 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.692982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.701753 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 372.741739 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.742986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.751819 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 372.751820 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.761029 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 372.771011 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 372.771013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 372.791748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.793019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.841761 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.842988 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.891711 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.892992 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.941742 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.942980 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 372.951708 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 372.991725 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 372.992988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.001795 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 373.001797 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.011000 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 373.020998 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 373.021000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.041757 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.043021 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.091714 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.092985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.141710 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.142995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.191735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.192982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.201700 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 373.241703 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.242982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.251815 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 373.251817 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.261011 1 1ceb56f4x Rx d 8 01 1C 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 373.271000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 373.271002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.291714 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.293017 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.341708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.342989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.391721 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.392982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.441731 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.443010 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.451716 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 373.491696 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.492988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.501783 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 373.501785 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.511003 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 373.521001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 373.521003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.541748 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.542992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.591692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.592987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.641724 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.642977 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.691707 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.692985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.701718 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 373.741720 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.742989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.751827 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 373.751828 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.761046 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 373.771008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 373.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 373.791708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.792992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.841697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.842996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.891700 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.892983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.941723 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.942981 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 373.951716 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 373.991723 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 373.992988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.001817 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 374.001819 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.010996 1 1ceb56f4x Rx d 8 01 17 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 374.020992 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 374.020995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.041747 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.042982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.091696 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.092992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.141723 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.142982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.191710 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.192995 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.201701 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 374.241702 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.242980 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.251796 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 374.251798 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.260999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 374.271024 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 374.271026 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.291697 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.292986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.341719 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.343028 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.391720 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.392982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.441700 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.442988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.451673 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 374.491737 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.492988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.501816 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 374.501818 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.511004 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 374.521008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 374.521010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.541692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.543034 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.591700 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.592987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.641685 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.642994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.691692 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.692986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.701676 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 374.741699 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.742993 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.751796 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 374.751798 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.761037 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 374.770994 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 374.770997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 374.791687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.792987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.841712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.842985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.891669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.892988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.941686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.942983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.951677 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 374.991681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.992985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.001791 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.001797 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.011003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.021033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.023025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.041735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.042982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.091659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.092984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.141706 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.142981 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.191684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.192998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.201675 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.241679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.242992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.251799 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.251801 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.261001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.271012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.271014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.291682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.293003 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.341706 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.342996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.391682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.392983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.441684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.442982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.451686 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.491716 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.492985 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.501676 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.510999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.521017 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.521019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.541705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.542990 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.591674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.592986 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.641689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.643005 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.691672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.692984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.701658 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.741668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.742987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.751827 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.751828 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.760997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.771020 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.771022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.791674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.792994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.841689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.842980 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.891676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.892994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.941705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.942987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.951634 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.991658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.992986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.001774 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.001775 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.010993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.020999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.041665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.042987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.091670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.093025 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.141708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.142988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.191709 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.192994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.201671 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.241676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.242979 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.251786 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.251787 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.261011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.271003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.271005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.291650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.293019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.341682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.342987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.391667 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.393019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.441646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.442983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.451660 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.491736 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.492988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.501814 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.501816 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.510998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.521002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.523014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.541654 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.543016 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.591679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.592987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.641679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.642986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.691663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.692982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.701671 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.741659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.742989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.751736 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.751744 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.761018 1 1ceb56f4x Rx d 8 01 3A 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.770989 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.770990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.791657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.793019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.841681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.842984 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.891671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.892987 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.941651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.942982 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.951639 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.991651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.993000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.001797 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.001799 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.010999 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.021036 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.021038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.041673 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.042983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.091663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.092983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.141662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.142981 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.191660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.193007 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.201636 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.241635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.242986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.251745 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.251746 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.261012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.271021 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.271025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.291653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.292991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.341643 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.342983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.391671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.392988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.441636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.442997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.451647 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.491672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.492986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.501753 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.501755 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.511028 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.521023 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.521025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.541656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.542991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.591681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.592986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.641644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.642990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.691647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.692989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.701640 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.741636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.742983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.751743 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.751744 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.761006 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.771002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.771004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.791624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.793012 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.841623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.842990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.891614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.892984 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.941650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.942981 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.951613 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.991618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.992988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.001771 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.001773 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.011030 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.021016 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.023015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.041626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.042984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.091636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.141637 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.142985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.191620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.192982 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.201633 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.241614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.242984 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.251734 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.251736 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.261039 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.271028 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.271031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.291620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.292992 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.341632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.342991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.391626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.392988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.441628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.442981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.451649 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.491647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.492988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.501666 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.511004 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.521001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.521003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.541632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.543019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.591604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.592983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.641632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.642988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.691613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.692981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.701627 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.741623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.743030 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.751681 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.751683 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.760994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.771003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.771006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.791626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.793019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.841634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.842984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.891636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.892982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.941629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.942978 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.951611 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.991652 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.992999 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.001717 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.001719 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.011002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.021025 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.021033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.041630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.091608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.092981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.141604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.142981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.191586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.192988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.201610 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.241636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.242988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.251712 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.251714 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.261011 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.270995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.270997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.291605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.292997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.341643 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.342983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.391620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.393023 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.441618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.442981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.451618 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.491603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.492982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.501687 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.501689 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.511021 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.520995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.523013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.541603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.542986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.591577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.592986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.641601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.643032 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.691594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.692989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.701579 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.741625 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.742978 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.751707 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.751709 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.761022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.771000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.791602 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.793010 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.841603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.842983 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.891623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.892986 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.941630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.942989 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.951590 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.991598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.992986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.001629 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.002993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.010998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.020998 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.041579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.043000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.091583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.093004 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.141605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.142980 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.191594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.192988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.201582 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.241581 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.242986 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.251690 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.251691 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.261037 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.271012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.271014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.291620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.293021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.341604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.342988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.391570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.393015 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.441620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.451566 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.491611 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.492986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.501690 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.501691 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.511046 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.521002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.521004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.541603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.543017 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.591586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.592990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.641562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.642991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.691598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.692994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.701590 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.741556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.742983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.751697 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.751699 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.760992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.770997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.770999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.791579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.792992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.841555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.842988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.891603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.892989 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.941578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.943040 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.951580 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.991578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.992993 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.001666 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.001667 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.011004 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.021022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.023015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.041576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.091555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.092989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.141582 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.191599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.192982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.201556 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.241617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.242983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.251641 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.251643 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.261030 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.270989 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.270990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.291580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.292987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.341567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.391567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.392997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.441595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.442988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.451576 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.491568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.492988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.501598 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.502989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.511034 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.520993 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.520995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.541555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.542990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.591587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.593021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.641579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.643031 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.691589 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.692984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.701539 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.741561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.742983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.751664 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.751665 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.761009 1 1ceb56f4x Rx d 8 01 30 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.771027 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.771029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.791579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.792993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.841608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.842985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.891553 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.892994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.941580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.942990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.951560 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.991586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.992998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.001648 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.001650 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.011005 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.020999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.041581 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.043020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.091567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.141584 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.143012 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.191543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.193028 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.201541 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.241546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.242979 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.251655 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.251656 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.261018 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.271008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.271010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.291534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.293008 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.341580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.342988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.391559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.392997 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.441539 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.442982 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.451523 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.491565 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.492987 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.501678 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.501680 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.511007 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.520994 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.523024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.541539 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.543021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.591561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.592984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.641556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.642986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.691548 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.692990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.701539 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.741547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.743025 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.751657 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.751659 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.760997 1 1ceb56f4x Rx d 8 01 12 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.771000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.791577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.792987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.841549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.842982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.891544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.893029 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.941558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.942994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.951528 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.991519 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.992987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.001566 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.002997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.011022 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.021021 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.021024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.041574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.042986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.091549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.092983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.141567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.142987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.191555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.192984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.201570 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.241501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.242994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.251630 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.251632 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.261023 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.271016 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.271018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.291592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.292994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.341552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.391550 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.392988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.441571 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.442998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.451524 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.491557 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.492986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.501655 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.501657 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.511006 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.520997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.521000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.541546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.543020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.591540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.592991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.641527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.642985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.691529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.692992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.701495 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.741574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.742987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.751641 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.751643 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.760997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.771007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.791556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.792996 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.841554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.843038 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.891501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.893019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.941491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.942989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.951521 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.991529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.992990 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.001657 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.001659 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.011027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.020995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.020997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.041500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.043000 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.091504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.092991 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.141507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.143039 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.191541 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.192981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.201495 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.241529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.243011 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.251636 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.251637 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.261007 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.271033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.271036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.291518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.293038 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.341520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.391495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.392987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.441529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.442987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.451508 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.491542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.492998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.501513 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.502987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.511014 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.521024 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.521027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.541529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.543000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.591518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.593020 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.641520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.642985 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.691504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.692987 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.701507 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.741507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.742999 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.751597 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.751598 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.761002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.771011 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.771013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.791511 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.792996 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.841515 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.842988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.891489 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.892997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.941495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.942984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.951496 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.991501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.992990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.001640 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.001642 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.010999 1 1ceb56f4x Rx d 8 01 30 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.020997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.020999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.041477 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.091502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.092991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.141514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.142990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.191508 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.192985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.201496 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.241493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.243000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.251609 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.251611 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.261004 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.270999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.271001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.291480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.292987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.341509 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.342991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.391485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.393020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.441483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.442997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.451469 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.491495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.492993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.501587 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.501593 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.511019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.521007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.521009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.541500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.543025 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.591501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.593014 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.641530 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.642989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.691562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.692988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.701470 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.741535 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.743035 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.751597 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.751598 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.760998 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.770997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.770999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.791494 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.792983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.841547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.842981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.891490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.892979 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.941546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.942983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.951512 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.991485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.992984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.001503 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.002999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.011030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.020995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.020997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.041501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.042989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.091488 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.092984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.141504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.191467 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.192988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.201435 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.241495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.242991 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.251544 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.251546 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.261024 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.271004 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.271006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.291525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.293018 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.341472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.342988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.391490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.392984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.441491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.451474 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.491482 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.492987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.501586 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.501588 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.510996 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.521011 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.521013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.541458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.543028 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.591450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.592975 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.641507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.642986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.691498 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.692999 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.701477 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.741476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.743019 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.751604 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.751606 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.761039 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.771001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.791465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.792988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.841508 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.842986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.891468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.892986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.941490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.943033 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.951440 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.991466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.992986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.001558 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.001560 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.010992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.020996 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.020998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.041455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.042997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.091473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.141472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.191466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.193000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.201439 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.241462 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.242984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.251599 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.251601 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.260998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.271002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.271004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.291455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.293012 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.341491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.343009 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.391468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.392992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.441471 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.451436 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.491458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.492985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.501479 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.503005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.511013 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.521022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.521024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.541474 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.543006 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.591468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.593009 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.641480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.642990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.691492 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.692986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.701459 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.741460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.742985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.751580 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.751583 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.760991 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.771007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.791480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.793006 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.841463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.842993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.891430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.892989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.941487 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.942989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.951430 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.991431 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.993003 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 388.001551 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.001552 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.011013 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.021025 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.021027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.041442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.091465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.141440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.191455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.201432 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.241486 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.251511 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.251512 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.261005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.271028 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.271030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.291429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.341450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.391444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.441443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.451440 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.491430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.501538 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.501540 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.511001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.521003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.521005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.541430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.591427 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.641419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.691483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.701435 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.741444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.751527 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.751529 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.761014 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.771009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.771012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.791435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.841457 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.891432 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.941442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.951424 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.991456 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.001451 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.002996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.011003 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.021010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.021012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.041419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.091438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.141443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.191451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.201415 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.241444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.251537 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.251539 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.260996 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.271001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.271003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.291416 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.341423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.391435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.441485 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.441488 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.442985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.451011 1 1ceb56f4x Rx d 8 01 D9 12 D4 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.453010 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.453011 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.461033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.461035 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.491436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.541443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.591434 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.641429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.691439 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.701547 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.701549 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.703043 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.703044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.710992 1 1ceb56f4x Rx d 8 01 D9 12 CE 0E 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.721003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.721007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.741401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.791394 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.841435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.891435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.941436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.951468 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.951470 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.952996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.952998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.961004 1 1ceb56f4x Rx d 8 01 D4 12 50 0F 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.971000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.971002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.991429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 390.201394 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.451445 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.701420 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.952097 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.202037 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.452179 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.702096 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.952105 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.202110 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.452104 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.702103 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.951453 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.201622 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.451409 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.702121 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.951449 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.202089 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.452088 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.702061 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.952032 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 395.201623 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x +End TriggerBlock diff --git a/bem_cut.asc b/bem_cut.asc new file mode 100644 index 0000000..54513fc --- /dev/null +++ b/bem_cut.asc @@ -0,0 +1,962 @@ + + 374.791687 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.792987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.841712 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.842985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.891669 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.892988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.941686 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.942983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 374.951677 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 374.991681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 374.992985 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.001791 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.001797 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.011003 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.021033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.023025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.041735 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.042982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.091659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.092984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.141706 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.142981 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.191684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.192998 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.201675 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.241679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.242992 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.251799 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.251801 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.261001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.271012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.271014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.291682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.293003 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.341706 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.342996 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.391682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.392983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.441684 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.442982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.451686 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.491716 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.492985 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.501676 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.510999 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.521017 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.521019 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.541705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.542990 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.591674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.592986 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.641689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.643005 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.691672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.692984 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.701658 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.741668 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.742987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.751827 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 375.751828 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.760997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 375.771020 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 375.771022 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 375.791674 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.792994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.841689 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.842980 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.891676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.892994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.941705 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.942987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 375.951634 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 375.991658 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 375.992986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.001774 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.001775 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.010993 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.020999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.041665 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.042987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.091670 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.093025 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.141708 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.142988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.191709 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.192994 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.201671 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.241676 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.242979 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.251786 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.251787 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.261011 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.271003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.271005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.291650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.293019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.341682 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.342987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.391667 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.393019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.441646 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.442983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.451660 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.491736 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.492988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.501814 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.501816 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.510998 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.521002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.523014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.541654 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.543016 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.591679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.592987 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.641679 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.642986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.691663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.692982 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.701671 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.741659 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.742989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.751736 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 376.751744 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.761018 1 1ceb56f4x Rx d 8 01 3A 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 376.770989 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 376.770990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 376.791657 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.793019 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.841681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.842984 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.891671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.892987 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.941651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.942982 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 376.951639 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 376.991651 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 376.993000 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.001797 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.001799 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.010999 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.021036 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.021038 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.041673 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.042983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.091663 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.092983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.141662 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.142981 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.191660 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.193007 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.201636 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.241635 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.242986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.251745 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.251746 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.261012 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.271021 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.271025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.291653 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.292991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.341643 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.342983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.391671 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.392988 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.441636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.442997 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.451647 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.491672 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.492986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.501753 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.501755 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.511028 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.521023 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.521025 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.541656 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.542991 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.591681 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.592986 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.641644 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.642990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.691647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.692989 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.701640 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.741636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.742983 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.751743 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 377.751744 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.761006 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 377.771002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 377.771004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 377.791624 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.793012 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.841623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.842990 1 1812f456x Rx d 8 12 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.891614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.892984 1 1812f456x Rx d 8 08 11 92 0D 38 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.941650 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.942981 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 377.951613 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 377.991618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 377.992988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.001771 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.001773 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.011030 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.021016 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.023015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.041626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.042984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.091636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.141637 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.142985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.191620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.192982 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.201633 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.241614 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.242984 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.251734 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.251736 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.261039 1 1ceb56f4x Rx d 8 01 1C 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.271028 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.271031 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.291620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.292992 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.341632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.342991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.391626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.392988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.441628 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.442981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.451649 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.491647 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.492988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.501666 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.502994 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.511004 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.521001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.521003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.541632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.543019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.591604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.592983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.641632 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.642988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.691613 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.692981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.701627 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.741623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.743030 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.751681 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 378.751683 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.760994 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 378.771003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 378.771006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 378.791626 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.793019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.841634 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.842984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.891636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.892982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.941629 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.942978 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 378.951611 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 378.991652 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 378.992999 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.001717 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.001719 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.011002 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.021025 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.021033 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.041630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.091608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.092981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.141604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.142981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.191586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.192988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.201610 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.241636 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.242988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.251712 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.251714 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.261011 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.270995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.270997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.291605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.292997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.341643 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.342983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.391620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.393023 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.441618 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.442981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.451618 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.491603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.492982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.501687 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.501689 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.511021 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.520995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.523013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.541603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.542986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.591577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.592986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.641601 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.643032 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.691594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.692989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.701579 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.741625 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.742978 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.751707 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 379.751709 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.761022 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 379.771000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 379.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 379.791602 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.793010 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.841603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.842983 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.891623 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.892986 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.941630 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.942989 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 379.951590 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 379.991598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 379.992986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.001629 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.002993 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.010998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.020998 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.041579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.043000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.091583 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.093004 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.141605 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.142980 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.191594 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.192988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.201582 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.241581 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.242986 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.251690 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.251691 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.261037 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.271012 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.271014 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.291620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.293021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.341604 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.342988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.391570 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.393015 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.441620 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.451566 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.491611 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.492986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.501690 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.501691 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.511046 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.521002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.521004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.541603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.543017 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.591586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.592990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.641562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.642991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.691598 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.692994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.701590 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.741556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.742983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.751697 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 380.751699 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.760992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 380.770997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 380.770999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 380.791579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.792992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.841555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.842988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.891603 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.892989 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.941578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.943040 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 380.951580 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 380.991578 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 380.992993 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.001666 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.001667 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.011004 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.021022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.023015 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.041576 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.091555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.092989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.141582 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.191599 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.192982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.201556 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.241617 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.242983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.251641 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.251643 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.261030 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.270989 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.270990 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.291580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.292987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.341567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.391567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.392997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.441595 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.442988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.451576 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.491568 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.492988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.501598 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.502989 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.511034 1 1ceb56f4x Rx d 8 01 21 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.520993 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.520995 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.541555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.542990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.591587 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.593021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.641579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.643031 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.691589 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.692984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.701539 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.741561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.742983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.751664 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 381.751665 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.761009 1 1ceb56f4x Rx d 8 01 30 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 381.771027 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 381.771029 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 381.791579 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.792993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.841608 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.842985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.891553 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.892994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.941580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.942990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 381.951560 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 381.991586 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 381.992998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.001648 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.001650 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.011005 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.020999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.021001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.041581 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.043020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.091567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.141584 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.143012 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.191543 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.193028 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.201541 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.241546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.242979 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.251655 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.251656 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.261018 1 1ceb56f4x Rx d 8 01 21 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.271008 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.271010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.291534 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.293008 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.341580 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.342988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.391559 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.392997 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.441539 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.442982 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.451523 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.491565 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.492987 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.501678 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.501680 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.511007 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.520994 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.523024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.541539 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.543021 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.591561 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.592984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.641556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.642986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.691548 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.692990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.701539 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.741547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.743025 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.751657 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 382.751659 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.760997 1 1ceb56f4x Rx d 8 01 12 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 382.771000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 382.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 382.791577 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.792987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.841549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.842982 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.891544 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.893029 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.941558 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.942994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 382.951528 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 382.991519 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 382.992987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.001566 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.002997 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.011022 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.021021 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.021024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.041574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.042986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.091549 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.092983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.141567 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.142987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.191555 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.192984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.201570 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.241501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.242994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.251630 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.251632 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.261023 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.271016 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.271018 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.291592 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.292994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.341552 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.391550 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.392988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.441571 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.442998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.451524 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.491557 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.492986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.501655 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.501657 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.511006 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.520997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.521000 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.541546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.543020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.591540 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.592991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.641527 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.642985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.691529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.692992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.701495 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.741574 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.742987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.751641 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 383.751643 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.760997 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 383.771007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 383.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 383.791556 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.792996 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.841554 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.843038 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.891501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.893019 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.941491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.942989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 383.951521 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 383.991529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 383.992990 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.001657 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.001659 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.011027 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.020995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.020997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.041500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.043000 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.091504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.092991 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.141507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.143039 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.191541 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.192981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.201495 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.241529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.243011 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.251636 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.251637 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.261007 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.271033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.271036 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.291518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.293038 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.341520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.342984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.391495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.392987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.441529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.442987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.451508 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.491542 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.492998 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.501513 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.502987 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.511014 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.521024 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.521027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.541529 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.543000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.591518 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.593020 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.641520 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.642985 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.691504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.692987 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.701507 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.741507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.742999 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.751597 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 384.751598 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.761002 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 384.771011 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 384.771013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 384.791511 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.792996 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.841515 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.842988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.891489 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.892997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.941495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.942984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 384.951496 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 384.991501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 384.992990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.001640 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.001642 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.010999 1 1ceb56f4x Rx d 8 01 30 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.020997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.020999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.041477 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.042994 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.091502 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.092991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.141514 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.142990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.191508 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.192985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.201496 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.241493 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.243000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.251609 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.251611 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.261004 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.270999 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.271001 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.291480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.292987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.341509 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.342991 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.391485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.393020 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.441483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.442997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.451469 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.491495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.492993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.501587 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.501593 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.511019 1 1ceb56f4x Rx d 8 01 17 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.521007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.521009 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.541500 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.543025 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.591501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.593014 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.641530 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.642989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.691562 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.692988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.701470 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.741535 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.743035 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.751597 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 385.751598 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.760998 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 385.770997 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 385.770999 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 385.791494 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.792983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.841547 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.842981 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.891490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.892979 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.941546 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.942983 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 385.951512 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 385.991485 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 385.992984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.001503 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.002999 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.011030 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.020995 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.020997 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.041501 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.042989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.091488 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.092984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.141504 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.191467 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.192988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.201435 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.241495 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.242991 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.251544 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.251546 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.261024 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.271004 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.271006 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.291525 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.293018 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.341472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.342988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.391490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.392984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.441491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.451474 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.491482 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.492987 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.501586 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.501588 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.510996 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.521011 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.521013 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.541458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.543028 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.591450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.592975 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.641507 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.642986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.691498 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.692999 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.701477 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.741476 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.743019 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.751604 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 386.751606 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.761039 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 386.771001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 386.771003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 386.791465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.792988 1 1812f456x Rx d 8 08 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.841508 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.842986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.891468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.892986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.941490 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.943033 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 386.951440 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 386.991466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 386.992986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.001558 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.001560 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.010992 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.020996 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.020998 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.041455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.042997 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.091473 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.092990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.141472 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.142988 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.191466 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.193000 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.201439 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.241462 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.242984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.251599 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.251601 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.260998 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.271002 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.271004 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.291455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.293012 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.341491 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.343009 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.391468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.392992 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.441471 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.442984 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.451436 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.491458 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.492985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.501479 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.503005 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.511013 1 1ceb56f4x Rx d 8 01 26 11 8E 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.521022 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.521024 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.541474 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.543006 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.591468 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.593009 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.641480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.642990 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.691492 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.692986 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.701459 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.741460 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.742985 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.751580 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 387.751583 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.760991 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 387.771007 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 387.771010 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 387.791480 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.793006 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.841463 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.842993 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.891430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.892989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.941487 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.942989 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 387.951430 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 387.991431 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 387.993003 1 1812f456x Rx d 8 12 11 92 0D 39 00 FD FF Length = 0 BitCount = 0 ID = 403895382x + 388.001551 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.001552 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.011013 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.021025 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.021027 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.041442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.091465 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.141440 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.191455 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.201432 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.241486 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.251511 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.251512 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.261005 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.271028 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.271030 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.291429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.341450 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.391444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.441443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.451440 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.491430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.501538 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.501540 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.511001 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.521003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.521005 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.541430 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.591427 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.641419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.691483 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.701435 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.741444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.751527 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 388.751529 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.761014 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 388.771009 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 388.771012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 388.791435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.841457 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.891432 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.941442 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 388.951424 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 388.991456 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.001451 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.002996 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.011003 1 1ceb56f4x Rx d 8 01 26 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.021010 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.021012 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.041419 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.091438 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.141443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.191451 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.201415 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.241444 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.251537 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.251539 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.260996 1 1ceb56f4x Rx d 8 01 2B 11 98 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.271001 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.271003 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.291416 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.341423 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.391435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.441485 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.441488 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.442985 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.451011 1 1ceb56f4x Rx d 8 01 D9 12 D4 0D 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.453010 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.453011 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.461033 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.461035 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.491436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.541443 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.591434 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.641429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.691439 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.701547 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.701549 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.703043 1 181356f4x Rx d 7 38 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.703044 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.710992 1 1ceb56f4x Rx d 8 01 D9 12 CE 0E 83 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.721003 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.721007 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.741401 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.791394 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.841435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.891435 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.941436 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 389.951468 1 1cec56f4x Rx d 8 10 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485250804x + 389.951470 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 389.952996 1 181356f4x Rx d 7 3C 4A 00 46 00 00 D0 Length = 0 BitCount = 0 ID = 403920628x + 389.952998 1 1cecf456x Rx d 8 11 02 01 FF FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.961004 1 1ceb56f4x Rx d 8 01 D4 12 50 0F 82 F1 3E Length = 0 BitCount = 0 ID = 485185268x + 389.971000 1 1ceb56f4x Rx d 8 02 75 00 FF FF FF FF FF Length = 0 BitCount = 0 ID = 485185268x + 389.971002 1 1cecf456x Rx d 8 13 09 00 02 FF 00 11 00 Length = 0 BitCount = 0 ID = 485291094x + 389.991429 1 181056f4x Rx d 5 C0 12 B8 0B 02 Length = 0 BitCount = 0 ID = 403724020x + 390.201394 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.451445 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.701420 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 390.952097 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.202037 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.452179 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.702096 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 391.952105 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.202110 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.452104 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.702103 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 392.951453 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.201622 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.451409 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.702121 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 393.951449 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.202089 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.452088 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.702061 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 394.952032 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x + 395.201623 1 81e56f4x Rx d 4 F0 F0 F1 FC Length = 0 BitCount = 0 ID = 136206068x +End TriggerBlock diff --git a/log.txt b/log.txt new file mode 100644 index 0000000..df4eed3 --- /dev/null +++ b/log.txt @@ -0,0 +1,320 @@ +Startup (type 'help' for command list) +CONN_Initializing +CONN_Available + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE +GBT_DISABLED + +CONN_Preparing + +CONN_Charging +GBT_S3_STARTED +GBT_S31_WAIT_BHM + +GBT_S4_ISOTEST + +GBT_S5_BAT_INFO + +GBT_S6_BAT_STAT +EV info: +GBT_ver V1.10 +Battery type: 6 +Battery capacity: 1525 +Battery voltage: 7090 +Battery vendor: � +Battery SN: 257 +Battery manufacture date: 255.255.1985 +Battery cycles: 255 +Own auto: 255 +EVIN: L6T79ZCE6RP431111 +EV_SW_VER: ���� + +GBT_S7_BMS_WAIT +Battery info: +maxCV 4V +maxCC 0A +totE 108kWh +maxCV 844V +maxT 60C +SOC 94p +Volt. 530V + +GBT_S8_INIT_CHARGER + +GBT_S9_WAIT_BCL + +GBT_S10_CHARGING +CONN_Charging + +2! �(������2)�(k� +!ѡ�Q�)�� +Bš&ee� —��� �+�.$H�Q2 �-���h�� +�(k�%RLGH8Ъ �-ɩ�h, f-��� �+�.$H�Q2 �2! �(�����b Ɣ�H��P5�PQ�)�(k��RLGH8Ъ �-ɩ�h, f-��� �+�.$H�Q2 �2! �(�����B Ɣ�H��P5�PQ�)�(k�%RLGH�P���++���J8Ъ �����h, f-��� �+�.$H�Q2 �2! �(�����B Ɣ�H��P5�PQ�)�� +Bš&ee� ���� �+�2! �(������2)�(k� +!ѡ� +CONN_Available +GBT_DISABLED + +CONN_Preparing + +CONN_Charging +GBT_S3_STARTED +GBT_S31_WAIT_BHM + +GBT_S4_ISOTEST + +GBT_S5_BAT_INFO + +GBT_S6_BAT_STAT +EV info: +GBT_ver V1.10 +Battery type: 6 +Battery capacity: 1525 +Battery voltage: 7090 +Battery vendor: � +Battery SN: 257 +Battery manufacture date: 255.255.1985 +Battery cycles: 255 +Own auto: 255 +EVIN: L6T79ZCE6RP431111 +EV_SW_VER: ���� + +GBT_S7_BMS_WAIT +Battery info: +maxCV 4V +maxCC 0A +totE 108kWh +maxCV 844V +maxT 60C +SOC 98p +Volt. 390V + +GBT_S8_INIT_CHARGER + +GBT_S9_WAIT_BCL + +GBT_S10_CHARGING +CONN_Charging + + +----- + +GBT_DISABLED + +BEM Received, force stopping... +BEM: F0 F0 F1 FC 00 00 0F FF +GBT_COMPLETE +BEM Received, force stopping... +BEM: F0 F0 F1 FC 00 00 3F FF +GBT_COMPLETE +BEM Received, force stopping... +BEM: F0 F0 F1 FC 00 00 01 FF +GBT_COMPLETE +GBT_DISABLED + +CONN_Finishing + +CONN_Available + +----- + + +CONN_Charging +GBT_S3_STARTED +GBT_S31_WAIT_BHM + +GBT_S4_ISOTEST + +GBT_S5_BAT_INFO + +GBT_S6_BAT_STAT +EV info: +GBT_ver V1.10 +Battery type: 6 +Battery capacity: 1525 +Battery voltage: 7090 +Battery vendor: � +Battery SN: 257 +Battery manufacture date: 255.255.1985 +Battery cycles: 255 +Own auto: 255 +EVIN: L6T79ZCE6RP431111 +EV_SW_VER: ���� + +GBT_S7_BMS_WAIT +Battery info: +maxCV 4V +maxCC 0A +totE 108kWh +maxCV 844V +maxT 60C +SOC 98p +Volt. 825V + +GBT_S8_INIT_CHARGER + +GBT_S9_WAIT_BCL + +GBT_S10_CHARGING +CONN_Charging + +CONN_Available +GBT_DISABLED + +CONN_Preparing + +CONN_Charging +GBT_S3_STARTED +GBT_S31_WAIT_BHM + +GBT_S4_ISOTEST + +GBT_S5_BAT_INFO + +GBT_S6_BAT_STAT +EV info: +GBT_ver V1.10 +Battery type: 6 +Battery capacity: 1525 +Battery voltage: 7090 +Battery vendor: � +Battery SN: 257 +Battery manufacture date: 255.255.1985 +Battery cycles: 255 +Own auto: 255 +EVIN: L6T79ZCE6RP431111 +EV_SW_VER: ���� + +BST Received, stopping... +BST: 01 00 00 F0 00 00 0F FF +GBT_STOP +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 7F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 FF FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 00 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 01 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 01 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 03 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 03 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 07 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 07 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 0F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 0F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 1F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 1F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 7F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 7F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 00 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 00 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 01 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 01 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 03 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 03 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 07 FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 0F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 0F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 1F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 1F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 7F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 7F FF +BST Received, stopping... +BST: 01 00 00 F0 00 00 3F FF + +GBT_STOP_CSD + +GBT_COMPLETE +CONN_Suspended_EV + +GBT_DISABLED + +CONN_Finishing + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +BEM Received, force stopping... +BEM: F0 F0 F0 FD FF FF FF FF +GBT_COMPLETE + +CONN_Available +GBT_DISABLED \ No newline at end of file